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TARGET_NUCLEO_F410RB/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:: <>
Date:: Mon Jan 16 12:05:23 2017 +0000
Revision:: 134:ad3be0349dc5
Parent:: 128:9bcdf88f62b0
Child:: 145:64910690c574

Release 134 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/**
Kojto	122:f9eeca106725	2	******************************************************************************
Kojto	122:f9eeca106725	3	* @file stm32f4xx_ll_fmc.h
Kojto	122:f9eeca106725	4	* @author MCD Application Team
Kojto	122:f9eeca106725	5	* @version V1.5.0
Kojto	122:f9eeca106725	6	* @date 06-May-2016
Kojto	122:f9eeca106725	7	* @brief Header file of FMC HAL module.
Kojto	122:f9eeca106725	8	******************************************************************************
Kojto	122:f9eeca106725	9	* @attention
Kojto	122:f9eeca106725	10	*
Kojto	122:f9eeca106725	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto	122:f9eeca106725	12	*
Kojto	122:f9eeca106725	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	122:f9eeca106725	14	* are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	122:f9eeca106725	16	* this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	122:f9eeca106725	18	* this list of conditions and the following disclaimer in the documentation
Kojto	122:f9eeca106725	19	* and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	122:f9eeca106725	21	* may be used to endorse or promote products derived from this software
Kojto	122:f9eeca106725	22	* without specific prior written permission.
Kojto	122:f9eeca106725	23	*
Kojto	122:f9eeca106725	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	122:f9eeca106725	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	122:f9eeca106725	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	122:f9eeca106725	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	122:f9eeca106725	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	122:f9eeca106725	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	122:f9eeca106725	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	122:f9eeca106725	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	34	*
Kojto	122:f9eeca106725	35	******************************************************************************
Kojto	122:f9eeca106725	36	*/
Kojto	122:f9eeca106725	37
Kojto	122:f9eeca106725	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	122:f9eeca106725	39	#ifndef __STM32F4xx_LL_FMC_H
Kojto	122:f9eeca106725	40	#define __STM32F4xx_LL_FMC_H
Kojto	122:f9eeca106725	41
Kojto	122:f9eeca106725	42	#ifdef __cplusplus
Kojto	122:f9eeca106725	43	extern "C" {
Kojto	122:f9eeca106725	44	#endif
Kojto	122:f9eeca106725	45
Kojto	122:f9eeca106725	46	/* Includes ------------------------------------------------------------------*/
Kojto	122:f9eeca106725	47	#include "stm32f4xx_hal_def.h"
Kojto	122:f9eeca106725	48
Kojto	122:f9eeca106725	49	/** @addtogroup STM32F4xx_HAL_Driver
Kojto	122:f9eeca106725	50	* @{
Kojto	122:f9eeca106725	51	*/
Kojto	122:f9eeca106725	52
Kojto	122:f9eeca106725	53	/** @addtogroup FMC_LL
Kojto	122:f9eeca106725	54	* @{
Kojto	122:f9eeca106725	55	*/
Kojto	122:f9eeca106725	56	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	122:f9eeca106725	57	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	58	/* Private types -------------------------------------------------------------*/
Kojto	122:f9eeca106725	59	/** @defgroup FMC_LL_Private_Types FMC Private Types
Kojto	122:f9eeca106725	60	* @{
Kojto	122:f9eeca106725	61	*/
Kojto	122:f9eeca106725	62
Kojto	122:f9eeca106725	63	/**
Kojto	122:f9eeca106725	64	* @brief FMC NORSRAM Configuration Structure definition
Kojto	122:f9eeca106725	65	*/
Kojto	122:f9eeca106725	66	typedef struct
Kojto	122:f9eeca106725	67	{
Kojto	122:f9eeca106725	68	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
Kojto	122:f9eeca106725	69	This parameter can be a value of @ref FMC_NORSRAM_Bank */
Kojto	122:f9eeca106725	70
Kojto	122:f9eeca106725	71	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
Kojto	122:f9eeca106725	72	multiplexed on the data bus or not.
Kojto	122:f9eeca106725	73	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
Kojto	122:f9eeca106725	74
Kojto	122:f9eeca106725	75	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
Kojto	122:f9eeca106725	76	the corresponding memory device.
Kojto	122:f9eeca106725	77	This parameter can be a value of @ref FMC_Memory_Type */
Kojto	122:f9eeca106725	78
Kojto	122:f9eeca106725	79	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto	122:f9eeca106725	80	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
Kojto	122:f9eeca106725	81
Kojto	122:f9eeca106725	82	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
Kojto	122:f9eeca106725	83	valid only with synchronous burst Flash memories.
Kojto	122:f9eeca106725	84	This parameter can be a value of @ref FMC_Burst_Access_Mode */
Kojto	122:f9eeca106725	85
Kojto	122:f9eeca106725	86	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
Kojto	122:f9eeca106725	87	the Flash memory in burst mode.
Kojto	122:f9eeca106725	88	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
Kojto	122:f9eeca106725	89
Kojto	122:f9eeca106725	90	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
Kojto	122:f9eeca106725	91	memory, valid only when accessing Flash memories in burst mode.
Kojto	122:f9eeca106725	92	This parameter can be a value of @ref FMC_Wrap_Mode
Kojto	122:f9eeca106725	93	This mode is not available for the STM32F446/467/479xx devices */
Kojto	122:f9eeca106725	94
Kojto	122:f9eeca106725	95	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
Kojto	122:f9eeca106725	96	clock cycle before the wait state or during the wait state,
Kojto	122:f9eeca106725	97	valid only when accessing memories in burst mode.
Kojto	122:f9eeca106725	98	This parameter can be a value of @ref FMC_Wait_Timing */
Kojto	122:f9eeca106725	99
Kojto	122:f9eeca106725	100	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
Kojto	122:f9eeca106725	101	This parameter can be a value of @ref FMC_Write_Operation */
Kojto	122:f9eeca106725	102
Kojto	122:f9eeca106725	103	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
Kojto	122:f9eeca106725	104	signal, valid for Flash memory access in burst mode.
Kojto	122:f9eeca106725	105	This parameter can be a value of @ref FMC_Wait_Signal */
Kojto	122:f9eeca106725	106
Kojto	122:f9eeca106725	107	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
Kojto	122:f9eeca106725	108	This parameter can be a value of @ref FMC_Extended_Mode */
Kojto	122:f9eeca106725	109
Kojto	122:f9eeca106725	110	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
Kojto	122:f9eeca106725	111	valid only with asynchronous Flash memories.
Kojto	122:f9eeca106725	112	This parameter can be a value of @ref FMC_AsynchronousWait */
Kojto	122:f9eeca106725	113
Kojto	122:f9eeca106725	114	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
Kojto	122:f9eeca106725	115	This parameter can be a value of @ref FMC_Write_Burst */
Kojto	122:f9eeca106725	116
Kojto	122:f9eeca106725	117	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
Kojto	122:f9eeca106725	118	This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto	122:f9eeca106725	119	through FMC_BCR2..4 registers.
Kojto	122:f9eeca106725	120	This parameter can be a value of @ref FMC_Continous_Clock */
Kojto	122:f9eeca106725	121
Kojto	122:f9eeca106725	122	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
Kojto	122:f9eeca106725	123	This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto	122:f9eeca106725	124	through FMC_BCR2..4 registers.
Kojto	122:f9eeca106725	125	This parameter can be a value of @ref FMC_Write_FIFO
Kojto	122:f9eeca106725	126	This mode is available only for the STM32F446/469/479xx devices */
Kojto	122:f9eeca106725	127
Kojto	122:f9eeca106725	128	uint32_t PageSize; /*!< Specifies the memory page size.
Kojto	122:f9eeca106725	129	This parameter can be a value of @ref FMC_Page_Size */
Kojto	122:f9eeca106725	130	}FMC_NORSRAM_InitTypeDef;
Kojto	122:f9eeca106725	131
Kojto	122:f9eeca106725	132	/**
Kojto	122:f9eeca106725	133	* @brief FMC NORSRAM Timing parameters structure definition
Kojto	122:f9eeca106725	134	*/
Kojto	122:f9eeca106725	135	typedef struct
Kojto	122:f9eeca106725	136	{
Kojto	122:f9eeca106725	137	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto	122:f9eeca106725	138	the duration of the address setup time.
Kojto	122:f9eeca106725	139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto	122:f9eeca106725	140	@note This parameter is not used with synchronous NOR Flash memories. */
Kojto	122:f9eeca106725	141
Kojto	122:f9eeca106725	142	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
Kojto	122:f9eeca106725	143	the duration of the address hold time.
Kojto	122:f9eeca106725	144	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
Kojto	122:f9eeca106725	145	@note This parameter is not used with synchronous NOR Flash memories. */
Kojto	122:f9eeca106725	146
Kojto	122:f9eeca106725	147	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto	122:f9eeca106725	148	the duration of the data setup time.
Kojto	122:f9eeca106725	149	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
Kojto	122:f9eeca106725	150	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
Kojto	122:f9eeca106725	151	NOR Flash memories. */
Kojto	122:f9eeca106725	152
Kojto	122:f9eeca106725	153	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
Kojto	122:f9eeca106725	154	the duration of the bus turnaround.
Kojto	122:f9eeca106725	155	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto	122:f9eeca106725	156	@note This parameter is only used for multiplexed NOR Flash memories. */
Kojto	122:f9eeca106725	157
Kojto	122:f9eeca106725	158	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
Kojto	122:f9eeca106725	159	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
Kojto	122:f9eeca106725	160	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
Kojto	122:f9eeca106725	161	accesses. */
Kojto	122:f9eeca106725	162
Kojto	122:f9eeca106725	163	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
Kojto	122:f9eeca106725	164	to the memory before getting the first data.
Kojto	122:f9eeca106725	165	The parameter value depends on the memory type as shown below:
Kojto	122:f9eeca106725	166	- It must be set to 0 in case of a CRAM
Kojto	122:f9eeca106725	167	- It is don't care in asynchronous NOR, SRAM or ROM accesses
Kojto	122:f9eeca106725	168	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
Kojto	122:f9eeca106725	169	with synchronous burst mode enable */
Kojto	122:f9eeca106725	170
Kojto	122:f9eeca106725	171	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
Kojto	122:f9eeca106725	172	This parameter can be a value of @ref FMC_Access_Mode */
Kojto	122:f9eeca106725	173	}FMC_NORSRAM_TimingTypeDef;
Kojto	122:f9eeca106725	174
Kojto	122:f9eeca106725	175	/**
Kojto	122:f9eeca106725	176	* @brief FMC NAND Configuration Structure definition
Kojto	122:f9eeca106725	177	*/
Kojto	122:f9eeca106725	178	typedef struct
Kojto	122:f9eeca106725	179	{
Kojto	122:f9eeca106725	180	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
Kojto	122:f9eeca106725	181	This parameter can be a value of @ref FMC_NAND_Bank */
Kojto	122:f9eeca106725	182
Kojto	122:f9eeca106725	183	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
Kojto	122:f9eeca106725	184	This parameter can be any value of @ref FMC_Wait_feature */
Kojto	122:f9eeca106725	185
Kojto	122:f9eeca106725	186	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto	122:f9eeca106725	187	This parameter can be any value of @ref FMC_NAND_Data_Width */
Kojto	122:f9eeca106725	188
Kojto	122:f9eeca106725	189	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
Kojto	122:f9eeca106725	190	This parameter can be any value of @ref FMC_ECC */
Kojto	122:f9eeca106725	191
Kojto	122:f9eeca106725	192	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
Kojto	122:f9eeca106725	193	This parameter can be any value of @ref FMC_ECC_Page_Size */
Kojto	122:f9eeca106725	194
Kojto	122:f9eeca106725	195	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	122:f9eeca106725	196	delay between CLE low and RE low.
Kojto	122:f9eeca106725	197	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto	122:f9eeca106725	198
Kojto	122:f9eeca106725	199	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	122:f9eeca106725	200	delay between ALE low and RE low.
Kojto	122:f9eeca106725	201	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	122:f9eeca106725	202	}FMC_NAND_InitTypeDef;
Kojto	122:f9eeca106725	203
Kojto	122:f9eeca106725	204	/**
Kojto	122:f9eeca106725	205	* @brief FMC NAND/PCCARD Timing parameters structure definition
Kojto	122:f9eeca106725	206	*/
Kojto	122:f9eeca106725	207	typedef struct
Kojto	122:f9eeca106725	208	{
Kojto	122:f9eeca106725	209	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
Kojto	122:f9eeca106725	210	the command assertion for NAND-Flash read or write access
Kojto	122:f9eeca106725	211	to common/Attribute or I/O memory space (depending on
Kojto	122:f9eeca106725	212	the memory space timing to be configured).
Kojto	122:f9eeca106725	213	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto	122:f9eeca106725	214
Kojto	122:f9eeca106725	215	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
Kojto	122:f9eeca106725	216	command for NAND-Flash read or write access to
Kojto	122:f9eeca106725	217	common/Attribute or I/O memory space (depending on the
Kojto	122:f9eeca106725	218	memory space timing to be configured).
Kojto	122:f9eeca106725	219	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	122:f9eeca106725	220
Kojto	122:f9eeca106725	221	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
Kojto	122:f9eeca106725	222	(and data for write access) after the command de-assertion
Kojto	122:f9eeca106725	223	for NAND-Flash read or write access to common/Attribute
Kojto	122:f9eeca106725	224	or I/O memory space (depending on the memory space timing
Kojto	122:f9eeca106725	225	to be configured).
Kojto	122:f9eeca106725	226	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	122:f9eeca106725	227
Kojto	122:f9eeca106725	228	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
Kojto	122:f9eeca106725	229	data bus is kept in HiZ after the start of a NAND-Flash
Kojto	122:f9eeca106725	230	write access to common/Attribute or I/O memory space (depending
Kojto	122:f9eeca106725	231	on the memory space timing to be configured).
Kojto	122:f9eeca106725	232	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	122:f9eeca106725	233	}FMC_NAND_PCC_TimingTypeDef;
Kojto	122:f9eeca106725	234
Kojto	122:f9eeca106725	235	/**
Kojto	122:f9eeca106725	236	* @brief FMC NAND Configuration Structure definition
Kojto	122:f9eeca106725	237	*/
Kojto	122:f9eeca106725	238	typedef struct
Kojto	122:f9eeca106725	239	{
Kojto	122:f9eeca106725	240	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
Kojto	122:f9eeca106725	241	This parameter can be any value of @ref FMC_Wait_feature */
Kojto	122:f9eeca106725	242
Kojto	122:f9eeca106725	243	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	122:f9eeca106725	244	delay between CLE low and RE low.
Kojto	122:f9eeca106725	245	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto	122:f9eeca106725	246
Kojto	122:f9eeca106725	247	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto	122:f9eeca106725	248	delay between ALE low and RE low.
Kojto	122:f9eeca106725	249	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto	122:f9eeca106725	250	}FMC_PCCARD_InitTypeDef;
Kojto	122:f9eeca106725	251
Kojto	122:f9eeca106725	252	/**
Kojto	122:f9eeca106725	253	* @brief FMC SDRAM Configuration Structure definition
Kojto	122:f9eeca106725	254	*/
Kojto	122:f9eeca106725	255	typedef struct
Kojto	122:f9eeca106725	256	{
Kojto	122:f9eeca106725	257	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
Kojto	122:f9eeca106725	258	This parameter can be a value of @ref FMC_SDRAM_Bank */
Kojto	122:f9eeca106725	259
Kojto	122:f9eeca106725	260	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
Kojto	122:f9eeca106725	261	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
Kojto	122:f9eeca106725	262
Kojto	122:f9eeca106725	263	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
Kojto	122:f9eeca106725	264	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
Kojto	122:f9eeca106725	265
Kojto	122:f9eeca106725	266	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
Kojto	122:f9eeca106725	267	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
Kojto	122:f9eeca106725	268
Kojto	122:f9eeca106725	269	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
Kojto	122:f9eeca106725	270	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
Kojto	122:f9eeca106725	271
Kojto	122:f9eeca106725	272	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
Kojto	122:f9eeca106725	273	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
Kojto	122:f9eeca106725	274
Kojto	122:f9eeca106725	275	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
Kojto	122:f9eeca106725	276	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
Kojto	122:f9eeca106725	277
Kojto	122:f9eeca106725	278	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
Kojto	122:f9eeca106725	279	to disable the clock before changing frequency.
Kojto	122:f9eeca106725	280	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
Kojto	122:f9eeca106725	281
Kojto	122:f9eeca106725	282	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
Kojto	122:f9eeca106725	283	commands during the CAS latency and stores data in the Read FIFO.
Kojto	122:f9eeca106725	284	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
Kojto	122:f9eeca106725	285
Kojto	122:f9eeca106725	286	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
Kojto	122:f9eeca106725	287	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
Kojto	122:f9eeca106725	288	}FMC_SDRAM_InitTypeDef;
Kojto	122:f9eeca106725	289
Kojto	122:f9eeca106725	290	/**
Kojto	122:f9eeca106725	291	* @brief FMC SDRAM Timing parameters structure definition
Kojto	122:f9eeca106725	292	*/
Kojto	122:f9eeca106725	293	typedef struct
Kojto	122:f9eeca106725	294	{
Kojto	122:f9eeca106725	295	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
Kojto	122:f9eeca106725	296	an active or Refresh command in number of memory clock cycles.
Kojto	122:f9eeca106725	297	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	122:f9eeca106725	298
Kojto	122:f9eeca106725	299	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
Kojto	122:f9eeca106725	300	issuing the Activate command in number of memory clock cycles.
Kojto	122:f9eeca106725	301	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	122:f9eeca106725	302
Kojto	122:f9eeca106725	303	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
Kojto	122:f9eeca106725	304	cycles.
Kojto	122:f9eeca106725	305	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	122:f9eeca106725	306
Kojto	122:f9eeca106725	307	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
Kojto	122:f9eeca106725	308	and the delay between two consecutive Refresh commands in number of
Kojto	122:f9eeca106725	309	memory clock cycles.
Kojto	122:f9eeca106725	310	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	122:f9eeca106725	311
Kojto	122:f9eeca106725	312	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
Kojto	122:f9eeca106725	313	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	122:f9eeca106725	314
Kojto	122:f9eeca106725	315	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
Kojto	122:f9eeca106725	316	in number of memory clock cycles.
Kojto	122:f9eeca106725	317	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	122:f9eeca106725	318
Kojto	122:f9eeca106725	319	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
Kojto	122:f9eeca106725	320	command in number of memory clock cycles.
Kojto	122:f9eeca106725	321	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	122:f9eeca106725	322	}FMC_SDRAM_TimingTypeDef;
Kojto	122:f9eeca106725	323
Kojto	122:f9eeca106725	324	/**
Kojto	122:f9eeca106725	325	* @brief SDRAM command parameters structure definition
Kojto	122:f9eeca106725	326	*/
Kojto	122:f9eeca106725	327	typedef struct
Kojto	122:f9eeca106725	328	{
Kojto	122:f9eeca106725	329	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
Kojto	122:f9eeca106725	330	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
Kojto	122:f9eeca106725	331
Kojto	122:f9eeca106725	332	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
Kojto	122:f9eeca106725	333	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
Kojto	122:f9eeca106725	334
Kojto	122:f9eeca106725	335	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
Kojto	122:f9eeca106725	336	in auto refresh mode.
Kojto	122:f9eeca106725	337	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto	122:f9eeca106725	338	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
Kojto	122:f9eeca106725	339	}FMC_SDRAM_CommandTypeDef;
Kojto	122:f9eeca106725	340	/**
Kojto	122:f9eeca106725	341	* @}
Kojto	122:f9eeca106725	342	*/
Kojto	122:f9eeca106725	343
Kojto	122:f9eeca106725	344	/* Private constants ---------------------------------------------------------*/
Kojto	122:f9eeca106725	345	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
Kojto	122:f9eeca106725	346	* @{
Kojto	122:f9eeca106725	347	*/
Kojto	122:f9eeca106725	348
Kojto	122:f9eeca106725	349	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
Kojto	122:f9eeca106725	350	* @{
Kojto	122:f9eeca106725	351	*/
Kojto	122:f9eeca106725	352	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
Kojto	122:f9eeca106725	353	* @{
Kojto	122:f9eeca106725	354	*/
Kojto	122:f9eeca106725	355	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	356	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	357	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	358	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
Kojto	122:f9eeca106725	359	/**
Kojto	122:f9eeca106725	360	* @}
Kojto	122:f9eeca106725	361	*/
Kojto	122:f9eeca106725	362
Kojto	122:f9eeca106725	363	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
Kojto	122:f9eeca106725	364	* @{
Kojto	122:f9eeca106725	365	*/
Kojto	122:f9eeca106725	366	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	367	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	368	/**
Kojto	122:f9eeca106725	369	* @}
Kojto	122:f9eeca106725	370	*/
Kojto	122:f9eeca106725	371
Kojto	122:f9eeca106725	372	/** @defgroup FMC_Memory_Type FMC Memory Type
Kojto	122:f9eeca106725	373	* @{
Kojto	122:f9eeca106725	374	*/
Kojto	122:f9eeca106725	375	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	376	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	377	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
Kojto	122:f9eeca106725	378	/**
Kojto	122:f9eeca106725	379	* @}
Kojto	122:f9eeca106725	380	*/
Kojto	122:f9eeca106725	381
Kojto	122:f9eeca106725	382	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
Kojto	122:f9eeca106725	383	* @{
Kojto	122:f9eeca106725	384	*/
Kojto	122:f9eeca106725	385	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	386	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	387	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
Kojto	122:f9eeca106725	388	/**
Kojto	122:f9eeca106725	389	* @}
Kojto	122:f9eeca106725	390	*/
Kojto	122:f9eeca106725	391
Kojto	122:f9eeca106725	392	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
Kojto	122:f9eeca106725	393	* @{
Kojto	122:f9eeca106725	394	*/
Kojto	122:f9eeca106725	395	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
Kojto	122:f9eeca106725	396	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	397	/**
Kojto	122:f9eeca106725	398	* @}
Kojto	122:f9eeca106725	399	*/
Kojto	122:f9eeca106725	400
Kojto	122:f9eeca106725	401	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
Kojto	122:f9eeca106725	402	* @{
Kojto	122:f9eeca106725	403	*/
Kojto	122:f9eeca106725	404	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	405	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
Kojto	122:f9eeca106725	406	/**
Kojto	122:f9eeca106725	407	* @}
Kojto	122:f9eeca106725	408	*/
Kojto	122:f9eeca106725	409
Kojto	122:f9eeca106725	410	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
Kojto	122:f9eeca106725	411	* @{
Kojto	122:f9eeca106725	412	*/
Kojto	122:f9eeca106725	413	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	414	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
Kojto	122:f9eeca106725	415	/**
Kojto	122:f9eeca106725	416	* @}
Kojto	122:f9eeca106725	417	*/
Kojto	122:f9eeca106725	418
Kojto	122:f9eeca106725	419	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
Kojto	122:f9eeca106725	420	* @{
Kojto	122:f9eeca106725	421	*/
Kojto	122:f9eeca106725	422	/** @note This mode is not available for the STM32F446/469/479xx devices
Kojto	122:f9eeca106725	423	*/
Kojto	122:f9eeca106725	424	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	425	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
Kojto	122:f9eeca106725	426	/**
Kojto	122:f9eeca106725	427	* @}
Kojto	122:f9eeca106725	428	*/
Kojto	122:f9eeca106725	429
Kojto	122:f9eeca106725	430	/** @defgroup FMC_Wait_Timing FMC Wait Timing
Kojto	122:f9eeca106725	431	* @{
Kojto	122:f9eeca106725	432	*/
Kojto	122:f9eeca106725	433	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	434	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
Kojto	122:f9eeca106725	435	/**
Kojto	122:f9eeca106725	436	* @}
Kojto	122:f9eeca106725	437	*/
Kojto	122:f9eeca106725	438
Kojto	122:f9eeca106725	439	/** @defgroup FMC_Write_Operation FMC Write Operation
Kojto	122:f9eeca106725	440	* @{
Kojto	122:f9eeca106725	441	*/
Kojto	122:f9eeca106725	442	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	443	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
Kojto	122:f9eeca106725	444	/**
Kojto	122:f9eeca106725	445	* @}
Kojto	122:f9eeca106725	446	*/
Kojto	122:f9eeca106725	447
Kojto	122:f9eeca106725	448	/** @defgroup FMC_Wait_Signal FMC Wait Signal
Kojto	122:f9eeca106725	449	* @{
Kojto	122:f9eeca106725	450	*/
Kojto	122:f9eeca106725	451	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	452	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
Kojto	122:f9eeca106725	453	/**
Kojto	122:f9eeca106725	454	* @}
Kojto	122:f9eeca106725	455	*/
Kojto	122:f9eeca106725	456
Kojto	122:f9eeca106725	457	/** @defgroup FMC_Extended_Mode FMC Extended Mode
Kojto	122:f9eeca106725	458	* @{
Kojto	122:f9eeca106725	459	*/
Kojto	122:f9eeca106725	460	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	461	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
Kojto	122:f9eeca106725	462	/**
Kojto	122:f9eeca106725	463	* @}
Kojto	122:f9eeca106725	464	*/
Kojto	122:f9eeca106725	465
Kojto	122:f9eeca106725	466	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
Kojto	122:f9eeca106725	467	* @{
Kojto	122:f9eeca106725	468	*/
Kojto	122:f9eeca106725	469	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	470	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
Kojto	122:f9eeca106725	471	/**
Kojto	122:f9eeca106725	472	* @}
Kojto	122:f9eeca106725	473	*/
Kojto	122:f9eeca106725	474
Kojto	122:f9eeca106725	475	/** @defgroup FMC_Page_Size FMC Page Size
Kojto	122:f9eeca106725	476	* @{
Kojto	122:f9eeca106725	477	*/
Kojto	122:f9eeca106725	478	#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	479	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
Kojto	122:f9eeca106725	480	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
Kojto	122:f9eeca106725	481	#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 \| FMC_BCR1_CPSIZE_1))
Kojto	122:f9eeca106725	482	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
Kojto	122:f9eeca106725	483	/**
Kojto	122:f9eeca106725	484	* @}
Kojto	122:f9eeca106725	485	*/
Kojto	122:f9eeca106725	486
Kojto	122:f9eeca106725	487	/** @defgroup FMC_Write_FIFO FMC Write FIFO
Kojto	122:f9eeca106725	488	* @note These values are available only for the STM32F446/469/479xx devices.
Kojto	122:f9eeca106725	489	* @{
Kojto	122:f9eeca106725	490	*/
Kojto	122:f9eeca106725	491	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
Kojto	122:f9eeca106725	492	#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	493	/**
Kojto	122:f9eeca106725	494	* @}
Kojto	122:f9eeca106725	495	*/
Kojto	122:f9eeca106725	496
Kojto	122:f9eeca106725	497	/** @defgroup FMC_Write_Burst FMC Write Burst
Kojto	122:f9eeca106725	498	* @{
Kojto	122:f9eeca106725	499	*/
Kojto	122:f9eeca106725	500	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	501	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
Kojto	122:f9eeca106725	502	/**
Kojto	122:f9eeca106725	503	* @}
Kojto	122:f9eeca106725	504	*/
Kojto	122:f9eeca106725	505
Kojto	122:f9eeca106725	506	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
Kojto	122:f9eeca106725	507	* @{
Kojto	122:f9eeca106725	508	*/
Kojto	122:f9eeca106725	509	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	510	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
Kojto	122:f9eeca106725	511	/**
Kojto	122:f9eeca106725	512	* @}
Kojto	122:f9eeca106725	513	*/
Kojto	122:f9eeca106725	514
Kojto	122:f9eeca106725	515	/** @defgroup FMC_Access_Mode FMC Access Mode
Kojto	122:f9eeca106725	516	* @{
Kojto	122:f9eeca106725	517	*/
Kojto	122:f9eeca106725	518	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	519	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
Kojto	122:f9eeca106725	520	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
Kojto	122:f9eeca106725	521	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
Kojto	122:f9eeca106725	522	/**
Kojto	122:f9eeca106725	523	* @}
Kojto	122:f9eeca106725	524	*/
Kojto	122:f9eeca106725	525
Kojto	122:f9eeca106725	526	/**
Kojto	122:f9eeca106725	527	* @}
Kojto	122:f9eeca106725	528	*/
Kojto	122:f9eeca106725	529
Kojto	122:f9eeca106725	530	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
Kojto	122:f9eeca106725	531	* @{
Kojto	122:f9eeca106725	532	*/
Kojto	122:f9eeca106725	533	/** @defgroup FMC_NAND_Bank FMC NAND Bank
Kojto	122:f9eeca106725	534	* @{
Kojto	122:f9eeca106725	535	*/
Kojto	122:f9eeca106725	536	#define FMC_NAND_BANK2 ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	537	#define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
Kojto	122:f9eeca106725	538	/**
Kojto	122:f9eeca106725	539	* @}
Kojto	122:f9eeca106725	540	*/
Kojto	122:f9eeca106725	541
Kojto	122:f9eeca106725	542	/** @defgroup FMC_Wait_feature FMC Wait feature
Kojto	122:f9eeca106725	543	* @{
Kojto	122:f9eeca106725	544	*/
Kojto	122:f9eeca106725	545	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	546	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	547	/**
Kojto	122:f9eeca106725	548	* @}
Kojto	122:f9eeca106725	549	*/
Kojto	122:f9eeca106725	550
Kojto	122:f9eeca106725	551	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
Kojto	122:f9eeca106725	552	* @{
Kojto	122:f9eeca106725	553	*/
Kojto	122:f9eeca106725	554	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	555	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
Kojto	122:f9eeca106725	556	/**
Kojto	122:f9eeca106725	557	* @}
Kojto	122:f9eeca106725	558	*/
Kojto	122:f9eeca106725	559
Kojto	122:f9eeca106725	560	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
Kojto	122:f9eeca106725	561	* @{
Kojto	122:f9eeca106725	562	*/
Kojto	122:f9eeca106725	563	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	564	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	565	/**
Kojto	122:f9eeca106725	566	* @}
Kojto	122:f9eeca106725	567	*/
Kojto	122:f9eeca106725	568
Kojto	122:f9eeca106725	569	/** @defgroup FMC_ECC FMC ECC
Kojto	122:f9eeca106725	570	* @{
Kojto	122:f9eeca106725	571	*/
Kojto	122:f9eeca106725	572	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	573	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
Kojto	122:f9eeca106725	574	/**
Kojto	122:f9eeca106725	575	* @}
Kojto	122:f9eeca106725	576	*/
Kojto	122:f9eeca106725	577
Kojto	122:f9eeca106725	578	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
Kojto	122:f9eeca106725	579	* @{
Kojto	122:f9eeca106725	580	*/
Kojto	122:f9eeca106725	581	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	582	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
Kojto	122:f9eeca106725	583	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
Kojto	122:f9eeca106725	584	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
Kojto	122:f9eeca106725	585	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
Kojto	122:f9eeca106725	586	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
Kojto	122:f9eeca106725	587	/**
Kojto	122:f9eeca106725	588	* @}
Kojto	122:f9eeca106725	589	*/
Kojto	122:f9eeca106725	590
Kojto	122:f9eeca106725	591	/**
Kojto	122:f9eeca106725	592	* @}
Kojto	122:f9eeca106725	593	*/
Kojto	122:f9eeca106725	594
Kojto	122:f9eeca106725	595	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
Kojto	122:f9eeca106725	596	* @{
Kojto	122:f9eeca106725	597	*/
Kojto	122:f9eeca106725	598	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
Kojto	122:f9eeca106725	599	* @{
Kojto	122:f9eeca106725	600	*/
Kojto	122:f9eeca106725	601	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	602	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
Kojto	122:f9eeca106725	603	/**
Kojto	122:f9eeca106725	604	* @}
Kojto	122:f9eeca106725	605	*/
Kojto	122:f9eeca106725	606
Kojto	122:f9eeca106725	607	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
Kojto	122:f9eeca106725	608	* @{
Kojto	122:f9eeca106725	609	*/
Kojto	122:f9eeca106725	610	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	611	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
Kojto	122:f9eeca106725	612	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	613	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
Kojto	122:f9eeca106725	614	/**
Kojto	122:f9eeca106725	615	* @}
Kojto	122:f9eeca106725	616	*/
Kojto	122:f9eeca106725	617
Kojto	122:f9eeca106725	618	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
Kojto	122:f9eeca106725	619	* @{
Kojto	122:f9eeca106725	620	*/
Kojto	122:f9eeca106725	621	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	622	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	623	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
Kojto	122:f9eeca106725	624	/**
Kojto	122:f9eeca106725	625	* @}
Kojto	122:f9eeca106725	626	*/
Kojto	122:f9eeca106725	627
Kojto	122:f9eeca106725	628	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
Kojto	122:f9eeca106725	629	* @{
Kojto	122:f9eeca106725	630	*/
Kojto	122:f9eeca106725	631	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	632	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	633	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
Kojto	122:f9eeca106725	634	/**
Kojto	122:f9eeca106725	635	* @}
Kojto	122:f9eeca106725	636	*/
Kojto	122:f9eeca106725	637
Kojto	122:f9eeca106725	638	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
Kojto	122:f9eeca106725	639	* @{
Kojto	122:f9eeca106725	640	*/
Kojto	122:f9eeca106725	641	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	642	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
Kojto	122:f9eeca106725	643	/**
Kojto	122:f9eeca106725	644	* @}
Kojto	122:f9eeca106725	645	*/
Kojto	122:f9eeca106725	646
Kojto	122:f9eeca106725	647	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
Kojto	122:f9eeca106725	648	* @{
Kojto	122:f9eeca106725	649	*/
Kojto	122:f9eeca106725	650	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
Kojto	122:f9eeca106725	651	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
Kojto	122:f9eeca106725	652	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180U)
Kojto	122:f9eeca106725	653	/**
Kojto	122:f9eeca106725	654	* @}
Kojto	122:f9eeca106725	655	*/
Kojto	122:f9eeca106725	656
Kojto	122:f9eeca106725	657	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
Kojto	122:f9eeca106725	658	* @{
Kojto	122:f9eeca106725	659	*/
Kojto	122:f9eeca106725	660	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	661	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
Kojto	122:f9eeca106725	662
Kojto	122:f9eeca106725	663	/**
Kojto	122:f9eeca106725	664	* @}
Kojto	122:f9eeca106725	665	*/
Kojto	122:f9eeca106725	666
Kojto	122:f9eeca106725	667	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
Kojto	122:f9eeca106725	668	* @{
Kojto	122:f9eeca106725	669	*/
Kojto	122:f9eeca106725	670	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	671	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
Kojto	122:f9eeca106725	672	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00U)
Kojto	122:f9eeca106725	673	/**
Kojto	122:f9eeca106725	674	* @}
Kojto	122:f9eeca106725	675	*/
Kojto	122:f9eeca106725	676
Kojto	122:f9eeca106725	677	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
Kojto	122:f9eeca106725	678	* @{
Kojto	122:f9eeca106725	679	*/
Kojto	122:f9eeca106725	680	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	681	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
Kojto	122:f9eeca106725	682	/**
Kojto	122:f9eeca106725	683	* @}
Kojto	122:f9eeca106725	684	*/
Kojto	122:f9eeca106725	685
Kojto	122:f9eeca106725	686	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
Kojto	122:f9eeca106725	687	* @{
Kojto	122:f9eeca106725	688	*/
Kojto	122:f9eeca106725	689	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	690	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
Kojto	122:f9eeca106725	691	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
Kojto	122:f9eeca106725	692	/**
Kojto	122:f9eeca106725	693	* @}
Kojto	122:f9eeca106725	694	*/
Kojto	122:f9eeca106725	695
Kojto	122:f9eeca106725	696	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
Kojto	122:f9eeca106725	697	* @{
Kojto	122:f9eeca106725	698	*/
Kojto	122:f9eeca106725	699	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	700	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
Kojto	122:f9eeca106725	701	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	702	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
Kojto	122:f9eeca106725	703	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	704	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
Kojto	122:f9eeca106725	705	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
Kojto	122:f9eeca106725	706	/**
Kojto	122:f9eeca106725	707	* @}
Kojto	122:f9eeca106725	708	*/
Kojto	122:f9eeca106725	709
Kojto	122:f9eeca106725	710	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
Kojto	122:f9eeca106725	711	* @{
Kojto	122:f9eeca106725	712	*/
Kojto	122:f9eeca106725	713	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
Kojto	122:f9eeca106725	714	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
Kojto	122:f9eeca106725	715	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
Kojto	122:f9eeca106725	716	/**
Kojto	122:f9eeca106725	717	* @}
Kojto	122:f9eeca106725	718	*/
Kojto	122:f9eeca106725	719
Kojto	122:f9eeca106725	720	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
Kojto	122:f9eeca106725	721	* @{
Kojto	122:f9eeca106725	722	*/
Kojto	122:f9eeca106725	723	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	724	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
Kojto	122:f9eeca106725	725	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
Kojto	122:f9eeca106725	726	/**
Kojto	122:f9eeca106725	727	* @}
Kojto	122:f9eeca106725	728	*/
Kojto	122:f9eeca106725	729
Kojto	122:f9eeca106725	730	/**
Kojto	122:f9eeca106725	731	* @}
Kojto	122:f9eeca106725	732	*/
Kojto	122:f9eeca106725	733
Kojto	122:f9eeca106725	734	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
Kojto	122:f9eeca106725	735	* @{
Kojto	122:f9eeca106725	736	*/
Kojto	122:f9eeca106725	737	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
Kojto	122:f9eeca106725	738	#define FMC_IT_LEVEL ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	739	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
Kojto	122:f9eeca106725	740	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
Kojto	122:f9eeca106725	741	/**
Kojto	122:f9eeca106725	742	* @}
Kojto	122:f9eeca106725	743	*/
Kojto	122:f9eeca106725	744
Kojto	122:f9eeca106725	745	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
Kojto	122:f9eeca106725	746	* @{
Kojto	122:f9eeca106725	747	*/
Kojto	122:f9eeca106725	748	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
Kojto	122:f9eeca106725	749	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	750	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	751	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
Kojto	122:f9eeca106725	752	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
Kojto	122:f9eeca106725	753	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
Kojto	122:f9eeca106725	754	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
Kojto	122:f9eeca106725	755	/**
Kojto	122:f9eeca106725	756	* @}
Kojto	122:f9eeca106725	757	*/
Kojto	122:f9eeca106725	758
Kojto	122:f9eeca106725	759	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
Kojto	122:f9eeca106725	760	* @{
Kojto	122:f9eeca106725	761	*/
Kojto	122:f9eeca106725	762	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	763	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
Kojto	122:f9eeca106725	764	#else
Kojto	122:f9eeca106725	765	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
Kojto	122:f9eeca106725	766	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
Kojto	122:f9eeca106725	767	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	768	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
Kojto	122:f9eeca106725	769	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
Kojto	122:f9eeca106725	770	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
Kojto	122:f9eeca106725	771
Kojto	122:f9eeca106725	772
Kojto	122:f9eeca106725	773	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	774	#define FMC_NAND_DEVICE FMC_Bank3
Kojto	122:f9eeca106725	775	#else
Kojto	122:f9eeca106725	776	#define FMC_NAND_DEVICE FMC_Bank2_3
Kojto	122:f9eeca106725	777	#define FMC_PCCARD_DEVICE FMC_Bank4
Kojto	122:f9eeca106725	778	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	779	#define FMC_NORSRAM_DEVICE FMC_Bank1
Kojto	122:f9eeca106725	780	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
Kojto	122:f9eeca106725	781	#define FMC_SDRAM_DEVICE FMC_Bank5_6
Kojto	122:f9eeca106725	782	/**
Kojto	122:f9eeca106725	783	* @}
Kojto	122:f9eeca106725	784	*/
Kojto	122:f9eeca106725	785
Kojto	122:f9eeca106725	786	/**
Kojto	122:f9eeca106725	787	* @}
Kojto	122:f9eeca106725	788	*/
Kojto	122:f9eeca106725	789
Kojto	122:f9eeca106725	790	/* Private macro -------------------------------------------------------------*/
Kojto	122:f9eeca106725	791	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
Kojto	122:f9eeca106725	792	* @{
Kojto	122:f9eeca106725	793	*/
Kojto	122:f9eeca106725	794
Kojto	122:f9eeca106725	795	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
Kojto	122:f9eeca106725	796	* @brief macros to handle NOR device enable/disable and read/write operations
Kojto	122:f9eeca106725	797	* @{
Kojto	122:f9eeca106725	798	*/
Kojto	122:f9eeca106725	799	/**
Kojto	122:f9eeca106725	800	* @brief Enable the NORSRAM device access.
Kojto	122:f9eeca106725	801	* @param __INSTANCE__: FMC_NORSRAM Instance
Kojto	122:f9eeca106725	802	* @param __BANK__: FMC_NORSRAM Bank
Kojto	122:f9eeca106725	803	* @retval None
Kojto	122:f9eeca106725	804	*/
Kojto	122:f9eeca106725	805	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
Kojto	122:f9eeca106725	806
Kojto	122:f9eeca106725	807	/**
Kojto	122:f9eeca106725	808	* @brief Disable the NORSRAM device access.
Kojto	122:f9eeca106725	809	* @param __INSTANCE__: FMC_NORSRAM Instance
Kojto	122:f9eeca106725	810	* @param __BANK__: FMC_NORSRAM Bank
Kojto	122:f9eeca106725	811	* @retval None
Kojto	122:f9eeca106725	812	*/
Kojto	122:f9eeca106725	813	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
Kojto	122:f9eeca106725	814	/**
Kojto	122:f9eeca106725	815	* @}
Kojto	122:f9eeca106725	816	*/
Kojto	122:f9eeca106725	817
Kojto	122:f9eeca106725	818	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
Kojto	122:f9eeca106725	819	* @brief macros to handle NAND device enable/disable
Kojto	122:f9eeca106725	820	* @{
Kojto	122:f9eeca106725	821	*/
Kojto	122:f9eeca106725	822	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	823	/**
Kojto	122:f9eeca106725	824	* @brief Enable the NAND device access.
Kojto	122:f9eeca106725	825	* @param __INSTANCE__: FMC_NAND Instance
Kojto	122:f9eeca106725	826	* @param __BANK__: FMC_NAND Bank
Kojto	122:f9eeca106725	827	* @retval None
Kojto	122:f9eeca106725	828	*/
Kojto	122:f9eeca106725	829	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
Kojto	122:f9eeca106725	830
Kojto	122:f9eeca106725	831	/**
Kojto	122:f9eeca106725	832	* @brief Disable the NAND device access.
Kojto	122:f9eeca106725	833	* @param __INSTANCE__: FMC_NAND Instance
Kojto	122:f9eeca106725	834	* @param __BANK__: FMC_NAND Bank
Kojto	122:f9eeca106725	835	* @retval None
Kojto	122:f9eeca106725	836	*/
Kojto	122:f9eeca106725	837	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
Kojto	122:f9eeca106725	838	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	122:f9eeca106725	839	/**
Kojto	122:f9eeca106725	840	* @brief Enable the NAND device access.
Kojto	122:f9eeca106725	841	* @param __INSTANCE__: FMC_NAND Instance
Kojto	122:f9eeca106725	842	* @param __BANK__: FMC_NAND Bank
Kojto	122:f9eeca106725	843	* @retval None
Kojto	122:f9eeca106725	844	*/
Kojto	122:f9eeca106725	845	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
Kojto	122:f9eeca106725	846	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
Kojto	122:f9eeca106725	847
Kojto	122:f9eeca106725	848	/**
Kojto	122:f9eeca106725	849	* @brief Disable the NAND device access.
Kojto	122:f9eeca106725	850	* @param __INSTANCE__: FMC_NAND Instance
Kojto	122:f9eeca106725	851	* @param __BANK__: FMC_NAND Bank
Kojto	122:f9eeca106725	852	* @retval None
Kojto	122:f9eeca106725	853	*/
Kojto	122:f9eeca106725	854	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
Kojto	122:f9eeca106725	855	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
Kojto	122:f9eeca106725	856
Kojto	122:f9eeca106725	857	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
Kojto	122:f9eeca106725	858	/**
Kojto	122:f9eeca106725	859	* @}
Kojto	122:f9eeca106725	860	*/
Kojto	122:f9eeca106725	861	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	122:f9eeca106725	862	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
Kojto	122:f9eeca106725	863	* @brief macros to handle SRAM read/write operations
Kojto	122:f9eeca106725	864	* @{
Kojto	122:f9eeca106725	865	*/
Kojto	122:f9eeca106725	866	/**
Kojto	122:f9eeca106725	867	* @brief Enable the PCCARD device access.
Kojto	122:f9eeca106725	868	* @param __INSTANCE__: FMC_PCCARD Instance
Kojto	122:f9eeca106725	869	* @retval None
Kojto	122:f9eeca106725	870	*/
Kojto	122:f9eeca106725	871	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
Kojto	122:f9eeca106725	872
Kojto	122:f9eeca106725	873	/**
Kojto	122:f9eeca106725	874	* @brief Disable the PCCARD device access.
Kojto	122:f9eeca106725	875	* @param __INSTANCE__: FMC_PCCARD Instance
Kojto	122:f9eeca106725	876	* @retval None
Kojto	122:f9eeca106725	877	*/
Kojto	122:f9eeca106725	878	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
Kojto	122:f9eeca106725	879	/**
Kojto	122:f9eeca106725	880	* @}
Kojto	122:f9eeca106725	881	*/
Kojto	122:f9eeca106725	882	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	122:f9eeca106725	883
Kojto	122:f9eeca106725	884	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
Kojto	122:f9eeca106725	885	* @brief macros to handle FMC flags and interrupts
Kojto	122:f9eeca106725	886	* @{
Kojto	122:f9eeca106725	887	*/
Kojto	122:f9eeca106725	888	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	889	/**
Kojto	122:f9eeca106725	890	* @brief Enable the NAND device interrupt.
Kojto	122:f9eeca106725	891	* @param __INSTANCE__: FMC_NAND instance
Kojto	122:f9eeca106725	892	* @param __BANK__: FMC_NAND Bank
Kojto	122:f9eeca106725	893	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	122:f9eeca106725	894	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	895	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	122:f9eeca106725	896	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	122:f9eeca106725	897	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	122:f9eeca106725	898	* @retval None
Kojto	122:f9eeca106725	899	*/
Kojto	122:f9eeca106725	900	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
Kojto	122:f9eeca106725	901
Kojto	122:f9eeca106725	902	/**
Kojto	122:f9eeca106725	903	* @brief Disable the NAND device interrupt.
Kojto	122:f9eeca106725	904	* @param __INSTANCE__: FMC_NAND Instance
Kojto	122:f9eeca106725	905	* @param __BANK__: FMC_NAND Bank
Kojto	122:f9eeca106725	906	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	122:f9eeca106725	907	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	908	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	122:f9eeca106725	909	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	122:f9eeca106725	910	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	122:f9eeca106725	911	* @retval None
Kojto	122:f9eeca106725	912	*/
Kojto	122:f9eeca106725	913	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
Kojto	122:f9eeca106725	914
Kojto	122:f9eeca106725	915	/**
Kojto	122:f9eeca106725	916	* @brief Get flag status of the NAND device.
Kojto	122:f9eeca106725	917	* @param __INSTANCE__: FMC_NAND Instance
Kojto	122:f9eeca106725	918	* @param __BANK__: FMC_NAND Bank
Kojto	122:f9eeca106725	919	* @param __FLAG__: FMC_NAND flag
Kojto	122:f9eeca106725	920	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	921	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	122:f9eeca106725	922	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	122:f9eeca106725	923	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	122:f9eeca106725	924	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	122:f9eeca106725	925	* @retval The state of FLAG (SET or RESET).
Kojto	122:f9eeca106725	926	*/
Kojto	122:f9eeca106725	927	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
Kojto	122:f9eeca106725	928	/**
Kojto	122:f9eeca106725	929	* @brief Clear flag status of the NAND device.
Kojto	122:f9eeca106725	930	* @param __INSTANCE__: FMC_NAND Instance
Kojto	122:f9eeca106725	931	* @param __BANK__: FMC_NAND Bank
Kojto	122:f9eeca106725	932	* @param __FLAG__: FMC_NAND flag
Kojto	122:f9eeca106725	933	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	934	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	122:f9eeca106725	935	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	122:f9eeca106725	936	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	122:f9eeca106725	937	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	122:f9eeca106725	938	* @retval None
Kojto	122:f9eeca106725	939	*/
Kojto	122:f9eeca106725	940	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
Kojto	122:f9eeca106725	941	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	122:f9eeca106725	942	/**
Kojto	122:f9eeca106725	943	* @brief Enable the NAND device interrupt.
Kojto	122:f9eeca106725	944	* @param __INSTANCE__: FMC_NAND instance
Kojto	122:f9eeca106725	945	* @param __BANK__: FMC_NAND Bank
Kojto	122:f9eeca106725	946	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	122:f9eeca106725	947	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	948	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	122:f9eeca106725	949	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	122:f9eeca106725	950	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	122:f9eeca106725	951	* @retval None
Kojto	122:f9eeca106725	952	*/
Kojto	122:f9eeca106725	953	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
Kojto	122:f9eeca106725	954	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
Kojto	122:f9eeca106725	955
Kojto	122:f9eeca106725	956	/**
Kojto	122:f9eeca106725	957	* @brief Disable the NAND device interrupt.
Kojto	122:f9eeca106725	958	* @param __INSTANCE__: FMC_NAND Instance
Kojto	122:f9eeca106725	959	* @param __BANK__: FMC_NAND Bank
Kojto	122:f9eeca106725	960	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	122:f9eeca106725	961	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	962	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	122:f9eeca106725	963	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	122:f9eeca106725	964	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	122:f9eeca106725	965	* @retval None
Kojto	122:f9eeca106725	966	*/
Kojto	122:f9eeca106725	967	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
Kojto	122:f9eeca106725	968	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
Kojto	122:f9eeca106725	969
Kojto	122:f9eeca106725	970	/**
Kojto	122:f9eeca106725	971	* @brief Get flag status of the NAND device.
Kojto	122:f9eeca106725	972	* @param __INSTANCE__: FMC_NAND Instance
Kojto	122:f9eeca106725	973	* @param __BANK__: FMC_NAND Bank
Kojto	122:f9eeca106725	974	* @param __FLAG__: FMC_NAND flag
Kojto	122:f9eeca106725	975	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	976	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	122:f9eeca106725	977	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	122:f9eeca106725	978	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	122:f9eeca106725	979	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	122:f9eeca106725	980	* @retval The state of FLAG (SET or RESET).
Kojto	122:f9eeca106725	981	*/
Kojto	122:f9eeca106725	982	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
Kojto	122:f9eeca106725	983	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
Kojto	122:f9eeca106725	984	/**
Kojto	122:f9eeca106725	985	* @brief Clear flag status of the NAND device.
Kojto	122:f9eeca106725	986	* @param __INSTANCE__: FMC_NAND Instance
Kojto	122:f9eeca106725	987	* @param __BANK__: FMC_NAND Bank
Kojto	122:f9eeca106725	988	* @param __FLAG__: FMC_NAND flag
Kojto	122:f9eeca106725	989	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	990	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	122:f9eeca106725	991	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	122:f9eeca106725	992	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	122:f9eeca106725	993	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	122:f9eeca106725	994	* @retval None
Kojto	122:f9eeca106725	995	*/
Kojto	122:f9eeca106725	996	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
Kojto	122:f9eeca106725	997	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
Kojto	122:f9eeca106725	998	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
Kojto	122:f9eeca106725	999
Kojto	122:f9eeca106725	1000	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	122:f9eeca106725	1001	/**
Kojto	122:f9eeca106725	1002	* @brief Enable the PCCARD device interrupt.
Kojto	122:f9eeca106725	1003	* @param __INSTANCE__: FMC_PCCARD instance
Kojto	122:f9eeca106725	1004	* @param __INTERRUPT__: FMC_PCCARD interrupt
Kojto	122:f9eeca106725	1005	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1006	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	122:f9eeca106725	1007	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	122:f9eeca106725	1008	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	122:f9eeca106725	1009	* @retval None
Kojto	122:f9eeca106725	1010	*/
Kojto	122:f9eeca106725	1011	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
Kojto	122:f9eeca106725	1012
Kojto	122:f9eeca106725	1013	/**
Kojto	122:f9eeca106725	1014	* @brief Disable the PCCARD device interrupt.
Kojto	122:f9eeca106725	1015	* @param __INSTANCE__: FMC_PCCARD instance
Kojto	122:f9eeca106725	1016	* @param __INTERRUPT__: FMC_PCCARD interrupt
Kojto	122:f9eeca106725	1017	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1018	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	122:f9eeca106725	1019	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	122:f9eeca106725	1020	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	122:f9eeca106725	1021	* @retval None
Kojto	122:f9eeca106725	1022	*/
Kojto	122:f9eeca106725	1023	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
Kojto	122:f9eeca106725	1024
Kojto	122:f9eeca106725	1025	/**
Kojto	122:f9eeca106725	1026	* @brief Get flag status of the PCCARD device.
Kojto	122:f9eeca106725	1027	* @param __INSTANCE__: FMC_PCCARD instance
Kojto	122:f9eeca106725	1028	* @param __FLAG__: FMC_PCCARD flag
Kojto	122:f9eeca106725	1029	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1030	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	122:f9eeca106725	1031	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	122:f9eeca106725	1032	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	122:f9eeca106725	1033	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	122:f9eeca106725	1034	* @retval The state of FLAG (SET or RESET).
Kojto	122:f9eeca106725	1035	*/
Kojto	122:f9eeca106725	1036	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
Kojto	122:f9eeca106725	1037
Kojto	122:f9eeca106725	1038	/**
Kojto	122:f9eeca106725	1039	* @brief Clear flag status of the PCCARD device.
Kojto	122:f9eeca106725	1040	* @param __INSTANCE__: FMC_PCCARD instance
Kojto	122:f9eeca106725	1041	* @param __FLAG__: FMC_PCCARD flag
Kojto	122:f9eeca106725	1042	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1043	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	122:f9eeca106725	1044	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	122:f9eeca106725	1045	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	122:f9eeca106725	1046	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	122:f9eeca106725	1047	* @retval None
Kojto	122:f9eeca106725	1048	*/
Kojto	122:f9eeca106725	1049	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
Kojto	122:f9eeca106725	1050	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	122:f9eeca106725	1051
Kojto	122:f9eeca106725	1052	/**
Kojto	122:f9eeca106725	1053	* @brief Enable the SDRAM device interrupt.
Kojto	122:f9eeca106725	1054	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	122:f9eeca106725	1055	* @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto	122:f9eeca106725	1056	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1057	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto	122:f9eeca106725	1058	* @retval None
Kojto	122:f9eeca106725	1059	*/
Kojto	122:f9eeca106725	1060	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
Kojto	122:f9eeca106725	1061
Kojto	122:f9eeca106725	1062	/**
Kojto	122:f9eeca106725	1063	* @brief Disable the SDRAM device interrupt.
Kojto	122:f9eeca106725	1064	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	122:f9eeca106725	1065	* @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto	122:f9eeca106725	1066	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1067	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto	122:f9eeca106725	1068	* @retval None
Kojto	122:f9eeca106725	1069	*/
Kojto	122:f9eeca106725	1070	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
Kojto	122:f9eeca106725	1071
Kojto	122:f9eeca106725	1072	/**
Kojto	122:f9eeca106725	1073	* @brief Get flag status of the SDRAM device.
Kojto	122:f9eeca106725	1074	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	122:f9eeca106725	1075	* @param __FLAG__: FMC_SDRAM flag
Kojto	122:f9eeca106725	1076	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1077	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
Kojto	122:f9eeca106725	1078	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
Kojto	122:f9eeca106725	1079	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
Kojto	122:f9eeca106725	1080	* @retval The state of FLAG (SET or RESET).
Kojto	122:f9eeca106725	1081	*/
Kojto	122:f9eeca106725	1082	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
Kojto	122:f9eeca106725	1083
Kojto	122:f9eeca106725	1084	/**
Kojto	122:f9eeca106725	1085	* @brief Clear flag status of the SDRAM device.
Kojto	122:f9eeca106725	1086	* @param __INSTANCE__: FMC_SDRAM instance
Kojto	122:f9eeca106725	1087	* @param __FLAG__: FMC_SDRAM flag
Kojto	122:f9eeca106725	1088	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1089	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
Kojto	122:f9eeca106725	1090	* @retval None
Kojto	122:f9eeca106725	1091	*/
Kojto	122:f9eeca106725	1092	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
Kojto	122:f9eeca106725	1093	/**
Kojto	122:f9eeca106725	1094	* @}
Kojto	122:f9eeca106725	1095	*/
Kojto	122:f9eeca106725	1096
Kojto	122:f9eeca106725	1097	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
Kojto	122:f9eeca106725	1098	* @{
Kojto	122:f9eeca106725	1099	*/
Kojto	122:f9eeca106725	1100	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
Kojto	122:f9eeca106725	1101	((BANK) == FMC_NORSRAM_BANK2) \|\| \
Kojto	122:f9eeca106725	1102	((BANK) == FMC_NORSRAM_BANK3) \|\| \
Kojto	122:f9eeca106725	1103	((BANK) == FMC_NORSRAM_BANK4))
Kojto	122:f9eeca106725	1104
Kojto	122:f9eeca106725	1105	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
Kojto	122:f9eeca106725	1106	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
Kojto	122:f9eeca106725	1107
Kojto	122:f9eeca106725	1108	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
Kojto	122:f9eeca106725	1109	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
Kojto	122:f9eeca106725	1110	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
Kojto	122:f9eeca106725	1111
Kojto	122:f9eeca106725	1112	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	122:f9eeca106725	1113	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	122:f9eeca106725	1114	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto	122:f9eeca106725	1115
Kojto	122:f9eeca106725	1116	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
Kojto	122:f9eeca106725	1117	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
Kojto	122:f9eeca106725	1118	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
Kojto	122:f9eeca106725	1119	((__MODE__) == FMC_ACCESS_MODE_D))
Kojto	122:f9eeca106725	1120
Kojto	122:f9eeca106725	1121	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
Kojto	122:f9eeca106725	1122	((BANK) == FMC_NAND_BANK3))
Kojto	122:f9eeca106725	1123
Kojto	122:f9eeca106725	1124	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
Kojto	122:f9eeca106725	1125	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
Kojto	122:f9eeca106725	1126
Kojto	122:f9eeca106725	1127	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
Kojto	122:f9eeca106725	1128	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
Kojto	122:f9eeca106725	1129
Kojto	122:f9eeca106725	1130	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
Kojto	122:f9eeca106725	1131	((STATE) == FMC_NAND_ECC_ENABLE))
Kojto	122:f9eeca106725	1132
Kojto	122:f9eeca106725	1133	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
Kojto	122:f9eeca106725	1134	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
Kojto	122:f9eeca106725	1135	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
Kojto	122:f9eeca106725	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
Kojto	122:f9eeca106725	1137	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
Kojto	122:f9eeca106725	1138	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto	122:f9eeca106725	1139
Kojto	122:f9eeca106725	1140	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
Kojto	122:f9eeca106725	1141
Kojto	122:f9eeca106725	1142	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
Kojto	122:f9eeca106725	1143
Kojto	122:f9eeca106725	1144	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
Kojto	122:f9eeca106725	1145
Kojto	122:f9eeca106725	1146	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
Kojto	122:f9eeca106725	1147
Kojto	122:f9eeca106725	1148	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
Kojto	122:f9eeca106725	1149
Kojto	122:f9eeca106725	1150	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
Kojto	122:f9eeca106725	1151
Kojto	122:f9eeca106725	1152	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
Kojto	122:f9eeca106725	1153
Kojto	122:f9eeca106725	1154	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
Kojto	122:f9eeca106725	1155
Kojto	122:f9eeca106725	1156	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
Kojto	122:f9eeca106725	1157
Kojto	122:f9eeca106725	1158	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
Kojto	122:f9eeca106725	1159
Kojto	122:f9eeca106725	1160	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
Kojto	122:f9eeca106725	1161	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
Kojto	122:f9eeca106725	1162
Kojto	122:f9eeca106725	1163	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
Kojto	122:f9eeca106725	1164	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto	122:f9eeca106725	1165
Kojto	122:f9eeca106725	1166	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	122:f9eeca106725	1167	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
Kojto	122:f9eeca106725	1168	((__MODE__) == FMC_WRAP_MODE_ENABLE))
Kojto	122:f9eeca106725	1169	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	122:f9eeca106725	1170
Kojto	122:f9eeca106725	1171	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
Kojto	122:f9eeca106725	1172	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
Kojto	122:f9eeca106725	1173
Kojto	122:f9eeca106725	1174	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
Kojto	122:f9eeca106725	1175	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
Kojto	122:f9eeca106725	1176
Kojto	122:f9eeca106725	1177	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
Kojto	122:f9eeca106725	1178	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
Kojto	122:f9eeca106725	1179
Kojto	122:f9eeca106725	1180	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
Kojto	122:f9eeca106725	1181	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
Kojto	122:f9eeca106725	1182
Kojto	122:f9eeca106725	1183	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
Kojto	122:f9eeca106725	1184	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto	122:f9eeca106725	1185
Kojto	122:f9eeca106725	1186	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
Kojto	122:f9eeca106725	1187	((__BURST__) == FMC_WRITE_BURST_ENABLE))
Kojto	122:f9eeca106725	1188
Kojto	122:f9eeca106725	1189	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
Kojto	122:f9eeca106725	1190	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto	122:f9eeca106725	1191
Kojto	122:f9eeca106725	1192	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
Kojto	122:f9eeca106725	1193
Kojto	122:f9eeca106725	1194	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
Kojto	122:f9eeca106725	1195
Kojto	122:f9eeca106725	1196	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
Kojto	122:f9eeca106725	1197
Kojto	122:f9eeca106725	1198	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
Kojto	122:f9eeca106725	1199
Kojto	122:f9eeca106725	1200	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
Kojto	122:f9eeca106725	1201
Kojto	122:f9eeca106725	1202	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
Kojto	122:f9eeca106725	1203
Kojto	122:f9eeca106725	1204	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
Kojto	122:f9eeca106725	1205	((BANK) == FMC_SDRAM_BANK2))
Kojto	122:f9eeca106725	1206
Kojto	122:f9eeca106725	1207	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
Kojto	122:f9eeca106725	1208	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
Kojto	122:f9eeca106725	1209	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
Kojto	122:f9eeca106725	1210	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
Kojto	122:f9eeca106725	1211
Kojto	122:f9eeca106725	1212	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
Kojto	122:f9eeca106725	1213	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
Kojto	122:f9eeca106725	1214	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
Kojto	122:f9eeca106725	1215
Kojto	122:f9eeca106725	1216	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	122:f9eeca106725	1217	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	122:f9eeca106725	1218	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
Kojto	122:f9eeca106725	1219
Kojto	122:f9eeca106725	1220	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
Kojto	122:f9eeca106725	1221	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
Kojto	122:f9eeca106725	1222
Kojto	122:f9eeca106725	1223
Kojto	122:f9eeca106725	1224	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
Kojto	122:f9eeca106725	1225	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
Kojto	122:f9eeca106725	1226	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
Kojto	122:f9eeca106725	1227
Kojto	122:f9eeca106725	1228	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
Kojto	122:f9eeca106725	1229	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
Kojto	122:f9eeca106725	1230	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
Kojto	122:f9eeca106725	1231
Kojto	122:f9eeca106725	1232	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
Kojto	122:f9eeca106725	1233	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
Kojto	122:f9eeca106725	1234
Kojto	122:f9eeca106725	1235
Kojto	122:f9eeca106725	1236	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
Kojto	122:f9eeca106725	1237	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
Kojto	122:f9eeca106725	1238	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
Kojto	122:f9eeca106725	1239
Kojto	122:f9eeca106725	1240	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
Kojto	122:f9eeca106725	1241
Kojto	122:f9eeca106725	1242	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
Kojto	122:f9eeca106725	1243
Kojto	122:f9eeca106725	1244	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
Kojto	122:f9eeca106725	1245
Kojto	122:f9eeca106725	1246	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
Kojto	122:f9eeca106725	1247
Kojto	122:f9eeca106725	1248	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
Kojto	122:f9eeca106725	1249
Kojto	122:f9eeca106725	1250	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
Kojto	122:f9eeca106725	1251
Kojto	122:f9eeca106725	1252	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
Kojto	122:f9eeca106725	1253
Kojto	122:f9eeca106725	1254	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
Kojto	122:f9eeca106725	1255	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
Kojto	122:f9eeca106725	1256	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
Kojto	122:f9eeca106725	1257	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
Kojto	122:f9eeca106725	1258	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
Kojto	122:f9eeca106725	1259	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
Kojto	122:f9eeca106725	1260	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
Kojto	122:f9eeca106725	1261
Kojto	122:f9eeca106725	1262	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
Kojto	122:f9eeca106725	1263	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
Kojto	122:f9eeca106725	1264	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
Kojto	122:f9eeca106725	1265
Kojto	122:f9eeca106725	1266	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
Kojto	122:f9eeca106725	1267
Kojto	122:f9eeca106725	1268	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
Kojto	122:f9eeca106725	1269
Kojto	122:f9eeca106725	1270	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
Kojto	122:f9eeca106725	1271
Kojto	122:f9eeca106725	1272	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
Kojto	122:f9eeca106725	1273
Kojto	122:f9eeca106725	1274	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
Kojto	122:f9eeca106725	1275	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
Kojto	122:f9eeca106725	1276
Kojto	122:f9eeca106725	1277	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
Kojto	122:f9eeca106725	1278	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
Kojto	122:f9eeca106725	1279	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
Kojto	122:f9eeca106725	1280	((SIZE) == FMC_PAGE_SIZE_512) \|\| \
Kojto	122:f9eeca106725	1281	((SIZE) == FMC_PAGE_SIZE_1024))
Kojto	122:f9eeca106725	1282
Kojto	122:f9eeca106725	1283	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	1284	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
Kojto	122:f9eeca106725	1285	((FIFO) == FMC_WRITE_FIFO_ENABLE))
Kojto	122:f9eeca106725	1286	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	1287
Kojto	122:f9eeca106725	1288	/**
Kojto	122:f9eeca106725	1289	* @}
Kojto	122:f9eeca106725	1290	*/
Kojto	122:f9eeca106725	1291
Kojto	122:f9eeca106725	1292	/**
Kojto	122:f9eeca106725	1293	* @}
Kojto	122:f9eeca106725	1294	*/
Kojto	122:f9eeca106725	1295
Kojto	122:f9eeca106725	1296	/* Private functions ---------------------------------------------------------*/
Kojto	122:f9eeca106725	1297	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
Kojto	122:f9eeca106725	1298	* @{
Kojto	122:f9eeca106725	1299	*/
Kojto	122:f9eeca106725	1300
Kojto	122:f9eeca106725	1301	/** @defgroup FMC_LL_NORSRAM NOR SRAM
Kojto	122:f9eeca106725	1302	* @{
Kojto	122:f9eeca106725	1303	*/
Kojto	122:f9eeca106725	1304	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto	122:f9eeca106725	1305	* @{
Kojto	122:f9eeca106725	1306	*/
Kojto	122:f9eeca106725	1307	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
Kojto	122:f9eeca106725	1308	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
Kojto	122:f9eeca106725	1309	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
Kojto	122:f9eeca106725	1310	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
Kojto	122:f9eeca106725	1311	/**
Kojto	122:f9eeca106725	1312	* @}
Kojto	122:f9eeca106725	1313	*/
Kojto	122:f9eeca106725	1314
Kojto	122:f9eeca106725	1315	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto	122:f9eeca106725	1316	* @{
Kojto	122:f9eeca106725	1317	*/
Kojto	122:f9eeca106725	1318	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto	122:f9eeca106725	1319	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto	122:f9eeca106725	1320	/**
Kojto	122:f9eeca106725	1321	* @}
Kojto	122:f9eeca106725	1322	*/
Kojto	122:f9eeca106725	1323	/**
Kojto	122:f9eeca106725	1324	* @}
Kojto	122:f9eeca106725	1325	*/
Kojto	122:f9eeca106725	1326
Kojto	122:f9eeca106725	1327	/** @defgroup FMC_LL_NAND NAND
Kojto	122:f9eeca106725	1328	* @{
Kojto	122:f9eeca106725	1329	*/
Kojto	122:f9eeca106725	1330	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto	122:f9eeca106725	1331	* @{
Kojto	122:f9eeca106725	1332	*/
Kojto	122:f9eeca106725	1333	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
Kojto	122:f9eeca106725	1334	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
Kojto	122:f9eeca106725	1335	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
Kojto	122:f9eeca106725	1336	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	122:f9eeca106725	1337	/**
Kojto	122:f9eeca106725	1338	* @}
Kojto	122:f9eeca106725	1339	*/
Kojto	122:f9eeca106725	1340
Kojto	122:f9eeca106725	1341	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto	122:f9eeca106725	1342	* @{
Kojto	122:f9eeca106725	1343	*/
Kojto	122:f9eeca106725	1344	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	122:f9eeca106725	1345	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	122:f9eeca106725	1346	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
Kojto	122:f9eeca106725	1347
Kojto	122:f9eeca106725	1348	/**
Kojto	122:f9eeca106725	1349	* @}
Kojto	122:f9eeca106725	1350	*/
Kojto	122:f9eeca106725	1351	/**
Kojto	122:f9eeca106725	1352	* @}
Kojto	122:f9eeca106725	1353	*/
Kojto	122:f9eeca106725	1354	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	122:f9eeca106725	1355	/** @defgroup FMC_LL_PCCARD PCCARD
Kojto	122:f9eeca106725	1356	* @{
Kojto	122:f9eeca106725	1357	*/
Kojto	122:f9eeca106725	1358	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
Kojto	122:f9eeca106725	1359	* @{
Kojto	122:f9eeca106725	1360	*/
Kojto	122:f9eeca106725	1361	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
Kojto	122:f9eeca106725	1362	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
Kojto	122:f9eeca106725	1363	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
Kojto	122:f9eeca106725	1364	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
Kojto	122:f9eeca106725	1365	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
Kojto	122:f9eeca106725	1366	/**
Kojto	122:f9eeca106725	1367	* @}
Kojto	122:f9eeca106725	1368	*/
Kojto	122:f9eeca106725	1369	/**
Kojto	122:f9eeca106725	1370	* @}
Kojto	122:f9eeca106725	1371	*/
Kojto	122:f9eeca106725	1372	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	122:f9eeca106725	1373
Kojto	122:f9eeca106725	1374	/** @defgroup FMC_LL_SDRAM SDRAM
Kojto	122:f9eeca106725	1375	* @{
Kojto	122:f9eeca106725	1376	*/
Kojto	122:f9eeca106725	1377	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
Kojto	122:f9eeca106725	1378	* @{
Kojto	122:f9eeca106725	1379	*/
Kojto	122:f9eeca106725	1380	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
Kojto	122:f9eeca106725	1381	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
Kojto	122:f9eeca106725	1382	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	122:f9eeca106725	1383	/**
Kojto	122:f9eeca106725	1384	* @}
Kojto	122:f9eeca106725	1385	*/
Kojto	122:f9eeca106725	1386
Kojto	122:f9eeca106725	1387	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
Kojto	122:f9eeca106725	1388	* @{
Kojto	122:f9eeca106725	1389	*/
Kojto	122:f9eeca106725	1390	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	122:f9eeca106725	1391	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	122:f9eeca106725	1392	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
Kojto	122:f9eeca106725	1393	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
Kojto	122:f9eeca106725	1394	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
Kojto	122:f9eeca106725	1395	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	122:f9eeca106725	1396	/**
Kojto	122:f9eeca106725	1397	* @}
Kojto	122:f9eeca106725	1398	*/
Kojto	122:f9eeca106725	1399	/**
Kojto	122:f9eeca106725	1400	* @}
Kojto	122:f9eeca106725	1401	*/
Kojto	122:f9eeca106725	1402
Kojto	122:f9eeca106725	1403	/**
Kojto	122:f9eeca106725	1404	* @}
Kojto	122:f9eeca106725	1405	*/
Kojto	122:f9eeca106725	1406
Kojto	122:f9eeca106725	1407	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	1408	/**
Kojto	122:f9eeca106725	1409	* @}
Kojto	122:f9eeca106725	1410	*/
Kojto	122:f9eeca106725	1411
Kojto	122:f9eeca106725	1412	/**
Kojto	122:f9eeca106725	1413	* @}
Kojto	122:f9eeca106725	1414	*/
Kojto	122:f9eeca106725	1415	#ifdef __cplusplus
Kojto	122:f9eeca106725	1416	}
Kojto	122:f9eeca106725	1417	#endif
Kojto	122:f9eeca106725	1418
Kojto	122:f9eeca106725	1419	#endif /* __STM32F4xx_LL_FMC_H */
Kojto	122:f9eeca106725	1420
Kojto	122:f9eeca106725	1421	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/