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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_DISCO_F769NI/stm32f769xx.h@126:abea610beb85, 2016-09-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Sep 16 13:57:13 2016 +0100
Revision:
126:abea610beb85
Release 126 of the mbed library



Changes:



New Targets:

#2504: [Disco_F769NI] adding new target [https://github.com/ARMmbed/mbed-os/pull/2504]

#2654: DELTA_DFBM_NQ620 platform porting [https://github.com/ARMmbed/mbed-os/pull/2654]

#2615: [MTM_MTCONNECT04S] Added support for MTM_MTCONNECT04S [https://github.com/ARMmbed/mbed-os/pull/2615]

#2548: Nucleof303ze [https://github.com/ARMmbed/mbed-os/pull/2548]



Fixes:



#2657: [MAX326xx] Removed echoing of characters and carriage return. [https://github.com/ARMmbed/mbed-os/pull/2657]

#2651: Use lp_timer to count time in the deepsleep tests [https://github.com/ARMmbed/mbed-os/pull/2651]

#2643: Fix thread self termination [https://github.com/ARMmbed/mbed-os/pull/2643]

#2623: DISCO_L476VG - Add Serial Flow Control pins + add SERIAL_FC macro [https://github.com/ARMmbed/mbed-os/pull/2623]

#2617: STM32F2xx - Enable Serial Flow Control [https://github.com/ARMmbed/mbed-os/pull/2617]

#2601: Adding ON Semiconductor copyright notice to source and header files. [https://github.com/ARMmbed/mbed-os/pull/2601]

#2597: [HAL] Fixed "intrinsic is deprecated" warnings [https://github.com/ARMmbed/mbed-os/pull/2597]

#2589: [NUC472] Fix heap configuration error with armcc [https://github.com/ARMmbed/mbed-os/pull/2589]

#2587: add PTEx pins as option for SPI on Hexiwear - for SD Card Interface [https://github.com/ARMmbed/mbed-os/pull/2587]

#2584: Set size of callback irq array to IrqCnt [https://github.com/ARMmbed/mbed-os/pull/2584]

#2582: [GCC_CR] fix runtime hang for baremetal build [https://github.com/ARMmbed/mbed-os/pull/2582]

#2562: Fix GCC lazy init race condition and add test [https://github.com/ARMmbed/mbed-os/pull/2562]

#2538: STM32F4xx - Add support of ADC internal channels (Temp, VRef, VBat) [https://github.com/ARMmbed/mbed-os/pull/2538]

#2514: Updated FlexCan and SAI SDK drivers [https://github.com/ARMmbed/mbed-os/pull/2514]

#2442: Malloc heap info [https://github.com/ARMmbed/mbed-os/pull/2442]

#2419: [STM32F1] Add asynchronous serial [https://github.com/ARMmbed/mbed-os/pull/2419]

#2130: stm32 : reduce number of device.h files [https://github.com/ARMmbed/mbed-os/pull/2130]

#2678: Fixing NCS36510 compile on Linux [https://github.com/ARMmbed/mbed-os/pull/2678]

#2607: Fix uvisor memory tracing [https://github.com/ARMmbed/mbed-os/pull/2607]

#2596: [HAL] Improve memory tracer [https://github.com/ARMmbed/mbed-os/pull/2596]

#2487: Runtime dynamic memory tracing [https://github.com/ARMmbed/mbed-os/pull/2487]

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 126:abea610beb85 1 /**
AnnaBridge 126:abea610beb85 2 ******************************************************************************
AnnaBridge 126:abea610beb85 3 * @file stm32f769xx.h
AnnaBridge 126:abea610beb85 4 * @author MCD Application Team
AnnaBridge 126:abea610beb85 5 * @version V1.1.0
AnnaBridge 126:abea610beb85 6 * @date 22-April-2016
AnnaBridge 126:abea610beb85 7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
AnnaBridge 126:abea610beb85 8 *
AnnaBridge 126:abea610beb85 9 * This file contains:
AnnaBridge 126:abea610beb85 10 * - Data structures and the address mapping for all peripherals
AnnaBridge 126:abea610beb85 11 * - Peripheral's registers declarations and bits definition
AnnaBridge 126:abea610beb85 12 * - Macros to access peripheral’s registers hardware
AnnaBridge 126:abea610beb85 13 *
AnnaBridge 126:abea610beb85 14 ******************************************************************************
AnnaBridge 126:abea610beb85 15 * @attention
AnnaBridge 126:abea610beb85 16 *
AnnaBridge 126:abea610beb85 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 126:abea610beb85 18 *
AnnaBridge 126:abea610beb85 19 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 126:abea610beb85 20 * are permitted provided that the following conditions are met:
AnnaBridge 126:abea610beb85 21 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 126:abea610beb85 22 * this list of conditions and the following disclaimer.
AnnaBridge 126:abea610beb85 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 126:abea610beb85 24 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 126:abea610beb85 25 * and/or other materials provided with the distribution.
AnnaBridge 126:abea610beb85 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 126:abea610beb85 27 * may be used to endorse or promote products derived from this software
AnnaBridge 126:abea610beb85 28 * without specific prior written permission.
AnnaBridge 126:abea610beb85 29 *
AnnaBridge 126:abea610beb85 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 126:abea610beb85 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 126:abea610beb85 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 126:abea610beb85 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 126:abea610beb85 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 126:abea610beb85 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 126:abea610beb85 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 126:abea610beb85 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 126:abea610beb85 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 126:abea610beb85 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 126:abea610beb85 40 *
AnnaBridge 126:abea610beb85 41 ******************************************************************************
AnnaBridge 126:abea610beb85 42 */
AnnaBridge 126:abea610beb85 43
AnnaBridge 126:abea610beb85 44 /** @addtogroup CMSIS_Device
AnnaBridge 126:abea610beb85 45 * @{
AnnaBridge 126:abea610beb85 46 */
AnnaBridge 126:abea610beb85 47
AnnaBridge 126:abea610beb85 48 /** @addtogroup stm32f769xx
AnnaBridge 126:abea610beb85 49 * @{
AnnaBridge 126:abea610beb85 50 */
AnnaBridge 126:abea610beb85 51
AnnaBridge 126:abea610beb85 52 #ifndef __STM32F769xx_H
AnnaBridge 126:abea610beb85 53 #define __STM32F769xx_H
AnnaBridge 126:abea610beb85 54
AnnaBridge 126:abea610beb85 55 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 56 extern "C" {
AnnaBridge 126:abea610beb85 57 #endif /* __cplusplus */
AnnaBridge 126:abea610beb85 58
AnnaBridge 126:abea610beb85 59 /** @addtogroup Configuration_section_for_CMSIS
AnnaBridge 126:abea610beb85 60 * @{
AnnaBridge 126:abea610beb85 61 */
AnnaBridge 126:abea610beb85 62
AnnaBridge 126:abea610beb85 63 /**
AnnaBridge 126:abea610beb85 64 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
AnnaBridge 126:abea610beb85 65 * in @ref Library_configuration_section
AnnaBridge 126:abea610beb85 66 */
AnnaBridge 126:abea610beb85 67 typedef enum
AnnaBridge 126:abea610beb85 68 {
AnnaBridge 126:abea610beb85 69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
AnnaBridge 126:abea610beb85 70 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 126:abea610beb85 71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
AnnaBridge 126:abea610beb85 72 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
AnnaBridge 126:abea610beb85 73 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
AnnaBridge 126:abea610beb85 74 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
AnnaBridge 126:abea610beb85 75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
AnnaBridge 126:abea610beb85 76 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
AnnaBridge 126:abea610beb85 77 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
AnnaBridge 126:abea610beb85 78 /****** STM32 specific Interrupt Numbers **********************************************************************/
AnnaBridge 126:abea610beb85 79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
AnnaBridge 126:abea610beb85 80 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
AnnaBridge 126:abea610beb85 81 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
AnnaBridge 126:abea610beb85 82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
AnnaBridge 126:abea610beb85 83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
AnnaBridge 126:abea610beb85 84 RCC_IRQn = 5, /*!< RCC global Interrupt */
AnnaBridge 126:abea610beb85 85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
AnnaBridge 126:abea610beb85 86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
AnnaBridge 126:abea610beb85 87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
AnnaBridge 126:abea610beb85 88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
AnnaBridge 126:abea610beb85 89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
AnnaBridge 126:abea610beb85 90 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
AnnaBridge 126:abea610beb85 91 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
AnnaBridge 126:abea610beb85 92 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
AnnaBridge 126:abea610beb85 93 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
AnnaBridge 126:abea610beb85 94 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
AnnaBridge 126:abea610beb85 95 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
AnnaBridge 126:abea610beb85 96 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
AnnaBridge 126:abea610beb85 97 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
AnnaBridge 126:abea610beb85 98 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
AnnaBridge 126:abea610beb85 99 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
AnnaBridge 126:abea610beb85 100 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
AnnaBridge 126:abea610beb85 101 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
AnnaBridge 126:abea610beb85 102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
AnnaBridge 126:abea610beb85 103 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
AnnaBridge 126:abea610beb85 104 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
AnnaBridge 126:abea610beb85 105 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
AnnaBridge 126:abea610beb85 106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
AnnaBridge 126:abea610beb85 107 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
AnnaBridge 126:abea610beb85 108 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
AnnaBridge 126:abea610beb85 109 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
AnnaBridge 126:abea610beb85 110 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
AnnaBridge 126:abea610beb85 111 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
AnnaBridge 126:abea610beb85 112 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
AnnaBridge 126:abea610beb85 113 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
AnnaBridge 126:abea610beb85 114 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
AnnaBridge 126:abea610beb85 115 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
AnnaBridge 126:abea610beb85 116 USART1_IRQn = 37, /*!< USART1 global Interrupt */
AnnaBridge 126:abea610beb85 117 USART2_IRQn = 38, /*!< USART2 global Interrupt */
AnnaBridge 126:abea610beb85 118 USART3_IRQn = 39, /*!< USART3 global Interrupt */
AnnaBridge 126:abea610beb85 119 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
AnnaBridge 126:abea610beb85 120 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
AnnaBridge 126:abea610beb85 121 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
AnnaBridge 126:abea610beb85 122 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
AnnaBridge 126:abea610beb85 123 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
AnnaBridge 126:abea610beb85 124 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
AnnaBridge 126:abea610beb85 125 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
AnnaBridge 126:abea610beb85 126 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
AnnaBridge 126:abea610beb85 127 FMC_IRQn = 48, /*!< FMC global Interrupt */
AnnaBridge 126:abea610beb85 128 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
AnnaBridge 126:abea610beb85 129 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
AnnaBridge 126:abea610beb85 130 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
AnnaBridge 126:abea610beb85 131 UART4_IRQn = 52, /*!< UART4 global Interrupt */
AnnaBridge 126:abea610beb85 132 UART5_IRQn = 53, /*!< UART5 global Interrupt */
AnnaBridge 126:abea610beb85 133 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
AnnaBridge 126:abea610beb85 134 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
AnnaBridge 126:abea610beb85 135 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
AnnaBridge 126:abea610beb85 136 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
AnnaBridge 126:abea610beb85 137 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
AnnaBridge 126:abea610beb85 138 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
AnnaBridge 126:abea610beb85 139 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
AnnaBridge 126:abea610beb85 140 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
AnnaBridge 126:abea610beb85 141 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
AnnaBridge 126:abea610beb85 142 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
AnnaBridge 126:abea610beb85 143 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
AnnaBridge 126:abea610beb85 144 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
AnnaBridge 126:abea610beb85 145 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
AnnaBridge 126:abea610beb85 146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
AnnaBridge 126:abea610beb85 147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
AnnaBridge 126:abea610beb85 148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
AnnaBridge 126:abea610beb85 149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
AnnaBridge 126:abea610beb85 150 USART6_IRQn = 71, /*!< USART6 global interrupt */
AnnaBridge 126:abea610beb85 151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
AnnaBridge 126:abea610beb85 152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
AnnaBridge 126:abea610beb85 153 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
AnnaBridge 126:abea610beb85 154 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
AnnaBridge 126:abea610beb85 155 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
AnnaBridge 126:abea610beb85 156 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
AnnaBridge 126:abea610beb85 157 DCMI_IRQn = 78, /*!< DCMI global interrupt */
AnnaBridge 126:abea610beb85 158 RNG_IRQn = 80, /*!< RNG global interrupt */
AnnaBridge 126:abea610beb85 159 FPU_IRQn = 81, /*!< FPU global interrupt */
AnnaBridge 126:abea610beb85 160 UART7_IRQn = 82, /*!< UART7 global interrupt */
AnnaBridge 126:abea610beb85 161 UART8_IRQn = 83, /*!< UART8 global interrupt */
AnnaBridge 126:abea610beb85 162 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
AnnaBridge 126:abea610beb85 163 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
AnnaBridge 126:abea610beb85 164 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
AnnaBridge 126:abea610beb85 165 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
AnnaBridge 126:abea610beb85 166 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
AnnaBridge 126:abea610beb85 167 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
AnnaBridge 126:abea610beb85 168 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
AnnaBridge 126:abea610beb85 169 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
AnnaBridge 126:abea610beb85 170 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
AnnaBridge 126:abea610beb85 171 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
AnnaBridge 126:abea610beb85 172 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
AnnaBridge 126:abea610beb85 173 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
AnnaBridge 126:abea610beb85 174 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
AnnaBridge 126:abea610beb85 175 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
AnnaBridge 126:abea610beb85 176 DSI_IRQn = 98, /*!< DSI global Interrupt */
AnnaBridge 126:abea610beb85 177 DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */
AnnaBridge 126:abea610beb85 178 DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */
AnnaBridge 126:abea610beb85 179 DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */
AnnaBridge 126:abea610beb85 180 DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */
AnnaBridge 126:abea610beb85 181 SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */
AnnaBridge 126:abea610beb85 182 CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */
AnnaBridge 126:abea610beb85 183 CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */
AnnaBridge 126:abea610beb85 184 CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */
AnnaBridge 126:abea610beb85 185 CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */
AnnaBridge 126:abea610beb85 186 JPEG_IRQn = 108, /*!< JPEG global Interrupt */
AnnaBridge 126:abea610beb85 187 MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */
AnnaBridge 126:abea610beb85 188 } IRQn_Type;
AnnaBridge 126:abea610beb85 189
AnnaBridge 126:abea610beb85 190 /**
AnnaBridge 126:abea610beb85 191 * @}
AnnaBridge 126:abea610beb85 192 */
AnnaBridge 126:abea610beb85 193
AnnaBridge 126:abea610beb85 194 /**
AnnaBridge 126:abea610beb85 195 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
AnnaBridge 126:abea610beb85 196 */
AnnaBridge 126:abea610beb85 197 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
AnnaBridge 126:abea610beb85 198 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
AnnaBridge 126:abea610beb85 199 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
AnnaBridge 126:abea610beb85 200 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 126:abea610beb85 201 #define __FPU_PRESENT 1 /*!< FPU present */
AnnaBridge 126:abea610beb85 202 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
AnnaBridge 126:abea610beb85 203 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
AnnaBridge 126:abea610beb85 204 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
AnnaBridge 126:abea610beb85 205
AnnaBridge 126:abea610beb85 206
AnnaBridge 126:abea610beb85 207 #include "system_stm32f7xx.h"
AnnaBridge 126:abea610beb85 208 #include <stdint.h>
AnnaBridge 126:abea610beb85 209
AnnaBridge 126:abea610beb85 210 /** @addtogroup Peripheral_registers_structures
AnnaBridge 126:abea610beb85 211 * @{
AnnaBridge 126:abea610beb85 212 */
AnnaBridge 126:abea610beb85 213
AnnaBridge 126:abea610beb85 214 /**
AnnaBridge 126:abea610beb85 215 * @brief Analog to Digital Converter
AnnaBridge 126:abea610beb85 216 */
AnnaBridge 126:abea610beb85 217
AnnaBridge 126:abea610beb85 218 typedef struct
AnnaBridge 126:abea610beb85 219 {
AnnaBridge 126:abea610beb85 220 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 221 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 222 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 223 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 224 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 225 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 226 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 227 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 228 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 229 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
AnnaBridge 126:abea610beb85 230 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
AnnaBridge 126:abea610beb85 231 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
AnnaBridge 126:abea610beb85 232 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
AnnaBridge 126:abea610beb85 233 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
AnnaBridge 126:abea610beb85 234 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
AnnaBridge 126:abea610beb85 235 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
AnnaBridge 126:abea610beb85 236 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
AnnaBridge 126:abea610beb85 237 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
AnnaBridge 126:abea610beb85 238 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
AnnaBridge 126:abea610beb85 239 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
AnnaBridge 126:abea610beb85 240 } ADC_TypeDef;
AnnaBridge 126:abea610beb85 241
AnnaBridge 126:abea610beb85 242 typedef struct
AnnaBridge 126:abea610beb85 243 {
AnnaBridge 126:abea610beb85 244 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
AnnaBridge 126:abea610beb85 245 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
AnnaBridge 126:abea610beb85 246 __IO uint32_t CDR; /*!< ADC common regular data register for dual
AnnaBridge 126:abea610beb85 247 AND triple modes, Address offset: ADC1 base address + 0x308 */
AnnaBridge 126:abea610beb85 248 } ADC_Common_TypeDef;
AnnaBridge 126:abea610beb85 249
AnnaBridge 126:abea610beb85 250
AnnaBridge 126:abea610beb85 251 /**
AnnaBridge 126:abea610beb85 252 * @brief Controller Area Network TxMailBox
AnnaBridge 126:abea610beb85 253 */
AnnaBridge 126:abea610beb85 254
AnnaBridge 126:abea610beb85 255 typedef struct
AnnaBridge 126:abea610beb85 256 {
AnnaBridge 126:abea610beb85 257 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
AnnaBridge 126:abea610beb85 258 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
AnnaBridge 126:abea610beb85 259 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
AnnaBridge 126:abea610beb85 260 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
AnnaBridge 126:abea610beb85 261 } CAN_TxMailBox_TypeDef;
AnnaBridge 126:abea610beb85 262
AnnaBridge 126:abea610beb85 263 /**
AnnaBridge 126:abea610beb85 264 * @brief Controller Area Network FIFOMailBox
AnnaBridge 126:abea610beb85 265 */
AnnaBridge 126:abea610beb85 266
AnnaBridge 126:abea610beb85 267 typedef struct
AnnaBridge 126:abea610beb85 268 {
AnnaBridge 126:abea610beb85 269 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
AnnaBridge 126:abea610beb85 270 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
AnnaBridge 126:abea610beb85 271 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
AnnaBridge 126:abea610beb85 272 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
AnnaBridge 126:abea610beb85 273 } CAN_FIFOMailBox_TypeDef;
AnnaBridge 126:abea610beb85 274
AnnaBridge 126:abea610beb85 275 /**
AnnaBridge 126:abea610beb85 276 * @brief Controller Area Network FilterRegister
AnnaBridge 126:abea610beb85 277 */
AnnaBridge 126:abea610beb85 278
AnnaBridge 126:abea610beb85 279 typedef struct
AnnaBridge 126:abea610beb85 280 {
AnnaBridge 126:abea610beb85 281 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
AnnaBridge 126:abea610beb85 282 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
AnnaBridge 126:abea610beb85 283 } CAN_FilterRegister_TypeDef;
AnnaBridge 126:abea610beb85 284
AnnaBridge 126:abea610beb85 285 /**
AnnaBridge 126:abea610beb85 286 * @brief Controller Area Network
AnnaBridge 126:abea610beb85 287 */
AnnaBridge 126:abea610beb85 288
AnnaBridge 126:abea610beb85 289 typedef struct
AnnaBridge 126:abea610beb85 290 {
AnnaBridge 126:abea610beb85 291 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 292 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 293 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 294 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 295 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 296 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 297 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 298 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 299 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
AnnaBridge 126:abea610beb85 300 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
AnnaBridge 126:abea610beb85 301 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
AnnaBridge 126:abea610beb85 302 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
AnnaBridge 126:abea610beb85 303 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
AnnaBridge 126:abea610beb85 304 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
AnnaBridge 126:abea610beb85 305 uint32_t RESERVED2; /*!< Reserved, 0x208 */
AnnaBridge 126:abea610beb85 306 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
AnnaBridge 126:abea610beb85 307 uint32_t RESERVED3; /*!< Reserved, 0x210 */
AnnaBridge 126:abea610beb85 308 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
AnnaBridge 126:abea610beb85 309 uint32_t RESERVED4; /*!< Reserved, 0x218 */
AnnaBridge 126:abea610beb85 310 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
AnnaBridge 126:abea610beb85 311 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
AnnaBridge 126:abea610beb85 312 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
AnnaBridge 126:abea610beb85 313 } CAN_TypeDef;
AnnaBridge 126:abea610beb85 314
AnnaBridge 126:abea610beb85 315 /**
AnnaBridge 126:abea610beb85 316 * @brief HDMI-CEC
AnnaBridge 126:abea610beb85 317 */
AnnaBridge 126:abea610beb85 318
AnnaBridge 126:abea610beb85 319 typedef struct
AnnaBridge 126:abea610beb85 320 {
AnnaBridge 126:abea610beb85 321 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
AnnaBridge 126:abea610beb85 322 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
AnnaBridge 126:abea610beb85 323 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
AnnaBridge 126:abea610beb85 324 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
AnnaBridge 126:abea610beb85 325 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
AnnaBridge 126:abea610beb85 326 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
AnnaBridge 126:abea610beb85 327 }CEC_TypeDef;
AnnaBridge 126:abea610beb85 328
AnnaBridge 126:abea610beb85 329
AnnaBridge 126:abea610beb85 330 /**
AnnaBridge 126:abea610beb85 331 * @brief CRC calculation unit
AnnaBridge 126:abea610beb85 332 */
AnnaBridge 126:abea610beb85 333
AnnaBridge 126:abea610beb85 334 typedef struct
AnnaBridge 126:abea610beb85 335 {
AnnaBridge 126:abea610beb85 336 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 337 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 338 uint8_t RESERVED0; /*!< Reserved, 0x05 */
AnnaBridge 126:abea610beb85 339 uint16_t RESERVED1; /*!< Reserved, 0x06 */
AnnaBridge 126:abea610beb85 340 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 341 uint32_t RESERVED2; /*!< Reserved, 0x0C */
AnnaBridge 126:abea610beb85 342 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 343 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 344 } CRC_TypeDef;
AnnaBridge 126:abea610beb85 345
AnnaBridge 126:abea610beb85 346 /**
AnnaBridge 126:abea610beb85 347 * @brief Digital to Analog Converter
AnnaBridge 126:abea610beb85 348 */
AnnaBridge 126:abea610beb85 349
AnnaBridge 126:abea610beb85 350 typedef struct
AnnaBridge 126:abea610beb85 351 {
AnnaBridge 126:abea610beb85 352 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 353 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 354 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 355 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 356 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 357 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 358 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 359 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 360 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 361 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
AnnaBridge 126:abea610beb85 362 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
AnnaBridge 126:abea610beb85 363 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
AnnaBridge 126:abea610beb85 364 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
AnnaBridge 126:abea610beb85 365 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
AnnaBridge 126:abea610beb85 366 } DAC_TypeDef;
AnnaBridge 126:abea610beb85 367
AnnaBridge 126:abea610beb85 368 /**
AnnaBridge 126:abea610beb85 369 * @brief DFSDM module registers
AnnaBridge 126:abea610beb85 370 */
AnnaBridge 126:abea610beb85 371 typedef struct
AnnaBridge 126:abea610beb85 372 {
AnnaBridge 126:abea610beb85 373 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
AnnaBridge 126:abea610beb85 374 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
AnnaBridge 126:abea610beb85 375 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
AnnaBridge 126:abea610beb85 376 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
AnnaBridge 126:abea610beb85 377 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
AnnaBridge 126:abea610beb85 378 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
AnnaBridge 126:abea610beb85 379 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
AnnaBridge 126:abea610beb85 380 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
AnnaBridge 126:abea610beb85 381 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
AnnaBridge 126:abea610beb85 382 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
AnnaBridge 126:abea610beb85 383 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
AnnaBridge 126:abea610beb85 384 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
AnnaBridge 126:abea610beb85 385 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
AnnaBridge 126:abea610beb85 386 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
AnnaBridge 126:abea610beb85 387 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
AnnaBridge 126:abea610beb85 388 } DFSDM_Filter_TypeDef;
AnnaBridge 126:abea610beb85 389
AnnaBridge 126:abea610beb85 390 /**
AnnaBridge 126:abea610beb85 391 * @brief DFSDM channel configuration registers
AnnaBridge 126:abea610beb85 392 */
AnnaBridge 126:abea610beb85 393 typedef struct
AnnaBridge 126:abea610beb85 394 {
AnnaBridge 126:abea610beb85 395 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 396 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 397 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
AnnaBridge 126:abea610beb85 398 short circuit detector register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 399 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 400 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 401 } DFSDM_Channel_TypeDef;
AnnaBridge 126:abea610beb85 402
AnnaBridge 126:abea610beb85 403 /**
AnnaBridge 126:abea610beb85 404 * @brief Debug MCU
AnnaBridge 126:abea610beb85 405 */
AnnaBridge 126:abea610beb85 406
AnnaBridge 126:abea610beb85 407 typedef struct
AnnaBridge 126:abea610beb85 408 {
AnnaBridge 126:abea610beb85 409 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 410 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 411 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 412 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 413 }DBGMCU_TypeDef;
AnnaBridge 126:abea610beb85 414
AnnaBridge 126:abea610beb85 415 /**
AnnaBridge 126:abea610beb85 416 * @brief DCMI
AnnaBridge 126:abea610beb85 417 */
AnnaBridge 126:abea610beb85 418
AnnaBridge 126:abea610beb85 419 typedef struct
AnnaBridge 126:abea610beb85 420 {
AnnaBridge 126:abea610beb85 421 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 422 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 423 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 424 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 425 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 426 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 427 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 428 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 429 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 430 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
AnnaBridge 126:abea610beb85 431 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
AnnaBridge 126:abea610beb85 432 } DCMI_TypeDef;
AnnaBridge 126:abea610beb85 433
AnnaBridge 126:abea610beb85 434 /**
AnnaBridge 126:abea610beb85 435 * @brief DMA Controller
AnnaBridge 126:abea610beb85 436 */
AnnaBridge 126:abea610beb85 437
AnnaBridge 126:abea610beb85 438 typedef struct
AnnaBridge 126:abea610beb85 439 {
AnnaBridge 126:abea610beb85 440 __IO uint32_t CR; /*!< DMA stream x configuration register */
AnnaBridge 126:abea610beb85 441 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
AnnaBridge 126:abea610beb85 442 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
AnnaBridge 126:abea610beb85 443 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
AnnaBridge 126:abea610beb85 444 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
AnnaBridge 126:abea610beb85 445 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
AnnaBridge 126:abea610beb85 446 } DMA_Stream_TypeDef;
AnnaBridge 126:abea610beb85 447
AnnaBridge 126:abea610beb85 448 typedef struct
AnnaBridge 126:abea610beb85 449 {
AnnaBridge 126:abea610beb85 450 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 451 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 452 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 453 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 454 } DMA_TypeDef;
AnnaBridge 126:abea610beb85 455
AnnaBridge 126:abea610beb85 456
AnnaBridge 126:abea610beb85 457 /**
AnnaBridge 126:abea610beb85 458 * @brief DMA2D Controller
AnnaBridge 126:abea610beb85 459 */
AnnaBridge 126:abea610beb85 460
AnnaBridge 126:abea610beb85 461 typedef struct
AnnaBridge 126:abea610beb85 462 {
AnnaBridge 126:abea610beb85 463 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 464 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 465 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 466 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 467 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 468 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 469 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 470 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 471 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 472 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
AnnaBridge 126:abea610beb85 473 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
AnnaBridge 126:abea610beb85 474 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
AnnaBridge 126:abea610beb85 475 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
AnnaBridge 126:abea610beb85 476 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
AnnaBridge 126:abea610beb85 477 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
AnnaBridge 126:abea610beb85 478 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
AnnaBridge 126:abea610beb85 479 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
AnnaBridge 126:abea610beb85 480 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
AnnaBridge 126:abea610beb85 481 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
AnnaBridge 126:abea610beb85 482 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
AnnaBridge 126:abea610beb85 483 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
AnnaBridge 126:abea610beb85 484 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
AnnaBridge 126:abea610beb85 485 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
AnnaBridge 126:abea610beb85 486 } DMA2D_TypeDef;
AnnaBridge 126:abea610beb85 487
AnnaBridge 126:abea610beb85 488
AnnaBridge 126:abea610beb85 489 /**
AnnaBridge 126:abea610beb85 490 * @brief Ethernet MAC
AnnaBridge 126:abea610beb85 491 */
AnnaBridge 126:abea610beb85 492
AnnaBridge 126:abea610beb85 493 typedef struct
AnnaBridge 126:abea610beb85 494 {
AnnaBridge 126:abea610beb85 495 __IO uint32_t MACCR;
AnnaBridge 126:abea610beb85 496 __IO uint32_t MACFFR;
AnnaBridge 126:abea610beb85 497 __IO uint32_t MACHTHR;
AnnaBridge 126:abea610beb85 498 __IO uint32_t MACHTLR;
AnnaBridge 126:abea610beb85 499 __IO uint32_t MACMIIAR;
AnnaBridge 126:abea610beb85 500 __IO uint32_t MACMIIDR;
AnnaBridge 126:abea610beb85 501 __IO uint32_t MACFCR;
AnnaBridge 126:abea610beb85 502 __IO uint32_t MACVLANTR; /* 8 */
AnnaBridge 126:abea610beb85 503 uint32_t RESERVED0[2];
AnnaBridge 126:abea610beb85 504 __IO uint32_t MACRWUFFR; /* 11 */
AnnaBridge 126:abea610beb85 505 __IO uint32_t MACPMTCSR;
AnnaBridge 126:abea610beb85 506 uint32_t RESERVED1[2];
AnnaBridge 126:abea610beb85 507 __IO uint32_t MACSR; /* 15 */
AnnaBridge 126:abea610beb85 508 __IO uint32_t MACIMR;
AnnaBridge 126:abea610beb85 509 __IO uint32_t MACA0HR;
AnnaBridge 126:abea610beb85 510 __IO uint32_t MACA0LR;
AnnaBridge 126:abea610beb85 511 __IO uint32_t MACA1HR;
AnnaBridge 126:abea610beb85 512 __IO uint32_t MACA1LR;
AnnaBridge 126:abea610beb85 513 __IO uint32_t MACA2HR;
AnnaBridge 126:abea610beb85 514 __IO uint32_t MACA2LR;
AnnaBridge 126:abea610beb85 515 __IO uint32_t MACA3HR;
AnnaBridge 126:abea610beb85 516 __IO uint32_t MACA3LR; /* 24 */
AnnaBridge 126:abea610beb85 517 uint32_t RESERVED2[40];
AnnaBridge 126:abea610beb85 518 __IO uint32_t MMCCR; /* 65 */
AnnaBridge 126:abea610beb85 519 __IO uint32_t MMCRIR;
AnnaBridge 126:abea610beb85 520 __IO uint32_t MMCTIR;
AnnaBridge 126:abea610beb85 521 __IO uint32_t MMCRIMR;
AnnaBridge 126:abea610beb85 522 __IO uint32_t MMCTIMR; /* 69 */
AnnaBridge 126:abea610beb85 523 uint32_t RESERVED3[14];
AnnaBridge 126:abea610beb85 524 __IO uint32_t MMCTGFSCCR; /* 84 */
AnnaBridge 126:abea610beb85 525 __IO uint32_t MMCTGFMSCCR;
AnnaBridge 126:abea610beb85 526 uint32_t RESERVED4[5];
AnnaBridge 126:abea610beb85 527 __IO uint32_t MMCTGFCR;
AnnaBridge 126:abea610beb85 528 uint32_t RESERVED5[10];
AnnaBridge 126:abea610beb85 529 __IO uint32_t MMCRFCECR;
AnnaBridge 126:abea610beb85 530 __IO uint32_t MMCRFAECR;
AnnaBridge 126:abea610beb85 531 uint32_t RESERVED6[10];
AnnaBridge 126:abea610beb85 532 __IO uint32_t MMCRGUFCR;
AnnaBridge 126:abea610beb85 533 uint32_t RESERVED7[334];
AnnaBridge 126:abea610beb85 534 __IO uint32_t PTPTSCR;
AnnaBridge 126:abea610beb85 535 __IO uint32_t PTPSSIR;
AnnaBridge 126:abea610beb85 536 __IO uint32_t PTPTSHR;
AnnaBridge 126:abea610beb85 537 __IO uint32_t PTPTSLR;
AnnaBridge 126:abea610beb85 538 __IO uint32_t PTPTSHUR;
AnnaBridge 126:abea610beb85 539 __IO uint32_t PTPTSLUR;
AnnaBridge 126:abea610beb85 540 __IO uint32_t PTPTSAR;
AnnaBridge 126:abea610beb85 541 __IO uint32_t PTPTTHR;
AnnaBridge 126:abea610beb85 542 __IO uint32_t PTPTTLR;
AnnaBridge 126:abea610beb85 543 __IO uint32_t RESERVED8;
AnnaBridge 126:abea610beb85 544 __IO uint32_t PTPTSSR;
AnnaBridge 126:abea610beb85 545 uint32_t RESERVED9[565];
AnnaBridge 126:abea610beb85 546 __IO uint32_t DMABMR;
AnnaBridge 126:abea610beb85 547 __IO uint32_t DMATPDR;
AnnaBridge 126:abea610beb85 548 __IO uint32_t DMARPDR;
AnnaBridge 126:abea610beb85 549 __IO uint32_t DMARDLAR;
AnnaBridge 126:abea610beb85 550 __IO uint32_t DMATDLAR;
AnnaBridge 126:abea610beb85 551 __IO uint32_t DMASR;
AnnaBridge 126:abea610beb85 552 __IO uint32_t DMAOMR;
AnnaBridge 126:abea610beb85 553 __IO uint32_t DMAIER;
AnnaBridge 126:abea610beb85 554 __IO uint32_t DMAMFBOCR;
AnnaBridge 126:abea610beb85 555 __IO uint32_t DMARSWTR;
AnnaBridge 126:abea610beb85 556 uint32_t RESERVED10[8];
AnnaBridge 126:abea610beb85 557 __IO uint32_t DMACHTDR;
AnnaBridge 126:abea610beb85 558 __IO uint32_t DMACHRDR;
AnnaBridge 126:abea610beb85 559 __IO uint32_t DMACHTBAR;
AnnaBridge 126:abea610beb85 560 __IO uint32_t DMACHRBAR;
AnnaBridge 126:abea610beb85 561 } ETH_TypeDef;
AnnaBridge 126:abea610beb85 562
AnnaBridge 126:abea610beb85 563 /**
AnnaBridge 126:abea610beb85 564 * @brief External Interrupt/Event Controller
AnnaBridge 126:abea610beb85 565 */
AnnaBridge 126:abea610beb85 566
AnnaBridge 126:abea610beb85 567 typedef struct
AnnaBridge 126:abea610beb85 568 {
AnnaBridge 126:abea610beb85 569 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 570 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 571 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 572 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 573 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 574 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 575 } EXTI_TypeDef;
AnnaBridge 126:abea610beb85 576
AnnaBridge 126:abea610beb85 577 /**
AnnaBridge 126:abea610beb85 578 * @brief FLASH Registers
AnnaBridge 126:abea610beb85 579 */
AnnaBridge 126:abea610beb85 580
AnnaBridge 126:abea610beb85 581 typedef struct
AnnaBridge 126:abea610beb85 582 {
AnnaBridge 126:abea610beb85 583 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 584 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 585 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 586 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 587 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 588 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
AnnaBridge 126:abea610beb85 589 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
AnnaBridge 126:abea610beb85 590 } FLASH_TypeDef;
AnnaBridge 126:abea610beb85 591
AnnaBridge 126:abea610beb85 592
AnnaBridge 126:abea610beb85 593
AnnaBridge 126:abea610beb85 594 /**
AnnaBridge 126:abea610beb85 595 * @brief Flexible Memory Controller
AnnaBridge 126:abea610beb85 596 */
AnnaBridge 126:abea610beb85 597
AnnaBridge 126:abea610beb85 598 typedef struct
AnnaBridge 126:abea610beb85 599 {
AnnaBridge 126:abea610beb85 600 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
AnnaBridge 126:abea610beb85 601 } FMC_Bank1_TypeDef;
AnnaBridge 126:abea610beb85 602
AnnaBridge 126:abea610beb85 603 /**
AnnaBridge 126:abea610beb85 604 * @brief Flexible Memory Controller Bank1E
AnnaBridge 126:abea610beb85 605 */
AnnaBridge 126:abea610beb85 606
AnnaBridge 126:abea610beb85 607 typedef struct
AnnaBridge 126:abea610beb85 608 {
AnnaBridge 126:abea610beb85 609 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
AnnaBridge 126:abea610beb85 610 } FMC_Bank1E_TypeDef;
AnnaBridge 126:abea610beb85 611
AnnaBridge 126:abea610beb85 612 /**
AnnaBridge 126:abea610beb85 613 * @brief Flexible Memory Controller Bank3
AnnaBridge 126:abea610beb85 614 */
AnnaBridge 126:abea610beb85 615
AnnaBridge 126:abea610beb85 616 typedef struct
AnnaBridge 126:abea610beb85 617 {
AnnaBridge 126:abea610beb85 618 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
AnnaBridge 126:abea610beb85 619 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
AnnaBridge 126:abea610beb85 620 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
AnnaBridge 126:abea610beb85 621 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
AnnaBridge 126:abea610beb85 622 uint32_t RESERVED0; /*!< Reserved, 0x90 */
AnnaBridge 126:abea610beb85 623 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
AnnaBridge 126:abea610beb85 624 } FMC_Bank3_TypeDef;
AnnaBridge 126:abea610beb85 625
AnnaBridge 126:abea610beb85 626 /**
AnnaBridge 126:abea610beb85 627 * @brief Flexible Memory Controller Bank5_6
AnnaBridge 126:abea610beb85 628 */
AnnaBridge 126:abea610beb85 629
AnnaBridge 126:abea610beb85 630 typedef struct
AnnaBridge 126:abea610beb85 631 {
AnnaBridge 126:abea610beb85 632 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
AnnaBridge 126:abea610beb85 633 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
AnnaBridge 126:abea610beb85 634 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
AnnaBridge 126:abea610beb85 635 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
AnnaBridge 126:abea610beb85 636 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
AnnaBridge 126:abea610beb85 637 } FMC_Bank5_6_TypeDef;
AnnaBridge 126:abea610beb85 638
AnnaBridge 126:abea610beb85 639
AnnaBridge 126:abea610beb85 640 /**
AnnaBridge 126:abea610beb85 641 * @brief General Purpose I/O
AnnaBridge 126:abea610beb85 642 */
AnnaBridge 126:abea610beb85 643
AnnaBridge 126:abea610beb85 644 typedef struct
AnnaBridge 126:abea610beb85 645 {
AnnaBridge 126:abea610beb85 646 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 647 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 648 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 649 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 650 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 651 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 652 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 653 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 654 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
AnnaBridge 126:abea610beb85 655 } GPIO_TypeDef;
AnnaBridge 126:abea610beb85 656
AnnaBridge 126:abea610beb85 657 /**
AnnaBridge 126:abea610beb85 658 * @brief System configuration controller
AnnaBridge 126:abea610beb85 659 */
AnnaBridge 126:abea610beb85 660
AnnaBridge 126:abea610beb85 661 typedef struct
AnnaBridge 126:abea610beb85 662 {
AnnaBridge 126:abea610beb85 663 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 664 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 665 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
AnnaBridge 126:abea610beb85 666 uint32_t RESERVED; /*!< Reserved, 0x18 */
AnnaBridge 126:abea610beb85 667 __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 668 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 669 } SYSCFG_TypeDef;
AnnaBridge 126:abea610beb85 670
AnnaBridge 126:abea610beb85 671 /**
AnnaBridge 126:abea610beb85 672 * @brief Inter-integrated Circuit Interface
AnnaBridge 126:abea610beb85 673 */
AnnaBridge 126:abea610beb85 674
AnnaBridge 126:abea610beb85 675 typedef struct
AnnaBridge 126:abea610beb85 676 {
AnnaBridge 126:abea610beb85 677 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 678 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 679 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 680 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 681 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 682 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 683 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 684 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 685 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 686 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
AnnaBridge 126:abea610beb85 687 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
AnnaBridge 126:abea610beb85 688 } I2C_TypeDef;
AnnaBridge 126:abea610beb85 689
AnnaBridge 126:abea610beb85 690 /**
AnnaBridge 126:abea610beb85 691 * @brief Independent WATCHDOG
AnnaBridge 126:abea610beb85 692 */
AnnaBridge 126:abea610beb85 693
AnnaBridge 126:abea610beb85 694 typedef struct
AnnaBridge 126:abea610beb85 695 {
AnnaBridge 126:abea610beb85 696 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 697 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 698 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 699 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 700 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 701 } IWDG_TypeDef;
AnnaBridge 126:abea610beb85 702
AnnaBridge 126:abea610beb85 703
AnnaBridge 126:abea610beb85 704 /**
AnnaBridge 126:abea610beb85 705 * @brief LCD-TFT Display Controller
AnnaBridge 126:abea610beb85 706 */
AnnaBridge 126:abea610beb85 707
AnnaBridge 126:abea610beb85 708 typedef struct
AnnaBridge 126:abea610beb85 709 {
AnnaBridge 126:abea610beb85 710 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
AnnaBridge 126:abea610beb85 711 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 712 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 713 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 714 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 715 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 716 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
AnnaBridge 126:abea610beb85 717 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
AnnaBridge 126:abea610beb85 718 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
AnnaBridge 126:abea610beb85 719 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
AnnaBridge 126:abea610beb85 720 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
AnnaBridge 126:abea610beb85 721 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
AnnaBridge 126:abea610beb85 722 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
AnnaBridge 126:abea610beb85 723 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
AnnaBridge 126:abea610beb85 724 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
AnnaBridge 126:abea610beb85 725 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
AnnaBridge 126:abea610beb85 726 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
AnnaBridge 126:abea610beb85 727 } LTDC_TypeDef;
AnnaBridge 126:abea610beb85 728
AnnaBridge 126:abea610beb85 729 /**
AnnaBridge 126:abea610beb85 730 * @brief LCD-TFT Display layer x Controller
AnnaBridge 126:abea610beb85 731 */
AnnaBridge 126:abea610beb85 732
AnnaBridge 126:abea610beb85 733 typedef struct
AnnaBridge 126:abea610beb85 734 {
AnnaBridge 126:abea610beb85 735 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
AnnaBridge 126:abea610beb85 736 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
AnnaBridge 126:abea610beb85 737 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
AnnaBridge 126:abea610beb85 738 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
AnnaBridge 126:abea610beb85 739 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
AnnaBridge 126:abea610beb85 740 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
AnnaBridge 126:abea610beb85 741 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
AnnaBridge 126:abea610beb85 742 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
AnnaBridge 126:abea610beb85 743 uint32_t RESERVED0[2]; /*!< Reserved */
AnnaBridge 126:abea610beb85 744 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
AnnaBridge 126:abea610beb85 745 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
AnnaBridge 126:abea610beb85 746 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
AnnaBridge 126:abea610beb85 747 uint32_t RESERVED1[3]; /*!< Reserved */
AnnaBridge 126:abea610beb85 748 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
AnnaBridge 126:abea610beb85 749
AnnaBridge 126:abea610beb85 750 } LTDC_Layer_TypeDef;
AnnaBridge 126:abea610beb85 751
AnnaBridge 126:abea610beb85 752 /**
AnnaBridge 126:abea610beb85 753 * @brief Power Control
AnnaBridge 126:abea610beb85 754 */
AnnaBridge 126:abea610beb85 755
AnnaBridge 126:abea610beb85 756 typedef struct
AnnaBridge 126:abea610beb85 757 {
AnnaBridge 126:abea610beb85 758 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 759 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 760 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 761 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 762 } PWR_TypeDef;
AnnaBridge 126:abea610beb85 763
AnnaBridge 126:abea610beb85 764
AnnaBridge 126:abea610beb85 765 /**
AnnaBridge 126:abea610beb85 766 * @brief Reset and Clock Control
AnnaBridge 126:abea610beb85 767 */
AnnaBridge 126:abea610beb85 768
AnnaBridge 126:abea610beb85 769 typedef struct
AnnaBridge 126:abea610beb85 770 {
AnnaBridge 126:abea610beb85 771 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 772 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 773 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 774 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 775 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 776 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 777 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 778 uint32_t RESERVED0; /*!< Reserved, 0x1C */
AnnaBridge 126:abea610beb85 779 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 780 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
AnnaBridge 126:abea610beb85 781 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
AnnaBridge 126:abea610beb85 782 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
AnnaBridge 126:abea610beb85 783 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
AnnaBridge 126:abea610beb85 784 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
AnnaBridge 126:abea610beb85 785 uint32_t RESERVED2; /*!< Reserved, 0x3C */
AnnaBridge 126:abea610beb85 786 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
AnnaBridge 126:abea610beb85 787 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
AnnaBridge 126:abea610beb85 788 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
AnnaBridge 126:abea610beb85 789 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
AnnaBridge 126:abea610beb85 790 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
AnnaBridge 126:abea610beb85 791 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
AnnaBridge 126:abea610beb85 792 uint32_t RESERVED4; /*!< Reserved, 0x5C */
AnnaBridge 126:abea610beb85 793 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
AnnaBridge 126:abea610beb85 794 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
AnnaBridge 126:abea610beb85 795 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
AnnaBridge 126:abea610beb85 796 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
AnnaBridge 126:abea610beb85 797 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
AnnaBridge 126:abea610beb85 798 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
AnnaBridge 126:abea610beb85 799 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
AnnaBridge 126:abea610beb85 800 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
AnnaBridge 126:abea610beb85 801 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
AnnaBridge 126:abea610beb85 802 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
AnnaBridge 126:abea610beb85 803 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
AnnaBridge 126:abea610beb85 804
AnnaBridge 126:abea610beb85 805 } RCC_TypeDef;
AnnaBridge 126:abea610beb85 806
AnnaBridge 126:abea610beb85 807 /**
AnnaBridge 126:abea610beb85 808 * @brief Real-Time Clock
AnnaBridge 126:abea610beb85 809 */
AnnaBridge 126:abea610beb85 810
AnnaBridge 126:abea610beb85 811 typedef struct
AnnaBridge 126:abea610beb85 812 {
AnnaBridge 126:abea610beb85 813 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 814 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 815 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 816 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 817 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 818 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 819 uint32_t reserved; /*!< Reserved */
AnnaBridge 126:abea610beb85 820 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 821 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 822 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
AnnaBridge 126:abea610beb85 823 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
AnnaBridge 126:abea610beb85 824 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
AnnaBridge 126:abea610beb85 825 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
AnnaBridge 126:abea610beb85 826 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
AnnaBridge 126:abea610beb85 827 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
AnnaBridge 126:abea610beb85 828 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
AnnaBridge 126:abea610beb85 829 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
AnnaBridge 126:abea610beb85 830 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
AnnaBridge 126:abea610beb85 831 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
AnnaBridge 126:abea610beb85 832 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
AnnaBridge 126:abea610beb85 833 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
AnnaBridge 126:abea610beb85 834 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
AnnaBridge 126:abea610beb85 835 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
AnnaBridge 126:abea610beb85 836 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
AnnaBridge 126:abea610beb85 837 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
AnnaBridge 126:abea610beb85 838 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
AnnaBridge 126:abea610beb85 839 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
AnnaBridge 126:abea610beb85 840 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
AnnaBridge 126:abea610beb85 841 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
AnnaBridge 126:abea610beb85 842 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
AnnaBridge 126:abea610beb85 843 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
AnnaBridge 126:abea610beb85 844 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
AnnaBridge 126:abea610beb85 845 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
AnnaBridge 126:abea610beb85 846 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
AnnaBridge 126:abea610beb85 847 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
AnnaBridge 126:abea610beb85 848 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
AnnaBridge 126:abea610beb85 849 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
AnnaBridge 126:abea610beb85 850 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
AnnaBridge 126:abea610beb85 851 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
AnnaBridge 126:abea610beb85 852 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
AnnaBridge 126:abea610beb85 853 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
AnnaBridge 126:abea610beb85 854 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
AnnaBridge 126:abea610beb85 855 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
AnnaBridge 126:abea610beb85 856 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
AnnaBridge 126:abea610beb85 857 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
AnnaBridge 126:abea610beb85 858 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
AnnaBridge 126:abea610beb85 859 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
AnnaBridge 126:abea610beb85 860 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
AnnaBridge 126:abea610beb85 861 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
AnnaBridge 126:abea610beb85 862 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
AnnaBridge 126:abea610beb85 863 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
AnnaBridge 126:abea610beb85 864 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
AnnaBridge 126:abea610beb85 865 } RTC_TypeDef;
AnnaBridge 126:abea610beb85 866
AnnaBridge 126:abea610beb85 867
AnnaBridge 126:abea610beb85 868 /**
AnnaBridge 126:abea610beb85 869 * @brief Serial Audio Interface
AnnaBridge 126:abea610beb85 870 */
AnnaBridge 126:abea610beb85 871
AnnaBridge 126:abea610beb85 872 typedef struct
AnnaBridge 126:abea610beb85 873 {
AnnaBridge 126:abea610beb85 874 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 875 } SAI_TypeDef;
AnnaBridge 126:abea610beb85 876
AnnaBridge 126:abea610beb85 877 typedef struct
AnnaBridge 126:abea610beb85 878 {
AnnaBridge 126:abea610beb85 879 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 880 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 881 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 882 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 883 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 884 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 885 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 886 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 887 } SAI_Block_TypeDef;
AnnaBridge 126:abea610beb85 888
AnnaBridge 126:abea610beb85 889 /**
AnnaBridge 126:abea610beb85 890 * @brief SPDIF-RX Interface
AnnaBridge 126:abea610beb85 891 */
AnnaBridge 126:abea610beb85 892
AnnaBridge 126:abea610beb85 893 typedef struct
AnnaBridge 126:abea610beb85 894 {
AnnaBridge 126:abea610beb85 895 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 896 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 897 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 898 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 899 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 900 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 901 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 902 } SPDIFRX_TypeDef;
AnnaBridge 126:abea610beb85 903
AnnaBridge 126:abea610beb85 904
AnnaBridge 126:abea610beb85 905 /**
AnnaBridge 126:abea610beb85 906 * @brief SD host Interface
AnnaBridge 126:abea610beb85 907 */
AnnaBridge 126:abea610beb85 908
AnnaBridge 126:abea610beb85 909 typedef struct
AnnaBridge 126:abea610beb85 910 {
AnnaBridge 126:abea610beb85 911 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 912 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 913 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 914 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 915 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 916 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 917 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 918 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 919 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 920 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
AnnaBridge 126:abea610beb85 921 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
AnnaBridge 126:abea610beb85 922 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
AnnaBridge 126:abea610beb85 923 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
AnnaBridge 126:abea610beb85 924 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
AnnaBridge 126:abea610beb85 925 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
AnnaBridge 126:abea610beb85 926 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
AnnaBridge 126:abea610beb85 927 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
AnnaBridge 126:abea610beb85 928 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
AnnaBridge 126:abea610beb85 929 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
AnnaBridge 126:abea610beb85 930 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
AnnaBridge 126:abea610beb85 931 } SDMMC_TypeDef;
AnnaBridge 126:abea610beb85 932
AnnaBridge 126:abea610beb85 933 /**
AnnaBridge 126:abea610beb85 934 * @brief Serial Peripheral Interface
AnnaBridge 126:abea610beb85 935 */
AnnaBridge 126:abea610beb85 936
AnnaBridge 126:abea610beb85 937 typedef struct
AnnaBridge 126:abea610beb85 938 {
AnnaBridge 126:abea610beb85 939 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
AnnaBridge 126:abea610beb85 940 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 941 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 942 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 943 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
AnnaBridge 126:abea610beb85 944 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
AnnaBridge 126:abea610beb85 945 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
AnnaBridge 126:abea610beb85 946 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 947 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 948 } SPI_TypeDef;
AnnaBridge 126:abea610beb85 949
AnnaBridge 126:abea610beb85 950 /**
AnnaBridge 126:abea610beb85 951 * @brief QUAD Serial Peripheral Interface
AnnaBridge 126:abea610beb85 952 */
AnnaBridge 126:abea610beb85 953
AnnaBridge 126:abea610beb85 954 typedef struct
AnnaBridge 126:abea610beb85 955 {
AnnaBridge 126:abea610beb85 956 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 957 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 958 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 959 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 960 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 961 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 962 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 963 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 964 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 965 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
AnnaBridge 126:abea610beb85 966 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
AnnaBridge 126:abea610beb85 967 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
AnnaBridge 126:abea610beb85 968 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
AnnaBridge 126:abea610beb85 969 } QUADSPI_TypeDef;
AnnaBridge 126:abea610beb85 970
AnnaBridge 126:abea610beb85 971 /**
AnnaBridge 126:abea610beb85 972 * @brief TIM
AnnaBridge 126:abea610beb85 973 */
AnnaBridge 126:abea610beb85 974
AnnaBridge 126:abea610beb85 975 typedef struct
AnnaBridge 126:abea610beb85 976 {
AnnaBridge 126:abea610beb85 977 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 978 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 979 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 980 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 981 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 982 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 983 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 984 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 985 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 986 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
AnnaBridge 126:abea610beb85 987 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
AnnaBridge 126:abea610beb85 988 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
AnnaBridge 126:abea610beb85 989 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
AnnaBridge 126:abea610beb85 990 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
AnnaBridge 126:abea610beb85 991 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
AnnaBridge 126:abea610beb85 992 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
AnnaBridge 126:abea610beb85 993 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
AnnaBridge 126:abea610beb85 994 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
AnnaBridge 126:abea610beb85 995 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
AnnaBridge 126:abea610beb85 996 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
AnnaBridge 126:abea610beb85 997 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
AnnaBridge 126:abea610beb85 998 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
AnnaBridge 126:abea610beb85 999 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
AnnaBridge 126:abea610beb85 1000 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
AnnaBridge 126:abea610beb85 1001 __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */
AnnaBridge 126:abea610beb85 1002 __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */
AnnaBridge 126:abea610beb85 1003
AnnaBridge 126:abea610beb85 1004 } TIM_TypeDef;
AnnaBridge 126:abea610beb85 1005
AnnaBridge 126:abea610beb85 1006 /**
AnnaBridge 126:abea610beb85 1007 * @brief LPTIMIMER
AnnaBridge 126:abea610beb85 1008 */
AnnaBridge 126:abea610beb85 1009 typedef struct
AnnaBridge 126:abea610beb85 1010 {
AnnaBridge 126:abea610beb85 1011 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 1012 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 1013 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 1014 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 1015 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 1016 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 1017 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 1018 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 1019 } LPTIM_TypeDef;
AnnaBridge 126:abea610beb85 1020
AnnaBridge 126:abea610beb85 1021
AnnaBridge 126:abea610beb85 1022 /**
AnnaBridge 126:abea610beb85 1023 * @brief Universal Synchronous Asynchronous Receiver Transmitter
AnnaBridge 126:abea610beb85 1024 */
AnnaBridge 126:abea610beb85 1025
AnnaBridge 126:abea610beb85 1026 typedef struct
AnnaBridge 126:abea610beb85 1027 {
AnnaBridge 126:abea610beb85 1028 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 1029 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 1030 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 1031 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 1032 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 1033 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 1034 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 1035 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
AnnaBridge 126:abea610beb85 1036 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
AnnaBridge 126:abea610beb85 1037 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
AnnaBridge 126:abea610beb85 1038 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
AnnaBridge 126:abea610beb85 1039 } USART_TypeDef;
AnnaBridge 126:abea610beb85 1040
AnnaBridge 126:abea610beb85 1041
AnnaBridge 126:abea610beb85 1042 /**
AnnaBridge 126:abea610beb85 1043 * @brief Window WATCHDOG
AnnaBridge 126:abea610beb85 1044 */
AnnaBridge 126:abea610beb85 1045
AnnaBridge 126:abea610beb85 1046 typedef struct
AnnaBridge 126:abea610beb85 1047 {
AnnaBridge 126:abea610beb85 1048 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 1049 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 1050 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 1051 } WWDG_TypeDef;
AnnaBridge 126:abea610beb85 1052
AnnaBridge 126:abea610beb85 1053
AnnaBridge 126:abea610beb85 1054 /**
AnnaBridge 126:abea610beb85 1055 * @brief RNG
AnnaBridge 126:abea610beb85 1056 */
AnnaBridge 126:abea610beb85 1057
AnnaBridge 126:abea610beb85 1058 typedef struct
AnnaBridge 126:abea610beb85 1059 {
AnnaBridge 126:abea610beb85 1060 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 1061 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 1062 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 1063 } RNG_TypeDef;
AnnaBridge 126:abea610beb85 1064
AnnaBridge 126:abea610beb85 1065 /**
AnnaBridge 126:abea610beb85 1066 * @}
AnnaBridge 126:abea610beb85 1067 */
AnnaBridge 126:abea610beb85 1068
AnnaBridge 126:abea610beb85 1069 /**
AnnaBridge 126:abea610beb85 1070 * @brief USB_OTG_Core_Registers
AnnaBridge 126:abea610beb85 1071 */
AnnaBridge 126:abea610beb85 1072 typedef struct
AnnaBridge 126:abea610beb85 1073 {
AnnaBridge 126:abea610beb85 1074 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
AnnaBridge 126:abea610beb85 1075 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
AnnaBridge 126:abea610beb85 1076 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
AnnaBridge 126:abea610beb85 1077 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
AnnaBridge 126:abea610beb85 1078 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
AnnaBridge 126:abea610beb85 1079 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
AnnaBridge 126:abea610beb85 1080 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
AnnaBridge 126:abea610beb85 1081 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
AnnaBridge 126:abea610beb85 1082 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
AnnaBridge 126:abea610beb85 1083 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
AnnaBridge 126:abea610beb85 1084 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
AnnaBridge 126:abea610beb85 1085 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
AnnaBridge 126:abea610beb85 1086 uint32_t Reserved30[2]; /*!< Reserved 030h */
AnnaBridge 126:abea610beb85 1087 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
AnnaBridge 126:abea610beb85 1088 __IO uint32_t CID; /*!< User ID Register 03Ch */
AnnaBridge 126:abea610beb85 1089 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
AnnaBridge 126:abea610beb85 1090 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
AnnaBridge 126:abea610beb85 1091 uint32_t Reserved6; /*!< Reserved 050h */
AnnaBridge 126:abea610beb85 1092 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
AnnaBridge 126:abea610beb85 1093 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
AnnaBridge 126:abea610beb85 1094 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
AnnaBridge 126:abea610beb85 1095 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
AnnaBridge 126:abea610beb85 1096 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
AnnaBridge 126:abea610beb85 1097 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
AnnaBridge 126:abea610beb85 1098 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
AnnaBridge 126:abea610beb85 1099 } USB_OTG_GlobalTypeDef;
AnnaBridge 126:abea610beb85 1100
AnnaBridge 126:abea610beb85 1101
AnnaBridge 126:abea610beb85 1102 /**
AnnaBridge 126:abea610beb85 1103 * @brief USB_OTG_device_Registers
AnnaBridge 126:abea610beb85 1104 */
AnnaBridge 126:abea610beb85 1105 typedef struct
AnnaBridge 126:abea610beb85 1106 {
AnnaBridge 126:abea610beb85 1107 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
AnnaBridge 126:abea610beb85 1108 __IO uint32_t DCTL; /*!< dev Control Register 804h */
AnnaBridge 126:abea610beb85 1109 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
AnnaBridge 126:abea610beb85 1110 uint32_t Reserved0C; /*!< Reserved 80Ch */
AnnaBridge 126:abea610beb85 1111 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
AnnaBridge 126:abea610beb85 1112 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
AnnaBridge 126:abea610beb85 1113 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
AnnaBridge 126:abea610beb85 1114 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
AnnaBridge 126:abea610beb85 1115 uint32_t Reserved20; /*!< Reserved 820h */
AnnaBridge 126:abea610beb85 1116 uint32_t Reserved9; /*!< Reserved 824h */
AnnaBridge 126:abea610beb85 1117 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
AnnaBridge 126:abea610beb85 1118 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
AnnaBridge 126:abea610beb85 1119 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
AnnaBridge 126:abea610beb85 1120 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
AnnaBridge 126:abea610beb85 1121 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
AnnaBridge 126:abea610beb85 1122 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
AnnaBridge 126:abea610beb85 1123 uint32_t Reserved40; /*!< dedicated EP mask 840h */
AnnaBridge 126:abea610beb85 1124 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
AnnaBridge 126:abea610beb85 1125 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
AnnaBridge 126:abea610beb85 1126 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
AnnaBridge 126:abea610beb85 1127 } USB_OTG_DeviceTypeDef;
AnnaBridge 126:abea610beb85 1128
AnnaBridge 126:abea610beb85 1129
AnnaBridge 126:abea610beb85 1130 /**
AnnaBridge 126:abea610beb85 1131 * @brief USB_OTG_IN_Endpoint-Specific_Register
AnnaBridge 126:abea610beb85 1132 */
AnnaBridge 126:abea610beb85 1133 typedef struct
AnnaBridge 126:abea610beb85 1134 {
AnnaBridge 126:abea610beb85 1135 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
AnnaBridge 126:abea610beb85 1136 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
AnnaBridge 126:abea610beb85 1137 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
AnnaBridge 126:abea610beb85 1138 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
AnnaBridge 126:abea610beb85 1139 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
AnnaBridge 126:abea610beb85 1140 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
AnnaBridge 126:abea610beb85 1141 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
AnnaBridge 126:abea610beb85 1142 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
AnnaBridge 126:abea610beb85 1143 } USB_OTG_INEndpointTypeDef;
AnnaBridge 126:abea610beb85 1144
AnnaBridge 126:abea610beb85 1145
AnnaBridge 126:abea610beb85 1146 /**
AnnaBridge 126:abea610beb85 1147 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
AnnaBridge 126:abea610beb85 1148 */
AnnaBridge 126:abea610beb85 1149 typedef struct
AnnaBridge 126:abea610beb85 1150 {
AnnaBridge 126:abea610beb85 1151 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
AnnaBridge 126:abea610beb85 1152 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
AnnaBridge 126:abea610beb85 1153 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
AnnaBridge 126:abea610beb85 1154 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
AnnaBridge 126:abea610beb85 1155 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
AnnaBridge 126:abea610beb85 1156 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
AnnaBridge 126:abea610beb85 1157 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
AnnaBridge 126:abea610beb85 1158 } USB_OTG_OUTEndpointTypeDef;
AnnaBridge 126:abea610beb85 1159
AnnaBridge 126:abea610beb85 1160
AnnaBridge 126:abea610beb85 1161 /**
AnnaBridge 126:abea610beb85 1162 * @brief USB_OTG_Host_Mode_Register_Structures
AnnaBridge 126:abea610beb85 1163 */
AnnaBridge 126:abea610beb85 1164 typedef struct
AnnaBridge 126:abea610beb85 1165 {
AnnaBridge 126:abea610beb85 1166 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
AnnaBridge 126:abea610beb85 1167 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
AnnaBridge 126:abea610beb85 1168 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
AnnaBridge 126:abea610beb85 1169 uint32_t Reserved40C; /*!< Reserved 40Ch */
AnnaBridge 126:abea610beb85 1170 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
AnnaBridge 126:abea610beb85 1171 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
AnnaBridge 126:abea610beb85 1172 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
AnnaBridge 126:abea610beb85 1173 } USB_OTG_HostTypeDef;
AnnaBridge 126:abea610beb85 1174
AnnaBridge 126:abea610beb85 1175 /**
AnnaBridge 126:abea610beb85 1176 * @brief USB_OTG_Host_Channel_Specific_Registers
AnnaBridge 126:abea610beb85 1177 */
AnnaBridge 126:abea610beb85 1178 typedef struct
AnnaBridge 126:abea610beb85 1179 {
AnnaBridge 126:abea610beb85 1180 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
AnnaBridge 126:abea610beb85 1181 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
AnnaBridge 126:abea610beb85 1182 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
AnnaBridge 126:abea610beb85 1183 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
AnnaBridge 126:abea610beb85 1184 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
AnnaBridge 126:abea610beb85 1185 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
AnnaBridge 126:abea610beb85 1186 uint32_t Reserved[2]; /*!< Reserved */
AnnaBridge 126:abea610beb85 1187 } USB_OTG_HostChannelTypeDef;
AnnaBridge 126:abea610beb85 1188 /**
AnnaBridge 126:abea610beb85 1189 * @}
AnnaBridge 126:abea610beb85 1190 */
AnnaBridge 126:abea610beb85 1191
AnnaBridge 126:abea610beb85 1192 /**
AnnaBridge 126:abea610beb85 1193 * @brief JPEG Codec
AnnaBridge 126:abea610beb85 1194 */
AnnaBridge 126:abea610beb85 1195 typedef struct
AnnaBridge 126:abea610beb85 1196 {
AnnaBridge 126:abea610beb85 1197 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
AnnaBridge 126:abea610beb85 1198 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
AnnaBridge 126:abea610beb85 1199 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
AnnaBridge 126:abea610beb85 1200 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
AnnaBridge 126:abea610beb85 1201 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
AnnaBridge 126:abea610beb85 1202 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
AnnaBridge 126:abea610beb85 1203 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
AnnaBridge 126:abea610beb85 1204 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
AnnaBridge 126:abea610beb85 1205 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
AnnaBridge 126:abea610beb85 1206 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
AnnaBridge 126:abea610beb85 1207 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
AnnaBridge 126:abea610beb85 1208 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
AnnaBridge 126:abea610beb85 1209 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
AnnaBridge 126:abea610beb85 1210 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
AnnaBridge 126:abea610beb85 1211 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
AnnaBridge 126:abea610beb85 1212 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
AnnaBridge 126:abea610beb85 1213 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
AnnaBridge 126:abea610beb85 1214 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
AnnaBridge 126:abea610beb85 1215 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
AnnaBridge 126:abea610beb85 1216 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
AnnaBridge 126:abea610beb85 1217 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
AnnaBridge 126:abea610beb85 1218 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
AnnaBridge 126:abea610beb85 1219 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
AnnaBridge 126:abea610beb85 1220 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
AnnaBridge 126:abea610beb85 1221 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
AnnaBridge 126:abea610beb85 1222 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */
AnnaBridge 126:abea610beb85 1223 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */
AnnaBridge 126:abea610beb85 1224 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */
AnnaBridge 126:abea610beb85 1225 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */
AnnaBridge 126:abea610beb85 1226
AnnaBridge 126:abea610beb85 1227 } JPEG_TypeDef;
AnnaBridge 126:abea610beb85 1228
AnnaBridge 126:abea610beb85 1229 /**
AnnaBridge 126:abea610beb85 1230 * @brief MDIOS
AnnaBridge 126:abea610beb85 1231 */
AnnaBridge 126:abea610beb85 1232
AnnaBridge 126:abea610beb85 1233 typedef struct
AnnaBridge 126:abea610beb85 1234 {
AnnaBridge 126:abea610beb85 1235 __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */
AnnaBridge 126:abea610beb85 1236 __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */
AnnaBridge 126:abea610beb85 1237 __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */
AnnaBridge 126:abea610beb85 1238 __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */
AnnaBridge 126:abea610beb85 1239 __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */
AnnaBridge 126:abea610beb85 1240 __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */
AnnaBridge 126:abea610beb85 1241 __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */
AnnaBridge 126:abea610beb85 1242 uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
AnnaBridge 126:abea610beb85 1243 __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */
AnnaBridge 126:abea610beb85 1244 __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */
AnnaBridge 126:abea610beb85 1245 __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */
AnnaBridge 126:abea610beb85 1246 __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */
AnnaBridge 126:abea610beb85 1247 __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */
AnnaBridge 126:abea610beb85 1248 __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */
AnnaBridge 126:abea610beb85 1249 __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */
AnnaBridge 126:abea610beb85 1250 __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */
AnnaBridge 126:abea610beb85 1251 __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */
AnnaBridge 126:abea610beb85 1252 __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */
AnnaBridge 126:abea610beb85 1253 __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */
AnnaBridge 126:abea610beb85 1254 __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */
AnnaBridge 126:abea610beb85 1255 __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */
AnnaBridge 126:abea610beb85 1256 __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */
AnnaBridge 126:abea610beb85 1257 __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */
AnnaBridge 126:abea610beb85 1258 __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */
AnnaBridge 126:abea610beb85 1259 __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */
AnnaBridge 126:abea610beb85 1260 __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */
AnnaBridge 126:abea610beb85 1261 __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */
AnnaBridge 126:abea610beb85 1262 __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */
AnnaBridge 126:abea610beb85 1263 __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */
AnnaBridge 126:abea610beb85 1264 __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */
AnnaBridge 126:abea610beb85 1265 __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */
AnnaBridge 126:abea610beb85 1266 __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */
AnnaBridge 126:abea610beb85 1267 __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */
AnnaBridge 126:abea610beb85 1268 __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */
AnnaBridge 126:abea610beb85 1269 __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */
AnnaBridge 126:abea610beb85 1270 __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */
AnnaBridge 126:abea610beb85 1271 __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */
AnnaBridge 126:abea610beb85 1272 __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */
AnnaBridge 126:abea610beb85 1273 __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */
AnnaBridge 126:abea610beb85 1274 __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */
AnnaBridge 126:abea610beb85 1275 __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */
AnnaBridge 126:abea610beb85 1276 __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */
AnnaBridge 126:abea610beb85 1277 __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */
AnnaBridge 126:abea610beb85 1278 __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */
AnnaBridge 126:abea610beb85 1279 __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */
AnnaBridge 126:abea610beb85 1280 __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */
AnnaBridge 126:abea610beb85 1281 __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */
AnnaBridge 126:abea610beb85 1282 __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */
AnnaBridge 126:abea610beb85 1283 __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */
AnnaBridge 126:abea610beb85 1284 __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */
AnnaBridge 126:abea610beb85 1285 __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */
AnnaBridge 126:abea610beb85 1286 __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */
AnnaBridge 126:abea610beb85 1287 __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */
AnnaBridge 126:abea610beb85 1288 __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */
AnnaBridge 126:abea610beb85 1289 __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */
AnnaBridge 126:abea610beb85 1290 __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */
AnnaBridge 126:abea610beb85 1291 __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */
AnnaBridge 126:abea610beb85 1292 __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */
AnnaBridge 126:abea610beb85 1293 __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */
AnnaBridge 126:abea610beb85 1294 __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */
AnnaBridge 126:abea610beb85 1295 __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */
AnnaBridge 126:abea610beb85 1296 __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */
AnnaBridge 126:abea610beb85 1297 __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */
AnnaBridge 126:abea610beb85 1298 __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */
AnnaBridge 126:abea610beb85 1299 __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */
AnnaBridge 126:abea610beb85 1300 __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */
AnnaBridge 126:abea610beb85 1301 __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */
AnnaBridge 126:abea610beb85 1302 __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */
AnnaBridge 126:abea610beb85 1303 __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */
AnnaBridge 126:abea610beb85 1304 __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */
AnnaBridge 126:abea610beb85 1305 __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */
AnnaBridge 126:abea610beb85 1306 __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */
AnnaBridge 126:abea610beb85 1307 } MDIOS_TypeDef;
AnnaBridge 126:abea610beb85 1308
AnnaBridge 126:abea610beb85 1309 /**
AnnaBridge 126:abea610beb85 1310 * @brief DSI Controller
AnnaBridge 126:abea610beb85 1311 */
AnnaBridge 126:abea610beb85 1312
AnnaBridge 126:abea610beb85 1313 typedef struct
AnnaBridge 126:abea610beb85 1314 {
AnnaBridge 126:abea610beb85 1315 __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
AnnaBridge 126:abea610beb85 1316 __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
AnnaBridge 126:abea610beb85 1317 __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
AnnaBridge 126:abea610beb85 1318 __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
AnnaBridge 126:abea610beb85 1319 __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
AnnaBridge 126:abea610beb85 1320 __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
AnnaBridge 126:abea610beb85 1321 __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
AnnaBridge 126:abea610beb85 1322 uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
AnnaBridge 126:abea610beb85 1323 __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
AnnaBridge 126:abea610beb85 1324 __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
AnnaBridge 126:abea610beb85 1325 __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
AnnaBridge 126:abea610beb85 1326 __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
AnnaBridge 126:abea610beb85 1327 __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
AnnaBridge 126:abea610beb85 1328 __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
AnnaBridge 126:abea610beb85 1329 __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
AnnaBridge 126:abea610beb85 1330 __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
AnnaBridge 126:abea610beb85 1331 __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
AnnaBridge 126:abea610beb85 1332 __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
AnnaBridge 126:abea610beb85 1333 __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
AnnaBridge 126:abea610beb85 1334 __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
AnnaBridge 126:abea610beb85 1335 __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
AnnaBridge 126:abea610beb85 1336 __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
AnnaBridge 126:abea610beb85 1337 __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
AnnaBridge 126:abea610beb85 1338 __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
AnnaBridge 126:abea610beb85 1339 __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
AnnaBridge 126:abea610beb85 1340 __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
AnnaBridge 126:abea610beb85 1341 __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
AnnaBridge 126:abea610beb85 1342 __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
AnnaBridge 126:abea610beb85 1343 __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
AnnaBridge 126:abea610beb85 1344 __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
AnnaBridge 126:abea610beb85 1345 __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
AnnaBridge 126:abea610beb85 1346 __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
AnnaBridge 126:abea610beb85 1347 __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
AnnaBridge 126:abea610beb85 1348 __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
AnnaBridge 126:abea610beb85 1349 __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
AnnaBridge 126:abea610beb85 1350 __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
AnnaBridge 126:abea610beb85 1351 __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
AnnaBridge 126:abea610beb85 1352 uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
AnnaBridge 126:abea610beb85 1353 __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
AnnaBridge 126:abea610beb85 1354 __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
AnnaBridge 126:abea610beb85 1355 uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
AnnaBridge 126:abea610beb85 1356 __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
AnnaBridge 126:abea610beb85 1357 uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
AnnaBridge 126:abea610beb85 1358 __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
AnnaBridge 126:abea610beb85 1359 uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
AnnaBridge 126:abea610beb85 1360 __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
AnnaBridge 126:abea610beb85 1361 __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
AnnaBridge 126:abea610beb85 1362 uint32_t RESERVED5; /*!< Reserved, 0x114 */
AnnaBridge 126:abea610beb85 1363 __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
AnnaBridge 126:abea610beb85 1364 uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
AnnaBridge 126:abea610beb85 1365 __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
AnnaBridge 126:abea610beb85 1366 __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
AnnaBridge 126:abea610beb85 1367 __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
AnnaBridge 126:abea610beb85 1368 __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
AnnaBridge 126:abea610beb85 1369 __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
AnnaBridge 126:abea610beb85 1370 __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
AnnaBridge 126:abea610beb85 1371 __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
AnnaBridge 126:abea610beb85 1372 __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
AnnaBridge 126:abea610beb85 1373 __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
AnnaBridge 126:abea610beb85 1374 __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
AnnaBridge 126:abea610beb85 1375 __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
AnnaBridge 126:abea610beb85 1376 uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
AnnaBridge 126:abea610beb85 1377 __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
AnnaBridge 126:abea610beb85 1378 uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
AnnaBridge 126:abea610beb85 1379 __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
AnnaBridge 126:abea610beb85 1380 __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
AnnaBridge 126:abea610beb85 1381 __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
AnnaBridge 126:abea610beb85 1382 __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
AnnaBridge 126:abea610beb85 1383 __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
AnnaBridge 126:abea610beb85 1384 uint32_t RESERVED9; /*!< Reserved, 0x414 */
AnnaBridge 126:abea610beb85 1385 __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
AnnaBridge 126:abea610beb85 1386 uint32_t RESERVED10; /*!< Reserved, 0x42C */
AnnaBridge 126:abea610beb85 1387 __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
AnnaBridge 126:abea610beb85 1388 } DSI_TypeDef;
AnnaBridge 126:abea610beb85 1389
AnnaBridge 126:abea610beb85 1390 /** @addtogroup Peripheral_memory_map
AnnaBridge 126:abea610beb85 1391 * @{
AnnaBridge 126:abea610beb85 1392 */
AnnaBridge 126:abea610beb85 1393 #define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
AnnaBridge 126:abea610beb85 1394 #define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */
AnnaBridge 126:abea610beb85 1395 #define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
AnnaBridge 126:abea610beb85 1396 #define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */
AnnaBridge 126:abea610beb85 1397 #define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
AnnaBridge 126:abea610beb85 1398 #define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
AnnaBridge 126:abea610beb85 1399 #define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
AnnaBridge 126:abea610beb85 1400 #define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
AnnaBridge 126:abea610beb85 1401 #define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
AnnaBridge 126:abea610beb85 1402 #define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */
AnnaBridge 126:abea610beb85 1403 #define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
AnnaBridge 126:abea610beb85 1404 #define FLASH_END 0x081FFFFFU /*!< FLASH end address */
AnnaBridge 126:abea610beb85 1405
AnnaBridge 126:abea610beb85 1406 /* Legacy define */
AnnaBridge 126:abea610beb85 1407 #define FLASH_BASE FLASHAXI_BASE
AnnaBridge 126:abea610beb85 1408
AnnaBridge 126:abea610beb85 1409 /*!< Peripheral memory map */
AnnaBridge 126:abea610beb85 1410 #define APB1PERIPH_BASE PERIPH_BASE
AnnaBridge 126:abea610beb85 1411 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
AnnaBridge 126:abea610beb85 1412 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
AnnaBridge 126:abea610beb85 1413 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
AnnaBridge 126:abea610beb85 1414
AnnaBridge 126:abea610beb85 1415 /*!< APB1 peripherals */
AnnaBridge 126:abea610beb85 1416 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
AnnaBridge 126:abea610beb85 1417 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
AnnaBridge 126:abea610beb85 1418 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
AnnaBridge 126:abea610beb85 1419 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
AnnaBridge 126:abea610beb85 1420 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
AnnaBridge 126:abea610beb85 1421 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
AnnaBridge 126:abea610beb85 1422 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
AnnaBridge 126:abea610beb85 1423 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
AnnaBridge 126:abea610beb85 1424 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
AnnaBridge 126:abea610beb85 1425 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
AnnaBridge 126:abea610beb85 1426 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
AnnaBridge 126:abea610beb85 1427 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
AnnaBridge 126:abea610beb85 1428 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
AnnaBridge 126:abea610beb85 1429 #define CAN3_BASE (APB1PERIPH_BASE + 0x3400U)
AnnaBridge 126:abea610beb85 1430 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
AnnaBridge 126:abea610beb85 1431 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
AnnaBridge 126:abea610beb85 1432 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
AnnaBridge 126:abea610beb85 1433 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
AnnaBridge 126:abea610beb85 1434 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
AnnaBridge 126:abea610beb85 1435 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
AnnaBridge 126:abea610beb85 1436 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
AnnaBridge 126:abea610beb85 1437 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
AnnaBridge 126:abea610beb85 1438 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
AnnaBridge 126:abea610beb85 1439 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
AnnaBridge 126:abea610beb85 1440 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
AnnaBridge 126:abea610beb85 1441 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
AnnaBridge 126:abea610beb85 1442 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
AnnaBridge 126:abea610beb85 1443 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
AnnaBridge 126:abea610beb85 1444 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
AnnaBridge 126:abea610beb85 1445 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
AnnaBridge 126:abea610beb85 1446 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
AnnaBridge 126:abea610beb85 1447 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
AnnaBridge 126:abea610beb85 1448
AnnaBridge 126:abea610beb85 1449 /*!< APB2 peripherals */
AnnaBridge 126:abea610beb85 1450 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
AnnaBridge 126:abea610beb85 1451 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
AnnaBridge 126:abea610beb85 1452 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
AnnaBridge 126:abea610beb85 1453 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
AnnaBridge 126:abea610beb85 1454 #define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
AnnaBridge 126:abea610beb85 1455 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
AnnaBridge 126:abea610beb85 1456 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
AnnaBridge 126:abea610beb85 1457 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
AnnaBridge 126:abea610beb85 1458 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
AnnaBridge 126:abea610beb85 1459 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
AnnaBridge 126:abea610beb85 1460 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
AnnaBridge 126:abea610beb85 1461 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
AnnaBridge 126:abea610beb85 1462 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
AnnaBridge 126:abea610beb85 1463 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
AnnaBridge 126:abea610beb85 1464 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
AnnaBridge 126:abea610beb85 1465 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
AnnaBridge 126:abea610beb85 1466 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
AnnaBridge 126:abea610beb85 1467 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
AnnaBridge 126:abea610beb85 1468 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
AnnaBridge 126:abea610beb85 1469 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
AnnaBridge 126:abea610beb85 1470 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
AnnaBridge 126:abea610beb85 1471 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
AnnaBridge 126:abea610beb85 1472 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
AnnaBridge 126:abea610beb85 1473 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
AnnaBridge 126:abea610beb85 1474 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
AnnaBridge 126:abea610beb85 1475 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
AnnaBridge 126:abea610beb85 1476 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
AnnaBridge 126:abea610beb85 1477 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
AnnaBridge 126:abea610beb85 1478 #define DSI_BASE (APB2PERIPH_BASE + 0x6C00U)
AnnaBridge 126:abea610beb85 1479 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U)
AnnaBridge 126:abea610beb85 1480 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
AnnaBridge 126:abea610beb85 1481 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
AnnaBridge 126:abea610beb85 1482 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
AnnaBridge 126:abea610beb85 1483 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
AnnaBridge 126:abea610beb85 1484 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U)
AnnaBridge 126:abea610beb85 1485 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U)
AnnaBridge 126:abea610beb85 1486 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U)
AnnaBridge 126:abea610beb85 1487 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U)
AnnaBridge 126:abea610beb85 1488 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
AnnaBridge 126:abea610beb85 1489 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
AnnaBridge 126:abea610beb85 1490 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U)
AnnaBridge 126:abea610beb85 1491 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U)
AnnaBridge 126:abea610beb85 1492 #define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U)
AnnaBridge 126:abea610beb85 1493 /*!< AHB1 peripherals */
AnnaBridge 126:abea610beb85 1494 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
AnnaBridge 126:abea610beb85 1495 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
AnnaBridge 126:abea610beb85 1496 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
AnnaBridge 126:abea610beb85 1497 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
AnnaBridge 126:abea610beb85 1498 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
AnnaBridge 126:abea610beb85 1499 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
AnnaBridge 126:abea610beb85 1500 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
AnnaBridge 126:abea610beb85 1501 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
AnnaBridge 126:abea610beb85 1502 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
AnnaBridge 126:abea610beb85 1503 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
AnnaBridge 126:abea610beb85 1504 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
AnnaBridge 126:abea610beb85 1505 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
AnnaBridge 126:abea610beb85 1506 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
AnnaBridge 126:abea610beb85 1507 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
AnnaBridge 126:abea610beb85 1508 #define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */
AnnaBridge 126:abea610beb85 1509 #define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */
AnnaBridge 126:abea610beb85 1510 #define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */
AnnaBridge 126:abea610beb85 1511 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
AnnaBridge 126:abea610beb85 1512 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
AnnaBridge 126:abea610beb85 1513 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
AnnaBridge 126:abea610beb85 1514 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
AnnaBridge 126:abea610beb85 1515 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
AnnaBridge 126:abea610beb85 1516 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
AnnaBridge 126:abea610beb85 1517 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
AnnaBridge 126:abea610beb85 1518 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
AnnaBridge 126:abea610beb85 1519 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
AnnaBridge 126:abea610beb85 1520 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
AnnaBridge 126:abea610beb85 1521 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
AnnaBridge 126:abea610beb85 1522 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
AnnaBridge 126:abea610beb85 1523 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
AnnaBridge 126:abea610beb85 1524 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
AnnaBridge 126:abea610beb85 1525 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
AnnaBridge 126:abea610beb85 1526 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
AnnaBridge 126:abea610beb85 1527 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
AnnaBridge 126:abea610beb85 1528 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
AnnaBridge 126:abea610beb85 1529 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
AnnaBridge 126:abea610beb85 1530 #define ETH_MAC_BASE (ETH_BASE)
AnnaBridge 126:abea610beb85 1531 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
AnnaBridge 126:abea610beb85 1532 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
AnnaBridge 126:abea610beb85 1533 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
AnnaBridge 126:abea610beb85 1534 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
AnnaBridge 126:abea610beb85 1535 /*!< AHB2 peripherals */
AnnaBridge 126:abea610beb85 1536 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
AnnaBridge 126:abea610beb85 1537 #define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U)
AnnaBridge 126:abea610beb85 1538 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
AnnaBridge 126:abea610beb85 1539 /*!< FMC Bankx registers base address */
AnnaBridge 126:abea610beb85 1540 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
AnnaBridge 126:abea610beb85 1541 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
AnnaBridge 126:abea610beb85 1542 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
AnnaBridge 126:abea610beb85 1543 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
AnnaBridge 126:abea610beb85 1544
AnnaBridge 126:abea610beb85 1545 /* Debug MCU registers base address */
AnnaBridge 126:abea610beb85 1546 #define DBGMCU_BASE 0xE0042000U
AnnaBridge 126:abea610beb85 1547
AnnaBridge 126:abea610beb85 1548 /*!< USB registers base address */
AnnaBridge 126:abea610beb85 1549 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
AnnaBridge 126:abea610beb85 1550 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
AnnaBridge 126:abea610beb85 1551
AnnaBridge 126:abea610beb85 1552 #define USB_OTG_GLOBAL_BASE 0x000U
AnnaBridge 126:abea610beb85 1553 #define USB_OTG_DEVICE_BASE 0x800U
AnnaBridge 126:abea610beb85 1554 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
AnnaBridge 126:abea610beb85 1555 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
AnnaBridge 126:abea610beb85 1556 #define USB_OTG_EP_REG_SIZE 0x20U
AnnaBridge 126:abea610beb85 1557 #define USB_OTG_HOST_BASE 0x400U
AnnaBridge 126:abea610beb85 1558 #define USB_OTG_HOST_PORT_BASE 0x440U
AnnaBridge 126:abea610beb85 1559 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
AnnaBridge 126:abea610beb85 1560 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
AnnaBridge 126:abea610beb85 1561 #define USB_OTG_PCGCCTL_BASE 0xE00U
AnnaBridge 126:abea610beb85 1562 #define USB_OTG_FIFO_BASE 0x1000U
AnnaBridge 126:abea610beb85 1563 #define USB_OTG_FIFO_SIZE 0x1000U
AnnaBridge 126:abea610beb85 1564
AnnaBridge 126:abea610beb85 1565 /**
AnnaBridge 126:abea610beb85 1566 * @}
AnnaBridge 126:abea610beb85 1567 */
AnnaBridge 126:abea610beb85 1568
AnnaBridge 126:abea610beb85 1569 /** @addtogroup Peripheral_declaration
AnnaBridge 126:abea610beb85 1570 * @{
AnnaBridge 126:abea610beb85 1571 */
AnnaBridge 126:abea610beb85 1572 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
AnnaBridge 126:abea610beb85 1573 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
AnnaBridge 126:abea610beb85 1574 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
AnnaBridge 126:abea610beb85 1575 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
AnnaBridge 126:abea610beb85 1576 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
AnnaBridge 126:abea610beb85 1577 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
AnnaBridge 126:abea610beb85 1578 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
AnnaBridge 126:abea610beb85 1579 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
AnnaBridge 126:abea610beb85 1580 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
AnnaBridge 126:abea610beb85 1581 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
AnnaBridge 126:abea610beb85 1582 #define RTC ((RTC_TypeDef *) RTC_BASE)
AnnaBridge 126:abea610beb85 1583 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
AnnaBridge 126:abea610beb85 1584 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
AnnaBridge 126:abea610beb85 1585 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
AnnaBridge 126:abea610beb85 1586 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
AnnaBridge 126:abea610beb85 1587 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
AnnaBridge 126:abea610beb85 1588 #define USART2 ((USART_TypeDef *) USART2_BASE)
AnnaBridge 126:abea610beb85 1589 #define USART3 ((USART_TypeDef *) USART3_BASE)
AnnaBridge 126:abea610beb85 1590 #define UART4 ((USART_TypeDef *) UART4_BASE)
AnnaBridge 126:abea610beb85 1591 #define UART5 ((USART_TypeDef *) UART5_BASE)
AnnaBridge 126:abea610beb85 1592 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 126:abea610beb85 1593 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
AnnaBridge 126:abea610beb85 1594 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
AnnaBridge 126:abea610beb85 1595 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
AnnaBridge 126:abea610beb85 1596 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
AnnaBridge 126:abea610beb85 1597 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
AnnaBridge 126:abea610beb85 1598 #define CEC ((CEC_TypeDef *) CEC_BASE)
AnnaBridge 126:abea610beb85 1599 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 126:abea610beb85 1600 #define DAC ((DAC_TypeDef *) DAC_BASE)
AnnaBridge 126:abea610beb85 1601 #define UART7 ((USART_TypeDef *) UART7_BASE)
AnnaBridge 126:abea610beb85 1602 #define UART8 ((USART_TypeDef *) UART8_BASE)
AnnaBridge 126:abea610beb85 1603 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
AnnaBridge 126:abea610beb85 1604 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
AnnaBridge 126:abea610beb85 1605 #define USART1 ((USART_TypeDef *) USART1_BASE)
AnnaBridge 126:abea610beb85 1606 #define USART6 ((USART_TypeDef *) USART6_BASE)
AnnaBridge 126:abea610beb85 1607 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
AnnaBridge 126:abea610beb85 1608 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 126:abea610beb85 1609 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
AnnaBridge 126:abea610beb85 1610 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
AnnaBridge 126:abea610beb85 1611 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
AnnaBridge 126:abea610beb85 1612 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 126:abea610beb85 1613 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
AnnaBridge 126:abea610beb85 1614 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
AnnaBridge 126:abea610beb85 1615 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
AnnaBridge 126:abea610beb85 1616 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
AnnaBridge 126:abea610beb85 1617 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
AnnaBridge 126:abea610beb85 1618 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
AnnaBridge 126:abea610beb85 1619 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
AnnaBridge 126:abea610beb85 1620 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
AnnaBridge 126:abea610beb85 1621 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
AnnaBridge 126:abea610beb85 1622 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
AnnaBridge 126:abea610beb85 1623 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
AnnaBridge 126:abea610beb85 1624 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
AnnaBridge 126:abea610beb85 1625 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
AnnaBridge 126:abea610beb85 1626 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
AnnaBridge 126:abea610beb85 1627 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
AnnaBridge 126:abea610beb85 1628 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
AnnaBridge 126:abea610beb85 1629 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
AnnaBridge 126:abea610beb85 1630 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
AnnaBridge 126:abea610beb85 1631 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
AnnaBridge 126:abea610beb85 1632 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
AnnaBridge 126:abea610beb85 1633 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
AnnaBridge 126:abea610beb85 1634 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
AnnaBridge 126:abea610beb85 1635 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
AnnaBridge 126:abea610beb85 1636 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
AnnaBridge 126:abea610beb85 1637 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
AnnaBridge 126:abea610beb85 1638 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
AnnaBridge 126:abea610beb85 1639 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
AnnaBridge 126:abea610beb85 1640 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
AnnaBridge 126:abea610beb85 1641 #define CRC ((CRC_TypeDef *) CRC_BASE)
AnnaBridge 126:abea610beb85 1642 #define RCC ((RCC_TypeDef *) RCC_BASE)
AnnaBridge 126:abea610beb85 1643 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
AnnaBridge 126:abea610beb85 1644 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
AnnaBridge 126:abea610beb85 1645 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
AnnaBridge 126:abea610beb85 1646 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
AnnaBridge 126:abea610beb85 1647 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
AnnaBridge 126:abea610beb85 1648 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
AnnaBridge 126:abea610beb85 1649 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
AnnaBridge 126:abea610beb85 1650 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
AnnaBridge 126:abea610beb85 1651 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
AnnaBridge 126:abea610beb85 1652 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
AnnaBridge 126:abea610beb85 1653 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
AnnaBridge 126:abea610beb85 1654 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
AnnaBridge 126:abea610beb85 1655 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
AnnaBridge 126:abea610beb85 1656 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
AnnaBridge 126:abea610beb85 1657 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
AnnaBridge 126:abea610beb85 1658 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
AnnaBridge 126:abea610beb85 1659 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
AnnaBridge 126:abea610beb85 1660 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
AnnaBridge 126:abea610beb85 1661 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
AnnaBridge 126:abea610beb85 1662 #define ETH ((ETH_TypeDef *) ETH_BASE)
AnnaBridge 126:abea610beb85 1663 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
AnnaBridge 126:abea610beb85 1664 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
AnnaBridge 126:abea610beb85 1665 #define RNG ((RNG_TypeDef *) RNG_BASE)
AnnaBridge 126:abea610beb85 1666 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
AnnaBridge 126:abea610beb85 1667 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
AnnaBridge 126:abea610beb85 1668 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
AnnaBridge 126:abea610beb85 1669 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
AnnaBridge 126:abea610beb85 1670 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
AnnaBridge 126:abea610beb85 1671 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
AnnaBridge 126:abea610beb85 1672 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
AnnaBridge 126:abea610beb85 1673 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
AnnaBridge 126:abea610beb85 1674 #define CAN3 ((CAN_TypeDef *) CAN3_BASE)
AnnaBridge 126:abea610beb85 1675 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
AnnaBridge 126:abea610beb85 1676 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
AnnaBridge 126:abea610beb85 1677 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
AnnaBridge 126:abea610beb85 1678 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
AnnaBridge 126:abea610beb85 1679 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
AnnaBridge 126:abea610beb85 1680 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
AnnaBridge 126:abea610beb85 1681 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
AnnaBridge 126:abea610beb85 1682 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
AnnaBridge 126:abea610beb85 1683 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
AnnaBridge 126:abea610beb85 1684 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
AnnaBridge 126:abea610beb85 1685 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
AnnaBridge 126:abea610beb85 1686 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
AnnaBridge 126:abea610beb85 1687 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
AnnaBridge 126:abea610beb85 1688 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
AnnaBridge 126:abea610beb85 1689 #define JPEG ((JPEG_TypeDef *) JPEG_BASE)
AnnaBridge 126:abea610beb85 1690 #define DSI ((DSI_TypeDef *)DSI_BASE)
AnnaBridge 126:abea610beb85 1691
AnnaBridge 126:abea610beb85 1692 /**
AnnaBridge 126:abea610beb85 1693 * @}
AnnaBridge 126:abea610beb85 1694 */
AnnaBridge 126:abea610beb85 1695
AnnaBridge 126:abea610beb85 1696 /** @addtogroup Exported_constants
AnnaBridge 126:abea610beb85 1697 * @{
AnnaBridge 126:abea610beb85 1698 */
AnnaBridge 126:abea610beb85 1699
AnnaBridge 126:abea610beb85 1700 /** @addtogroup Peripheral_Registers_Bits_Definition
AnnaBridge 126:abea610beb85 1701 * @{
AnnaBridge 126:abea610beb85 1702 */
AnnaBridge 126:abea610beb85 1703
AnnaBridge 126:abea610beb85 1704 /******************************************************************************/
AnnaBridge 126:abea610beb85 1705 /* Peripheral Registers_Bits_Definition */
AnnaBridge 126:abea610beb85 1706 /******************************************************************************/
AnnaBridge 126:abea610beb85 1707
AnnaBridge 126:abea610beb85 1708 /******************************************************************************/
AnnaBridge 126:abea610beb85 1709 /* */
AnnaBridge 126:abea610beb85 1710 /* Analog to Digital Converter */
AnnaBridge 126:abea610beb85 1711 /* */
AnnaBridge 126:abea610beb85 1712 /******************************************************************************/
AnnaBridge 126:abea610beb85 1713 /******************** Bit definition for ADC_SR register ********************/
AnnaBridge 126:abea610beb85 1714 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
AnnaBridge 126:abea610beb85 1715 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
AnnaBridge 126:abea610beb85 1716 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
AnnaBridge 126:abea610beb85 1717 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
AnnaBridge 126:abea610beb85 1718 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
AnnaBridge 126:abea610beb85 1719 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
AnnaBridge 126:abea610beb85 1720
AnnaBridge 126:abea610beb85 1721 /******************* Bit definition for ADC_CR1 register ********************/
AnnaBridge 126:abea610beb85 1722 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
AnnaBridge 126:abea610beb85 1723 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1724 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1725 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1726 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1727 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1728 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
AnnaBridge 126:abea610beb85 1729 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
AnnaBridge 126:abea610beb85 1730 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
AnnaBridge 126:abea610beb85 1731 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
AnnaBridge 126:abea610beb85 1732 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
AnnaBridge 126:abea610beb85 1733 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
AnnaBridge 126:abea610beb85 1734 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
AnnaBridge 126:abea610beb85 1735 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
AnnaBridge 126:abea610beb85 1736 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
AnnaBridge 126:abea610beb85 1737 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1738 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1739 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1740 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
AnnaBridge 126:abea610beb85 1741 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
AnnaBridge 126:abea610beb85 1742 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
AnnaBridge 126:abea610beb85 1743 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1744 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1745 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
AnnaBridge 126:abea610beb85 1746
AnnaBridge 126:abea610beb85 1747 /******************* Bit definition for ADC_CR2 register ********************/
AnnaBridge 126:abea610beb85 1748 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
AnnaBridge 126:abea610beb85 1749 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
AnnaBridge 126:abea610beb85 1750 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
AnnaBridge 126:abea610beb85 1751 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
AnnaBridge 126:abea610beb85 1752 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
AnnaBridge 126:abea610beb85 1753 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
AnnaBridge 126:abea610beb85 1754 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
AnnaBridge 126:abea610beb85 1755 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1756 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1757 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1758 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1759 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
AnnaBridge 126:abea610beb85 1760 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1761 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1762 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
AnnaBridge 126:abea610beb85 1763 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
AnnaBridge 126:abea610beb85 1764 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1765 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1766 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1767 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1768 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
AnnaBridge 126:abea610beb85 1769 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1770 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1771 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
AnnaBridge 126:abea610beb85 1772
AnnaBridge 126:abea610beb85 1773 /****************** Bit definition for ADC_SMPR1 register *******************/
AnnaBridge 126:abea610beb85 1774 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
AnnaBridge 126:abea610beb85 1775 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1776 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1777 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1778 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
AnnaBridge 126:abea610beb85 1779 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1780 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1781 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1782 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
AnnaBridge 126:abea610beb85 1783 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1784 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1785 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1786 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
AnnaBridge 126:abea610beb85 1787 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1788 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1789 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1790 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
AnnaBridge 126:abea610beb85 1791 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1792 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1793 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1794 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
AnnaBridge 126:abea610beb85 1795 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1796 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1797 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1798 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
AnnaBridge 126:abea610beb85 1799 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1800 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1801 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1802 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
AnnaBridge 126:abea610beb85 1803 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1804 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1805 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1806 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
AnnaBridge 126:abea610beb85 1807 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1808 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1809 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1810
AnnaBridge 126:abea610beb85 1811 /****************** Bit definition for ADC_SMPR2 register *******************/
AnnaBridge 126:abea610beb85 1812 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
AnnaBridge 126:abea610beb85 1813 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1814 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1815 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1816 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
AnnaBridge 126:abea610beb85 1817 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1818 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1819 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1820 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
AnnaBridge 126:abea610beb85 1821 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1822 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1823 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1824 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
AnnaBridge 126:abea610beb85 1825 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1826 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1827 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1828 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
AnnaBridge 126:abea610beb85 1829 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1830 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1831 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1832 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
AnnaBridge 126:abea610beb85 1833 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1834 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1835 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1836 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
AnnaBridge 126:abea610beb85 1837 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1838 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1839 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1840 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
AnnaBridge 126:abea610beb85 1841 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1842 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1843 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1844 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
AnnaBridge 126:abea610beb85 1845 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1846 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1847 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1848 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
AnnaBridge 126:abea610beb85 1849 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1850 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1851 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1852
AnnaBridge 126:abea610beb85 1853 /****************** Bit definition for ADC_JOFR1 register *******************/
AnnaBridge 126:abea610beb85 1854 #define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
AnnaBridge 126:abea610beb85 1855
AnnaBridge 126:abea610beb85 1856 /****************** Bit definition for ADC_JOFR2 register *******************/
AnnaBridge 126:abea610beb85 1857 #define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
AnnaBridge 126:abea610beb85 1858
AnnaBridge 126:abea610beb85 1859 /****************** Bit definition for ADC_JOFR3 register *******************/
AnnaBridge 126:abea610beb85 1860 #define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
AnnaBridge 126:abea610beb85 1861
AnnaBridge 126:abea610beb85 1862 /****************** Bit definition for ADC_JOFR4 register *******************/
AnnaBridge 126:abea610beb85 1863 #define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
AnnaBridge 126:abea610beb85 1864
AnnaBridge 126:abea610beb85 1865 /******************* Bit definition for ADC_HTR register ********************/
AnnaBridge 126:abea610beb85 1866 #define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
AnnaBridge 126:abea610beb85 1867
AnnaBridge 126:abea610beb85 1868 /******************* Bit definition for ADC_LTR register ********************/
AnnaBridge 126:abea610beb85 1869 #define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
AnnaBridge 126:abea610beb85 1870
AnnaBridge 126:abea610beb85 1871 /******************* Bit definition for ADC_SQR1 register *******************/
AnnaBridge 126:abea610beb85 1872 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1873 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1874 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1875 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1876 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1877 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1878 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1879 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1880 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1881 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1882 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1883 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1884 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1885 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1886 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1887 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1888 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1889 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1890 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1891 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1892 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1893 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1894 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1895 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1896 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
AnnaBridge 126:abea610beb85 1897 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1898 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1899 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1900 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1901
AnnaBridge 126:abea610beb85 1902 /******************* Bit definition for ADC_SQR2 register *******************/
AnnaBridge 126:abea610beb85 1903 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1904 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1905 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1906 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1907 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1908 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1909 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1910 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1911 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1912 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1913 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1914 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1915 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1916 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1917 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1918 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1919 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1920 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1921 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1922 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1923 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1924 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1925 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1926 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1927 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1928 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1929 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1930 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1931 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1932 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1933 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1934 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1935 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1936 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1937 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1938 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1939
AnnaBridge 126:abea610beb85 1940 /******************* Bit definition for ADC_SQR3 register *******************/
AnnaBridge 126:abea610beb85 1941 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1942 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1943 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1944 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1945 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1946 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1947 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1948 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1949 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1950 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1951 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1952 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1953 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1954 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1955 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1956 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1957 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1958 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1959 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1960 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1961 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1962 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1963 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1964 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1965 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1966 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1967 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1968 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1969 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1970 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1971 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
AnnaBridge 126:abea610beb85 1972 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1973 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1974 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1975 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1976 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1977
AnnaBridge 126:abea610beb85 1978 /******************* Bit definition for ADC_JSQR register *******************/
AnnaBridge 126:abea610beb85 1979 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
AnnaBridge 126:abea610beb85 1980 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1981 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1982 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1983 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1984 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1985 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
AnnaBridge 126:abea610beb85 1986 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1987 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1988 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1989 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1990 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1991 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
AnnaBridge 126:abea610beb85 1992 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1993 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 1994 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 1995 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 1996 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 1997 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
AnnaBridge 126:abea610beb85 1998 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 1999 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 2000 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 2001 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 2002 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 2003 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
AnnaBridge 126:abea610beb85 2004 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 2005 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 2006
AnnaBridge 126:abea610beb85 2007 /******************* Bit definition for ADC_JDR1 register *******************/
AnnaBridge 126:abea610beb85 2008 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
AnnaBridge 126:abea610beb85 2009
AnnaBridge 126:abea610beb85 2010 /******************* Bit definition for ADC_JDR2 register *******************/
AnnaBridge 126:abea610beb85 2011 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
AnnaBridge 126:abea610beb85 2012
AnnaBridge 126:abea610beb85 2013 /******************* Bit definition for ADC_JDR3 register *******************/
AnnaBridge 126:abea610beb85 2014 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
AnnaBridge 126:abea610beb85 2015
AnnaBridge 126:abea610beb85 2016 /******************* Bit definition for ADC_JDR4 register *******************/
AnnaBridge 126:abea610beb85 2017 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
AnnaBridge 126:abea610beb85 2018
AnnaBridge 126:abea610beb85 2019 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 126:abea610beb85 2020 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
AnnaBridge 126:abea610beb85 2021 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
AnnaBridge 126:abea610beb85 2022
AnnaBridge 126:abea610beb85 2023 /******************* Bit definition for ADC_CSR register ********************/
AnnaBridge 126:abea610beb85 2024 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
AnnaBridge 126:abea610beb85 2025 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
AnnaBridge 126:abea610beb85 2026 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
AnnaBridge 126:abea610beb85 2027 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
AnnaBridge 126:abea610beb85 2028 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
AnnaBridge 126:abea610beb85 2029 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 Overrun flag */
AnnaBridge 126:abea610beb85 2030 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
AnnaBridge 126:abea610beb85 2031 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
AnnaBridge 126:abea610beb85 2032 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
AnnaBridge 126:abea610beb85 2033 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
AnnaBridge 126:abea610beb85 2034 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
AnnaBridge 126:abea610beb85 2035 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 Overrun flag */
AnnaBridge 126:abea610beb85 2036 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
AnnaBridge 126:abea610beb85 2037 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
AnnaBridge 126:abea610beb85 2038 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
AnnaBridge 126:abea610beb85 2039 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
AnnaBridge 126:abea610beb85 2040 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
AnnaBridge 126:abea610beb85 2041 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 Overrun flag */
AnnaBridge 126:abea610beb85 2042
AnnaBridge 126:abea610beb85 2043 /* Legacy defines */
AnnaBridge 126:abea610beb85 2044 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
AnnaBridge 126:abea610beb85 2045 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
AnnaBridge 126:abea610beb85 2046 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
AnnaBridge 126:abea610beb85 2047
AnnaBridge 126:abea610beb85 2048
AnnaBridge 126:abea610beb85 2049 /******************* Bit definition for ADC_CCR register ********************/
AnnaBridge 126:abea610beb85 2050 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
AnnaBridge 126:abea610beb85 2051 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 2052 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 2053 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 2054 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 2055 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 2056 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
AnnaBridge 126:abea610beb85 2057 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 2058 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 2059 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 2060 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 2061 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
AnnaBridge 126:abea610beb85 2062 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
AnnaBridge 126:abea610beb85 2063 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 2064 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 2065 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
AnnaBridge 126:abea610beb85 2066 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 2067 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 2068 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
AnnaBridge 126:abea610beb85 2069 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
AnnaBridge 126:abea610beb85 2070
AnnaBridge 126:abea610beb85 2071 /******************* Bit definition for ADC_CDR register ********************/
AnnaBridge 126:abea610beb85 2072 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
AnnaBridge 126:abea610beb85 2073 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
AnnaBridge 126:abea610beb85 2074
AnnaBridge 126:abea610beb85 2075 /******************************************************************************/
AnnaBridge 126:abea610beb85 2076 /* */
AnnaBridge 126:abea610beb85 2077 /* Controller Area Network */
AnnaBridge 126:abea610beb85 2078 /* */
AnnaBridge 126:abea610beb85 2079 /******************************************************************************/
AnnaBridge 126:abea610beb85 2080 /*!<CAN control and status registers */
AnnaBridge 126:abea610beb85 2081 /******************* Bit definition for CAN_MCR register ********************/
AnnaBridge 126:abea610beb85 2082 #define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
AnnaBridge 126:abea610beb85 2083 #define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
AnnaBridge 126:abea610beb85 2084 #define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
AnnaBridge 126:abea610beb85 2085 #define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
AnnaBridge 126:abea610beb85 2086 #define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
AnnaBridge 126:abea610beb85 2087 #define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
AnnaBridge 126:abea610beb85 2088 #define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
AnnaBridge 126:abea610beb85 2089 #define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
AnnaBridge 126:abea610beb85 2090 #define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
AnnaBridge 126:abea610beb85 2091
AnnaBridge 126:abea610beb85 2092 /******************* Bit definition for CAN_MSR register ********************/
AnnaBridge 126:abea610beb85 2093 #define CAN_MSR_INAK 0x00000001U /*!<Initialization Acknowledge */
AnnaBridge 126:abea610beb85 2094 #define CAN_MSR_SLAK 0x00000002U /*!<Sleep Acknowledge */
AnnaBridge 126:abea610beb85 2095 #define CAN_MSR_ERRI 0x00000004U /*!<Error Interrupt */
AnnaBridge 126:abea610beb85 2096 #define CAN_MSR_WKUI 0x00000008U /*!<Wakeup Interrupt */
AnnaBridge 126:abea610beb85 2097 #define CAN_MSR_SLAKI 0x00000010U /*!<Sleep Acknowledge Interrupt */
AnnaBridge 126:abea610beb85 2098 #define CAN_MSR_TXM 0x00000100U /*!<Transmit Mode */
AnnaBridge 126:abea610beb85 2099 #define CAN_MSR_RXM 0x00000200U /*!<Receive Mode */
AnnaBridge 126:abea610beb85 2100 #define CAN_MSR_SAMP 0x00000400U /*!<Last Sample Point */
AnnaBridge 126:abea610beb85 2101 #define CAN_MSR_RX 0x00000800U /*!<CAN Rx Signal */
AnnaBridge 126:abea610beb85 2102
AnnaBridge 126:abea610beb85 2103 /******************* Bit definition for CAN_TSR register ********************/
AnnaBridge 126:abea610beb85 2104 #define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
AnnaBridge 126:abea610beb85 2105 #define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
AnnaBridge 126:abea610beb85 2106 #define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
AnnaBridge 126:abea610beb85 2107 #define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
AnnaBridge 126:abea610beb85 2108 #define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
AnnaBridge 126:abea610beb85 2109 #define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
AnnaBridge 126:abea610beb85 2110 #define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
AnnaBridge 126:abea610beb85 2111 #define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
AnnaBridge 126:abea610beb85 2112 #define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
AnnaBridge 126:abea610beb85 2113 #define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
AnnaBridge 126:abea610beb85 2114 #define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
AnnaBridge 126:abea610beb85 2115 #define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
AnnaBridge 126:abea610beb85 2116 #define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
AnnaBridge 126:abea610beb85 2117 #define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
AnnaBridge 126:abea610beb85 2118 #define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
AnnaBridge 126:abea610beb85 2119 #define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
AnnaBridge 126:abea610beb85 2120
AnnaBridge 126:abea610beb85 2121 #define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
AnnaBridge 126:abea610beb85 2122 #define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
AnnaBridge 126:abea610beb85 2123 #define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
AnnaBridge 126:abea610beb85 2124 #define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
AnnaBridge 126:abea610beb85 2125
AnnaBridge 126:abea610beb85 2126 #define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
AnnaBridge 126:abea610beb85 2127 #define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
AnnaBridge 126:abea610beb85 2128 #define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
AnnaBridge 126:abea610beb85 2129 #define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
AnnaBridge 126:abea610beb85 2130
AnnaBridge 126:abea610beb85 2131 /******************* Bit definition for CAN_RF0R register *******************/
AnnaBridge 126:abea610beb85 2132 #define CAN_RF0R_FMP0 0x00000003U /*!<FIFO 0 Message Pending */
AnnaBridge 126:abea610beb85 2133 #define CAN_RF0R_FULL0 0x00000008U /*!<FIFO 0 Full */
AnnaBridge 126:abea610beb85 2134 #define CAN_RF0R_FOVR0 0x00000010U /*!<FIFO 0 Overrun */
AnnaBridge 126:abea610beb85 2135 #define CAN_RF0R_RFOM0 0x00000020U /*!<Release FIFO 0 Output Mailbox */
AnnaBridge 126:abea610beb85 2136
AnnaBridge 126:abea610beb85 2137 /******************* Bit definition for CAN_RF1R register *******************/
AnnaBridge 126:abea610beb85 2138 #define CAN_RF1R_FMP1 0x00000003U /*!<FIFO 1 Message Pending */
AnnaBridge 126:abea610beb85 2139 #define CAN_RF1R_FULL1 0x00000008U /*!<FIFO 1 Full */
AnnaBridge 126:abea610beb85 2140 #define CAN_RF1R_FOVR1 0x00000010U /*!<FIFO 1 Overrun */
AnnaBridge 126:abea610beb85 2141 #define CAN_RF1R_RFOM1 0x00000020U /*!<Release FIFO 1 Output Mailbox */
AnnaBridge 126:abea610beb85 2142
AnnaBridge 126:abea610beb85 2143 /******************** Bit definition for CAN_IER register *******************/
AnnaBridge 126:abea610beb85 2144 #define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
AnnaBridge 126:abea610beb85 2145 #define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 126:abea610beb85 2146 #define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
AnnaBridge 126:abea610beb85 2147 #define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 126:abea610beb85 2148 #define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 126:abea610beb85 2149 #define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
AnnaBridge 126:abea610beb85 2150 #define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 126:abea610beb85 2151 #define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
AnnaBridge 126:abea610beb85 2152 #define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
AnnaBridge 126:abea610beb85 2153 #define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
AnnaBridge 126:abea610beb85 2154 #define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
AnnaBridge 126:abea610beb85 2155 #define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
AnnaBridge 126:abea610beb85 2156 #define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
AnnaBridge 126:abea610beb85 2157 #define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
AnnaBridge 126:abea610beb85 2158
AnnaBridge 126:abea610beb85 2159 /******************** Bit definition for CAN_ESR register *******************/
AnnaBridge 126:abea610beb85 2160 #define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
AnnaBridge 126:abea610beb85 2161 #define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
AnnaBridge 126:abea610beb85 2162 #define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
AnnaBridge 126:abea610beb85 2163
AnnaBridge 126:abea610beb85 2164 #define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
AnnaBridge 126:abea610beb85 2165 #define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 2166 #define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 2167 #define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 2168
AnnaBridge 126:abea610beb85 2169 #define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
AnnaBridge 126:abea610beb85 2170 #define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
AnnaBridge 126:abea610beb85 2171
AnnaBridge 126:abea610beb85 2172 /******************* Bit definition for CAN_BTR register ********************/
AnnaBridge 126:abea610beb85 2173 #define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
AnnaBridge 126:abea610beb85 2174 #define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
AnnaBridge 126:abea610beb85 2175 #define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 2176 #define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 2177 #define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 2178 #define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 2179 #define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
AnnaBridge 126:abea610beb85 2180 #define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 2181 #define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 2182 #define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 2183 #define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
AnnaBridge 126:abea610beb85 2184 #define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 2185 #define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 2186 #define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
AnnaBridge 126:abea610beb85 2187 #define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
AnnaBridge 126:abea610beb85 2188
AnnaBridge 126:abea610beb85 2189 /*!<Mailbox registers */
AnnaBridge 126:abea610beb85 2190 /****************** Bit definition for CAN_TI0R register ********************/
AnnaBridge 126:abea610beb85 2191 #define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
AnnaBridge 126:abea610beb85 2192 #define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
AnnaBridge 126:abea610beb85 2193 #define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
AnnaBridge 126:abea610beb85 2194 #define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
AnnaBridge 126:abea610beb85 2195 #define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
AnnaBridge 126:abea610beb85 2196
AnnaBridge 126:abea610beb85 2197 /****************** Bit definition for CAN_TDT0R register *******************/
AnnaBridge 126:abea610beb85 2198 #define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
AnnaBridge 126:abea610beb85 2199 #define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
AnnaBridge 126:abea610beb85 2200 #define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
AnnaBridge 126:abea610beb85 2201
AnnaBridge 126:abea610beb85 2202 /****************** Bit definition for CAN_TDL0R register *******************/
AnnaBridge 126:abea610beb85 2203 #define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
AnnaBridge 126:abea610beb85 2204 #define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
AnnaBridge 126:abea610beb85 2205 #define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
AnnaBridge 126:abea610beb85 2206 #define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
AnnaBridge 126:abea610beb85 2207
AnnaBridge 126:abea610beb85 2208 /****************** Bit definition for CAN_TDH0R register *******************/
AnnaBridge 126:abea610beb85 2209 #define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
AnnaBridge 126:abea610beb85 2210 #define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
AnnaBridge 126:abea610beb85 2211 #define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
AnnaBridge 126:abea610beb85 2212 #define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
AnnaBridge 126:abea610beb85 2213
AnnaBridge 126:abea610beb85 2214 /******************* Bit definition for CAN_TI1R register *******************/
AnnaBridge 126:abea610beb85 2215 #define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
AnnaBridge 126:abea610beb85 2216 #define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
AnnaBridge 126:abea610beb85 2217 #define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
AnnaBridge 126:abea610beb85 2218 #define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
AnnaBridge 126:abea610beb85 2219 #define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
AnnaBridge 126:abea610beb85 2220
AnnaBridge 126:abea610beb85 2221 /******************* Bit definition for CAN_TDT1R register ******************/
AnnaBridge 126:abea610beb85 2222 #define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
AnnaBridge 126:abea610beb85 2223 #define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
AnnaBridge 126:abea610beb85 2224 #define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
AnnaBridge 126:abea610beb85 2225
AnnaBridge 126:abea610beb85 2226 /******************* Bit definition for CAN_TDL1R register ******************/
AnnaBridge 126:abea610beb85 2227 #define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
AnnaBridge 126:abea610beb85 2228 #define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
AnnaBridge 126:abea610beb85 2229 #define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
AnnaBridge 126:abea610beb85 2230 #define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
AnnaBridge 126:abea610beb85 2231
AnnaBridge 126:abea610beb85 2232 /******************* Bit definition for CAN_TDH1R register ******************/
AnnaBridge 126:abea610beb85 2233 #define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
AnnaBridge 126:abea610beb85 2234 #define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
AnnaBridge 126:abea610beb85 2235 #define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
AnnaBridge 126:abea610beb85 2236 #define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
AnnaBridge 126:abea610beb85 2237
AnnaBridge 126:abea610beb85 2238 /******************* Bit definition for CAN_TI2R register *******************/
AnnaBridge 126:abea610beb85 2239 #define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
AnnaBridge 126:abea610beb85 2240 #define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
AnnaBridge 126:abea610beb85 2241 #define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
AnnaBridge 126:abea610beb85 2242 #define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
AnnaBridge 126:abea610beb85 2243 #define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
AnnaBridge 126:abea610beb85 2244
AnnaBridge 126:abea610beb85 2245 /******************* Bit definition for CAN_TDT2R register ******************/
AnnaBridge 126:abea610beb85 2246 #define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
AnnaBridge 126:abea610beb85 2247 #define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
AnnaBridge 126:abea610beb85 2248 #define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
AnnaBridge 126:abea610beb85 2249
AnnaBridge 126:abea610beb85 2250 /******************* Bit definition for CAN_TDL2R register ******************/
AnnaBridge 126:abea610beb85 2251 #define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
AnnaBridge 126:abea610beb85 2252 #define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
AnnaBridge 126:abea610beb85 2253 #define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
AnnaBridge 126:abea610beb85 2254 #define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
AnnaBridge 126:abea610beb85 2255
AnnaBridge 126:abea610beb85 2256 /******************* Bit definition for CAN_TDH2R register ******************/
AnnaBridge 126:abea610beb85 2257 #define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
AnnaBridge 126:abea610beb85 2258 #define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
AnnaBridge 126:abea610beb85 2259 #define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
AnnaBridge 126:abea610beb85 2260 #define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
AnnaBridge 126:abea610beb85 2261
AnnaBridge 126:abea610beb85 2262 /******************* Bit definition for CAN_RI0R register *******************/
AnnaBridge 126:abea610beb85 2263 #define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
AnnaBridge 126:abea610beb85 2264 #define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
AnnaBridge 126:abea610beb85 2265 #define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
AnnaBridge 126:abea610beb85 2266 #define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
AnnaBridge 126:abea610beb85 2267
AnnaBridge 126:abea610beb85 2268 /******************* Bit definition for CAN_RDT0R register ******************/
AnnaBridge 126:abea610beb85 2269 #define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
AnnaBridge 126:abea610beb85 2270 #define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
AnnaBridge 126:abea610beb85 2271 #define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
AnnaBridge 126:abea610beb85 2272
AnnaBridge 126:abea610beb85 2273 /******************* Bit definition for CAN_RDL0R register ******************/
AnnaBridge 126:abea610beb85 2274 #define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
AnnaBridge 126:abea610beb85 2275 #define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
AnnaBridge 126:abea610beb85 2276 #define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
AnnaBridge 126:abea610beb85 2277 #define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
AnnaBridge 126:abea610beb85 2278
AnnaBridge 126:abea610beb85 2279 /******************* Bit definition for CAN_RDH0R register ******************/
AnnaBridge 126:abea610beb85 2280 #define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
AnnaBridge 126:abea610beb85 2281 #define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
AnnaBridge 126:abea610beb85 2282 #define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
AnnaBridge 126:abea610beb85 2283 #define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
AnnaBridge 126:abea610beb85 2284
AnnaBridge 126:abea610beb85 2285 /******************* Bit definition for CAN_RI1R register *******************/
AnnaBridge 126:abea610beb85 2286 #define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
AnnaBridge 126:abea610beb85 2287 #define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
AnnaBridge 126:abea610beb85 2288 #define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
AnnaBridge 126:abea610beb85 2289 #define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
AnnaBridge 126:abea610beb85 2290
AnnaBridge 126:abea610beb85 2291 /******************* Bit definition for CAN_RDT1R register ******************/
AnnaBridge 126:abea610beb85 2292 #define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
AnnaBridge 126:abea610beb85 2293 #define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
AnnaBridge 126:abea610beb85 2294 #define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
AnnaBridge 126:abea610beb85 2295
AnnaBridge 126:abea610beb85 2296 /******************* Bit definition for CAN_RDL1R register ******************/
AnnaBridge 126:abea610beb85 2297 #define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
AnnaBridge 126:abea610beb85 2298 #define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
AnnaBridge 126:abea610beb85 2299 #define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
AnnaBridge 126:abea610beb85 2300 #define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
AnnaBridge 126:abea610beb85 2301
AnnaBridge 126:abea610beb85 2302 /******************* Bit definition for CAN_RDH1R register ******************/
AnnaBridge 126:abea610beb85 2303 #define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
AnnaBridge 126:abea610beb85 2304 #define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
AnnaBridge 126:abea610beb85 2305 #define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
AnnaBridge 126:abea610beb85 2306 #define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
AnnaBridge 126:abea610beb85 2307
AnnaBridge 126:abea610beb85 2308 /*!<CAN filter registers */
AnnaBridge 126:abea610beb85 2309 /******************* Bit definition for CAN_FMR register ********************/
AnnaBridge 126:abea610beb85 2310 #define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
AnnaBridge 126:abea610beb85 2311 #define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
AnnaBridge 126:abea610beb85 2312
AnnaBridge 126:abea610beb85 2313 /******************* Bit definition for CAN_FM1R register *******************/
AnnaBridge 126:abea610beb85 2314 #define CAN_FM1R_FBM 0x3FFFU /*!<Filter Mode */
AnnaBridge 126:abea610beb85 2315 #define CAN_FM1R_FBM0 0x0001U /*!<Filter Init Mode bit 0 */
AnnaBridge 126:abea610beb85 2316 #define CAN_FM1R_FBM1 0x0002U /*!<Filter Init Mode bit 1 */
AnnaBridge 126:abea610beb85 2317 #define CAN_FM1R_FBM2 0x0004U /*!<Filter Init Mode bit 2 */
AnnaBridge 126:abea610beb85 2318 #define CAN_FM1R_FBM3 0x0008U /*!<Filter Init Mode bit 3 */
AnnaBridge 126:abea610beb85 2319 #define CAN_FM1R_FBM4 0x0010U /*!<Filter Init Mode bit 4 */
AnnaBridge 126:abea610beb85 2320 #define CAN_FM1R_FBM5 0x0020U /*!<Filter Init Mode bit 5 */
AnnaBridge 126:abea610beb85 2321 #define CAN_FM1R_FBM6 0x0040U /*!<Filter Init Mode bit 6 */
AnnaBridge 126:abea610beb85 2322 #define CAN_FM1R_FBM7 0x0080U /*!<Filter Init Mode bit 7 */
AnnaBridge 126:abea610beb85 2323 #define CAN_FM1R_FBM8 0x0100U /*!<Filter Init Mode bit 8 */
AnnaBridge 126:abea610beb85 2324 #define CAN_FM1R_FBM9 0x0200U /*!<Filter Init Mode bit 9 */
AnnaBridge 126:abea610beb85 2325 #define CAN_FM1R_FBM10 0x0400U /*!<Filter Init Mode bit 10 */
AnnaBridge 126:abea610beb85 2326 #define CAN_FM1R_FBM11 0x0800U /*!<Filter Init Mode bit 11 */
AnnaBridge 126:abea610beb85 2327 #define CAN_FM1R_FBM12 0x1000U /*!<Filter Init Mode bit 12 */
AnnaBridge 126:abea610beb85 2328 #define CAN_FM1R_FBM13 0x2000U /*!<Filter Init Mode bit 13 */
AnnaBridge 126:abea610beb85 2329
AnnaBridge 126:abea610beb85 2330 /******************* Bit definition for CAN_FS1R register *******************/
AnnaBridge 126:abea610beb85 2331 #define CAN_FS1R_FSC 0x00003FFFU /*!<Filter Scale Configuration */
AnnaBridge 126:abea610beb85 2332 #define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
AnnaBridge 126:abea610beb85 2333 #define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
AnnaBridge 126:abea610beb85 2334 #define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
AnnaBridge 126:abea610beb85 2335 #define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
AnnaBridge 126:abea610beb85 2336 #define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
AnnaBridge 126:abea610beb85 2337 #define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
AnnaBridge 126:abea610beb85 2338 #define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
AnnaBridge 126:abea610beb85 2339 #define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
AnnaBridge 126:abea610beb85 2340 #define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
AnnaBridge 126:abea610beb85 2341 #define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
AnnaBridge 126:abea610beb85 2342 #define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
AnnaBridge 126:abea610beb85 2343 #define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
AnnaBridge 126:abea610beb85 2344 #define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
AnnaBridge 126:abea610beb85 2345 #define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
AnnaBridge 126:abea610beb85 2346
AnnaBridge 126:abea610beb85 2347 /****************** Bit definition for CAN_FFA1R register *******************/
AnnaBridge 126:abea610beb85 2348 #define CAN_FFA1R_FFA 0x00003FFFU /*!<Filter FIFO Assignment */
AnnaBridge 126:abea610beb85 2349 #define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment for Filter 0 */
AnnaBridge 126:abea610beb85 2350 #define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment for Filter 1 */
AnnaBridge 126:abea610beb85 2351 #define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment for Filter 2 */
AnnaBridge 126:abea610beb85 2352 #define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment for Filter 3 */
AnnaBridge 126:abea610beb85 2353 #define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment for Filter 4 */
AnnaBridge 126:abea610beb85 2354 #define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment for Filter 5 */
AnnaBridge 126:abea610beb85 2355 #define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment for Filter 6 */
AnnaBridge 126:abea610beb85 2356 #define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment for Filter 7 */
AnnaBridge 126:abea610beb85 2357 #define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment for Filter 8 */
AnnaBridge 126:abea610beb85 2358 #define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment for Filter 9 */
AnnaBridge 126:abea610beb85 2359 #define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment for Filter 10 */
AnnaBridge 126:abea610beb85 2360 #define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment for Filter 11 */
AnnaBridge 126:abea610beb85 2361 #define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment for Filter 12 */
AnnaBridge 126:abea610beb85 2362 #define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment for Filter 13 */
AnnaBridge 126:abea610beb85 2363
AnnaBridge 126:abea610beb85 2364 /******************* Bit definition for CAN_FA1R register *******************/
AnnaBridge 126:abea610beb85 2365 #define CAN_FA1R_FACT 0x00003FFFU /*!<Filter Active */
AnnaBridge 126:abea610beb85 2366 #define CAN_FA1R_FACT0 0x00000001U /*!<Filter 0 Active */
AnnaBridge 126:abea610beb85 2367 #define CAN_FA1R_FACT1 0x00000002U /*!<Filter 1 Active */
AnnaBridge 126:abea610beb85 2368 #define CAN_FA1R_FACT2 0x00000004U /*!<Filter 2 Active */
AnnaBridge 126:abea610beb85 2369 #define CAN_FA1R_FACT3 0x00000008U /*!<Filter 3 Active */
AnnaBridge 126:abea610beb85 2370 #define CAN_FA1R_FACT4 0x00000010U /*!<Filter 4 Active */
AnnaBridge 126:abea610beb85 2371 #define CAN_FA1R_FACT5 0x00000020U /*!<Filter 5 Active */
AnnaBridge 126:abea610beb85 2372 #define CAN_FA1R_FACT6 0x00000040U /*!<Filter 6 Active */
AnnaBridge 126:abea610beb85 2373 #define CAN_FA1R_FACT7 0x00000080U /*!<Filter 7 Active */
AnnaBridge 126:abea610beb85 2374 #define CAN_FA1R_FACT8 0x00000100U /*!<Filter 8 Active */
AnnaBridge 126:abea610beb85 2375 #define CAN_FA1R_FACT9 0x00000200U /*!<Filter 9 Active */
AnnaBridge 126:abea610beb85 2376 #define CAN_FA1R_FACT10 0x00000400U /*!<Filter 10 Active */
AnnaBridge 126:abea610beb85 2377 #define CAN_FA1R_FACT11 0x00000800U /*!<Filter 11 Active */
AnnaBridge 126:abea610beb85 2378 #define CAN_FA1R_FACT12 0x00001000U /*!<Filter 12 Active */
AnnaBridge 126:abea610beb85 2379 #define CAN_FA1R_FACT13 0x00002000U /*!<Filter 13 Active */
AnnaBridge 126:abea610beb85 2380
AnnaBridge 126:abea610beb85 2381 /******************* Bit definition for CAN_F0R1 register *******************/
AnnaBridge 126:abea610beb85 2382 #define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2383 #define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2384 #define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2385 #define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2386 #define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2387 #define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2388 #define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2389 #define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2390 #define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2391 #define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2392 #define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2393 #define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2394 #define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2395 #define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2396 #define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2397 #define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2398 #define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2399 #define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2400 #define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2401 #define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2402 #define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2403 #define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2404 #define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2405 #define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2406 #define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2407 #define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2408 #define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2409 #define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2410 #define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2411 #define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2412 #define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2413 #define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2414
AnnaBridge 126:abea610beb85 2415 /******************* Bit definition for CAN_F1R1 register *******************/
AnnaBridge 126:abea610beb85 2416 #define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2417 #define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2418 #define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2419 #define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2420 #define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2421 #define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2422 #define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2423 #define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2424 #define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2425 #define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2426 #define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2427 #define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2428 #define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2429 #define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2430 #define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2431 #define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2432 #define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2433 #define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2434 #define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2435 #define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2436 #define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2437 #define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2438 #define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2439 #define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2440 #define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2441 #define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2442 #define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2443 #define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2444 #define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2445 #define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2446 #define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2447 #define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2448
AnnaBridge 126:abea610beb85 2449 /******************* Bit definition for CAN_F2R1 register *******************/
AnnaBridge 126:abea610beb85 2450 #define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2451 #define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2452 #define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2453 #define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2454 #define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2455 #define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2456 #define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2457 #define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2458 #define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2459 #define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2460 #define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2461 #define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2462 #define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2463 #define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2464 #define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2465 #define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2466 #define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2467 #define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2468 #define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2469 #define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2470 #define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2471 #define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2472 #define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2473 #define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2474 #define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2475 #define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2476 #define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2477 #define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2478 #define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2479 #define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2480 #define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2481 #define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2482
AnnaBridge 126:abea610beb85 2483 /******************* Bit definition for CAN_F3R1 register *******************/
AnnaBridge 126:abea610beb85 2484 #define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2485 #define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2486 #define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2487 #define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2488 #define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2489 #define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2490 #define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2491 #define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2492 #define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2493 #define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2494 #define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2495 #define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2496 #define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2497 #define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2498 #define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2499 #define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2500 #define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2501 #define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2502 #define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2503 #define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2504 #define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2505 #define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2506 #define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2507 #define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2508 #define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2509 #define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2510 #define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2511 #define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2512 #define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2513 #define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2514 #define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2515 #define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2516
AnnaBridge 126:abea610beb85 2517 /******************* Bit definition for CAN_F4R1 register *******************/
AnnaBridge 126:abea610beb85 2518 #define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2519 #define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2520 #define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2521 #define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2522 #define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2523 #define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2524 #define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2525 #define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2526 #define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2527 #define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2528 #define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2529 #define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2530 #define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2531 #define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2532 #define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2533 #define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2534 #define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2535 #define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2536 #define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2537 #define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2538 #define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2539 #define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2540 #define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2541 #define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2542 #define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2543 #define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2544 #define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2545 #define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2546 #define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2547 #define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2548 #define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2549 #define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2550
AnnaBridge 126:abea610beb85 2551 /******************* Bit definition for CAN_F5R1 register *******************/
AnnaBridge 126:abea610beb85 2552 #define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2553 #define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2554 #define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2555 #define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2556 #define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2557 #define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2558 #define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2559 #define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2560 #define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2561 #define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2562 #define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2563 #define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2564 #define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2565 #define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2566 #define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2567 #define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2568 #define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2569 #define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2570 #define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2571 #define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2572 #define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2573 #define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2574 #define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2575 #define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2576 #define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2577 #define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2578 #define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2579 #define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2580 #define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2581 #define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2582 #define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2583 #define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2584
AnnaBridge 126:abea610beb85 2585 /******************* Bit definition for CAN_F6R1 register *******************/
AnnaBridge 126:abea610beb85 2586 #define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2587 #define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2588 #define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2589 #define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2590 #define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2591 #define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2592 #define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2593 #define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2594 #define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2595 #define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2596 #define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2597 #define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2598 #define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2599 #define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2600 #define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2601 #define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2602 #define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2603 #define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2604 #define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2605 #define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2606 #define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2607 #define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2608 #define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2609 #define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2610 #define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2611 #define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2612 #define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2613 #define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2614 #define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2615 #define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2616 #define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2617 #define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2618
AnnaBridge 126:abea610beb85 2619 /******************* Bit definition for CAN_F7R1 register *******************/
AnnaBridge 126:abea610beb85 2620 #define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2621 #define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2622 #define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2623 #define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2624 #define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2625 #define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2626 #define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2627 #define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2628 #define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2629 #define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2630 #define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2631 #define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2632 #define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2633 #define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2634 #define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2635 #define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2636 #define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2637 #define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2638 #define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2639 #define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2640 #define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2641 #define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2642 #define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2643 #define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2644 #define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2645 #define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2646 #define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2647 #define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2648 #define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2649 #define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2650 #define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2651 #define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2652
AnnaBridge 126:abea610beb85 2653 /******************* Bit definition for CAN_F8R1 register *******************/
AnnaBridge 126:abea610beb85 2654 #define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2655 #define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2656 #define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2657 #define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2658 #define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2659 #define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2660 #define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2661 #define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2662 #define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2663 #define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2664 #define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2665 #define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2666 #define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2667 #define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2668 #define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2669 #define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2670 #define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2671 #define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2672 #define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2673 #define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2674 #define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2675 #define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2676 #define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2677 #define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2678 #define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2679 #define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2680 #define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2681 #define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2682 #define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2683 #define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2684 #define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2685 #define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2686
AnnaBridge 126:abea610beb85 2687 /******************* Bit definition for CAN_F9R1 register *******************/
AnnaBridge 126:abea610beb85 2688 #define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2689 #define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2690 #define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2691 #define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2692 #define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2693 #define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2694 #define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2695 #define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2696 #define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2697 #define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2698 #define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2699 #define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2700 #define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2701 #define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2702 #define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2703 #define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2704 #define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2705 #define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2706 #define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2707 #define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2708 #define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2709 #define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2710 #define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2711 #define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2712 #define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2713 #define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2714 #define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2715 #define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2716 #define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2717 #define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2718 #define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2719 #define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2720
AnnaBridge 126:abea610beb85 2721 /******************* Bit definition for CAN_F10R1 register ******************/
AnnaBridge 126:abea610beb85 2722 #define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2723 #define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2724 #define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2725 #define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2726 #define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2727 #define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2728 #define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2729 #define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2730 #define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2731 #define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2732 #define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2733 #define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2734 #define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2735 #define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2736 #define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2737 #define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2738 #define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2739 #define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2740 #define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2741 #define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2742 #define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2743 #define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2744 #define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2745 #define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2746 #define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2747 #define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2748 #define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2749 #define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2750 #define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2751 #define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2752 #define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2753 #define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2754
AnnaBridge 126:abea610beb85 2755 /******************* Bit definition for CAN_F11R1 register ******************/
AnnaBridge 126:abea610beb85 2756 #define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2757 #define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2758 #define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2759 #define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2760 #define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2761 #define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2762 #define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2763 #define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2764 #define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2765 #define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2766 #define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2767 #define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2768 #define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2769 #define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2770 #define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2771 #define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2772 #define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2773 #define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2774 #define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2775 #define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2776 #define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2777 #define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2778 #define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2779 #define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2780 #define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2781 #define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2782 #define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2783 #define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2784 #define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2785 #define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2786 #define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2787 #define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2788
AnnaBridge 126:abea610beb85 2789 /******************* Bit definition for CAN_F12R1 register ******************/
AnnaBridge 126:abea610beb85 2790 #define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2791 #define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2792 #define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2793 #define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2794 #define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2795 #define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2796 #define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2797 #define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2798 #define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2799 #define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2800 #define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2801 #define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2802 #define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2803 #define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2804 #define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2805 #define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2806 #define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2807 #define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2808 #define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2809 #define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2810 #define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2811 #define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2812 #define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2813 #define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2814 #define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2815 #define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2816 #define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2817 #define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2818 #define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2819 #define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2820 #define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2821 #define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2822
AnnaBridge 126:abea610beb85 2823 /******************* Bit definition for CAN_F13R1 register ******************/
AnnaBridge 126:abea610beb85 2824 #define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2825 #define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2826 #define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2827 #define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2828 #define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2829 #define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2830 #define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2831 #define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2832 #define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2833 #define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2834 #define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2835 #define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2836 #define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2837 #define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2838 #define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2839 #define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2840 #define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2841 #define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2842 #define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2843 #define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2844 #define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2845 #define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2846 #define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2847 #define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2848 #define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2849 #define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2850 #define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2851 #define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2852 #define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2853 #define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2854 #define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2855 #define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2856
AnnaBridge 126:abea610beb85 2857 /******************* Bit definition for CAN_F0R2 register *******************/
AnnaBridge 126:abea610beb85 2858 #define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2859 #define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2860 #define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2861 #define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2862 #define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2863 #define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2864 #define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2865 #define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2866 #define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2867 #define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2868 #define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2869 #define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2870 #define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2871 #define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2872 #define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2873 #define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2874 #define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2875 #define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2876 #define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2877 #define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2878 #define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2879 #define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2880 #define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2881 #define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2882 #define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2883 #define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2884 #define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2885 #define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2886 #define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2887 #define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2888 #define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2889 #define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2890
AnnaBridge 126:abea610beb85 2891 /******************* Bit definition for CAN_F1R2 register *******************/
AnnaBridge 126:abea610beb85 2892 #define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2893 #define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2894 #define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2895 #define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2896 #define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2897 #define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2898 #define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2899 #define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2900 #define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2901 #define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2902 #define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2903 #define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2904 #define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2905 #define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2906 #define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2907 #define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2908 #define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2909 #define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2910 #define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2911 #define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2912 #define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2913 #define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2914 #define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2915 #define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2916 #define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2917 #define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2918 #define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2919 #define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2920 #define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2921 #define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2922 #define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2923 #define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2924
AnnaBridge 126:abea610beb85 2925 /******************* Bit definition for CAN_F2R2 register *******************/
AnnaBridge 126:abea610beb85 2926 #define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2927 #define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2928 #define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2929 #define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2930 #define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2931 #define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2932 #define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2933 #define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2934 #define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2935 #define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2936 #define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2937 #define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2938 #define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2939 #define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2940 #define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2941 #define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2942 #define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2943 #define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2944 #define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2945 #define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2946 #define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2947 #define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2948 #define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2949 #define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2950 #define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2951 #define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2952 #define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2953 #define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2954 #define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2955 #define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2956 #define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2957 #define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2958
AnnaBridge 126:abea610beb85 2959 /******************* Bit definition for CAN_F3R2 register *******************/
AnnaBridge 126:abea610beb85 2960 #define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2961 #define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2962 #define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2963 #define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2964 #define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2965 #define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 2966 #define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 2967 #define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 2968 #define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 2969 #define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 2970 #define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 2971 #define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 2972 #define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 2973 #define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 2974 #define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 2975 #define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 2976 #define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 2977 #define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 2978 #define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 2979 #define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 2980 #define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 2981 #define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 2982 #define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 2983 #define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 2984 #define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 2985 #define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 2986 #define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 2987 #define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 2988 #define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 2989 #define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 2990 #define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 2991 #define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 2992
AnnaBridge 126:abea610beb85 2993 /******************* Bit definition for CAN_F4R2 register *******************/
AnnaBridge 126:abea610beb85 2994 #define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 2995 #define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 2996 #define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 2997 #define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 2998 #define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 2999 #define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 3000 #define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 3001 #define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 3002 #define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 3003 #define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 3004 #define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 3005 #define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 3006 #define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 3007 #define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 3008 #define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 3009 #define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 3010 #define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 3011 #define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 3012 #define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 3013 #define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 3014 #define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 3015 #define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 3016 #define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 3017 #define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 3018 #define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 3019 #define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 3020 #define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 3021 #define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 3022 #define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 3023 #define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 3024 #define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 3025 #define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 3026
AnnaBridge 126:abea610beb85 3027 /******************* Bit definition for CAN_F5R2 register *******************/
AnnaBridge 126:abea610beb85 3028 #define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 3029 #define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 3030 #define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 3031 #define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 3032 #define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 3033 #define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 3034 #define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 3035 #define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 3036 #define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 3037 #define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 3038 #define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 3039 #define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 3040 #define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 3041 #define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 3042 #define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 3043 #define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 3044 #define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 3045 #define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 3046 #define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 3047 #define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 3048 #define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 3049 #define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 3050 #define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 3051 #define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 3052 #define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 3053 #define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 3054 #define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 3055 #define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 3056 #define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 3057 #define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 3058 #define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 3059 #define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 3060
AnnaBridge 126:abea610beb85 3061 /******************* Bit definition for CAN_F6R2 register *******************/
AnnaBridge 126:abea610beb85 3062 #define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 3063 #define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 3064 #define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 3065 #define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 3066 #define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 3067 #define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 3068 #define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 3069 #define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 3070 #define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 3071 #define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 3072 #define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 3073 #define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 3074 #define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 3075 #define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 3076 #define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 3077 #define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 3078 #define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 3079 #define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 3080 #define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 3081 #define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 3082 #define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 3083 #define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 3084 #define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 3085 #define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 3086 #define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 3087 #define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 3088 #define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 3089 #define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 3090 #define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 3091 #define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 3092 #define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 3093 #define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 3094
AnnaBridge 126:abea610beb85 3095 /******************* Bit definition for CAN_F7R2 register *******************/
AnnaBridge 126:abea610beb85 3096 #define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 3097 #define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 3098 #define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 3099 #define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 3100 #define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 3101 #define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 3102 #define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 3103 #define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 3104 #define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 3105 #define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 3106 #define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 3107 #define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 3108 #define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 3109 #define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 3110 #define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 3111 #define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 3112 #define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 3113 #define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 3114 #define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 3115 #define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 3116 #define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 3117 #define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 3118 #define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 3119 #define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 3120 #define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 3121 #define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 3122 #define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 3123 #define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 3124 #define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 3125 #define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 3126 #define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 3127 #define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 3128
AnnaBridge 126:abea610beb85 3129 /******************* Bit definition for CAN_F8R2 register *******************/
AnnaBridge 126:abea610beb85 3130 #define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 3131 #define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 3132 #define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 3133 #define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 3134 #define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 3135 #define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 3136 #define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 3137 #define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 3138 #define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 3139 #define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 3140 #define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 3141 #define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 3142 #define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 3143 #define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 3144 #define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 3145 #define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 3146 #define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 3147 #define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 3148 #define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 3149 #define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 3150 #define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 3151 #define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 3152 #define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 3153 #define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 3154 #define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 3155 #define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 3156 #define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 3157 #define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 3158 #define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 3159 #define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 3160 #define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 3161 #define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 3162
AnnaBridge 126:abea610beb85 3163 /******************* Bit definition for CAN_F9R2 register *******************/
AnnaBridge 126:abea610beb85 3164 #define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 3165 #define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 3166 #define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 3167 #define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 3168 #define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 3169 #define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 3170 #define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 3171 #define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 3172 #define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 3173 #define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 3174 #define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 3175 #define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 3176 #define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 3177 #define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 3178 #define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 3179 #define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 3180 #define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 3181 #define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 3182 #define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 3183 #define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 3184 #define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 3185 #define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 3186 #define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 3187 #define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 3188 #define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 3189 #define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 3190 #define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 3191 #define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 3192 #define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 3193 #define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 3194 #define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 3195 #define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 3196
AnnaBridge 126:abea610beb85 3197 /******************* Bit definition for CAN_F10R2 register ******************/
AnnaBridge 126:abea610beb85 3198 #define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 3199 #define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 3200 #define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 3201 #define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 3202 #define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 3203 #define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 3204 #define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 3205 #define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 3206 #define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 3207 #define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 3208 #define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 3209 #define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 3210 #define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 3211 #define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 3212 #define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 3213 #define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 3214 #define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 3215 #define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 3216 #define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 3217 #define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 3218 #define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 3219 #define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 3220 #define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 3221 #define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 3222 #define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 3223 #define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 3224 #define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 3225 #define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 3226 #define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 3227 #define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 3228 #define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 3229 #define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 3230
AnnaBridge 126:abea610beb85 3231 /******************* Bit definition for CAN_F11R2 register ******************/
AnnaBridge 126:abea610beb85 3232 #define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 3233 #define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 3234 #define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 3235 #define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 3236 #define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 3237 #define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 3238 #define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 3239 #define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 3240 #define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 3241 #define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 3242 #define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 3243 #define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 3244 #define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 3245 #define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 3246 #define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 3247 #define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 3248 #define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 3249 #define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 3250 #define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 3251 #define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 3252 #define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 3253 #define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 3254 #define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 3255 #define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 3256 #define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 3257 #define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 3258 #define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 3259 #define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 3260 #define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 3261 #define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 3262 #define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 3263 #define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 3264
AnnaBridge 126:abea610beb85 3265 /******************* Bit definition for CAN_F12R2 register ******************/
AnnaBridge 126:abea610beb85 3266 #define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 3267 #define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 3268 #define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 3269 #define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 3270 #define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 3271 #define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 3272 #define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 3273 #define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 3274 #define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 3275 #define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 3276 #define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 3277 #define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 3278 #define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 3279 #define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 3280 #define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 3281 #define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 3282 #define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 3283 #define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 3284 #define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 3285 #define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 3286 #define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 3287 #define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 3288 #define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 3289 #define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 3290 #define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 3291 #define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 3292 #define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 3293 #define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 3294 #define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 3295 #define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 3296 #define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 3297 #define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 3298
AnnaBridge 126:abea610beb85 3299 /******************* Bit definition for CAN_F13R2 register ******************/
AnnaBridge 126:abea610beb85 3300 #define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
AnnaBridge 126:abea610beb85 3301 #define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
AnnaBridge 126:abea610beb85 3302 #define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
AnnaBridge 126:abea610beb85 3303 #define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
AnnaBridge 126:abea610beb85 3304 #define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
AnnaBridge 126:abea610beb85 3305 #define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
AnnaBridge 126:abea610beb85 3306 #define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
AnnaBridge 126:abea610beb85 3307 #define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
AnnaBridge 126:abea610beb85 3308 #define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
AnnaBridge 126:abea610beb85 3309 #define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
AnnaBridge 126:abea610beb85 3310 #define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
AnnaBridge 126:abea610beb85 3311 #define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
AnnaBridge 126:abea610beb85 3312 #define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
AnnaBridge 126:abea610beb85 3313 #define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
AnnaBridge 126:abea610beb85 3314 #define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
AnnaBridge 126:abea610beb85 3315 #define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
AnnaBridge 126:abea610beb85 3316 #define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
AnnaBridge 126:abea610beb85 3317 #define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
AnnaBridge 126:abea610beb85 3318 #define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
AnnaBridge 126:abea610beb85 3319 #define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
AnnaBridge 126:abea610beb85 3320 #define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
AnnaBridge 126:abea610beb85 3321 #define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
AnnaBridge 126:abea610beb85 3322 #define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
AnnaBridge 126:abea610beb85 3323 #define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
AnnaBridge 126:abea610beb85 3324 #define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
AnnaBridge 126:abea610beb85 3325 #define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
AnnaBridge 126:abea610beb85 3326 #define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
AnnaBridge 126:abea610beb85 3327 #define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
AnnaBridge 126:abea610beb85 3328 #define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
AnnaBridge 126:abea610beb85 3329 #define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
AnnaBridge 126:abea610beb85 3330 #define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
AnnaBridge 126:abea610beb85 3331 #define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
AnnaBridge 126:abea610beb85 3332
AnnaBridge 126:abea610beb85 3333 /******************************************************************************/
AnnaBridge 126:abea610beb85 3334 /* */
AnnaBridge 126:abea610beb85 3335 /* HDMI-CEC (CEC) */
AnnaBridge 126:abea610beb85 3336 /* */
AnnaBridge 126:abea610beb85 3337 /******************************************************************************/
AnnaBridge 126:abea610beb85 3338
AnnaBridge 126:abea610beb85 3339 /******************* Bit definition for CEC_CR register *********************/
AnnaBridge 126:abea610beb85 3340 #define CEC_CR_CECEN 0x00000001U /*!< CEC Enable */
AnnaBridge 126:abea610beb85 3341 #define CEC_CR_TXSOM 0x00000002U /*!< CEC Tx Start Of Message */
AnnaBridge 126:abea610beb85 3342 #define CEC_CR_TXEOM 0x00000004U /*!< CEC Tx End Of Message */
AnnaBridge 126:abea610beb85 3343
AnnaBridge 126:abea610beb85 3344 /******************* Bit definition for CEC_CFGR register *******************/
AnnaBridge 126:abea610beb85 3345 #define CEC_CFGR_SFT 0x00000007U /*!< CEC Signal Free Time */
AnnaBridge 126:abea610beb85 3346 #define CEC_CFGR_RXTOL 0x00000008U /*!< CEC Tolerance */
AnnaBridge 126:abea610beb85 3347 #define CEC_CFGR_BRESTP 0x00000010U /*!< CEC Rx Stop */
AnnaBridge 126:abea610beb85 3348 #define CEC_CFGR_BREGEN 0x00000020U /*!< CEC Bit Rising Error generation */
AnnaBridge 126:abea610beb85 3349 #define CEC_CFGR_LBPEGEN 0x00000040U /*!< CEC Long Period Error generation */
AnnaBridge 126:abea610beb85 3350 #define CEC_CFGR_BRDNOGEN 0x00000080U /*!< CEC Broadcast no Error generation */
AnnaBridge 126:abea610beb85 3351 #define CEC_CFGR_SFTOPT 0x00000100U /*!< CEC Signal Free Time optional */
AnnaBridge 126:abea610beb85 3352 #define CEC_CFGR_OAR 0x7FFF0000U /*!< CEC Own Address */
AnnaBridge 126:abea610beb85 3353 #define CEC_CFGR_LSTN 0x80000000U /*!< CEC Listen mode */
AnnaBridge 126:abea610beb85 3354
AnnaBridge 126:abea610beb85 3355 /******************* Bit definition for CEC_TXDR register *******************/
AnnaBridge 126:abea610beb85 3356 #define CEC_TXDR_TXD 0x000000FFU /*!< CEC Tx Data */
AnnaBridge 126:abea610beb85 3357
AnnaBridge 126:abea610beb85 3358 /******************* Bit definition for CEC_RXDR register *******************/
AnnaBridge 126:abea610beb85 3359 #define CEC_TXDR_RXD 0x000000FFU /*!< CEC Rx Data */
AnnaBridge 126:abea610beb85 3360
AnnaBridge 126:abea610beb85 3361 /******************* Bit definition for CEC_ISR register ********************/
AnnaBridge 126:abea610beb85 3362 #define CEC_ISR_RXBR 0x00000001U /*!< CEC Rx-Byte Received */
AnnaBridge 126:abea610beb85 3363 #define CEC_ISR_RXEND 0x00000002U /*!< CEC End Of Reception */
AnnaBridge 126:abea610beb85 3364 #define CEC_ISR_RXOVR 0x00000004U /*!< CEC Rx-Overrun */
AnnaBridge 126:abea610beb85 3365 #define CEC_ISR_BRE 0x00000008U /*!< CEC Rx Bit Rising Error */
AnnaBridge 126:abea610beb85 3366 #define CEC_ISR_SBPE 0x00000010U /*!< CEC Rx Short Bit period Error */
AnnaBridge 126:abea610beb85 3367 #define CEC_ISR_LBPE 0x00000020U /*!< CEC Rx Long Bit period Error */
AnnaBridge 126:abea610beb85 3368 #define CEC_ISR_RXACKE 0x00000040U /*!< CEC Rx Missing Acknowledge */
AnnaBridge 126:abea610beb85 3369 #define CEC_ISR_ARBLST 0x00000080U /*!< CEC Arbitration Lost */
AnnaBridge 126:abea610beb85 3370 #define CEC_ISR_TXBR 0x00000100U /*!< CEC Tx Byte Request */
AnnaBridge 126:abea610beb85 3371 #define CEC_ISR_TXEND 0x00000200U /*!< CEC End of Transmission */
AnnaBridge 126:abea610beb85 3372 #define CEC_ISR_TXUDR 0x00000400U /*!< CEC Tx-Buffer Underrun */
AnnaBridge 126:abea610beb85 3373 #define CEC_ISR_TXERR 0x00000800U /*!< CEC Tx-Error */
AnnaBridge 126:abea610beb85 3374 #define CEC_ISR_TXACKE 0x00001000U /*!< CEC Tx Missing Acknowledge */
AnnaBridge 126:abea610beb85 3375
AnnaBridge 126:abea610beb85 3376 /******************* Bit definition for CEC_IER register ********************/
AnnaBridge 126:abea610beb85 3377 #define CEC_IER_RXBRIE 0x00000001U /*!< CEC Rx-Byte Received IT Enable */
AnnaBridge 126:abea610beb85 3378 #define CEC_IER_RXENDIE 0x00000002U /*!< CEC End Of Reception IT Enable */
AnnaBridge 126:abea610beb85 3379 #define CEC_IER_RXOVRIE 0x00000004U /*!< CEC Rx-Overrun IT Enable */
AnnaBridge 126:abea610beb85 3380 #define CEC_IER_BREIE 0x00000008U /*!< CEC Rx Bit Rising Error IT Enable */
AnnaBridge 126:abea610beb85 3381 #define CEC_IER_SBPEIE 0x00000010U /*!< CEC Rx Short Bit period Error IT Enable*/
AnnaBridge 126:abea610beb85 3382 #define CEC_IER_LBPEIE 0x00000020U /*!< CEC Rx Long Bit period Error IT Enable */
AnnaBridge 126:abea610beb85 3383 #define CEC_IER_RXACKEIE 0x00000040U /*!< CEC Rx Missing Acknowledge IT Enable */
AnnaBridge 126:abea610beb85 3384 #define CEC_IER_ARBLSTIE 0x00000080U /*!< CEC Arbitration Lost IT Enable */
AnnaBridge 126:abea610beb85 3385 #define CEC_IER_TXBRIE 0x00000100U /*!< CEC Tx Byte Request IT Enable */
AnnaBridge 126:abea610beb85 3386 #define CEC_IER_TXENDIE 0x00000200U /*!< CEC End of Transmission IT Enable */
AnnaBridge 126:abea610beb85 3387 #define CEC_IER_TXUDRIE 0x00000400U /*!< CEC Tx-Buffer Underrun IT Enable */
AnnaBridge 126:abea610beb85 3388 #define CEC_IER_TXERRIE 0x00000800U /*!< CEC Tx-Error IT Enable */
AnnaBridge 126:abea610beb85 3389 #define CEC_IER_TXACKEIE 0x00001000U /*!< CEC Tx Missing Acknowledge IT Enable */
AnnaBridge 126:abea610beb85 3390
AnnaBridge 126:abea610beb85 3391 /******************************************************************************/
AnnaBridge 126:abea610beb85 3392 /* */
AnnaBridge 126:abea610beb85 3393 /* CRC calculation unit */
AnnaBridge 126:abea610beb85 3394 /* */
AnnaBridge 126:abea610beb85 3395 /******************************************************************************/
AnnaBridge 126:abea610beb85 3396 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 126:abea610beb85 3397 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
AnnaBridge 126:abea610beb85 3398
AnnaBridge 126:abea610beb85 3399 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 126:abea610beb85 3400 #define CRC_IDR_IDR 0x000000FFU /*!< General-purpose 8-bit data register bits */
AnnaBridge 126:abea610beb85 3401
AnnaBridge 126:abea610beb85 3402 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 126:abea610beb85 3403 #define CRC_CR_RESET 0x00000001U /*!< RESET the CRC computation unit bit */
AnnaBridge 126:abea610beb85 3404 #define CRC_CR_POLYSIZE 0x00000018U /*!< Polynomial size bits */
AnnaBridge 126:abea610beb85 3405 #define CRC_CR_POLYSIZE_0 0x00000008U /*!< Polynomial size bit 0 */
AnnaBridge 126:abea610beb85 3406 #define CRC_CR_POLYSIZE_1 0x00000010U /*!< Polynomial size bit 1 */
AnnaBridge 126:abea610beb85 3407 #define CRC_CR_REV_IN 0x00000060U /*!< REV_IN Reverse Input Data bits */
AnnaBridge 126:abea610beb85 3408 #define CRC_CR_REV_IN_0 0x00000020U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 3409 #define CRC_CR_REV_IN_1 0x00000040U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 3410 #define CRC_CR_REV_OUT 0x00000080U /*!< REV_OUT Reverse Output Data bits */
AnnaBridge 126:abea610beb85 3411
AnnaBridge 126:abea610beb85 3412 /******************* Bit definition for CRC_INIT register *******************/
AnnaBridge 126:abea610beb85 3413 #define CRC_INIT_INIT 0xFFFFFFFFU /*!< Initial CRC value bits */
AnnaBridge 126:abea610beb85 3414
AnnaBridge 126:abea610beb85 3415 /******************* Bit definition for CRC_POL register ********************/
AnnaBridge 126:abea610beb85 3416 #define CRC_POL_POL 0xFFFFFFFFU /*!< Coefficients of the polynomial */
AnnaBridge 126:abea610beb85 3417
AnnaBridge 126:abea610beb85 3418
AnnaBridge 126:abea610beb85 3419 /******************************************************************************/
AnnaBridge 126:abea610beb85 3420 /* */
AnnaBridge 126:abea610beb85 3421 /* Digital to Analog Converter */
AnnaBridge 126:abea610beb85 3422 /* */
AnnaBridge 126:abea610beb85 3423 /******************************************************************************/
AnnaBridge 126:abea610beb85 3424 /******************** Bit definition for DAC_CR register ********************/
AnnaBridge 126:abea610beb85 3425 #define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
AnnaBridge 126:abea610beb85 3426 #define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
AnnaBridge 126:abea610beb85 3427 #define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
AnnaBridge 126:abea610beb85 3428 #define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
AnnaBridge 126:abea610beb85 3429 #define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 3430 #define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 3431 #define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 3432 #define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
AnnaBridge 126:abea610beb85 3433 #define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 3434 #define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 3435 #define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
AnnaBridge 126:abea610beb85 3436 #define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 3437 #define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 3438 #define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 3439 #define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 3440 #define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
AnnaBridge 126:abea610beb85 3441 #define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable */
AnnaBridge 126:abea610beb85 3442 #define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
AnnaBridge 126:abea610beb85 3443 #define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
AnnaBridge 126:abea610beb85 3444 #define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
AnnaBridge 126:abea610beb85 3445 #define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
AnnaBridge 126:abea610beb85 3446 #define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 3447 #define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 3448 #define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 3449 #define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
AnnaBridge 126:abea610beb85 3450 #define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 3451 #define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 3452 #define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
AnnaBridge 126:abea610beb85 3453 #define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 3454 #define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 3455 #define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 3456 #define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 3457 #define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enable */
AnnaBridge 126:abea610beb85 3458 #define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable */
AnnaBridge 126:abea610beb85 3459
AnnaBridge 126:abea610beb85 3460 /***************** Bit definition for DAC_SWTRIGR register ******************/
AnnaBridge 126:abea610beb85 3461 #define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
AnnaBridge 126:abea610beb85 3462 #define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
AnnaBridge 126:abea610beb85 3463
AnnaBridge 126:abea610beb85 3464 /***************** Bit definition for DAC_DHR12R1 register ******************/
AnnaBridge 126:abea610beb85 3465 #define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 126:abea610beb85 3466
AnnaBridge 126:abea610beb85 3467 /***************** Bit definition for DAC_DHR12L1 register ******************/
AnnaBridge 126:abea610beb85 3468 #define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 126:abea610beb85 3469
AnnaBridge 126:abea610beb85 3470 /****************** Bit definition for DAC_DHR8R1 register ******************/
AnnaBridge 126:abea610beb85 3471 #define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 126:abea610beb85 3472
AnnaBridge 126:abea610beb85 3473 /***************** Bit definition for DAC_DHR12R2 register ******************/
AnnaBridge 126:abea610beb85 3474 #define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 126:abea610beb85 3475
AnnaBridge 126:abea610beb85 3476 /***************** Bit definition for DAC_DHR12L2 register ******************/
AnnaBridge 126:abea610beb85 3477 #define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 126:abea610beb85 3478
AnnaBridge 126:abea610beb85 3479 /****************** Bit definition for DAC_DHR8R2 register ******************/
AnnaBridge 126:abea610beb85 3480 #define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 126:abea610beb85 3481
AnnaBridge 126:abea610beb85 3482 /***************** Bit definition for DAC_DHR12RD register ******************/
AnnaBridge 126:abea610beb85 3483 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 126:abea610beb85 3484 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 126:abea610beb85 3485
AnnaBridge 126:abea610beb85 3486 /***************** Bit definition for DAC_DHR12LD register ******************/
AnnaBridge 126:abea610beb85 3487 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 126:abea610beb85 3488 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 126:abea610beb85 3489
AnnaBridge 126:abea610beb85 3490 /****************** Bit definition for DAC_DHR8RD register ******************/
AnnaBridge 126:abea610beb85 3491 #define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 126:abea610beb85 3492 #define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 126:abea610beb85 3493
AnnaBridge 126:abea610beb85 3494 /******************* Bit definition for DAC_DOR1 register *******************/
AnnaBridge 126:abea610beb85 3495 #define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
AnnaBridge 126:abea610beb85 3496
AnnaBridge 126:abea610beb85 3497 /******************* Bit definition for DAC_DOR2 register *******************/
AnnaBridge 126:abea610beb85 3498 #define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
AnnaBridge 126:abea610beb85 3499
AnnaBridge 126:abea610beb85 3500 /******************** Bit definition for DAC_SR register ********************/
AnnaBridge 126:abea610beb85 3501 #define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
AnnaBridge 126:abea610beb85 3502 #define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
AnnaBridge 126:abea610beb85 3503
AnnaBridge 126:abea610beb85 3504 /******************************************************************************/
AnnaBridge 126:abea610beb85 3505 /* */
AnnaBridge 126:abea610beb85 3506 /* Digital Filter for Sigma Delta Modulators */
AnnaBridge 126:abea610beb85 3507 /* */
AnnaBridge 126:abea610beb85 3508 /******************************************************************************/
AnnaBridge 126:abea610beb85 3509
AnnaBridge 126:abea610beb85 3510 /**************** DFSDM channel configuration registers ********************/
AnnaBridge 126:abea610beb85 3511
AnnaBridge 126:abea610beb85 3512 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
AnnaBridge 126:abea610beb85 3513 #define DFSDM_CHCFGR1_DFSDMEN 0x80000000U /*!< Global enable for DFSDM interface */
AnnaBridge 126:abea610beb85 3514 #define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U /*!< Output serial clock source selection */
AnnaBridge 126:abea610beb85 3515 #define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U /*!< CKOUTDIV[7:0] output serial clock divider */
AnnaBridge 126:abea610beb85 3516 #define DFSDM_CHCFGR1_DATPACK 0x0000C000U /*!< DATPACK[1:0] Data packing mode */
AnnaBridge 126:abea610beb85 3517 #define DFSDM_CHCFGR1_DATPACK_1 0x00008000U /*!< Data packing mode, Bit 1 */
AnnaBridge 126:abea610beb85 3518 #define DFSDM_CHCFGR1_DATPACK_0 0x00004000U /*!< Data packing mode, Bit 0 */
AnnaBridge 126:abea610beb85 3519 #define DFSDM_CHCFGR1_DATMPX 0x00003000U /*!< DATMPX[1:0] Input data multiplexer for channel y */
AnnaBridge 126:abea610beb85 3520 #define DFSDM_CHCFGR1_DATMPX_1 0x00002000U /*!< Input data multiplexer for channel y, Bit 1 */
AnnaBridge 126:abea610beb85 3521 #define DFSDM_CHCFGR1_DATMPX_0 0x00001000U /*!< Input data multiplexer for channel y, Bit 0 */
AnnaBridge 126:abea610beb85 3522 #define DFSDM_CHCFGR1_CHINSEL 0x00000100U /*!< Serial inputs selection for channel y */
AnnaBridge 126:abea610beb85 3523 #define DFSDM_CHCFGR1_CHEN 0x00000080U /*!< Channel y enable */
AnnaBridge 126:abea610beb85 3524 #define DFSDM_CHCFGR1_CKABEN 0x00000040U /*!< Clock absence detector enable on channel y */
AnnaBridge 126:abea610beb85 3525 #define DFSDM_CHCFGR1_SCDEN 0x00000020U /*!< Short circuit detector enable on channel y */
AnnaBridge 126:abea610beb85 3526 #define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU /*!< SPICKSEL[1:0] SPI clock select for channel y */
AnnaBridge 126:abea610beb85 3527 #define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U /*!< SPI clock select for channel y, Bit 1 */
AnnaBridge 126:abea610beb85 3528 #define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U /*!< SPI clock select for channel y, Bit 0 */
AnnaBridge 126:abea610beb85 3529 #define DFSDM_CHCFGR1_SITP 0x00000003U /*!< SITP[1:0] Serial interface type for channel y */
AnnaBridge 126:abea610beb85 3530 #define DFSDM_CHCFGR1_SITP_1 0x00000002U /*!< Serial interface type for channel y, Bit 1 */
AnnaBridge 126:abea610beb85 3531 #define DFSDM_CHCFGR1_SITP_0 0x00000001U /*!< Serial interface type for channel y, Bit 0 */
AnnaBridge 126:abea610beb85 3532
AnnaBridge 126:abea610beb85 3533 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
AnnaBridge 126:abea610beb85 3534 #define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
AnnaBridge 126:abea610beb85 3535 #define DFSDM_CHCFGR2_DTRBS 0x000000F8U /*!< DTRBS[4:0] Data right bit-shift for channel y */
AnnaBridge 126:abea610beb85 3536
AnnaBridge 126:abea610beb85 3537 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
AnnaBridge 126:abea610beb85 3538 #define DFSDM_CHAWSCDR_AWFORD 0x00C00000U /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
AnnaBridge 126:abea610beb85 3539 #define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
AnnaBridge 126:abea610beb85 3540 #define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
AnnaBridge 126:abea610beb85 3541 #define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
AnnaBridge 126:abea610beb85 3542 #define DFSDM_CHAWSCDR_BKSCD 0x0000F000U /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
AnnaBridge 126:abea610beb85 3543 #define DFSDM_CHAWSCDR_SCDT 0x000000FFU /*!< SCDT[7:0] Short circuit detector threshold for channel y */
AnnaBridge 126:abea610beb85 3544
AnnaBridge 126:abea610beb85 3545 /**************** Bit definition for DFSDM_CHWDATR register *******************/
AnnaBridge 126:abea610beb85 3546 #define DFSDM_CHWDATR_WDATA 0x0000FFFFU /*!< WDATA[15:0] Input channel y watchdog data */
AnnaBridge 126:abea610beb85 3547
AnnaBridge 126:abea610beb85 3548 /**************** Bit definition for DFSDM_CHDATINR register *****************/
AnnaBridge 126:abea610beb85 3549 #define DFSDM_CHDATINR_INDAT0 0x0000FFFFU /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
AnnaBridge 126:abea610beb85 3550 #define DFSDM_CHDATINR_INDAT1 0xFFFF0000U /*!< INDAT0[15:0] Input data for channel y */
AnnaBridge 126:abea610beb85 3551
AnnaBridge 126:abea610beb85 3552 /************************ DFSDM module registers ****************************/
AnnaBridge 126:abea610beb85 3553
AnnaBridge 126:abea610beb85 3554 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
AnnaBridge 126:abea610beb85 3555 #define DFSDM_FLTCR1_AWFSEL 0x40000000U /*!< Analog watchdog fast mode select */
AnnaBridge 126:abea610beb85 3556 #define DFSDM_FLTCR1_FAST 0x20000000U /*!< Fast conversion mode selection */
AnnaBridge 126:abea610beb85 3557 #define DFSDM_FLTCR1_RCH 0x07000000U /*!< RCH[2:0] Regular channel selection */
AnnaBridge 126:abea610beb85 3558 #define DFSDM_FLTCR1_RDMAEN 0x00200000U /*!< DMA channel enabled to read data for the regular conversion */
AnnaBridge 126:abea610beb85 3559 #define DFSDM_FLTCR1_RSYNC 0x00080000U /*!< Launch regular conversion synchronously with DFSDMx */
AnnaBridge 126:abea610beb85 3560 #define DFSDM_FLTCR1_RCONT 0x00040000U /*!< Continuous mode selection for regular conversions */
AnnaBridge 126:abea610beb85 3561 #define DFSDM_FLTCR1_RSWSTART 0x00020000U /*!< Software start of a conversion on the regular channel */
AnnaBridge 126:abea610beb85 3562 #define DFSDM_FLTCR1_JEXTEN 0x00006000U /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
AnnaBridge 126:abea610beb85 3563 #define DFSDM_FLTCR1_JEXTEN_1 0x00004000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
AnnaBridge 126:abea610beb85 3564 #define DFSDM_FLTCR1_JEXTEN_0 0x00002000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
AnnaBridge 126:abea610beb85 3565 #define DFSDM_FLTCR1_JEXTSEL 0x00001F00U /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
AnnaBridge 126:abea610beb85 3566 #define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U /*!< Trigger signal selection for launching injected conversions, Bit 0 */
AnnaBridge 126:abea610beb85 3567 #define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U /*!< Trigger signal selection for launching injected conversions, Bit 1 */
AnnaBridge 126:abea610beb85 3568 #define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U /*!< Trigger signal selection for launching injected conversions, Bit 2 */
AnnaBridge 126:abea610beb85 3569 #define DFSDM_FLTCR1_JEXTSEL_3 0x00000800U /*!< Trigger signal selection for launching injected conversions, Bit 3 */
AnnaBridge 126:abea610beb85 3570 #define DFSDM_FLTCR1_JEXTSEL_4 0x00001000U /*!< Trigger signal selection for launching injected conversions, Bit 4 */
AnnaBridge 126:abea610beb85 3571 #define DFSDM_FLTCR1_JDMAEN 0x00000020U /*!< DMA channel enabled to read data for the injected channel group */
AnnaBridge 126:abea610beb85 3572 #define DFSDM_FLTCR1_JSCAN 0x00000010U /*!< Scanning conversion in continuous mode selection for injected conversions */
AnnaBridge 126:abea610beb85 3573 #define DFSDM_FLTCR1_JSYNC 0x00000008U /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
AnnaBridge 126:abea610beb85 3574 #define DFSDM_FLTCR1_JSWSTART 0x00000002U /*!< Start the conversion of the injected group of channels */
AnnaBridge 126:abea610beb85 3575 #define DFSDM_FLTCR1_DFEN 0x00000001U /*!< DFSDM enable */
AnnaBridge 126:abea610beb85 3576
AnnaBridge 126:abea610beb85 3577 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
AnnaBridge 126:abea610beb85 3578 #define DFSDM_FLTCR2_AWDCH 0x00FF0000U /*!< AWDCH[7:0] Analog watchdog channel selection */
AnnaBridge 126:abea610beb85 3579 #define DFSDM_FLTCR2_EXCH 0x0000FF00U /*!< EXCH[7:0] Extreme detector channel selection */
AnnaBridge 126:abea610beb85 3580 #define DFSDM_FLTCR2_CKABIE 0x00000040U /*!< Clock absence interrupt enable */
AnnaBridge 126:abea610beb85 3581 #define DFSDM_FLTCR2_SCDIE 0x00000020U /*!< Short circuit detector interrupt enable */
AnnaBridge 126:abea610beb85 3582 #define DFSDM_FLTCR2_AWDIE 0x00000010U /*!< Analog watchdog interrupt enable */
AnnaBridge 126:abea610beb85 3583 #define DFSDM_FLTCR2_ROVRIE 0x00000008U /*!< Regular data overrun interrupt enable */
AnnaBridge 126:abea610beb85 3584 #define DFSDM_FLTCR2_JOVRIE 0x00000004U /*!< Injected data overrun interrupt enable */
AnnaBridge 126:abea610beb85 3585 #define DFSDM_FLTCR2_REOCIE 0x00000002U /*!< Regular end of conversion interrupt enable */
AnnaBridge 126:abea610beb85 3586 #define DFSDM_FLTCR2_JEOCIE 0x00000001U /*!< Injected end of conversion interrupt enable */
AnnaBridge 126:abea610beb85 3587
AnnaBridge 126:abea610beb85 3588 /******************** Bit definition for DFSDM_FLTISR register *******************/
AnnaBridge 126:abea610beb85 3589 #define DFSDM_FLTISR_SCDF 0xFF000000U /*!< SCDF[7:0] Short circuit detector flag */
AnnaBridge 126:abea610beb85 3590 #define DFSDM_FLTISR_CKABF 0x00FF0000U /*!< CKABF[7:0] Clock absence flag */
AnnaBridge 126:abea610beb85 3591 #define DFSDM_FLTISR_RCIP 0x00004000U /*!< Regular conversion in progress status */
AnnaBridge 126:abea610beb85 3592 #define DFSDM_FLTISR_JCIP 0x00002000U /*!< Injected conversion in progress status */
AnnaBridge 126:abea610beb85 3593 #define DFSDM_FLTISR_AWDF 0x00000010U /*!< Analog watchdog */
AnnaBridge 126:abea610beb85 3594 #define DFSDM_FLTISR_ROVRF 0x00000008U /*!< Regular conversion overrun flag */
AnnaBridge 126:abea610beb85 3595 #define DFSDM_FLTISR_JOVRF 0x00000004U /*!< Injected conversion overrun flag */
AnnaBridge 126:abea610beb85 3596 #define DFSDM_FLTISR_REOCF 0x00000002U /*!< End of regular conversion flag */
AnnaBridge 126:abea610beb85 3597 #define DFSDM_FLTISR_JEOCF 0x00000001U /*!< End of injected conversion flag */
AnnaBridge 126:abea610beb85 3598
AnnaBridge 126:abea610beb85 3599 /******************** Bit definition for DFSDM_FLTICR register *******************/
AnnaBridge 126:abea610beb85 3600 #define DFSDM_FLTICR_CLRSCSDF 0xFF000000U /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
AnnaBridge 126:abea610beb85 3601 #define DFSDM_FLTICR_CLRCKABF 0x00FF0000U /*!< CLRCKABF[7:0] Clear the clock absence flag */
AnnaBridge 126:abea610beb85 3602 #define DFSDM_FLTICR_CLRROVRF 0x00000008U /*!< Clear the regular conversion overrun flag */
AnnaBridge 126:abea610beb85 3603 #define DFSDM_FLTICR_CLRJOVRF 0x00000004U /*!< Clear the injected conversion overrun flag */
AnnaBridge 126:abea610beb85 3604
AnnaBridge 126:abea610beb85 3605 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
AnnaBridge 126:abea610beb85 3606 #define DFSDM_FLTJCHGR_JCHG 0x000000FFU /*!< JCHG[7:0] Injected channel group selection */
AnnaBridge 126:abea610beb85 3607
AnnaBridge 126:abea610beb85 3608 /******************** Bit definition for DFSDM_FLTFCR register *******************/
AnnaBridge 126:abea610beb85 3609 #define DFSDM_FLTFCR_FORD 0xE0000000U /*!< FORD[2:0] Sinc filter order */
AnnaBridge 126:abea610beb85 3610 #define DFSDM_FLTFCR_FORD_2 0x80000000U /*!< Sinc filter order, Bit 2 */
AnnaBridge 126:abea610beb85 3611 #define DFSDM_FLTFCR_FORD_1 0x40000000U /*!< Sinc filter order, Bit 1 */
AnnaBridge 126:abea610beb85 3612 #define DFSDM_FLTFCR_FORD_0 0x20000000U /*!< Sinc filter order, Bit 0 */
AnnaBridge 126:abea610beb85 3613 #define DFSDM_FLTFCR_FOSR 0x03FF0000U /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
AnnaBridge 126:abea610beb85 3614 #define DFSDM_FLTFCR_IOSR 0x000000FFU /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
AnnaBridge 126:abea610beb85 3615
AnnaBridge 126:abea610beb85 3616 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
AnnaBridge 126:abea610beb85 3617 #define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U /*!< JDATA[23:0] Injected group conversion data */
AnnaBridge 126:abea610beb85 3618 #define DFSDM_FLTJDATAR_JDATACH 0x00000007U /*!< JDATACH[2:0] Injected channel most recently converted */
AnnaBridge 126:abea610beb85 3619
AnnaBridge 126:abea610beb85 3620 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
AnnaBridge 126:abea610beb85 3621 #define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U /*!< RDATA[23:0] Regular channel conversion data */
AnnaBridge 126:abea610beb85 3622 #define DFSDM_FLTRDATAR_RPEND 0x00000010U /*!< RPEND Regular channel pending data */
AnnaBridge 126:abea610beb85 3623 #define DFSDM_FLTRDATAR_RDATACH 0x00000007U /*!< RDATACH[2:0] Regular channel most recently converted */
AnnaBridge 126:abea610beb85 3624
AnnaBridge 126:abea610beb85 3625 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
AnnaBridge 126:abea610beb85 3626 #define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U /*!< AWHT[23:0] Analog watchdog high threshold */
AnnaBridge 126:abea610beb85 3627 #define DFSDM_FLTAWHTR_BKAWH 0x0000000FU /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
AnnaBridge 126:abea610beb85 3628
AnnaBridge 126:abea610beb85 3629 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
AnnaBridge 126:abea610beb85 3630 #define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U /*!< AWLT[23:0] Analog watchdog low threshold */
AnnaBridge 126:abea610beb85 3631 #define DFSDM_FLTAWLTR_BKAWL 0x0000000FU /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
AnnaBridge 126:abea610beb85 3632
AnnaBridge 126:abea610beb85 3633 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
AnnaBridge 126:abea610beb85 3634 #define DFSDM_FLTAWSR_AWHTF 0x0000FF00U /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
AnnaBridge 126:abea610beb85 3635 #define DFSDM_FLTAWSR_AWLTF 0x000000FFU /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
AnnaBridge 126:abea610beb85 3636
AnnaBridge 126:abea610beb85 3637 /****************** Bit definition for DFSDM_FLTAWCFR register *****************/
AnnaBridge 126:abea610beb85 3638 #define DFSDM_FLTAWCFR_CLRAWHTF 0x0000FF00U /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
AnnaBridge 126:abea610beb85 3639 #define DFSDM_FLTAWCFR_CLRAWLTF 0x000000FFU /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
AnnaBridge 126:abea610beb85 3640
AnnaBridge 126:abea610beb85 3641 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
AnnaBridge 126:abea610beb85 3642 #define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U /*!< EXMAX[23:0] Extreme detector maximum value */
AnnaBridge 126:abea610beb85 3643 #define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
AnnaBridge 126:abea610beb85 3644
AnnaBridge 126:abea610beb85 3645 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
AnnaBridge 126:abea610beb85 3646 #define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U /*!< EXMIN[23:0] Extreme detector minimum value */
AnnaBridge 126:abea610beb85 3647 #define DFSDM_FLTEXMIN_EXMINCH 0x00000007U /*!< EXMINCH[2:0] Extreme detector minimum data channel */
AnnaBridge 126:abea610beb85 3648
AnnaBridge 126:abea610beb85 3649 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
AnnaBridge 126:abea610beb85 3650 #define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
AnnaBridge 126:abea610beb85 3651
AnnaBridge 126:abea610beb85 3652 /******************************************************************************/
AnnaBridge 126:abea610beb85 3653 /* */
AnnaBridge 126:abea610beb85 3654 /* Debug MCU */
AnnaBridge 126:abea610beb85 3655 /* */
AnnaBridge 126:abea610beb85 3656 /******************************************************************************/
AnnaBridge 126:abea610beb85 3657
AnnaBridge 126:abea610beb85 3658 /******************************************************************************/
AnnaBridge 126:abea610beb85 3659 /* */
AnnaBridge 126:abea610beb85 3660 /* DCMI */
AnnaBridge 126:abea610beb85 3661 /* */
AnnaBridge 126:abea610beb85 3662 /******************************************************************************/
AnnaBridge 126:abea610beb85 3663 /******************** Bits definition for DCMI_CR register ******************/
AnnaBridge 126:abea610beb85 3664 #define DCMI_CR_CAPTURE 0x00000001U
AnnaBridge 126:abea610beb85 3665 #define DCMI_CR_CM 0x00000002U
AnnaBridge 126:abea610beb85 3666 #define DCMI_CR_CROP 0x00000004U
AnnaBridge 126:abea610beb85 3667 #define DCMI_CR_JPEG 0x00000008U
AnnaBridge 126:abea610beb85 3668 #define DCMI_CR_ESS 0x00000010U
AnnaBridge 126:abea610beb85 3669 #define DCMI_CR_PCKPOL 0x00000020U
AnnaBridge 126:abea610beb85 3670 #define DCMI_CR_HSPOL 0x00000040U
AnnaBridge 126:abea610beb85 3671 #define DCMI_CR_VSPOL 0x00000080U
AnnaBridge 126:abea610beb85 3672 #define DCMI_CR_FCRC_0 0x00000100U
AnnaBridge 126:abea610beb85 3673 #define DCMI_CR_FCRC_1 0x00000200U
AnnaBridge 126:abea610beb85 3674 #define DCMI_CR_EDM_0 0x00000400U
AnnaBridge 126:abea610beb85 3675 #define DCMI_CR_EDM_1 0x00000800U
AnnaBridge 126:abea610beb85 3676 #define DCMI_CR_CRE 0x00001000U
AnnaBridge 126:abea610beb85 3677 #define DCMI_CR_ENABLE 0x00004000U
AnnaBridge 126:abea610beb85 3678 #define DCMI_CR_BSM 0x00030000U
AnnaBridge 126:abea610beb85 3679 #define DCMI_CR_BSM_0 0x00010000U
AnnaBridge 126:abea610beb85 3680 #define DCMI_CR_BSM_1 0x00020000U
AnnaBridge 126:abea610beb85 3681 #define DCMI_CR_OEBS 0x00040000U
AnnaBridge 126:abea610beb85 3682 #define DCMI_CR_LSM 0x00080000U
AnnaBridge 126:abea610beb85 3683 #define DCMI_CR_OELS 0x00100000U
AnnaBridge 126:abea610beb85 3684
AnnaBridge 126:abea610beb85 3685 /******************** Bits definition for DCMI_SR register ******************/
AnnaBridge 126:abea610beb85 3686 #define DCMI_SR_HSYNC 0x00000001U
AnnaBridge 126:abea610beb85 3687 #define DCMI_SR_VSYNC 0x00000002U
AnnaBridge 126:abea610beb85 3688 #define DCMI_SR_FNE 0x00000004U
AnnaBridge 126:abea610beb85 3689
AnnaBridge 126:abea610beb85 3690 /******************** Bits definition for DCMI_RIS register ****************/
AnnaBridge 126:abea610beb85 3691 #define DCMI_RIS_FRAME_RIS 0x00000001U
AnnaBridge 126:abea610beb85 3692 #define DCMI_RIS_OVR_RIS 0x00000002U
AnnaBridge 126:abea610beb85 3693 #define DCMI_RIS_ERR_RIS 0x00000004U
AnnaBridge 126:abea610beb85 3694 #define DCMI_RIS_VSYNC_RIS 0x00000008U
AnnaBridge 126:abea610beb85 3695 #define DCMI_RIS_LINE_RIS 0x00000010U
AnnaBridge 126:abea610beb85 3696
AnnaBridge 126:abea610beb85 3697 /* Legacy defines */
AnnaBridge 126:abea610beb85 3698 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
AnnaBridge 126:abea610beb85 3699 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
AnnaBridge 126:abea610beb85 3700 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
AnnaBridge 126:abea610beb85 3701 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
AnnaBridge 126:abea610beb85 3702 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
AnnaBridge 126:abea610beb85 3703
AnnaBridge 126:abea610beb85 3704 /******************** Bits definition for DCMI_IER register *****************/
AnnaBridge 126:abea610beb85 3705 #define DCMI_IER_FRAME_IE 0x00000001U
AnnaBridge 126:abea610beb85 3706 #define DCMI_IER_OVR_IE 0x00000002U
AnnaBridge 126:abea610beb85 3707 #define DCMI_IER_ERR_IE 0x00000004U
AnnaBridge 126:abea610beb85 3708 #define DCMI_IER_VSYNC_IE 0x00000008U
AnnaBridge 126:abea610beb85 3709 #define DCMI_IER_LINE_IE 0x00000010U
AnnaBridge 126:abea610beb85 3710
AnnaBridge 126:abea610beb85 3711
AnnaBridge 126:abea610beb85 3712 /******************** Bits definition for DCMI_MIS register *****************/
AnnaBridge 126:abea610beb85 3713 #define DCMI_MIS_FRAME_MIS 0x00000001U
AnnaBridge 126:abea610beb85 3714 #define DCMI_MIS_OVR_MIS 0x00000002U
AnnaBridge 126:abea610beb85 3715 #define DCMI_MIS_ERR_MIS 0x00000004U
AnnaBridge 126:abea610beb85 3716 #define DCMI_MIS_VSYNC_MIS 0x00000008U
AnnaBridge 126:abea610beb85 3717 #define DCMI_MIS_LINE_MIS 0x00000010U
AnnaBridge 126:abea610beb85 3718
AnnaBridge 126:abea610beb85 3719
AnnaBridge 126:abea610beb85 3720 /******************** Bits definition for DCMI_ICR register *****************/
AnnaBridge 126:abea610beb85 3721 #define DCMI_ICR_FRAME_ISC 0x00000001U
AnnaBridge 126:abea610beb85 3722 #define DCMI_ICR_OVR_ISC 0x00000002U
AnnaBridge 126:abea610beb85 3723 #define DCMI_ICR_ERR_ISC 0x00000004U
AnnaBridge 126:abea610beb85 3724 #define DCMI_ICR_VSYNC_ISC 0x00000008U
AnnaBridge 126:abea610beb85 3725 #define DCMI_ICR_LINE_ISC 0x00000010U
AnnaBridge 126:abea610beb85 3726
AnnaBridge 126:abea610beb85 3727
AnnaBridge 126:abea610beb85 3728 /******************** Bits definition for DCMI_ESCR register ******************/
AnnaBridge 126:abea610beb85 3729 #define DCMI_ESCR_FSC 0x000000FFU
AnnaBridge 126:abea610beb85 3730 #define DCMI_ESCR_LSC 0x0000FF00U
AnnaBridge 126:abea610beb85 3731 #define DCMI_ESCR_LEC 0x00FF0000U
AnnaBridge 126:abea610beb85 3732 #define DCMI_ESCR_FEC 0xFF000000U
AnnaBridge 126:abea610beb85 3733
AnnaBridge 126:abea610beb85 3734 /******************** Bits definition for DCMI_ESUR register ******************/
AnnaBridge 126:abea610beb85 3735 #define DCMI_ESUR_FSU 0x000000FFU
AnnaBridge 126:abea610beb85 3736 #define DCMI_ESUR_LSU 0x0000FF00U
AnnaBridge 126:abea610beb85 3737 #define DCMI_ESUR_LEU 0x00FF0000U
AnnaBridge 126:abea610beb85 3738 #define DCMI_ESUR_FEU 0xFF000000U
AnnaBridge 126:abea610beb85 3739
AnnaBridge 126:abea610beb85 3740 /******************** Bits definition for DCMI_CWSTRT register ******************/
AnnaBridge 126:abea610beb85 3741 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
AnnaBridge 126:abea610beb85 3742 #define DCMI_CWSTRT_VST 0x1FFF0000U
AnnaBridge 126:abea610beb85 3743
AnnaBridge 126:abea610beb85 3744 /******************** Bits definition for DCMI_CWSIZE register ******************/
AnnaBridge 126:abea610beb85 3745 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
AnnaBridge 126:abea610beb85 3746 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
AnnaBridge 126:abea610beb85 3747
AnnaBridge 126:abea610beb85 3748 /******************** Bits definition for DCMI_DR register ******************/
AnnaBridge 126:abea610beb85 3749 #define DCMI_DR_BYTE0 0x000000FFU
AnnaBridge 126:abea610beb85 3750 #define DCMI_DR_BYTE1 0x0000FF00U
AnnaBridge 126:abea610beb85 3751 #define DCMI_DR_BYTE2 0x00FF0000U
AnnaBridge 126:abea610beb85 3752 #define DCMI_DR_BYTE3 0xFF000000U
AnnaBridge 126:abea610beb85 3753
AnnaBridge 126:abea610beb85 3754 /******************************************************************************/
AnnaBridge 126:abea610beb85 3755 /* */
AnnaBridge 126:abea610beb85 3756 /* DMA Controller */
AnnaBridge 126:abea610beb85 3757 /* */
AnnaBridge 126:abea610beb85 3758 /******************************************************************************/
AnnaBridge 126:abea610beb85 3759 /******************** Bits definition for DMA_SxCR register *****************/
AnnaBridge 126:abea610beb85 3760 #define DMA_SxCR_CHSEL 0x1E000000U
AnnaBridge 126:abea610beb85 3761 #define DMA_SxCR_CHSEL_0 0x02000000U
AnnaBridge 126:abea610beb85 3762 #define DMA_SxCR_CHSEL_1 0x04000000U
AnnaBridge 126:abea610beb85 3763 #define DMA_SxCR_CHSEL_2 0x08000000U
AnnaBridge 126:abea610beb85 3764 #define DMA_SxCR_CHSEL_3 0x10000000U
AnnaBridge 126:abea610beb85 3765 #define DMA_SxCR_MBURST 0x01800000U
AnnaBridge 126:abea610beb85 3766 #define DMA_SxCR_MBURST_0 0x00800000U
AnnaBridge 126:abea610beb85 3767 #define DMA_SxCR_MBURST_1 0x01000000U
AnnaBridge 126:abea610beb85 3768 #define DMA_SxCR_PBURST 0x00600000U
AnnaBridge 126:abea610beb85 3769 #define DMA_SxCR_PBURST_0 0x00200000U
AnnaBridge 126:abea610beb85 3770 #define DMA_SxCR_PBURST_1 0x00400000U
AnnaBridge 126:abea610beb85 3771 #define DMA_SxCR_CT 0x00080000U
AnnaBridge 126:abea610beb85 3772 #define DMA_SxCR_DBM 0x00040000U
AnnaBridge 126:abea610beb85 3773 #define DMA_SxCR_PL 0x00030000U
AnnaBridge 126:abea610beb85 3774 #define DMA_SxCR_PL_0 0x00010000U
AnnaBridge 126:abea610beb85 3775 #define DMA_SxCR_PL_1 0x00020000U
AnnaBridge 126:abea610beb85 3776 #define DMA_SxCR_PINCOS 0x00008000U
AnnaBridge 126:abea610beb85 3777 #define DMA_SxCR_MSIZE 0x00006000U
AnnaBridge 126:abea610beb85 3778 #define DMA_SxCR_MSIZE_0 0x00002000U
AnnaBridge 126:abea610beb85 3779 #define DMA_SxCR_MSIZE_1 0x00004000U
AnnaBridge 126:abea610beb85 3780 #define DMA_SxCR_PSIZE 0x00001800U
AnnaBridge 126:abea610beb85 3781 #define DMA_SxCR_PSIZE_0 0x00000800U
AnnaBridge 126:abea610beb85 3782 #define DMA_SxCR_PSIZE_1 0x00001000U
AnnaBridge 126:abea610beb85 3783 #define DMA_SxCR_MINC 0x00000400U
AnnaBridge 126:abea610beb85 3784 #define DMA_SxCR_PINC 0x00000200U
AnnaBridge 126:abea610beb85 3785 #define DMA_SxCR_CIRC 0x00000100U
AnnaBridge 126:abea610beb85 3786 #define DMA_SxCR_DIR 0x000000C0U
AnnaBridge 126:abea610beb85 3787 #define DMA_SxCR_DIR_0 0x00000040U
AnnaBridge 126:abea610beb85 3788 #define DMA_SxCR_DIR_1 0x00000080U
AnnaBridge 126:abea610beb85 3789 #define DMA_SxCR_PFCTRL 0x00000020U
AnnaBridge 126:abea610beb85 3790 #define DMA_SxCR_TCIE 0x00000010U
AnnaBridge 126:abea610beb85 3791 #define DMA_SxCR_HTIE 0x00000008U
AnnaBridge 126:abea610beb85 3792 #define DMA_SxCR_TEIE 0x00000004U
AnnaBridge 126:abea610beb85 3793 #define DMA_SxCR_DMEIE 0x00000002U
AnnaBridge 126:abea610beb85 3794 #define DMA_SxCR_EN 0x00000001U
AnnaBridge 126:abea610beb85 3795
AnnaBridge 126:abea610beb85 3796 /******************** Bits definition for DMA_SxCNDTR register **************/
AnnaBridge 126:abea610beb85 3797 #define DMA_SxNDT 0x0000FFFFU
AnnaBridge 126:abea610beb85 3798 #define DMA_SxNDT_0 0x00000001U
AnnaBridge 126:abea610beb85 3799 #define DMA_SxNDT_1 0x00000002U
AnnaBridge 126:abea610beb85 3800 #define DMA_SxNDT_2 0x00000004U
AnnaBridge 126:abea610beb85 3801 #define DMA_SxNDT_3 0x00000008U
AnnaBridge 126:abea610beb85 3802 #define DMA_SxNDT_4 0x00000010U
AnnaBridge 126:abea610beb85 3803 #define DMA_SxNDT_5 0x00000020U
AnnaBridge 126:abea610beb85 3804 #define DMA_SxNDT_6 0x00000040U
AnnaBridge 126:abea610beb85 3805 #define DMA_SxNDT_7 0x00000080U
AnnaBridge 126:abea610beb85 3806 #define DMA_SxNDT_8 0x00000100U
AnnaBridge 126:abea610beb85 3807 #define DMA_SxNDT_9 0x00000200U
AnnaBridge 126:abea610beb85 3808 #define DMA_SxNDT_10 0x00000400U
AnnaBridge 126:abea610beb85 3809 #define DMA_SxNDT_11 0x00000800U
AnnaBridge 126:abea610beb85 3810 #define DMA_SxNDT_12 0x00001000U
AnnaBridge 126:abea610beb85 3811 #define DMA_SxNDT_13 0x00002000U
AnnaBridge 126:abea610beb85 3812 #define DMA_SxNDT_14 0x00004000U
AnnaBridge 126:abea610beb85 3813 #define DMA_SxNDT_15 0x00008000U
AnnaBridge 126:abea610beb85 3814
AnnaBridge 126:abea610beb85 3815 /******************** Bits definition for DMA_SxFCR register ****************/
AnnaBridge 126:abea610beb85 3816 #define DMA_SxFCR_FEIE 0x00000080U
AnnaBridge 126:abea610beb85 3817 #define DMA_SxFCR_FS 0x00000038U
AnnaBridge 126:abea610beb85 3818 #define DMA_SxFCR_FS_0 0x00000008U
AnnaBridge 126:abea610beb85 3819 #define DMA_SxFCR_FS_1 0x00000010U
AnnaBridge 126:abea610beb85 3820 #define DMA_SxFCR_FS_2 0x00000020U
AnnaBridge 126:abea610beb85 3821 #define DMA_SxFCR_DMDIS 0x00000004U
AnnaBridge 126:abea610beb85 3822 #define DMA_SxFCR_FTH 0x00000003U
AnnaBridge 126:abea610beb85 3823 #define DMA_SxFCR_FTH_0 0x00000001U
AnnaBridge 126:abea610beb85 3824 #define DMA_SxFCR_FTH_1 0x00000002U
AnnaBridge 126:abea610beb85 3825
AnnaBridge 126:abea610beb85 3826 /******************** Bits definition for DMA_LISR register *****************/
AnnaBridge 126:abea610beb85 3827 #define DMA_LISR_TCIF3 0x08000000U
AnnaBridge 126:abea610beb85 3828 #define DMA_LISR_HTIF3 0x04000000U
AnnaBridge 126:abea610beb85 3829 #define DMA_LISR_TEIF3 0x02000000U
AnnaBridge 126:abea610beb85 3830 #define DMA_LISR_DMEIF3 0x01000000U
AnnaBridge 126:abea610beb85 3831 #define DMA_LISR_FEIF3 0x00400000U
AnnaBridge 126:abea610beb85 3832 #define DMA_LISR_TCIF2 0x00200000U
AnnaBridge 126:abea610beb85 3833 #define DMA_LISR_HTIF2 0x00100000U
AnnaBridge 126:abea610beb85 3834 #define DMA_LISR_TEIF2 0x00080000U
AnnaBridge 126:abea610beb85 3835 #define DMA_LISR_DMEIF2 0x00040000U
AnnaBridge 126:abea610beb85 3836 #define DMA_LISR_FEIF2 0x00010000U
AnnaBridge 126:abea610beb85 3837 #define DMA_LISR_TCIF1 0x00000800U
AnnaBridge 126:abea610beb85 3838 #define DMA_LISR_HTIF1 0x00000400U
AnnaBridge 126:abea610beb85 3839 #define DMA_LISR_TEIF1 0x00000200U
AnnaBridge 126:abea610beb85 3840 #define DMA_LISR_DMEIF1 0x00000100U
AnnaBridge 126:abea610beb85 3841 #define DMA_LISR_FEIF1 0x00000040U
AnnaBridge 126:abea610beb85 3842 #define DMA_LISR_TCIF0 0x00000020U
AnnaBridge 126:abea610beb85 3843 #define DMA_LISR_HTIF0 0x00000010U
AnnaBridge 126:abea610beb85 3844 #define DMA_LISR_TEIF0 0x00000008U
AnnaBridge 126:abea610beb85 3845 #define DMA_LISR_DMEIF0 0x00000004U
AnnaBridge 126:abea610beb85 3846 #define DMA_LISR_FEIF0 0x00000001U
AnnaBridge 126:abea610beb85 3847
AnnaBridge 126:abea610beb85 3848 /******************** Bits definition for DMA_HISR register *****************/
AnnaBridge 126:abea610beb85 3849 #define DMA_HISR_TCIF7 0x08000000U
AnnaBridge 126:abea610beb85 3850 #define DMA_HISR_HTIF7 0x04000000U
AnnaBridge 126:abea610beb85 3851 #define DMA_HISR_TEIF7 0x02000000U
AnnaBridge 126:abea610beb85 3852 #define DMA_HISR_DMEIF7 0x01000000U
AnnaBridge 126:abea610beb85 3853 #define DMA_HISR_FEIF7 0x00400000U
AnnaBridge 126:abea610beb85 3854 #define DMA_HISR_TCIF6 0x00200000U
AnnaBridge 126:abea610beb85 3855 #define DMA_HISR_HTIF6 0x00100000U
AnnaBridge 126:abea610beb85 3856 #define DMA_HISR_TEIF6 0x00080000U
AnnaBridge 126:abea610beb85 3857 #define DMA_HISR_DMEIF6 0x00040000U
AnnaBridge 126:abea610beb85 3858 #define DMA_HISR_FEIF6 0x00010000U
AnnaBridge 126:abea610beb85 3859 #define DMA_HISR_TCIF5 0x00000800U
AnnaBridge 126:abea610beb85 3860 #define DMA_HISR_HTIF5 0x00000400U
AnnaBridge 126:abea610beb85 3861 #define DMA_HISR_TEIF5 0x00000200U
AnnaBridge 126:abea610beb85 3862 #define DMA_HISR_DMEIF5 0x00000100U
AnnaBridge 126:abea610beb85 3863 #define DMA_HISR_FEIF5 0x00000040U
AnnaBridge 126:abea610beb85 3864 #define DMA_HISR_TCIF4 0x00000020U
AnnaBridge 126:abea610beb85 3865 #define DMA_HISR_HTIF4 0x00000010U
AnnaBridge 126:abea610beb85 3866 #define DMA_HISR_TEIF4 0x00000008U
AnnaBridge 126:abea610beb85 3867 #define DMA_HISR_DMEIF4 0x00000004U
AnnaBridge 126:abea610beb85 3868 #define DMA_HISR_FEIF4 0x00000001U
AnnaBridge 126:abea610beb85 3869
AnnaBridge 126:abea610beb85 3870 /******************** Bits definition for DMA_LIFCR register ****************/
AnnaBridge 126:abea610beb85 3871 #define DMA_LIFCR_CTCIF3 0x08000000U
AnnaBridge 126:abea610beb85 3872 #define DMA_LIFCR_CHTIF3 0x04000000U
AnnaBridge 126:abea610beb85 3873 #define DMA_LIFCR_CTEIF3 0x02000000U
AnnaBridge 126:abea610beb85 3874 #define DMA_LIFCR_CDMEIF3 0x01000000U
AnnaBridge 126:abea610beb85 3875 #define DMA_LIFCR_CFEIF3 0x00400000U
AnnaBridge 126:abea610beb85 3876 #define DMA_LIFCR_CTCIF2 0x00200000U
AnnaBridge 126:abea610beb85 3877 #define DMA_LIFCR_CHTIF2 0x00100000U
AnnaBridge 126:abea610beb85 3878 #define DMA_LIFCR_CTEIF2 0x00080000U
AnnaBridge 126:abea610beb85 3879 #define DMA_LIFCR_CDMEIF2 0x00040000U
AnnaBridge 126:abea610beb85 3880 #define DMA_LIFCR_CFEIF2 0x00010000U
AnnaBridge 126:abea610beb85 3881 #define DMA_LIFCR_CTCIF1 0x00000800U
AnnaBridge 126:abea610beb85 3882 #define DMA_LIFCR_CHTIF1 0x00000400U
AnnaBridge 126:abea610beb85 3883 #define DMA_LIFCR_CTEIF1 0x00000200U
AnnaBridge 126:abea610beb85 3884 #define DMA_LIFCR_CDMEIF1 0x00000100U
AnnaBridge 126:abea610beb85 3885 #define DMA_LIFCR_CFEIF1 0x00000040U
AnnaBridge 126:abea610beb85 3886 #define DMA_LIFCR_CTCIF0 0x00000020U
AnnaBridge 126:abea610beb85 3887 #define DMA_LIFCR_CHTIF0 0x00000010U
AnnaBridge 126:abea610beb85 3888 #define DMA_LIFCR_CTEIF0 0x00000008U
AnnaBridge 126:abea610beb85 3889 #define DMA_LIFCR_CDMEIF0 0x00000004U
AnnaBridge 126:abea610beb85 3890 #define DMA_LIFCR_CFEIF0 0x00000001U
AnnaBridge 126:abea610beb85 3891
AnnaBridge 126:abea610beb85 3892 /******************** Bits definition for DMA_HIFCR register ****************/
AnnaBridge 126:abea610beb85 3893 #define DMA_HIFCR_CTCIF7 0x08000000U
AnnaBridge 126:abea610beb85 3894 #define DMA_HIFCR_CHTIF7 0x04000000U
AnnaBridge 126:abea610beb85 3895 #define DMA_HIFCR_CTEIF7 0x02000000U
AnnaBridge 126:abea610beb85 3896 #define DMA_HIFCR_CDMEIF7 0x01000000U
AnnaBridge 126:abea610beb85 3897 #define DMA_HIFCR_CFEIF7 0x00400000U
AnnaBridge 126:abea610beb85 3898 #define DMA_HIFCR_CTCIF6 0x00200000U
AnnaBridge 126:abea610beb85 3899 #define DMA_HIFCR_CHTIF6 0x00100000U
AnnaBridge 126:abea610beb85 3900 #define DMA_HIFCR_CTEIF6 0x00080000U
AnnaBridge 126:abea610beb85 3901 #define DMA_HIFCR_CDMEIF6 0x00040000U
AnnaBridge 126:abea610beb85 3902 #define DMA_HIFCR_CFEIF6 0x00010000U
AnnaBridge 126:abea610beb85 3903 #define DMA_HIFCR_CTCIF5 0x00000800U
AnnaBridge 126:abea610beb85 3904 #define DMA_HIFCR_CHTIF5 0x00000400U
AnnaBridge 126:abea610beb85 3905 #define DMA_HIFCR_CTEIF5 0x00000200U
AnnaBridge 126:abea610beb85 3906 #define DMA_HIFCR_CDMEIF5 0x00000100U
AnnaBridge 126:abea610beb85 3907 #define DMA_HIFCR_CFEIF5 0x00000040U
AnnaBridge 126:abea610beb85 3908 #define DMA_HIFCR_CTCIF4 0x00000020U
AnnaBridge 126:abea610beb85 3909 #define DMA_HIFCR_CHTIF4 0x00000010U
AnnaBridge 126:abea610beb85 3910 #define DMA_HIFCR_CTEIF4 0x00000008U
AnnaBridge 126:abea610beb85 3911 #define DMA_HIFCR_CDMEIF4 0x00000004U
AnnaBridge 126:abea610beb85 3912 #define DMA_HIFCR_CFEIF4 0x00000001U
AnnaBridge 126:abea610beb85 3913
AnnaBridge 126:abea610beb85 3914 /******************************************************************************/
AnnaBridge 126:abea610beb85 3915 /* */
AnnaBridge 126:abea610beb85 3916 /* AHB Master DMA2D Controller (DMA2D) */
AnnaBridge 126:abea610beb85 3917 /* */
AnnaBridge 126:abea610beb85 3918 /******************************************************************************/
AnnaBridge 126:abea610beb85 3919
AnnaBridge 126:abea610beb85 3920 /******************** Bit definition for DMA2D_CR register ******************/
AnnaBridge 126:abea610beb85 3921
AnnaBridge 126:abea610beb85 3922 #define DMA2D_CR_START 0x00000001U /*!< Start transfer */
AnnaBridge 126:abea610beb85 3923 #define DMA2D_CR_SUSP 0x00000002U /*!< Suspend transfer */
AnnaBridge 126:abea610beb85 3924 #define DMA2D_CR_ABORT 0x00000004U /*!< Abort transfer */
AnnaBridge 126:abea610beb85 3925 #define DMA2D_CR_TEIE 0x00000100U /*!< Transfer Error Interrupt Enable */
AnnaBridge 126:abea610beb85 3926 #define DMA2D_CR_TCIE 0x00000200U /*!< Transfer Complete Interrupt Enable */
AnnaBridge 126:abea610beb85 3927 #define DMA2D_CR_TWIE 0x00000400U /*!< Transfer Watermark Interrupt Enable */
AnnaBridge 126:abea610beb85 3928 #define DMA2D_CR_CAEIE 0x00000800U /*!< CLUT Access Error Interrupt Enable */
AnnaBridge 126:abea610beb85 3929 #define DMA2D_CR_CTCIE 0x00001000U /*!< CLUT Transfer Complete Interrupt Enable */
AnnaBridge 126:abea610beb85 3930 #define DMA2D_CR_CEIE 0x00002000U /*!< Configuration Error Interrupt Enable */
AnnaBridge 126:abea610beb85 3931 #define DMA2D_CR_MODE 0x00030000U /*!< DMA2D Mode[1:0] */
AnnaBridge 126:abea610beb85 3932 #define DMA2D_CR_MODE_0 0x00010000U /*!< DMA2D Mode bit 0 */
AnnaBridge 126:abea610beb85 3933 #define DMA2D_CR_MODE_1 0x00020000U /*!< DMA2D Mode bit 1 */
AnnaBridge 126:abea610beb85 3934
AnnaBridge 126:abea610beb85 3935 /******************** Bit definition for DMA2D_ISR register *****************/
AnnaBridge 126:abea610beb85 3936
AnnaBridge 126:abea610beb85 3937 #define DMA2D_ISR_TEIF 0x00000001U /*!< Transfer Error Interrupt Flag */
AnnaBridge 126:abea610beb85 3938 #define DMA2D_ISR_TCIF 0x00000002U /*!< Transfer Complete Interrupt Flag */
AnnaBridge 126:abea610beb85 3939 #define DMA2D_ISR_TWIF 0x00000004U /*!< Transfer Watermark Interrupt Flag */
AnnaBridge 126:abea610beb85 3940 #define DMA2D_ISR_CAEIF 0x00000008U /*!< CLUT Access Error Interrupt Flag */
AnnaBridge 126:abea610beb85 3941 #define DMA2D_ISR_CTCIF 0x00000010U /*!< CLUT Transfer Complete Interrupt Flag */
AnnaBridge 126:abea610beb85 3942 #define DMA2D_ISR_CEIF 0x00000020U /*!< Configuration Error Interrupt Flag */
AnnaBridge 126:abea610beb85 3943
AnnaBridge 126:abea610beb85 3944 /******************** Bit definition for DMA2D_IFCR register ****************/
AnnaBridge 126:abea610beb85 3945
AnnaBridge 126:abea610beb85 3946 #define DMA2D_IFCR_CTEIF 0x00000001U /*!< Clears Transfer Error Interrupt Flag */
AnnaBridge 126:abea610beb85 3947 #define DMA2D_IFCR_CTCIF 0x00000002U /*!< Clears Transfer Complete Interrupt Flag */
AnnaBridge 126:abea610beb85 3948 #define DMA2D_IFCR_CTWIF 0x00000004U /*!< Clears Transfer Watermark Interrupt Flag */
AnnaBridge 126:abea610beb85 3949 #define DMA2D_IFCR_CAECIF 0x00000008U /*!< Clears CLUT Access Error Interrupt Flag */
AnnaBridge 126:abea610beb85 3950 #define DMA2D_IFCR_CCTCIF 0x00000010U /*!< Clears CLUT Transfer Complete Interrupt Flag */
AnnaBridge 126:abea610beb85 3951 #define DMA2D_IFCR_CCEIF 0x00000020U /*!< Clears Configuration Error Interrupt Flag */
AnnaBridge 126:abea610beb85 3952
AnnaBridge 126:abea610beb85 3953 /* Legacy defines */
AnnaBridge 126:abea610beb85 3954 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
AnnaBridge 126:abea610beb85 3955 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
AnnaBridge 126:abea610beb85 3956 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
AnnaBridge 126:abea610beb85 3957 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
AnnaBridge 126:abea610beb85 3958 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
AnnaBridge 126:abea610beb85 3959 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
AnnaBridge 126:abea610beb85 3960
AnnaBridge 126:abea610beb85 3961 /******************** Bit definition for DMA2D_FGMAR register ***************/
AnnaBridge 126:abea610beb85 3962
AnnaBridge 126:abea610beb85 3963 #define DMA2D_FGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
AnnaBridge 126:abea610beb85 3964
AnnaBridge 126:abea610beb85 3965 /******************** Bit definition for DMA2D_FGOR register ****************/
AnnaBridge 126:abea610beb85 3966
AnnaBridge 126:abea610beb85 3967 #define DMA2D_FGOR_LO 0x00003FFFU /*!< Line Offset */
AnnaBridge 126:abea610beb85 3968
AnnaBridge 126:abea610beb85 3969 /******************** Bit definition for DMA2D_BGMAR register ***************/
AnnaBridge 126:abea610beb85 3970
AnnaBridge 126:abea610beb85 3971 #define DMA2D_BGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
AnnaBridge 126:abea610beb85 3972
AnnaBridge 126:abea610beb85 3973 /******************** Bit definition for DMA2D_BGOR register ****************/
AnnaBridge 126:abea610beb85 3974
AnnaBridge 126:abea610beb85 3975 #define DMA2D_BGOR_LO 0x00003FFFU /*!< Line Offset */
AnnaBridge 126:abea610beb85 3976
AnnaBridge 126:abea610beb85 3977 /******************** Bit definition for DMA2D_FGPFCCR register *************/
AnnaBridge 126:abea610beb85 3978
AnnaBridge 126:abea610beb85 3979 #define DMA2D_FGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
AnnaBridge 126:abea610beb85 3980 #define DMA2D_FGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
AnnaBridge 126:abea610beb85 3981 #define DMA2D_FGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
AnnaBridge 126:abea610beb85 3982 #define DMA2D_FGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
AnnaBridge 126:abea610beb85 3983 #define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
AnnaBridge 126:abea610beb85 3984 #define DMA2D_FGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
AnnaBridge 126:abea610beb85 3985 #define DMA2D_FGPFCCR_START 0x00000020U /*!< Start */
AnnaBridge 126:abea610beb85 3986 #define DMA2D_FGPFCCR_CS 0x0000FF00U /*!< CLUT size */
AnnaBridge 126:abea610beb85 3987 #define DMA2D_FGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
AnnaBridge 126:abea610beb85 3988 #define DMA2D_FGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
AnnaBridge 126:abea610beb85 3989 #define DMA2D_FGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
AnnaBridge 126:abea610beb85 3990 #define DMA2D_FGPFCCR_AI 0x00100000U /*!< Foreground Input Alpha Inverted */
AnnaBridge 126:abea610beb85 3991 #define DMA2D_FGPFCCR_RBS 0x00200000U /*!< Foreground Input Red Blue Swap */
AnnaBridge 126:abea610beb85 3992 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U /*!< Alpha value */
AnnaBridge 126:abea610beb85 3993
AnnaBridge 126:abea610beb85 3994 /******************** Bit definition for DMA2D_FGCOLR register **************/
AnnaBridge 126:abea610beb85 3995
AnnaBridge 126:abea610beb85 3996 #define DMA2D_FGCOLR_BLUE 0x000000FFU /*!< Blue Value */
AnnaBridge 126:abea610beb85 3997 #define DMA2D_FGCOLR_GREEN 0x0000FF00U /*!< Green Value */
AnnaBridge 126:abea610beb85 3998 #define DMA2D_FGCOLR_RED 0x00FF0000U /*!< Red Value */
AnnaBridge 126:abea610beb85 3999
AnnaBridge 126:abea610beb85 4000 /******************** Bit definition for DMA2D_BGPFCCR register *************/
AnnaBridge 126:abea610beb85 4001
AnnaBridge 126:abea610beb85 4002 #define DMA2D_BGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
AnnaBridge 126:abea610beb85 4003 #define DMA2D_BGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
AnnaBridge 126:abea610beb85 4004 #define DMA2D_BGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
AnnaBridge 126:abea610beb85 4005 #define DMA2D_BGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
AnnaBridge 126:abea610beb85 4006 #define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
AnnaBridge 126:abea610beb85 4007 #define DMA2D_BGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
AnnaBridge 126:abea610beb85 4008 #define DMA2D_BGPFCCR_START 0x00000020U /*!< Start */
AnnaBridge 126:abea610beb85 4009 #define DMA2D_BGPFCCR_CS 0x0000FF00U /*!< CLUT size */
AnnaBridge 126:abea610beb85 4010 #define DMA2D_BGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
AnnaBridge 126:abea610beb85 4011 #define DMA2D_BGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
AnnaBridge 126:abea610beb85 4012 #define DMA2D_BGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
AnnaBridge 126:abea610beb85 4013 #define DMA2D_BGPFCCR_AI 0x00100000U /*!< background Input Alpha Inverted */
AnnaBridge 126:abea610beb85 4014 #define DMA2D_BGPFCCR_RBS 0x00200000U /*!< Background Input Red Blue Swap */
AnnaBridge 126:abea610beb85 4015 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U /*!< background Input Alpha value */
AnnaBridge 126:abea610beb85 4016
AnnaBridge 126:abea610beb85 4017 /******************** Bit definition for DMA2D_BGCOLR register **************/
AnnaBridge 126:abea610beb85 4018
AnnaBridge 126:abea610beb85 4019 #define DMA2D_BGCOLR_BLUE 0x000000FFU /*!< Blue Value */
AnnaBridge 126:abea610beb85 4020 #define DMA2D_BGCOLR_GREEN 0x0000FF00U /*!< Green Value */
AnnaBridge 126:abea610beb85 4021 #define DMA2D_BGCOLR_RED 0x00FF0000U /*!< Red Value */
AnnaBridge 126:abea610beb85 4022
AnnaBridge 126:abea610beb85 4023 /******************** Bit definition for DMA2D_FGCMAR register **************/
AnnaBridge 126:abea610beb85 4024
AnnaBridge 126:abea610beb85 4025 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
AnnaBridge 126:abea610beb85 4026
AnnaBridge 126:abea610beb85 4027 /******************** Bit definition for DMA2D_BGCMAR register **************/
AnnaBridge 126:abea610beb85 4028
AnnaBridge 126:abea610beb85 4029 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
AnnaBridge 126:abea610beb85 4030
AnnaBridge 126:abea610beb85 4031 /******************** Bit definition for DMA2D_OPFCCR register **************/
AnnaBridge 126:abea610beb85 4032
AnnaBridge 126:abea610beb85 4033 #define DMA2D_OPFCCR_CM 0x00000007U /*!< Color mode CM[2:0] */
AnnaBridge 126:abea610beb85 4034 #define DMA2D_OPFCCR_CM_0 0x00000001U /*!< Color mode CM bit 0 */
AnnaBridge 126:abea610beb85 4035 #define DMA2D_OPFCCR_CM_1 0x00000002U /*!< Color mode CM bit 1 */
AnnaBridge 126:abea610beb85 4036 #define DMA2D_OPFCCR_CM_2 0x00000004U /*!< Color mode CM bit 2 */
AnnaBridge 126:abea610beb85 4037 #define DMA2D_OPFCCR_AI 0x00100000U /*!< Output Alpha Inverted */
AnnaBridge 126:abea610beb85 4038 #define DMA2D_OPFCCR_RBS 0x00200000U /*!< Output Red Blue Swap */
AnnaBridge 126:abea610beb85 4039
AnnaBridge 126:abea610beb85 4040 /******************** Bit definition for DMA2D_OCOLR register ***************/
AnnaBridge 126:abea610beb85 4041
AnnaBridge 126:abea610beb85 4042 /*!<Mode_ARGB8888/RGB888 */
AnnaBridge 126:abea610beb85 4043
AnnaBridge 126:abea610beb85 4044 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
AnnaBridge 126:abea610beb85 4045 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
AnnaBridge 126:abea610beb85 4046 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
AnnaBridge 126:abea610beb85 4047 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
AnnaBridge 126:abea610beb85 4048
AnnaBridge 126:abea610beb85 4049 /*!<Mode_RGB565 */
AnnaBridge 126:abea610beb85 4050 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
AnnaBridge 126:abea610beb85 4051 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
AnnaBridge 126:abea610beb85 4052 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
AnnaBridge 126:abea610beb85 4053
AnnaBridge 126:abea610beb85 4054 /*!<Mode_ARGB1555 */
AnnaBridge 126:abea610beb85 4055 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
AnnaBridge 126:abea610beb85 4056 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
AnnaBridge 126:abea610beb85 4057 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
AnnaBridge 126:abea610beb85 4058 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
AnnaBridge 126:abea610beb85 4059
AnnaBridge 126:abea610beb85 4060 /*!<Mode_ARGB4444 */
AnnaBridge 126:abea610beb85 4061 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
AnnaBridge 126:abea610beb85 4062 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
AnnaBridge 126:abea610beb85 4063 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
AnnaBridge 126:abea610beb85 4064 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
AnnaBridge 126:abea610beb85 4065
AnnaBridge 126:abea610beb85 4066 /******************** Bit definition for DMA2D_OMAR register ****************/
AnnaBridge 126:abea610beb85 4067
AnnaBridge 126:abea610beb85 4068 #define DMA2D_OMAR_MA 0xFFFFFFFFU /*!< Memory Address */
AnnaBridge 126:abea610beb85 4069
AnnaBridge 126:abea610beb85 4070 /******************** Bit definition for DMA2D_OOR register *****************/
AnnaBridge 126:abea610beb85 4071
AnnaBridge 126:abea610beb85 4072 #define DMA2D_OOR_LO 0x00003FFFU /*!< Line Offset */
AnnaBridge 126:abea610beb85 4073
AnnaBridge 126:abea610beb85 4074 /******************** Bit definition for DMA2D_NLR register *****************/
AnnaBridge 126:abea610beb85 4075
AnnaBridge 126:abea610beb85 4076 #define DMA2D_NLR_NL 0x0000FFFFU /*!< Number of Lines */
AnnaBridge 126:abea610beb85 4077 #define DMA2D_NLR_PL 0x3FFF0000U /*!< Pixel per Lines */
AnnaBridge 126:abea610beb85 4078
AnnaBridge 126:abea610beb85 4079 /******************** Bit definition for DMA2D_LWR register *****************/
AnnaBridge 126:abea610beb85 4080
AnnaBridge 126:abea610beb85 4081 #define DMA2D_LWR_LW 0x0000FFFFU /*!< Line Watermark */
AnnaBridge 126:abea610beb85 4082
AnnaBridge 126:abea610beb85 4083 /******************** Bit definition for DMA2D_AMTCR register ***************/
AnnaBridge 126:abea610beb85 4084
AnnaBridge 126:abea610beb85 4085 #define DMA2D_AMTCR_EN 0x00000001U /*!< Enable */
AnnaBridge 126:abea610beb85 4086 #define DMA2D_AMTCR_DT 0x0000FF00U /*!< Dead Time */
AnnaBridge 126:abea610beb85 4087
AnnaBridge 126:abea610beb85 4088
AnnaBridge 126:abea610beb85 4089 /******************** Bit definition for DMA2D_FGCLUT register **************/
AnnaBridge 126:abea610beb85 4090
AnnaBridge 126:abea610beb85 4091 /******************** Bit definition for DMA2D_BGCLUT register **************/
AnnaBridge 126:abea610beb85 4092
AnnaBridge 126:abea610beb85 4093
AnnaBridge 126:abea610beb85 4094 /******************************************************************************/
AnnaBridge 126:abea610beb85 4095 /* */
AnnaBridge 126:abea610beb85 4096 /* External Interrupt/Event Controller */
AnnaBridge 126:abea610beb85 4097 /* */
AnnaBridge 126:abea610beb85 4098 /******************************************************************************/
AnnaBridge 126:abea610beb85 4099 /******************* Bit definition for EXTI_IMR register *******************/
AnnaBridge 126:abea610beb85 4100 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
AnnaBridge 126:abea610beb85 4101 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
AnnaBridge 126:abea610beb85 4102 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
AnnaBridge 126:abea610beb85 4103 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
AnnaBridge 126:abea610beb85 4104 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
AnnaBridge 126:abea610beb85 4105 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
AnnaBridge 126:abea610beb85 4106 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
AnnaBridge 126:abea610beb85 4107 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
AnnaBridge 126:abea610beb85 4108 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
AnnaBridge 126:abea610beb85 4109 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
AnnaBridge 126:abea610beb85 4110 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
AnnaBridge 126:abea610beb85 4111 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
AnnaBridge 126:abea610beb85 4112 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
AnnaBridge 126:abea610beb85 4113 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
AnnaBridge 126:abea610beb85 4114 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
AnnaBridge 126:abea610beb85 4115 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
AnnaBridge 126:abea610beb85 4116 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
AnnaBridge 126:abea610beb85 4117 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
AnnaBridge 126:abea610beb85 4118 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
AnnaBridge 126:abea610beb85 4119 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
AnnaBridge 126:abea610beb85 4120 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
AnnaBridge 126:abea610beb85 4121 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
AnnaBridge 126:abea610beb85 4122 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
AnnaBridge 126:abea610beb85 4123 #define EXTI_IMR_MR23 0x00800000U /*!< Interrupt Mask on line 23 */
AnnaBridge 126:abea610beb85 4124 #define EXTI_IMR_MR24 0x01000000U /*!< Interrupt Mask on line 24 */
AnnaBridge 126:abea610beb85 4125
AnnaBridge 126:abea610beb85 4126 /* Reference Defines */
AnnaBridge 126:abea610beb85 4127 #define EXTI_IMR_IM0 EXTI_IMR_MR0
AnnaBridge 126:abea610beb85 4128 #define EXTI_IMR_IM1 EXTI_IMR_MR1
AnnaBridge 126:abea610beb85 4129 #define EXTI_IMR_IM2 EXTI_IMR_MR2
AnnaBridge 126:abea610beb85 4130 #define EXTI_IMR_IM3 EXTI_IMR_MR3
AnnaBridge 126:abea610beb85 4131 #define EXTI_IMR_IM4 EXTI_IMR_MR4
AnnaBridge 126:abea610beb85 4132 #define EXTI_IMR_IM5 EXTI_IMR_MR5
AnnaBridge 126:abea610beb85 4133 #define EXTI_IMR_IM6 EXTI_IMR_MR6
AnnaBridge 126:abea610beb85 4134 #define EXTI_IMR_IM7 EXTI_IMR_MR7
AnnaBridge 126:abea610beb85 4135 #define EXTI_IMR_IM8 EXTI_IMR_MR8
AnnaBridge 126:abea610beb85 4136 #define EXTI_IMR_IM9 EXTI_IMR_MR9
AnnaBridge 126:abea610beb85 4137 #define EXTI_IMR_IM10 EXTI_IMR_MR10
AnnaBridge 126:abea610beb85 4138 #define EXTI_IMR_IM11 EXTI_IMR_MR11
AnnaBridge 126:abea610beb85 4139 #define EXTI_IMR_IM12 EXTI_IMR_MR12
AnnaBridge 126:abea610beb85 4140 #define EXTI_IMR_IM13 EXTI_IMR_MR13
AnnaBridge 126:abea610beb85 4141 #define EXTI_IMR_IM14 EXTI_IMR_MR14
AnnaBridge 126:abea610beb85 4142 #define EXTI_IMR_IM15 EXTI_IMR_MR15
AnnaBridge 126:abea610beb85 4143 #define EXTI_IMR_IM16 EXTI_IMR_MR16
AnnaBridge 126:abea610beb85 4144 #define EXTI_IMR_IM17 EXTI_IMR_MR17
AnnaBridge 126:abea610beb85 4145 #define EXTI_IMR_IM18 EXTI_IMR_MR18
AnnaBridge 126:abea610beb85 4146 #define EXTI_IMR_IM19 EXTI_IMR_MR19
AnnaBridge 126:abea610beb85 4147 #define EXTI_IMR_IM20 EXTI_IMR_MR20
AnnaBridge 126:abea610beb85 4148 #define EXTI_IMR_IM21 EXTI_IMR_MR21
AnnaBridge 126:abea610beb85 4149 #define EXTI_IMR_IM22 EXTI_IMR_MR22
AnnaBridge 126:abea610beb85 4150 #define EXTI_IMR_IM23 EXTI_IMR_MR23
AnnaBridge 126:abea610beb85 4151 #define EXTI_IMR_IM24 EXTI_IMR_MR24
AnnaBridge 126:abea610beb85 4152
AnnaBridge 126:abea610beb85 4153 #define EXTI_IMR_IM 0x01FFFFFFU /*!< Interrupt Mask All */
AnnaBridge 126:abea610beb85 4154
AnnaBridge 126:abea610beb85 4155 /******************* Bit definition for EXTI_EMR register *******************/
AnnaBridge 126:abea610beb85 4156 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
AnnaBridge 126:abea610beb85 4157 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
AnnaBridge 126:abea610beb85 4158 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
AnnaBridge 126:abea610beb85 4159 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
AnnaBridge 126:abea610beb85 4160 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
AnnaBridge 126:abea610beb85 4161 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
AnnaBridge 126:abea610beb85 4162 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
AnnaBridge 126:abea610beb85 4163 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
AnnaBridge 126:abea610beb85 4164 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
AnnaBridge 126:abea610beb85 4165 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
AnnaBridge 126:abea610beb85 4166 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
AnnaBridge 126:abea610beb85 4167 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
AnnaBridge 126:abea610beb85 4168 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
AnnaBridge 126:abea610beb85 4169 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
AnnaBridge 126:abea610beb85 4170 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
AnnaBridge 126:abea610beb85 4171 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
AnnaBridge 126:abea610beb85 4172 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
AnnaBridge 126:abea610beb85 4173 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
AnnaBridge 126:abea610beb85 4174 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
AnnaBridge 126:abea610beb85 4175 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
AnnaBridge 126:abea610beb85 4176 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
AnnaBridge 126:abea610beb85 4177 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
AnnaBridge 126:abea610beb85 4178 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
AnnaBridge 126:abea610beb85 4179 #define EXTI_EMR_MR23 0x00800000U /*!< Event Mask on line 23 */
AnnaBridge 126:abea610beb85 4180 #define EXTI_EMR_MR24 0x01000000U /*!< Event Mask on line 24 */
AnnaBridge 126:abea610beb85 4181
AnnaBridge 126:abea610beb85 4182 /* Reference Defines */
AnnaBridge 126:abea610beb85 4183 #define EXTI_EMR_EM0 EXTI_EMR_MR0
AnnaBridge 126:abea610beb85 4184 #define EXTI_EMR_EM1 EXTI_EMR_MR1
AnnaBridge 126:abea610beb85 4185 #define EXTI_EMR_EM2 EXTI_EMR_MR2
AnnaBridge 126:abea610beb85 4186 #define EXTI_EMR_EM3 EXTI_EMR_MR3
AnnaBridge 126:abea610beb85 4187 #define EXTI_EMR_EM4 EXTI_EMR_MR4
AnnaBridge 126:abea610beb85 4188 #define EXTI_EMR_EM5 EXTI_EMR_MR5
AnnaBridge 126:abea610beb85 4189 #define EXTI_EMR_EM6 EXTI_EMR_MR6
AnnaBridge 126:abea610beb85 4190 #define EXTI_EMR_EM7 EXTI_EMR_MR7
AnnaBridge 126:abea610beb85 4191 #define EXTI_EMR_EM8 EXTI_EMR_MR8
AnnaBridge 126:abea610beb85 4192 #define EXTI_EMR_EM9 EXTI_EMR_MR9
AnnaBridge 126:abea610beb85 4193 #define EXTI_EMR_EM10 EXTI_EMR_MR10
AnnaBridge 126:abea610beb85 4194 #define EXTI_EMR_EM11 EXTI_EMR_MR11
AnnaBridge 126:abea610beb85 4195 #define EXTI_EMR_EM12 EXTI_EMR_MR12
AnnaBridge 126:abea610beb85 4196 #define EXTI_EMR_EM13 EXTI_EMR_MR13
AnnaBridge 126:abea610beb85 4197 #define EXTI_EMR_EM14 EXTI_EMR_MR14
AnnaBridge 126:abea610beb85 4198 #define EXTI_EMR_EM15 EXTI_EMR_MR15
AnnaBridge 126:abea610beb85 4199 #define EXTI_EMR_EM16 EXTI_EMR_MR16
AnnaBridge 126:abea610beb85 4200 #define EXTI_EMR_EM17 EXTI_EMR_MR17
AnnaBridge 126:abea610beb85 4201 #define EXTI_EMR_EM18 EXTI_EMR_MR18
AnnaBridge 126:abea610beb85 4202 #define EXTI_EMR_EM19 EXTI_EMR_MR19
AnnaBridge 126:abea610beb85 4203 #define EXTI_EMR_EM20 EXTI_EMR_MR20
AnnaBridge 126:abea610beb85 4204 #define EXTI_EMR_EM21 EXTI_EMR_MR21
AnnaBridge 126:abea610beb85 4205 #define EXTI_EMR_EM22 EXTI_EMR_MR22
AnnaBridge 126:abea610beb85 4206 #define EXTI_EMR_EM23 EXTI_EMR_MR23
AnnaBridge 126:abea610beb85 4207 #define EXTI_EMR_EM24 EXTI_EMR_MR24
AnnaBridge 126:abea610beb85 4208
AnnaBridge 126:abea610beb85 4209
AnnaBridge 126:abea610beb85 4210 /****************** Bit definition for EXTI_RTSR register *******************/
AnnaBridge 126:abea610beb85 4211 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 126:abea610beb85 4212 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 126:abea610beb85 4213 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 126:abea610beb85 4214 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 126:abea610beb85 4215 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 126:abea610beb85 4216 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 126:abea610beb85 4217 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 126:abea610beb85 4218 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 126:abea610beb85 4219 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 126:abea610beb85 4220 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 126:abea610beb85 4221 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 126:abea610beb85 4222 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 126:abea610beb85 4223 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 126:abea610beb85 4224 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 126:abea610beb85 4225 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 126:abea610beb85 4226 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 126:abea610beb85 4227 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 126:abea610beb85 4228 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 126:abea610beb85 4229 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
AnnaBridge 126:abea610beb85 4230 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 126:abea610beb85 4231 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 126:abea610beb85 4232 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 126:abea610beb85 4233 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
AnnaBridge 126:abea610beb85 4234 #define EXTI_RTSR_TR23 0x00800000U /*!< Rising trigger event configuration bit of line 23 */
AnnaBridge 126:abea610beb85 4235 #define EXTI_RTSR_TR24 0x01000000U /*!< Rising trigger event configuration bit of line 24 */
AnnaBridge 126:abea610beb85 4236
AnnaBridge 126:abea610beb85 4237 /****************** Bit definition for EXTI_FTSR register *******************/
AnnaBridge 126:abea610beb85 4238 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 126:abea610beb85 4239 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 126:abea610beb85 4240 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 126:abea610beb85 4241 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 126:abea610beb85 4242 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 126:abea610beb85 4243 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 126:abea610beb85 4244 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 126:abea610beb85 4245 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 126:abea610beb85 4246 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 126:abea610beb85 4247 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 126:abea610beb85 4248 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 126:abea610beb85 4249 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 126:abea610beb85 4250 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 126:abea610beb85 4251 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 126:abea610beb85 4252 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 126:abea610beb85 4253 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 126:abea610beb85 4254 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 126:abea610beb85 4255 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 126:abea610beb85 4256 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
AnnaBridge 126:abea610beb85 4257 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 126:abea610beb85 4258 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 126:abea610beb85 4259 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 126:abea610beb85 4260 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
AnnaBridge 126:abea610beb85 4261 #define EXTI_FTSR_TR23 0x00800000U /*!< Falling trigger event configuration bit of line 23 */
AnnaBridge 126:abea610beb85 4262 #define EXTI_FTSR_TR24 0x01000000U /*!< Falling trigger event configuration bit of line 24 */
AnnaBridge 126:abea610beb85 4263
AnnaBridge 126:abea610beb85 4264 /****************** Bit definition for EXTI_SWIER register ******************/
AnnaBridge 126:abea610beb85 4265 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
AnnaBridge 126:abea610beb85 4266 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
AnnaBridge 126:abea610beb85 4267 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
AnnaBridge 126:abea610beb85 4268 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
AnnaBridge 126:abea610beb85 4269 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
AnnaBridge 126:abea610beb85 4270 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
AnnaBridge 126:abea610beb85 4271 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
AnnaBridge 126:abea610beb85 4272 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
AnnaBridge 126:abea610beb85 4273 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
AnnaBridge 126:abea610beb85 4274 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
AnnaBridge 126:abea610beb85 4275 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
AnnaBridge 126:abea610beb85 4276 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
AnnaBridge 126:abea610beb85 4277 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
AnnaBridge 126:abea610beb85 4278 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
AnnaBridge 126:abea610beb85 4279 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
AnnaBridge 126:abea610beb85 4280 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
AnnaBridge 126:abea610beb85 4281 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
AnnaBridge 126:abea610beb85 4282 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
AnnaBridge 126:abea610beb85 4283 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
AnnaBridge 126:abea610beb85 4284 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
AnnaBridge 126:abea610beb85 4285 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
AnnaBridge 126:abea610beb85 4286 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
AnnaBridge 126:abea610beb85 4287 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
AnnaBridge 126:abea610beb85 4288 #define EXTI_SWIER_SWIER23 0x00800000U /*!< Software Interrupt on line 23 */
AnnaBridge 126:abea610beb85 4289 #define EXTI_SWIER_SWIER24 0x01000000U /*!< Software Interrupt on line 24 */
AnnaBridge 126:abea610beb85 4290
AnnaBridge 126:abea610beb85 4291 /******************* Bit definition for EXTI_PR register ********************/
AnnaBridge 126:abea610beb85 4292 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
AnnaBridge 126:abea610beb85 4293 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
AnnaBridge 126:abea610beb85 4294 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
AnnaBridge 126:abea610beb85 4295 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
AnnaBridge 126:abea610beb85 4296 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
AnnaBridge 126:abea610beb85 4297 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
AnnaBridge 126:abea610beb85 4298 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
AnnaBridge 126:abea610beb85 4299 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
AnnaBridge 126:abea610beb85 4300 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
AnnaBridge 126:abea610beb85 4301 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
AnnaBridge 126:abea610beb85 4302 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
AnnaBridge 126:abea610beb85 4303 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
AnnaBridge 126:abea610beb85 4304 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
AnnaBridge 126:abea610beb85 4305 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
AnnaBridge 126:abea610beb85 4306 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
AnnaBridge 126:abea610beb85 4307 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
AnnaBridge 126:abea610beb85 4308 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
AnnaBridge 126:abea610beb85 4309 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
AnnaBridge 126:abea610beb85 4310 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
AnnaBridge 126:abea610beb85 4311 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
AnnaBridge 126:abea610beb85 4312 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
AnnaBridge 126:abea610beb85 4313 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
AnnaBridge 126:abea610beb85 4314 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
AnnaBridge 126:abea610beb85 4315 #define EXTI_PR_PR23 0x00800000U /*!< Pending bit for line 23 */
AnnaBridge 126:abea610beb85 4316 #define EXTI_PR_PR24 0x01000000U /*!< Pending bit for line 24 */
AnnaBridge 126:abea610beb85 4317
AnnaBridge 126:abea610beb85 4318 /******************************************************************************/
AnnaBridge 126:abea610beb85 4319 /* */
AnnaBridge 126:abea610beb85 4320 /* FLASH */
AnnaBridge 126:abea610beb85 4321 /* */
AnnaBridge 126:abea610beb85 4322 /******************************************************************************/
AnnaBridge 126:abea610beb85 4323 /*
AnnaBridge 126:abea610beb85 4324 * @brief FLASH Total Sectors Number
AnnaBridge 126:abea610beb85 4325 */
AnnaBridge 126:abea610beb85 4326 #define FLASH_SECTOR_TOTAL 24
AnnaBridge 126:abea610beb85 4327
AnnaBridge 126:abea610beb85 4328 /******************* Bits definition for FLASH_ACR register *****************/
AnnaBridge 126:abea610beb85 4329 #define FLASH_ACR_LATENCY 0x0000000FU
AnnaBridge 126:abea610beb85 4330 #define FLASH_ACR_LATENCY_0WS 0x00000000U
AnnaBridge 126:abea610beb85 4331 #define FLASH_ACR_LATENCY_1WS 0x00000001U
AnnaBridge 126:abea610beb85 4332 #define FLASH_ACR_LATENCY_2WS 0x00000002U
AnnaBridge 126:abea610beb85 4333 #define FLASH_ACR_LATENCY_3WS 0x00000003U
AnnaBridge 126:abea610beb85 4334 #define FLASH_ACR_LATENCY_4WS 0x00000004U
AnnaBridge 126:abea610beb85 4335 #define FLASH_ACR_LATENCY_5WS 0x00000005U
AnnaBridge 126:abea610beb85 4336 #define FLASH_ACR_LATENCY_6WS 0x00000006U
AnnaBridge 126:abea610beb85 4337 #define FLASH_ACR_LATENCY_7WS 0x00000007U
AnnaBridge 126:abea610beb85 4338 #define FLASH_ACR_LATENCY_8WS 0x00000008U
AnnaBridge 126:abea610beb85 4339 #define FLASH_ACR_LATENCY_9WS 0x00000009U
AnnaBridge 126:abea610beb85 4340 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
AnnaBridge 126:abea610beb85 4341 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
AnnaBridge 126:abea610beb85 4342 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
AnnaBridge 126:abea610beb85 4343 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
AnnaBridge 126:abea610beb85 4344 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
AnnaBridge 126:abea610beb85 4345 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
AnnaBridge 126:abea610beb85 4346 #define FLASH_ACR_PRFTEN 0x00000100U
AnnaBridge 126:abea610beb85 4347 #define FLASH_ACR_ARTEN 0x00000200U
AnnaBridge 126:abea610beb85 4348 #define FLASH_ACR_ARTRST 0x00000800U
AnnaBridge 126:abea610beb85 4349
AnnaBridge 126:abea610beb85 4350 /******************* Bits definition for FLASH_SR register ******************/
AnnaBridge 126:abea610beb85 4351 #define FLASH_SR_EOP 0x00000001U
AnnaBridge 126:abea610beb85 4352 #define FLASH_SR_OPERR 0x00000002U
AnnaBridge 126:abea610beb85 4353 #define FLASH_SR_WRPERR 0x00000010U
AnnaBridge 126:abea610beb85 4354 #define FLASH_SR_PGAERR 0x00000020U
AnnaBridge 126:abea610beb85 4355 #define FLASH_SR_PGPERR 0x00000040U
AnnaBridge 126:abea610beb85 4356 #define FLASH_SR_ERSERR 0x00000080U
AnnaBridge 126:abea610beb85 4357 #define FLASH_SR_BSY 0x00010000U
AnnaBridge 126:abea610beb85 4358
AnnaBridge 126:abea610beb85 4359 /******************* Bits definition for FLASH_CR register ******************/
AnnaBridge 126:abea610beb85 4360 #define FLASH_CR_PG 0x00000001U
AnnaBridge 126:abea610beb85 4361 #define FLASH_CR_SER 0x00000002U
AnnaBridge 126:abea610beb85 4362 #define FLASH_CR_MER 0x00000004U
AnnaBridge 126:abea610beb85 4363 #define FLASH_CR_MER1 FLASH_CR_MER
AnnaBridge 126:abea610beb85 4364 #define FLASH_CR_SNB 0x000000F8U
AnnaBridge 126:abea610beb85 4365 #define FLASH_CR_SNB_0 0x00000008U
AnnaBridge 126:abea610beb85 4366 #define FLASH_CR_SNB_1 0x00000010U
AnnaBridge 126:abea610beb85 4367 #define FLASH_CR_SNB_2 0x00000020U
AnnaBridge 126:abea610beb85 4368 #define FLASH_CR_SNB_3 0x00000040U
AnnaBridge 126:abea610beb85 4369 #define FLASH_CR_SNB_4 0x00000080U
AnnaBridge 126:abea610beb85 4370 #define FLASH_CR_PSIZE 0x00000300U
AnnaBridge 126:abea610beb85 4371 #define FLASH_CR_PSIZE_0 0x00000100U
AnnaBridge 126:abea610beb85 4372 #define FLASH_CR_PSIZE_1 0x00000200U
AnnaBridge 126:abea610beb85 4373 #define FLASH_CR_MER2 0x00008000U
AnnaBridge 126:abea610beb85 4374 #define FLASH_CR_STRT 0x00010000U
AnnaBridge 126:abea610beb85 4375 #define FLASH_CR_EOPIE 0x01000000U
AnnaBridge 126:abea610beb85 4376 #define FLASH_CR_ERRIE 0x02000000U
AnnaBridge 126:abea610beb85 4377 #define FLASH_CR_LOCK 0x80000000U
AnnaBridge 126:abea610beb85 4378
AnnaBridge 126:abea610beb85 4379 /******************* Bits definition for FLASH_OPTCR register ***************/
AnnaBridge 126:abea610beb85 4380 #define FLASH_OPTCR_OPTLOCK 0x00000001U
AnnaBridge 126:abea610beb85 4381 #define FLASH_OPTCR_OPTSTRT 0x00000002U
AnnaBridge 126:abea610beb85 4382 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
AnnaBridge 126:abea610beb85 4383 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
AnnaBridge 126:abea610beb85 4384 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
AnnaBridge 126:abea610beb85 4385 #define FLASH_OPTCR_WWDG_SW 0x00000010U
AnnaBridge 126:abea610beb85 4386 #define FLASH_OPTCR_IWDG_SW 0x00000020U
AnnaBridge 126:abea610beb85 4387 #define FLASH_OPTCR_nRST_STOP 0x00000040U
AnnaBridge 126:abea610beb85 4388 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
AnnaBridge 126:abea610beb85 4389 #define FLASH_OPTCR_RDP 0x0000FF00U
AnnaBridge 126:abea610beb85 4390 #define FLASH_OPTCR_RDP_0 0x00000100U
AnnaBridge 126:abea610beb85 4391 #define FLASH_OPTCR_RDP_1 0x00000200U
AnnaBridge 126:abea610beb85 4392 #define FLASH_OPTCR_RDP_2 0x00000400U
AnnaBridge 126:abea610beb85 4393 #define FLASH_OPTCR_RDP_3 0x00000800U
AnnaBridge 126:abea610beb85 4394 #define FLASH_OPTCR_RDP_4 0x00001000U
AnnaBridge 126:abea610beb85 4395 #define FLASH_OPTCR_RDP_5 0x00002000U
AnnaBridge 126:abea610beb85 4396 #define FLASH_OPTCR_RDP_6 0x00004000U
AnnaBridge 126:abea610beb85 4397 #define FLASH_OPTCR_RDP_7 0x00008000U
AnnaBridge 126:abea610beb85 4398 #define FLASH_OPTCR_nWRP 0x0FFF0000U
AnnaBridge 126:abea610beb85 4399 #define FLASH_OPTCR_nWRP_0 0x00010000U
AnnaBridge 126:abea610beb85 4400 #define FLASH_OPTCR_nWRP_1 0x00020000U
AnnaBridge 126:abea610beb85 4401 #define FLASH_OPTCR_nWRP_2 0x00040000U
AnnaBridge 126:abea610beb85 4402 #define FLASH_OPTCR_nWRP_3 0x00080000U
AnnaBridge 126:abea610beb85 4403 #define FLASH_OPTCR_nWRP_4 0x00100000U
AnnaBridge 126:abea610beb85 4404 #define FLASH_OPTCR_nWRP_5 0x00200000U
AnnaBridge 126:abea610beb85 4405 #define FLASH_OPTCR_nWRP_6 0x00400000U
AnnaBridge 126:abea610beb85 4406 #define FLASH_OPTCR_nWRP_7 0x00800000U
AnnaBridge 126:abea610beb85 4407 #define FLASH_OPTCR_nWRP_8 0x01000000U
AnnaBridge 126:abea610beb85 4408 #define FLASH_OPTCR_nWRP_9 0x02000000U
AnnaBridge 126:abea610beb85 4409 #define FLASH_OPTCR_nWRP_10 0x04000000U
AnnaBridge 126:abea610beb85 4410 #define FLASH_OPTCR_nWRP_11 0x08000000U
AnnaBridge 126:abea610beb85 4411 #define FLASH_OPTCR_nDBOOT 0x10000000U
AnnaBridge 126:abea610beb85 4412 #define FLASH_OPTCR_nDBANK 0x20000000U
AnnaBridge 126:abea610beb85 4413 #define FLASH_OPTCR_IWDG_STDBY 0x40000000U
AnnaBridge 126:abea610beb85 4414 #define FLASH_OPTCR_IWDG_STOP 0x80000000U
AnnaBridge 126:abea610beb85 4415
AnnaBridge 126:abea610beb85 4416 /******************* Bits definition for FLASH_OPTCR1 register ***************/
AnnaBridge 126:abea610beb85 4417 #define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
AnnaBridge 126:abea610beb85 4418 #define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
AnnaBridge 126:abea610beb85 4419
AnnaBridge 126:abea610beb85 4420 /******************************************************************************/
AnnaBridge 126:abea610beb85 4421 /* */
AnnaBridge 126:abea610beb85 4422 /* Flexible Memory Controller */
AnnaBridge 126:abea610beb85 4423 /* */
AnnaBridge 126:abea610beb85 4424 /******************************************************************************/
AnnaBridge 126:abea610beb85 4425 /****************** Bit definition for FMC_BCR1 register *******************/
AnnaBridge 126:abea610beb85 4426 #define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
AnnaBridge 126:abea610beb85 4427 #define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
AnnaBridge 126:abea610beb85 4428 #define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 126:abea610beb85 4429 #define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4430 #define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4431 #define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 126:abea610beb85 4432 #define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4433 #define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4434 #define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
AnnaBridge 126:abea610beb85 4435 #define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
AnnaBridge 126:abea610beb85 4436 #define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
AnnaBridge 126:abea610beb85 4437 #define FMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
AnnaBridge 126:abea610beb85 4438 #define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
AnnaBridge 126:abea610beb85 4439 #define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
AnnaBridge 126:abea610beb85 4440 #define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
AnnaBridge 126:abea610beb85 4441 #define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
AnnaBridge 126:abea610beb85 4442 #define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
AnnaBridge 126:abea610beb85 4443 #define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
AnnaBridge 126:abea610beb85 4444 #define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4445 #define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4446 #define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4447 #define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
AnnaBridge 126:abea610beb85 4448 #define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
AnnaBridge 126:abea610beb85 4449 #define FMC_BCR1_WFDIS 0x00200000U /*!<Write FIFO Disable */
AnnaBridge 126:abea610beb85 4450
AnnaBridge 126:abea610beb85 4451 /****************** Bit definition for FMC_BCR2 register *******************/
AnnaBridge 126:abea610beb85 4452 #define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
AnnaBridge 126:abea610beb85 4453 #define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
AnnaBridge 126:abea610beb85 4454 #define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 126:abea610beb85 4455 #define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4456 #define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4457 #define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 126:abea610beb85 4458 #define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4459 #define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4460 #define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
AnnaBridge 126:abea610beb85 4461 #define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
AnnaBridge 126:abea610beb85 4462 #define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
AnnaBridge 126:abea610beb85 4463 #define FMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
AnnaBridge 126:abea610beb85 4464 #define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
AnnaBridge 126:abea610beb85 4465 #define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
AnnaBridge 126:abea610beb85 4466 #define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
AnnaBridge 126:abea610beb85 4467 #define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
AnnaBridge 126:abea610beb85 4468 #define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
AnnaBridge 126:abea610beb85 4469 #define FMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
AnnaBridge 126:abea610beb85 4470 #define FMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4471 #define FMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4472 #define FMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4473 #define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
AnnaBridge 126:abea610beb85 4474
AnnaBridge 126:abea610beb85 4475 /****************** Bit definition for FMC_BCR3 register *******************/
AnnaBridge 126:abea610beb85 4476 #define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
AnnaBridge 126:abea610beb85 4477 #define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
AnnaBridge 126:abea610beb85 4478 #define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 126:abea610beb85 4479 #define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4480 #define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4481 #define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 126:abea610beb85 4482 #define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4483 #define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4484 #define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
AnnaBridge 126:abea610beb85 4485 #define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
AnnaBridge 126:abea610beb85 4486 #define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
AnnaBridge 126:abea610beb85 4487 #define FMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
AnnaBridge 126:abea610beb85 4488 #define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
AnnaBridge 126:abea610beb85 4489 #define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
AnnaBridge 126:abea610beb85 4490 #define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
AnnaBridge 126:abea610beb85 4491 #define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
AnnaBridge 126:abea610beb85 4492 #define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
AnnaBridge 126:abea610beb85 4493 #define FMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
AnnaBridge 126:abea610beb85 4494 #define FMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4495 #define FMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4496 #define FMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4497 #define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
AnnaBridge 126:abea610beb85 4498
AnnaBridge 126:abea610beb85 4499 /****************** Bit definition for FMC_BCR4 register *******************/
AnnaBridge 126:abea610beb85 4500 #define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
AnnaBridge 126:abea610beb85 4501 #define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
AnnaBridge 126:abea610beb85 4502 #define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 126:abea610beb85 4503 #define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4504 #define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4505 #define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 126:abea610beb85 4506 #define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4507 #define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4508 #define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
AnnaBridge 126:abea610beb85 4509 #define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
AnnaBridge 126:abea610beb85 4510 #define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
AnnaBridge 126:abea610beb85 4511 #define FMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
AnnaBridge 126:abea610beb85 4512 #define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
AnnaBridge 126:abea610beb85 4513 #define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
AnnaBridge 126:abea610beb85 4514 #define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
AnnaBridge 126:abea610beb85 4515 #define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
AnnaBridge 126:abea610beb85 4516 #define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
AnnaBridge 126:abea610beb85 4517 #define FMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
AnnaBridge 126:abea610beb85 4518 #define FMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4519 #define FMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4520 #define FMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4521 #define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
AnnaBridge 126:abea610beb85 4522
AnnaBridge 126:abea610beb85 4523 /****************** Bit definition for FMC_BTR1 register ******************/
AnnaBridge 126:abea610beb85 4524 #define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 126:abea610beb85 4525 #define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4526 #define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4527 #define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4528 #define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4529 #define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 126:abea610beb85 4530 #define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4531 #define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4532 #define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4533 #define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4534 #define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 126:abea610beb85 4535 #define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4536 #define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4537 #define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4538 #define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4539 #define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4540 #define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4541 #define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4542 #define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4543 #define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 126:abea610beb85 4544 #define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4545 #define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4546 #define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4547 #define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4548 #define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 126:abea610beb85 4549 #define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4550 #define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4551 #define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4552 #define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4553 #define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 126:abea610beb85 4554 #define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4555 #define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4556 #define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4557 #define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4558 #define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 126:abea610beb85 4559 #define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4560 #define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4561
AnnaBridge 126:abea610beb85 4562 /****************** Bit definition for FMC_BTR2 register *******************/
AnnaBridge 126:abea610beb85 4563 #define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 126:abea610beb85 4564 #define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4565 #define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4566 #define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4567 #define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4568 #define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 126:abea610beb85 4569 #define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4570 #define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4571 #define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4572 #define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4573 #define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 126:abea610beb85 4574 #define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4575 #define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4576 #define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4577 #define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4578 #define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4579 #define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4580 #define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4581 #define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4582 #define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 126:abea610beb85 4583 #define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4584 #define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4585 #define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4586 #define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4587 #define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 126:abea610beb85 4588 #define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4589 #define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4590 #define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4591 #define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4592 #define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 126:abea610beb85 4593 #define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4594 #define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4595 #define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4596 #define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4597 #define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 126:abea610beb85 4598 #define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4599 #define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4600
AnnaBridge 126:abea610beb85 4601 /******************* Bit definition for FMC_BTR3 register *******************/
AnnaBridge 126:abea610beb85 4602 #define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 126:abea610beb85 4603 #define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4604 #define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4605 #define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4606 #define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4607 #define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 126:abea610beb85 4608 #define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4609 #define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4610 #define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4611 #define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4612 #define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 126:abea610beb85 4613 #define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4614 #define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4615 #define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4616 #define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4617 #define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4618 #define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4619 #define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4620 #define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4621 #define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 126:abea610beb85 4622 #define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4623 #define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4624 #define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4625 #define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4626 #define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 126:abea610beb85 4627 #define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4628 #define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4629 #define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4630 #define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4631 #define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 126:abea610beb85 4632 #define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4633 #define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4634 #define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4635 #define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4636 #define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 126:abea610beb85 4637 #define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4638 #define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4639
AnnaBridge 126:abea610beb85 4640 /****************** Bit definition for FMC_BTR4 register *******************/
AnnaBridge 126:abea610beb85 4641 #define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 126:abea610beb85 4642 #define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4643 #define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4644 #define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4645 #define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4646 #define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 126:abea610beb85 4647 #define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4648 #define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4649 #define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4650 #define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4651 #define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 126:abea610beb85 4652 #define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4653 #define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4654 #define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4655 #define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4656 #define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4657 #define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4658 #define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4659 #define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4660 #define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 126:abea610beb85 4661 #define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4662 #define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4663 #define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4664 #define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4665 #define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 126:abea610beb85 4666 #define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4667 #define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4668 #define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4669 #define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4670 #define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 126:abea610beb85 4671 #define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4672 #define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4673 #define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4674 #define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4675 #define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 126:abea610beb85 4676 #define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4677 #define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4678
AnnaBridge 126:abea610beb85 4679 /****************** Bit definition for FMC_BWTR1 register ******************/
AnnaBridge 126:abea610beb85 4680 #define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 126:abea610beb85 4681 #define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4682 #define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4683 #define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4684 #define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4685 #define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 126:abea610beb85 4686 #define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4687 #define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4688 #define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4689 #define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4690 #define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 126:abea610beb85 4691 #define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4692 #define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4693 #define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4694 #define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4695 #define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4696 #define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4697 #define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4698 #define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4699 #define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 126:abea610beb85 4700 #define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4701 #define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4702 #define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4703 #define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4704 #define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 126:abea610beb85 4705 #define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4706 #define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4707
AnnaBridge 126:abea610beb85 4708 /****************** Bit definition for FMC_BWTR2 register ******************/
AnnaBridge 126:abea610beb85 4709 #define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 126:abea610beb85 4710 #define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4711 #define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4712 #define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4713 #define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4714 #define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 126:abea610beb85 4715 #define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4716 #define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4717 #define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4718 #define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4719 #define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 126:abea610beb85 4720 #define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4721 #define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4722 #define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4723 #define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4724 #define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4725 #define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4726 #define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4727 #define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4728 #define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 126:abea610beb85 4729 #define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4730 #define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4731 #define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4732 #define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4733 #define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 126:abea610beb85 4734 #define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4735 #define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4736
AnnaBridge 126:abea610beb85 4737 /****************** Bit definition for FMC_BWTR3 register ******************/
AnnaBridge 126:abea610beb85 4738 #define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 126:abea610beb85 4739 #define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4740 #define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4741 #define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4742 #define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4743 #define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 126:abea610beb85 4744 #define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4745 #define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4746 #define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4747 #define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4748 #define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 126:abea610beb85 4749 #define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4750 #define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4751 #define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4752 #define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4753 #define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4754 #define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4755 #define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4756 #define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4757 #define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 126:abea610beb85 4758 #define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4759 #define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4760 #define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4761 #define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4762 #define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 126:abea610beb85 4763 #define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4764 #define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4765
AnnaBridge 126:abea610beb85 4766 /****************** Bit definition for FMC_BWTR4 register ******************/
AnnaBridge 126:abea610beb85 4767 #define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 126:abea610beb85 4768 #define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4769 #define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4770 #define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4771 #define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4772 #define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 126:abea610beb85 4773 #define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4774 #define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4775 #define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4776 #define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4777 #define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 126:abea610beb85 4778 #define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4779 #define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4780 #define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4781 #define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4782 #define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4783 #define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4784 #define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4785 #define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4786 #define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 126:abea610beb85 4787 #define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4788 #define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4789 #define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4790 #define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4791 #define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 126:abea610beb85 4792 #define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4793 #define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4794
AnnaBridge 126:abea610beb85 4795 /****************** Bit definition for FMC_PCR register *******************/
AnnaBridge 126:abea610beb85 4796 #define FMC_PCR_PWAITEN 0x00000002U /*!<Wait feature enable bit */
AnnaBridge 126:abea610beb85 4797 #define FMC_PCR_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
AnnaBridge 126:abea610beb85 4798 #define FMC_PCR_PTYP 0x00000008U /*!<Memory type */
AnnaBridge 126:abea610beb85 4799 #define FMC_PCR_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
AnnaBridge 126:abea610beb85 4800 #define FMC_PCR_PWID_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4801 #define FMC_PCR_PWID_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4802 #define FMC_PCR_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
AnnaBridge 126:abea610beb85 4803 #define FMC_PCR_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
AnnaBridge 126:abea610beb85 4804 #define FMC_PCR_TCLR_0 0x00000200U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4805 #define FMC_PCR_TCLR_1 0x00000400U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4806 #define FMC_PCR_TCLR_2 0x00000800U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4807 #define FMC_PCR_TCLR_3 0x00001000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4808 #define FMC_PCR_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
AnnaBridge 126:abea610beb85 4809 #define FMC_PCR_TAR_0 0x00002000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4810 #define FMC_PCR_TAR_1 0x00004000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4811 #define FMC_PCR_TAR_2 0x00008000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4812 #define FMC_PCR_TAR_3 0x00010000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4813 #define FMC_PCR_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
AnnaBridge 126:abea610beb85 4814 #define FMC_PCR_ECCPS_0 0x00020000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4815 #define FMC_PCR_ECCPS_1 0x00040000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4816 #define FMC_PCR_ECCPS_2 0x00080000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4817
AnnaBridge 126:abea610beb85 4818 /******************* Bit definition for FMC_SR register *******************/
AnnaBridge 126:abea610beb85 4819 #define FMC_SR_IRS 0x01U /*!<Interrupt Rising Edge status */
AnnaBridge 126:abea610beb85 4820 #define FMC_SR_ILS 0x02U /*!<Interrupt Level status */
AnnaBridge 126:abea610beb85 4821 #define FMC_SR_IFS 0x04U /*!<Interrupt Falling Edge status */
AnnaBridge 126:abea610beb85 4822 #define FMC_SR_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
AnnaBridge 126:abea610beb85 4823 #define FMC_SR_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
AnnaBridge 126:abea610beb85 4824 #define FMC_SR_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
AnnaBridge 126:abea610beb85 4825 #define FMC_SR_FEMPT 0x40U /*!<FIFO empty */
AnnaBridge 126:abea610beb85 4826
AnnaBridge 126:abea610beb85 4827 /****************** Bit definition for FMC_PMEM register ******************/
AnnaBridge 126:abea610beb85 4828 #define FMC_PMEM_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
AnnaBridge 126:abea610beb85 4829 #define FMC_PMEM_MEMSET3_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4830 #define FMC_PMEM_MEMSET3_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4831 #define FMC_PMEM_MEMSET3_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4832 #define FMC_PMEM_MEMSET3_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4833 #define FMC_PMEM_MEMSET3_4 0x00000010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4834 #define FMC_PMEM_MEMSET3_5 0x00000020U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4835 #define FMC_PMEM_MEMSET3_6 0x00000040U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4836 #define FMC_PMEM_MEMSET3_7 0x00000080U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4837 #define FMC_PMEM_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
AnnaBridge 126:abea610beb85 4838 #define FMC_PMEM_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4839 #define FMC_PMEM_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4840 #define FMC_PMEM_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4841 #define FMC_PMEM_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4842 #define FMC_PMEM_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4843 #define FMC_PMEM_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4844 #define FMC_PMEM_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4845 #define FMC_PMEM_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4846 #define FMC_PMEM_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
AnnaBridge 126:abea610beb85 4847 #define FMC_PMEM_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4848 #define FMC_PMEM_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4849 #define FMC_PMEM_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4850 #define FMC_PMEM_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4851 #define FMC_PMEM_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4852 #define FMC_PMEM_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4853 #define FMC_PMEM_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4854 #define FMC_PMEM_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4855 #define FMC_PMEM_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
AnnaBridge 126:abea610beb85 4856 #define FMC_PMEM_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4857 #define FMC_PMEM_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4858 #define FMC_PMEM_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4859 #define FMC_PMEM_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4860 #define FMC_PMEM_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4861 #define FMC_PMEM_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4862 #define FMC_PMEM_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4863 #define FMC_PMEM_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4864
AnnaBridge 126:abea610beb85 4865 /****************** Bit definition for FMC_PATT register ******************/
AnnaBridge 126:abea610beb85 4866 #define FMC_PATT_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
AnnaBridge 126:abea610beb85 4867 #define FMC_PATT_ATTSET3_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4868 #define FMC_PATT_ATTSET3_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4869 #define FMC_PATT_ATTSET3_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4870 #define FMC_PATT_ATTSET3_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4871 #define FMC_PATT_ATTSET3_4 0x00000010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4872 #define FMC_PATT_ATTSET3_5 0x00000020U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4873 #define FMC_PATT_ATTSET3_6 0x00000040U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4874 #define FMC_PATT_ATTSET3_7 0x00000080U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4875 #define FMC_PATT_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
AnnaBridge 126:abea610beb85 4876 #define FMC_PATT_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4877 #define FMC_PATT_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4878 #define FMC_PATT_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4879 #define FMC_PATT_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4880 #define FMC_PATT_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4881 #define FMC_PATT_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4882 #define FMC_PATT_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4883 #define FMC_PATT_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4884 #define FMC_PATT_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
AnnaBridge 126:abea610beb85 4885 #define FMC_PATT_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4886 #define FMC_PATT_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4887 #define FMC_PATT_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4888 #define FMC_PATT_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4889 #define FMC_PATT_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4890 #define FMC_PATT_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4891 #define FMC_PATT_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4892 #define FMC_PATT_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4893 #define FMC_PATT_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
AnnaBridge 126:abea610beb85 4894 #define FMC_PATT_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4895 #define FMC_PATT_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4896 #define FMC_PATT_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4897 #define FMC_PATT_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4898 #define FMC_PATT_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 4899 #define FMC_PATT_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 4900 #define FMC_PATT_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 4901 #define FMC_PATT_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 4902
AnnaBridge 126:abea610beb85 4903 /****************** Bit definition for FMC_ECCR register ******************/
AnnaBridge 126:abea610beb85 4904 #define FMC_ECCR_ECC3 0xFFFFFFFFU /*!<ECC result */
AnnaBridge 126:abea610beb85 4905
AnnaBridge 126:abea610beb85 4906 /****************** Bit definition for FMC_SDCR1 register ******************/
AnnaBridge 126:abea610beb85 4907 #define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
AnnaBridge 126:abea610beb85 4908 #define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4909 #define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4910 #define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 126:abea610beb85 4911 #define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4912 #define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4913 #define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 126:abea610beb85 4914 #define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4915 #define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4916 #define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */
AnnaBridge 126:abea610beb85 4917 #define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
AnnaBridge 126:abea610beb85 4918 #define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4919 #define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4920 #define FMC_SDCR1_WP 0x00000200U /*!<Write protection */
AnnaBridge 126:abea610beb85 4921 #define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */
AnnaBridge 126:abea610beb85 4922 #define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4923 #define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4924 #define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */
AnnaBridge 126:abea610beb85 4925 #define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */
AnnaBridge 126:abea610beb85 4926 #define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4927 #define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4928
AnnaBridge 126:abea610beb85 4929 /****************** Bit definition for FMC_SDCR2 register ******************/
AnnaBridge 126:abea610beb85 4930 #define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
AnnaBridge 126:abea610beb85 4931 #define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4932 #define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4933 #define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 126:abea610beb85 4934 #define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4935 #define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4936 #define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 126:abea610beb85 4937 #define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4938 #define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4939 #define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */
AnnaBridge 126:abea610beb85 4940 #define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
AnnaBridge 126:abea610beb85 4941 #define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4942 #define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4943 #define FMC_SDCR2_WP 0x00000200U /*!<Write protection */
AnnaBridge 126:abea610beb85 4944 #define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */
AnnaBridge 126:abea610beb85 4945 #define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4946 #define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4947 #define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */
AnnaBridge 126:abea610beb85 4948 #define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */
AnnaBridge 126:abea610beb85 4949 #define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4950 #define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4951
AnnaBridge 126:abea610beb85 4952 /****************** Bit definition for FMC_SDTR1 register ******************/
AnnaBridge 126:abea610beb85 4953 #define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
AnnaBridge 126:abea610beb85 4954 #define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4955 #define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4956 #define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4957 #define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4958 #define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
AnnaBridge 126:abea610beb85 4959 #define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4960 #define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4961 #define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4962 #define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4963 #define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
AnnaBridge 126:abea610beb85 4964 #define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4965 #define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4966 #define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4967 #define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4968 #define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
AnnaBridge 126:abea610beb85 4969 #define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4970 #define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4971 #define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4972 #define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
AnnaBridge 126:abea610beb85 4973 #define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4974 #define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4975 #define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4976 #define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
AnnaBridge 126:abea610beb85 4977 #define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4978 #define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4979 #define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4980 #define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
AnnaBridge 126:abea610beb85 4981 #define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4982 #define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4983 #define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4984
AnnaBridge 126:abea610beb85 4985 /****************** Bit definition for FMC_SDTR2 register ******************/
AnnaBridge 126:abea610beb85 4986 #define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
AnnaBridge 126:abea610beb85 4987 #define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4988 #define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4989 #define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4990 #define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4991 #define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
AnnaBridge 126:abea610beb85 4992 #define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4993 #define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4994 #define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 4995 #define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 4996 #define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
AnnaBridge 126:abea610beb85 4997 #define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 4998 #define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 4999 #define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 5000 #define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 5001 #define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
AnnaBridge 126:abea610beb85 5002 #define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 5003 #define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 5004 #define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 5005 #define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
AnnaBridge 126:abea610beb85 5006 #define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 5007 #define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 5008 #define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 5009 #define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
AnnaBridge 126:abea610beb85 5010 #define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 5011 #define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 5012 #define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 5013 #define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
AnnaBridge 126:abea610beb85 5014 #define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 5015 #define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 5016 #define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 5017
AnnaBridge 126:abea610beb85 5018 /****************** Bit definition for FMC_SDCMR register ******************/
AnnaBridge 126:abea610beb85 5019 #define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */
AnnaBridge 126:abea610beb85 5020 #define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 5021 #define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 5022 #define FMC_SDCMR_MODE_2 0x00000003U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 5023 #define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */
AnnaBridge 126:abea610beb85 5024 #define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */
AnnaBridge 126:abea610beb85 5025 #define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */
AnnaBridge 126:abea610beb85 5026 #define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 5027 #define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 5028 #define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 5029 #define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 5030 #define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */
AnnaBridge 126:abea610beb85 5031
AnnaBridge 126:abea610beb85 5032 /****************** Bit definition for FMC_SDRTR register ******************/
AnnaBridge 126:abea610beb85 5033 #define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */
AnnaBridge 126:abea610beb85 5034 #define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */
AnnaBridge 126:abea610beb85 5035 #define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */
AnnaBridge 126:abea610beb85 5036
AnnaBridge 126:abea610beb85 5037 /****************** Bit definition for FMC_SDSR register ******************/
AnnaBridge 126:abea610beb85 5038 #define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */
AnnaBridge 126:abea610beb85 5039 #define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */
AnnaBridge 126:abea610beb85 5040 #define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 5041 #define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 5042 #define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */
AnnaBridge 126:abea610beb85 5043 #define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 5044 #define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 5045 #define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */
AnnaBridge 126:abea610beb85 5046
AnnaBridge 126:abea610beb85 5047 /******************************************************************************/
AnnaBridge 126:abea610beb85 5048 /* */
AnnaBridge 126:abea610beb85 5049 /* General Purpose I/O */
AnnaBridge 126:abea610beb85 5050 /* */
AnnaBridge 126:abea610beb85 5051 /******************************************************************************/
AnnaBridge 126:abea610beb85 5052 /****************** Bits definition for GPIO_MODER register *****************/
AnnaBridge 126:abea610beb85 5053 #define GPIO_MODER_MODER0 0x00000003U
AnnaBridge 126:abea610beb85 5054 #define GPIO_MODER_MODER0_0 0x00000001U
AnnaBridge 126:abea610beb85 5055 #define GPIO_MODER_MODER0_1 0x00000002U
AnnaBridge 126:abea610beb85 5056 #define GPIO_MODER_MODER1 0x0000000CU
AnnaBridge 126:abea610beb85 5057 #define GPIO_MODER_MODER1_0 0x00000004U
AnnaBridge 126:abea610beb85 5058 #define GPIO_MODER_MODER1_1 0x00000008U
AnnaBridge 126:abea610beb85 5059 #define GPIO_MODER_MODER2 0x00000030U
AnnaBridge 126:abea610beb85 5060 #define GPIO_MODER_MODER2_0 0x00000010U
AnnaBridge 126:abea610beb85 5061 #define GPIO_MODER_MODER2_1 0x00000020U
AnnaBridge 126:abea610beb85 5062 #define GPIO_MODER_MODER3 0x000000C0U
AnnaBridge 126:abea610beb85 5063 #define GPIO_MODER_MODER3_0 0x00000040U
AnnaBridge 126:abea610beb85 5064 #define GPIO_MODER_MODER3_1 0x00000080U
AnnaBridge 126:abea610beb85 5065 #define GPIO_MODER_MODER4 0x00000300U
AnnaBridge 126:abea610beb85 5066 #define GPIO_MODER_MODER4_0 0x00000100U
AnnaBridge 126:abea610beb85 5067 #define GPIO_MODER_MODER4_1 0x00000200U
AnnaBridge 126:abea610beb85 5068 #define GPIO_MODER_MODER5 0x00000C00U
AnnaBridge 126:abea610beb85 5069 #define GPIO_MODER_MODER5_0 0x00000400U
AnnaBridge 126:abea610beb85 5070 #define GPIO_MODER_MODER5_1 0x00000800U
AnnaBridge 126:abea610beb85 5071 #define GPIO_MODER_MODER6 0x00003000U
AnnaBridge 126:abea610beb85 5072 #define GPIO_MODER_MODER6_0 0x00001000U
AnnaBridge 126:abea610beb85 5073 #define GPIO_MODER_MODER6_1 0x00002000U
AnnaBridge 126:abea610beb85 5074 #define GPIO_MODER_MODER7 0x0000C000U
AnnaBridge 126:abea610beb85 5075 #define GPIO_MODER_MODER7_0 0x00004000U
AnnaBridge 126:abea610beb85 5076 #define GPIO_MODER_MODER7_1 0x00008000U
AnnaBridge 126:abea610beb85 5077 #define GPIO_MODER_MODER8 0x00030000U
AnnaBridge 126:abea610beb85 5078 #define GPIO_MODER_MODER8_0 0x00010000U
AnnaBridge 126:abea610beb85 5079 #define GPIO_MODER_MODER8_1 0x00020000U
AnnaBridge 126:abea610beb85 5080 #define GPIO_MODER_MODER9 0x000C0000U
AnnaBridge 126:abea610beb85 5081 #define GPIO_MODER_MODER9_0 0x00040000U
AnnaBridge 126:abea610beb85 5082 #define GPIO_MODER_MODER9_1 0x00080000U
AnnaBridge 126:abea610beb85 5083 #define GPIO_MODER_MODER10 0x00300000U
AnnaBridge 126:abea610beb85 5084 #define GPIO_MODER_MODER10_0 0x00100000U
AnnaBridge 126:abea610beb85 5085 #define GPIO_MODER_MODER10_1 0x00200000U
AnnaBridge 126:abea610beb85 5086 #define GPIO_MODER_MODER11 0x00C00000U
AnnaBridge 126:abea610beb85 5087 #define GPIO_MODER_MODER11_0 0x00400000U
AnnaBridge 126:abea610beb85 5088 #define GPIO_MODER_MODER11_1 0x00800000U
AnnaBridge 126:abea610beb85 5089 #define GPIO_MODER_MODER12 0x03000000U
AnnaBridge 126:abea610beb85 5090 #define GPIO_MODER_MODER12_0 0x01000000U
AnnaBridge 126:abea610beb85 5091 #define GPIO_MODER_MODER12_1 0x02000000U
AnnaBridge 126:abea610beb85 5092 #define GPIO_MODER_MODER13 0x0C000000U
AnnaBridge 126:abea610beb85 5093 #define GPIO_MODER_MODER13_0 0x04000000U
AnnaBridge 126:abea610beb85 5094 #define GPIO_MODER_MODER13_1 0x08000000U
AnnaBridge 126:abea610beb85 5095 #define GPIO_MODER_MODER14 0x30000000U
AnnaBridge 126:abea610beb85 5096 #define GPIO_MODER_MODER14_0 0x10000000U
AnnaBridge 126:abea610beb85 5097 #define GPIO_MODER_MODER14_1 0x20000000U
AnnaBridge 126:abea610beb85 5098 #define GPIO_MODER_MODER15 0xC0000000U
AnnaBridge 126:abea610beb85 5099 #define GPIO_MODER_MODER15_0 0x40000000U
AnnaBridge 126:abea610beb85 5100 #define GPIO_MODER_MODER15_1 0x80000000U
AnnaBridge 126:abea610beb85 5101
AnnaBridge 126:abea610beb85 5102 /****************** Bits definition for GPIO_OTYPER register ****************/
AnnaBridge 126:abea610beb85 5103 #define GPIO_OTYPER_OT_0 0x00000001U
AnnaBridge 126:abea610beb85 5104 #define GPIO_OTYPER_OT_1 0x00000002U
AnnaBridge 126:abea610beb85 5105 #define GPIO_OTYPER_OT_2 0x00000004U
AnnaBridge 126:abea610beb85 5106 #define GPIO_OTYPER_OT_3 0x00000008U
AnnaBridge 126:abea610beb85 5107 #define GPIO_OTYPER_OT_4 0x00000010U
AnnaBridge 126:abea610beb85 5108 #define GPIO_OTYPER_OT_5 0x00000020U
AnnaBridge 126:abea610beb85 5109 #define GPIO_OTYPER_OT_6 0x00000040U
AnnaBridge 126:abea610beb85 5110 #define GPIO_OTYPER_OT_7 0x00000080U
AnnaBridge 126:abea610beb85 5111 #define GPIO_OTYPER_OT_8 0x00000100U
AnnaBridge 126:abea610beb85 5112 #define GPIO_OTYPER_OT_9 0x00000200U
AnnaBridge 126:abea610beb85 5113 #define GPIO_OTYPER_OT_10 0x00000400U
AnnaBridge 126:abea610beb85 5114 #define GPIO_OTYPER_OT_11 0x00000800U
AnnaBridge 126:abea610beb85 5115 #define GPIO_OTYPER_OT_12 0x00001000U
AnnaBridge 126:abea610beb85 5116 #define GPIO_OTYPER_OT_13 0x00002000U
AnnaBridge 126:abea610beb85 5117 #define GPIO_OTYPER_OT_14 0x00004000U
AnnaBridge 126:abea610beb85 5118 #define GPIO_OTYPER_OT_15 0x00008000U
AnnaBridge 126:abea610beb85 5119
AnnaBridge 126:abea610beb85 5120 /****************** Bits definition for GPIO_OSPEEDR register ***************/
AnnaBridge 126:abea610beb85 5121 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
AnnaBridge 126:abea610beb85 5122 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
AnnaBridge 126:abea610beb85 5123 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
AnnaBridge 126:abea610beb85 5124 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
AnnaBridge 126:abea610beb85 5125 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
AnnaBridge 126:abea610beb85 5126 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
AnnaBridge 126:abea610beb85 5127 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
AnnaBridge 126:abea610beb85 5128 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
AnnaBridge 126:abea610beb85 5129 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
AnnaBridge 126:abea610beb85 5130 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
AnnaBridge 126:abea610beb85 5131 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
AnnaBridge 126:abea610beb85 5132 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
AnnaBridge 126:abea610beb85 5133 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
AnnaBridge 126:abea610beb85 5134 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
AnnaBridge 126:abea610beb85 5135 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
AnnaBridge 126:abea610beb85 5136 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
AnnaBridge 126:abea610beb85 5137 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
AnnaBridge 126:abea610beb85 5138 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
AnnaBridge 126:abea610beb85 5139 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
AnnaBridge 126:abea610beb85 5140 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
AnnaBridge 126:abea610beb85 5141 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
AnnaBridge 126:abea610beb85 5142 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
AnnaBridge 126:abea610beb85 5143 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
AnnaBridge 126:abea610beb85 5144 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
AnnaBridge 126:abea610beb85 5145 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
AnnaBridge 126:abea610beb85 5146 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
AnnaBridge 126:abea610beb85 5147 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
AnnaBridge 126:abea610beb85 5148 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
AnnaBridge 126:abea610beb85 5149 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
AnnaBridge 126:abea610beb85 5150 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
AnnaBridge 126:abea610beb85 5151 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
AnnaBridge 126:abea610beb85 5152 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
AnnaBridge 126:abea610beb85 5153 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
AnnaBridge 126:abea610beb85 5154 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
AnnaBridge 126:abea610beb85 5155 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
AnnaBridge 126:abea610beb85 5156 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
AnnaBridge 126:abea610beb85 5157 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
AnnaBridge 126:abea610beb85 5158 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
AnnaBridge 126:abea610beb85 5159 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
AnnaBridge 126:abea610beb85 5160 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
AnnaBridge 126:abea610beb85 5161 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
AnnaBridge 126:abea610beb85 5162 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
AnnaBridge 126:abea610beb85 5163 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
AnnaBridge 126:abea610beb85 5164 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
AnnaBridge 126:abea610beb85 5165 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
AnnaBridge 126:abea610beb85 5166 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
AnnaBridge 126:abea610beb85 5167 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
AnnaBridge 126:abea610beb85 5168 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
AnnaBridge 126:abea610beb85 5169
AnnaBridge 126:abea610beb85 5170 /****************** Bits definition for GPIO_PUPDR register *****************/
AnnaBridge 126:abea610beb85 5171 #define GPIO_PUPDR_PUPDR0 0x00000003U
AnnaBridge 126:abea610beb85 5172 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
AnnaBridge 126:abea610beb85 5173 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
AnnaBridge 126:abea610beb85 5174 #define GPIO_PUPDR_PUPDR1 0x0000000CU
AnnaBridge 126:abea610beb85 5175 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
AnnaBridge 126:abea610beb85 5176 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
AnnaBridge 126:abea610beb85 5177 #define GPIO_PUPDR_PUPDR2 0x00000030U
AnnaBridge 126:abea610beb85 5178 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
AnnaBridge 126:abea610beb85 5179 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
AnnaBridge 126:abea610beb85 5180 #define GPIO_PUPDR_PUPDR3 0x000000C0U
AnnaBridge 126:abea610beb85 5181 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
AnnaBridge 126:abea610beb85 5182 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
AnnaBridge 126:abea610beb85 5183 #define GPIO_PUPDR_PUPDR4 0x00000300U
AnnaBridge 126:abea610beb85 5184 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
AnnaBridge 126:abea610beb85 5185 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
AnnaBridge 126:abea610beb85 5186 #define GPIO_PUPDR_PUPDR5 0x00000C00U
AnnaBridge 126:abea610beb85 5187 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
AnnaBridge 126:abea610beb85 5188 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
AnnaBridge 126:abea610beb85 5189 #define GPIO_PUPDR_PUPDR6 0x00003000U
AnnaBridge 126:abea610beb85 5190 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
AnnaBridge 126:abea610beb85 5191 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
AnnaBridge 126:abea610beb85 5192 #define GPIO_PUPDR_PUPDR7 0x0000C000U
AnnaBridge 126:abea610beb85 5193 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
AnnaBridge 126:abea610beb85 5194 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
AnnaBridge 126:abea610beb85 5195 #define GPIO_PUPDR_PUPDR8 0x00030000U
AnnaBridge 126:abea610beb85 5196 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
AnnaBridge 126:abea610beb85 5197 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
AnnaBridge 126:abea610beb85 5198 #define GPIO_PUPDR_PUPDR9 0x000C0000U
AnnaBridge 126:abea610beb85 5199 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
AnnaBridge 126:abea610beb85 5200 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
AnnaBridge 126:abea610beb85 5201 #define GPIO_PUPDR_PUPDR10 0x00300000U
AnnaBridge 126:abea610beb85 5202 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
AnnaBridge 126:abea610beb85 5203 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
AnnaBridge 126:abea610beb85 5204 #define GPIO_PUPDR_PUPDR11 0x00C00000U
AnnaBridge 126:abea610beb85 5205 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
AnnaBridge 126:abea610beb85 5206 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
AnnaBridge 126:abea610beb85 5207 #define GPIO_PUPDR_PUPDR12 0x03000000U
AnnaBridge 126:abea610beb85 5208 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
AnnaBridge 126:abea610beb85 5209 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
AnnaBridge 126:abea610beb85 5210 #define GPIO_PUPDR_PUPDR13 0x0C000000U
AnnaBridge 126:abea610beb85 5211 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
AnnaBridge 126:abea610beb85 5212 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
AnnaBridge 126:abea610beb85 5213 #define GPIO_PUPDR_PUPDR14 0x30000000U
AnnaBridge 126:abea610beb85 5214 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
AnnaBridge 126:abea610beb85 5215 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
AnnaBridge 126:abea610beb85 5216 #define GPIO_PUPDR_PUPDR15 0xC0000000U
AnnaBridge 126:abea610beb85 5217 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
AnnaBridge 126:abea610beb85 5218 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
AnnaBridge 126:abea610beb85 5219
AnnaBridge 126:abea610beb85 5220 /****************** Bits definition for GPIO_IDR register *******************/
AnnaBridge 126:abea610beb85 5221 #define GPIO_IDR_IDR_0 0x00000001U
AnnaBridge 126:abea610beb85 5222 #define GPIO_IDR_IDR_1 0x00000002U
AnnaBridge 126:abea610beb85 5223 #define GPIO_IDR_IDR_2 0x00000004U
AnnaBridge 126:abea610beb85 5224 #define GPIO_IDR_IDR_3 0x00000008U
AnnaBridge 126:abea610beb85 5225 #define GPIO_IDR_IDR_4 0x00000010U
AnnaBridge 126:abea610beb85 5226 #define GPIO_IDR_IDR_5 0x00000020U
AnnaBridge 126:abea610beb85 5227 #define GPIO_IDR_IDR_6 0x00000040U
AnnaBridge 126:abea610beb85 5228 #define GPIO_IDR_IDR_7 0x00000080U
AnnaBridge 126:abea610beb85 5229 #define GPIO_IDR_IDR_8 0x00000100U
AnnaBridge 126:abea610beb85 5230 #define GPIO_IDR_IDR_9 0x00000200U
AnnaBridge 126:abea610beb85 5231 #define GPIO_IDR_IDR_10 0x00000400U
AnnaBridge 126:abea610beb85 5232 #define GPIO_IDR_IDR_11 0x00000800U
AnnaBridge 126:abea610beb85 5233 #define GPIO_IDR_IDR_12 0x00001000U
AnnaBridge 126:abea610beb85 5234 #define GPIO_IDR_IDR_13 0x00002000U
AnnaBridge 126:abea610beb85 5235 #define GPIO_IDR_IDR_14 0x00004000U
AnnaBridge 126:abea610beb85 5236 #define GPIO_IDR_IDR_15 0x00008000U
AnnaBridge 126:abea610beb85 5237
AnnaBridge 126:abea610beb85 5238 /****************** Bits definition for GPIO_ODR register *******************/
AnnaBridge 126:abea610beb85 5239 #define GPIO_ODR_ODR_0 0x00000001U
AnnaBridge 126:abea610beb85 5240 #define GPIO_ODR_ODR_1 0x00000002U
AnnaBridge 126:abea610beb85 5241 #define GPIO_ODR_ODR_2 0x00000004U
AnnaBridge 126:abea610beb85 5242 #define GPIO_ODR_ODR_3 0x00000008U
AnnaBridge 126:abea610beb85 5243 #define GPIO_ODR_ODR_4 0x00000010U
AnnaBridge 126:abea610beb85 5244 #define GPIO_ODR_ODR_5 0x00000020U
AnnaBridge 126:abea610beb85 5245 #define GPIO_ODR_ODR_6 0x00000040U
AnnaBridge 126:abea610beb85 5246 #define GPIO_ODR_ODR_7 0x00000080U
AnnaBridge 126:abea610beb85 5247 #define GPIO_ODR_ODR_8 0x00000100U
AnnaBridge 126:abea610beb85 5248 #define GPIO_ODR_ODR_9 0x00000200U
AnnaBridge 126:abea610beb85 5249 #define GPIO_ODR_ODR_10 0x00000400U
AnnaBridge 126:abea610beb85 5250 #define GPIO_ODR_ODR_11 0x00000800U
AnnaBridge 126:abea610beb85 5251 #define GPIO_ODR_ODR_12 0x00001000U
AnnaBridge 126:abea610beb85 5252 #define GPIO_ODR_ODR_13 0x00002000U
AnnaBridge 126:abea610beb85 5253 #define GPIO_ODR_ODR_14 0x00004000U
AnnaBridge 126:abea610beb85 5254 #define GPIO_ODR_ODR_15 0x00008000U
AnnaBridge 126:abea610beb85 5255
AnnaBridge 126:abea610beb85 5256 /****************** Bits definition for GPIO_BSRR register ******************/
AnnaBridge 126:abea610beb85 5257 #define GPIO_BSRR_BS_0 0x00000001U
AnnaBridge 126:abea610beb85 5258 #define GPIO_BSRR_BS_1 0x00000002U
AnnaBridge 126:abea610beb85 5259 #define GPIO_BSRR_BS_2 0x00000004U
AnnaBridge 126:abea610beb85 5260 #define GPIO_BSRR_BS_3 0x00000008U
AnnaBridge 126:abea610beb85 5261 #define GPIO_BSRR_BS_4 0x00000010U
AnnaBridge 126:abea610beb85 5262 #define GPIO_BSRR_BS_5 0x00000020U
AnnaBridge 126:abea610beb85 5263 #define GPIO_BSRR_BS_6 0x00000040U
AnnaBridge 126:abea610beb85 5264 #define GPIO_BSRR_BS_7 0x00000080U
AnnaBridge 126:abea610beb85 5265 #define GPIO_BSRR_BS_8 0x00000100U
AnnaBridge 126:abea610beb85 5266 #define GPIO_BSRR_BS_9 0x00000200U
AnnaBridge 126:abea610beb85 5267 #define GPIO_BSRR_BS_10 0x00000400U
AnnaBridge 126:abea610beb85 5268 #define GPIO_BSRR_BS_11 0x00000800U
AnnaBridge 126:abea610beb85 5269 #define GPIO_BSRR_BS_12 0x00001000U
AnnaBridge 126:abea610beb85 5270 #define GPIO_BSRR_BS_13 0x00002000U
AnnaBridge 126:abea610beb85 5271 #define GPIO_BSRR_BS_14 0x00004000U
AnnaBridge 126:abea610beb85 5272 #define GPIO_BSRR_BS_15 0x00008000U
AnnaBridge 126:abea610beb85 5273 #define GPIO_BSRR_BR_0 0x00010000U
AnnaBridge 126:abea610beb85 5274 #define GPIO_BSRR_BR_1 0x00020000U
AnnaBridge 126:abea610beb85 5275 #define GPIO_BSRR_BR_2 0x00040000U
AnnaBridge 126:abea610beb85 5276 #define GPIO_BSRR_BR_3 0x00080000U
AnnaBridge 126:abea610beb85 5277 #define GPIO_BSRR_BR_4 0x00100000U
AnnaBridge 126:abea610beb85 5278 #define GPIO_BSRR_BR_5 0x00200000U
AnnaBridge 126:abea610beb85 5279 #define GPIO_BSRR_BR_6 0x00400000U
AnnaBridge 126:abea610beb85 5280 #define GPIO_BSRR_BR_7 0x00800000U
AnnaBridge 126:abea610beb85 5281 #define GPIO_BSRR_BR_8 0x01000000U
AnnaBridge 126:abea610beb85 5282 #define GPIO_BSRR_BR_9 0x02000000U
AnnaBridge 126:abea610beb85 5283 #define GPIO_BSRR_BR_10 0x04000000U
AnnaBridge 126:abea610beb85 5284 #define GPIO_BSRR_BR_11 0x08000000U
AnnaBridge 126:abea610beb85 5285 #define GPIO_BSRR_BR_12 0x10000000U
AnnaBridge 126:abea610beb85 5286 #define GPIO_BSRR_BR_13 0x20000000U
AnnaBridge 126:abea610beb85 5287 #define GPIO_BSRR_BR_14 0x40000000U
AnnaBridge 126:abea610beb85 5288 #define GPIO_BSRR_BR_15 0x80000000U
AnnaBridge 126:abea610beb85 5289
AnnaBridge 126:abea610beb85 5290 /****************** Bit definition for GPIO_LCKR register *********************/
AnnaBridge 126:abea610beb85 5291 #define GPIO_LCKR_LCK0 0x00000001U
AnnaBridge 126:abea610beb85 5292 #define GPIO_LCKR_LCK1 0x00000002U
AnnaBridge 126:abea610beb85 5293 #define GPIO_LCKR_LCK2 0x00000004U
AnnaBridge 126:abea610beb85 5294 #define GPIO_LCKR_LCK3 0x00000008U
AnnaBridge 126:abea610beb85 5295 #define GPIO_LCKR_LCK4 0x00000010U
AnnaBridge 126:abea610beb85 5296 #define GPIO_LCKR_LCK5 0x00000020U
AnnaBridge 126:abea610beb85 5297 #define GPIO_LCKR_LCK6 0x00000040U
AnnaBridge 126:abea610beb85 5298 #define GPIO_LCKR_LCK7 0x00000080U
AnnaBridge 126:abea610beb85 5299 #define GPIO_LCKR_LCK8 0x00000100U
AnnaBridge 126:abea610beb85 5300 #define GPIO_LCKR_LCK9 0x00000200U
AnnaBridge 126:abea610beb85 5301 #define GPIO_LCKR_LCK10 0x00000400U
AnnaBridge 126:abea610beb85 5302 #define GPIO_LCKR_LCK11 0x00000800U
AnnaBridge 126:abea610beb85 5303 #define GPIO_LCKR_LCK12 0x00001000U
AnnaBridge 126:abea610beb85 5304 #define GPIO_LCKR_LCK13 0x00002000U
AnnaBridge 126:abea610beb85 5305 #define GPIO_LCKR_LCK14 0x00004000U
AnnaBridge 126:abea610beb85 5306 #define GPIO_LCKR_LCK15 0x00008000U
AnnaBridge 126:abea610beb85 5307 #define GPIO_LCKR_LCKK 0x00010000U
AnnaBridge 126:abea610beb85 5308
AnnaBridge 126:abea610beb85 5309
AnnaBridge 126:abea610beb85 5310 /******************************************************************************/
AnnaBridge 126:abea610beb85 5311 /* */
AnnaBridge 126:abea610beb85 5312 /* Inter-integrated Circuit Interface (I2C) */
AnnaBridge 126:abea610beb85 5313 /* */
AnnaBridge 126:abea610beb85 5314 /******************************************************************************/
AnnaBridge 126:abea610beb85 5315 /******************* Bit definition for I2C_CR1 register *******************/
AnnaBridge 126:abea610beb85 5316 #define I2C_CR1_PE 0x00000001U /*!< Peripheral enable */
AnnaBridge 126:abea610beb85 5317 #define I2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
AnnaBridge 126:abea610beb85 5318 #define I2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
AnnaBridge 126:abea610beb85 5319 #define I2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
AnnaBridge 126:abea610beb85 5320 #define I2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
AnnaBridge 126:abea610beb85 5321 #define I2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
AnnaBridge 126:abea610beb85 5322 #define I2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
AnnaBridge 126:abea610beb85 5323 #define I2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
AnnaBridge 126:abea610beb85 5324 #define I2C_CR1_DNF 0x00000F00U /*!< Digital noise filter */
AnnaBridge 126:abea610beb85 5325 #define I2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
AnnaBridge 126:abea610beb85 5326 #define I2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
AnnaBridge 126:abea610beb85 5327 #define I2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
AnnaBridge 126:abea610beb85 5328 #define I2C_CR1_SBC 0x00010000U /*!< Slave byte control */
AnnaBridge 126:abea610beb85 5329 #define I2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
AnnaBridge 126:abea610beb85 5330 #define I2C_CR1_GCEN 0x00080000U /*!< General call enable */
AnnaBridge 126:abea610beb85 5331 #define I2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
AnnaBridge 126:abea610beb85 5332 #define I2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
AnnaBridge 126:abea610beb85 5333 #define I2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
AnnaBridge 126:abea610beb85 5334 #define I2C_CR1_PECEN 0x00800000U /*!< PEC enable */
AnnaBridge 126:abea610beb85 5335
AnnaBridge 126:abea610beb85 5336
AnnaBridge 126:abea610beb85 5337 /****************** Bit definition for I2C_CR2 register ********************/
AnnaBridge 126:abea610beb85 5338 #define I2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
AnnaBridge 126:abea610beb85 5339 #define I2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
AnnaBridge 126:abea610beb85 5340 #define I2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
AnnaBridge 126:abea610beb85 5341 #define I2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
AnnaBridge 126:abea610beb85 5342 #define I2C_CR2_START 0x00002000U /*!< START generation */
AnnaBridge 126:abea610beb85 5343 #define I2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
AnnaBridge 126:abea610beb85 5344 #define I2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
AnnaBridge 126:abea610beb85 5345 #define I2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
AnnaBridge 126:abea610beb85 5346 #define I2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
AnnaBridge 126:abea610beb85 5347 #define I2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
AnnaBridge 126:abea610beb85 5348 #define I2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
AnnaBridge 126:abea610beb85 5349
AnnaBridge 126:abea610beb85 5350 /******************* Bit definition for I2C_OAR1 register ******************/
AnnaBridge 126:abea610beb85 5351 #define I2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
AnnaBridge 126:abea610beb85 5352 #define I2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
AnnaBridge 126:abea610beb85 5353 #define I2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
AnnaBridge 126:abea610beb85 5354
AnnaBridge 126:abea610beb85 5355 /******************* Bit definition for I2C_OAR2 register ******************/
AnnaBridge 126:abea610beb85 5356 #define I2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
AnnaBridge 126:abea610beb85 5357 #define I2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
AnnaBridge 126:abea610beb85 5358 #define I2C_OAR2_OA2NOMASK 0x00000000U /*!< No mask */
AnnaBridge 126:abea610beb85 5359 #define I2C_OAR2_OA2MASK01 0x00000100U /*!< OA2[1] is masked, Only OA2[7:2] are compared */
AnnaBridge 126:abea610beb85 5360 #define I2C_OAR2_OA2MASK02 0x00000200U /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
AnnaBridge 126:abea610beb85 5361 #define I2C_OAR2_OA2MASK03 0x00000300U /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
AnnaBridge 126:abea610beb85 5362 #define I2C_OAR2_OA2MASK04 0x00000400U /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
AnnaBridge 126:abea610beb85 5363 #define I2C_OAR2_OA2MASK05 0x00000500U /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
AnnaBridge 126:abea610beb85 5364 #define I2C_OAR2_OA2MASK06 0x00000600U /*!< OA2[6:1] is masked, Only OA2[7] are compared */
AnnaBridge 126:abea610beb85 5365 #define I2C_OAR2_OA2MASK07 0x00000700U /*!< OA2[7:1] is masked, No comparison is done */
AnnaBridge 126:abea610beb85 5366 #define I2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
AnnaBridge 126:abea610beb85 5367
AnnaBridge 126:abea610beb85 5368 /******************* Bit definition for I2C_TIMINGR register *******************/
AnnaBridge 126:abea610beb85 5369 #define I2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
AnnaBridge 126:abea610beb85 5370 #define I2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
AnnaBridge 126:abea610beb85 5371 #define I2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
AnnaBridge 126:abea610beb85 5372 #define I2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
AnnaBridge 126:abea610beb85 5373 #define I2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
AnnaBridge 126:abea610beb85 5374
AnnaBridge 126:abea610beb85 5375 /******************* Bit definition for I2C_TIMEOUTR register *******************/
AnnaBridge 126:abea610beb85 5376 #define I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
AnnaBridge 126:abea610beb85 5377 #define I2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
AnnaBridge 126:abea610beb85 5378 #define I2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
AnnaBridge 126:abea610beb85 5379 #define I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
AnnaBridge 126:abea610beb85 5380 #define I2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
AnnaBridge 126:abea610beb85 5381
AnnaBridge 126:abea610beb85 5382 /****************** Bit definition for I2C_ISR register *********************/
AnnaBridge 126:abea610beb85 5383 #define I2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
AnnaBridge 126:abea610beb85 5384 #define I2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
AnnaBridge 126:abea610beb85 5385 #define I2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
AnnaBridge 126:abea610beb85 5386 #define I2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
AnnaBridge 126:abea610beb85 5387 #define I2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
AnnaBridge 126:abea610beb85 5388 #define I2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
AnnaBridge 126:abea610beb85 5389 #define I2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
AnnaBridge 126:abea610beb85 5390 #define I2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
AnnaBridge 126:abea610beb85 5391 #define I2C_ISR_BERR 0x00000100U /*!< Bus error */
AnnaBridge 126:abea610beb85 5392 #define I2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
AnnaBridge 126:abea610beb85 5393 #define I2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
AnnaBridge 126:abea610beb85 5394 #define I2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
AnnaBridge 126:abea610beb85 5395 #define I2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
AnnaBridge 126:abea610beb85 5396 #define I2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
AnnaBridge 126:abea610beb85 5397 #define I2C_ISR_BUSY 0x00008000U /*!< Bus busy */
AnnaBridge 126:abea610beb85 5398 #define I2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
AnnaBridge 126:abea610beb85 5399 #define I2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
AnnaBridge 126:abea610beb85 5400
AnnaBridge 126:abea610beb85 5401 /****************** Bit definition for I2C_ICR register *********************/
AnnaBridge 126:abea610beb85 5402 #define I2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
AnnaBridge 126:abea610beb85 5403 #define I2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
AnnaBridge 126:abea610beb85 5404 #define I2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
AnnaBridge 126:abea610beb85 5405 #define I2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
AnnaBridge 126:abea610beb85 5406 #define I2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
AnnaBridge 126:abea610beb85 5407 #define I2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
AnnaBridge 126:abea610beb85 5408 #define I2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
AnnaBridge 126:abea610beb85 5409 #define I2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
AnnaBridge 126:abea610beb85 5410 #define I2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
AnnaBridge 126:abea610beb85 5411
AnnaBridge 126:abea610beb85 5412 /****************** Bit definition for I2C_PECR register *********************/
AnnaBridge 126:abea610beb85 5413 #define I2C_PECR_PEC 0x000000FFU /*!< PEC register */
AnnaBridge 126:abea610beb85 5414
AnnaBridge 126:abea610beb85 5415 /****************** Bit definition for I2C_RXDR register *********************/
AnnaBridge 126:abea610beb85 5416 #define I2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
AnnaBridge 126:abea610beb85 5417
AnnaBridge 126:abea610beb85 5418 /****************** Bit definition for I2C_TXDR register *********************/
AnnaBridge 126:abea610beb85 5419 #define I2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
AnnaBridge 126:abea610beb85 5420
AnnaBridge 126:abea610beb85 5421
AnnaBridge 126:abea610beb85 5422 /******************************************************************************/
AnnaBridge 126:abea610beb85 5423 /* */
AnnaBridge 126:abea610beb85 5424 /* Independent WATCHDOG */
AnnaBridge 126:abea610beb85 5425 /* */
AnnaBridge 126:abea610beb85 5426 /******************************************************************************/
AnnaBridge 126:abea610beb85 5427 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 126:abea610beb85 5428 #define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
AnnaBridge 126:abea610beb85 5429
AnnaBridge 126:abea610beb85 5430 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 126:abea610beb85 5431 #define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
AnnaBridge 126:abea610beb85 5432 #define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 5433 #define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 5434 #define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 5435
AnnaBridge 126:abea610beb85 5436 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 126:abea610beb85 5437 #define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
AnnaBridge 126:abea610beb85 5438
AnnaBridge 126:abea610beb85 5439 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 126:abea610beb85 5440 #define IWDG_SR_PVU 0x01U /*!< Watchdog prescaler value update */
AnnaBridge 126:abea610beb85 5441 #define IWDG_SR_RVU 0x02U /*!< Watchdog counter reload value update */
AnnaBridge 126:abea610beb85 5442 #define IWDG_SR_WVU 0x04U /*!< Watchdog counter window value update */
AnnaBridge 126:abea610beb85 5443
AnnaBridge 126:abea610beb85 5444 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 126:abea610beb85 5445 #define IWDG_WINR_WIN 0x0FFFU /*!< Watchdog counter window value */
AnnaBridge 126:abea610beb85 5446
AnnaBridge 126:abea610beb85 5447 /******************************************************************************/
AnnaBridge 126:abea610beb85 5448 /* */
AnnaBridge 126:abea610beb85 5449 /* LCD-TFT Display Controller (LTDC) */
AnnaBridge 126:abea610beb85 5450 /* */
AnnaBridge 126:abea610beb85 5451 /******************************************************************************/
AnnaBridge 126:abea610beb85 5452
AnnaBridge 126:abea610beb85 5453 /******************** Bit definition for LTDC_SSCR register *****************/
AnnaBridge 126:abea610beb85 5454
AnnaBridge 126:abea610beb85 5455 #define LTDC_SSCR_VSH 0x000007FFU /*!< Vertical Synchronization Height */
AnnaBridge 126:abea610beb85 5456 #define LTDC_SSCR_HSW 0x0FFF0000U /*!< Horizontal Synchronization Width */
AnnaBridge 126:abea610beb85 5457
AnnaBridge 126:abea610beb85 5458 /******************** Bit definition for LTDC_BPCR register *****************/
AnnaBridge 126:abea610beb85 5459
AnnaBridge 126:abea610beb85 5460 #define LTDC_BPCR_AVBP 0x000007FFU /*!< Accumulated Vertical Back Porch */
AnnaBridge 126:abea610beb85 5461 #define LTDC_BPCR_AHBP 0x0FFF0000U /*!< Accumulated Horizontal Back Porch */
AnnaBridge 126:abea610beb85 5462
AnnaBridge 126:abea610beb85 5463 /******************** Bit definition for LTDC_AWCR register *****************/
AnnaBridge 126:abea610beb85 5464
AnnaBridge 126:abea610beb85 5465 #define LTDC_AWCR_AAH 0x000007FFU /*!< Accumulated Active heigh */
AnnaBridge 126:abea610beb85 5466 #define LTDC_AWCR_AAW 0x0FFF0000U /*!< Accumulated Active Width */
AnnaBridge 126:abea610beb85 5467
AnnaBridge 126:abea610beb85 5468 /******************** Bit definition for LTDC_TWCR register *****************/
AnnaBridge 126:abea610beb85 5469
AnnaBridge 126:abea610beb85 5470 #define LTDC_TWCR_TOTALH 0x000007FFU /*!< Total Heigh */
AnnaBridge 126:abea610beb85 5471 #define LTDC_TWCR_TOTALW 0x0FFF0000U /*!< Total Width */
AnnaBridge 126:abea610beb85 5472
AnnaBridge 126:abea610beb85 5473 /******************** Bit definition for LTDC_GCR register ******************/
AnnaBridge 126:abea610beb85 5474
AnnaBridge 126:abea610beb85 5475 #define LTDC_GCR_LTDCEN 0x00000001U /*!< LCD-TFT controller enable bit */
AnnaBridge 126:abea610beb85 5476 #define LTDC_GCR_DBW 0x00000070U /*!< Dither Blue Width */
AnnaBridge 126:abea610beb85 5477 #define LTDC_GCR_DGW 0x00000700U /*!< Dither Green Width */
AnnaBridge 126:abea610beb85 5478 #define LTDC_GCR_DRW 0x00007000U /*!< Dither Red Width */
AnnaBridge 126:abea610beb85 5479 #define LTDC_GCR_DEN 0x00010000U /*!< Dither Enable */
AnnaBridge 126:abea610beb85 5480 #define LTDC_GCR_PCPOL 0x10000000U /*!< Pixel Clock Polarity */
AnnaBridge 126:abea610beb85 5481 #define LTDC_GCR_DEPOL 0x20000000U /*!< Data Enable Polarity */
AnnaBridge 126:abea610beb85 5482 #define LTDC_GCR_VSPOL 0x40000000U /*!< Vertical Synchronization Polarity */
AnnaBridge 126:abea610beb85 5483 #define LTDC_GCR_HSPOL 0x80000000U /*!< Horizontal Synchronization Polarity */
AnnaBridge 126:abea610beb85 5484
AnnaBridge 126:abea610beb85 5485
AnnaBridge 126:abea610beb85 5486 /******************** Bit definition for LTDC_SRCR register *****************/
AnnaBridge 126:abea610beb85 5487
AnnaBridge 126:abea610beb85 5488 #define LTDC_SRCR_IMR 0x00000001U /*!< Immediate Reload */
AnnaBridge 126:abea610beb85 5489 #define LTDC_SRCR_VBR 0x00000002U /*!< Vertical Blanking Reload */
AnnaBridge 126:abea610beb85 5490
AnnaBridge 126:abea610beb85 5491 /******************** Bit definition for LTDC_BCCR register *****************/
AnnaBridge 126:abea610beb85 5492
AnnaBridge 126:abea610beb85 5493 #define LTDC_BCCR_BCBLUE 0x000000FFU /*!< Background Blue value */
AnnaBridge 126:abea610beb85 5494 #define LTDC_BCCR_BCGREEN 0x0000FF00U /*!< Background Green value */
AnnaBridge 126:abea610beb85 5495 #define LTDC_BCCR_BCRED 0x00FF0000U /*!< Background Red value */
AnnaBridge 126:abea610beb85 5496
AnnaBridge 126:abea610beb85 5497 /******************** Bit definition for LTDC_IER register ******************/
AnnaBridge 126:abea610beb85 5498
AnnaBridge 126:abea610beb85 5499 #define LTDC_IER_LIE 0x00000001U /*!< Line Interrupt Enable */
AnnaBridge 126:abea610beb85 5500 #define LTDC_IER_FUIE 0x00000002U /*!< FIFO Underrun Interrupt Enable */
AnnaBridge 126:abea610beb85 5501 #define LTDC_IER_TERRIE 0x00000004U /*!< Transfer Error Interrupt Enable */
AnnaBridge 126:abea610beb85 5502 #define LTDC_IER_RRIE 0x00000008U /*!< Register Reload interrupt enable */
AnnaBridge 126:abea610beb85 5503
AnnaBridge 126:abea610beb85 5504 /******************** Bit definition for LTDC_ISR register ******************/
AnnaBridge 126:abea610beb85 5505
AnnaBridge 126:abea610beb85 5506 #define LTDC_ISR_LIF 0x00000001U /*!< Line Interrupt Flag */
AnnaBridge 126:abea610beb85 5507 #define LTDC_ISR_FUIF 0x00000002U /*!< FIFO Underrun Interrupt Flag */
AnnaBridge 126:abea610beb85 5508 #define LTDC_ISR_TERRIF 0x00000004U /*!< Transfer Error Interrupt Flag */
AnnaBridge 126:abea610beb85 5509 #define LTDC_ISR_RRIF 0x00000008U /*!< Register Reload interrupt Flag */
AnnaBridge 126:abea610beb85 5510
AnnaBridge 126:abea610beb85 5511 /******************** Bit definition for LTDC_ICR register ******************/
AnnaBridge 126:abea610beb85 5512
AnnaBridge 126:abea610beb85 5513 #define LTDC_ICR_CLIF 0x00000001U /*!< Clears the Line Interrupt Flag */
AnnaBridge 126:abea610beb85 5514 #define LTDC_ICR_CFUIF 0x00000002U /*!< Clears the FIFO Underrun Interrupt Flag */
AnnaBridge 126:abea610beb85 5515 #define LTDC_ICR_CTERRIF 0x00000004U /*!< Clears the Transfer Error Interrupt Flag */
AnnaBridge 126:abea610beb85 5516 #define LTDC_ICR_CRRIF 0x00000008U /*!< Clears Register Reload interrupt Flag */
AnnaBridge 126:abea610beb85 5517
AnnaBridge 126:abea610beb85 5518 /******************** Bit definition for LTDC_LIPCR register ****************/
AnnaBridge 126:abea610beb85 5519
AnnaBridge 126:abea610beb85 5520 #define LTDC_LIPCR_LIPOS 0x000007FFU /*!< Line Interrupt Position */
AnnaBridge 126:abea610beb85 5521
AnnaBridge 126:abea610beb85 5522 /******************** Bit definition for LTDC_CPSR register *****************/
AnnaBridge 126:abea610beb85 5523
AnnaBridge 126:abea610beb85 5524 #define LTDC_CPSR_CYPOS 0x0000FFFFU /*!< Current Y Position */
AnnaBridge 126:abea610beb85 5525 #define LTDC_CPSR_CXPOS 0xFFFF0000U /*!< Current X Position */
AnnaBridge 126:abea610beb85 5526
AnnaBridge 126:abea610beb85 5527 /******************** Bit definition for LTDC_CDSR register *****************/
AnnaBridge 126:abea610beb85 5528
AnnaBridge 126:abea610beb85 5529 #define LTDC_CDSR_VDES 0x00000001U /*!< Vertical Data Enable Status */
AnnaBridge 126:abea610beb85 5530 #define LTDC_CDSR_HDES 0x00000002U /*!< Horizontal Data Enable Status */
AnnaBridge 126:abea610beb85 5531 #define LTDC_CDSR_VSYNCS 0x00000004U /*!< Vertical Synchronization Status */
AnnaBridge 126:abea610beb85 5532 #define LTDC_CDSR_HSYNCS 0x00000008U /*!< Horizontal Synchronization Status */
AnnaBridge 126:abea610beb85 5533
AnnaBridge 126:abea610beb85 5534 /******************** Bit definition for LTDC_LxCR register *****************/
AnnaBridge 126:abea610beb85 5535
AnnaBridge 126:abea610beb85 5536 #define LTDC_LxCR_LEN 0x00000001U /*!< Layer Enable */
AnnaBridge 126:abea610beb85 5537 #define LTDC_LxCR_COLKEN 0x00000002U /*!< Color Keying Enable */
AnnaBridge 126:abea610beb85 5538 #define LTDC_LxCR_CLUTEN 0x00000010U /*!< Color Lockup Table Enable */
AnnaBridge 126:abea610beb85 5539
AnnaBridge 126:abea610beb85 5540 /******************** Bit definition for LTDC_LxWHPCR register **************/
AnnaBridge 126:abea610beb85 5541
AnnaBridge 126:abea610beb85 5542 #define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU /*!< Window Horizontal Start Position */
AnnaBridge 126:abea610beb85 5543 #define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U /*!< Window Horizontal Stop Position */
AnnaBridge 126:abea610beb85 5544
AnnaBridge 126:abea610beb85 5545 /******************** Bit definition for LTDC_LxWVPCR register **************/
AnnaBridge 126:abea610beb85 5546
AnnaBridge 126:abea610beb85 5547 #define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU /*!< Window Vertical Start Position */
AnnaBridge 126:abea610beb85 5548 #define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U /*!< Window Vertical Stop Position */
AnnaBridge 126:abea610beb85 5549
AnnaBridge 126:abea610beb85 5550 /******************** Bit definition for LTDC_LxCKCR register ***************/
AnnaBridge 126:abea610beb85 5551
AnnaBridge 126:abea610beb85 5552 #define LTDC_LxCKCR_CKBLUE 0x000000FFU /*!< Color Key Blue value */
AnnaBridge 126:abea610beb85 5553 #define LTDC_LxCKCR_CKGREEN 0x0000FF00U /*!< Color Key Green value */
AnnaBridge 126:abea610beb85 5554 #define LTDC_LxCKCR_CKRED 0x00FF0000U /*!< Color Key Red value */
AnnaBridge 126:abea610beb85 5555
AnnaBridge 126:abea610beb85 5556 /******************** Bit definition for LTDC_LxPFCR register ***************/
AnnaBridge 126:abea610beb85 5557
AnnaBridge 126:abea610beb85 5558 #define LTDC_LxPFCR_PF 0x00000007U /*!< Pixel Format */
AnnaBridge 126:abea610beb85 5559
AnnaBridge 126:abea610beb85 5560 /******************** Bit definition for LTDC_LxCACR register ***************/
AnnaBridge 126:abea610beb85 5561
AnnaBridge 126:abea610beb85 5562 #define LTDC_LxCACR_CONSTA 0x000000FFU /*!< Constant Alpha */
AnnaBridge 126:abea610beb85 5563
AnnaBridge 126:abea610beb85 5564 /******************** Bit definition for LTDC_LxDCCR register ***************/
AnnaBridge 126:abea610beb85 5565
AnnaBridge 126:abea610beb85 5566 #define LTDC_LxDCCR_DCBLUE 0x000000FFU /*!< Default Color Blue */
AnnaBridge 126:abea610beb85 5567 #define LTDC_LxDCCR_DCGREEN 0x0000FF00U /*!< Default Color Green */
AnnaBridge 126:abea610beb85 5568 #define LTDC_LxDCCR_DCRED 0x00FF0000U /*!< Default Color Red */
AnnaBridge 126:abea610beb85 5569 #define LTDC_LxDCCR_DCALPHA 0xFF000000U /*!< Default Color Alpha */
AnnaBridge 126:abea610beb85 5570
AnnaBridge 126:abea610beb85 5571 /******************** Bit definition for LTDC_LxBFCR register ***************/
AnnaBridge 126:abea610beb85 5572
AnnaBridge 126:abea610beb85 5573 #define LTDC_LxBFCR_BF2 0x00000007U /*!< Blending Factor 2 */
AnnaBridge 126:abea610beb85 5574 #define LTDC_LxBFCR_BF1 0x00000700U /*!< Blending Factor 1 */
AnnaBridge 126:abea610beb85 5575
AnnaBridge 126:abea610beb85 5576 /******************** Bit definition for LTDC_LxCFBAR register **************/
AnnaBridge 126:abea610beb85 5577
AnnaBridge 126:abea610beb85 5578 #define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU /*!< Color Frame Buffer Start Address */
AnnaBridge 126:abea610beb85 5579
AnnaBridge 126:abea610beb85 5580 /******************** Bit definition for LTDC_LxCFBLR register **************/
AnnaBridge 126:abea610beb85 5581
AnnaBridge 126:abea610beb85 5582 #define LTDC_LxCFBLR_CFBLL 0x00001FFFU /*!< Color Frame Buffer Line Length */
AnnaBridge 126:abea610beb85 5583 #define LTDC_LxCFBLR_CFBP 0x1FFF0000U /*!< Color Frame Buffer Pitch in bytes */
AnnaBridge 126:abea610beb85 5584
AnnaBridge 126:abea610beb85 5585 /******************** Bit definition for LTDC_LxCFBLNR register *************/
AnnaBridge 126:abea610beb85 5586
AnnaBridge 126:abea610beb85 5587 #define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU /*!< Frame Buffer Line Number */
AnnaBridge 126:abea610beb85 5588
AnnaBridge 126:abea610beb85 5589 /******************** Bit definition for LTDC_LxCLUTWR register *************/
AnnaBridge 126:abea610beb85 5590
AnnaBridge 126:abea610beb85 5591 #define LTDC_LxCLUTWR_BLUE 0x000000FFU /*!< Blue value */
AnnaBridge 126:abea610beb85 5592 #define LTDC_LxCLUTWR_GREEN 0x0000FF00U /*!< Green value */
AnnaBridge 126:abea610beb85 5593 #define LTDC_LxCLUTWR_RED 0x00FF0000U /*!< Red value */
AnnaBridge 126:abea610beb85 5594 #define LTDC_LxCLUTWR_CLUTADD 0xFF000000U /*!< CLUT address */
AnnaBridge 126:abea610beb85 5595
AnnaBridge 126:abea610beb85 5596 /******************************************************************************/
AnnaBridge 126:abea610beb85 5597 /* */
AnnaBridge 126:abea610beb85 5598 /* Power Control */
AnnaBridge 126:abea610beb85 5599 /* */
AnnaBridge 126:abea610beb85 5600 /******************************************************************************/
AnnaBridge 126:abea610beb85 5601 /******************** Bit definition for PWR_CR1 register ********************/
AnnaBridge 126:abea610beb85 5602 #define PWR_CR1_LPDS 0x00000001U /*!< Low-Power Deepsleep */
AnnaBridge 126:abea610beb85 5603 #define PWR_CR1_PDDS 0x00000002U /*!< Power Down Deepsleep */
AnnaBridge 126:abea610beb85 5604 #define PWR_CR1_CSBF 0x00000008U /*!< Clear Standby Flag */
AnnaBridge 126:abea610beb85 5605 #define PWR_CR1_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
AnnaBridge 126:abea610beb85 5606 #define PWR_CR1_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
AnnaBridge 126:abea610beb85 5607 #define PWR_CR1_PLS_0 0x00000020U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5608 #define PWR_CR1_PLS_1 0x00000040U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5609 #define PWR_CR1_PLS_2 0x00000080U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 5610
AnnaBridge 126:abea610beb85 5611 /*!< PVD level configuration */
AnnaBridge 126:abea610beb85 5612 #define PWR_CR1_PLS_LEV0 0x00000000U /*!< PVD level 0 */
AnnaBridge 126:abea610beb85 5613 #define PWR_CR1_PLS_LEV1 0x00000020U /*!< PVD level 1 */
AnnaBridge 126:abea610beb85 5614 #define PWR_CR1_PLS_LEV2 0x00000040U /*!< PVD level 2 */
AnnaBridge 126:abea610beb85 5615 #define PWR_CR1_PLS_LEV3 0x00000060U /*!< PVD level 3 */
AnnaBridge 126:abea610beb85 5616 #define PWR_CR1_PLS_LEV4 0x00000080U /*!< PVD level 4 */
AnnaBridge 126:abea610beb85 5617 #define PWR_CR1_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
AnnaBridge 126:abea610beb85 5618 #define PWR_CR1_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
AnnaBridge 126:abea610beb85 5619 #define PWR_CR1_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
AnnaBridge 126:abea610beb85 5620 #define PWR_CR1_DBP 0x00000100U /*!< Disable Backup Domain write protection */
AnnaBridge 126:abea610beb85 5621 #define PWR_CR1_FPDS 0x00000200U /*!< Flash power down in Stop mode */
AnnaBridge 126:abea610beb85 5622 #define PWR_CR1_LPUDS 0x00000400U /*!< Low-power regulator in deepsleep under-drive mode */
AnnaBridge 126:abea610beb85 5623 #define PWR_CR1_MRUDS 0x00000800U /*!< Main regulator in deepsleep under-drive mode */
AnnaBridge 126:abea610beb85 5624 #define PWR_CR1_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 126:abea610beb85 5625 #define PWR_CR1_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
AnnaBridge 126:abea610beb85 5626 #define PWR_CR1_VOS_0 0x00004000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5627 #define PWR_CR1_VOS_1 0x00008000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5628 #define PWR_CR1_ODEN 0x00010000U /*!< Over Drive enable */
AnnaBridge 126:abea610beb85 5629 #define PWR_CR1_ODSWEN 0x00020000U /*!< Over Drive switch enabled */
AnnaBridge 126:abea610beb85 5630 #define PWR_CR1_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */
AnnaBridge 126:abea610beb85 5631 #define PWR_CR1_UDEN_0 0x00040000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5632 #define PWR_CR1_UDEN_1 0x00080000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5633
AnnaBridge 126:abea610beb85 5634 /******************* Bit definition for PWR_CSR1 register ********************/
AnnaBridge 126:abea610beb85 5635 #define PWR_CSR1_WUIF 0x00000001U /*!< Wake up internal Flag */
AnnaBridge 126:abea610beb85 5636 #define PWR_CSR1_SBF 0x00000002U /*!< Standby Flag */
AnnaBridge 126:abea610beb85 5637 #define PWR_CSR1_PVDO 0x00000004U /*!< PVD Output */
AnnaBridge 126:abea610beb85 5638 #define PWR_CSR1_BRR 0x00000008U /*!< Backup regulator ready */
AnnaBridge 126:abea610beb85 5639 #define PWR_CSR1_EIWUP 0x00000100U /*!< Enable internal wakeup */
AnnaBridge 126:abea610beb85 5640 #define PWR_CSR1_BRE 0x00000200U /*!< Backup regulator enable */
AnnaBridge 126:abea610beb85 5641 #define PWR_CSR1_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
AnnaBridge 126:abea610beb85 5642 #define PWR_CSR1_ODRDY 0x00010000U /*!< Over Drive generator ready */
AnnaBridge 126:abea610beb85 5643 #define PWR_CSR1_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */
AnnaBridge 126:abea610beb85 5644 #define PWR_CSR1_UDRDY 0x000C0000U /*!< Under Drive ready */
AnnaBridge 126:abea610beb85 5645
AnnaBridge 126:abea610beb85 5646
AnnaBridge 126:abea610beb85 5647 /******************** Bit definition for PWR_CR2 register ********************/
AnnaBridge 126:abea610beb85 5648 #define PWR_CR2_CWUPF1 0x00000001U /*!< Clear Wakeup Pin Flag for PA0 */
AnnaBridge 126:abea610beb85 5649 #define PWR_CR2_CWUPF2 0x00000002U /*!< Clear Wakeup Pin Flag for PA2 */
AnnaBridge 126:abea610beb85 5650 #define PWR_CR2_CWUPF3 0x00000004U /*!< Clear Wakeup Pin Flag for PC1 */
AnnaBridge 126:abea610beb85 5651 #define PWR_CR2_CWUPF4 0x00000008U /*!< Clear Wakeup Pin Flag for PC13 */
AnnaBridge 126:abea610beb85 5652 #define PWR_CR2_CWUPF5 0x00000010U /*!< Clear Wakeup Pin Flag for PI8 */
AnnaBridge 126:abea610beb85 5653 #define PWR_CR2_CWUPF6 0x00000020U /*!< Clear Wakeup Pin Flag for PI11 */
AnnaBridge 126:abea610beb85 5654 #define PWR_CR2_WUPP1 0x00000100U /*!< Wakeup Pin Polarity bit for PA0 */
AnnaBridge 126:abea610beb85 5655 #define PWR_CR2_WUPP2 0x00000200U /*!< Wakeup Pin Polarity bit for PA2 */
AnnaBridge 126:abea610beb85 5656 #define PWR_CR2_WUPP3 0x00000400U /*!< Wakeup Pin Polarity bit for PC1 */
AnnaBridge 126:abea610beb85 5657 #define PWR_CR2_WUPP4 0x00000800U /*!< Wakeup Pin Polarity bit for PC13 */
AnnaBridge 126:abea610beb85 5658 #define PWR_CR2_WUPP5 0x00001000U /*!< Wakeup Pin Polarity bit for PI8 */
AnnaBridge 126:abea610beb85 5659 #define PWR_CR2_WUPP6 0x00002000U /*!< Wakeup Pin Polarity bit for PI11 */
AnnaBridge 126:abea610beb85 5660
AnnaBridge 126:abea610beb85 5661 /******************* Bit definition for PWR_CSR2 register ********************/
AnnaBridge 126:abea610beb85 5662 #define PWR_CSR2_WUPF1 0x00000001U /*!< Wakeup Pin Flag for PA0 */
AnnaBridge 126:abea610beb85 5663 #define PWR_CSR2_WUPF2 0x00000002U /*!< Wakeup Pin Flag for PA2 */
AnnaBridge 126:abea610beb85 5664 #define PWR_CSR2_WUPF3 0x00000004U /*!< Wakeup Pin Flag for PC1 */
AnnaBridge 126:abea610beb85 5665 #define PWR_CSR2_WUPF4 0x00000008U /*!< Wakeup Pin Flag for PC13 */
AnnaBridge 126:abea610beb85 5666 #define PWR_CSR2_WUPF5 0x00000010U /*!< Wakeup Pin Flag for PI8 */
AnnaBridge 126:abea610beb85 5667 #define PWR_CSR2_WUPF6 0x00000020U /*!< Wakeup Pin Flag for PI11 */
AnnaBridge 126:abea610beb85 5668 #define PWR_CSR2_EWUP1 0x00000100U /*!< Enable Wakeup Pin PA0 */
AnnaBridge 126:abea610beb85 5669 #define PWR_CSR2_EWUP2 0x00000200U /*!< Enable Wakeup Pin PA2 */
AnnaBridge 126:abea610beb85 5670 #define PWR_CSR2_EWUP3 0x00000400U /*!< Enable Wakeup Pin PC1 */
AnnaBridge 126:abea610beb85 5671 #define PWR_CSR2_EWUP4 0x00000800U /*!< Enable Wakeup Pin PC13 */
AnnaBridge 126:abea610beb85 5672 #define PWR_CSR2_EWUP5 0x00001000U /*!< Enable Wakeup Pin PI8 */
AnnaBridge 126:abea610beb85 5673 #define PWR_CSR2_EWUP6 0x00002000U /*!< Enable Wakeup Pin PI11 */
AnnaBridge 126:abea610beb85 5674
AnnaBridge 126:abea610beb85 5675 /******************************************************************************/
AnnaBridge 126:abea610beb85 5676 /* */
AnnaBridge 126:abea610beb85 5677 /* QUADSPI */
AnnaBridge 126:abea610beb85 5678 /* */
AnnaBridge 126:abea610beb85 5679 /******************************************************************************/
AnnaBridge 126:abea610beb85 5680 /***************** Bit definition for QUADSPI_CR register *******************/
AnnaBridge 126:abea610beb85 5681 #define QUADSPI_CR_EN 0x00000001U /*!< Enable */
AnnaBridge 126:abea610beb85 5682 #define QUADSPI_CR_ABORT 0x00000002U /*!< Abort request */
AnnaBridge 126:abea610beb85 5683 #define QUADSPI_CR_DMAEN 0x00000004U /*!< DMA Enable */
AnnaBridge 126:abea610beb85 5684 #define QUADSPI_CR_TCEN 0x00000008U /*!< Timeout Counter Enable */
AnnaBridge 126:abea610beb85 5685 #define QUADSPI_CR_SSHIFT 0x00000010U /*!< Sample Shift */
AnnaBridge 126:abea610beb85 5686 #define QUADSPI_CR_DFM 0x00000040U /*!< Dual Flash Mode */
AnnaBridge 126:abea610beb85 5687 #define QUADSPI_CR_FSEL 0x00000080U /*!< Flash Select */
AnnaBridge 126:abea610beb85 5688 #define QUADSPI_CR_FTHRES 0x00001F00U /*!< FTHRES[4:0] FIFO Level */
AnnaBridge 126:abea610beb85 5689 #define QUADSPI_CR_FTHRES_0 0x00000100U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5690 #define QUADSPI_CR_FTHRES_1 0x00000200U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5691 #define QUADSPI_CR_FTHRES_2 0x00000400U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 5692 #define QUADSPI_CR_FTHRES_3 0x00000800U /*!< Bit 3 */
AnnaBridge 126:abea610beb85 5693 #define QUADSPI_CR_FTHRES_4 0x00001000U /*!< Bit 4 */
AnnaBridge 126:abea610beb85 5694 #define QUADSPI_CR_TEIE 0x00010000U /*!< Transfer Error Interrupt Enable */
AnnaBridge 126:abea610beb85 5695 #define QUADSPI_CR_TCIE 0x00020000U /*!< Transfer Complete Interrupt Enable */
AnnaBridge 126:abea610beb85 5696 #define QUADSPI_CR_FTIE 0x00040000U /*!< FIFO Threshold Interrupt Enable */
AnnaBridge 126:abea610beb85 5697 #define QUADSPI_CR_SMIE 0x00080000U /*!< Status Match Interrupt Enable */
AnnaBridge 126:abea610beb85 5698 #define QUADSPI_CR_TOIE 0x00100000U /*!< TimeOut Interrupt Enable */
AnnaBridge 126:abea610beb85 5699 #define QUADSPI_CR_APMS 0x00400000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5700 #define QUADSPI_CR_PMM 0x00800000U /*!< Polling Match Mode */
AnnaBridge 126:abea610beb85 5701 #define QUADSPI_CR_PRESCALER 0xFF000000U /*!< PRESCALER[7:0] Clock prescaler */
AnnaBridge 126:abea610beb85 5702 #define QUADSPI_CR_PRESCALER_0 0x01000000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5703 #define QUADSPI_CR_PRESCALER_1 0x02000000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5704 #define QUADSPI_CR_PRESCALER_2 0x04000000U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 5705 #define QUADSPI_CR_PRESCALER_3 0x08000000U /*!< Bit 3 */
AnnaBridge 126:abea610beb85 5706 #define QUADSPI_CR_PRESCALER_4 0x10000000U /*!< Bit 4 */
AnnaBridge 126:abea610beb85 5707 #define QUADSPI_CR_PRESCALER_5 0x20000000U /*!< Bit 5 */
AnnaBridge 126:abea610beb85 5708 #define QUADSPI_CR_PRESCALER_6 0x40000000U /*!< Bit 6 */
AnnaBridge 126:abea610beb85 5709 #define QUADSPI_CR_PRESCALER_7 0x80000000U /*!< Bit 7 */
AnnaBridge 126:abea610beb85 5710
AnnaBridge 126:abea610beb85 5711 /***************** Bit definition for QUADSPI_DCR register ******************/
AnnaBridge 126:abea610beb85 5712 #define QUADSPI_DCR_CKMODE 0x00000001U /*!< Mode 0 / Mode 3 */
AnnaBridge 126:abea610beb85 5713 #define QUADSPI_DCR_CSHT 0x00000700U /*!< CSHT[2:0]: ChipSelect High Time */
AnnaBridge 126:abea610beb85 5714 #define QUADSPI_DCR_CSHT_0 0x00000100U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5715 #define QUADSPI_DCR_CSHT_1 0x00000200U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5716 #define QUADSPI_DCR_CSHT_2 0x00000400U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 5717 #define QUADSPI_DCR_FSIZE 0x001F0000U /*!< FSIZE[4:0]: Flash Size */
AnnaBridge 126:abea610beb85 5718 #define QUADSPI_DCR_FSIZE_0 0x00010000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5719 #define QUADSPI_DCR_FSIZE_1 0x00020000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5720 #define QUADSPI_DCR_FSIZE_2 0x00040000U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 5721 #define QUADSPI_DCR_FSIZE_3 0x00080000U /*!< Bit 3 */
AnnaBridge 126:abea610beb85 5722 #define QUADSPI_DCR_FSIZE_4 0x00100000U /*!< Bit 4 */
AnnaBridge 126:abea610beb85 5723
AnnaBridge 126:abea610beb85 5724 /****************** Bit definition for QUADSPI_SR register *******************/
AnnaBridge 126:abea610beb85 5725 #define QUADSPI_SR_TEF 0x00000001U /*!< Transfer Error Flag */
AnnaBridge 126:abea610beb85 5726 #define QUADSPI_SR_TCF 0x00000002U /*!< Transfer Complete Flag */
AnnaBridge 126:abea610beb85 5727 #define QUADSPI_SR_FTF 0x00000004U /*!< FIFO Threshlod Flag */
AnnaBridge 126:abea610beb85 5728 #define QUADSPI_SR_SMF 0x00000008U /*!< Status Match Flag */
AnnaBridge 126:abea610beb85 5729 #define QUADSPI_SR_TOF 0x00000010U /*!< Timeout Flag */
AnnaBridge 126:abea610beb85 5730 #define QUADSPI_SR_BUSY 0x00000020U /*!< Busy */
AnnaBridge 126:abea610beb85 5731 #define QUADSPI_SR_FLEVEL 0x00001F00U /*!< FIFO Threshlod Flag */
AnnaBridge 126:abea610beb85 5732 #define QUADSPI_SR_FLEVEL_0 0x00000100U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5733 #define QUADSPI_SR_FLEVEL_1 0x00000200U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5734 #define QUADSPI_SR_FLEVEL_2 0x00000400U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 5735 #define QUADSPI_SR_FLEVEL_3 0x00000800U /*!< Bit 3 */
AnnaBridge 126:abea610beb85 5736 #define QUADSPI_SR_FLEVEL_4 0x00001000U /*!< Bit 4 */
AnnaBridge 126:abea610beb85 5737
AnnaBridge 126:abea610beb85 5738 /****************** Bit definition for QUADSPI_FCR register ******************/
AnnaBridge 126:abea610beb85 5739 #define QUADSPI_FCR_CTEF 0x00000001U /*!< Clear Transfer Error Flag */
AnnaBridge 126:abea610beb85 5740 #define QUADSPI_FCR_CTCF 0x00000002U /*!< Clear Transfer Complete Flag */
AnnaBridge 126:abea610beb85 5741 #define QUADSPI_FCR_CSMF 0x00000008U /*!< Clear Status Match Flag */
AnnaBridge 126:abea610beb85 5742 #define QUADSPI_FCR_CTOF 0x00000010U /*!< Clear Timeout Flag */
AnnaBridge 126:abea610beb85 5743
AnnaBridge 126:abea610beb85 5744 /****************** Bit definition for QUADSPI_DLR register ******************/
AnnaBridge 126:abea610beb85 5745 #define QUADSPI_DLR_DL 0xFFFFFFFFU /*!< DL[31:0]: Data Length */
AnnaBridge 126:abea610beb85 5746
AnnaBridge 126:abea610beb85 5747 /****************** Bit definition for QUADSPI_CCR register ******************/
AnnaBridge 126:abea610beb85 5748 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU /*!< INSTRUCTION[7:0]: Instruction */
AnnaBridge 126:abea610beb85 5749 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5750 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5751 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 5752 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /*!< Bit 3 */
AnnaBridge 126:abea610beb85 5753 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /*!< Bit 4 */
AnnaBridge 126:abea610beb85 5754 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /*!< Bit 5 */
AnnaBridge 126:abea610beb85 5755 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /*!< Bit 6 */
AnnaBridge 126:abea610beb85 5756 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /*!< Bit 7 */
AnnaBridge 126:abea610beb85 5757 #define QUADSPI_CCR_IMODE 0x00000300U /*!< IMODE[1:0]: Instruction Mode */
AnnaBridge 126:abea610beb85 5758 #define QUADSPI_CCR_IMODE_0 0x00000100U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5759 #define QUADSPI_CCR_IMODE_1 0x00000200U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5760 #define QUADSPI_CCR_ADMODE 0x00000C00U /*!< ADMODE[1:0]: Address Mode */
AnnaBridge 126:abea610beb85 5761 #define QUADSPI_CCR_ADMODE_0 0x00000400U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5762 #define QUADSPI_CCR_ADMODE_1 0x00000800U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5763 #define QUADSPI_CCR_ADSIZE 0x00003000U /*!< ADSIZE[1:0]: Address Size */
AnnaBridge 126:abea610beb85 5764 #define QUADSPI_CCR_ADSIZE_0 0x00001000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5765 #define QUADSPI_CCR_ADSIZE_1 0x00002000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5766 #define QUADSPI_CCR_ABMODE 0x0000C000U /*!< ABMODE[1:0]: Alternate Bytes Mode */
AnnaBridge 126:abea610beb85 5767 #define QUADSPI_CCR_ABMODE_0 0x00004000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5768 #define QUADSPI_CCR_ABMODE_1 0x00008000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5769 #define QUADSPI_CCR_ABSIZE 0x00030000U /*!< ABSIZE[1:0]: Instruction Mode */
AnnaBridge 126:abea610beb85 5770 #define QUADSPI_CCR_ABSIZE_0 0x00010000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5771 #define QUADSPI_CCR_ABSIZE_1 0x00020000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5772 #define QUADSPI_CCR_DCYC 0x007C0000U /*!< DCYC[4:0]: Dummy Cycles */
AnnaBridge 126:abea610beb85 5773 #define QUADSPI_CCR_DCYC_0 0x00040000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5774 #define QUADSPI_CCR_DCYC_1 0x00080000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5775 #define QUADSPI_CCR_DCYC_2 0x00100000U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 5776 #define QUADSPI_CCR_DCYC_3 0x00200000U /*!< Bit 3 */
AnnaBridge 126:abea610beb85 5777 #define QUADSPI_CCR_DCYC_4 0x00400000U /*!< Bit 4 */
AnnaBridge 126:abea610beb85 5778 #define QUADSPI_CCR_DMODE 0x03000000U /*!< DMODE[1:0]: Data Mode */
AnnaBridge 126:abea610beb85 5779 #define QUADSPI_CCR_DMODE_0 0x01000000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5780 #define QUADSPI_CCR_DMODE_1 0x02000000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5781 #define QUADSPI_CCR_FMODE 0x0C000000U /*!< FMODE[1:0]: Functional Mode */
AnnaBridge 126:abea610beb85 5782 #define QUADSPI_CCR_FMODE_0 0x04000000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5783 #define QUADSPI_CCR_FMODE_1 0x08000000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5784 #define QUADSPI_CCR_SIOO 0x10000000U /*!< SIOO: Send Instruction Only Once Mode */
AnnaBridge 126:abea610beb85 5785 #define QUADSPI_CCR_DHHC 0x40000000U /*!< DHHC: Delay Half Hclk Cycle */
AnnaBridge 126:abea610beb85 5786 #define QUADSPI_CCR_DDRM 0x80000000U /*!< DDRM: Double Data Rate Mode */
AnnaBridge 126:abea610beb85 5787 /****************** Bit definition for QUADSPI_AR register *******************/
AnnaBridge 126:abea610beb85 5788 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /*!< ADDRESS[31:0]: Address */
AnnaBridge 126:abea610beb85 5789
AnnaBridge 126:abea610beb85 5790 /****************** Bit definition for QUADSPI_ABR register ******************/
AnnaBridge 126:abea610beb85 5791 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /*!< ALTERNATE[31:0]: Alternate Bytes */
AnnaBridge 126:abea610beb85 5792
AnnaBridge 126:abea610beb85 5793 /****************** Bit definition for QUADSPI_DR register *******************/
AnnaBridge 126:abea610beb85 5794 #define QUADSPI_DR_DATA 0xFFFFFFFFU /*!< DATA[31:0]: Data */
AnnaBridge 126:abea610beb85 5795
AnnaBridge 126:abea610beb85 5796 /****************** Bit definition for QUADSPI_PSMKR register ****************/
AnnaBridge 126:abea610beb85 5797 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /*!< MASK[31:0]: Status Mask */
AnnaBridge 126:abea610beb85 5798
AnnaBridge 126:abea610beb85 5799 /****************** Bit definition for QUADSPI_PSMAR register ****************/
AnnaBridge 126:abea610beb85 5800 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /*!< MATCH[31:0]: Status Match */
AnnaBridge 126:abea610beb85 5801
AnnaBridge 126:abea610beb85 5802 /****************** Bit definition for QUADSPI_PIR register *****************/
AnnaBridge 126:abea610beb85 5803 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU /*!< INTERVAL[15:0]: Polling Interval */
AnnaBridge 126:abea610beb85 5804
AnnaBridge 126:abea610beb85 5805 /****************** Bit definition for QUADSPI_LPTR register *****************/
AnnaBridge 126:abea610beb85 5806 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /*!< TIMEOUT[15:0]: Timeout period */
AnnaBridge 126:abea610beb85 5807
AnnaBridge 126:abea610beb85 5808 /******************************************************************************/
AnnaBridge 126:abea610beb85 5809 /* */
AnnaBridge 126:abea610beb85 5810 /* Reset and Clock Control */
AnnaBridge 126:abea610beb85 5811 /* */
AnnaBridge 126:abea610beb85 5812 /******************************************************************************/
AnnaBridge 126:abea610beb85 5813 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 126:abea610beb85 5814 #define RCC_CR_HSION 0x00000001U
AnnaBridge 126:abea610beb85 5815 #define RCC_CR_HSIRDY 0x00000002U
AnnaBridge 126:abea610beb85 5816 #define RCC_CR_HSITRIM 0x000000F8U
AnnaBridge 126:abea610beb85 5817 #define RCC_CR_HSITRIM_0 0x00000008U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 5818 #define RCC_CR_HSITRIM_1 0x00000010U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 5819 #define RCC_CR_HSITRIM_2 0x00000020U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 5820 #define RCC_CR_HSITRIM_3 0x00000040U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 5821 #define RCC_CR_HSITRIM_4 0x00000080U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 5822 #define RCC_CR_HSICAL 0x0000FF00U
AnnaBridge 126:abea610beb85 5823 #define RCC_CR_HSICAL_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 5824 #define RCC_CR_HSICAL_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 5825 #define RCC_CR_HSICAL_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 5826 #define RCC_CR_HSICAL_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 5827 #define RCC_CR_HSICAL_4 0x00001000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 5828 #define RCC_CR_HSICAL_5 0x00002000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 5829 #define RCC_CR_HSICAL_6 0x00004000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 5830 #define RCC_CR_HSICAL_7 0x00008000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 5831 #define RCC_CR_HSEON 0x00010000U
AnnaBridge 126:abea610beb85 5832 #define RCC_CR_HSERDY 0x00020000U
AnnaBridge 126:abea610beb85 5833 #define RCC_CR_HSEBYP 0x00040000U
AnnaBridge 126:abea610beb85 5834 #define RCC_CR_CSSON 0x00080000U
AnnaBridge 126:abea610beb85 5835 #define RCC_CR_PLLON 0x01000000U
AnnaBridge 126:abea610beb85 5836 #define RCC_CR_PLLRDY 0x02000000U
AnnaBridge 126:abea610beb85 5837 #define RCC_CR_PLLI2SON 0x04000000U
AnnaBridge 126:abea610beb85 5838 #define RCC_CR_PLLI2SRDY 0x08000000U
AnnaBridge 126:abea610beb85 5839 #define RCC_CR_PLLSAION 0x10000000U
AnnaBridge 126:abea610beb85 5840 #define RCC_CR_PLLSAIRDY 0x20000000U
AnnaBridge 126:abea610beb85 5841
AnnaBridge 126:abea610beb85 5842 /******************** Bit definition for RCC_PLLCFGR register ***************/
AnnaBridge 126:abea610beb85 5843 #define RCC_PLLCFGR_PLLM 0x0000003FU
AnnaBridge 126:abea610beb85 5844 #define RCC_PLLCFGR_PLLM_0 0x00000001U
AnnaBridge 126:abea610beb85 5845 #define RCC_PLLCFGR_PLLM_1 0x00000002U
AnnaBridge 126:abea610beb85 5846 #define RCC_PLLCFGR_PLLM_2 0x00000004U
AnnaBridge 126:abea610beb85 5847 #define RCC_PLLCFGR_PLLM_3 0x00000008U
AnnaBridge 126:abea610beb85 5848 #define RCC_PLLCFGR_PLLM_4 0x00000010U
AnnaBridge 126:abea610beb85 5849 #define RCC_PLLCFGR_PLLM_5 0x00000020U
AnnaBridge 126:abea610beb85 5850 #define RCC_PLLCFGR_PLLN 0x00007FC0U
AnnaBridge 126:abea610beb85 5851 #define RCC_PLLCFGR_PLLN_0 0x00000040U
AnnaBridge 126:abea610beb85 5852 #define RCC_PLLCFGR_PLLN_1 0x00000080U
AnnaBridge 126:abea610beb85 5853 #define RCC_PLLCFGR_PLLN_2 0x00000100U
AnnaBridge 126:abea610beb85 5854 #define RCC_PLLCFGR_PLLN_3 0x00000200U
AnnaBridge 126:abea610beb85 5855 #define RCC_PLLCFGR_PLLN_4 0x00000400U
AnnaBridge 126:abea610beb85 5856 #define RCC_PLLCFGR_PLLN_5 0x00000800U
AnnaBridge 126:abea610beb85 5857 #define RCC_PLLCFGR_PLLN_6 0x00001000U
AnnaBridge 126:abea610beb85 5858 #define RCC_PLLCFGR_PLLN_7 0x00002000U
AnnaBridge 126:abea610beb85 5859 #define RCC_PLLCFGR_PLLN_8 0x00004000U
AnnaBridge 126:abea610beb85 5860 #define RCC_PLLCFGR_PLLP 0x00030000U
AnnaBridge 126:abea610beb85 5861 #define RCC_PLLCFGR_PLLP_0 0x00010000U
AnnaBridge 126:abea610beb85 5862 #define RCC_PLLCFGR_PLLP_1 0x00020000U
AnnaBridge 126:abea610beb85 5863 #define RCC_PLLCFGR_PLLSRC 0x00400000U
AnnaBridge 126:abea610beb85 5864 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
AnnaBridge 126:abea610beb85 5865 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
AnnaBridge 126:abea610beb85 5866 #define RCC_PLLCFGR_PLLQ 0x0F000000U
AnnaBridge 126:abea610beb85 5867 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
AnnaBridge 126:abea610beb85 5868 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
AnnaBridge 126:abea610beb85 5869 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
AnnaBridge 126:abea610beb85 5870 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
AnnaBridge 126:abea610beb85 5871
AnnaBridge 126:abea610beb85 5872 #define RCC_PLLCFGR_PLLR 0x70000000U
AnnaBridge 126:abea610beb85 5873 #define RCC_PLLCFGR_PLLR_0 0x10000000U
AnnaBridge 126:abea610beb85 5874 #define RCC_PLLCFGR_PLLR_1 0x20000000U
AnnaBridge 126:abea610beb85 5875 #define RCC_PLLCFGR_PLLR_2 0x40000000U
AnnaBridge 126:abea610beb85 5876
AnnaBridge 126:abea610beb85 5877 /******************** Bit definition for RCC_CFGR register ******************/
AnnaBridge 126:abea610beb85 5878 /*!< SW configuration */
AnnaBridge 126:abea610beb85 5879 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 126:abea610beb85 5880 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5881 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5882 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
AnnaBridge 126:abea610beb85 5883 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
AnnaBridge 126:abea610beb85 5884 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
AnnaBridge 126:abea610beb85 5885
AnnaBridge 126:abea610beb85 5886 /*!< SWS configuration */
AnnaBridge 126:abea610beb85 5887 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 126:abea610beb85 5888 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5889 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5890 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
AnnaBridge 126:abea610beb85 5891 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
AnnaBridge 126:abea610beb85 5892 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
AnnaBridge 126:abea610beb85 5893
AnnaBridge 126:abea610beb85 5894 /*!< HPRE configuration */
AnnaBridge 126:abea610beb85 5895 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 126:abea610beb85 5896 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5897 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5898 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 5899 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
AnnaBridge 126:abea610beb85 5900
AnnaBridge 126:abea610beb85 5901 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
AnnaBridge 126:abea610beb85 5902 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
AnnaBridge 126:abea610beb85 5903 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
AnnaBridge 126:abea610beb85 5904 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
AnnaBridge 126:abea610beb85 5905 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
AnnaBridge 126:abea610beb85 5906 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
AnnaBridge 126:abea610beb85 5907 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
AnnaBridge 126:abea610beb85 5908 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
AnnaBridge 126:abea610beb85 5909 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
AnnaBridge 126:abea610beb85 5910
AnnaBridge 126:abea610beb85 5911 /*!< PPRE1 configuration */
AnnaBridge 126:abea610beb85 5912 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
AnnaBridge 126:abea610beb85 5913 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5914 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5915 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 5916
AnnaBridge 126:abea610beb85 5917 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 126:abea610beb85 5918 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
AnnaBridge 126:abea610beb85 5919 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
AnnaBridge 126:abea610beb85 5920 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
AnnaBridge 126:abea610beb85 5921 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
AnnaBridge 126:abea610beb85 5922
AnnaBridge 126:abea610beb85 5923 /*!< PPRE2 configuration */
AnnaBridge 126:abea610beb85 5924 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 126:abea610beb85 5925 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 5926 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 5927 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 5928
AnnaBridge 126:abea610beb85 5929 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 126:abea610beb85 5930 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
AnnaBridge 126:abea610beb85 5931 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
AnnaBridge 126:abea610beb85 5932 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
AnnaBridge 126:abea610beb85 5933 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
AnnaBridge 126:abea610beb85 5934
AnnaBridge 126:abea610beb85 5935 /*!< RTCPRE configuration */
AnnaBridge 126:abea610beb85 5936 #define RCC_CFGR_RTCPRE 0x001F0000U
AnnaBridge 126:abea610beb85 5937 #define RCC_CFGR_RTCPRE_0 0x00010000U
AnnaBridge 126:abea610beb85 5938 #define RCC_CFGR_RTCPRE_1 0x00020000U
AnnaBridge 126:abea610beb85 5939 #define RCC_CFGR_RTCPRE_2 0x00040000U
AnnaBridge 126:abea610beb85 5940 #define RCC_CFGR_RTCPRE_3 0x00080000U
AnnaBridge 126:abea610beb85 5941 #define RCC_CFGR_RTCPRE_4 0x00100000U
AnnaBridge 126:abea610beb85 5942
AnnaBridge 126:abea610beb85 5943 /*!< MCO1 configuration */
AnnaBridge 126:abea610beb85 5944 #define RCC_CFGR_MCO1 0x00600000U
AnnaBridge 126:abea610beb85 5945 #define RCC_CFGR_MCO1_0 0x00200000U
AnnaBridge 126:abea610beb85 5946 #define RCC_CFGR_MCO1_1 0x00400000U
AnnaBridge 126:abea610beb85 5947
AnnaBridge 126:abea610beb85 5948 #define RCC_CFGR_I2SSRC 0x00800000U
AnnaBridge 126:abea610beb85 5949
AnnaBridge 126:abea610beb85 5950 #define RCC_CFGR_MCO1PRE 0x07000000U
AnnaBridge 126:abea610beb85 5951 #define RCC_CFGR_MCO1PRE_0 0x01000000U
AnnaBridge 126:abea610beb85 5952 #define RCC_CFGR_MCO1PRE_1 0x02000000U
AnnaBridge 126:abea610beb85 5953 #define RCC_CFGR_MCO1PRE_2 0x04000000U
AnnaBridge 126:abea610beb85 5954
AnnaBridge 126:abea610beb85 5955 #define RCC_CFGR_MCO2PRE 0x38000000U
AnnaBridge 126:abea610beb85 5956 #define RCC_CFGR_MCO2PRE_0 0x08000000U
AnnaBridge 126:abea610beb85 5957 #define RCC_CFGR_MCO2PRE_1 0x10000000U
AnnaBridge 126:abea610beb85 5958 #define RCC_CFGR_MCO2PRE_2 0x20000000U
AnnaBridge 126:abea610beb85 5959
AnnaBridge 126:abea610beb85 5960 #define RCC_CFGR_MCO2 0xC0000000U
AnnaBridge 126:abea610beb85 5961 #define RCC_CFGR_MCO2_0 0x40000000U
AnnaBridge 126:abea610beb85 5962 #define RCC_CFGR_MCO2_1 0x80000000U
AnnaBridge 126:abea610beb85 5963
AnnaBridge 126:abea610beb85 5964 /******************** Bit definition for RCC_CIR register *******************/
AnnaBridge 126:abea610beb85 5965 #define RCC_CIR_LSIRDYF 0x00000001U
AnnaBridge 126:abea610beb85 5966 #define RCC_CIR_LSERDYF 0x00000002U
AnnaBridge 126:abea610beb85 5967 #define RCC_CIR_HSIRDYF 0x00000004U
AnnaBridge 126:abea610beb85 5968 #define RCC_CIR_HSERDYF 0x00000008U
AnnaBridge 126:abea610beb85 5969 #define RCC_CIR_PLLRDYF 0x00000010U
AnnaBridge 126:abea610beb85 5970 #define RCC_CIR_PLLI2SRDYF 0x00000020U
AnnaBridge 126:abea610beb85 5971 #define RCC_CIR_PLLSAIRDYF 0x00000040U
AnnaBridge 126:abea610beb85 5972 #define RCC_CIR_CSSF 0x00000080U
AnnaBridge 126:abea610beb85 5973 #define RCC_CIR_LSIRDYIE 0x00000100U
AnnaBridge 126:abea610beb85 5974 #define RCC_CIR_LSERDYIE 0x00000200U
AnnaBridge 126:abea610beb85 5975 #define RCC_CIR_HSIRDYIE 0x00000400U
AnnaBridge 126:abea610beb85 5976 #define RCC_CIR_HSERDYIE 0x00000800U
AnnaBridge 126:abea610beb85 5977 #define RCC_CIR_PLLRDYIE 0x00001000U
AnnaBridge 126:abea610beb85 5978 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
AnnaBridge 126:abea610beb85 5979 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
AnnaBridge 126:abea610beb85 5980 #define RCC_CIR_LSIRDYC 0x00010000U
AnnaBridge 126:abea610beb85 5981 #define RCC_CIR_LSERDYC 0x00020000U
AnnaBridge 126:abea610beb85 5982 #define RCC_CIR_HSIRDYC 0x00040000U
AnnaBridge 126:abea610beb85 5983 #define RCC_CIR_HSERDYC 0x00080000U
AnnaBridge 126:abea610beb85 5984 #define RCC_CIR_PLLRDYC 0x00100000U
AnnaBridge 126:abea610beb85 5985 #define RCC_CIR_PLLI2SRDYC 0x00200000U
AnnaBridge 126:abea610beb85 5986 #define RCC_CIR_PLLSAIRDYC 0x00400000U
AnnaBridge 126:abea610beb85 5987 #define RCC_CIR_CSSC 0x00800000U
AnnaBridge 126:abea610beb85 5988
AnnaBridge 126:abea610beb85 5989 /******************** Bit definition for RCC_AHB1RSTR register **************/
AnnaBridge 126:abea610beb85 5990 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
AnnaBridge 126:abea610beb85 5991 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
AnnaBridge 126:abea610beb85 5992 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
AnnaBridge 126:abea610beb85 5993 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
AnnaBridge 126:abea610beb85 5994 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
AnnaBridge 126:abea610beb85 5995 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
AnnaBridge 126:abea610beb85 5996 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
AnnaBridge 126:abea610beb85 5997 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
AnnaBridge 126:abea610beb85 5998 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
AnnaBridge 126:abea610beb85 5999 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
AnnaBridge 126:abea610beb85 6000 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
AnnaBridge 126:abea610beb85 6001 #define RCC_AHB1RSTR_CRCRST 0x00001000U
AnnaBridge 126:abea610beb85 6002 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
AnnaBridge 126:abea610beb85 6003 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
AnnaBridge 126:abea610beb85 6004 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
AnnaBridge 126:abea610beb85 6005 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
AnnaBridge 126:abea610beb85 6006 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
AnnaBridge 126:abea610beb85 6007
AnnaBridge 126:abea610beb85 6008 /******************** Bit definition for RCC_AHB2RSTR register **************/
AnnaBridge 126:abea610beb85 6009 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
AnnaBridge 126:abea610beb85 6010 #define RCC_AHB2RSTR_JPEGRST 0x00000002U
AnnaBridge 126:abea610beb85 6011 #define RCC_AHB2RSTR_RNGRST 0x00000040U
AnnaBridge 126:abea610beb85 6012 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
AnnaBridge 126:abea610beb85 6013
AnnaBridge 126:abea610beb85 6014 /******************** Bit definition for RCC_AHB3RSTR register **************/
AnnaBridge 126:abea610beb85 6015
AnnaBridge 126:abea610beb85 6016 #define RCC_AHB3RSTR_FMCRST 0x00000001U
AnnaBridge 126:abea610beb85 6017 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
AnnaBridge 126:abea610beb85 6018
AnnaBridge 126:abea610beb85 6019 /******************** Bit definition for RCC_APB1RSTR register **************/
AnnaBridge 126:abea610beb85 6020 #define RCC_APB1RSTR_TIM2RST 0x00000001U
AnnaBridge 126:abea610beb85 6021 #define RCC_APB1RSTR_TIM3RST 0x00000002U
AnnaBridge 126:abea610beb85 6022 #define RCC_APB1RSTR_TIM4RST 0x00000004U
AnnaBridge 126:abea610beb85 6023 #define RCC_APB1RSTR_TIM5RST 0x00000008U
AnnaBridge 126:abea610beb85 6024 #define RCC_APB1RSTR_TIM6RST 0x00000010U
AnnaBridge 126:abea610beb85 6025 #define RCC_APB1RSTR_TIM7RST 0x00000020U
AnnaBridge 126:abea610beb85 6026 #define RCC_APB1RSTR_TIM12RST 0x00000040U
AnnaBridge 126:abea610beb85 6027 #define RCC_APB1RSTR_TIM13RST 0x00000080U
AnnaBridge 126:abea610beb85 6028 #define RCC_APB1RSTR_TIM14RST 0x00000100U
AnnaBridge 126:abea610beb85 6029 #define RCC_APB1RSTR_LPTIM1RST 0x00000200U
AnnaBridge 126:abea610beb85 6030 #define RCC_APB1RSTR_WWDGRST 0x00000800U
AnnaBridge 126:abea610beb85 6031 #define RCC_APB1RSTR_CAN3RST 0x00002000U
AnnaBridge 126:abea610beb85 6032 #define RCC_APB1RSTR_SPI2RST 0x00004000U
AnnaBridge 126:abea610beb85 6033 #define RCC_APB1RSTR_SPI3RST 0x00008000U
AnnaBridge 126:abea610beb85 6034 #define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
AnnaBridge 126:abea610beb85 6035 #define RCC_APB1RSTR_USART2RST 0x00020000U
AnnaBridge 126:abea610beb85 6036 #define RCC_APB1RSTR_USART3RST 0x00040000U
AnnaBridge 126:abea610beb85 6037 #define RCC_APB1RSTR_UART4RST 0x00080000U
AnnaBridge 126:abea610beb85 6038 #define RCC_APB1RSTR_UART5RST 0x00100000U
AnnaBridge 126:abea610beb85 6039 #define RCC_APB1RSTR_I2C1RST 0x00200000U
AnnaBridge 126:abea610beb85 6040 #define RCC_APB1RSTR_I2C2RST 0x00400000U
AnnaBridge 126:abea610beb85 6041 #define RCC_APB1RSTR_I2C3RST 0x00800000U
AnnaBridge 126:abea610beb85 6042 #define RCC_APB1RSTR_I2C4RST 0x01000000U
AnnaBridge 126:abea610beb85 6043 #define RCC_APB1RSTR_CAN1RST 0x02000000U
AnnaBridge 126:abea610beb85 6044 #define RCC_APB1RSTR_CAN2RST 0x04000000U
AnnaBridge 126:abea610beb85 6045 #define RCC_APB1RSTR_CECRST 0x08000000U
AnnaBridge 126:abea610beb85 6046 #define RCC_APB1RSTR_PWRRST 0x10000000U
AnnaBridge 126:abea610beb85 6047 #define RCC_APB1RSTR_DACRST 0x20000000U
AnnaBridge 126:abea610beb85 6048 #define RCC_APB1RSTR_UART7RST 0x40000000U
AnnaBridge 126:abea610beb85 6049 #define RCC_APB1RSTR_UART8RST 0x80000000U
AnnaBridge 126:abea610beb85 6050
AnnaBridge 126:abea610beb85 6051 /******************** Bit definition for RCC_APB2RSTR register **************/
AnnaBridge 126:abea610beb85 6052 #define RCC_APB2RSTR_TIM1RST 0x00000001U
AnnaBridge 126:abea610beb85 6053 #define RCC_APB2RSTR_TIM8RST 0x00000002U
AnnaBridge 126:abea610beb85 6054 #define RCC_APB2RSTR_USART1RST 0x00000010U
AnnaBridge 126:abea610beb85 6055 #define RCC_APB2RSTR_USART6RST 0x00000020U
AnnaBridge 126:abea610beb85 6056 #define RCC_APB2RSTR_SDMMC2RST 0x00000080U
AnnaBridge 126:abea610beb85 6057 #define RCC_APB2RSTR_ADCRST 0x00000100U
AnnaBridge 126:abea610beb85 6058 #define RCC_APB2RSTR_SDMMC1RST 0x00000800U
AnnaBridge 126:abea610beb85 6059 #define RCC_APB2RSTR_SPI1RST 0x00001000U
AnnaBridge 126:abea610beb85 6060 #define RCC_APB2RSTR_SPI4RST 0x00002000U
AnnaBridge 126:abea610beb85 6061 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
AnnaBridge 126:abea610beb85 6062 #define RCC_APB2RSTR_TIM9RST 0x00010000U
AnnaBridge 126:abea610beb85 6063 #define RCC_APB2RSTR_TIM10RST 0x00020000U
AnnaBridge 126:abea610beb85 6064 #define RCC_APB2RSTR_TIM11RST 0x00040000U
AnnaBridge 126:abea610beb85 6065 #define RCC_APB2RSTR_SPI5RST 0x00100000U
AnnaBridge 126:abea610beb85 6066 #define RCC_APB2RSTR_SPI6RST 0x00200000U
AnnaBridge 126:abea610beb85 6067 #define RCC_APB2RSTR_SAI1RST 0x00400000U
AnnaBridge 126:abea610beb85 6068 #define RCC_APB2RSTR_SAI2RST 0x00800000U
AnnaBridge 126:abea610beb85 6069 #define RCC_APB2RSTR_LTDCRST 0x04000000U
AnnaBridge 126:abea610beb85 6070 #define RCC_APB2RSTR_DSIRST 0x08000000U
AnnaBridge 126:abea610beb85 6071 #define RCC_APB2RSTR_DFSDM1RST 0x20000000U
AnnaBridge 126:abea610beb85 6072 #define RCC_APB2RSTR_MDIORST 0x40000000U
AnnaBridge 126:abea610beb85 6073
AnnaBridge 126:abea610beb85 6074 /******************** Bit definition for RCC_AHB1ENR register ***************/
AnnaBridge 126:abea610beb85 6075 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
AnnaBridge 126:abea610beb85 6076 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
AnnaBridge 126:abea610beb85 6077 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
AnnaBridge 126:abea610beb85 6078 #define RCC_AHB1ENR_GPIODEN 0x00000008U
AnnaBridge 126:abea610beb85 6079 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
AnnaBridge 126:abea610beb85 6080 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
AnnaBridge 126:abea610beb85 6081 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
AnnaBridge 126:abea610beb85 6082 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
AnnaBridge 126:abea610beb85 6083 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
AnnaBridge 126:abea610beb85 6084 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
AnnaBridge 126:abea610beb85 6085 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
AnnaBridge 126:abea610beb85 6086 #define RCC_AHB1ENR_CRCEN 0x00001000U
AnnaBridge 126:abea610beb85 6087 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
AnnaBridge 126:abea610beb85 6088 #define RCC_AHB1ENR_DTCMRAMEN 0x00100000U
AnnaBridge 126:abea610beb85 6089 #define RCC_AHB1ENR_DMA1EN 0x00200000U
AnnaBridge 126:abea610beb85 6090 #define RCC_AHB1ENR_DMA2EN 0x00400000U
AnnaBridge 126:abea610beb85 6091 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
AnnaBridge 126:abea610beb85 6092 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
AnnaBridge 126:abea610beb85 6093 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
AnnaBridge 126:abea610beb85 6094 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
AnnaBridge 126:abea610beb85 6095 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
AnnaBridge 126:abea610beb85 6096 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
AnnaBridge 126:abea610beb85 6097 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
AnnaBridge 126:abea610beb85 6098
AnnaBridge 126:abea610beb85 6099 /******************** Bit definition for RCC_AHB2ENR register ***************/
AnnaBridge 126:abea610beb85 6100 #define RCC_AHB2ENR_DCMIEN 0x00000001U
AnnaBridge 126:abea610beb85 6101 #define RCC_AHB2ENR_JPEGEN 0x00000002U
AnnaBridge 126:abea610beb85 6102 #define RCC_AHB2ENR_RNGEN 0x00000040U
AnnaBridge 126:abea610beb85 6103 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
AnnaBridge 126:abea610beb85 6104
AnnaBridge 126:abea610beb85 6105 /******************** Bit definition for RCC_AHB3ENR register ***************/
AnnaBridge 126:abea610beb85 6106 #define RCC_AHB3ENR_FMCEN 0x00000001U
AnnaBridge 126:abea610beb85 6107 #define RCC_AHB3ENR_QSPIEN 0x00000002U
AnnaBridge 126:abea610beb85 6108
AnnaBridge 126:abea610beb85 6109 /******************** Bit definition for RCC_APB1ENR register ***************/
AnnaBridge 126:abea610beb85 6110 #define RCC_APB1ENR_TIM2EN 0x00000001U
AnnaBridge 126:abea610beb85 6111 #define RCC_APB1ENR_TIM3EN 0x00000002U
AnnaBridge 126:abea610beb85 6112 #define RCC_APB1ENR_TIM4EN 0x00000004U
AnnaBridge 126:abea610beb85 6113 #define RCC_APB1ENR_TIM5EN 0x00000008U
AnnaBridge 126:abea610beb85 6114 #define RCC_APB1ENR_TIM6EN 0x00000010U
AnnaBridge 126:abea610beb85 6115 #define RCC_APB1ENR_TIM7EN 0x00000020U
AnnaBridge 126:abea610beb85 6116 #define RCC_APB1ENR_TIM12EN 0x00000040U
AnnaBridge 126:abea610beb85 6117 #define RCC_APB1ENR_TIM13EN 0x00000080U
AnnaBridge 126:abea610beb85 6118 #define RCC_APB1ENR_TIM14EN 0x00000100U
AnnaBridge 126:abea610beb85 6119 #define RCC_APB1ENR_LPTIM1EN 0x00000200U
AnnaBridge 126:abea610beb85 6120 #define RCC_APB1ENR_RTCEN 0x00000400U
AnnaBridge 126:abea610beb85 6121 #define RCC_APB1ENR_WWDGEN 0x00000800U
AnnaBridge 126:abea610beb85 6122 #define RCC_APB1ENR_CAN3EN 0x00002000U
AnnaBridge 126:abea610beb85 6123 #define RCC_APB1ENR_SPI2EN 0x00004000U
AnnaBridge 126:abea610beb85 6124 #define RCC_APB1ENR_SPI3EN 0x00008000U
AnnaBridge 126:abea610beb85 6125 #define RCC_APB1ENR_SPDIFRXEN 0x00010000U
AnnaBridge 126:abea610beb85 6126 #define RCC_APB1ENR_USART2EN 0x00020000U
AnnaBridge 126:abea610beb85 6127 #define RCC_APB1ENR_USART3EN 0x00040000U
AnnaBridge 126:abea610beb85 6128 #define RCC_APB1ENR_UART4EN 0x00080000U
AnnaBridge 126:abea610beb85 6129 #define RCC_APB1ENR_UART5EN 0x00100000U
AnnaBridge 126:abea610beb85 6130 #define RCC_APB1ENR_I2C1EN 0x00200000U
AnnaBridge 126:abea610beb85 6131 #define RCC_APB1ENR_I2C2EN 0x00400000U
AnnaBridge 126:abea610beb85 6132 #define RCC_APB1ENR_I2C3EN 0x00800000U
AnnaBridge 126:abea610beb85 6133 #define RCC_APB1ENR_I2C4EN 0x01000000U
AnnaBridge 126:abea610beb85 6134 #define RCC_APB1ENR_CAN1EN 0x02000000U
AnnaBridge 126:abea610beb85 6135 #define RCC_APB1ENR_CAN2EN 0x04000000U
AnnaBridge 126:abea610beb85 6136 #define RCC_APB1ENR_CECEN 0x08000000U
AnnaBridge 126:abea610beb85 6137 #define RCC_APB1ENR_PWREN 0x10000000U
AnnaBridge 126:abea610beb85 6138 #define RCC_APB1ENR_DACEN 0x20000000U
AnnaBridge 126:abea610beb85 6139 #define RCC_APB1ENR_UART7EN 0x40000000U
AnnaBridge 126:abea610beb85 6140 #define RCC_APB1ENR_UART8EN 0x80000000U
AnnaBridge 126:abea610beb85 6141
AnnaBridge 126:abea610beb85 6142 /******************** Bit definition for RCC_APB2ENR register ***************/
AnnaBridge 126:abea610beb85 6143 #define RCC_APB2ENR_TIM1EN 0x00000001U
AnnaBridge 126:abea610beb85 6144 #define RCC_APB2ENR_TIM8EN 0x00000002U
AnnaBridge 126:abea610beb85 6145 #define RCC_APB2ENR_USART1EN 0x00000010U
AnnaBridge 126:abea610beb85 6146 #define RCC_APB2ENR_USART6EN 0x00000020U
AnnaBridge 126:abea610beb85 6147 #define RCC_APB2ENR_SDMMC2EN 0x00000080U
AnnaBridge 126:abea610beb85 6148 #define RCC_APB2ENR_ADC1EN 0x00000100U
AnnaBridge 126:abea610beb85 6149 #define RCC_APB2ENR_ADC2EN 0x00000200U
AnnaBridge 126:abea610beb85 6150 #define RCC_APB2ENR_ADC3EN 0x00000400U
AnnaBridge 126:abea610beb85 6151 #define RCC_APB2ENR_SDMMC1EN 0x00000800U
AnnaBridge 126:abea610beb85 6152 #define RCC_APB2ENR_SPI1EN 0x00001000U
AnnaBridge 126:abea610beb85 6153 #define RCC_APB2ENR_SPI4EN 0x00002000U
AnnaBridge 126:abea610beb85 6154 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
AnnaBridge 126:abea610beb85 6155 #define RCC_APB2ENR_TIM9EN 0x00010000U
AnnaBridge 126:abea610beb85 6156 #define RCC_APB2ENR_TIM10EN 0x00020000U
AnnaBridge 126:abea610beb85 6157 #define RCC_APB2ENR_TIM11EN 0x00040000U
AnnaBridge 126:abea610beb85 6158 #define RCC_APB2ENR_SPI5EN 0x00100000U
AnnaBridge 126:abea610beb85 6159 #define RCC_APB2ENR_SPI6EN 0x00200000U
AnnaBridge 126:abea610beb85 6160 #define RCC_APB2ENR_SAI1EN 0x00400000U
AnnaBridge 126:abea610beb85 6161 #define RCC_APB2ENR_SAI2EN 0x00800000U
AnnaBridge 126:abea610beb85 6162 #define RCC_APB2ENR_LTDCEN 0x04000000U
AnnaBridge 126:abea610beb85 6163 #define RCC_APB2ENR_DSIEN 0x08000000U
AnnaBridge 126:abea610beb85 6164 #define RCC_APB2ENR_DFSDM1EN 0x20000000U
AnnaBridge 126:abea610beb85 6165 #define RCC_APB2ENR_MDIOEN 0x40000000U
AnnaBridge 126:abea610beb85 6166
AnnaBridge 126:abea610beb85 6167 /******************** Bit definition for RCC_AHB1LPENR register *************/
AnnaBridge 126:abea610beb85 6168 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
AnnaBridge 126:abea610beb85 6169 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
AnnaBridge 126:abea610beb85 6170 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
AnnaBridge 126:abea610beb85 6171 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
AnnaBridge 126:abea610beb85 6172 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
AnnaBridge 126:abea610beb85 6173 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
AnnaBridge 126:abea610beb85 6174 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
AnnaBridge 126:abea610beb85 6175 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
AnnaBridge 126:abea610beb85 6176 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
AnnaBridge 126:abea610beb85 6177 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
AnnaBridge 126:abea610beb85 6178 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
AnnaBridge 126:abea610beb85 6179 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
AnnaBridge 126:abea610beb85 6180 #define RCC_AHB1LPENR_AXILPEN 0x00002000U
AnnaBridge 126:abea610beb85 6181 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
AnnaBridge 126:abea610beb85 6182 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
AnnaBridge 126:abea610beb85 6183 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
AnnaBridge 126:abea610beb85 6184 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
AnnaBridge 126:abea610beb85 6185 #define RCC_AHB1LPENR_DTCMLPEN 0x00100000U
AnnaBridge 126:abea610beb85 6186 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
AnnaBridge 126:abea610beb85 6187 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
AnnaBridge 126:abea610beb85 6188 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
AnnaBridge 126:abea610beb85 6189 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
AnnaBridge 126:abea610beb85 6190 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
AnnaBridge 126:abea610beb85 6191 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
AnnaBridge 126:abea610beb85 6192 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
AnnaBridge 126:abea610beb85 6193 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
AnnaBridge 126:abea610beb85 6194 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
AnnaBridge 126:abea610beb85 6195
AnnaBridge 126:abea610beb85 6196 /******************** Bit definition for RCC_AHB2LPENR register *************/
AnnaBridge 126:abea610beb85 6197 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
AnnaBridge 126:abea610beb85 6198 #define RCC_AHB2LPENR_JPEGLPEN 0x00000002U
AnnaBridge 126:abea610beb85 6199 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
AnnaBridge 126:abea610beb85 6200 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
AnnaBridge 126:abea610beb85 6201
AnnaBridge 126:abea610beb85 6202 /******************** Bit definition for RCC_AHB3LPENR register *************/
AnnaBridge 126:abea610beb85 6203 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
AnnaBridge 126:abea610beb85 6204 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
AnnaBridge 126:abea610beb85 6205 /******************** Bit definition for RCC_APB1LPENR register *************/
AnnaBridge 126:abea610beb85 6206 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
AnnaBridge 126:abea610beb85 6207 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
AnnaBridge 126:abea610beb85 6208 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
AnnaBridge 126:abea610beb85 6209 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
AnnaBridge 126:abea610beb85 6210 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
AnnaBridge 126:abea610beb85 6211 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
AnnaBridge 126:abea610beb85 6212 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
AnnaBridge 126:abea610beb85 6213 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
AnnaBridge 126:abea610beb85 6214 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
AnnaBridge 126:abea610beb85 6215 #define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
AnnaBridge 126:abea610beb85 6216 #define RCC_APB1LPENR_RTCLPEN 0x00000400U
AnnaBridge 126:abea610beb85 6217 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
AnnaBridge 126:abea610beb85 6218 #define RCC_APB1LPENR_CAN3LPEN 0x00002000U
AnnaBridge 126:abea610beb85 6219 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
AnnaBridge 126:abea610beb85 6220 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
AnnaBridge 126:abea610beb85 6221 #define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
AnnaBridge 126:abea610beb85 6222 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
AnnaBridge 126:abea610beb85 6223 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
AnnaBridge 126:abea610beb85 6224 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
AnnaBridge 126:abea610beb85 6225 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
AnnaBridge 126:abea610beb85 6226 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
AnnaBridge 126:abea610beb85 6227 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
AnnaBridge 126:abea610beb85 6228 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
AnnaBridge 126:abea610beb85 6229 #define RCC_APB1LPENR_I2C4LPEN 0x01000000U
AnnaBridge 126:abea610beb85 6230 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
AnnaBridge 126:abea610beb85 6231 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
AnnaBridge 126:abea610beb85 6232 #define RCC_APB1LPENR_CECLPEN 0x08000000U
AnnaBridge 126:abea610beb85 6233 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
AnnaBridge 126:abea610beb85 6234 #define RCC_APB1LPENR_DACLPEN 0x20000000U
AnnaBridge 126:abea610beb85 6235 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
AnnaBridge 126:abea610beb85 6236 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
AnnaBridge 126:abea610beb85 6237
AnnaBridge 126:abea610beb85 6238 /******************** Bit definition for RCC_APB2LPENR register *************/
AnnaBridge 126:abea610beb85 6239 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
AnnaBridge 126:abea610beb85 6240 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
AnnaBridge 126:abea610beb85 6241 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
AnnaBridge 126:abea610beb85 6242 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
AnnaBridge 126:abea610beb85 6243 #define RCC_APB2LPENR_SDMMC2LPEN 0x00000080U
AnnaBridge 126:abea610beb85 6244 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
AnnaBridge 126:abea610beb85 6245 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
AnnaBridge 126:abea610beb85 6246 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
AnnaBridge 126:abea610beb85 6247 #define RCC_APB2LPENR_SDMMC1LPEN 0x00000800U
AnnaBridge 126:abea610beb85 6248 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
AnnaBridge 126:abea610beb85 6249 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
AnnaBridge 126:abea610beb85 6250 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
AnnaBridge 126:abea610beb85 6251 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
AnnaBridge 126:abea610beb85 6252 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
AnnaBridge 126:abea610beb85 6253 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
AnnaBridge 126:abea610beb85 6254 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
AnnaBridge 126:abea610beb85 6255 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
AnnaBridge 126:abea610beb85 6256 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
AnnaBridge 126:abea610beb85 6257 #define RCC_APB2LPENR_SAI2LPEN 0x00800000U
AnnaBridge 126:abea610beb85 6258 #define RCC_APB2LPENR_LTDCLPEN 0x04000000U
AnnaBridge 126:abea610beb85 6259 #define RCC_APB2LPENR_DSILPEN 0x08000000U
AnnaBridge 126:abea610beb85 6260 #define RCC_APB2LPENR_DFSDM1LPEN 0x20000000U
AnnaBridge 126:abea610beb85 6261 #define RCC_APB2LPENR_MDIOLPEN 0x40000000U
AnnaBridge 126:abea610beb85 6262
AnnaBridge 126:abea610beb85 6263 /******************** Bit definition for RCC_BDCR register ******************/
AnnaBridge 126:abea610beb85 6264 #define RCC_BDCR_LSEON 0x00000001U
AnnaBridge 126:abea610beb85 6265 #define RCC_BDCR_LSERDY 0x00000002U
AnnaBridge 126:abea610beb85 6266 #define RCC_BDCR_LSEBYP 0x00000004U
AnnaBridge 126:abea610beb85 6267 #define RCC_BDCR_LSEDRV 0x00000018U
AnnaBridge 126:abea610beb85 6268 #define RCC_BDCR_LSEDRV_0 0x00000008U
AnnaBridge 126:abea610beb85 6269 #define RCC_BDCR_LSEDRV_1 0x00000010U
AnnaBridge 126:abea610beb85 6270 #define RCC_BDCR_RTCSEL 0x00000300U
AnnaBridge 126:abea610beb85 6271 #define RCC_BDCR_RTCSEL_0 0x00000100U
AnnaBridge 126:abea610beb85 6272 #define RCC_BDCR_RTCSEL_1 0x00000200U
AnnaBridge 126:abea610beb85 6273 #define RCC_BDCR_RTCEN 0x00008000U
AnnaBridge 126:abea610beb85 6274 #define RCC_BDCR_BDRST 0x00010000U
AnnaBridge 126:abea610beb85 6275
AnnaBridge 126:abea610beb85 6276 /******************** Bit definition for RCC_CSR register *******************/
AnnaBridge 126:abea610beb85 6277 #define RCC_CSR_LSION 0x00000001U
AnnaBridge 126:abea610beb85 6278 #define RCC_CSR_LSIRDY 0x00000002U
AnnaBridge 126:abea610beb85 6279 #define RCC_CSR_RMVF 0x01000000U
AnnaBridge 126:abea610beb85 6280 #define RCC_CSR_BORRSTF 0x02000000U
AnnaBridge 126:abea610beb85 6281 #define RCC_CSR_PINRSTF 0x04000000U
AnnaBridge 126:abea610beb85 6282 #define RCC_CSR_PORRSTF 0x08000000U
AnnaBridge 126:abea610beb85 6283 #define RCC_CSR_SFTRSTF 0x10000000U
AnnaBridge 126:abea610beb85 6284 #define RCC_CSR_IWDGRSTF 0x20000000U
AnnaBridge 126:abea610beb85 6285 #define RCC_CSR_WWDGRSTF 0x40000000U
AnnaBridge 126:abea610beb85 6286 #define RCC_CSR_LPWRRSTF 0x80000000U
AnnaBridge 126:abea610beb85 6287
AnnaBridge 126:abea610beb85 6288 /******************** Bit definition for RCC_SSCGR register *****************/
AnnaBridge 126:abea610beb85 6289 #define RCC_SSCGR_MODPER 0x00001FFFU
AnnaBridge 126:abea610beb85 6290 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
AnnaBridge 126:abea610beb85 6291 #define RCC_SSCGR_SPREADSEL 0x40000000U
AnnaBridge 126:abea610beb85 6292 #define RCC_SSCGR_SSCGEN 0x80000000U
AnnaBridge 126:abea610beb85 6293
AnnaBridge 126:abea610beb85 6294 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
AnnaBridge 126:abea610beb85 6295 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
AnnaBridge 126:abea610beb85 6296 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
AnnaBridge 126:abea610beb85 6297 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
AnnaBridge 126:abea610beb85 6298 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
AnnaBridge 126:abea610beb85 6299 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
AnnaBridge 126:abea610beb85 6300 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
AnnaBridge 126:abea610beb85 6301 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
AnnaBridge 126:abea610beb85 6302 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
AnnaBridge 126:abea610beb85 6303 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
AnnaBridge 126:abea610beb85 6304 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
AnnaBridge 126:abea610beb85 6305 #define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
AnnaBridge 126:abea610beb85 6306 #define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
AnnaBridge 126:abea610beb85 6307 #define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
AnnaBridge 126:abea610beb85 6308 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
AnnaBridge 126:abea610beb85 6309 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
AnnaBridge 126:abea610beb85 6310 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
AnnaBridge 126:abea610beb85 6311 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
AnnaBridge 126:abea610beb85 6312 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
AnnaBridge 126:abea610beb85 6313 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
AnnaBridge 126:abea610beb85 6314 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
AnnaBridge 126:abea610beb85 6315 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
AnnaBridge 126:abea610beb85 6316 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
AnnaBridge 126:abea610beb85 6317
AnnaBridge 126:abea610beb85 6318 /******************** Bit definition for RCC_PLLSAICFGR register ************/
AnnaBridge 126:abea610beb85 6319 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
AnnaBridge 126:abea610beb85 6320 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
AnnaBridge 126:abea610beb85 6321 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
AnnaBridge 126:abea610beb85 6322 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
AnnaBridge 126:abea610beb85 6323 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
AnnaBridge 126:abea610beb85 6324 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
AnnaBridge 126:abea610beb85 6325 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
AnnaBridge 126:abea610beb85 6326 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
AnnaBridge 126:abea610beb85 6327 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
AnnaBridge 126:abea610beb85 6328 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
AnnaBridge 126:abea610beb85 6329 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
AnnaBridge 126:abea610beb85 6330 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
AnnaBridge 126:abea610beb85 6331 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
AnnaBridge 126:abea610beb85 6332 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
AnnaBridge 126:abea610beb85 6333 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
AnnaBridge 126:abea610beb85 6334 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
AnnaBridge 126:abea610beb85 6335 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
AnnaBridge 126:abea610beb85 6336 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
AnnaBridge 126:abea610beb85 6337 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
AnnaBridge 126:abea610beb85 6338 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
AnnaBridge 126:abea610beb85 6339 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
AnnaBridge 126:abea610beb85 6340 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
AnnaBridge 126:abea610beb85 6341
AnnaBridge 126:abea610beb85 6342 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
AnnaBridge 126:abea610beb85 6343 #define RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU
AnnaBridge 126:abea610beb85 6344 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U
AnnaBridge 126:abea610beb85 6345 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U
AnnaBridge 126:abea610beb85 6346 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U
AnnaBridge 126:abea610beb85 6347 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U
AnnaBridge 126:abea610beb85 6348 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U
AnnaBridge 126:abea610beb85 6349
AnnaBridge 126:abea610beb85 6350 #define RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U
AnnaBridge 126:abea610beb85 6351 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U
AnnaBridge 126:abea610beb85 6352 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U
AnnaBridge 126:abea610beb85 6353 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U
AnnaBridge 126:abea610beb85 6354 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U
AnnaBridge 126:abea610beb85 6355 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U
AnnaBridge 126:abea610beb85 6356
AnnaBridge 126:abea610beb85 6357 #define RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U
AnnaBridge 126:abea610beb85 6358 #define RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U
AnnaBridge 126:abea610beb85 6359 #define RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U
AnnaBridge 126:abea610beb85 6360
AnnaBridge 126:abea610beb85 6361 #define RCC_DCKCFGR1_SAI1SEL 0x00300000U
AnnaBridge 126:abea610beb85 6362 #define RCC_DCKCFGR1_SAI1SEL_0 0x00100000U
AnnaBridge 126:abea610beb85 6363 #define RCC_DCKCFGR1_SAI1SEL_1 0x00200000U
AnnaBridge 126:abea610beb85 6364
AnnaBridge 126:abea610beb85 6365 #define RCC_DCKCFGR1_SAI2SEL 0x00C00000U
AnnaBridge 126:abea610beb85 6366 #define RCC_DCKCFGR1_SAI2SEL_0 0x00400000U
AnnaBridge 126:abea610beb85 6367 #define RCC_DCKCFGR1_SAI2SEL_1 0x00800000U
AnnaBridge 126:abea610beb85 6368
AnnaBridge 126:abea610beb85 6369 #define RCC_DCKCFGR1_TIMPRE 0x01000000U
AnnaBridge 126:abea610beb85 6370 #define RCC_DCKCFGR1_DFSDM1SEL 0x02000000U
AnnaBridge 126:abea610beb85 6371 #define RCC_DCKCFGR1_ADFSDM1SEL 0x04000000U
AnnaBridge 126:abea610beb85 6372
AnnaBridge 126:abea610beb85 6373 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
AnnaBridge 126:abea610beb85 6374 #define RCC_DCKCFGR2_USART1SEL 0x00000003U
AnnaBridge 126:abea610beb85 6375 #define RCC_DCKCFGR2_USART1SEL_0 0x00000001U
AnnaBridge 126:abea610beb85 6376 #define RCC_DCKCFGR2_USART1SEL_1 0x00000002U
AnnaBridge 126:abea610beb85 6377 #define RCC_DCKCFGR2_USART2SEL 0x0000000CU
AnnaBridge 126:abea610beb85 6378 #define RCC_DCKCFGR2_USART2SEL_0 0x00000004U
AnnaBridge 126:abea610beb85 6379 #define RCC_DCKCFGR2_USART2SEL_1 0x00000008U
AnnaBridge 126:abea610beb85 6380 #define RCC_DCKCFGR2_USART3SEL 0x00000030U
AnnaBridge 126:abea610beb85 6381 #define RCC_DCKCFGR2_USART3SEL_0 0x00000010U
AnnaBridge 126:abea610beb85 6382 #define RCC_DCKCFGR2_USART3SEL_1 0x00000020U
AnnaBridge 126:abea610beb85 6383 #define RCC_DCKCFGR2_UART4SEL 0x000000C0U
AnnaBridge 126:abea610beb85 6384 #define RCC_DCKCFGR2_UART4SEL_0 0x00000040U
AnnaBridge 126:abea610beb85 6385 #define RCC_DCKCFGR2_UART4SEL_1 0x00000080U
AnnaBridge 126:abea610beb85 6386 #define RCC_DCKCFGR2_UART5SEL 0x00000300U
AnnaBridge 126:abea610beb85 6387 #define RCC_DCKCFGR2_UART5SEL_0 0x00000100U
AnnaBridge 126:abea610beb85 6388 #define RCC_DCKCFGR2_UART5SEL_1 0x00000200U
AnnaBridge 126:abea610beb85 6389 #define RCC_DCKCFGR2_USART6SEL 0x00000C00U
AnnaBridge 126:abea610beb85 6390 #define RCC_DCKCFGR2_USART6SEL_0 0x00000400U
AnnaBridge 126:abea610beb85 6391 #define RCC_DCKCFGR2_USART6SEL_1 0x00000800U
AnnaBridge 126:abea610beb85 6392 #define RCC_DCKCFGR2_UART7SEL 0x00003000U
AnnaBridge 126:abea610beb85 6393 #define RCC_DCKCFGR2_UART7SEL_0 0x00001000U
AnnaBridge 126:abea610beb85 6394 #define RCC_DCKCFGR2_UART7SEL_1 0x00002000U
AnnaBridge 126:abea610beb85 6395 #define RCC_DCKCFGR2_UART8SEL 0x0000C000U
AnnaBridge 126:abea610beb85 6396 #define RCC_DCKCFGR2_UART8SEL_0 0x00004000U
AnnaBridge 126:abea610beb85 6397 #define RCC_DCKCFGR2_UART8SEL_1 0x00008000U
AnnaBridge 126:abea610beb85 6398 #define RCC_DCKCFGR2_I2C1SEL 0x00030000U
AnnaBridge 126:abea610beb85 6399 #define RCC_DCKCFGR2_I2C1SEL_0 0x00010000U
AnnaBridge 126:abea610beb85 6400 #define RCC_DCKCFGR2_I2C1SEL_1 0x00020000U
AnnaBridge 126:abea610beb85 6401 #define RCC_DCKCFGR2_I2C2SEL 0x000C0000U
AnnaBridge 126:abea610beb85 6402 #define RCC_DCKCFGR2_I2C2SEL_0 0x00040000U
AnnaBridge 126:abea610beb85 6403 #define RCC_DCKCFGR2_I2C2SEL_1 0x00080000U
AnnaBridge 126:abea610beb85 6404 #define RCC_DCKCFGR2_I2C3SEL 0x00300000U
AnnaBridge 126:abea610beb85 6405 #define RCC_DCKCFGR2_I2C3SEL_0 0x00100000U
AnnaBridge 126:abea610beb85 6406 #define RCC_DCKCFGR2_I2C3SEL_1 0x00200000U
AnnaBridge 126:abea610beb85 6407 #define RCC_DCKCFGR2_I2C4SEL 0x00C00000U
AnnaBridge 126:abea610beb85 6408 #define RCC_DCKCFGR2_I2C4SEL_0 0x00400000U
AnnaBridge 126:abea610beb85 6409 #define RCC_DCKCFGR2_I2C4SEL_1 0x00800000U
AnnaBridge 126:abea610beb85 6410 #define RCC_DCKCFGR2_LPTIM1SEL 0x03000000U
AnnaBridge 126:abea610beb85 6411 #define RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U
AnnaBridge 126:abea610beb85 6412 #define RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U
AnnaBridge 126:abea610beb85 6413 #define RCC_DCKCFGR2_CECSEL 0x04000000U
AnnaBridge 126:abea610beb85 6414 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
AnnaBridge 126:abea610beb85 6415 #define RCC_DCKCFGR2_SDMMC1SEL 0x10000000U
AnnaBridge 126:abea610beb85 6416 #define RCC_DCKCFGR2_SDMMC2SEL 0x20000000U
AnnaBridge 126:abea610beb85 6417 #define RCC_DCKCFGR2_DSISEL 0x40000000U
AnnaBridge 126:abea610beb85 6418
AnnaBridge 126:abea610beb85 6419 /******************************************************************************/
AnnaBridge 126:abea610beb85 6420 /* */
AnnaBridge 126:abea610beb85 6421 /* RNG */
AnnaBridge 126:abea610beb85 6422 /* */
AnnaBridge 126:abea610beb85 6423 /******************************************************************************/
AnnaBridge 126:abea610beb85 6424 /******************** Bits definition for RNG_CR register *******************/
AnnaBridge 126:abea610beb85 6425 #define RNG_CR_RNGEN 0x00000004U
AnnaBridge 126:abea610beb85 6426 #define RNG_CR_IE 0x00000008U
AnnaBridge 126:abea610beb85 6427
AnnaBridge 126:abea610beb85 6428 /******************** Bits definition for RNG_SR register *******************/
AnnaBridge 126:abea610beb85 6429 #define RNG_SR_DRDY 0x00000001U
AnnaBridge 126:abea610beb85 6430 #define RNG_SR_CECS 0x00000002U
AnnaBridge 126:abea610beb85 6431 #define RNG_SR_SECS 0x00000004U
AnnaBridge 126:abea610beb85 6432 #define RNG_SR_CEIS 0x00000020U
AnnaBridge 126:abea610beb85 6433 #define RNG_SR_SEIS 0x00000040U
AnnaBridge 126:abea610beb85 6434
AnnaBridge 126:abea610beb85 6435 /******************************************************************************/
AnnaBridge 126:abea610beb85 6436 /* */
AnnaBridge 126:abea610beb85 6437 /* Real-Time Clock (RTC) */
AnnaBridge 126:abea610beb85 6438 /* */
AnnaBridge 126:abea610beb85 6439 /******************************************************************************/
AnnaBridge 126:abea610beb85 6440 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 126:abea610beb85 6441 #define RTC_TR_PM 0x00400000U
AnnaBridge 126:abea610beb85 6442 #define RTC_TR_HT 0x00300000U
AnnaBridge 126:abea610beb85 6443 #define RTC_TR_HT_0 0x00100000U
AnnaBridge 126:abea610beb85 6444 #define RTC_TR_HT_1 0x00200000U
AnnaBridge 126:abea610beb85 6445 #define RTC_TR_HU 0x000F0000U
AnnaBridge 126:abea610beb85 6446 #define RTC_TR_HU_0 0x00010000U
AnnaBridge 126:abea610beb85 6447 #define RTC_TR_HU_1 0x00020000U
AnnaBridge 126:abea610beb85 6448 #define RTC_TR_HU_2 0x00040000U
AnnaBridge 126:abea610beb85 6449 #define RTC_TR_HU_3 0x00080000U
AnnaBridge 126:abea610beb85 6450 #define RTC_TR_MNT 0x00007000U
AnnaBridge 126:abea610beb85 6451 #define RTC_TR_MNT_0 0x00001000U
AnnaBridge 126:abea610beb85 6452 #define RTC_TR_MNT_1 0x00002000U
AnnaBridge 126:abea610beb85 6453 #define RTC_TR_MNT_2 0x00004000U
AnnaBridge 126:abea610beb85 6454 #define RTC_TR_MNU 0x00000F00U
AnnaBridge 126:abea610beb85 6455 #define RTC_TR_MNU_0 0x00000100U
AnnaBridge 126:abea610beb85 6456 #define RTC_TR_MNU_1 0x00000200U
AnnaBridge 126:abea610beb85 6457 #define RTC_TR_MNU_2 0x00000400U
AnnaBridge 126:abea610beb85 6458 #define RTC_TR_MNU_3 0x00000800U
AnnaBridge 126:abea610beb85 6459 #define RTC_TR_ST 0x00000070U
AnnaBridge 126:abea610beb85 6460 #define RTC_TR_ST_0 0x00000010U
AnnaBridge 126:abea610beb85 6461 #define RTC_TR_ST_1 0x00000020U
AnnaBridge 126:abea610beb85 6462 #define RTC_TR_ST_2 0x00000040U
AnnaBridge 126:abea610beb85 6463 #define RTC_TR_SU 0x0000000FU
AnnaBridge 126:abea610beb85 6464 #define RTC_TR_SU_0 0x00000001U
AnnaBridge 126:abea610beb85 6465 #define RTC_TR_SU_1 0x00000002U
AnnaBridge 126:abea610beb85 6466 #define RTC_TR_SU_2 0x00000004U
AnnaBridge 126:abea610beb85 6467 #define RTC_TR_SU_3 0x00000008U
AnnaBridge 126:abea610beb85 6468
AnnaBridge 126:abea610beb85 6469 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 126:abea610beb85 6470 #define RTC_DR_YT 0x00F00000U
AnnaBridge 126:abea610beb85 6471 #define RTC_DR_YT_0 0x00100000U
AnnaBridge 126:abea610beb85 6472 #define RTC_DR_YT_1 0x00200000U
AnnaBridge 126:abea610beb85 6473 #define RTC_DR_YT_2 0x00400000U
AnnaBridge 126:abea610beb85 6474 #define RTC_DR_YT_3 0x00800000U
AnnaBridge 126:abea610beb85 6475 #define RTC_DR_YU 0x000F0000U
AnnaBridge 126:abea610beb85 6476 #define RTC_DR_YU_0 0x00010000U
AnnaBridge 126:abea610beb85 6477 #define RTC_DR_YU_1 0x00020000U
AnnaBridge 126:abea610beb85 6478 #define RTC_DR_YU_2 0x00040000U
AnnaBridge 126:abea610beb85 6479 #define RTC_DR_YU_3 0x00080000U
AnnaBridge 126:abea610beb85 6480 #define RTC_DR_WDU 0x0000E000U
AnnaBridge 126:abea610beb85 6481 #define RTC_DR_WDU_0 0x00002000U
AnnaBridge 126:abea610beb85 6482 #define RTC_DR_WDU_1 0x00004000U
AnnaBridge 126:abea610beb85 6483 #define RTC_DR_WDU_2 0x00008000U
AnnaBridge 126:abea610beb85 6484 #define RTC_DR_MT 0x00001000U
AnnaBridge 126:abea610beb85 6485 #define RTC_DR_MU 0x00000F00U
AnnaBridge 126:abea610beb85 6486 #define RTC_DR_MU_0 0x00000100U
AnnaBridge 126:abea610beb85 6487 #define RTC_DR_MU_1 0x00000200U
AnnaBridge 126:abea610beb85 6488 #define RTC_DR_MU_2 0x00000400U
AnnaBridge 126:abea610beb85 6489 #define RTC_DR_MU_3 0x00000800U
AnnaBridge 126:abea610beb85 6490 #define RTC_DR_DT 0x00000030U
AnnaBridge 126:abea610beb85 6491 #define RTC_DR_DT_0 0x00000010U
AnnaBridge 126:abea610beb85 6492 #define RTC_DR_DT_1 0x00000020U
AnnaBridge 126:abea610beb85 6493 #define RTC_DR_DU 0x0000000FU
AnnaBridge 126:abea610beb85 6494 #define RTC_DR_DU_0 0x00000001U
AnnaBridge 126:abea610beb85 6495 #define RTC_DR_DU_1 0x00000002U
AnnaBridge 126:abea610beb85 6496 #define RTC_DR_DU_2 0x00000004U
AnnaBridge 126:abea610beb85 6497 #define RTC_DR_DU_3 0x00000008U
AnnaBridge 126:abea610beb85 6498
AnnaBridge 126:abea610beb85 6499 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 126:abea610beb85 6500 #define RTC_CR_ITSE 0x01000000U
AnnaBridge 126:abea610beb85 6501 #define RTC_CR_COE 0x00800000U
AnnaBridge 126:abea610beb85 6502 #define RTC_CR_OSEL 0x00600000U
AnnaBridge 126:abea610beb85 6503 #define RTC_CR_OSEL_0 0x00200000U
AnnaBridge 126:abea610beb85 6504 #define RTC_CR_OSEL_1 0x00400000U
AnnaBridge 126:abea610beb85 6505 #define RTC_CR_POL 0x00100000U
AnnaBridge 126:abea610beb85 6506 #define RTC_CR_COSEL 0x00080000U
AnnaBridge 126:abea610beb85 6507 #define RTC_CR_BCK 0x00040000U
AnnaBridge 126:abea610beb85 6508 #define RTC_CR_SUB1H 0x00020000U
AnnaBridge 126:abea610beb85 6509 #define RTC_CR_ADD1H 0x00010000U
AnnaBridge 126:abea610beb85 6510 #define RTC_CR_TSIE 0x00008000U
AnnaBridge 126:abea610beb85 6511 #define RTC_CR_WUTIE 0x00004000U
AnnaBridge 126:abea610beb85 6512 #define RTC_CR_ALRBIE 0x00002000U
AnnaBridge 126:abea610beb85 6513 #define RTC_CR_ALRAIE 0x00001000U
AnnaBridge 126:abea610beb85 6514 #define RTC_CR_TSE 0x00000800U
AnnaBridge 126:abea610beb85 6515 #define RTC_CR_WUTE 0x00000400U
AnnaBridge 126:abea610beb85 6516 #define RTC_CR_ALRBE 0x00000200U
AnnaBridge 126:abea610beb85 6517 #define RTC_CR_ALRAE 0x00000100U
AnnaBridge 126:abea610beb85 6518 #define RTC_CR_FMT 0x00000040U
AnnaBridge 126:abea610beb85 6519 #define RTC_CR_BYPSHAD 0x00000020U
AnnaBridge 126:abea610beb85 6520 #define RTC_CR_REFCKON 0x00000010U
AnnaBridge 126:abea610beb85 6521 #define RTC_CR_TSEDGE 0x00000008U
AnnaBridge 126:abea610beb85 6522 #define RTC_CR_WUCKSEL 0x00000007U
AnnaBridge 126:abea610beb85 6523 #define RTC_CR_WUCKSEL_0 0x00000001U
AnnaBridge 126:abea610beb85 6524 #define RTC_CR_WUCKSEL_1 0x00000002U
AnnaBridge 126:abea610beb85 6525 #define RTC_CR_WUCKSEL_2 0x00000004U
AnnaBridge 126:abea610beb85 6526
AnnaBridge 126:abea610beb85 6527 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 126:abea610beb85 6528 #define RTC_ISR_ITSF 0x00020000U
AnnaBridge 126:abea610beb85 6529 #define RTC_ISR_RECALPF 0x00010000U
AnnaBridge 126:abea610beb85 6530 #define RTC_ISR_TAMP3F 0x00008000U
AnnaBridge 126:abea610beb85 6531 #define RTC_ISR_TAMP2F 0x00004000U
AnnaBridge 126:abea610beb85 6532 #define RTC_ISR_TAMP1F 0x00002000U
AnnaBridge 126:abea610beb85 6533 #define RTC_ISR_TSOVF 0x00001000U
AnnaBridge 126:abea610beb85 6534 #define RTC_ISR_TSF 0x00000800U
AnnaBridge 126:abea610beb85 6535 #define RTC_ISR_WUTF 0x00000400U
AnnaBridge 126:abea610beb85 6536 #define RTC_ISR_ALRBF 0x00000200U
AnnaBridge 126:abea610beb85 6537 #define RTC_ISR_ALRAF 0x00000100U
AnnaBridge 126:abea610beb85 6538 #define RTC_ISR_INIT 0x00000080U
AnnaBridge 126:abea610beb85 6539 #define RTC_ISR_INITF 0x00000040U
AnnaBridge 126:abea610beb85 6540 #define RTC_ISR_RSF 0x00000020U
AnnaBridge 126:abea610beb85 6541 #define RTC_ISR_INITS 0x00000010U
AnnaBridge 126:abea610beb85 6542 #define RTC_ISR_SHPF 0x00000008U
AnnaBridge 126:abea610beb85 6543 #define RTC_ISR_WUTWF 0x00000004U
AnnaBridge 126:abea610beb85 6544 #define RTC_ISR_ALRBWF 0x00000002U
AnnaBridge 126:abea610beb85 6545 #define RTC_ISR_ALRAWF 0x00000001U
AnnaBridge 126:abea610beb85 6546
AnnaBridge 126:abea610beb85 6547 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 126:abea610beb85 6548 #define RTC_PRER_PREDIV_A 0x007F0000U
AnnaBridge 126:abea610beb85 6549 #define RTC_PRER_PREDIV_S 0x00007FFFU
AnnaBridge 126:abea610beb85 6550
AnnaBridge 126:abea610beb85 6551 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 126:abea610beb85 6552 #define RTC_WUTR_WUT 0x0000FFFFU
AnnaBridge 126:abea610beb85 6553
AnnaBridge 126:abea610beb85 6554 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 126:abea610beb85 6555 #define RTC_ALRMAR_MSK4 0x80000000U
AnnaBridge 126:abea610beb85 6556 #define RTC_ALRMAR_WDSEL 0x40000000U
AnnaBridge 126:abea610beb85 6557 #define RTC_ALRMAR_DT 0x30000000U
AnnaBridge 126:abea610beb85 6558 #define RTC_ALRMAR_DT_0 0x10000000U
AnnaBridge 126:abea610beb85 6559 #define RTC_ALRMAR_DT_1 0x20000000U
AnnaBridge 126:abea610beb85 6560 #define RTC_ALRMAR_DU 0x0F000000U
AnnaBridge 126:abea610beb85 6561 #define RTC_ALRMAR_DU_0 0x01000000U
AnnaBridge 126:abea610beb85 6562 #define RTC_ALRMAR_DU_1 0x02000000U
AnnaBridge 126:abea610beb85 6563 #define RTC_ALRMAR_DU_2 0x04000000U
AnnaBridge 126:abea610beb85 6564 #define RTC_ALRMAR_DU_3 0x08000000U
AnnaBridge 126:abea610beb85 6565 #define RTC_ALRMAR_MSK3 0x00800000U
AnnaBridge 126:abea610beb85 6566 #define RTC_ALRMAR_PM 0x00400000U
AnnaBridge 126:abea610beb85 6567 #define RTC_ALRMAR_HT 0x00300000U
AnnaBridge 126:abea610beb85 6568 #define RTC_ALRMAR_HT_0 0x00100000U
AnnaBridge 126:abea610beb85 6569 #define RTC_ALRMAR_HT_1 0x00200000U
AnnaBridge 126:abea610beb85 6570 #define RTC_ALRMAR_HU 0x000F0000U
AnnaBridge 126:abea610beb85 6571 #define RTC_ALRMAR_HU_0 0x00010000U
AnnaBridge 126:abea610beb85 6572 #define RTC_ALRMAR_HU_1 0x00020000U
AnnaBridge 126:abea610beb85 6573 #define RTC_ALRMAR_HU_2 0x00040000U
AnnaBridge 126:abea610beb85 6574 #define RTC_ALRMAR_HU_3 0x00080000U
AnnaBridge 126:abea610beb85 6575 #define RTC_ALRMAR_MSK2 0x00008000U
AnnaBridge 126:abea610beb85 6576 #define RTC_ALRMAR_MNT 0x00007000U
AnnaBridge 126:abea610beb85 6577 #define RTC_ALRMAR_MNT_0 0x00001000U
AnnaBridge 126:abea610beb85 6578 #define RTC_ALRMAR_MNT_1 0x00002000U
AnnaBridge 126:abea610beb85 6579 #define RTC_ALRMAR_MNT_2 0x00004000U
AnnaBridge 126:abea610beb85 6580 #define RTC_ALRMAR_MNU 0x00000F00U
AnnaBridge 126:abea610beb85 6581 #define RTC_ALRMAR_MNU_0 0x00000100U
AnnaBridge 126:abea610beb85 6582 #define RTC_ALRMAR_MNU_1 0x00000200U
AnnaBridge 126:abea610beb85 6583 #define RTC_ALRMAR_MNU_2 0x00000400U
AnnaBridge 126:abea610beb85 6584 #define RTC_ALRMAR_MNU_3 0x00000800U
AnnaBridge 126:abea610beb85 6585 #define RTC_ALRMAR_MSK1 0x00000080U
AnnaBridge 126:abea610beb85 6586 #define RTC_ALRMAR_ST 0x00000070U
AnnaBridge 126:abea610beb85 6587 #define RTC_ALRMAR_ST_0 0x00000010U
AnnaBridge 126:abea610beb85 6588 #define RTC_ALRMAR_ST_1 0x00000020U
AnnaBridge 126:abea610beb85 6589 #define RTC_ALRMAR_ST_2 0x00000040U
AnnaBridge 126:abea610beb85 6590 #define RTC_ALRMAR_SU 0x0000000FU
AnnaBridge 126:abea610beb85 6591 #define RTC_ALRMAR_SU_0 0x00000001U
AnnaBridge 126:abea610beb85 6592 #define RTC_ALRMAR_SU_1 0x00000002U
AnnaBridge 126:abea610beb85 6593 #define RTC_ALRMAR_SU_2 0x00000004U
AnnaBridge 126:abea610beb85 6594 #define RTC_ALRMAR_SU_3 0x00000008U
AnnaBridge 126:abea610beb85 6595
AnnaBridge 126:abea610beb85 6596 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 126:abea610beb85 6597 #define RTC_ALRMBR_MSK4 0x80000000U
AnnaBridge 126:abea610beb85 6598 #define RTC_ALRMBR_WDSEL 0x40000000U
AnnaBridge 126:abea610beb85 6599 #define RTC_ALRMBR_DT 0x30000000U
AnnaBridge 126:abea610beb85 6600 #define RTC_ALRMBR_DT_0 0x10000000U
AnnaBridge 126:abea610beb85 6601 #define RTC_ALRMBR_DT_1 0x20000000U
AnnaBridge 126:abea610beb85 6602 #define RTC_ALRMBR_DU 0x0F000000U
AnnaBridge 126:abea610beb85 6603 #define RTC_ALRMBR_DU_0 0x01000000U
AnnaBridge 126:abea610beb85 6604 #define RTC_ALRMBR_DU_1 0x02000000U
AnnaBridge 126:abea610beb85 6605 #define RTC_ALRMBR_DU_2 0x04000000U
AnnaBridge 126:abea610beb85 6606 #define RTC_ALRMBR_DU_3 0x08000000U
AnnaBridge 126:abea610beb85 6607 #define RTC_ALRMBR_MSK3 0x00800000U
AnnaBridge 126:abea610beb85 6608 #define RTC_ALRMBR_PM 0x00400000U
AnnaBridge 126:abea610beb85 6609 #define RTC_ALRMBR_HT 0x00300000U
AnnaBridge 126:abea610beb85 6610 #define RTC_ALRMBR_HT_0 0x00100000U
AnnaBridge 126:abea610beb85 6611 #define RTC_ALRMBR_HT_1 0x00200000U
AnnaBridge 126:abea610beb85 6612 #define RTC_ALRMBR_HU 0x000F0000U
AnnaBridge 126:abea610beb85 6613 #define RTC_ALRMBR_HU_0 0x00010000U
AnnaBridge 126:abea610beb85 6614 #define RTC_ALRMBR_HU_1 0x00020000U
AnnaBridge 126:abea610beb85 6615 #define RTC_ALRMBR_HU_2 0x00040000U
AnnaBridge 126:abea610beb85 6616 #define RTC_ALRMBR_HU_3 0x00080000U
AnnaBridge 126:abea610beb85 6617 #define RTC_ALRMBR_MSK2 0x00008000U
AnnaBridge 126:abea610beb85 6618 #define RTC_ALRMBR_MNT 0x00007000U
AnnaBridge 126:abea610beb85 6619 #define RTC_ALRMBR_MNT_0 0x00001000U
AnnaBridge 126:abea610beb85 6620 #define RTC_ALRMBR_MNT_1 0x00002000U
AnnaBridge 126:abea610beb85 6621 #define RTC_ALRMBR_MNT_2 0x00004000U
AnnaBridge 126:abea610beb85 6622 #define RTC_ALRMBR_MNU 0x00000F00U
AnnaBridge 126:abea610beb85 6623 #define RTC_ALRMBR_MNU_0 0x00000100U
AnnaBridge 126:abea610beb85 6624 #define RTC_ALRMBR_MNU_1 0x00000200U
AnnaBridge 126:abea610beb85 6625 #define RTC_ALRMBR_MNU_2 0x00000400U
AnnaBridge 126:abea610beb85 6626 #define RTC_ALRMBR_MNU_3 0x00000800U
AnnaBridge 126:abea610beb85 6627 #define RTC_ALRMBR_MSK1 0x00000080U
AnnaBridge 126:abea610beb85 6628 #define RTC_ALRMBR_ST 0x00000070U
AnnaBridge 126:abea610beb85 6629 #define RTC_ALRMBR_ST_0 0x00000010U
AnnaBridge 126:abea610beb85 6630 #define RTC_ALRMBR_ST_1 0x00000020U
AnnaBridge 126:abea610beb85 6631 #define RTC_ALRMBR_ST_2 0x00000040U
AnnaBridge 126:abea610beb85 6632 #define RTC_ALRMBR_SU 0x0000000FU
AnnaBridge 126:abea610beb85 6633 #define RTC_ALRMBR_SU_0 0x00000001U
AnnaBridge 126:abea610beb85 6634 #define RTC_ALRMBR_SU_1 0x00000002U
AnnaBridge 126:abea610beb85 6635 #define RTC_ALRMBR_SU_2 0x00000004U
AnnaBridge 126:abea610beb85 6636 #define RTC_ALRMBR_SU_3 0x00000008U
AnnaBridge 126:abea610beb85 6637
AnnaBridge 126:abea610beb85 6638 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 126:abea610beb85 6639 #define RTC_WPR_KEY 0x000000FFU
AnnaBridge 126:abea610beb85 6640
AnnaBridge 126:abea610beb85 6641 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 126:abea610beb85 6642 #define RTC_SSR_SS 0x0000FFFFU
AnnaBridge 126:abea610beb85 6643
AnnaBridge 126:abea610beb85 6644 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 126:abea610beb85 6645 #define RTC_SHIFTR_SUBFS 0x00007FFFU
AnnaBridge 126:abea610beb85 6646 #define RTC_SHIFTR_ADD1S 0x80000000U
AnnaBridge 126:abea610beb85 6647
AnnaBridge 126:abea610beb85 6648 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 126:abea610beb85 6649 #define RTC_TSTR_PM 0x00400000U
AnnaBridge 126:abea610beb85 6650 #define RTC_TSTR_HT 0x00300000U
AnnaBridge 126:abea610beb85 6651 #define RTC_TSTR_HT_0 0x00100000U
AnnaBridge 126:abea610beb85 6652 #define RTC_TSTR_HT_1 0x00200000U
AnnaBridge 126:abea610beb85 6653 #define RTC_TSTR_HU 0x000F0000U
AnnaBridge 126:abea610beb85 6654 #define RTC_TSTR_HU_0 0x00010000U
AnnaBridge 126:abea610beb85 6655 #define RTC_TSTR_HU_1 0x00020000U
AnnaBridge 126:abea610beb85 6656 #define RTC_TSTR_HU_2 0x00040000U
AnnaBridge 126:abea610beb85 6657 #define RTC_TSTR_HU_3 0x00080000U
AnnaBridge 126:abea610beb85 6658 #define RTC_TSTR_MNT 0x00007000U
AnnaBridge 126:abea610beb85 6659 #define RTC_TSTR_MNT_0 0x00001000U
AnnaBridge 126:abea610beb85 6660 #define RTC_TSTR_MNT_1 0x00002000U
AnnaBridge 126:abea610beb85 6661 #define RTC_TSTR_MNT_2 0x00004000U
AnnaBridge 126:abea610beb85 6662 #define RTC_TSTR_MNU 0x00000F00U
AnnaBridge 126:abea610beb85 6663 #define RTC_TSTR_MNU_0 0x00000100U
AnnaBridge 126:abea610beb85 6664 #define RTC_TSTR_MNU_1 0x00000200U
AnnaBridge 126:abea610beb85 6665 #define RTC_TSTR_MNU_2 0x00000400U
AnnaBridge 126:abea610beb85 6666 #define RTC_TSTR_MNU_3 0x00000800U
AnnaBridge 126:abea610beb85 6667 #define RTC_TSTR_ST 0x00000070U
AnnaBridge 126:abea610beb85 6668 #define RTC_TSTR_ST_0 0x00000010U
AnnaBridge 126:abea610beb85 6669 #define RTC_TSTR_ST_1 0x00000020U
AnnaBridge 126:abea610beb85 6670 #define RTC_TSTR_ST_2 0x00000040U
AnnaBridge 126:abea610beb85 6671 #define RTC_TSTR_SU 0x0000000FU
AnnaBridge 126:abea610beb85 6672 #define RTC_TSTR_SU_0 0x00000001U
AnnaBridge 126:abea610beb85 6673 #define RTC_TSTR_SU_1 0x00000002U
AnnaBridge 126:abea610beb85 6674 #define RTC_TSTR_SU_2 0x00000004U
AnnaBridge 126:abea610beb85 6675 #define RTC_TSTR_SU_3 0x00000008U
AnnaBridge 126:abea610beb85 6676
AnnaBridge 126:abea610beb85 6677 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 126:abea610beb85 6678 #define RTC_TSDR_WDU 0x0000E000U
AnnaBridge 126:abea610beb85 6679 #define RTC_TSDR_WDU_0 0x00002000U
AnnaBridge 126:abea610beb85 6680 #define RTC_TSDR_WDU_1 0x00004000U
AnnaBridge 126:abea610beb85 6681 #define RTC_TSDR_WDU_2 0x00008000U
AnnaBridge 126:abea610beb85 6682 #define RTC_TSDR_MT 0x00001000U
AnnaBridge 126:abea610beb85 6683 #define RTC_TSDR_MU 0x00000F00U
AnnaBridge 126:abea610beb85 6684 #define RTC_TSDR_MU_0 0x00000100U
AnnaBridge 126:abea610beb85 6685 #define RTC_TSDR_MU_1 0x00000200U
AnnaBridge 126:abea610beb85 6686 #define RTC_TSDR_MU_2 0x00000400U
AnnaBridge 126:abea610beb85 6687 #define RTC_TSDR_MU_3 0x00000800U
AnnaBridge 126:abea610beb85 6688 #define RTC_TSDR_DT 0x00000030U
AnnaBridge 126:abea610beb85 6689 #define RTC_TSDR_DT_0 0x00000010U
AnnaBridge 126:abea610beb85 6690 #define RTC_TSDR_DT_1 0x00000020U
AnnaBridge 126:abea610beb85 6691 #define RTC_TSDR_DU 0x0000000FU
AnnaBridge 126:abea610beb85 6692 #define RTC_TSDR_DU_0 0x00000001U
AnnaBridge 126:abea610beb85 6693 #define RTC_TSDR_DU_1 0x00000002U
AnnaBridge 126:abea610beb85 6694 #define RTC_TSDR_DU_2 0x00000004U
AnnaBridge 126:abea610beb85 6695 #define RTC_TSDR_DU_3 0x00000008U
AnnaBridge 126:abea610beb85 6696
AnnaBridge 126:abea610beb85 6697 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 126:abea610beb85 6698 #define RTC_TSSSR_SS 0x0000FFFFU
AnnaBridge 126:abea610beb85 6699
AnnaBridge 126:abea610beb85 6700 /******************** Bits definition for RTC_CAL register *****************/
AnnaBridge 126:abea610beb85 6701 #define RTC_CALR_CALP 0x00008000U
AnnaBridge 126:abea610beb85 6702 #define RTC_CALR_CALW8 0x00004000U
AnnaBridge 126:abea610beb85 6703 #define RTC_CALR_CALW16 0x00002000U
AnnaBridge 126:abea610beb85 6704 #define RTC_CALR_CALM 0x000001FFU
AnnaBridge 126:abea610beb85 6705 #define RTC_CALR_CALM_0 0x00000001U
AnnaBridge 126:abea610beb85 6706 #define RTC_CALR_CALM_1 0x00000002U
AnnaBridge 126:abea610beb85 6707 #define RTC_CALR_CALM_2 0x00000004U
AnnaBridge 126:abea610beb85 6708 #define RTC_CALR_CALM_3 0x00000008U
AnnaBridge 126:abea610beb85 6709 #define RTC_CALR_CALM_4 0x00000010U
AnnaBridge 126:abea610beb85 6710 #define RTC_CALR_CALM_5 0x00000020U
AnnaBridge 126:abea610beb85 6711 #define RTC_CALR_CALM_6 0x00000040U
AnnaBridge 126:abea610beb85 6712 #define RTC_CALR_CALM_7 0x00000080U
AnnaBridge 126:abea610beb85 6713 #define RTC_CALR_CALM_8 0x00000100U
AnnaBridge 126:abea610beb85 6714
AnnaBridge 126:abea610beb85 6715 /******************** Bits definition for RTC_TAMPCR register ****************/
AnnaBridge 126:abea610beb85 6716 #define RTC_TAMPCR_TAMP3MF 0x01000000U
AnnaBridge 126:abea610beb85 6717 #define RTC_TAMPCR_TAMP3NOERASE 0x00800000U
AnnaBridge 126:abea610beb85 6718 #define RTC_TAMPCR_TAMP3IE 0x00400000U
AnnaBridge 126:abea610beb85 6719 #define RTC_TAMPCR_TAMP2MF 0x00200000U
AnnaBridge 126:abea610beb85 6720 #define RTC_TAMPCR_TAMP2NOERASE 0x00100000U
AnnaBridge 126:abea610beb85 6721 #define RTC_TAMPCR_TAMP2IE 0x00080000U
AnnaBridge 126:abea610beb85 6722 #define RTC_TAMPCR_TAMP1MF 0x00040000U
AnnaBridge 126:abea610beb85 6723 #define RTC_TAMPCR_TAMP1NOERASE 0x00020000U
AnnaBridge 126:abea610beb85 6724 #define RTC_TAMPCR_TAMP1IE 0x00010000U
AnnaBridge 126:abea610beb85 6725 #define RTC_TAMPCR_TAMPPUDIS 0x00008000U
AnnaBridge 126:abea610beb85 6726 #define RTC_TAMPCR_TAMPPRCH 0x00006000U
AnnaBridge 126:abea610beb85 6727 #define RTC_TAMPCR_TAMPPRCH_0 0x00002000U
AnnaBridge 126:abea610beb85 6728 #define RTC_TAMPCR_TAMPPRCH_1 0x00004000U
AnnaBridge 126:abea610beb85 6729 #define RTC_TAMPCR_TAMPFLT 0x00001800U
AnnaBridge 126:abea610beb85 6730 #define RTC_TAMPCR_TAMPFLT_0 0x00000800U
AnnaBridge 126:abea610beb85 6731 #define RTC_TAMPCR_TAMPFLT_1 0x00001000U
AnnaBridge 126:abea610beb85 6732 #define RTC_TAMPCR_TAMPFREQ 0x00000700U
AnnaBridge 126:abea610beb85 6733 #define RTC_TAMPCR_TAMPFREQ_0 0x00000100U
AnnaBridge 126:abea610beb85 6734 #define RTC_TAMPCR_TAMPFREQ_1 0x00000200U
AnnaBridge 126:abea610beb85 6735 #define RTC_TAMPCR_TAMPFREQ_2 0x00000400U
AnnaBridge 126:abea610beb85 6736 #define RTC_TAMPCR_TAMPTS 0x00000080U
AnnaBridge 126:abea610beb85 6737 #define RTC_TAMPCR_TAMP3TRG 0x00000040U
AnnaBridge 126:abea610beb85 6738 #define RTC_TAMPCR_TAMP3E 0x00000020U
AnnaBridge 126:abea610beb85 6739 #define RTC_TAMPCR_TAMP2TRG 0x00000010U
AnnaBridge 126:abea610beb85 6740 #define RTC_TAMPCR_TAMP2E 0x00000008U
AnnaBridge 126:abea610beb85 6741 #define RTC_TAMPCR_TAMPIE 0x00000004U
AnnaBridge 126:abea610beb85 6742 #define RTC_TAMPCR_TAMP1TRG 0x00000002U
AnnaBridge 126:abea610beb85 6743 #define RTC_TAMPCR_TAMP1E 0x00000001U
AnnaBridge 126:abea610beb85 6744
AnnaBridge 126:abea610beb85 6745
AnnaBridge 126:abea610beb85 6746 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 126:abea610beb85 6747 #define RTC_ALRMASSR_MASKSS 0x0F000000U
AnnaBridge 126:abea610beb85 6748 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
AnnaBridge 126:abea610beb85 6749 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
AnnaBridge 126:abea610beb85 6750 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
AnnaBridge 126:abea610beb85 6751 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
AnnaBridge 126:abea610beb85 6752 #define RTC_ALRMASSR_SS 0x00007FFFU
AnnaBridge 126:abea610beb85 6753
AnnaBridge 126:abea610beb85 6754 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 126:abea610beb85 6755 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
AnnaBridge 126:abea610beb85 6756 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
AnnaBridge 126:abea610beb85 6757 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
AnnaBridge 126:abea610beb85 6758 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
AnnaBridge 126:abea610beb85 6759 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
AnnaBridge 126:abea610beb85 6760 #define RTC_ALRMBSSR_SS 0x00007FFFU
AnnaBridge 126:abea610beb85 6761
AnnaBridge 126:abea610beb85 6762 /******************** Bits definition for RTC_OR register ****************/
AnnaBridge 126:abea610beb85 6763 #define RTC_OR_TSINSEL 0x00000006U
AnnaBridge 126:abea610beb85 6764 #define RTC_OR_TSINSEL_0 0x00000002U
AnnaBridge 126:abea610beb85 6765 #define RTC_OR_TSINSEL_1 0x00000004U
AnnaBridge 126:abea610beb85 6766 #define RTC_OR_ALARMTYPE 0x00000008U
AnnaBridge 126:abea610beb85 6767
AnnaBridge 126:abea610beb85 6768 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 126:abea610beb85 6769 #define RTC_BKP0R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6770
AnnaBridge 126:abea610beb85 6771 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 126:abea610beb85 6772 #define RTC_BKP1R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6773
AnnaBridge 126:abea610beb85 6774 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 126:abea610beb85 6775 #define RTC_BKP2R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6776
AnnaBridge 126:abea610beb85 6777 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 126:abea610beb85 6778 #define RTC_BKP3R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6779
AnnaBridge 126:abea610beb85 6780 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 126:abea610beb85 6781 #define RTC_BKP4R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6782
AnnaBridge 126:abea610beb85 6783 /******************** Bits definition for RTC_BKP5R register ****************/
AnnaBridge 126:abea610beb85 6784 #define RTC_BKP5R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6785
AnnaBridge 126:abea610beb85 6786 /******************** Bits definition for RTC_BKP6R register ****************/
AnnaBridge 126:abea610beb85 6787 #define RTC_BKP6R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6788
AnnaBridge 126:abea610beb85 6789 /******************** Bits definition for RTC_BKP7R register ****************/
AnnaBridge 126:abea610beb85 6790 #define RTC_BKP7R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6791
AnnaBridge 126:abea610beb85 6792 /******************** Bits definition for RTC_BKP8R register ****************/
AnnaBridge 126:abea610beb85 6793 #define RTC_BKP8R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6794
AnnaBridge 126:abea610beb85 6795 /******************** Bits definition for RTC_BKP9R register ****************/
AnnaBridge 126:abea610beb85 6796 #define RTC_BKP9R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6797
AnnaBridge 126:abea610beb85 6798 /******************** Bits definition for RTC_BKP10R register ***************/
AnnaBridge 126:abea610beb85 6799 #define RTC_BKP10R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6800
AnnaBridge 126:abea610beb85 6801 /******************** Bits definition for RTC_BKP11R register ***************/
AnnaBridge 126:abea610beb85 6802 #define RTC_BKP11R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6803
AnnaBridge 126:abea610beb85 6804 /******************** Bits definition for RTC_BKP12R register ***************/
AnnaBridge 126:abea610beb85 6805 #define RTC_BKP12R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6806
AnnaBridge 126:abea610beb85 6807 /******************** Bits definition for RTC_BKP13R register ***************/
AnnaBridge 126:abea610beb85 6808 #define RTC_BKP13R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6809
AnnaBridge 126:abea610beb85 6810 /******************** Bits definition for RTC_BKP14R register ***************/
AnnaBridge 126:abea610beb85 6811 #define RTC_BKP14R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6812
AnnaBridge 126:abea610beb85 6813 /******************** Bits definition for RTC_BKP15R register ***************/
AnnaBridge 126:abea610beb85 6814 #define RTC_BKP15R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6815
AnnaBridge 126:abea610beb85 6816 /******************** Bits definition for RTC_BKP16R register ***************/
AnnaBridge 126:abea610beb85 6817 #define RTC_BKP16R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6818
AnnaBridge 126:abea610beb85 6819 /******************** Bits definition for RTC_BKP17R register ***************/
AnnaBridge 126:abea610beb85 6820 #define RTC_BKP17R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6821
AnnaBridge 126:abea610beb85 6822 /******************** Bits definition for RTC_BKP18R register ***************/
AnnaBridge 126:abea610beb85 6823 #define RTC_BKP18R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6824
AnnaBridge 126:abea610beb85 6825 /******************** Bits definition for RTC_BKP19R register ***************/
AnnaBridge 126:abea610beb85 6826 #define RTC_BKP19R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6827
AnnaBridge 126:abea610beb85 6828 /******************** Bits definition for RTC_BKP20R register ***************/
AnnaBridge 126:abea610beb85 6829 #define RTC_BKP20R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6830
AnnaBridge 126:abea610beb85 6831 /******************** Bits definition for RTC_BKP21R register ***************/
AnnaBridge 126:abea610beb85 6832 #define RTC_BKP21R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6833
AnnaBridge 126:abea610beb85 6834 /******************** Bits definition for RTC_BKP22R register ***************/
AnnaBridge 126:abea610beb85 6835 #define RTC_BKP22R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6836
AnnaBridge 126:abea610beb85 6837 /******************** Bits definition for RTC_BKP23R register ***************/
AnnaBridge 126:abea610beb85 6838 #define RTC_BKP23R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6839
AnnaBridge 126:abea610beb85 6840 /******************** Bits definition for RTC_BKP24R register ***************/
AnnaBridge 126:abea610beb85 6841 #define RTC_BKP24R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6842
AnnaBridge 126:abea610beb85 6843 /******************** Bits definition for RTC_BKP25R register ***************/
AnnaBridge 126:abea610beb85 6844 #define RTC_BKP25R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6845
AnnaBridge 126:abea610beb85 6846 /******************** Bits definition for RTC_BKP26R register ***************/
AnnaBridge 126:abea610beb85 6847 #define RTC_BKP26R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6848
AnnaBridge 126:abea610beb85 6849 /******************** Bits definition for RTC_BKP27R register ***************/
AnnaBridge 126:abea610beb85 6850 #define RTC_BKP27R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6851
AnnaBridge 126:abea610beb85 6852 /******************** Bits definition for RTC_BKP28R register ***************/
AnnaBridge 126:abea610beb85 6853 #define RTC_BKP28R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6854
AnnaBridge 126:abea610beb85 6855 /******************** Bits definition for RTC_BKP29R register ***************/
AnnaBridge 126:abea610beb85 6856 #define RTC_BKP29R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6857
AnnaBridge 126:abea610beb85 6858 /******************** Bits definition for RTC_BKP30R register ***************/
AnnaBridge 126:abea610beb85 6859 #define RTC_BKP30R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6860
AnnaBridge 126:abea610beb85 6861 /******************** Bits definition for RTC_BKP31R register ***************/
AnnaBridge 126:abea610beb85 6862 #define RTC_BKP31R 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 6863
AnnaBridge 126:abea610beb85 6864 /******************** Number of backup registers ******************************/
AnnaBridge 126:abea610beb85 6865 #define RTC_BKP_NUMBER 0x00000020U
AnnaBridge 126:abea610beb85 6866
AnnaBridge 126:abea610beb85 6867
AnnaBridge 126:abea610beb85 6868 /******************************************************************************/
AnnaBridge 126:abea610beb85 6869 /* */
AnnaBridge 126:abea610beb85 6870 /* Serial Audio Interface */
AnnaBridge 126:abea610beb85 6871 /* */
AnnaBridge 126:abea610beb85 6872 /******************************************************************************/
AnnaBridge 126:abea610beb85 6873 /******************** Bit definition for SAI_GCR register *******************/
AnnaBridge 126:abea610beb85 6874 #define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
AnnaBridge 126:abea610beb85 6875 #define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6876 #define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6877
AnnaBridge 126:abea610beb85 6878 #define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
AnnaBridge 126:abea610beb85 6879 #define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6880 #define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6881
AnnaBridge 126:abea610beb85 6882 /******************* Bit definition for SAI_xCR1 register *******************/
AnnaBridge 126:abea610beb85 6883 #define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
AnnaBridge 126:abea610beb85 6884 #define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6885 #define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6886
AnnaBridge 126:abea610beb85 6887 #define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
AnnaBridge 126:abea610beb85 6888 #define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6889 #define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6890
AnnaBridge 126:abea610beb85 6891 #define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
AnnaBridge 126:abea610beb85 6892 #define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6893 #define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6894 #define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 6895
AnnaBridge 126:abea610beb85 6896 #define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
AnnaBridge 126:abea610beb85 6897 #define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
AnnaBridge 126:abea610beb85 6898
AnnaBridge 126:abea610beb85 6899 #define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
AnnaBridge 126:abea610beb85 6900 #define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6901 #define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6902
AnnaBridge 126:abea610beb85 6903 #define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
AnnaBridge 126:abea610beb85 6904 #define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
AnnaBridge 126:abea610beb85 6905 #define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
AnnaBridge 126:abea610beb85 6906 #define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
AnnaBridge 126:abea610beb85 6907 #define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */
AnnaBridge 126:abea610beb85 6908
AnnaBridge 126:abea610beb85 6909 #define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */
AnnaBridge 126:abea610beb85 6910 #define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6911 #define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6912 #define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 6913 #define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 6914
AnnaBridge 126:abea610beb85 6915 /******************* Bit definition for SAI_xCR2 register *******************/
AnnaBridge 126:abea610beb85 6916 #define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
AnnaBridge 126:abea610beb85 6917 #define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6918 #define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6919 #define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 6920
AnnaBridge 126:abea610beb85 6921 #define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
AnnaBridge 126:abea610beb85 6922 #define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
AnnaBridge 126:abea610beb85 6923 #define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
AnnaBridge 126:abea610beb85 6924 #define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
AnnaBridge 126:abea610beb85 6925
AnnaBridge 126:abea610beb85 6926 #define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
AnnaBridge 126:abea610beb85 6927 #define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6928 #define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6929 #define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 6930 #define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 6931 #define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 6932 #define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 6933
AnnaBridge 126:abea610beb85 6934 #define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
AnnaBridge 126:abea610beb85 6935
AnnaBridge 126:abea610beb85 6936 #define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
AnnaBridge 126:abea610beb85 6937 #define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6938 #define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6939
AnnaBridge 126:abea610beb85 6940 /****************** Bit definition for SAI_xFRCR register *******************/
AnnaBridge 126:abea610beb85 6941 #define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */
AnnaBridge 126:abea610beb85 6942 #define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6943 #define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6944 #define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 6945 #define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 6946 #define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 6947 #define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 6948 #define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 6949 #define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 6950
AnnaBridge 126:abea610beb85 6951 #define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */
AnnaBridge 126:abea610beb85 6952 #define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6953 #define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6954 #define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 6955 #define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 6956 #define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 6957 #define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 6958 #define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 6959
AnnaBridge 126:abea610beb85 6960 #define SAI_xFRCR_FSDEF 0x00010000U /*!<Frame Synchronization Definition */
AnnaBridge 126:abea610beb85 6961 #define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
AnnaBridge 126:abea610beb85 6962 #define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
AnnaBridge 126:abea610beb85 6963
AnnaBridge 126:abea610beb85 6964 /* Legacy define */
AnnaBridge 126:abea610beb85 6965 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
AnnaBridge 126:abea610beb85 6966
AnnaBridge 126:abea610beb85 6967 /****************** Bit definition for SAI_xSLOTR register *******************/
AnnaBridge 126:abea610beb85 6968 #define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */
AnnaBridge 126:abea610beb85 6969 #define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6970 #define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6971 #define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 6972 #define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 6973 #define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 6974
AnnaBridge 126:abea610beb85 6975 #define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
AnnaBridge 126:abea610beb85 6976 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6977 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6978
AnnaBridge 126:abea610beb85 6979 #define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
AnnaBridge 126:abea610beb85 6980 #define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 6981 #define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 6982 #define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 6983 #define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 6984
AnnaBridge 126:abea610beb85 6985 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
AnnaBridge 126:abea610beb85 6986
AnnaBridge 126:abea610beb85 6987 /******************* Bit definition for SAI_xIMR register *******************/
AnnaBridge 126:abea610beb85 6988 #define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
AnnaBridge 126:abea610beb85 6989 #define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
AnnaBridge 126:abea610beb85 6990 #define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
AnnaBridge 126:abea610beb85 6991 #define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
AnnaBridge 126:abea610beb85 6992 #define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
AnnaBridge 126:abea610beb85 6993 #define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
AnnaBridge 126:abea610beb85 6994 #define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
AnnaBridge 126:abea610beb85 6995
AnnaBridge 126:abea610beb85 6996 /******************** Bit definition for SAI_xSR register *******************/
AnnaBridge 126:abea610beb85 6997 #define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
AnnaBridge 126:abea610beb85 6998 #define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
AnnaBridge 126:abea610beb85 6999 #define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
AnnaBridge 126:abea610beb85 7000 #define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
AnnaBridge 126:abea610beb85 7001 #define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
AnnaBridge 126:abea610beb85 7002 #define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
AnnaBridge 126:abea610beb85 7003 #define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
AnnaBridge 126:abea610beb85 7004
AnnaBridge 126:abea610beb85 7005 #define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
AnnaBridge 126:abea610beb85 7006 #define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7007 #define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7008 #define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7009
AnnaBridge 126:abea610beb85 7010 /****************** Bit definition for SAI_xCLRFR register ******************/
AnnaBridge 126:abea610beb85 7011 #define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
AnnaBridge 126:abea610beb85 7012 #define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
AnnaBridge 126:abea610beb85 7013 #define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
AnnaBridge 126:abea610beb85 7014 #define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
AnnaBridge 126:abea610beb85 7015 #define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
AnnaBridge 126:abea610beb85 7016 #define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
AnnaBridge 126:abea610beb85 7017 #define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
AnnaBridge 126:abea610beb85 7018
AnnaBridge 126:abea610beb85 7019 /****************** Bit definition for SAI_xDR register *********************/
AnnaBridge 126:abea610beb85 7020 #define SAI_xDR_DATA 0xFFFFFFFFU
AnnaBridge 126:abea610beb85 7021
AnnaBridge 126:abea610beb85 7022 /******************************************************************************/
AnnaBridge 126:abea610beb85 7023 /* */
AnnaBridge 126:abea610beb85 7024 /* SPDIF-RX Interface */
AnnaBridge 126:abea610beb85 7025 /* */
AnnaBridge 126:abea610beb85 7026 /******************************************************************************/
AnnaBridge 126:abea610beb85 7027 /******************** Bit definition for SPDIF_CR register *******************/
AnnaBridge 126:abea610beb85 7028 #define SPDIFRX_CR_SPDIFEN 0x00000003U /*!<Peripheral Block Enable */
AnnaBridge 126:abea610beb85 7029 #define SPDIFRX_CR_RXDMAEN 0x00000004U /*!<Receiver DMA Enable for data flow */
AnnaBridge 126:abea610beb85 7030 #define SPDIFRX_CR_RXSTEO 0x00000008U /*!<Stereo Mode */
AnnaBridge 126:abea610beb85 7031 #define SPDIFRX_CR_DRFMT 0x00000030U /*!<RX Data format */
AnnaBridge 126:abea610beb85 7032 #define SPDIFRX_CR_PMSK 0x00000040U /*!<Mask Parity error bit */
AnnaBridge 126:abea610beb85 7033 #define SPDIFRX_CR_VMSK 0x00000080U /*!<Mask of Validity bit */
AnnaBridge 126:abea610beb85 7034 #define SPDIFRX_CR_CUMSK 0x00000100U /*!<Mask of channel status and user bits */
AnnaBridge 126:abea610beb85 7035 #define SPDIFRX_CR_PTMSK 0x00000200U /*!<Mask of Preamble Type bits */
AnnaBridge 126:abea610beb85 7036 #define SPDIFRX_CR_CBDMAEN 0x00000400U /*!<Control Buffer DMA ENable for control flow */
AnnaBridge 126:abea610beb85 7037 #define SPDIFRX_CR_CHSEL 0x00000800U /*!<Channel Selection */
AnnaBridge 126:abea610beb85 7038 #define SPDIFRX_CR_NBTR 0x00003000U /*!<Maximum allowed re-tries during synchronization phase */
AnnaBridge 126:abea610beb85 7039 #define SPDIFRX_CR_WFA 0x00004000U /*!<Wait For Activity */
AnnaBridge 126:abea610beb85 7040 #define SPDIFRX_CR_INSEL 0x00070000U /*!<SPDIF input selection */
AnnaBridge 126:abea610beb85 7041
AnnaBridge 126:abea610beb85 7042 /******************* Bit definition for SPDIFRX_IMR register *******************/
AnnaBridge 126:abea610beb85 7043 #define SPDIFRX_IMR_RXNEIE 0x00000001U /*!<RXNE interrupt enable */
AnnaBridge 126:abea610beb85 7044 #define SPDIFRX_IMR_CSRNEIE 0x00000002U /*!<Control Buffer Ready Interrupt Enable */
AnnaBridge 126:abea610beb85 7045 #define SPDIFRX_IMR_PERRIE 0x00000004U /*!<Parity error interrupt enable */
AnnaBridge 126:abea610beb85 7046 #define SPDIFRX_IMR_OVRIE 0x00000008U /*!<Overrun error Interrupt Enable */
AnnaBridge 126:abea610beb85 7047 #define SPDIFRX_IMR_SBLKIE 0x00000010U /*!<Synchronization Block Detected Interrupt Enable */
AnnaBridge 126:abea610beb85 7048 #define SPDIFRX_IMR_SYNCDIE 0x00000020U /*!<Synchronization Done */
AnnaBridge 126:abea610beb85 7049 #define SPDIFRX_IMR_IFEIE 0x00000040U /*!<Serial Interface Error Interrupt Enable */
AnnaBridge 126:abea610beb85 7050
AnnaBridge 126:abea610beb85 7051 /******************* Bit definition for SPDIFRX_SR register *******************/
AnnaBridge 126:abea610beb85 7052 #define SPDIFRX_SR_RXNE 0x00000001U /*!<Read data register not empty */
AnnaBridge 126:abea610beb85 7053 #define SPDIFRX_SR_CSRNE 0x00000002U /*!<The Control Buffer register is not empty */
AnnaBridge 126:abea610beb85 7054 #define SPDIFRX_SR_PERR 0x00000004U /*!<Parity error */
AnnaBridge 126:abea610beb85 7055 #define SPDIFRX_SR_OVR 0x00000008U /*!<Overrun error */
AnnaBridge 126:abea610beb85 7056 #define SPDIFRX_SR_SBD 0x00000010U /*!<Synchronization Block Detected */
AnnaBridge 126:abea610beb85 7057 #define SPDIFRX_SR_SYNCD 0x00000020U /*!<Synchronization Done */
AnnaBridge 126:abea610beb85 7058 #define SPDIFRX_SR_FERR 0x00000040U /*!<Framing error */
AnnaBridge 126:abea610beb85 7059 #define SPDIFRX_SR_SERR 0x00000080U /*!<Synchronization error */
AnnaBridge 126:abea610beb85 7060 #define SPDIFRX_SR_TERR 0x00000100U /*!<Time-out error */
AnnaBridge 126:abea610beb85 7061 #define SPDIFRX_SR_WIDTH5 0x7FFF0000U /*!<Duration of 5 symbols counted with spdif_clk */
AnnaBridge 126:abea610beb85 7062
AnnaBridge 126:abea610beb85 7063 /******************* Bit definition for SPDIFRX_IFCR register *******************/
AnnaBridge 126:abea610beb85 7064 #define SPDIFRX_IFCR_PERRCF 0x00000004U /*!<Clears the Parity error flag */
AnnaBridge 126:abea610beb85 7065 #define SPDIFRX_IFCR_OVRCF 0x00000008U /*!<Clears the Overrun error flag */
AnnaBridge 126:abea610beb85 7066 #define SPDIFRX_IFCR_SBDCF 0x00000010U /*!<Clears the Synchronization Block Detected flag */
AnnaBridge 126:abea610beb85 7067 #define SPDIFRX_IFCR_SYNCDCF 0x00000020U /*!<Clears the Synchronization Done flag */
AnnaBridge 126:abea610beb85 7068
AnnaBridge 126:abea610beb85 7069 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
AnnaBridge 126:abea610beb85 7070 #define SPDIFRX_DR0_DR 0x00FFFFFFU /*!<Data value */
AnnaBridge 126:abea610beb85 7071 #define SPDIFRX_DR0_PE 0x01000000U /*!<Parity Error bit */
AnnaBridge 126:abea610beb85 7072 #define SPDIFRX_DR0_V 0x02000000U /*!<Validity bit */
AnnaBridge 126:abea610beb85 7073 #define SPDIFRX_DR0_U 0x04000000U /*!<User bit */
AnnaBridge 126:abea610beb85 7074 #define SPDIFRX_DR0_C 0x08000000U /*!<Channel Status bit */
AnnaBridge 126:abea610beb85 7075 #define SPDIFRX_DR0_PT 0x30000000U /*!<Preamble Type */
AnnaBridge 126:abea610beb85 7076
AnnaBridge 126:abea610beb85 7077 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
AnnaBridge 126:abea610beb85 7078 #define SPDIFRX_DR1_DR 0xFFFFFF00U /*!<Data value */
AnnaBridge 126:abea610beb85 7079 #define SPDIFRX_DR1_PT 0x00000030U /*!<Preamble Type */
AnnaBridge 126:abea610beb85 7080 #define SPDIFRX_DR1_C 0x00000008U /*!<Channel Status bit */
AnnaBridge 126:abea610beb85 7081 #define SPDIFRX_DR1_U 0x00000004U /*!<User bit */
AnnaBridge 126:abea610beb85 7082 #define SPDIFRX_DR1_V 0x00000002U /*!<Validity bit */
AnnaBridge 126:abea610beb85 7083 #define SPDIFRX_DR1_PE 0x00000001U /*!<Parity Error bit */
AnnaBridge 126:abea610beb85 7084
AnnaBridge 126:abea610beb85 7085 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
AnnaBridge 126:abea610beb85 7086 #define SPDIFRX_DR1_DRNL1 0xFFFF0000U /*!<Data value Channel B */
AnnaBridge 126:abea610beb85 7087 #define SPDIFRX_DR1_DRNL2 0x0000FFFFU /*!<Data value Channel A */
AnnaBridge 126:abea610beb85 7088
AnnaBridge 126:abea610beb85 7089 /******************* Bit definition for SPDIFRX_CSR register *******************/
AnnaBridge 126:abea610beb85 7090 #define SPDIFRX_CSR_USR 0x0000FFFFU /*!<User data information */
AnnaBridge 126:abea610beb85 7091 #define SPDIFRX_CSR_CS 0x00FF0000U /*!<Channel A status information */
AnnaBridge 126:abea610beb85 7092 #define SPDIFRX_CSR_SOB 0x01000000U /*!<Start Of Block */
AnnaBridge 126:abea610beb85 7093
AnnaBridge 126:abea610beb85 7094 /******************* Bit definition for SPDIFRX_DIR register *******************/
AnnaBridge 126:abea610beb85 7095 #define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */
AnnaBridge 126:abea610beb85 7096 #define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */
AnnaBridge 126:abea610beb85 7097
AnnaBridge 126:abea610beb85 7098
AnnaBridge 126:abea610beb85 7099 /******************************************************************************/
AnnaBridge 126:abea610beb85 7100 /* */
AnnaBridge 126:abea610beb85 7101 /* SD host Interface */
AnnaBridge 126:abea610beb85 7102 /* */
AnnaBridge 126:abea610beb85 7103 /******************************************************************************/
AnnaBridge 126:abea610beb85 7104 /****************** Bit definition for SDMMC_POWER register ******************/
AnnaBridge 126:abea610beb85 7105 #define SDMMC_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
AnnaBridge 126:abea610beb85 7106 #define SDMMC_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7107 #define SDMMC_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7108
AnnaBridge 126:abea610beb85 7109 /****************** Bit definition for SDMMC_CLKCR register ******************/
AnnaBridge 126:abea610beb85 7110 #define SDMMC_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
AnnaBridge 126:abea610beb85 7111 #define SDMMC_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
AnnaBridge 126:abea610beb85 7112 #define SDMMC_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
AnnaBridge 126:abea610beb85 7113 #define SDMMC_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
AnnaBridge 126:abea610beb85 7114
AnnaBridge 126:abea610beb85 7115 #define SDMMC_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
AnnaBridge 126:abea610beb85 7116 #define SDMMC_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7117 #define SDMMC_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7118
AnnaBridge 126:abea610beb85 7119 #define SDMMC_CLKCR_NEGEDGE 0x2000U /*!<SDMMC_CK dephasing selection bit */
AnnaBridge 126:abea610beb85 7120 #define SDMMC_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
AnnaBridge 126:abea610beb85 7121
AnnaBridge 126:abea610beb85 7122 /******************* Bit definition for SDMMC_ARG register *******************/
AnnaBridge 126:abea610beb85 7123 #define SDMMC_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
AnnaBridge 126:abea610beb85 7124
AnnaBridge 126:abea610beb85 7125 /******************* Bit definition for SDMMC_CMD register *******************/
AnnaBridge 126:abea610beb85 7126 #define SDMMC_CMD_CMDINDEX 0x003FU /*!<Command Index */
AnnaBridge 126:abea610beb85 7127
AnnaBridge 126:abea610beb85 7128 #define SDMMC_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
AnnaBridge 126:abea610beb85 7129 #define SDMMC_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 7130 #define SDMMC_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 7131
AnnaBridge 126:abea610beb85 7132 #define SDMMC_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
AnnaBridge 126:abea610beb85 7133 #define SDMMC_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
AnnaBridge 126:abea610beb85 7134 #define SDMMC_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
AnnaBridge 126:abea610beb85 7135 #define SDMMC_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
AnnaBridge 126:abea610beb85 7136
AnnaBridge 126:abea610beb85 7137 /***************** Bit definition for SDMMC_RESPCMD register *****************/
AnnaBridge 126:abea610beb85 7138 #define SDMMC_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
AnnaBridge 126:abea610beb85 7139
AnnaBridge 126:abea610beb85 7140 /****************** Bit definition for SDMMC_RESP0 register ******************/
AnnaBridge 126:abea610beb85 7141 #define SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
AnnaBridge 126:abea610beb85 7142
AnnaBridge 126:abea610beb85 7143 /****************** Bit definition for SDMMC_RESP1 register ******************/
AnnaBridge 126:abea610beb85 7144 #define SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
AnnaBridge 126:abea610beb85 7145
AnnaBridge 126:abea610beb85 7146 /****************** Bit definition for SDMMC_RESP2 register ******************/
AnnaBridge 126:abea610beb85 7147 #define SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
AnnaBridge 126:abea610beb85 7148
AnnaBridge 126:abea610beb85 7149 /****************** Bit definition for SDMMC_RESP3 register ******************/
AnnaBridge 126:abea610beb85 7150 #define SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
AnnaBridge 126:abea610beb85 7151
AnnaBridge 126:abea610beb85 7152 /****************** Bit definition for SDMMC_RESP4 register ******************/
AnnaBridge 126:abea610beb85 7153 #define SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
AnnaBridge 126:abea610beb85 7154
AnnaBridge 126:abea610beb85 7155 /****************** Bit definition for SDMMC_DTIMER register *****************/
AnnaBridge 126:abea610beb85 7156 #define SDMMC_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
AnnaBridge 126:abea610beb85 7157
AnnaBridge 126:abea610beb85 7158 /****************** Bit definition for SDMMC_DLEN register *******************/
AnnaBridge 126:abea610beb85 7159 #define SDMMC_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
AnnaBridge 126:abea610beb85 7160
AnnaBridge 126:abea610beb85 7161 /****************** Bit definition for SDMMC_DCTRL register ******************/
AnnaBridge 126:abea610beb85 7162 #define SDMMC_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
AnnaBridge 126:abea610beb85 7163 #define SDMMC_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
AnnaBridge 126:abea610beb85 7164 #define SDMMC_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
AnnaBridge 126:abea610beb85 7165 #define SDMMC_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
AnnaBridge 126:abea610beb85 7166
AnnaBridge 126:abea610beb85 7167 #define SDMMC_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
AnnaBridge 126:abea610beb85 7168 #define SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7169 #define SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7170 #define SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7171 #define SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7172
AnnaBridge 126:abea610beb85 7173 #define SDMMC_DCTRL_RWSTART 0x0100U /*!<Read wait start */
AnnaBridge 126:abea610beb85 7174 #define SDMMC_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
AnnaBridge 126:abea610beb85 7175 #define SDMMC_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
AnnaBridge 126:abea610beb85 7176 #define SDMMC_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
AnnaBridge 126:abea610beb85 7177
AnnaBridge 126:abea610beb85 7178 /****************** Bit definition for SDMMC_DCOUNT register *****************/
AnnaBridge 126:abea610beb85 7179 #define SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
AnnaBridge 126:abea610beb85 7180
AnnaBridge 126:abea610beb85 7181 /****************** Bit definition for SDMMC_STA registe ********************/
AnnaBridge 126:abea610beb85 7182 #define SDMMC_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
AnnaBridge 126:abea610beb85 7183 #define SDMMC_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
AnnaBridge 126:abea610beb85 7184 #define SDMMC_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
AnnaBridge 126:abea610beb85 7185 #define SDMMC_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
AnnaBridge 126:abea610beb85 7186 #define SDMMC_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
AnnaBridge 126:abea610beb85 7187 #define SDMMC_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
AnnaBridge 126:abea610beb85 7188 #define SDMMC_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
AnnaBridge 126:abea610beb85 7189 #define SDMMC_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
AnnaBridge 126:abea610beb85 7190 #define SDMMC_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
AnnaBridge 126:abea610beb85 7191 #define SDMMC_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
AnnaBridge 126:abea610beb85 7192 #define SDMMC_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
AnnaBridge 126:abea610beb85 7193 #define SDMMC_STA_TXACT 0x00001000U /*!<Data transmit in progress */
AnnaBridge 126:abea610beb85 7194 #define SDMMC_STA_RXACT 0x00002000U /*!<Data receive in progress */
AnnaBridge 126:abea610beb85 7195 #define SDMMC_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
AnnaBridge 126:abea610beb85 7196 #define SDMMC_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
AnnaBridge 126:abea610beb85 7197 #define SDMMC_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
AnnaBridge 126:abea610beb85 7198 #define SDMMC_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
AnnaBridge 126:abea610beb85 7199 #define SDMMC_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
AnnaBridge 126:abea610beb85 7200 #define SDMMC_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
AnnaBridge 126:abea610beb85 7201 #define SDMMC_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
AnnaBridge 126:abea610beb85 7202 #define SDMMC_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
AnnaBridge 126:abea610beb85 7203 #define SDMMC_STA_SDIOIT 0x00400000U /*!<SDMMC interrupt received */
AnnaBridge 126:abea610beb85 7204
AnnaBridge 126:abea610beb85 7205 /******************* Bit definition for SDMMC_ICR register *******************/
AnnaBridge 126:abea610beb85 7206 #define SDMMC_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
AnnaBridge 126:abea610beb85 7207 #define SDMMC_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
AnnaBridge 126:abea610beb85 7208 #define SDMMC_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
AnnaBridge 126:abea610beb85 7209 #define SDMMC_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
AnnaBridge 126:abea610beb85 7210 #define SDMMC_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
AnnaBridge 126:abea610beb85 7211 #define SDMMC_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
AnnaBridge 126:abea610beb85 7212 #define SDMMC_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
AnnaBridge 126:abea610beb85 7213 #define SDMMC_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
AnnaBridge 126:abea610beb85 7214 #define SDMMC_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
AnnaBridge 126:abea610beb85 7215 #define SDMMC_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
AnnaBridge 126:abea610beb85 7216 #define SDMMC_ICR_SDIOITC 0x00400000U /*!<SDMMCIT flag clear bit */
AnnaBridge 126:abea610beb85 7217
AnnaBridge 126:abea610beb85 7218 /****************** Bit definition for SDMMC_MASK register *******************/
AnnaBridge 126:abea610beb85 7219 #define SDMMC_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
AnnaBridge 126:abea610beb85 7220 #define SDMMC_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
AnnaBridge 126:abea610beb85 7221 #define SDMMC_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
AnnaBridge 126:abea610beb85 7222 #define SDMMC_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
AnnaBridge 126:abea610beb85 7223 #define SDMMC_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
AnnaBridge 126:abea610beb85 7224 #define SDMMC_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
AnnaBridge 126:abea610beb85 7225 #define SDMMC_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
AnnaBridge 126:abea610beb85 7226 #define SDMMC_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
AnnaBridge 126:abea610beb85 7227 #define SDMMC_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
AnnaBridge 126:abea610beb85 7228 #define SDMMC_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
AnnaBridge 126:abea610beb85 7229 #define SDMMC_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
AnnaBridge 126:abea610beb85 7230 #define SDMMC_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
AnnaBridge 126:abea610beb85 7231 #define SDMMC_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
AnnaBridge 126:abea610beb85 7232 #define SDMMC_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
AnnaBridge 126:abea610beb85 7233 #define SDMMC_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
AnnaBridge 126:abea610beb85 7234 #define SDMMC_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
AnnaBridge 126:abea610beb85 7235 #define SDMMC_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
AnnaBridge 126:abea610beb85 7236 #define SDMMC_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
AnnaBridge 126:abea610beb85 7237 #define SDMMC_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
AnnaBridge 126:abea610beb85 7238 #define SDMMC_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
AnnaBridge 126:abea610beb85 7239 #define SDMMC_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
AnnaBridge 126:abea610beb85 7240 #define SDMMC_MASK_SDIOITIE 0x00400000U /*!<SDMMC Mode Interrupt Received interrupt Enable */
AnnaBridge 126:abea610beb85 7241
AnnaBridge 126:abea610beb85 7242 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
AnnaBridge 126:abea610beb85 7243 #define SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
AnnaBridge 126:abea610beb85 7244
AnnaBridge 126:abea610beb85 7245 /****************** Bit definition for SDMMC_FIFO register *******************/
AnnaBridge 126:abea610beb85 7246 #define SDMMC_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
AnnaBridge 126:abea610beb85 7247
AnnaBridge 126:abea610beb85 7248 /******************************************************************************/
AnnaBridge 126:abea610beb85 7249 /* */
AnnaBridge 126:abea610beb85 7250 /* Serial Peripheral Interface (SPI) */
AnnaBridge 126:abea610beb85 7251 /* */
AnnaBridge 126:abea610beb85 7252 /******************************************************************************/
AnnaBridge 126:abea610beb85 7253 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 126:abea610beb85 7254 #define SPI_CR1_CPHA 0x00000001U /*!< Clock Phase */
AnnaBridge 126:abea610beb85 7255 #define SPI_CR1_CPOL 0x00000002U /*!< Clock Polarity */
AnnaBridge 126:abea610beb85 7256 #define SPI_CR1_MSTR 0x00000004U /*!< Master Selection */
AnnaBridge 126:abea610beb85 7257 #define SPI_CR1_BR 0x00000038U /*!< BR[2:0] bits (Baud Rate Control) */
AnnaBridge 126:abea610beb85 7258 #define SPI_CR1_BR_0 0x00000008U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 7259 #define SPI_CR1_BR_1 0x00000010U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 7260 #define SPI_CR1_BR_2 0x00000020U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 7261 #define SPI_CR1_SPE 0x00000040U /*!< SPI Enable */
AnnaBridge 126:abea610beb85 7262 #define SPI_CR1_LSBFIRST 0x00000080U /*!< Frame Format */
AnnaBridge 126:abea610beb85 7263 #define SPI_CR1_SSI 0x00000100U /*!< Internal slave select */
AnnaBridge 126:abea610beb85 7264 #define SPI_CR1_SSM 0x00000200U /*!< Software slave management */
AnnaBridge 126:abea610beb85 7265 #define SPI_CR1_RXONLY 0x00000400U /*!< Receive only */
AnnaBridge 126:abea610beb85 7266 #define SPI_CR1_CRCL 0x00000800U /*!< CRC Length */
AnnaBridge 126:abea610beb85 7267 #define SPI_CR1_CRCNEXT 0x00001000U /*!< Transmit CRC next */
AnnaBridge 126:abea610beb85 7268 #define SPI_CR1_CRCEN 0x00002000U /*!< Hardware CRC calculation enable */
AnnaBridge 126:abea610beb85 7269 #define SPI_CR1_BIDIOE 0x00004000U /*!< Output enable in bidirectional mode */
AnnaBridge 126:abea610beb85 7270 #define SPI_CR1_BIDIMODE 0x00008000U /*!< Bidirectional data mode enable */
AnnaBridge 126:abea610beb85 7271
AnnaBridge 126:abea610beb85 7272 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 126:abea610beb85 7273 #define SPI_CR2_RXDMAEN 0x00000001U /*!< Rx Buffer DMA Enable */
AnnaBridge 126:abea610beb85 7274 #define SPI_CR2_TXDMAEN 0x00000002U /*!< Tx Buffer DMA Enable */
AnnaBridge 126:abea610beb85 7275 #define SPI_CR2_SSOE 0x00000004U /*!< SS Output Enable */
AnnaBridge 126:abea610beb85 7276 #define SPI_CR2_NSSP 0x00000008U /*!< NSS pulse management Enable */
AnnaBridge 126:abea610beb85 7277 #define SPI_CR2_FRF 0x00000010U /*!< Frame Format Enable */
AnnaBridge 126:abea610beb85 7278 #define SPI_CR2_ERRIE 0x00000020U /*!< Error Interrupt Enable */
AnnaBridge 126:abea610beb85 7279 #define SPI_CR2_RXNEIE 0x00000040U /*!< RX buffer Not Empty Interrupt Enable */
AnnaBridge 126:abea610beb85 7280 #define SPI_CR2_TXEIE 0x00000080U /*!< Tx buffer Empty Interrupt Enable */
AnnaBridge 126:abea610beb85 7281 #define SPI_CR2_DS 0x00000F00U /*!< DS[3:0] Data Size */
AnnaBridge 126:abea610beb85 7282 #define SPI_CR2_DS_0 0x00000100U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 7283 #define SPI_CR2_DS_1 0x00000200U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 7284 #define SPI_CR2_DS_2 0x00000400U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 7285 #define SPI_CR2_DS_3 0x00000800U /*!< Bit 3 */
AnnaBridge 126:abea610beb85 7286 #define SPI_CR2_FRXTH 0x00001000U /*!< FIFO reception Threshold */
AnnaBridge 126:abea610beb85 7287 #define SPI_CR2_LDMARX 0x00002000U /*!< Last DMA transfer for reception */
AnnaBridge 126:abea610beb85 7288 #define SPI_CR2_LDMATX 0x00004000U /*!< Last DMA transfer for transmission */
AnnaBridge 126:abea610beb85 7289
AnnaBridge 126:abea610beb85 7290 /******************** Bit definition for SPI_SR register ********************/
AnnaBridge 126:abea610beb85 7291 #define SPI_SR_RXNE 0x00000001U /*!< Receive buffer Not Empty */
AnnaBridge 126:abea610beb85 7292 #define SPI_SR_TXE 0x00000002U /*!< Transmit buffer Empty */
AnnaBridge 126:abea610beb85 7293 #define SPI_SR_CHSIDE 0x00000004U /*!< Channel side */
AnnaBridge 126:abea610beb85 7294 #define SPI_SR_UDR 0x00000008U /*!< Underrun flag */
AnnaBridge 126:abea610beb85 7295 #define SPI_SR_CRCERR 0x00000010U /*!< CRC Error flag */
AnnaBridge 126:abea610beb85 7296 #define SPI_SR_MODF 0x00000020U /*!< Mode fault */
AnnaBridge 126:abea610beb85 7297 #define SPI_SR_OVR 0x00000040U /*!< Overrun flag */
AnnaBridge 126:abea610beb85 7298 #define SPI_SR_BSY 0x00000080U /*!< Busy flag */
AnnaBridge 126:abea610beb85 7299 #define SPI_SR_FRE 0x00000100U /*!< TI frame format error */
AnnaBridge 126:abea610beb85 7300 #define SPI_SR_FRLVL 0x00000600U /*!< FIFO Reception Level */
AnnaBridge 126:abea610beb85 7301 #define SPI_SR_FRLVL_0 0x00000200U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 7302 #define SPI_SR_FRLVL_1 0x00000400U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 7303 #define SPI_SR_FTLVL 0x00001800U /*!< FIFO Transmission Level */
AnnaBridge 126:abea610beb85 7304 #define SPI_SR_FTLVL_0 0x00000800U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 7305 #define SPI_SR_FTLVL_1 0x00001000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 7306
AnnaBridge 126:abea610beb85 7307 /******************** Bit definition for SPI_DR register ********************/
AnnaBridge 126:abea610beb85 7308 #define SPI_DR_DR 0xFFFFU /*!< Data Register */
AnnaBridge 126:abea610beb85 7309
AnnaBridge 126:abea610beb85 7310 /******************* Bit definition for SPI_CRCPR register ******************/
AnnaBridge 126:abea610beb85 7311 #define SPI_CRCPR_CRCPOLY 0xFFFFU /*!< CRC polynomial register */
AnnaBridge 126:abea610beb85 7312
AnnaBridge 126:abea610beb85 7313 /****************** Bit definition for SPI_RXCRCR register ******************/
AnnaBridge 126:abea610beb85 7314 #define SPI_RXCRCR_RXCRC 0xFFFFU /*!< Rx CRC Register */
AnnaBridge 126:abea610beb85 7315
AnnaBridge 126:abea610beb85 7316 /****************** Bit definition for SPI_TXCRCR register ******************/
AnnaBridge 126:abea610beb85 7317 #define SPI_TXCRCR_TXCRC 0xFFFFU /*!< Tx CRC Register */
AnnaBridge 126:abea610beb85 7318
AnnaBridge 126:abea610beb85 7319 /****************** Bit definition for SPI_I2SCFGR register *****************/
AnnaBridge 126:abea610beb85 7320 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
AnnaBridge 126:abea610beb85 7321 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
AnnaBridge 126:abea610beb85 7322 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7323 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7324 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
AnnaBridge 126:abea610beb85 7325 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
AnnaBridge 126:abea610beb85 7326 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7327 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7328 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
AnnaBridge 126:abea610beb85 7329 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
AnnaBridge 126:abea610beb85 7330 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7331 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7332 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
AnnaBridge 126:abea610beb85 7333 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
AnnaBridge 126:abea610beb85 7334 #define SPI_I2SCFGR_ASTRTEN 0x00001000U /*!<Asynchronous start enable */
AnnaBridge 126:abea610beb85 7335
AnnaBridge 126:abea610beb85 7336 /****************** Bit definition for SPI_I2SPR register *******************/
AnnaBridge 126:abea610beb85 7337 #define SPI_I2SPR_I2SDIV 0x00FFU /*!<I2S Linear prescaler */
AnnaBridge 126:abea610beb85 7338 #define SPI_I2SPR_ODD 0x0100U /*!<Odd factor for the prescaler */
AnnaBridge 126:abea610beb85 7339 #define SPI_I2SPR_MCKOE 0x0200U /*!<Master Clock Output Enable */
AnnaBridge 126:abea610beb85 7340
AnnaBridge 126:abea610beb85 7341
AnnaBridge 126:abea610beb85 7342 /******************************************************************************/
AnnaBridge 126:abea610beb85 7343 /* */
AnnaBridge 126:abea610beb85 7344 /* SYSCFG */
AnnaBridge 126:abea610beb85 7345 /* */
AnnaBridge 126:abea610beb85 7346 /******************************************************************************/
AnnaBridge 126:abea610beb85 7347 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
AnnaBridge 126:abea610beb85 7348 #define SYSCFG_MEMRMP_MEM_BOOT 0x00000001U /*!< Boot information after Reset */
AnnaBridge 126:abea610beb85 7349
AnnaBridge 126:abea610beb85 7350 #define SYSCFG_MEMRMP_SWP_FB 0x00000100U /*!< User Flash Bank swap */
AnnaBridge 126:abea610beb85 7351
AnnaBridge 126:abea610beb85 7352 #define SYSCFG_MEMRMP_SWP_FMC 0x00000C00U /*!< FMC Memory Mapping swapping */
AnnaBridge 126:abea610beb85 7353 #define SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U
AnnaBridge 126:abea610beb85 7354 #define SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U
AnnaBridge 126:abea610beb85 7355
AnnaBridge 126:abea610beb85 7356 /****************** Bit definition for SYSCFG_PMC register ******************/
AnnaBridge 126:abea610beb85 7357 #define SYSCFG_PMC_I2C1_FMP 0x00000001U /*!< I2C1_FMP I2C1 Fast Mode + Enable */
AnnaBridge 126:abea610beb85 7358 #define SYSCFG_PMC_I2C2_FMP 0x00000002U /*!< I2C2_FMP I2C2 Fast Mode + Enable */
AnnaBridge 126:abea610beb85 7359 #define SYSCFG_PMC_I2C3_FMP 0x00000004U /*!< I2C3_FMP I2C3 Fast Mode + Enable */
AnnaBridge 126:abea610beb85 7360 #define SYSCFG_PMC_I2C4_FMP 0x00000008U /*!< I2C4_FMP I2C4 Fast Mode + Enable */
AnnaBridge 126:abea610beb85 7361 #define SYSCFG_PMC_I2C_PB6_FMP 0x00000010U /*!< PB6_FMP Fast Mode + Enable */
AnnaBridge 126:abea610beb85 7362 #define SYSCFG_PMC_I2C_PB7_FMP 0x00000020U /*!< PB7_FMP Fast Mode + Enable */
AnnaBridge 126:abea610beb85 7363 #define SYSCFG_PMC_I2C_PB8_FMP 0x00000040U /*!< PB8_FMP Fast Mode + Enable */
AnnaBridge 126:abea610beb85 7364 #define SYSCFG_PMC_I2C_PB9_FMP 0x00000080U /*!< PB9_FMP Fast Mode + Enable */
AnnaBridge 126:abea610beb85 7365
AnnaBridge 126:abea610beb85 7366 #define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 126:abea610beb85 7367 #define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 126:abea610beb85 7368 #define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 126:abea610beb85 7369 #define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 126:abea610beb85 7370
AnnaBridge 126:abea610beb85 7371 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
AnnaBridge 126:abea610beb85 7372
AnnaBridge 126:abea610beb85 7373 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 126:abea610beb85 7374 #define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
AnnaBridge 126:abea610beb85 7375 #define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
AnnaBridge 126:abea610beb85 7376 #define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
AnnaBridge 126:abea610beb85 7377 #define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
AnnaBridge 126:abea610beb85 7378 /**
AnnaBridge 126:abea610beb85 7379 * @brief EXTI0 configuration
AnnaBridge 126:abea610beb85 7380 */
AnnaBridge 126:abea610beb85 7381 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
AnnaBridge 126:abea610beb85 7382 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
AnnaBridge 126:abea610beb85 7383 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
AnnaBridge 126:abea610beb85 7384 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
AnnaBridge 126:abea610beb85 7385 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
AnnaBridge 126:abea610beb85 7386 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
AnnaBridge 126:abea610beb85 7387 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
AnnaBridge 126:abea610beb85 7388 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
AnnaBridge 126:abea610beb85 7389 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
AnnaBridge 126:abea610beb85 7390 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
AnnaBridge 126:abea610beb85 7391 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
AnnaBridge 126:abea610beb85 7392
AnnaBridge 126:abea610beb85 7393 /**
AnnaBridge 126:abea610beb85 7394 * @brief EXTI1 configuration
AnnaBridge 126:abea610beb85 7395 */
AnnaBridge 126:abea610beb85 7396 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
AnnaBridge 126:abea610beb85 7397 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
AnnaBridge 126:abea610beb85 7398 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
AnnaBridge 126:abea610beb85 7399 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
AnnaBridge 126:abea610beb85 7400 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
AnnaBridge 126:abea610beb85 7401 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
AnnaBridge 126:abea610beb85 7402 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
AnnaBridge 126:abea610beb85 7403 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
AnnaBridge 126:abea610beb85 7404 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
AnnaBridge 126:abea610beb85 7405 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
AnnaBridge 126:abea610beb85 7406 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
AnnaBridge 126:abea610beb85 7407
AnnaBridge 126:abea610beb85 7408 /**
AnnaBridge 126:abea610beb85 7409 * @brief EXTI2 configuration
AnnaBridge 126:abea610beb85 7410 */
AnnaBridge 126:abea610beb85 7411 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
AnnaBridge 126:abea610beb85 7412 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
AnnaBridge 126:abea610beb85 7413 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
AnnaBridge 126:abea610beb85 7414 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
AnnaBridge 126:abea610beb85 7415 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
AnnaBridge 126:abea610beb85 7416 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
AnnaBridge 126:abea610beb85 7417 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
AnnaBridge 126:abea610beb85 7418 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
AnnaBridge 126:abea610beb85 7419 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
AnnaBridge 126:abea610beb85 7420 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
AnnaBridge 126:abea610beb85 7421 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
AnnaBridge 126:abea610beb85 7422
AnnaBridge 126:abea610beb85 7423 /**
AnnaBridge 126:abea610beb85 7424 * @brief EXTI3 configuration
AnnaBridge 126:abea610beb85 7425 */
AnnaBridge 126:abea610beb85 7426 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
AnnaBridge 126:abea610beb85 7427 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
AnnaBridge 126:abea610beb85 7428 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
AnnaBridge 126:abea610beb85 7429 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
AnnaBridge 126:abea610beb85 7430 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
AnnaBridge 126:abea610beb85 7431 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
AnnaBridge 126:abea610beb85 7432 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
AnnaBridge 126:abea610beb85 7433 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
AnnaBridge 126:abea610beb85 7434 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
AnnaBridge 126:abea610beb85 7435 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
AnnaBridge 126:abea610beb85 7436 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
AnnaBridge 126:abea610beb85 7437
AnnaBridge 126:abea610beb85 7438 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
AnnaBridge 126:abea610beb85 7439 #define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
AnnaBridge 126:abea610beb85 7440 #define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
AnnaBridge 126:abea610beb85 7441 #define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
AnnaBridge 126:abea610beb85 7442 #define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
AnnaBridge 126:abea610beb85 7443 /**
AnnaBridge 126:abea610beb85 7444 * @brief EXTI4 configuration
AnnaBridge 126:abea610beb85 7445 */
AnnaBridge 126:abea610beb85 7446 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
AnnaBridge 126:abea610beb85 7447 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
AnnaBridge 126:abea610beb85 7448 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
AnnaBridge 126:abea610beb85 7449 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
AnnaBridge 126:abea610beb85 7450 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
AnnaBridge 126:abea610beb85 7451 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
AnnaBridge 126:abea610beb85 7452 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
AnnaBridge 126:abea610beb85 7453 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
AnnaBridge 126:abea610beb85 7454 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
AnnaBridge 126:abea610beb85 7455 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
AnnaBridge 126:abea610beb85 7456 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
AnnaBridge 126:abea610beb85 7457
AnnaBridge 126:abea610beb85 7458 /**
AnnaBridge 126:abea610beb85 7459 * @brief EXTI5 configuration
AnnaBridge 126:abea610beb85 7460 */
AnnaBridge 126:abea610beb85 7461 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
AnnaBridge 126:abea610beb85 7462 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
AnnaBridge 126:abea610beb85 7463 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
AnnaBridge 126:abea610beb85 7464 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
AnnaBridge 126:abea610beb85 7465 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
AnnaBridge 126:abea610beb85 7466 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
AnnaBridge 126:abea610beb85 7467 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
AnnaBridge 126:abea610beb85 7468 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
AnnaBridge 126:abea610beb85 7469 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
AnnaBridge 126:abea610beb85 7470 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
AnnaBridge 126:abea610beb85 7471 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
AnnaBridge 126:abea610beb85 7472
AnnaBridge 126:abea610beb85 7473 /**
AnnaBridge 126:abea610beb85 7474 * @brief EXTI6 configuration
AnnaBridge 126:abea610beb85 7475 */
AnnaBridge 126:abea610beb85 7476 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
AnnaBridge 126:abea610beb85 7477 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
AnnaBridge 126:abea610beb85 7478 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
AnnaBridge 126:abea610beb85 7479 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
AnnaBridge 126:abea610beb85 7480 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
AnnaBridge 126:abea610beb85 7481 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
AnnaBridge 126:abea610beb85 7482 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
AnnaBridge 126:abea610beb85 7483 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
AnnaBridge 126:abea610beb85 7484 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
AnnaBridge 126:abea610beb85 7485 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
AnnaBridge 126:abea610beb85 7486 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
AnnaBridge 126:abea610beb85 7487
AnnaBridge 126:abea610beb85 7488 /**
AnnaBridge 126:abea610beb85 7489 * @brief EXTI7 configuration
AnnaBridge 126:abea610beb85 7490 */
AnnaBridge 126:abea610beb85 7491 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
AnnaBridge 126:abea610beb85 7492 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
AnnaBridge 126:abea610beb85 7493 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
AnnaBridge 126:abea610beb85 7494 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
AnnaBridge 126:abea610beb85 7495 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
AnnaBridge 126:abea610beb85 7496 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
AnnaBridge 126:abea610beb85 7497 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
AnnaBridge 126:abea610beb85 7498 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
AnnaBridge 126:abea610beb85 7499 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
AnnaBridge 126:abea610beb85 7500 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
AnnaBridge 126:abea610beb85 7501 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
AnnaBridge 126:abea610beb85 7502
AnnaBridge 126:abea610beb85 7503 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
AnnaBridge 126:abea610beb85 7504 #define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
AnnaBridge 126:abea610beb85 7505 #define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
AnnaBridge 126:abea610beb85 7506 #define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
AnnaBridge 126:abea610beb85 7507 #define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
AnnaBridge 126:abea610beb85 7508
AnnaBridge 126:abea610beb85 7509 /**
AnnaBridge 126:abea610beb85 7510 * @brief EXTI8 configuration
AnnaBridge 126:abea610beb85 7511 */
AnnaBridge 126:abea610beb85 7512 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
AnnaBridge 126:abea610beb85 7513 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
AnnaBridge 126:abea610beb85 7514 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
AnnaBridge 126:abea610beb85 7515 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
AnnaBridge 126:abea610beb85 7516 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
AnnaBridge 126:abea610beb85 7517 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
AnnaBridge 126:abea610beb85 7518 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
AnnaBridge 126:abea610beb85 7519 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
AnnaBridge 126:abea610beb85 7520 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
AnnaBridge 126:abea610beb85 7521 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
AnnaBridge 126:abea610beb85 7522
AnnaBridge 126:abea610beb85 7523 /**
AnnaBridge 126:abea610beb85 7524 * @brief EXTI9 configuration
AnnaBridge 126:abea610beb85 7525 */
AnnaBridge 126:abea610beb85 7526 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
AnnaBridge 126:abea610beb85 7527 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
AnnaBridge 126:abea610beb85 7528 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
AnnaBridge 126:abea610beb85 7529 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
AnnaBridge 126:abea610beb85 7530 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
AnnaBridge 126:abea610beb85 7531 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
AnnaBridge 126:abea610beb85 7532 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
AnnaBridge 126:abea610beb85 7533 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
AnnaBridge 126:abea610beb85 7534 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
AnnaBridge 126:abea610beb85 7535 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
AnnaBridge 126:abea610beb85 7536
AnnaBridge 126:abea610beb85 7537 /**
AnnaBridge 126:abea610beb85 7538 * @brief EXTI10 configuration
AnnaBridge 126:abea610beb85 7539 */
AnnaBridge 126:abea610beb85 7540 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
AnnaBridge 126:abea610beb85 7541 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
AnnaBridge 126:abea610beb85 7542 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
AnnaBridge 126:abea610beb85 7543 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
AnnaBridge 126:abea610beb85 7544 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
AnnaBridge 126:abea610beb85 7545 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
AnnaBridge 126:abea610beb85 7546 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
AnnaBridge 126:abea610beb85 7547 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
AnnaBridge 126:abea610beb85 7548 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
AnnaBridge 126:abea610beb85 7549 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
AnnaBridge 126:abea610beb85 7550
AnnaBridge 126:abea610beb85 7551 /**
AnnaBridge 126:abea610beb85 7552 * @brief EXTI11 configuration
AnnaBridge 126:abea610beb85 7553 */
AnnaBridge 126:abea610beb85 7554 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
AnnaBridge 126:abea610beb85 7555 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
AnnaBridge 126:abea610beb85 7556 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
AnnaBridge 126:abea610beb85 7557 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
AnnaBridge 126:abea610beb85 7558 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
AnnaBridge 126:abea610beb85 7559 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
AnnaBridge 126:abea610beb85 7560 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
AnnaBridge 126:abea610beb85 7561 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
AnnaBridge 126:abea610beb85 7562 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
AnnaBridge 126:abea610beb85 7563 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
AnnaBridge 126:abea610beb85 7564
AnnaBridge 126:abea610beb85 7565
AnnaBridge 126:abea610beb85 7566 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
AnnaBridge 126:abea610beb85 7567 #define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
AnnaBridge 126:abea610beb85 7568 #define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
AnnaBridge 126:abea610beb85 7569 #define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
AnnaBridge 126:abea610beb85 7570 #define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
AnnaBridge 126:abea610beb85 7571 /**
AnnaBridge 126:abea610beb85 7572 * @brief EXTI12 configuration
AnnaBridge 126:abea610beb85 7573 */
AnnaBridge 126:abea610beb85 7574 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
AnnaBridge 126:abea610beb85 7575 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
AnnaBridge 126:abea610beb85 7576 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
AnnaBridge 126:abea610beb85 7577 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
AnnaBridge 126:abea610beb85 7578 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
AnnaBridge 126:abea610beb85 7579 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
AnnaBridge 126:abea610beb85 7580 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
AnnaBridge 126:abea610beb85 7581 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
AnnaBridge 126:abea610beb85 7582 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
AnnaBridge 126:abea610beb85 7583 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
AnnaBridge 126:abea610beb85 7584
AnnaBridge 126:abea610beb85 7585 /**
AnnaBridge 126:abea610beb85 7586 * @brief EXTI13 configuration
AnnaBridge 126:abea610beb85 7587 */
AnnaBridge 126:abea610beb85 7588 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
AnnaBridge 126:abea610beb85 7589 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
AnnaBridge 126:abea610beb85 7590 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
AnnaBridge 126:abea610beb85 7591 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
AnnaBridge 126:abea610beb85 7592 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
AnnaBridge 126:abea610beb85 7593 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
AnnaBridge 126:abea610beb85 7594 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
AnnaBridge 126:abea610beb85 7595 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
AnnaBridge 126:abea610beb85 7596 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /*!<PI[13] pin */
AnnaBridge 126:abea610beb85 7597 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /*!<PJ[13] pin */
AnnaBridge 126:abea610beb85 7598
AnnaBridge 126:abea610beb85 7599 /**
AnnaBridge 126:abea610beb85 7600 * @brief EXTI14 configuration
AnnaBridge 126:abea610beb85 7601 */
AnnaBridge 126:abea610beb85 7602 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
AnnaBridge 126:abea610beb85 7603 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
AnnaBridge 126:abea610beb85 7604 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
AnnaBridge 126:abea610beb85 7605 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
AnnaBridge 126:abea610beb85 7606 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
AnnaBridge 126:abea610beb85 7607 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
AnnaBridge 126:abea610beb85 7608 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
AnnaBridge 126:abea610beb85 7609 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
AnnaBridge 126:abea610beb85 7610 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
AnnaBridge 126:abea610beb85 7611 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
AnnaBridge 126:abea610beb85 7612
AnnaBridge 126:abea610beb85 7613 /**
AnnaBridge 126:abea610beb85 7614 * @brief EXTI15 configuration
AnnaBridge 126:abea610beb85 7615 */
AnnaBridge 126:abea610beb85 7616 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
AnnaBridge 126:abea610beb85 7617 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
AnnaBridge 126:abea610beb85 7618 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
AnnaBridge 126:abea610beb85 7619 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
AnnaBridge 126:abea610beb85 7620 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
AnnaBridge 126:abea610beb85 7621 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
AnnaBridge 126:abea610beb85 7622 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
AnnaBridge 126:abea610beb85 7623 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
AnnaBridge 126:abea610beb85 7624 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
AnnaBridge 126:abea610beb85 7625 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
AnnaBridge 126:abea610beb85 7626
AnnaBridge 126:abea610beb85 7627 /****************** Bit definition for SYSCFG_CBR register ******************/
AnnaBridge 126:abea610beb85 7628 #define SYSCFG_CBR_CLL 0x00000001U /*!<Core Lockup Lock */
AnnaBridge 126:abea610beb85 7629 #define SYSCFG_CBR_PVDL 0x00000004U /*!<PVD Lock */
AnnaBridge 126:abea610beb85 7630
AnnaBridge 126:abea610beb85 7631 /****************** Bit definition for SYSCFG_CMPCR register ****************/
AnnaBridge 126:abea610beb85 7632 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell power-down */
AnnaBridge 126:abea610beb85 7633 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell ready flag */
AnnaBridge 126:abea610beb85 7634
AnnaBridge 126:abea610beb85 7635 /******************************************************************************/
AnnaBridge 126:abea610beb85 7636 /* */
AnnaBridge 126:abea610beb85 7637 /* TIM */
AnnaBridge 126:abea610beb85 7638 /* */
AnnaBridge 126:abea610beb85 7639 /******************************************************************************/
AnnaBridge 126:abea610beb85 7640 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 126:abea610beb85 7641 #define TIM_CR1_CEN 0x0001U /*!<Counter enable */
AnnaBridge 126:abea610beb85 7642 #define TIM_CR1_UDIS 0x0002U /*!<Update disable */
AnnaBridge 126:abea610beb85 7643 #define TIM_CR1_URS 0x0004U /*!<Update request source */
AnnaBridge 126:abea610beb85 7644 #define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
AnnaBridge 126:abea610beb85 7645 #define TIM_CR1_DIR 0x0010U /*!<Direction */
AnnaBridge 126:abea610beb85 7646
AnnaBridge 126:abea610beb85 7647 #define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 126:abea610beb85 7648 #define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7649 #define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7650
AnnaBridge 126:abea610beb85 7651 #define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
AnnaBridge 126:abea610beb85 7652
AnnaBridge 126:abea610beb85 7653 #define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
AnnaBridge 126:abea610beb85 7654 #define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7655 #define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7656 #define TIM_CR1_UIFREMAP 0x0800U /*!<UIF status bit */
AnnaBridge 126:abea610beb85 7657
AnnaBridge 126:abea610beb85 7658 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 126:abea610beb85 7659 #define TIM_CR2_CCPC 0x00000001U /*!<Capture/Compare Preloaded Control */
AnnaBridge 126:abea610beb85 7660 #define TIM_CR2_CCUS 0x00000004U /*!<Capture/Compare Control Update Selection */
AnnaBridge 126:abea610beb85 7661 #define TIM_CR2_CCDS 0x00000008U /*!<Capture/Compare DMA Selection */
AnnaBridge 126:abea610beb85 7662
AnnaBridge 126:abea610beb85 7663 #define TIM_CR2_OIS5 0x00010000U /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 126:abea610beb85 7664 #define TIM_CR2_OIS6 0x00040000U /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 126:abea610beb85 7665
AnnaBridge 126:abea610beb85 7666 #define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 126:abea610beb85 7667 #define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7668 #define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7669 #define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7670
AnnaBridge 126:abea610beb85 7671 #define TIM_CR2_MMS2 0x00F00000U /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 126:abea610beb85 7672 #define TIM_CR2_MMS2_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7673 #define TIM_CR2_MMS2_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7674 #define TIM_CR2_MMS2_2 0x00400000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7675 #define TIM_CR2_MMS2_3 0x00800000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7676
AnnaBridge 126:abea610beb85 7677 #define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
AnnaBridge 126:abea610beb85 7678 #define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
AnnaBridge 126:abea610beb85 7679 #define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
AnnaBridge 126:abea610beb85 7680 #define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
AnnaBridge 126:abea610beb85 7681 #define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
AnnaBridge 126:abea610beb85 7682 #define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
AnnaBridge 126:abea610beb85 7683 #define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
AnnaBridge 126:abea610beb85 7684 #define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 126:abea610beb85 7685
AnnaBridge 126:abea610beb85 7686 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 126:abea610beb85 7687 #define TIM_SMCR_SMS 0x00010007U /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 126:abea610beb85 7688 #define TIM_SMCR_SMS_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7689 #define TIM_SMCR_SMS_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7690 #define TIM_SMCR_SMS_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7691 #define TIM_SMCR_SMS_3 0x00010000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7692 #define TIM_SMCR_OCCS 0x00000008U /*!< OCREF clear selection */
AnnaBridge 126:abea610beb85 7693
AnnaBridge 126:abea610beb85 7694 #define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 126:abea610beb85 7695 #define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7696 #define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7697 #define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7698
AnnaBridge 126:abea610beb85 7699 #define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
AnnaBridge 126:abea610beb85 7700
AnnaBridge 126:abea610beb85 7701 #define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 126:abea610beb85 7702 #define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7703 #define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7704 #define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7705 #define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7706
AnnaBridge 126:abea610beb85 7707 #define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 126:abea610beb85 7708 #define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7709 #define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7710
AnnaBridge 126:abea610beb85 7711 #define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
AnnaBridge 126:abea610beb85 7712 #define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
AnnaBridge 126:abea610beb85 7713
AnnaBridge 126:abea610beb85 7714 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 126:abea610beb85 7715 #define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
AnnaBridge 126:abea610beb85 7716 #define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 126:abea610beb85 7717 #define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 126:abea610beb85 7718 #define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 126:abea610beb85 7719 #define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 126:abea610beb85 7720 #define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
AnnaBridge 126:abea610beb85 7721 #define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
AnnaBridge 126:abea610beb85 7722 #define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
AnnaBridge 126:abea610beb85 7723 #define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
AnnaBridge 126:abea610beb85 7724 #define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 126:abea610beb85 7725 #define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 126:abea610beb85 7726 #define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 126:abea610beb85 7727 #define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 126:abea610beb85 7728 #define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
AnnaBridge 126:abea610beb85 7729 #define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
AnnaBridge 126:abea610beb85 7730
AnnaBridge 126:abea610beb85 7731 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 126:abea610beb85 7732 #define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
AnnaBridge 126:abea610beb85 7733 #define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 126:abea610beb85 7734 #define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 126:abea610beb85 7735 #define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 126:abea610beb85 7736 #define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 126:abea610beb85 7737 #define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
AnnaBridge 126:abea610beb85 7738 #define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
AnnaBridge 126:abea610beb85 7739 #define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
AnnaBridge 126:abea610beb85 7740 #define TIM_SR_B2IF 0x0100U /*!<Break2 interrupt Flag */
AnnaBridge 126:abea610beb85 7741 #define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 126:abea610beb85 7742 #define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 126:abea610beb85 7743 #define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 126:abea610beb85 7744 #define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
AnnaBridge 126:abea610beb85 7745
AnnaBridge 126:abea610beb85 7746 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 126:abea610beb85 7747 #define TIM_EGR_UG 0x00000001U /*!<Update Generation */
AnnaBridge 126:abea610beb85 7748 #define TIM_EGR_CC1G 0x00000002U /*!<Capture/Compare 1 Generation */
AnnaBridge 126:abea610beb85 7749 #define TIM_EGR_CC2G 0x00000004U /*!<Capture/Compare 2 Generation */
AnnaBridge 126:abea610beb85 7750 #define TIM_EGR_CC3G 0x00000008U /*!<Capture/Compare 3 Generation */
AnnaBridge 126:abea610beb85 7751 #define TIM_EGR_CC4G 0x00000010U /*!<Capture/Compare 4 Generation */
AnnaBridge 126:abea610beb85 7752 #define TIM_EGR_COMG 0x00000020U /*!<Capture/Compare Control Update Generation */
AnnaBridge 126:abea610beb85 7753 #define TIM_EGR_TG 0x00000040U /*!<Trigger Generation */
AnnaBridge 126:abea610beb85 7754 #define TIM_EGR_BG 0x00000080U /*!<Break Generation */
AnnaBridge 126:abea610beb85 7755 #define TIM_EGR_B2G 0x00000100U /*!<Break2 Generation */
AnnaBridge 126:abea610beb85 7756
AnnaBridge 126:abea610beb85 7757 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 126:abea610beb85 7758 #define TIM_CCMR1_CC1S 0x00000003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 126:abea610beb85 7759 #define TIM_CCMR1_CC1S_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7760 #define TIM_CCMR1_CC1S_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7761
AnnaBridge 126:abea610beb85 7762 #define TIM_CCMR1_OC1FE 0x00000004U /*!<Output Compare 1 Fast enable */
AnnaBridge 126:abea610beb85 7763 #define TIM_CCMR1_OC1PE 0x00000008U /*!<Output Compare 1 Preload enable */
AnnaBridge 126:abea610beb85 7764
AnnaBridge 126:abea610beb85 7765 #define TIM_CCMR1_OC1M 0x00010070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 126:abea610beb85 7766 #define TIM_CCMR1_OC1M_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7767 #define TIM_CCMR1_OC1M_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7768 #define TIM_CCMR1_OC1M_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7769 #define TIM_CCMR1_OC1M_3 0x00010000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7770
AnnaBridge 126:abea610beb85 7771 #define TIM_CCMR1_OC1CE 0x00000080U /*!<Output Compare 1Clear Enable */
AnnaBridge 126:abea610beb85 7772
AnnaBridge 126:abea610beb85 7773 #define TIM_CCMR1_CC2S 0x00000300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 126:abea610beb85 7774 #define TIM_CCMR1_CC2S_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7775 #define TIM_CCMR1_CC2S_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7776
AnnaBridge 126:abea610beb85 7777 #define TIM_CCMR1_OC2FE 0x00000400U /*!<Output Compare 2 Fast enable */
AnnaBridge 126:abea610beb85 7778 #define TIM_CCMR1_OC2PE 0x00000800U /*!<Output Compare 2 Preload enable */
AnnaBridge 126:abea610beb85 7779
AnnaBridge 126:abea610beb85 7780 #define TIM_CCMR1_OC2M 0x01007000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 126:abea610beb85 7781 #define TIM_CCMR1_OC2M_0 0x00001000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7782 #define TIM_CCMR1_OC2M_1 0x00002000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7783 #define TIM_CCMR1_OC2M_2 0x00004000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7784 #define TIM_CCMR1_OC2M_3 0x01000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7785
AnnaBridge 126:abea610beb85 7786 #define TIM_CCMR1_OC2CE 0x00008000U /*!<Output Compare 2 Clear Enable */
AnnaBridge 126:abea610beb85 7787
AnnaBridge 126:abea610beb85 7788 /*----------------------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 7789
AnnaBridge 126:abea610beb85 7790 #define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 126:abea610beb85 7791 #define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7792 #define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7793
AnnaBridge 126:abea610beb85 7794 #define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 126:abea610beb85 7795 #define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7796 #define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7797 #define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7798 #define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7799
AnnaBridge 126:abea610beb85 7800 #define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 126:abea610beb85 7801 #define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7802 #define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7803
AnnaBridge 126:abea610beb85 7804 #define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 126:abea610beb85 7805 #define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7806 #define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7807 #define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7808 #define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7809
AnnaBridge 126:abea610beb85 7810 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 126:abea610beb85 7811 #define TIM_CCMR2_CC3S 0x00000003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 126:abea610beb85 7812 #define TIM_CCMR2_CC3S_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7813 #define TIM_CCMR2_CC3S_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7814
AnnaBridge 126:abea610beb85 7815 #define TIM_CCMR2_OC3FE 0x00000004U /*!<Output Compare 3 Fast enable */
AnnaBridge 126:abea610beb85 7816 #define TIM_CCMR2_OC3PE 0x00000008U /*!<Output Compare 3 Preload enable */
AnnaBridge 126:abea610beb85 7817
AnnaBridge 126:abea610beb85 7818 #define TIM_CCMR2_OC3M 0x00010070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 126:abea610beb85 7819 #define TIM_CCMR2_OC3M_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7820 #define TIM_CCMR2_OC3M_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7821 #define TIM_CCMR2_OC3M_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7822 #define TIM_CCMR2_OC3M_3 0x00010000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7823
AnnaBridge 126:abea610beb85 7824
AnnaBridge 126:abea610beb85 7825
AnnaBridge 126:abea610beb85 7826 #define TIM_CCMR2_OC3CE 0x00000080U /*!<Output Compare 3 Clear Enable */
AnnaBridge 126:abea610beb85 7827
AnnaBridge 126:abea610beb85 7828 #define TIM_CCMR2_CC4S 0x00000300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 126:abea610beb85 7829 #define TIM_CCMR2_CC4S_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7830 #define TIM_CCMR2_CC4S_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7831
AnnaBridge 126:abea610beb85 7832 #define TIM_CCMR2_OC4FE 0x00000400U /*!<Output Compare 4 Fast enable */
AnnaBridge 126:abea610beb85 7833 #define TIM_CCMR2_OC4PE 0x00000800U /*!<Output Compare 4 Preload enable */
AnnaBridge 126:abea610beb85 7834
AnnaBridge 126:abea610beb85 7835 #define TIM_CCMR2_OC4M 0x01007000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 126:abea610beb85 7836 #define TIM_CCMR2_OC4M_0 0x00001000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7837 #define TIM_CCMR2_OC4M_1 0x00002000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7838 #define TIM_CCMR2_OC4M_2 0x00004000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7839 #define TIM_CCMR2_OC4M_3 0x01000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7840
AnnaBridge 126:abea610beb85 7841 #define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
AnnaBridge 126:abea610beb85 7842
AnnaBridge 126:abea610beb85 7843 /*----------------------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 7844
AnnaBridge 126:abea610beb85 7845 #define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 126:abea610beb85 7846 #define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7847 #define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7848
AnnaBridge 126:abea610beb85 7849 #define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 126:abea610beb85 7850 #define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7851 #define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7852 #define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7853 #define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7854
AnnaBridge 126:abea610beb85 7855 #define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 126:abea610beb85 7856 #define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7857 #define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7858
AnnaBridge 126:abea610beb85 7859 #define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 126:abea610beb85 7860 #define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7861 #define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7862 #define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7863 #define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7864
AnnaBridge 126:abea610beb85 7865 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 126:abea610beb85 7866 #define TIM_CCER_CC1E 0x00000001U /*!<Capture/Compare 1 output enable */
AnnaBridge 126:abea610beb85 7867 #define TIM_CCER_CC1P 0x00000002U /*!<Capture/Compare 1 output Polarity */
AnnaBridge 126:abea610beb85 7868 #define TIM_CCER_CC1NE 0x00000004U /*!<Capture/Compare 1 Complementary output enable */
AnnaBridge 126:abea610beb85 7869 #define TIM_CCER_CC1NP 0x00000008U /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 126:abea610beb85 7870 #define TIM_CCER_CC2E 0x00000010U /*!<Capture/Compare 2 output enable */
AnnaBridge 126:abea610beb85 7871 #define TIM_CCER_CC2P 0x00000020U /*!<Capture/Compare 2 output Polarity */
AnnaBridge 126:abea610beb85 7872 #define TIM_CCER_CC2NE 0x00000040U /*!<Capture/Compare 2 Complementary output enable */
AnnaBridge 126:abea610beb85 7873 #define TIM_CCER_CC2NP 0x00000080U /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 126:abea610beb85 7874 #define TIM_CCER_CC3E 0x00000100U /*!<Capture/Compare 3 output enable */
AnnaBridge 126:abea610beb85 7875 #define TIM_CCER_CC3P 0x00000200U /*!<Capture/Compare 3 output Polarity */
AnnaBridge 126:abea610beb85 7876 #define TIM_CCER_CC3NE 0x00000400U /*!<Capture/Compare 3 Complementary output enable */
AnnaBridge 126:abea610beb85 7877 #define TIM_CCER_CC3NP 0x00000800U /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 126:abea610beb85 7878 #define TIM_CCER_CC4E 0x00001000U /*!<Capture/Compare 4 output enable */
AnnaBridge 126:abea610beb85 7879 #define TIM_CCER_CC4P 0x00002000U /*!<Capture/Compare 4 output Polarity */
AnnaBridge 126:abea610beb85 7880 #define TIM_CCER_CC4NP 0x00008000U /*!<Capture/Compare 4 Complementary output Polarity */
AnnaBridge 126:abea610beb85 7881 #define TIM_CCER_CC5E 0x00010000U /*!<Capture/Compare 5 output enable */
AnnaBridge 126:abea610beb85 7882 #define TIM_CCER_CC5P 0x00020000U /*!<Capture/Compare 5 output Polarity */
AnnaBridge 126:abea610beb85 7883 #define TIM_CCER_CC6E 0x00100000U /*!<Capture/Compare 6 output enable */
AnnaBridge 126:abea610beb85 7884 #define TIM_CCER_CC6P 0x00200000U /*!<Capture/Compare 6 output Polarity */
AnnaBridge 126:abea610beb85 7885
AnnaBridge 126:abea610beb85 7886
AnnaBridge 126:abea610beb85 7887 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 126:abea610beb85 7888 #define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
AnnaBridge 126:abea610beb85 7889
AnnaBridge 126:abea610beb85 7890 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 126:abea610beb85 7891 #define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
AnnaBridge 126:abea610beb85 7892
AnnaBridge 126:abea610beb85 7893 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 126:abea610beb85 7894 #define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
AnnaBridge 126:abea610beb85 7895
AnnaBridge 126:abea610beb85 7896 /******************* Bit definition for TIM_RCR register ********************/
AnnaBridge 126:abea610beb85 7897 #define TIM_RCR_REP ((uint8_t)0xFFU) /*!<Repetition Counter Value */
AnnaBridge 126:abea610beb85 7898
AnnaBridge 126:abea610beb85 7899 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 126:abea610beb85 7900 #define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
AnnaBridge 126:abea610beb85 7901
AnnaBridge 126:abea610beb85 7902 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 126:abea610beb85 7903 #define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
AnnaBridge 126:abea610beb85 7904
AnnaBridge 126:abea610beb85 7905 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 126:abea610beb85 7906 #define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
AnnaBridge 126:abea610beb85 7907
AnnaBridge 126:abea610beb85 7908 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 126:abea610beb85 7909 #define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
AnnaBridge 126:abea610beb85 7910
AnnaBridge 126:abea610beb85 7911 /******************* Bit definition for TIM_BDTR register *******************/
AnnaBridge 126:abea610beb85 7912 #define TIM_BDTR_DTG 0x000000FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
AnnaBridge 126:abea610beb85 7913 #define TIM_BDTR_DTG_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7914 #define TIM_BDTR_DTG_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7915 #define TIM_BDTR_DTG_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7916 #define TIM_BDTR_DTG_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7917 #define TIM_BDTR_DTG_4 0x00000010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 7918 #define TIM_BDTR_DTG_5 0x00000020U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 7919 #define TIM_BDTR_DTG_6 0x00000040U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 7920 #define TIM_BDTR_DTG_7 0x00000080U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 7921
AnnaBridge 126:abea610beb85 7922 #define TIM_BDTR_LOCK 0x00000300U /*!<LOCK[1:0] bits (Lock Configuration) */
AnnaBridge 126:abea610beb85 7923 #define TIM_BDTR_LOCK_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7924 #define TIM_BDTR_LOCK_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7925
AnnaBridge 126:abea610beb85 7926 #define TIM_BDTR_OSSI 0x00000400U /*!<Off-State Selection for Idle mode */
AnnaBridge 126:abea610beb85 7927 #define TIM_BDTR_OSSR 0x00000800U /*!<Off-State Selection for Run mode */
AnnaBridge 126:abea610beb85 7928 #define TIM_BDTR_BKE 0x00001000U /*!<Break enable */
AnnaBridge 126:abea610beb85 7929 #define TIM_BDTR_BKP 0x00002000U /*!<Break Polarity */
AnnaBridge 126:abea610beb85 7930 #define TIM_BDTR_AOE 0x00004000U /*!<Automatic Output enable */
AnnaBridge 126:abea610beb85 7931 #define TIM_BDTR_MOE 0x00008000U /*!<Main Output enable */
AnnaBridge 126:abea610beb85 7932 #define TIM_BDTR_BKF 0x000F0000U /*!<Break Filter for Break1 */
AnnaBridge 126:abea610beb85 7933 #define TIM_BDTR_BK2F 0x00F00000U /*!<Break Filter for Break2 */
AnnaBridge 126:abea610beb85 7934 #define TIM_BDTR_BK2E 0x01000000U /*!<Break enable for Break2 */
AnnaBridge 126:abea610beb85 7935 #define TIM_BDTR_BK2P 0x02000000U /*!<Break Polarity for Break2 */
AnnaBridge 126:abea610beb85 7936
AnnaBridge 126:abea610beb85 7937 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 126:abea610beb85 7938 #define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 126:abea610beb85 7939 #define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7940 #define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7941 #define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7942 #define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7943 #define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 7944
AnnaBridge 126:abea610beb85 7945 #define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 126:abea610beb85 7946 #define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7947 #define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7948 #define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7949 #define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7950 #define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 7951
AnnaBridge 126:abea610beb85 7952 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 126:abea610beb85 7953 #define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
AnnaBridge 126:abea610beb85 7954
AnnaBridge 126:abea610beb85 7955 /******************* Bit definition for TIM_OR regiter *********************/
AnnaBridge 126:abea610beb85 7956 #define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
AnnaBridge 126:abea610beb85 7957 #define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7958 #define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7959 #define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
AnnaBridge 126:abea610beb85 7960 #define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7961 #define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7962
AnnaBridge 126:abea610beb85 7963 /****************** Bit definition for TIM_CCMR3 register *******************/
AnnaBridge 126:abea610beb85 7964 #define TIM_CCMR3_OC5FE 0x00000004U /*!<Output Compare 5 Fast enable */
AnnaBridge 126:abea610beb85 7965 #define TIM_CCMR3_OC5PE 0x00000008U /*!<Output Compare 5 Preload enable */
AnnaBridge 126:abea610beb85 7966
AnnaBridge 126:abea610beb85 7967 #define TIM_CCMR3_OC5M 0x00010070U /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
AnnaBridge 126:abea610beb85 7968 #define TIM_CCMR3_OC5M_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7969 #define TIM_CCMR3_OC5M_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7970 #define TIM_CCMR3_OC5M_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7971 #define TIM_CCMR3_OC5M_3 0x00010000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7972
AnnaBridge 126:abea610beb85 7973 #define TIM_CCMR3_OC5CE 0x00000080U /*!<Output Compare 5 Clear Enable */
AnnaBridge 126:abea610beb85 7974
AnnaBridge 126:abea610beb85 7975 #define TIM_CCMR3_OC6FE 0x00000400U /*!<Output Compare 4 Fast enable */
AnnaBridge 126:abea610beb85 7976 #define TIM_CCMR3_OC6PE 0x00000800U /*!<Output Compare 4 Preload enable */
AnnaBridge 126:abea610beb85 7977
AnnaBridge 126:abea610beb85 7978 #define TIM_CCMR3_OC6M 0x01007000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 126:abea610beb85 7979 #define TIM_CCMR3_OC6M_0 0x00001000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 7980 #define TIM_CCMR3_OC6M_1 0x00002000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 7981 #define TIM_CCMR3_OC6M_2 0x00004000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 7982 #define TIM_CCMR3_OC6M_3 0x01000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 7983
AnnaBridge 126:abea610beb85 7984 #define TIM_CCMR3_OC6CE 0x00008000U /*!<Output Compare 4 Clear Enable */
AnnaBridge 126:abea610beb85 7985
AnnaBridge 126:abea610beb85 7986 /******************* Bit definition for TIM_CCR5 register *******************/
AnnaBridge 126:abea610beb85 7987 #define TIM_CCR5_CCR5 0xFFFFFFFFU /*!<Capture/Compare 5 Value */
AnnaBridge 126:abea610beb85 7988 #define TIM_CCR5_GC5C1 0x20000000U /*!<Group Channel 5 and Channel 1 */
AnnaBridge 126:abea610beb85 7989 #define TIM_CCR5_GC5C2 0x40000000U /*!<Group Channel 5 and Channel 2 */
AnnaBridge 126:abea610beb85 7990 #define TIM_CCR5_GC5C3 0x80000000U /*!<Group Channel 5 and Channel 3 */
AnnaBridge 126:abea610beb85 7991
AnnaBridge 126:abea610beb85 7992 /******************* Bit definition for TIM_CCR6 register *******************/
AnnaBridge 126:abea610beb85 7993 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /*!<Capture/Compare 6 Value */
AnnaBridge 126:abea610beb85 7994
AnnaBridge 126:abea610beb85 7995 /******************* Bit definition for TIM1_AF1 register *******************/
AnnaBridge 126:abea610beb85 7996 #define TIM1_AF1_BKINE 0x00000001U /*!<BRK BKIN input enable */
AnnaBridge 126:abea610beb85 7997 #define TIM1_AF1_BKDF1BKE 0x00000100U /*!<BRK DFSDM1_BREAK enable */
AnnaBridge 126:abea610beb85 7998
AnnaBridge 126:abea610beb85 7999 /******************* Bit definition for TIM1_AF2 register *******************/
AnnaBridge 126:abea610beb85 8000 #define TIM1_AF2_BK2INE 0x00000001U /*!<BRK2 BKIN input enable */
AnnaBridge 126:abea610beb85 8001 #define TIM1_AF2_BK2DF1BKE 0x00000100U /*!<BRK2 DFSDM1_BREAK enable */
AnnaBridge 126:abea610beb85 8002
AnnaBridge 126:abea610beb85 8003 /******************* Bit definition for TIM8_AF1 register *******************/
AnnaBridge 126:abea610beb85 8004 #define TIM8_AF1_BKINE 0x00000001U /*!<BRK BKIN input enable */
AnnaBridge 126:abea610beb85 8005 #define TIM8_AF1_BKDF1BKE 0x00000100U /*!<BRK DFSDM1_BREAK enable */
AnnaBridge 126:abea610beb85 8006
AnnaBridge 126:abea610beb85 8007 /******************* Bit definition for TIM8_AF2 register *******************/
AnnaBridge 126:abea610beb85 8008 #define TIM8_AF2_BK2INE 0x00000001U /*!<BRK2 BKIN2 input enable */
AnnaBridge 126:abea610beb85 8009 #define TIM8_AF2_BK2DF1BKE 0x00000100U /*!<BRK2 DFSDM1_BREAK enable */
AnnaBridge 126:abea610beb85 8010
AnnaBridge 126:abea610beb85 8011 /******************************************************************************/
AnnaBridge 126:abea610beb85 8012 /* */
AnnaBridge 126:abea610beb85 8013 /* Low Power Timer (LPTIM) */
AnnaBridge 126:abea610beb85 8014 /* */
AnnaBridge 126:abea610beb85 8015 /******************************************************************************/
AnnaBridge 126:abea610beb85 8016 /****************** Bit definition for LPTIM_ISR register *******************/
AnnaBridge 126:abea610beb85 8017 #define LPTIM_ISR_CMPM 0x00000001U /*!< Compare match */
AnnaBridge 126:abea610beb85 8018 #define LPTIM_ISR_ARRM 0x00000002U /*!< Autoreload match */
AnnaBridge 126:abea610beb85 8019 #define LPTIM_ISR_EXTTRIG 0x00000004U /*!< External trigger edge event */
AnnaBridge 126:abea610beb85 8020 #define LPTIM_ISR_CMPOK 0x00000008U /*!< Compare register update OK */
AnnaBridge 126:abea610beb85 8021 #define LPTIM_ISR_ARROK 0x00000010U /*!< Autoreload register update OK */
AnnaBridge 126:abea610beb85 8022 #define LPTIM_ISR_UP 0x00000020U /*!< Counter direction change down to up */
AnnaBridge 126:abea610beb85 8023 #define LPTIM_ISR_DOWN 0x00000040U /*!< Counter direction change up to down */
AnnaBridge 126:abea610beb85 8024
AnnaBridge 126:abea610beb85 8025 /****************** Bit definition for LPTIM_ICR register *******************/
AnnaBridge 126:abea610beb85 8026 #define LPTIM_ICR_CMPMCF 0x00000001U /*!< Compare match Clear Flag */
AnnaBridge 126:abea610beb85 8027 #define LPTIM_ICR_ARRMCF 0x00000002U /*!< Autoreload match Clear Flag */
AnnaBridge 126:abea610beb85 8028 #define LPTIM_ICR_EXTTRIGCF 0x00000004U /*!< External trigger edge event Clear Flag */
AnnaBridge 126:abea610beb85 8029 #define LPTIM_ICR_CMPOKCF 0x00000008U /*!< Compare register update OK Clear Flag */
AnnaBridge 126:abea610beb85 8030 #define LPTIM_ICR_ARROKCF 0x00000010U /*!< Autoreload register update OK Clear Flag */
AnnaBridge 126:abea610beb85 8031 #define LPTIM_ICR_UPCF 0x00000020U /*!< Counter direction change down to up Clear Flag */
AnnaBridge 126:abea610beb85 8032 #define LPTIM_ICR_DOWNCF 0x00000040U /*!< Counter direction change up to down Clear Flag */
AnnaBridge 126:abea610beb85 8033
AnnaBridge 126:abea610beb85 8034 /****************** Bit definition for LPTIM_IER register *******************/
AnnaBridge 126:abea610beb85 8035 #define LPTIM_IER_CMPMIE 0x00000001U /*!< Compare match Interrupt Enable */
AnnaBridge 126:abea610beb85 8036 #define LPTIM_IER_ARRMIE 0x00000002U /*!< Autoreload match Interrupt Enable */
AnnaBridge 126:abea610beb85 8037 #define LPTIM_IER_EXTTRIGIE 0x00000004U /*!< External trigger edge event Interrupt Enable */
AnnaBridge 126:abea610beb85 8038 #define LPTIM_IER_CMPOKIE 0x00000008U /*!< Compare register update OK Interrupt Enable */
AnnaBridge 126:abea610beb85 8039 #define LPTIM_IER_ARROKIE 0x00000010U /*!< Autoreload register update OK Interrupt Enable */
AnnaBridge 126:abea610beb85 8040 #define LPTIM_IER_UPIE 0x00000020U /*!< Counter direction change down to up Interrupt Enable */
AnnaBridge 126:abea610beb85 8041 #define LPTIM_IER_DOWNIE 0x00000040U /*!< Counter direction change up to down Interrupt Enable */
AnnaBridge 126:abea610beb85 8042
AnnaBridge 126:abea610beb85 8043 /****************** Bit definition for LPTIM_CFGR register*******************/
AnnaBridge 126:abea610beb85 8044 #define LPTIM_CFGR_CKSEL 0x00000001U /*!< Clock selector */
AnnaBridge 126:abea610beb85 8045
AnnaBridge 126:abea610beb85 8046 #define LPTIM_CFGR_CKPOL 0x00000006U /*!< CKPOL[1:0] bits (Clock polarity) */
AnnaBridge 126:abea610beb85 8047 #define LPTIM_CFGR_CKPOL_0 0x00000002U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 8048 #define LPTIM_CFGR_CKPOL_1 0x00000004U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 8049
AnnaBridge 126:abea610beb85 8050 #define LPTIM_CFGR_CKFLT 0x00000018U /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
AnnaBridge 126:abea610beb85 8051 #define LPTIM_CFGR_CKFLT_0 0x00000008U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 8052 #define LPTIM_CFGR_CKFLT_1 0x00000010U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 8053
AnnaBridge 126:abea610beb85 8054 #define LPTIM_CFGR_TRGFLT 0x000000C0U /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
AnnaBridge 126:abea610beb85 8055 #define LPTIM_CFGR_TRGFLT_0 0x00000040U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 8056 #define LPTIM_CFGR_TRGFLT_1 0x00000080U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 8057
AnnaBridge 126:abea610beb85 8058 #define LPTIM_CFGR_PRESC 0x00000E00U /*!< PRESC[2:0] bits (Clock prescaler) */
AnnaBridge 126:abea610beb85 8059 #define LPTIM_CFGR_PRESC_0 0x00000200U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 8060 #define LPTIM_CFGR_PRESC_1 0x00000400U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 8061 #define LPTIM_CFGR_PRESC_2 0x00000800U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 8062
AnnaBridge 126:abea610beb85 8063 #define LPTIM_CFGR_TRIGSEL 0x0000E000U /*!< TRIGSEL[2:0]] bits (Trigger selector) */
AnnaBridge 126:abea610beb85 8064 #define LPTIM_CFGR_TRIGSEL_0 0x00002000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 8065 #define LPTIM_CFGR_TRIGSEL_1 0x00004000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 8066 #define LPTIM_CFGR_TRIGSEL_2 0x00008000U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 8067
AnnaBridge 126:abea610beb85 8068 #define LPTIM_CFGR_TRIGEN 0x00060000U /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
AnnaBridge 126:abea610beb85 8069 #define LPTIM_CFGR_TRIGEN_0 0x00020000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 8070 #define LPTIM_CFGR_TRIGEN_1 0x00040000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 8071
AnnaBridge 126:abea610beb85 8072 #define LPTIM_CFGR_TIMOUT 0x00080000U /*!< Timout enable */
AnnaBridge 126:abea610beb85 8073 #define LPTIM_CFGR_WAVE 0x00100000U /*!< Waveform shape */
AnnaBridge 126:abea610beb85 8074 #define LPTIM_CFGR_WAVPOL 0x00200000U /*!< Waveform shape polarity */
AnnaBridge 126:abea610beb85 8075 #define LPTIM_CFGR_PRELOAD 0x00400000U /*!< Reg update mode */
AnnaBridge 126:abea610beb85 8076 #define LPTIM_CFGR_COUNTMODE 0x00800000U /*!< Counter mode enable */
AnnaBridge 126:abea610beb85 8077 #define LPTIM_CFGR_ENC 0x01000000U /*!< Encoder mode enable */
AnnaBridge 126:abea610beb85 8078
AnnaBridge 126:abea610beb85 8079 /****************** Bit definition for LPTIM_CR register ********************/
AnnaBridge 126:abea610beb85 8080 #define LPTIM_CR_ENABLE 0x00000001U /*!< LPTIMer enable */
AnnaBridge 126:abea610beb85 8081 #define LPTIM_CR_SNGSTRT 0x00000002U /*!< Timer start in single mode */
AnnaBridge 126:abea610beb85 8082 #define LPTIM_CR_CNTSTRT 0x00000004U /*!< Timer start in continuous mode */
AnnaBridge 126:abea610beb85 8083
AnnaBridge 126:abea610beb85 8084 /****************** Bit definition for LPTIM_CMP register *******************/
AnnaBridge 126:abea610beb85 8085 #define LPTIM_CMP_CMP 0x0000FFFFU /*!< Compare register */
AnnaBridge 126:abea610beb85 8086
AnnaBridge 126:abea610beb85 8087 /****************** Bit definition for LPTIM_ARR register *******************/
AnnaBridge 126:abea610beb85 8088 #define LPTIM_ARR_ARR 0x0000FFFFU /*!< Auto reload register */
AnnaBridge 126:abea610beb85 8089
AnnaBridge 126:abea610beb85 8090 /****************** Bit definition for LPTIM_CNT register *******************/
AnnaBridge 126:abea610beb85 8091 #define LPTIM_CNT_CNT 0x0000FFFFU /*!< Counter register */
AnnaBridge 126:abea610beb85 8092 /******************************************************************************/
AnnaBridge 126:abea610beb85 8093 /* */
AnnaBridge 126:abea610beb85 8094 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
AnnaBridge 126:abea610beb85 8095 /* */
AnnaBridge 126:abea610beb85 8096 /******************************************************************************/
AnnaBridge 126:abea610beb85 8097 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 126:abea610beb85 8098 #define USART_CR1_UE 0x00000001U /*!< USART Enable */
AnnaBridge 126:abea610beb85 8099 #define USART_CR1_RE 0x00000004U /*!< Receiver Enable */
AnnaBridge 126:abea610beb85 8100 #define USART_CR1_TE 0x00000008U /*!< Transmitter Enable */
AnnaBridge 126:abea610beb85 8101 #define USART_CR1_IDLEIE 0x00000010U /*!< IDLE Interrupt Enable */
AnnaBridge 126:abea610beb85 8102 #define USART_CR1_RXNEIE 0x00000020U /*!< RXNE Interrupt Enable */
AnnaBridge 126:abea610beb85 8103 #define USART_CR1_TCIE 0x00000040U /*!< Transmission Complete Interrupt Enable */
AnnaBridge 126:abea610beb85 8104 #define USART_CR1_TXEIE 0x00000080U /*!< TXE Interrupt Enable */
AnnaBridge 126:abea610beb85 8105 #define USART_CR1_PEIE 0x00000100U /*!< PE Interrupt Enable */
AnnaBridge 126:abea610beb85 8106 #define USART_CR1_PS 0x00000200U /*!< Parity Selection */
AnnaBridge 126:abea610beb85 8107 #define USART_CR1_PCE 0x00000400U /*!< Parity Control Enable */
AnnaBridge 126:abea610beb85 8108 #define USART_CR1_WAKE 0x00000800U /*!< Receiver Wakeup method */
AnnaBridge 126:abea610beb85 8109 #define USART_CR1_M 0x10001000U /*!< Word length */
AnnaBridge 126:abea610beb85 8110 #define USART_CR1_M_0 0x00001000U /*!< Word length - Bit 0 */
AnnaBridge 126:abea610beb85 8111 #define USART_CR1_MME 0x00002000U /*!< Mute Mode Enable */
AnnaBridge 126:abea610beb85 8112 #define USART_CR1_CMIE 0x00004000U /*!< Character match interrupt enable */
AnnaBridge 126:abea610beb85 8113 #define USART_CR1_OVER8 0x00008000U /*!< Oversampling by 8-bit or 16-bit mode */
AnnaBridge 126:abea610beb85 8114 #define USART_CR1_DEDT 0x001F0000U /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
AnnaBridge 126:abea610beb85 8115 #define USART_CR1_DEDT_0 0x00010000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 8116 #define USART_CR1_DEDT_1 0x00020000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 8117 #define USART_CR1_DEDT_2 0x00040000U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 8118 #define USART_CR1_DEDT_3 0x00080000U /*!< Bit 3 */
AnnaBridge 126:abea610beb85 8119 #define USART_CR1_DEDT_4 0x00100000U /*!< Bit 4 */
AnnaBridge 126:abea610beb85 8120 #define USART_CR1_DEAT 0x03E00000U /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
AnnaBridge 126:abea610beb85 8121 #define USART_CR1_DEAT_0 0x00200000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 8122 #define USART_CR1_DEAT_1 0x00400000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 8123 #define USART_CR1_DEAT_2 0x00800000U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 8124 #define USART_CR1_DEAT_3 0x01000000U /*!< Bit 3 */
AnnaBridge 126:abea610beb85 8125 #define USART_CR1_DEAT_4 0x02000000U /*!< Bit 4 */
AnnaBridge 126:abea610beb85 8126 #define USART_CR1_RTOIE 0x04000000U /*!< Receive Time Out interrupt enable */
AnnaBridge 126:abea610beb85 8127 #define USART_CR1_EOBIE 0x08000000U /*!< End of Block interrupt enable */
AnnaBridge 126:abea610beb85 8128 #define USART_CR1_M_1 0x10000000U /*!< Word length - Bit 1 */
AnnaBridge 126:abea610beb85 8129
AnnaBridge 126:abea610beb85 8130 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 126:abea610beb85 8131 #define USART_CR2_ADDM7 0x00000010U /*!< 7-bit or 4-bit Address Detection */
AnnaBridge 126:abea610beb85 8132 #define USART_CR2_LBDL 0x00000020U /*!< LIN Break Detection Length */
AnnaBridge 126:abea610beb85 8133 #define USART_CR2_LBDIE 0x00000040U /*!< LIN Break Detection Interrupt Enable */
AnnaBridge 126:abea610beb85 8134 #define USART_CR2_LBCL 0x00000100U /*!< Last Bit Clock pulse */
AnnaBridge 126:abea610beb85 8135 #define USART_CR2_CPHA 0x00000200U /*!< Clock Phase */
AnnaBridge 126:abea610beb85 8136 #define USART_CR2_CPOL 0x00000400U /*!< Clock Polarity */
AnnaBridge 126:abea610beb85 8137 #define USART_CR2_CLKEN 0x00000800U /*!< Clock Enable */
AnnaBridge 126:abea610beb85 8138 #define USART_CR2_STOP 0x00003000U /*!< STOP[1:0] bits (STOP bits) */
AnnaBridge 126:abea610beb85 8139 #define USART_CR2_STOP_0 0x00001000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 8140 #define USART_CR2_STOP_1 0x00002000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 8141 #define USART_CR2_LINEN 0x00004000U /*!< LIN mode enable */
AnnaBridge 126:abea610beb85 8142 #define USART_CR2_SWAP 0x00008000U /*!< SWAP TX/RX pins */
AnnaBridge 126:abea610beb85 8143 #define USART_CR2_RXINV 0x00010000U /*!< RX pin active level inversion */
AnnaBridge 126:abea610beb85 8144 #define USART_CR2_TXINV 0x00020000U /*!< TX pin active level inversion */
AnnaBridge 126:abea610beb85 8145 #define USART_CR2_DATAINV 0x00040000U /*!< Binary data inversion */
AnnaBridge 126:abea610beb85 8146 #define USART_CR2_MSBFIRST 0x00080000U /*!< Most Significant Bit First */
AnnaBridge 126:abea610beb85 8147 #define USART_CR2_ABREN 0x00100000U /*!< Auto Baud-Rate Enable */
AnnaBridge 126:abea610beb85 8148 #define USART_CR2_ABRMODE 0x00600000U /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
AnnaBridge 126:abea610beb85 8149 #define USART_CR2_ABRMODE_0 0x00200000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 8150 #define USART_CR2_ABRMODE_1 0x00400000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 8151 #define USART_CR2_RTOEN 0x00800000U /*!< Receiver Time-Out enable */
AnnaBridge 126:abea610beb85 8152 #define USART_CR2_ADD 0xFF000000U /*!< Address of the USART node */
AnnaBridge 126:abea610beb85 8153
AnnaBridge 126:abea610beb85 8154 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 126:abea610beb85 8155 #define USART_CR3_EIE 0x00000001U /*!< Error Interrupt Enable */
AnnaBridge 126:abea610beb85 8156 #define USART_CR3_IREN 0x00000002U /*!< IrDA mode Enable */
AnnaBridge 126:abea610beb85 8157 #define USART_CR3_IRLP 0x00000004U /*!< IrDA Low-Power */
AnnaBridge 126:abea610beb85 8158 #define USART_CR3_HDSEL 0x00000008U /*!< Half-Duplex Selection */
AnnaBridge 126:abea610beb85 8159 #define USART_CR3_NACK 0x00000010U /*!< SmartCard NACK enable */
AnnaBridge 126:abea610beb85 8160 #define USART_CR3_SCEN 0x00000020U /*!< SmartCard mode enable */
AnnaBridge 126:abea610beb85 8161 #define USART_CR3_DMAR 0x00000040U /*!< DMA Enable Receiver */
AnnaBridge 126:abea610beb85 8162 #define USART_CR3_DMAT 0x00000080U /*!< DMA Enable Transmitter */
AnnaBridge 126:abea610beb85 8163 #define USART_CR3_RTSE 0x00000100U /*!< RTS Enable */
AnnaBridge 126:abea610beb85 8164 #define USART_CR3_CTSE 0x00000200U /*!< CTS Enable */
AnnaBridge 126:abea610beb85 8165 #define USART_CR3_CTSIE 0x00000400U /*!< CTS Interrupt Enable */
AnnaBridge 126:abea610beb85 8166 #define USART_CR3_ONEBIT 0x00000800U /*!< One sample bit method enable */
AnnaBridge 126:abea610beb85 8167 #define USART_CR3_OVRDIS 0x00001000U /*!< Overrun Disable */
AnnaBridge 126:abea610beb85 8168 #define USART_CR3_DDRE 0x00002000U /*!< DMA Disable on Reception Error */
AnnaBridge 126:abea610beb85 8169 #define USART_CR3_DEM 0x00004000U /*!< Driver Enable Mode */
AnnaBridge 126:abea610beb85 8170 #define USART_CR3_DEP 0x00008000U /*!< Driver Enable Polarity Selection */
AnnaBridge 126:abea610beb85 8171 #define USART_CR3_SCARCNT 0x000E0000U /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
AnnaBridge 126:abea610beb85 8172 #define USART_CR3_SCARCNT_0 0x00020000U /*!< Bit 0 */
AnnaBridge 126:abea610beb85 8173 #define USART_CR3_SCARCNT_1 0x00040000U /*!< Bit 1 */
AnnaBridge 126:abea610beb85 8174 #define USART_CR3_SCARCNT_2 0x00080000U /*!< Bit 2 */
AnnaBridge 126:abea610beb85 8175
AnnaBridge 126:abea610beb85 8176
AnnaBridge 126:abea610beb85 8177 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 126:abea610beb85 8178 #define USART_BRR_DIV_FRACTION 0x000FU /*!< Fraction of USARTDIV */
AnnaBridge 126:abea610beb85 8179 #define USART_BRR_DIV_MANTISSA 0xFFF0U /*!< Mantissa of USARTDIV */
AnnaBridge 126:abea610beb85 8180
AnnaBridge 126:abea610beb85 8181 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 126:abea610beb85 8182 #define USART_GTPR_PSC 0x00FFU /*!< PSC[7:0] bits (Prescaler value) */
AnnaBridge 126:abea610beb85 8183 #define USART_GTPR_GT 0xFF00U /*!< GT[7:0] bits (Guard time value) */
AnnaBridge 126:abea610beb85 8184
AnnaBridge 126:abea610beb85 8185
AnnaBridge 126:abea610beb85 8186 /******************* Bit definition for USART_RTOR register *****************/
AnnaBridge 126:abea610beb85 8187 #define USART_RTOR_RTO 0x00FFFFFFU /*!< Receiver Time Out Value */
AnnaBridge 126:abea610beb85 8188 #define USART_RTOR_BLEN 0xFF000000U /*!< Block Length */
AnnaBridge 126:abea610beb85 8189
AnnaBridge 126:abea610beb85 8190 /******************* Bit definition for USART_RQR register ******************/
AnnaBridge 126:abea610beb85 8191 #define USART_RQR_ABRRQ 0x0001U /*!< Auto-Baud Rate Request */
AnnaBridge 126:abea610beb85 8192 #define USART_RQR_SBKRQ 0x0002U /*!< Send Break Request */
AnnaBridge 126:abea610beb85 8193 #define USART_RQR_MMRQ 0x0004U /*!< Mute Mode Request */
AnnaBridge 126:abea610beb85 8194 #define USART_RQR_RXFRQ 0x0008U /*!< Receive Data flush Request */
AnnaBridge 126:abea610beb85 8195 #define USART_RQR_TXFRQ 0x0010U /*!< Transmit data flush Request */
AnnaBridge 126:abea610beb85 8196
AnnaBridge 126:abea610beb85 8197 /******************* Bit definition for USART_ISR register ******************/
AnnaBridge 126:abea610beb85 8198 #define USART_ISR_PE 0x00000001U /*!< Parity Error */
AnnaBridge 126:abea610beb85 8199 #define USART_ISR_FE 0x00000002U /*!< Framing Error */
AnnaBridge 126:abea610beb85 8200 #define USART_ISR_NE 0x00000004U /*!< Noise detected Flag */
AnnaBridge 126:abea610beb85 8201 #define USART_ISR_ORE 0x00000008U /*!< OverRun Error */
AnnaBridge 126:abea610beb85 8202 #define USART_ISR_IDLE 0x00000010U /*!< IDLE line detected */
AnnaBridge 126:abea610beb85 8203 #define USART_ISR_RXNE 0x00000020U /*!< Read Data Register Not Empty */
AnnaBridge 126:abea610beb85 8204 #define USART_ISR_TC 0x00000040U /*!< Transmission Complete */
AnnaBridge 126:abea610beb85 8205 #define USART_ISR_TXE 0x00000080U /*!< Transmit Data Register Empty */
AnnaBridge 126:abea610beb85 8206 #define USART_ISR_LBDF 0x00000100U /*!< LIN Break Detection Flag */
AnnaBridge 126:abea610beb85 8207 #define USART_ISR_CTSIF 0x00000200U /*!< CTS interrupt flag */
AnnaBridge 126:abea610beb85 8208 #define USART_ISR_CTS 0x00000400U /*!< CTS flag */
AnnaBridge 126:abea610beb85 8209 #define USART_ISR_RTOF 0x00000800U /*!< Receiver Time Out */
AnnaBridge 126:abea610beb85 8210 #define USART_ISR_EOBF 0x00001000U /*!< End Of Block Flag */
AnnaBridge 126:abea610beb85 8211 #define USART_ISR_ABRE 0x00004000U /*!< Auto-Baud Rate Error */
AnnaBridge 126:abea610beb85 8212 #define USART_ISR_ABRF 0x00008000U /*!< Auto-Baud Rate Flag */
AnnaBridge 126:abea610beb85 8213 #define USART_ISR_BUSY 0x00010000U /*!< Busy Flag */
AnnaBridge 126:abea610beb85 8214 #define USART_ISR_CMF 0x00020000U /*!< Character Match Flag */
AnnaBridge 126:abea610beb85 8215 #define USART_ISR_SBKF 0x00040000U /*!< Send Break Flag */
AnnaBridge 126:abea610beb85 8216 #define USART_ISR_RWU 0x00080000U /*!< Receive Wake Up from mute mode Flag */
AnnaBridge 126:abea610beb85 8217 #define USART_ISR_WUF 0x00100000U /*!< Wake Up from stop mode Flag */
AnnaBridge 126:abea610beb85 8218 #define USART_ISR_TEACK 0x00200000U /*!< Transmit Enable Acknowledge Flag */
AnnaBridge 126:abea610beb85 8219 #define USART_ISR_REACK 0x00400000U /*!< Receive Enable Acknowledge Flag */
AnnaBridge 126:abea610beb85 8220
AnnaBridge 126:abea610beb85 8221
AnnaBridge 126:abea610beb85 8222 /******************* Bit definition for USART_ICR register ******************/
AnnaBridge 126:abea610beb85 8223 #define USART_ICR_PECF 0x00000001U /*!< Parity Error Clear Flag */
AnnaBridge 126:abea610beb85 8224 #define USART_ICR_FECF 0x00000002U /*!< Framing Error Clear Flag */
AnnaBridge 126:abea610beb85 8225 #define USART_ICR_NCF 0x00000004U /*!< Noise detected Clear Flag */
AnnaBridge 126:abea610beb85 8226 #define USART_ICR_ORECF 0x00000008U /*!< OverRun Error Clear Flag */
AnnaBridge 126:abea610beb85 8227 #define USART_ICR_IDLECF 0x00000010U /*!< IDLE line detected Clear Flag */
AnnaBridge 126:abea610beb85 8228 #define USART_ICR_TCCF 0x00000040U /*!< Transmission Complete Clear Flag */
AnnaBridge 126:abea610beb85 8229 #define USART_ICR_LBDCF 0x00000100U /*!< LIN Break Detection Clear Flag */
AnnaBridge 126:abea610beb85 8230 #define USART_ICR_CTSCF 0x00000200U /*!< CTS Interrupt Clear Flag */
AnnaBridge 126:abea610beb85 8231 #define USART_ICR_RTOCF 0x00000800U /*!< Receiver Time Out Clear Flag */
AnnaBridge 126:abea610beb85 8232 #define USART_ICR_EOBCF 0x00001000U /*!< End Of Block Clear Flag */
AnnaBridge 126:abea610beb85 8233 #define USART_ICR_CMCF 0x00020000U /*!< Character Match Clear Flag */
AnnaBridge 126:abea610beb85 8234 #define USART_ICR_WUCF 0x00100000U /*!< Wake Up from stop mode Clear Flag */
AnnaBridge 126:abea610beb85 8235
AnnaBridge 126:abea610beb85 8236 /******************* Bit definition for USART_RDR register ******************/
AnnaBridge 126:abea610beb85 8237 #define USART_RDR_RDR 0x01FFU /*!< RDR[8:0] bits (Receive Data value) */
AnnaBridge 126:abea610beb85 8238
AnnaBridge 126:abea610beb85 8239 /******************* Bit definition for USART_TDR register ******************/
AnnaBridge 126:abea610beb85 8240 #define USART_TDR_TDR 0x01FFU /*!< TDR[8:0] bits (Transmit Data value) */
AnnaBridge 126:abea610beb85 8241
AnnaBridge 126:abea610beb85 8242 /******************************************************************************/
AnnaBridge 126:abea610beb85 8243 /* */
AnnaBridge 126:abea610beb85 8244 /* Window WATCHDOG */
AnnaBridge 126:abea610beb85 8245 /* */
AnnaBridge 126:abea610beb85 8246 /******************************************************************************/
AnnaBridge 126:abea610beb85 8247 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 126:abea610beb85 8248 #define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 126:abea610beb85 8249 #define WWDG_CR_T_0 0x01U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8250 #define WWDG_CR_T_1 0x02U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8251 #define WWDG_CR_T_2 0x04U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 8252 #define WWDG_CR_T_3 0x08U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 8253 #define WWDG_CR_T_4 0x10U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 8254 #define WWDG_CR_T_5 0x20U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 8255 #define WWDG_CR_T_6 0x40U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 8256
AnnaBridge 126:abea610beb85 8257
AnnaBridge 126:abea610beb85 8258 #define WWDG_CR_WDGA 0x80U /*!<Activation bit */
AnnaBridge 126:abea610beb85 8259
AnnaBridge 126:abea610beb85 8260 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 126:abea610beb85 8261 #define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
AnnaBridge 126:abea610beb85 8262 #define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8263 #define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8264 #define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 8265 #define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 8266 #define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 8267 #define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 8268 #define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 8269
AnnaBridge 126:abea610beb85 8270
AnnaBridge 126:abea610beb85 8271 #define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
AnnaBridge 126:abea610beb85 8272 #define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8273 #define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8274
AnnaBridge 126:abea610beb85 8275
AnnaBridge 126:abea610beb85 8276 #define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
AnnaBridge 126:abea610beb85 8277
AnnaBridge 126:abea610beb85 8278 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 126:abea610beb85 8279 #define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
AnnaBridge 126:abea610beb85 8280
AnnaBridge 126:abea610beb85 8281 /******************************************************************************/
AnnaBridge 126:abea610beb85 8282 /* */
AnnaBridge 126:abea610beb85 8283 /* DBG */
AnnaBridge 126:abea610beb85 8284 /* */
AnnaBridge 126:abea610beb85 8285 /******************************************************************************/
AnnaBridge 126:abea610beb85 8286 /******************** Bit definition for DBGMCU_IDCODE register *************/
AnnaBridge 126:abea610beb85 8287 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
AnnaBridge 126:abea610beb85 8288 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
AnnaBridge 126:abea610beb85 8289
AnnaBridge 126:abea610beb85 8290 /******************** Bit definition for DBGMCU_CR register *****************/
AnnaBridge 126:abea610beb85 8291 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
AnnaBridge 126:abea610beb85 8292 #define DBGMCU_CR_DBG_STOP 0x00000002U
AnnaBridge 126:abea610beb85 8293 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
AnnaBridge 126:abea610beb85 8294 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
AnnaBridge 126:abea610beb85 8295
AnnaBridge 126:abea610beb85 8296 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
AnnaBridge 126:abea610beb85 8297 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8298 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8299
AnnaBridge 126:abea610beb85 8300 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
AnnaBridge 126:abea610beb85 8301 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
AnnaBridge 126:abea610beb85 8302 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
AnnaBridge 126:abea610beb85 8303 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
AnnaBridge 126:abea610beb85 8304 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
AnnaBridge 126:abea610beb85 8305 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
AnnaBridge 126:abea610beb85 8306 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
AnnaBridge 126:abea610beb85 8307 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
AnnaBridge 126:abea610beb85 8308 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
AnnaBridge 126:abea610beb85 8309 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
AnnaBridge 126:abea610beb85 8310 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
AnnaBridge 126:abea610beb85 8311 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
AnnaBridge 126:abea610beb85 8312 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
AnnaBridge 126:abea610beb85 8313 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP 0x00002000U
AnnaBridge 126:abea610beb85 8314 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
AnnaBridge 126:abea610beb85 8315 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
AnnaBridge 126:abea610beb85 8316 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
AnnaBridge 126:abea610beb85 8317 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
AnnaBridge 126:abea610beb85 8318 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
AnnaBridge 126:abea610beb85 8319
AnnaBridge 126:abea610beb85 8320 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
AnnaBridge 126:abea610beb85 8321 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
AnnaBridge 126:abea610beb85 8322 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
AnnaBridge 126:abea610beb85 8323 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
AnnaBridge 126:abea610beb85 8324 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
AnnaBridge 126:abea610beb85 8325 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
AnnaBridge 126:abea610beb85 8326
AnnaBridge 126:abea610beb85 8327 /******************************************************************************/
AnnaBridge 126:abea610beb85 8328 /* */
AnnaBridge 126:abea610beb85 8329 /* Ethernet MAC Registers bits definitions */
AnnaBridge 126:abea610beb85 8330 /* */
AnnaBridge 126:abea610beb85 8331 /******************************************************************************/
AnnaBridge 126:abea610beb85 8332 /* Bit definition for Ethernet MAC Control Register register */
AnnaBridge 126:abea610beb85 8333 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
AnnaBridge 126:abea610beb85 8334 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
AnnaBridge 126:abea610beb85 8335 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
AnnaBridge 126:abea610beb85 8336 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
AnnaBridge 126:abea610beb85 8337 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
AnnaBridge 126:abea610beb85 8338 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
AnnaBridge 126:abea610beb85 8339 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
AnnaBridge 126:abea610beb85 8340 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
AnnaBridge 126:abea610beb85 8341 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
AnnaBridge 126:abea610beb85 8342 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
AnnaBridge 126:abea610beb85 8343 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
AnnaBridge 126:abea610beb85 8344 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
AnnaBridge 126:abea610beb85 8345 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
AnnaBridge 126:abea610beb85 8346 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
AnnaBridge 126:abea610beb85 8347 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
AnnaBridge 126:abea610beb85 8348 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
AnnaBridge 126:abea610beb85 8349 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
AnnaBridge 126:abea610beb85 8350 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
AnnaBridge 126:abea610beb85 8351 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
AnnaBridge 126:abea610beb85 8352 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
AnnaBridge 126:abea610beb85 8353 a transmission attempt during retries after a collision: 0 =< r <2^k */
AnnaBridge 126:abea610beb85 8354 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
AnnaBridge 126:abea610beb85 8355 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
AnnaBridge 126:abea610beb85 8356 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
AnnaBridge 126:abea610beb85 8357 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
AnnaBridge 126:abea610beb85 8358 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
AnnaBridge 126:abea610beb85 8359 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
AnnaBridge 126:abea610beb85 8360 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
AnnaBridge 126:abea610beb85 8361
AnnaBridge 126:abea610beb85 8362 /* Bit definition for Ethernet MAC Frame Filter Register */
AnnaBridge 126:abea610beb85 8363 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
AnnaBridge 126:abea610beb85 8364 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
AnnaBridge 126:abea610beb85 8365 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
AnnaBridge 126:abea610beb85 8366 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
AnnaBridge 126:abea610beb85 8367 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
AnnaBridge 126:abea610beb85 8368 #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
AnnaBridge 126:abea610beb85 8369 #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
AnnaBridge 126:abea610beb85 8370 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
AnnaBridge 126:abea610beb85 8371 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
AnnaBridge 126:abea610beb85 8372 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
AnnaBridge 126:abea610beb85 8373 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
AnnaBridge 126:abea610beb85 8374 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
AnnaBridge 126:abea610beb85 8375 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
AnnaBridge 126:abea610beb85 8376 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
AnnaBridge 126:abea610beb85 8377
AnnaBridge 126:abea610beb85 8378 /* Bit definition for Ethernet MAC Hash Table High Register */
AnnaBridge 126:abea610beb85 8379 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
AnnaBridge 126:abea610beb85 8380
AnnaBridge 126:abea610beb85 8381 /* Bit definition for Ethernet MAC Hash Table Low Register */
AnnaBridge 126:abea610beb85 8382 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
AnnaBridge 126:abea610beb85 8383
AnnaBridge 126:abea610beb85 8384 /* Bit definition for Ethernet MAC MII Address Register */
AnnaBridge 126:abea610beb85 8385 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
AnnaBridge 126:abea610beb85 8386 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
AnnaBridge 126:abea610beb85 8387 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
AnnaBridge 126:abea610beb85 8388 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
AnnaBridge 126:abea610beb85 8389 #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
AnnaBridge 126:abea610beb85 8390 #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
AnnaBridge 126:abea610beb85 8391 #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
AnnaBridge 126:abea610beb85 8392 #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
AnnaBridge 126:abea610beb85 8393 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
AnnaBridge 126:abea610beb85 8394 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
AnnaBridge 126:abea610beb85 8395
AnnaBridge 126:abea610beb85 8396 /* Bit definition for Ethernet MAC MII Data Register */
AnnaBridge 126:abea610beb85 8397 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
AnnaBridge 126:abea610beb85 8398
AnnaBridge 126:abea610beb85 8399 /* Bit definition for Ethernet MAC Flow Control Register */
AnnaBridge 126:abea610beb85 8400 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
AnnaBridge 126:abea610beb85 8401 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
AnnaBridge 126:abea610beb85 8402 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
AnnaBridge 126:abea610beb85 8403 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
AnnaBridge 126:abea610beb85 8404 #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
AnnaBridge 126:abea610beb85 8405 #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
AnnaBridge 126:abea610beb85 8406 #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
AnnaBridge 126:abea610beb85 8407 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
AnnaBridge 126:abea610beb85 8408 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
AnnaBridge 126:abea610beb85 8409 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
AnnaBridge 126:abea610beb85 8410 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
AnnaBridge 126:abea610beb85 8411
AnnaBridge 126:abea610beb85 8412 /* Bit definition for Ethernet MAC VLAN Tag Register */
AnnaBridge 126:abea610beb85 8413 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
AnnaBridge 126:abea610beb85 8414 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
AnnaBridge 126:abea610beb85 8415
AnnaBridge 126:abea610beb85 8416 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
AnnaBridge 126:abea610beb85 8417 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
AnnaBridge 126:abea610beb85 8418 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
AnnaBridge 126:abea610beb85 8419 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
AnnaBridge 126:abea610beb85 8420 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
AnnaBridge 126:abea610beb85 8421 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
AnnaBridge 126:abea610beb85 8422 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
AnnaBridge 126:abea610beb85 8423 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
AnnaBridge 126:abea610beb85 8424 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
AnnaBridge 126:abea610beb85 8425 RSVD - Filter1 Command - RSVD - Filter0 Command
AnnaBridge 126:abea610beb85 8426 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
AnnaBridge 126:abea610beb85 8427 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
AnnaBridge 126:abea610beb85 8428 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
AnnaBridge 126:abea610beb85 8429
AnnaBridge 126:abea610beb85 8430 /* Bit definition for Ethernet MAC PMT Control and Status Register */
AnnaBridge 126:abea610beb85 8431 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
AnnaBridge 126:abea610beb85 8432 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
AnnaBridge 126:abea610beb85 8433 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
AnnaBridge 126:abea610beb85 8434 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
AnnaBridge 126:abea610beb85 8435 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
AnnaBridge 126:abea610beb85 8436 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
AnnaBridge 126:abea610beb85 8437 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
AnnaBridge 126:abea610beb85 8438
AnnaBridge 126:abea610beb85 8439 /* Bit definition for Ethernet MAC Status Register */
AnnaBridge 126:abea610beb85 8440 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
AnnaBridge 126:abea610beb85 8441 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
AnnaBridge 126:abea610beb85 8442 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
AnnaBridge 126:abea610beb85 8443 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
AnnaBridge 126:abea610beb85 8444 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
AnnaBridge 126:abea610beb85 8445
AnnaBridge 126:abea610beb85 8446 /* Bit definition for Ethernet MAC Interrupt Mask Register */
AnnaBridge 126:abea610beb85 8447 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
AnnaBridge 126:abea610beb85 8448 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
AnnaBridge 126:abea610beb85 8449
AnnaBridge 126:abea610beb85 8450 /* Bit definition for Ethernet MAC Address0 High Register */
AnnaBridge 126:abea610beb85 8451 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
AnnaBridge 126:abea610beb85 8452
AnnaBridge 126:abea610beb85 8453 /* Bit definition for Ethernet MAC Address0 Low Register */
AnnaBridge 126:abea610beb85 8454 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
AnnaBridge 126:abea610beb85 8455
AnnaBridge 126:abea610beb85 8456 /* Bit definition for Ethernet MAC Address1 High Register */
AnnaBridge 126:abea610beb85 8457 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
AnnaBridge 126:abea610beb85 8458 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
AnnaBridge 126:abea610beb85 8459 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
AnnaBridge 126:abea610beb85 8460 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 126:abea610beb85 8461 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 126:abea610beb85 8462 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 126:abea610beb85 8463 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 126:abea610beb85 8464 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 126:abea610beb85 8465 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
AnnaBridge 126:abea610beb85 8466 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
AnnaBridge 126:abea610beb85 8467
AnnaBridge 126:abea610beb85 8468 /* Bit definition for Ethernet MAC Address1 Low Register */
AnnaBridge 126:abea610beb85 8469 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
AnnaBridge 126:abea610beb85 8470
AnnaBridge 126:abea610beb85 8471 /* Bit definition for Ethernet MAC Address2 High Register */
AnnaBridge 126:abea610beb85 8472 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
AnnaBridge 126:abea610beb85 8473 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
AnnaBridge 126:abea610beb85 8474 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
AnnaBridge 126:abea610beb85 8475 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 126:abea610beb85 8476 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 126:abea610beb85 8477 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 126:abea610beb85 8478 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 126:abea610beb85 8479 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 126:abea610beb85 8480 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
AnnaBridge 126:abea610beb85 8481 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
AnnaBridge 126:abea610beb85 8482
AnnaBridge 126:abea610beb85 8483 /* Bit definition for Ethernet MAC Address2 Low Register */
AnnaBridge 126:abea610beb85 8484 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
AnnaBridge 126:abea610beb85 8485
AnnaBridge 126:abea610beb85 8486 /* Bit definition for Ethernet MAC Address3 High Register */
AnnaBridge 126:abea610beb85 8487 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
AnnaBridge 126:abea610beb85 8488 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
AnnaBridge 126:abea610beb85 8489 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
AnnaBridge 126:abea610beb85 8490 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 126:abea610beb85 8491 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 126:abea610beb85 8492 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 126:abea610beb85 8493 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 126:abea610beb85 8494 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 126:abea610beb85 8495 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
AnnaBridge 126:abea610beb85 8496 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
AnnaBridge 126:abea610beb85 8497
AnnaBridge 126:abea610beb85 8498 /* Bit definition for Ethernet MAC Address3 Low Register */
AnnaBridge 126:abea610beb85 8499 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
AnnaBridge 126:abea610beb85 8500
AnnaBridge 126:abea610beb85 8501 /******************************************************************************/
AnnaBridge 126:abea610beb85 8502 /* Ethernet MMC Registers bits definition */
AnnaBridge 126:abea610beb85 8503 /******************************************************************************/
AnnaBridge 126:abea610beb85 8504
AnnaBridge 126:abea610beb85 8505 /* Bit definition for Ethernet MMC Contol Register */
AnnaBridge 126:abea610beb85 8506 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
AnnaBridge 126:abea610beb85 8507 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
AnnaBridge 126:abea610beb85 8508 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
AnnaBridge 126:abea610beb85 8509 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
AnnaBridge 126:abea610beb85 8510 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
AnnaBridge 126:abea610beb85 8511 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
AnnaBridge 126:abea610beb85 8512
AnnaBridge 126:abea610beb85 8513 /* Bit definition for Ethernet MMC Receive Interrupt Register */
AnnaBridge 126:abea610beb85 8514 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
AnnaBridge 126:abea610beb85 8515 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
AnnaBridge 126:abea610beb85 8516 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
AnnaBridge 126:abea610beb85 8517
AnnaBridge 126:abea610beb85 8518 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
AnnaBridge 126:abea610beb85 8519 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
AnnaBridge 126:abea610beb85 8520 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
AnnaBridge 126:abea610beb85 8521 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
AnnaBridge 126:abea610beb85 8522
AnnaBridge 126:abea610beb85 8523 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
AnnaBridge 126:abea610beb85 8524 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
AnnaBridge 126:abea610beb85 8525 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
AnnaBridge 126:abea610beb85 8526 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
AnnaBridge 126:abea610beb85 8527
AnnaBridge 126:abea610beb85 8528 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
AnnaBridge 126:abea610beb85 8529 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
AnnaBridge 126:abea610beb85 8530 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
AnnaBridge 126:abea610beb85 8531 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
AnnaBridge 126:abea610beb85 8532
AnnaBridge 126:abea610beb85 8533 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
AnnaBridge 126:abea610beb85 8534 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
AnnaBridge 126:abea610beb85 8535
AnnaBridge 126:abea610beb85 8536 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
AnnaBridge 126:abea610beb85 8537 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
AnnaBridge 126:abea610beb85 8538
AnnaBridge 126:abea610beb85 8539 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
AnnaBridge 126:abea610beb85 8540 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
AnnaBridge 126:abea610beb85 8541
AnnaBridge 126:abea610beb85 8542 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
AnnaBridge 126:abea610beb85 8543 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
AnnaBridge 126:abea610beb85 8544
AnnaBridge 126:abea610beb85 8545 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
AnnaBridge 126:abea610beb85 8546 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
AnnaBridge 126:abea610beb85 8547
AnnaBridge 126:abea610beb85 8548 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
AnnaBridge 126:abea610beb85 8549 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
AnnaBridge 126:abea610beb85 8550
AnnaBridge 126:abea610beb85 8551 /******************************************************************************/
AnnaBridge 126:abea610beb85 8552 /* Ethernet PTP Registers bits definition */
AnnaBridge 126:abea610beb85 8553 /******************************************************************************/
AnnaBridge 126:abea610beb85 8554
AnnaBridge 126:abea610beb85 8555 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
AnnaBridge 126:abea610beb85 8556 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
AnnaBridge 126:abea610beb85 8557 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
AnnaBridge 126:abea610beb85 8558 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
AnnaBridge 126:abea610beb85 8559 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
AnnaBridge 126:abea610beb85 8560 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
AnnaBridge 126:abea610beb85 8561 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
AnnaBridge 126:abea610beb85 8562 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
AnnaBridge 126:abea610beb85 8563 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
AnnaBridge 126:abea610beb85 8564 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
AnnaBridge 126:abea610beb85 8565
AnnaBridge 126:abea610beb85 8566 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
AnnaBridge 126:abea610beb85 8567 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
AnnaBridge 126:abea610beb85 8568 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
AnnaBridge 126:abea610beb85 8569 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
AnnaBridge 126:abea610beb85 8570 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
AnnaBridge 126:abea610beb85 8571 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
AnnaBridge 126:abea610beb85 8572
AnnaBridge 126:abea610beb85 8573 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
AnnaBridge 126:abea610beb85 8574 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
AnnaBridge 126:abea610beb85 8575
AnnaBridge 126:abea610beb85 8576 /* Bit definition for Ethernet PTP Time Stamp High Register */
AnnaBridge 126:abea610beb85 8577 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
AnnaBridge 126:abea610beb85 8578
AnnaBridge 126:abea610beb85 8579 /* Bit definition for Ethernet PTP Time Stamp Low Register */
AnnaBridge 126:abea610beb85 8580 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
AnnaBridge 126:abea610beb85 8581 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
AnnaBridge 126:abea610beb85 8582
AnnaBridge 126:abea610beb85 8583 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
AnnaBridge 126:abea610beb85 8584 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
AnnaBridge 126:abea610beb85 8585
AnnaBridge 126:abea610beb85 8586 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
AnnaBridge 126:abea610beb85 8587 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
AnnaBridge 126:abea610beb85 8588 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
AnnaBridge 126:abea610beb85 8589
AnnaBridge 126:abea610beb85 8590 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
AnnaBridge 126:abea610beb85 8591 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
AnnaBridge 126:abea610beb85 8592
AnnaBridge 126:abea610beb85 8593 /* Bit definition for Ethernet PTP Target Time High Register */
AnnaBridge 126:abea610beb85 8594 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
AnnaBridge 126:abea610beb85 8595
AnnaBridge 126:abea610beb85 8596 /* Bit definition for Ethernet PTP Target Time Low Register */
AnnaBridge 126:abea610beb85 8597 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
AnnaBridge 126:abea610beb85 8598
AnnaBridge 126:abea610beb85 8599 /* Bit definition for Ethernet PTP Time Stamp Status Register */
AnnaBridge 126:abea610beb85 8600 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
AnnaBridge 126:abea610beb85 8601 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
AnnaBridge 126:abea610beb85 8602
AnnaBridge 126:abea610beb85 8603 /******************************************************************************/
AnnaBridge 126:abea610beb85 8604 /* Ethernet DMA Registers bits definition */
AnnaBridge 126:abea610beb85 8605 /******************************************************************************/
AnnaBridge 126:abea610beb85 8606
AnnaBridge 126:abea610beb85 8607 /* Bit definition for Ethernet DMA Bus Mode Register */
AnnaBridge 126:abea610beb85 8608 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
AnnaBridge 126:abea610beb85 8609 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
AnnaBridge 126:abea610beb85 8610 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
AnnaBridge 126:abea610beb85 8611 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
AnnaBridge 126:abea610beb85 8612 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
AnnaBridge 126:abea610beb85 8613 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
AnnaBridge 126:abea610beb85 8614 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
AnnaBridge 126:abea610beb85 8615 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
AnnaBridge 126:abea610beb85 8616 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
AnnaBridge 126:abea610beb85 8617 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
AnnaBridge 126:abea610beb85 8618 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
AnnaBridge 126:abea610beb85 8619 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
AnnaBridge 126:abea610beb85 8620 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
AnnaBridge 126:abea610beb85 8621 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
AnnaBridge 126:abea610beb85 8622 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
AnnaBridge 126:abea610beb85 8623 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
AnnaBridge 126:abea610beb85 8624 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
AnnaBridge 126:abea610beb85 8625 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
AnnaBridge 126:abea610beb85 8626 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
AnnaBridge 126:abea610beb85 8627 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
AnnaBridge 126:abea610beb85 8628 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
AnnaBridge 126:abea610beb85 8629 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
AnnaBridge 126:abea610beb85 8630 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
AnnaBridge 126:abea610beb85 8631 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
AnnaBridge 126:abea610beb85 8632 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
AnnaBridge 126:abea610beb85 8633 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
AnnaBridge 126:abea610beb85 8634 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
AnnaBridge 126:abea610beb85 8635 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
AnnaBridge 126:abea610beb85 8636 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
AnnaBridge 126:abea610beb85 8637 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
AnnaBridge 126:abea610beb85 8638 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
AnnaBridge 126:abea610beb85 8639 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
AnnaBridge 126:abea610beb85 8640 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
AnnaBridge 126:abea610beb85 8641 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
AnnaBridge 126:abea610beb85 8642 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
AnnaBridge 126:abea610beb85 8643 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
AnnaBridge 126:abea610beb85 8644 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
AnnaBridge 126:abea610beb85 8645 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
AnnaBridge 126:abea610beb85 8646 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
AnnaBridge 126:abea610beb85 8647
AnnaBridge 126:abea610beb85 8648 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
AnnaBridge 126:abea610beb85 8649 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
AnnaBridge 126:abea610beb85 8650
AnnaBridge 126:abea610beb85 8651 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
AnnaBridge 126:abea610beb85 8652 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
AnnaBridge 126:abea610beb85 8653
AnnaBridge 126:abea610beb85 8654 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
AnnaBridge 126:abea610beb85 8655 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
AnnaBridge 126:abea610beb85 8656
AnnaBridge 126:abea610beb85 8657 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
AnnaBridge 126:abea610beb85 8658 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
AnnaBridge 126:abea610beb85 8659
AnnaBridge 126:abea610beb85 8660 /* Bit definition for Ethernet DMA Status Register */
AnnaBridge 126:abea610beb85 8661 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
AnnaBridge 126:abea610beb85 8662 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
AnnaBridge 126:abea610beb85 8663 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
AnnaBridge 126:abea610beb85 8664 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
AnnaBridge 126:abea610beb85 8665 /* combination with EBS[2:0] for GetFlagStatus function */
AnnaBridge 126:abea610beb85 8666 #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
AnnaBridge 126:abea610beb85 8667 #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
AnnaBridge 126:abea610beb85 8668 #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
AnnaBridge 126:abea610beb85 8669 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
AnnaBridge 126:abea610beb85 8670 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
AnnaBridge 126:abea610beb85 8671 #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
AnnaBridge 126:abea610beb85 8672 #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
AnnaBridge 126:abea610beb85 8673 #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
AnnaBridge 126:abea610beb85 8674 #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
AnnaBridge 126:abea610beb85 8675 #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
AnnaBridge 126:abea610beb85 8676 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
AnnaBridge 126:abea610beb85 8677 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
AnnaBridge 126:abea610beb85 8678 #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
AnnaBridge 126:abea610beb85 8679 #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
AnnaBridge 126:abea610beb85 8680 #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
AnnaBridge 126:abea610beb85 8681 #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
AnnaBridge 126:abea610beb85 8682 #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
AnnaBridge 126:abea610beb85 8683 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
AnnaBridge 126:abea610beb85 8684 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
AnnaBridge 126:abea610beb85 8685 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
AnnaBridge 126:abea610beb85 8686 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
AnnaBridge 126:abea610beb85 8687 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
AnnaBridge 126:abea610beb85 8688 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
AnnaBridge 126:abea610beb85 8689 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
AnnaBridge 126:abea610beb85 8690 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
AnnaBridge 126:abea610beb85 8691 #define ETH_DMASR_RS 0x00000040U /* Receive status */
AnnaBridge 126:abea610beb85 8692 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
AnnaBridge 126:abea610beb85 8693 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
AnnaBridge 126:abea610beb85 8694 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
AnnaBridge 126:abea610beb85 8695 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
AnnaBridge 126:abea610beb85 8696 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
AnnaBridge 126:abea610beb85 8697 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
AnnaBridge 126:abea610beb85 8698
AnnaBridge 126:abea610beb85 8699 /* Bit definition for Ethernet DMA Operation Mode Register */
AnnaBridge 126:abea610beb85 8700 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
AnnaBridge 126:abea610beb85 8701 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
AnnaBridge 126:abea610beb85 8702 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
AnnaBridge 126:abea610beb85 8703 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
AnnaBridge 126:abea610beb85 8704 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
AnnaBridge 126:abea610beb85 8705 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
AnnaBridge 126:abea610beb85 8706 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
AnnaBridge 126:abea610beb85 8707 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
AnnaBridge 126:abea610beb85 8708 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
AnnaBridge 126:abea610beb85 8709 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
AnnaBridge 126:abea610beb85 8710 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
AnnaBridge 126:abea610beb85 8711 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
AnnaBridge 126:abea610beb85 8712 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
AnnaBridge 126:abea610beb85 8713 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
AnnaBridge 126:abea610beb85 8714 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
AnnaBridge 126:abea610beb85 8715 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
AnnaBridge 126:abea610beb85 8716 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
AnnaBridge 126:abea610beb85 8717 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
AnnaBridge 126:abea610beb85 8718 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
AnnaBridge 126:abea610beb85 8719 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
AnnaBridge 126:abea610beb85 8720 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
AnnaBridge 126:abea610beb85 8721 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
AnnaBridge 126:abea610beb85 8722 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
AnnaBridge 126:abea610beb85 8723 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
AnnaBridge 126:abea610beb85 8724
AnnaBridge 126:abea610beb85 8725 /* Bit definition for Ethernet DMA Interrupt Enable Register */
AnnaBridge 126:abea610beb85 8726 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
AnnaBridge 126:abea610beb85 8727 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
AnnaBridge 126:abea610beb85 8728 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
AnnaBridge 126:abea610beb85 8729 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
AnnaBridge 126:abea610beb85 8730 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
AnnaBridge 126:abea610beb85 8731 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
AnnaBridge 126:abea610beb85 8732 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
AnnaBridge 126:abea610beb85 8733 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
AnnaBridge 126:abea610beb85 8734 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
AnnaBridge 126:abea610beb85 8735 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
AnnaBridge 126:abea610beb85 8736 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
AnnaBridge 126:abea610beb85 8737 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
AnnaBridge 126:abea610beb85 8738 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
AnnaBridge 126:abea610beb85 8739 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
AnnaBridge 126:abea610beb85 8740 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
AnnaBridge 126:abea610beb85 8741
AnnaBridge 126:abea610beb85 8742 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
AnnaBridge 126:abea610beb85 8743 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
AnnaBridge 126:abea610beb85 8744 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
AnnaBridge 126:abea610beb85 8745 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
AnnaBridge 126:abea610beb85 8746 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
AnnaBridge 126:abea610beb85 8747
AnnaBridge 126:abea610beb85 8748 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
AnnaBridge 126:abea610beb85 8749 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
AnnaBridge 126:abea610beb85 8750
AnnaBridge 126:abea610beb85 8751 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
AnnaBridge 126:abea610beb85 8752 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
AnnaBridge 126:abea610beb85 8753
AnnaBridge 126:abea610beb85 8754 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
AnnaBridge 126:abea610beb85 8755 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
AnnaBridge 126:abea610beb85 8756
AnnaBridge 126:abea610beb85 8757 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
AnnaBridge 126:abea610beb85 8758 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
AnnaBridge 126:abea610beb85 8759
AnnaBridge 126:abea610beb85 8760 /******************************************************************************/
AnnaBridge 126:abea610beb85 8761 /* */
AnnaBridge 126:abea610beb85 8762 /* USB_OTG */
AnnaBridge 126:abea610beb85 8763 /* */
AnnaBridge 126:abea610beb85 8764 /******************************************************************************/
AnnaBridge 126:abea610beb85 8765 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
AnnaBridge 126:abea610beb85 8766 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
AnnaBridge 126:abea610beb85 8767 #define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
AnnaBridge 126:abea610beb85 8768 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */
AnnaBridge 126:abea610beb85 8769 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */
AnnaBridge 126:abea610beb85 8770 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */
AnnaBridge 126:abea610beb85 8771 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */
AnnaBridge 126:abea610beb85 8772 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */
AnnaBridge 126:abea610beb85 8773 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */
AnnaBridge 126:abea610beb85 8774 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */
AnnaBridge 126:abea610beb85 8775 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
AnnaBridge 126:abea610beb85 8776 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
AnnaBridge 126:abea610beb85 8777 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
AnnaBridge 126:abea610beb85 8778 #define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */
AnnaBridge 126:abea610beb85 8779 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
AnnaBridge 126:abea610beb85 8780 #define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
AnnaBridge 126:abea610beb85 8781 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
AnnaBridge 126:abea610beb85 8782 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */
AnnaBridge 126:abea610beb85 8783 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */
AnnaBridge 126:abea610beb85 8784
AnnaBridge 126:abea610beb85 8785 /******************** Bit definition for USB_OTG_HCFG register ********************/
AnnaBridge 126:abea610beb85 8786 #define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
AnnaBridge 126:abea610beb85 8787 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8788 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8789 #define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
AnnaBridge 126:abea610beb85 8790
AnnaBridge 126:abea610beb85 8791 /******************** Bit definition for USB_OTG_DCFG register ********************/
AnnaBridge 126:abea610beb85 8792 #define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
AnnaBridge 126:abea610beb85 8793 #define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8794 #define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8795 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
AnnaBridge 126:abea610beb85 8796
AnnaBridge 126:abea610beb85 8797 #define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
AnnaBridge 126:abea610beb85 8798 #define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8799 #define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8800 #define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 8801 #define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 8802 #define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 8803 #define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 8804 #define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 8805
AnnaBridge 126:abea610beb85 8806 #define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
AnnaBridge 126:abea610beb85 8807 #define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8808 #define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8809
AnnaBridge 126:abea610beb85 8810 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
AnnaBridge 126:abea610beb85 8811 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8812 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8813
AnnaBridge 126:abea610beb85 8814 /******************** Bit definition for USB_OTG_PCGCR register ********************/
AnnaBridge 126:abea610beb85 8815 #define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
AnnaBridge 126:abea610beb85 8816 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
AnnaBridge 126:abea610beb85 8817 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
AnnaBridge 126:abea610beb85 8818
AnnaBridge 126:abea610beb85 8819 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
AnnaBridge 126:abea610beb85 8820 #define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
AnnaBridge 126:abea610beb85 8821 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
AnnaBridge 126:abea610beb85 8822 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
AnnaBridge 126:abea610beb85 8823 #define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
AnnaBridge 126:abea610beb85 8824 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
AnnaBridge 126:abea610beb85 8825 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
AnnaBridge 126:abea610beb85 8826 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */
AnnaBridge 126:abea610beb85 8827
AnnaBridge 126:abea610beb85 8828 /******************** Bit definition for USB_OTG_DCTL register ********************/
AnnaBridge 126:abea610beb85 8829 #define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
AnnaBridge 126:abea610beb85 8830 #define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
AnnaBridge 126:abea610beb85 8831 #define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
AnnaBridge 126:abea610beb85 8832 #define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
AnnaBridge 126:abea610beb85 8833
AnnaBridge 126:abea610beb85 8834 #define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
AnnaBridge 126:abea610beb85 8835 #define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8836 #define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8837 #define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 8838 #define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
AnnaBridge 126:abea610beb85 8839 #define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
AnnaBridge 126:abea610beb85 8840 #define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
AnnaBridge 126:abea610beb85 8841 #define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
AnnaBridge 126:abea610beb85 8842 #define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
AnnaBridge 126:abea610beb85 8843
AnnaBridge 126:abea610beb85 8844 /******************** Bit definition for USB_OTG_HFIR register ********************/
AnnaBridge 126:abea610beb85 8845 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
AnnaBridge 126:abea610beb85 8846
AnnaBridge 126:abea610beb85 8847 /******************** Bit definition for USB_OTG_HFNUM register ********************/
AnnaBridge 126:abea610beb85 8848 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
AnnaBridge 126:abea610beb85 8849 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
AnnaBridge 126:abea610beb85 8850
AnnaBridge 126:abea610beb85 8851 /******************** Bit definition for USB_OTG_DSTS register ********************/
AnnaBridge 126:abea610beb85 8852 #define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
AnnaBridge 126:abea610beb85 8853
AnnaBridge 126:abea610beb85 8854 #define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
AnnaBridge 126:abea610beb85 8855 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8856 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8857 #define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
AnnaBridge 126:abea610beb85 8858 #define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
AnnaBridge 126:abea610beb85 8859
AnnaBridge 126:abea610beb85 8860 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
AnnaBridge 126:abea610beb85 8861 #define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
AnnaBridge 126:abea610beb85 8862 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
AnnaBridge 126:abea610beb85 8863 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8864 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8865 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 8866 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 8867 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
AnnaBridge 126:abea610beb85 8868 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
AnnaBridge 126:abea610beb85 8869 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
AnnaBridge 126:abea610beb85 8870
AnnaBridge 126:abea610beb85 8871 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
AnnaBridge 126:abea610beb85 8872 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
AnnaBridge 126:abea610beb85 8873 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8874 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8875 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 8876 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
AnnaBridge 126:abea610beb85 8877 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
AnnaBridge 126:abea610beb85 8878 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
AnnaBridge 126:abea610beb85 8879 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
AnnaBridge 126:abea610beb85 8880 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8881 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8882 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 8883 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 8884 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
AnnaBridge 126:abea610beb85 8885 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
AnnaBridge 126:abea610beb85 8886 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
AnnaBridge 126:abea610beb85 8887 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
AnnaBridge 126:abea610beb85 8888 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
AnnaBridge 126:abea610beb85 8889 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
AnnaBridge 126:abea610beb85 8890 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
AnnaBridge 126:abea610beb85 8891 #define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
AnnaBridge 126:abea610beb85 8892 #define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
AnnaBridge 126:abea610beb85 8893 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
AnnaBridge 126:abea610beb85 8894 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
AnnaBridge 126:abea610beb85 8895 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
AnnaBridge 126:abea610beb85 8896 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
AnnaBridge 126:abea610beb85 8897
AnnaBridge 126:abea610beb85 8898 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
AnnaBridge 126:abea610beb85 8899 #define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
AnnaBridge 126:abea610beb85 8900 #define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
AnnaBridge 126:abea610beb85 8901 #define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
AnnaBridge 126:abea610beb85 8902 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
AnnaBridge 126:abea610beb85 8903 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
AnnaBridge 126:abea610beb85 8904 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
AnnaBridge 126:abea610beb85 8905 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8906 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8907 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 8908 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 8909 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 8910 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
AnnaBridge 126:abea610beb85 8911 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
AnnaBridge 126:abea610beb85 8912
AnnaBridge 126:abea610beb85 8913 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
AnnaBridge 126:abea610beb85 8914 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
AnnaBridge 126:abea610beb85 8915 #define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
AnnaBridge 126:abea610beb85 8916 #define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 126:abea610beb85 8917 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
AnnaBridge 126:abea610beb85 8918 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
AnnaBridge 126:abea610beb85 8919 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
AnnaBridge 126:abea610beb85 8920 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
AnnaBridge 126:abea610beb85 8921 #define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
AnnaBridge 126:abea610beb85 8922
AnnaBridge 126:abea610beb85 8923 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
AnnaBridge 126:abea610beb85 8924 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
AnnaBridge 126:abea610beb85 8925 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
AnnaBridge 126:abea610beb85 8926 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8927 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8928 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 8929 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 8930 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 8931 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 8932 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 8933 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 8934
AnnaBridge 126:abea610beb85 8935 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
AnnaBridge 126:abea610beb85 8936 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 8937 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 8938 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 8939 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 8940 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 8941 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 8942 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 8943 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 8944
AnnaBridge 126:abea610beb85 8945 /******************** Bit definition for USB_OTG_HAINT register ********************/
AnnaBridge 126:abea610beb85 8946 #define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
AnnaBridge 126:abea610beb85 8947
AnnaBridge 126:abea610beb85 8948 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
AnnaBridge 126:abea610beb85 8949 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
AnnaBridge 126:abea610beb85 8950 #define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
AnnaBridge 126:abea610beb85 8951 #define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
AnnaBridge 126:abea610beb85 8952 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
AnnaBridge 126:abea610beb85 8953 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */
AnnaBridge 126:abea610beb85 8954 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
AnnaBridge 126:abea610beb85 8955 #define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
AnnaBridge 126:abea610beb85 8956 #define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
AnnaBridge 126:abea610beb85 8957
AnnaBridge 126:abea610beb85 8958 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
AnnaBridge 126:abea610beb85 8959 #define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
AnnaBridge 126:abea610beb85 8960 #define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
AnnaBridge 126:abea610beb85 8961 #define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
AnnaBridge 126:abea610beb85 8962 #define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
AnnaBridge 126:abea610beb85 8963 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
AnnaBridge 126:abea610beb85 8964 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
AnnaBridge 126:abea610beb85 8965 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
AnnaBridge 126:abea610beb85 8966 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
AnnaBridge 126:abea610beb85 8967 #define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
AnnaBridge 126:abea610beb85 8968 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
AnnaBridge 126:abea610beb85 8969 #define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
AnnaBridge 126:abea610beb85 8970 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
AnnaBridge 126:abea610beb85 8971 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
AnnaBridge 126:abea610beb85 8972 #define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
AnnaBridge 126:abea610beb85 8973 #define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
AnnaBridge 126:abea610beb85 8974 #define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
AnnaBridge 126:abea610beb85 8975 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
AnnaBridge 126:abea610beb85 8976 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
AnnaBridge 126:abea610beb85 8977 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
AnnaBridge 126:abea610beb85 8978 #define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */
AnnaBridge 126:abea610beb85 8979 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
AnnaBridge 126:abea610beb85 8980 #define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
AnnaBridge 126:abea610beb85 8981 #define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
AnnaBridge 126:abea610beb85 8982 #define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */
AnnaBridge 126:abea610beb85 8983 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
AnnaBridge 126:abea610beb85 8984 #define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
AnnaBridge 126:abea610beb85 8985 #define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
AnnaBridge 126:abea610beb85 8986 #define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
AnnaBridge 126:abea610beb85 8987
AnnaBridge 126:abea610beb85 8988 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
AnnaBridge 126:abea610beb85 8989 #define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
AnnaBridge 126:abea610beb85 8990 #define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
AnnaBridge 126:abea610beb85 8991 #define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
AnnaBridge 126:abea610beb85 8992 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
AnnaBridge 126:abea610beb85 8993 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
AnnaBridge 126:abea610beb85 8994 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
AnnaBridge 126:abea610beb85 8995 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
AnnaBridge 126:abea610beb85 8996 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
AnnaBridge 126:abea610beb85 8997 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
AnnaBridge 126:abea610beb85 8998 #define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
AnnaBridge 126:abea610beb85 8999 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
AnnaBridge 126:abea610beb85 9000 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
AnnaBridge 126:abea610beb85 9001 #define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
AnnaBridge 126:abea610beb85 9002 #define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
AnnaBridge 126:abea610beb85 9003 #define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
AnnaBridge 126:abea610beb85 9004 #define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
AnnaBridge 126:abea610beb85 9005 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
AnnaBridge 126:abea610beb85 9006 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
AnnaBridge 126:abea610beb85 9007 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
AnnaBridge 126:abea610beb85 9008 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U /*!< Reset detected interrupt mask */
AnnaBridge 126:abea610beb85 9009 #define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
AnnaBridge 126:abea610beb85 9010 #define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
AnnaBridge 126:abea610beb85 9011 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
AnnaBridge 126:abea610beb85 9012 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */
AnnaBridge 126:abea610beb85 9013 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
AnnaBridge 126:abea610beb85 9014 #define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
AnnaBridge 126:abea610beb85 9015 #define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
AnnaBridge 126:abea610beb85 9016 #define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
AnnaBridge 126:abea610beb85 9017
AnnaBridge 126:abea610beb85 9018 /******************** Bit definition for USB_OTG_DAINT register ********************/
AnnaBridge 126:abea610beb85 9019 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
AnnaBridge 126:abea610beb85 9020 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
AnnaBridge 126:abea610beb85 9021
AnnaBridge 126:abea610beb85 9022 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
AnnaBridge 126:abea610beb85 9023 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
AnnaBridge 126:abea610beb85 9024
AnnaBridge 126:abea610beb85 9025 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
AnnaBridge 126:abea610beb85 9026 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
AnnaBridge 126:abea610beb85 9027 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
AnnaBridge 126:abea610beb85 9028 #define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
AnnaBridge 126:abea610beb85 9029 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
AnnaBridge 126:abea610beb85 9030
AnnaBridge 126:abea610beb85 9031 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
AnnaBridge 126:abea610beb85 9032 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
AnnaBridge 126:abea610beb85 9033 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
AnnaBridge 126:abea610beb85 9034
AnnaBridge 126:abea610beb85 9035 /******************** Bit definition for OTG register ********************/
AnnaBridge 126:abea610beb85 9036
AnnaBridge 126:abea610beb85 9037 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
AnnaBridge 126:abea610beb85 9038 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9039 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9040 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9041 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9042 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
AnnaBridge 126:abea610beb85 9043
AnnaBridge 126:abea610beb85 9044 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
AnnaBridge 126:abea610beb85 9045 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9046 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9047
AnnaBridge 126:abea610beb85 9048 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
AnnaBridge 126:abea610beb85 9049 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9050 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9051 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9052 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9053
AnnaBridge 126:abea610beb85 9054 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
AnnaBridge 126:abea610beb85 9055 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9056 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9057 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9058 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9059
AnnaBridge 126:abea610beb85 9060 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
AnnaBridge 126:abea610beb85 9061 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9062 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9063 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9064 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9065
AnnaBridge 126:abea610beb85 9066 /******************** Bit definition for OTG register ********************/
AnnaBridge 126:abea610beb85 9067
AnnaBridge 126:abea610beb85 9068 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
AnnaBridge 126:abea610beb85 9069 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9070 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9071 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9072 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9073 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
AnnaBridge 126:abea610beb85 9074
AnnaBridge 126:abea610beb85 9075 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
AnnaBridge 126:abea610beb85 9076 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9077 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9078
AnnaBridge 126:abea610beb85 9079 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
AnnaBridge 126:abea610beb85 9080 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9081 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9082 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9083 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9084
AnnaBridge 126:abea610beb85 9085 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
AnnaBridge 126:abea610beb85 9086 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9087 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9088 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9089 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9090
AnnaBridge 126:abea610beb85 9091 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
AnnaBridge 126:abea610beb85 9092 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9093 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9094 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9095 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9096
AnnaBridge 126:abea610beb85 9097 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
AnnaBridge 126:abea610beb85 9098 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
AnnaBridge 126:abea610beb85 9099
AnnaBridge 126:abea610beb85 9100 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
AnnaBridge 126:abea610beb85 9101 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
AnnaBridge 126:abea610beb85 9102
AnnaBridge 126:abea610beb85 9103 /******************** Bit definition for OTG register ********************/
AnnaBridge 126:abea610beb85 9104 #define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
AnnaBridge 126:abea610beb85 9105 #define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
AnnaBridge 126:abea610beb85 9106 #define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
AnnaBridge 126:abea610beb85 9107 #define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
AnnaBridge 126:abea610beb85 9108
AnnaBridge 126:abea610beb85 9109 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
AnnaBridge 126:abea610beb85 9110 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
AnnaBridge 126:abea610beb85 9111
AnnaBridge 126:abea610beb85 9112 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
AnnaBridge 126:abea610beb85 9113 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
AnnaBridge 126:abea610beb85 9114
AnnaBridge 126:abea610beb85 9115 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
AnnaBridge 126:abea610beb85 9116 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9117 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9118 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9119 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9120 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 9121 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 9122 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 9123 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 9124
AnnaBridge 126:abea610beb85 9125 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
AnnaBridge 126:abea610beb85 9126 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9127 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9128 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9129 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9130 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 9131 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 9132 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 9133
AnnaBridge 126:abea610beb85 9134 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
AnnaBridge 126:abea610beb85 9135 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
AnnaBridge 126:abea610beb85 9136 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
AnnaBridge 126:abea610beb85 9137
AnnaBridge 126:abea610beb85 9138 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
AnnaBridge 126:abea610beb85 9139 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9140 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9141 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9142 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9143 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 9144 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 9145 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 9146 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 9147 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
AnnaBridge 126:abea610beb85 9148 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
AnnaBridge 126:abea610beb85 9149
AnnaBridge 126:abea610beb85 9150 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
AnnaBridge 126:abea610beb85 9151 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9152 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9153 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9154 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9155 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 9156 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 9157 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 9158 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
AnnaBridge 126:abea610beb85 9159 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
AnnaBridge 126:abea610beb85 9160 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
AnnaBridge 126:abea610beb85 9161
AnnaBridge 126:abea610beb85 9162 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
AnnaBridge 126:abea610beb85 9163 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
AnnaBridge 126:abea610beb85 9164
AnnaBridge 126:abea610beb85 9165 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
AnnaBridge 126:abea610beb85 9166 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
AnnaBridge 126:abea610beb85 9167 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
AnnaBridge 126:abea610beb85 9168
AnnaBridge 126:abea610beb85 9169 /******************** Bit definition for USB_OTG_GCCFG register ********************/
AnnaBridge 126:abea610beb85 9170 #define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
AnnaBridge 126:abea610beb85 9171 #define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */
AnnaBridge 126:abea610beb85 9172
AnnaBridge 126:abea610beb85 9173 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
AnnaBridge 126:abea610beb85 9174 #define USB_OTG_GPWRDN_ADPMEN 0x00000001U /*!< ADP module enable */
AnnaBridge 126:abea610beb85 9175 #define USB_OTG_GPWRDN_ADPIF 0x00800000U /*!< ADP Interrupt flag */
AnnaBridge 126:abea610beb85 9176
AnnaBridge 126:abea610beb85 9177 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
AnnaBridge 126:abea610beb85 9178 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
AnnaBridge 126:abea610beb85 9179 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
AnnaBridge 126:abea610beb85 9180
AnnaBridge 126:abea610beb85 9181 /******************** Bit definition for USB_OTG_CID register ********************/
AnnaBridge 126:abea610beb85 9182 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
AnnaBridge 126:abea610beb85 9183
AnnaBridge 126:abea610beb85 9184 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
AnnaBridge 126:abea610beb85 9185 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */
AnnaBridge 126:abea610beb85 9186 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */
AnnaBridge 126:abea610beb85 9187 #define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */
AnnaBridge 126:abea610beb85 9188 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */
AnnaBridge 126:abea610beb85 9189 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */
AnnaBridge 126:abea610beb85 9190 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */
AnnaBridge 126:abea610beb85 9191 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */
AnnaBridge 126:abea610beb85 9192 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */
AnnaBridge 126:abea610beb85 9193 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */
AnnaBridge 126:abea610beb85 9194 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */
AnnaBridge 126:abea610beb85 9195 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */
AnnaBridge 126:abea610beb85 9196 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */
AnnaBridge 126:abea610beb85 9197 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */
AnnaBridge 126:abea610beb85 9198 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */
AnnaBridge 126:abea610beb85 9199 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */
AnnaBridge 126:abea610beb85 9200
AnnaBridge 126:abea610beb85 9201 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
AnnaBridge 126:abea610beb85 9202 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
AnnaBridge 126:abea610beb85 9203 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
AnnaBridge 126:abea610beb85 9204 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 126:abea610beb85 9205 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
AnnaBridge 126:abea610beb85 9206 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
AnnaBridge 126:abea610beb85 9207 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
AnnaBridge 126:abea610beb85 9208 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
AnnaBridge 126:abea610beb85 9209 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
AnnaBridge 126:abea610beb85 9210 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
AnnaBridge 126:abea610beb85 9211
AnnaBridge 126:abea610beb85 9212 /******************** Bit definition for USB_OTG_HPRT register ********************/
AnnaBridge 126:abea610beb85 9213 #define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
AnnaBridge 126:abea610beb85 9214 #define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
AnnaBridge 126:abea610beb85 9215 #define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
AnnaBridge 126:abea610beb85 9216 #define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
AnnaBridge 126:abea610beb85 9217 #define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
AnnaBridge 126:abea610beb85 9218 #define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
AnnaBridge 126:abea610beb85 9219 #define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
AnnaBridge 126:abea610beb85 9220 #define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
AnnaBridge 126:abea610beb85 9221 #define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
AnnaBridge 126:abea610beb85 9222
AnnaBridge 126:abea610beb85 9223 #define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
AnnaBridge 126:abea610beb85 9224 #define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9225 #define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9226 #define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
AnnaBridge 126:abea610beb85 9227
AnnaBridge 126:abea610beb85 9228 #define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
AnnaBridge 126:abea610beb85 9229 #define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9230 #define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9231 #define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9232 #define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9233
AnnaBridge 126:abea610beb85 9234 #define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
AnnaBridge 126:abea610beb85 9235 #define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9236 #define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9237
AnnaBridge 126:abea610beb85 9238 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
AnnaBridge 126:abea610beb85 9239 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
AnnaBridge 126:abea610beb85 9240 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
AnnaBridge 126:abea610beb85 9241 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
AnnaBridge 126:abea610beb85 9242 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
AnnaBridge 126:abea610beb85 9243 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
AnnaBridge 126:abea610beb85 9244 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
AnnaBridge 126:abea610beb85 9245 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
AnnaBridge 126:abea610beb85 9246 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
AnnaBridge 126:abea610beb85 9247 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
AnnaBridge 126:abea610beb85 9248 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
AnnaBridge 126:abea610beb85 9249 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
AnnaBridge 126:abea610beb85 9250
AnnaBridge 126:abea610beb85 9251 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
AnnaBridge 126:abea610beb85 9252 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
AnnaBridge 126:abea610beb85 9253 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
AnnaBridge 126:abea610beb85 9254
AnnaBridge 126:abea610beb85 9255 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
AnnaBridge 126:abea610beb85 9256 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
AnnaBridge 126:abea610beb85 9257 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
AnnaBridge 126:abea610beb85 9258 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
AnnaBridge 126:abea610beb85 9259 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
AnnaBridge 126:abea610beb85 9260
AnnaBridge 126:abea610beb85 9261 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
AnnaBridge 126:abea610beb85 9262 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9263 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9264 #define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
AnnaBridge 126:abea610beb85 9265
AnnaBridge 126:abea610beb85 9266 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
AnnaBridge 126:abea610beb85 9267 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9268 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9269 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9270 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9271 #define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
AnnaBridge 126:abea610beb85 9272 #define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
AnnaBridge 126:abea610beb85 9273 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
AnnaBridge 126:abea610beb85 9274 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
AnnaBridge 126:abea610beb85 9275 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
AnnaBridge 126:abea610beb85 9276 #define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
AnnaBridge 126:abea610beb85 9277
AnnaBridge 126:abea610beb85 9278 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
AnnaBridge 126:abea610beb85 9279 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
AnnaBridge 126:abea610beb85 9280
AnnaBridge 126:abea610beb85 9281 #define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
AnnaBridge 126:abea610beb85 9282 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9283 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9284 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9285 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9286 #define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
AnnaBridge 126:abea610beb85 9287 #define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
AnnaBridge 126:abea610beb85 9288
AnnaBridge 126:abea610beb85 9289 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
AnnaBridge 126:abea610beb85 9290 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9291 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9292
AnnaBridge 126:abea610beb85 9293 #define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
AnnaBridge 126:abea610beb85 9294 #define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9295 #define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9296
AnnaBridge 126:abea610beb85 9297 #define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
AnnaBridge 126:abea610beb85 9298 #define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9299 #define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9300 #define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9301 #define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9302 #define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 9303 #define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 9304 #define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 9305 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
AnnaBridge 126:abea610beb85 9306 #define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
AnnaBridge 126:abea610beb85 9307 #define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
AnnaBridge 126:abea610beb85 9308
AnnaBridge 126:abea610beb85 9309 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
AnnaBridge 126:abea610beb85 9310
AnnaBridge 126:abea610beb85 9311 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
AnnaBridge 126:abea610beb85 9312 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9313 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9314 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9315 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9316 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 9317 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 9318 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 9319
AnnaBridge 126:abea610beb85 9320 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
AnnaBridge 126:abea610beb85 9321 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9322 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9323 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9324 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9325 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 9326 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
AnnaBridge 126:abea610beb85 9327 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
AnnaBridge 126:abea610beb85 9328
AnnaBridge 126:abea610beb85 9329 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
AnnaBridge 126:abea610beb85 9330 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9331 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9332 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
AnnaBridge 126:abea610beb85 9333 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
AnnaBridge 126:abea610beb85 9334
AnnaBridge 126:abea610beb85 9335 /******************** Bit definition for USB_OTG_HCINT register ********************/
AnnaBridge 126:abea610beb85 9336 #define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
AnnaBridge 126:abea610beb85 9337 #define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
AnnaBridge 126:abea610beb85 9338 #define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
AnnaBridge 126:abea610beb85 9339 #define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
AnnaBridge 126:abea610beb85 9340 #define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
AnnaBridge 126:abea610beb85 9341 #define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
AnnaBridge 126:abea610beb85 9342 #define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
AnnaBridge 126:abea610beb85 9343 #define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
AnnaBridge 126:abea610beb85 9344 #define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
AnnaBridge 126:abea610beb85 9345 #define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
AnnaBridge 126:abea610beb85 9346 #define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
AnnaBridge 126:abea610beb85 9347
AnnaBridge 126:abea610beb85 9348 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
AnnaBridge 126:abea610beb85 9349 #define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
AnnaBridge 126:abea610beb85 9350 #define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
AnnaBridge 126:abea610beb85 9351 #define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
AnnaBridge 126:abea610beb85 9352 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
AnnaBridge 126:abea610beb85 9353 #define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
AnnaBridge 126:abea610beb85 9354 #define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
AnnaBridge 126:abea610beb85 9355 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
AnnaBridge 126:abea610beb85 9356 #define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
AnnaBridge 126:abea610beb85 9357 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
AnnaBridge 126:abea610beb85 9358 #define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
AnnaBridge 126:abea610beb85 9359 #define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
AnnaBridge 126:abea610beb85 9360
AnnaBridge 126:abea610beb85 9361 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
AnnaBridge 126:abea610beb85 9362 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
AnnaBridge 126:abea610beb85 9363 #define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
AnnaBridge 126:abea610beb85 9364 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
AnnaBridge 126:abea610beb85 9365 #define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
AnnaBridge 126:abea610beb85 9366 #define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
AnnaBridge 126:abea610beb85 9367 #define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
AnnaBridge 126:abea610beb85 9368 #define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
AnnaBridge 126:abea610beb85 9369 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
AnnaBridge 126:abea610beb85 9370 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
AnnaBridge 126:abea610beb85 9371 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
AnnaBridge 126:abea610beb85 9372 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
AnnaBridge 126:abea610beb85 9373
AnnaBridge 126:abea610beb85 9374 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
AnnaBridge 126:abea610beb85 9375
AnnaBridge 126:abea610beb85 9376 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
AnnaBridge 126:abea610beb85 9377 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
AnnaBridge 126:abea610beb85 9378 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
AnnaBridge 126:abea610beb85 9379 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
AnnaBridge 126:abea610beb85 9380 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
AnnaBridge 126:abea610beb85 9381 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
AnnaBridge 126:abea610beb85 9382 #define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
AnnaBridge 126:abea610beb85 9383 #define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
AnnaBridge 126:abea610beb85 9384 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9385 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9386
AnnaBridge 126:abea610beb85 9387 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
AnnaBridge 126:abea610beb85 9388 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
AnnaBridge 126:abea610beb85 9389
AnnaBridge 126:abea610beb85 9390 /******************** Bit definition for USB_OTG_HCDMA register ********************/
AnnaBridge 126:abea610beb85 9391 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
AnnaBridge 126:abea610beb85 9392
AnnaBridge 126:abea610beb85 9393 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
AnnaBridge 126:abea610beb85 9394 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
AnnaBridge 126:abea610beb85 9395
AnnaBridge 126:abea610beb85 9396 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
AnnaBridge 126:abea610beb85 9397 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
AnnaBridge 126:abea610beb85 9398 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
AnnaBridge 126:abea610beb85 9399
AnnaBridge 126:abea610beb85 9400 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
AnnaBridge 126:abea610beb85 9401 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9402 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
AnnaBridge 126:abea610beb85 9403 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
AnnaBridge 126:abea610beb85 9404 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
AnnaBridge 126:abea610beb85 9405 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
AnnaBridge 126:abea610beb85 9406 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
AnnaBridge 126:abea610beb85 9407 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9408 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9409 #define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
AnnaBridge 126:abea610beb85 9410 #define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
AnnaBridge 126:abea610beb85 9411 #define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
AnnaBridge 126:abea610beb85 9412 #define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
AnnaBridge 126:abea610beb85 9413 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
AnnaBridge 126:abea610beb85 9414 #define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
AnnaBridge 126:abea610beb85 9415
AnnaBridge 126:abea610beb85 9416 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
AnnaBridge 126:abea610beb85 9417 #define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
AnnaBridge 126:abea610beb85 9418 #define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
AnnaBridge 126:abea610beb85 9419 #define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
AnnaBridge 126:abea610beb85 9420 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
AnnaBridge 126:abea610beb85 9421 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */
AnnaBridge 126:abea610beb85 9422 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
AnnaBridge 126:abea610beb85 9423 #define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
AnnaBridge 126:abea610beb85 9424
AnnaBridge 126:abea610beb85 9425 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
AnnaBridge 126:abea610beb85 9426 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
AnnaBridge 126:abea610beb85 9427 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
AnnaBridge 126:abea610beb85 9428
AnnaBridge 126:abea610beb85 9429 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
AnnaBridge 126:abea610beb85 9430 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9431 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9432
AnnaBridge 126:abea610beb85 9433 /******************** Bit definition for PCGCCTL register ********************/
AnnaBridge 126:abea610beb85 9434 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
AnnaBridge 126:abea610beb85 9435 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9436 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9437
AnnaBridge 126:abea610beb85 9438 /******************************************************************************/
AnnaBridge 126:abea610beb85 9439 /* */
AnnaBridge 126:abea610beb85 9440 /* JPEG Encoder/Decoder */
AnnaBridge 126:abea610beb85 9441 /* */
AnnaBridge 126:abea610beb85 9442 /******************************************************************************/
AnnaBridge 126:abea610beb85 9443 /******************** Bit definition for CONFR0 register ********************/
AnnaBridge 126:abea610beb85 9444 #define JPEG_CONFR0_START 0x00000001U /*!<Start/Stop bit */
AnnaBridge 126:abea610beb85 9445
AnnaBridge 126:abea610beb85 9446 /******************** Bit definition for CONFR1 register *******************/
AnnaBridge 126:abea610beb85 9447 #define JPEG_CONFR1_NF 0x00000003U /*!<Number of color components */
AnnaBridge 126:abea610beb85 9448 #define JPEG_CONFR1_NF_0 0x00000001U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9449 #define JPEG_CONFR1_NF_1 0x00000002U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9450 #define JPEG_CONFR1_RE 0x00000004U /*!<Restart maker Enable */
AnnaBridge 126:abea610beb85 9451 #define JPEG_CONFR1_DE 0x00000008U /*!<Decoding Enable */
AnnaBridge 126:abea610beb85 9452 #define JPEG_CONFR1_COLORSPACE 0x00000030U /*!<Color Space */
AnnaBridge 126:abea610beb85 9453 #define JPEG_CONFR1_COLORSPACE_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9454 #define JPEG_CONFR1_COLORSPACE_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9455 #define JPEG_CONFR1_NS 0x000000C0U /*!<Number of components for Scan */
AnnaBridge 126:abea610beb85 9456 #define JPEG_CONFR1_NS_0 0x00000040U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9457 #define JPEG_CONFR1_NS_1 0x00000080U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9458 #define JPEG_CONFR1_HDR 0x00000100U /*!<Header Processing On/Off */
AnnaBridge 126:abea610beb85 9459 #define JPEG_CONFR1_YSIZE 0xFFFF0000U /*!<Number of lines in source image */
AnnaBridge 126:abea610beb85 9460
AnnaBridge 126:abea610beb85 9461 /******************** Bit definition for CONFR2 register *******************/
AnnaBridge 126:abea610beb85 9462 #define JPEG_CONFR2_NMCU 0x03FFFFFFU /*!<Number of MCU units minus 1 to encode */
AnnaBridge 126:abea610beb85 9463
AnnaBridge 126:abea610beb85 9464 /******************** Bit definition for CONFR3 register *******************/
AnnaBridge 126:abea610beb85 9465 #define JPEG_CONFR3_NRST 0x0000FFFFU /*!<Number of MCU between two restart makers minus 1 */
AnnaBridge 126:abea610beb85 9466 #define JPEG_CONFR3_XSIZE 0xFFFF0000U /*!<Number of pixels per line */
AnnaBridge 126:abea610beb85 9467
AnnaBridge 126:abea610beb85 9468 /******************** Bit definition for CONFR4 register *******************/
AnnaBridge 126:abea610beb85 9469 #define JPEG_CONFR4_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
AnnaBridge 126:abea610beb85 9470 #define JPEG_CONFR4_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
AnnaBridge 126:abea610beb85 9471 #define JPEG_CONFR4_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
AnnaBridge 126:abea610beb85 9472 #define JPEG_CONFR4_QT_0 0x00000004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9473 #define JPEG_CONFR4_QT_1 0x00000008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9474 #define JPEG_CONFR4_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
AnnaBridge 126:abea610beb85 9475 #define JPEG_CONFR4_NB_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9476 #define JPEG_CONFR4_NB_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9477 #define JPEG_CONFR4_NB_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9478 #define JPEG_CONFR4_NB_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9479 #define JPEG_CONFR4_VSF 0x00000F00U /*!<Vertical sampling factor for component 1 */
AnnaBridge 126:abea610beb85 9480 #define JPEG_CONFR4_VSF_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9481 #define JPEG_CONFR4_VSF_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9482 #define JPEG_CONFR4_VSF_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9483 #define JPEG_CONFR4_VSF_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9484 #define JPEG_CONFR4_HSF 0x0000F000U /*!<Horizontal sampling factor for component 1 */
AnnaBridge 126:abea610beb85 9485 #define JPEG_CONFR4_HSF_0 0x00001000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9486 #define JPEG_CONFR4_HSF_1 0x00002000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9487 #define JPEG_CONFR4_HSF_2 0x00004000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9488 #define JPEG_CONFR4_HSF_3 0x00008000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9489
AnnaBridge 126:abea610beb85 9490 /******************** Bit definition for CONFR5 register *******************/
AnnaBridge 126:abea610beb85 9491 #define JPEG_CONFR5_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
AnnaBridge 126:abea610beb85 9492 #define JPEG_CONFR5_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
AnnaBridge 126:abea610beb85 9493 #define JPEG_CONFR5_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
AnnaBridge 126:abea610beb85 9494 #define JPEG_CONFR5_QT_0 0x00000004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9495 #define JPEG_CONFR5_QT_1 0x00000008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9496 #define JPEG_CONFR5_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
AnnaBridge 126:abea610beb85 9497 #define JPEG_CONFR5_NB_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9498 #define JPEG_CONFR5_NB_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9499 #define JPEG_CONFR5_NB_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9500 #define JPEG_CONFR5_NB_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9501 #define JPEG_CONFR5_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */
AnnaBridge 126:abea610beb85 9502 #define JPEG_CONFR5_VSF_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9503 #define JPEG_CONFR5_VSF_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9504 #define JPEG_CONFR5_VSF_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9505 #define JPEG_CONFR5_VSF_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9506 #define JPEG_CONFR5_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */
AnnaBridge 126:abea610beb85 9507 #define JPEG_CONFR5_HSF_0 0x00001000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9508 #define JPEG_CONFR5_HSF_1 0x00002000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9509 #define JPEG_CONFR5_HSF_2 0x00004000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9510 #define JPEG_CONFR5_HSF_3 0x00008000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9511
AnnaBridge 126:abea610beb85 9512 /******************** Bit definition for CONFR6 register *******************/
AnnaBridge 126:abea610beb85 9513 #define JPEG_CONFR6_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
AnnaBridge 126:abea610beb85 9514 #define JPEG_CONFR6_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
AnnaBridge 126:abea610beb85 9515 #define JPEG_CONFR6_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
AnnaBridge 126:abea610beb85 9516 #define JPEG_CONFR6_QT_0 0x00000004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9517 #define JPEG_CONFR6_QT_1 0x00000008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9518 #define JPEG_CONFR6_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
AnnaBridge 126:abea610beb85 9519 #define JPEG_CONFR6_NB_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9520 #define JPEG_CONFR6_NB_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9521 #define JPEG_CONFR6_NB_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9522 #define JPEG_CONFR6_NB_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9523 #define JPEG_CONFR6_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */
AnnaBridge 126:abea610beb85 9524 #define JPEG_CONFR6_VSF_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9525 #define JPEG_CONFR6_VSF_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9526 #define JPEG_CONFR6_VSF_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9527 #define JPEG_CONFR6_VSF_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9528 #define JPEG_CONFR6_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */
AnnaBridge 126:abea610beb85 9529 #define JPEG_CONFR6_HSF_0 0x00001000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9530 #define JPEG_CONFR6_HSF_1 0x00002000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9531 #define JPEG_CONFR6_HSF_2 0x00004000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9532 #define JPEG_CONFR6_HSF_3 0x00008000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9533
AnnaBridge 126:abea610beb85 9534 /******************** Bit definition for CONFR7 register *******************/
AnnaBridge 126:abea610beb85 9535 #define JPEG_CONFR7_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
AnnaBridge 126:abea610beb85 9536 #define JPEG_CONFR7_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
AnnaBridge 126:abea610beb85 9537 #define JPEG_CONFR7_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
AnnaBridge 126:abea610beb85 9538 #define JPEG_CONFR7_QT_0 0x00000004U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9539 #define JPEG_CONFR7_QT_1 0x00000008U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9540 #define JPEG_CONFR7_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
AnnaBridge 126:abea610beb85 9541 #define JPEG_CONFR7_NB_0 0x00000010U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9542 #define JPEG_CONFR7_NB_1 0x00000020U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9543 #define JPEG_CONFR7_NB_2 0x00000040U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9544 #define JPEG_CONFR7_NB_3 0x00000080U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9545 #define JPEG_CONFR7_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */
AnnaBridge 126:abea610beb85 9546 #define JPEG_CONFR7_VSF_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9547 #define JPEG_CONFR7_VSF_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9548 #define JPEG_CONFR7_VSF_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9549 #define JPEG_CONFR7_VSF_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9550 #define JPEG_CONFR7_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */
AnnaBridge 126:abea610beb85 9551 #define JPEG_CONFR7_HSF_0 0x00001000U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9552 #define JPEG_CONFR7_HSF_1 0x00002000U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9553 #define JPEG_CONFR7_HSF_2 0x00004000U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9554 #define JPEG_CONFR7_HSF_3 0x00008000U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9555
AnnaBridge 126:abea610beb85 9556 /******************** Bit definition for CR register *******************/
AnnaBridge 126:abea610beb85 9557 #define JPEG_CR_JCEN 0x00000001U /*!<Enable the JPEG Codec Core */
AnnaBridge 126:abea610beb85 9558 #define JPEG_CR_IFTIE 0x00000002U /*!<Input FIFO Threshold Interrupt Enable */
AnnaBridge 126:abea610beb85 9559 #define JPEG_CR_IFNFIE 0x00000004U /*!<Input FIFO Not Full Interrupt Enable */
AnnaBridge 126:abea610beb85 9560 #define JPEG_CR_OFTIE 0x00000008U /*!<Output FIFO Threshold Interrupt Enable */
AnnaBridge 126:abea610beb85 9561 #define JPEG_CR_OFNEIE 0x00000010U /*!<Output FIFO Not Empty Interrupt Enable */
AnnaBridge 126:abea610beb85 9562 #define JPEG_CR_EOCIE 0x00000020U /*!<End of Conversion Interrupt Enable */
AnnaBridge 126:abea610beb85 9563 #define JPEG_CR_HPDIE 0x00000040U /*!<Header Parsing Done Interrupt Enable */
AnnaBridge 126:abea610beb85 9564 #define JPEG_CR_IDMAEN 0x00000800U /*!<Enable the DMA request generation for the input FIFO */
AnnaBridge 126:abea610beb85 9565 #define JPEG_CR_ODMAEN 0x00001000U /*!<Enable the DMA request generation for the output FIFO */
AnnaBridge 126:abea610beb85 9566 #define JPEG_CR_IFF 0x00002000U /*!<Flush the input FIFO */
AnnaBridge 126:abea610beb85 9567 #define JPEG_CR_OFF 0x00004000U /*!<Flush the output FIFO */
AnnaBridge 126:abea610beb85 9568
AnnaBridge 126:abea610beb85 9569 /******************** Bit definition for SR register *******************/
AnnaBridge 126:abea610beb85 9570 #define JPEG_SR_IFTF 0x00000002U /*!<Input FIFO is not full and is bellow its threshold flag */
AnnaBridge 126:abea610beb85 9571 #define JPEG_SR_IFNFF 0x00000004U /*!<Input FIFO Not Full Flag, a data can be written */
AnnaBridge 126:abea610beb85 9572 #define JPEG_SR_OFTF 0x00000008U /*!<Output FIFO is not empty and has reach its threshold */
AnnaBridge 126:abea610beb85 9573 #define JPEG_SR_OFNEF 0x000000010U /*!<Output FIFO is not empty, a data is available */
AnnaBridge 126:abea610beb85 9574 #define JPEG_SR_EOCF 0x000000020U /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
AnnaBridge 126:abea610beb85 9575 #define JPEG_SR_HPDF 0x000000040U /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
AnnaBridge 126:abea610beb85 9576 #define JPEG_SR_COF 0x000000080U /*!<JPEG Codec operation on going flag */
AnnaBridge 126:abea610beb85 9577
AnnaBridge 126:abea610beb85 9578 /******************** Bit definition for CFR register *******************/
AnnaBridge 126:abea610beb85 9579 #define JPEG_CFR_CEOCF 0x00000020U /*!<Clear End of Conversion Flag */
AnnaBridge 126:abea610beb85 9580 #define JPEG_CFR_CHPDF 0x00000040U /*!<Clear Header Parsing Done Flag */
AnnaBridge 126:abea610beb85 9581
AnnaBridge 126:abea610beb85 9582 /******************** Bit definition for DIR register ********************/
AnnaBridge 126:abea610beb85 9583 #define JPEG_DIR_DATAIN 0xFFFFFFFFU /*!<Data Input FIFO */
AnnaBridge 126:abea610beb85 9584
AnnaBridge 126:abea610beb85 9585 /******************** Bit definition for DOR register ********************/
AnnaBridge 126:abea610beb85 9586 #define JPEG_DOR_DATAOUT 0xFFFFFFFFU /*!<Data Output FIFO */
AnnaBridge 126:abea610beb85 9587
AnnaBridge 126:abea610beb85 9588 /******************************************************************************/
AnnaBridge 126:abea610beb85 9589 /* */
AnnaBridge 126:abea610beb85 9590 /* MDIOS */
AnnaBridge 126:abea610beb85 9591 /* */
AnnaBridge 126:abea610beb85 9592 /******************************************************************************/
AnnaBridge 126:abea610beb85 9593 /******************** Bit definition for MDIOS_CR register *******************/
AnnaBridge 126:abea610beb85 9594 #define MDIOS_CR_EN 0x00000001U /*!<Peripheral enable */
AnnaBridge 126:abea610beb85 9595 #define MDIOS_CR_WRIE 0x00000002U /*!<Register write interrupt enable */
AnnaBridge 126:abea610beb85 9596 #define MDIOS_CR_RDIE 0x00000004U /*!<Register Read Interrupt Enable */
AnnaBridge 126:abea610beb85 9597 #define MDIOS_CR_EIE 0x00000008U /*!<Error interrupt enable */
AnnaBridge 126:abea610beb85 9598 #define MDIOS_CR_DPC 0x00000080U /*!<Disable Preamble Check */
AnnaBridge 126:abea610beb85 9599 #define MDIOS_CR_PORT_ADDRESS 0x00001F00U /*!<PORT_ADDRESS[4:0] bits */
AnnaBridge 126:abea610beb85 9600 #define MDIOS_CR_PORT_ADDRESS_0 0x00000100U /*!<Bit 0 */
AnnaBridge 126:abea610beb85 9601 #define MDIOS_CR_PORT_ADDRESS_1 0x00000200U /*!<Bit 1 */
AnnaBridge 126:abea610beb85 9602 #define MDIOS_CR_PORT_ADDRESS_2 0x00000400U /*!<Bit 2 */
AnnaBridge 126:abea610beb85 9603 #define MDIOS_CR_PORT_ADDRESS_3 0x00000800U /*!<Bit 3 */
AnnaBridge 126:abea610beb85 9604 #define MDIOS_CR_PORT_ADDRESS_4 0x00001000U /*!<Bit 4 */
AnnaBridge 126:abea610beb85 9605
AnnaBridge 126:abea610beb85 9606 /******************** Bit definition for MDIOS_WRFR register *******************/
AnnaBridge 126:abea610beb85 9607 #define MDIOS_WRFR_WRF 0xFFFFFFFFU /*!<WRF[31:0] bits (Write flags for MDIO register 0 to 31) */
AnnaBridge 126:abea610beb85 9608
AnnaBridge 126:abea610beb85 9609 /******************** Bit definition for MDIOS_CWRFR register *******************/
AnnaBridge 126:abea610beb85 9610 #define MDIOS_CWRFR_CWRF 0xFFFFFFFFU /*!<CWRF[31:0] bits (Clear the write flag for MDIO register 0 to 31) */
AnnaBridge 126:abea610beb85 9611
AnnaBridge 126:abea610beb85 9612 /******************** Bit definition for MDIOS_RDFR register *******************/
AnnaBridge 126:abea610beb85 9613 #define MDIOS_RDFR_RDF 0xFFFFFFFFU /*!<RDF[31:0] bits (Read flags for MDIO registers 0 to 31) */
AnnaBridge 126:abea610beb85 9614
AnnaBridge 126:abea610beb85 9615 /******************** Bit definition for MDIOS_CRDFR register *******************/
AnnaBridge 126:abea610beb85 9616 #define MDIOS_CRDFR_CRDF 0xFFFFFFFFU /*!<CRDF[31:0] bits (Clear the read flag for MDIO registers 0 to 31) */
AnnaBridge 126:abea610beb85 9617
AnnaBridge 126:abea610beb85 9618 /******************** Bit definition for MDIOS_SR register *******************/
AnnaBridge 126:abea610beb85 9619 #define MDIOS_SR_PERF 0x00000001U /*!< Preamble error flag */
AnnaBridge 126:abea610beb85 9620 #define MDIOS_SR_SERF 0x00000002U /*!< Start error flag */
AnnaBridge 126:abea610beb85 9621 #define MDIOS_SR_TERF 0x00000004U /*!< Turnaround error flag */
AnnaBridge 126:abea610beb85 9622
AnnaBridge 126:abea610beb85 9623 /******************** Bit definition for MDIOS_CLRFR register *******************/
AnnaBridge 126:abea610beb85 9624 #define MDIOS_CLRFR_CPERF 0x00000001U /*!< Clear the preamble error flag */
AnnaBridge 126:abea610beb85 9625 #define MDIOS_CLRFR_CSERF 0x00000002U /*!< Clear the start error flag */
AnnaBridge 126:abea610beb85 9626 #define MDIOS_CLRFR_CTERF 0x00000004U /*!< Clear the turnaround error flag */
AnnaBridge 126:abea610beb85 9627
AnnaBridge 126:abea610beb85 9628 /******************************************************************************/
AnnaBridge 126:abea610beb85 9629 /* */
AnnaBridge 126:abea610beb85 9630 /* Display Serial Interface (DSI) */
AnnaBridge 126:abea610beb85 9631 /* */
AnnaBridge 126:abea610beb85 9632 /******************************************************************************/
AnnaBridge 126:abea610beb85 9633 /******************* Bit definition for DSI_VR register *****************/
AnnaBridge 126:abea610beb85 9634 #define DSI_VR 0x3133302AU /*!< DSI Host Version */
AnnaBridge 126:abea610beb85 9635
AnnaBridge 126:abea610beb85 9636 /******************* Bit definition for DSI_CR register *****************/
AnnaBridge 126:abea610beb85 9637 #define DSI_CR_EN 0x00000001U /*!< DSI Host power up and reset */
AnnaBridge 126:abea610beb85 9638
AnnaBridge 126:abea610beb85 9639 /******************* Bit definition for DSI_CCR register ****************/
AnnaBridge 126:abea610beb85 9640 #define DSI_CCR_TXECKDIV 0x000000FFU /*!< TX Escape Clock Division */
AnnaBridge 126:abea610beb85 9641 #define DSI_CCR_TXECKDIV0 0x00000001U
AnnaBridge 126:abea610beb85 9642 #define DSI_CCR_TXECKDIV1 0x00000002U
AnnaBridge 126:abea610beb85 9643 #define DSI_CCR_TXECKDIV2 0x00000004U
AnnaBridge 126:abea610beb85 9644 #define DSI_CCR_TXECKDIV3 0x00000008U
AnnaBridge 126:abea610beb85 9645 #define DSI_CCR_TXECKDIV4 0x00000010U
AnnaBridge 126:abea610beb85 9646 #define DSI_CCR_TXECKDIV5 0x00000020U
AnnaBridge 126:abea610beb85 9647 #define DSI_CCR_TXECKDIV6 0x00000040U
AnnaBridge 126:abea610beb85 9648 #define DSI_CCR_TXECKDIV7 0x00000080U
AnnaBridge 126:abea610beb85 9649
AnnaBridge 126:abea610beb85 9650 #define DSI_CCR_TOCKDIV 0x0000FF00U /*!< Timeout Clock Division */
AnnaBridge 126:abea610beb85 9651 #define DSI_CCR_TOCKDIV0 0x00000100U
AnnaBridge 126:abea610beb85 9652 #define DSI_CCR_TOCKDIV1 0x00000200U
AnnaBridge 126:abea610beb85 9653 #define DSI_CCR_TOCKDIV2 0x00000400U
AnnaBridge 126:abea610beb85 9654 #define DSI_CCR_TOCKDIV3 0x00000800U
AnnaBridge 126:abea610beb85 9655 #define DSI_CCR_TOCKDIV4 0x00001000U
AnnaBridge 126:abea610beb85 9656 #define DSI_CCR_TOCKDIV5 0x00002000U
AnnaBridge 126:abea610beb85 9657 #define DSI_CCR_TOCKDIV6 0x00004000U
AnnaBridge 126:abea610beb85 9658 #define DSI_CCR_TOCKDIV7 0x00008000U
AnnaBridge 126:abea610beb85 9659
AnnaBridge 126:abea610beb85 9660 /******************* Bit definition for DSI_LVCIDR register *************/
AnnaBridge 126:abea610beb85 9661 #define DSI_LVCIDR_VCID 0x00000003U /*!< Virtual Channel ID */
AnnaBridge 126:abea610beb85 9662 #define DSI_LVCIDR_VCID0 0x00000001U
AnnaBridge 126:abea610beb85 9663 #define DSI_LVCIDR_VCID1 0x00000002U
AnnaBridge 126:abea610beb85 9664
AnnaBridge 126:abea610beb85 9665 /******************* Bit definition for DSI_LCOLCR register *************/
AnnaBridge 126:abea610beb85 9666 #define DSI_LCOLCR_COLC 0x0000000FU /*!< Color Coding */
AnnaBridge 126:abea610beb85 9667 #define DSI_LCOLCR_COLC0 0x00000001U
AnnaBridge 126:abea610beb85 9668 #define DSI_LCOLCR_COLC1 0x00000020U
AnnaBridge 126:abea610beb85 9669 #define DSI_LCOLCR_COLC2 0x00000040U
AnnaBridge 126:abea610beb85 9670 #define DSI_LCOLCR_COLC3 0x00000080U
AnnaBridge 126:abea610beb85 9671
AnnaBridge 126:abea610beb85 9672 #define DSI_LCOLCR_LPE 0x00000100U /*!< Loosly Packet Enable */
AnnaBridge 126:abea610beb85 9673
AnnaBridge 126:abea610beb85 9674 /******************* Bit definition for DSI_LPCR register ***************/
AnnaBridge 126:abea610beb85 9675 #define DSI_LPCR_DEP 0x00000001U /*!< Data Enable Polarity */
AnnaBridge 126:abea610beb85 9676 #define DSI_LPCR_VSP 0x00000002U /*!< VSYNC Polarity */
AnnaBridge 126:abea610beb85 9677 #define DSI_LPCR_HSP 0x00000004U /*!< HSYNC Polarity */
AnnaBridge 126:abea610beb85 9678
AnnaBridge 126:abea610beb85 9679 /******************* Bit definition for DSI_LPMCR register **************/
AnnaBridge 126:abea610beb85 9680 #define DSI_LPMCR_VLPSIZE 0x000000FFU /*!< VACT Largest Packet Size */
AnnaBridge 126:abea610beb85 9681 #define DSI_LPMCR_VLPSIZE0 0x00000001U
AnnaBridge 126:abea610beb85 9682 #define DSI_LPMCR_VLPSIZE1 0x00000002U
AnnaBridge 126:abea610beb85 9683 #define DSI_LPMCR_VLPSIZE2 0x00000004U
AnnaBridge 126:abea610beb85 9684 #define DSI_LPMCR_VLPSIZE3 0x00000008U
AnnaBridge 126:abea610beb85 9685 #define DSI_LPMCR_VLPSIZE4 0x00000010U
AnnaBridge 126:abea610beb85 9686 #define DSI_LPMCR_VLPSIZE5 0x00000020U
AnnaBridge 126:abea610beb85 9687 #define DSI_LPMCR_VLPSIZE6 0x00000040U
AnnaBridge 126:abea610beb85 9688 #define DSI_LPMCR_VLPSIZE7 0x00000080U
AnnaBridge 126:abea610beb85 9689
AnnaBridge 126:abea610beb85 9690 #define DSI_LPMCR_LPSIZE 0x00FF0000U /*!< Largest Packet Size */
AnnaBridge 126:abea610beb85 9691 #define DSI_LPMCR_LPSIZE0 0x00010000U
AnnaBridge 126:abea610beb85 9692 #define DSI_LPMCR_LPSIZE1 0x00020000U
AnnaBridge 126:abea610beb85 9693 #define DSI_LPMCR_LPSIZE2 0x00040000U
AnnaBridge 126:abea610beb85 9694 #define DSI_LPMCR_LPSIZE3 0x00080000U
AnnaBridge 126:abea610beb85 9695 #define DSI_LPMCR_LPSIZE4 0x00100000U
AnnaBridge 126:abea610beb85 9696 #define DSI_LPMCR_LPSIZE5 0x00200000U
AnnaBridge 126:abea610beb85 9697 #define DSI_LPMCR_LPSIZE6 0x00400000U
AnnaBridge 126:abea610beb85 9698 #define DSI_LPMCR_LPSIZE7 0x00800000U
AnnaBridge 126:abea610beb85 9699
AnnaBridge 126:abea610beb85 9700 /******************* Bit definition for DSI_PCR register ****************/
AnnaBridge 126:abea610beb85 9701 #define DSI_PCR_ETTXE 0x00000001U /*!< EoTp Transmission Enable */
AnnaBridge 126:abea610beb85 9702 #define DSI_PCR_ETRXE 0x00000002U /*!< EoTp Reception Enable */
AnnaBridge 126:abea610beb85 9703 #define DSI_PCR_BTAE 0x00000004U /*!< Bus Turn Around Enable */
AnnaBridge 126:abea610beb85 9704 #define DSI_PCR_ECCRXE 0x00000008U /*!< ECC Reception Enable */
AnnaBridge 126:abea610beb85 9705 #define DSI_PCR_CRCRXE 0x00000010U /*!< CRC Reception Enable */
AnnaBridge 126:abea610beb85 9706
AnnaBridge 126:abea610beb85 9707 /******************* Bit definition for DSI_GVCIDR register *************/
AnnaBridge 126:abea610beb85 9708 #define DSI_GVCIDR_VCID 0x00000003U /*!< Virtual Channel ID */
AnnaBridge 126:abea610beb85 9709 #define DSI_GVCIDR_VCID0 0x00000001U
AnnaBridge 126:abea610beb85 9710 #define DSI_GVCIDR_VCID1 0x00000002U
AnnaBridge 126:abea610beb85 9711
AnnaBridge 126:abea610beb85 9712 /******************* Bit definition for DSI_MCR register ****************/
AnnaBridge 126:abea610beb85 9713 #define DSI_MCR_CMDM 0x00000001U /*!< Command Mode */
AnnaBridge 126:abea610beb85 9714
AnnaBridge 126:abea610beb85 9715 /******************* Bit definition for DSI_VMCR register ***************/
AnnaBridge 126:abea610beb85 9716 #define DSI_VMCR_VMT 0x00000003U /*!< Video Mode Type */
AnnaBridge 126:abea610beb85 9717 #define DSI_VMCR_VMT0 0x00000001U
AnnaBridge 126:abea610beb85 9718 #define DSI_VMCR_VMT1 0x00000002U
AnnaBridge 126:abea610beb85 9719
AnnaBridge 126:abea610beb85 9720 #define DSI_VMCR_LPVSAE 0x00000100U /*!< Low-Power Vertical Sync Active Enable */
AnnaBridge 126:abea610beb85 9721 #define DSI_VMCR_LPVBPE 0x00000200U /*!< Low-power Vertical Back-Porch Enable */
AnnaBridge 126:abea610beb85 9722 #define DSI_VMCR_LPVFPE 0x00000400U /*!< Low-power Vertical Front-porch Enable */
AnnaBridge 126:abea610beb85 9723 #define DSI_VMCR_LPVAE 0x00000800U /*!< Low-Power Vertical Active Enable */
AnnaBridge 126:abea610beb85 9724 #define DSI_VMCR_LPHBPE 0x00001000U /*!< Low-Power Horizontal Back-Porch Enable */
AnnaBridge 126:abea610beb85 9725 #define DSI_VMCR_LPHFPE 0x00002000U /*!< Low-Power Horizontal Front-Porch Enable */
AnnaBridge 126:abea610beb85 9726 #define DSI_VMCR_FBTAAE 0x00004000U /*!< Frame Bus-Turn-Around Acknowledge Enable */
AnnaBridge 126:abea610beb85 9727 #define DSI_VMCR_LPCE 0x00008000U /*!< Low-Power Command Enable */
AnnaBridge 126:abea610beb85 9728 #define DSI_VMCR_PGE 0x00010000U /*!< Pattern Generator Enable */
AnnaBridge 126:abea610beb85 9729 #define DSI_VMCR_PGM 0x00100000U /*!< Pattern Generator Mode */
AnnaBridge 126:abea610beb85 9730 #define DSI_VMCR_PGO 0x01000000U /*!< Pattern Generator Orientation */
AnnaBridge 126:abea610beb85 9731
AnnaBridge 126:abea610beb85 9732 /******************* Bit definition for DSI_VPCR register ***************/
AnnaBridge 126:abea610beb85 9733 #define DSI_VPCR_VPSIZE 0x00003FFFU /*!< Video Packet Size */
AnnaBridge 126:abea610beb85 9734 #define DSI_VPCR_VPSIZE0 0x00000001U
AnnaBridge 126:abea610beb85 9735 #define DSI_VPCR_VPSIZE1 0x00000002U
AnnaBridge 126:abea610beb85 9736 #define DSI_VPCR_VPSIZE2 0x00000004U
AnnaBridge 126:abea610beb85 9737 #define DSI_VPCR_VPSIZE3 0x00000008U
AnnaBridge 126:abea610beb85 9738 #define DSI_VPCR_VPSIZE4 0x00000010U
AnnaBridge 126:abea610beb85 9739 #define DSI_VPCR_VPSIZE5 0x00000020U
AnnaBridge 126:abea610beb85 9740 #define DSI_VPCR_VPSIZE6 0x00000040U
AnnaBridge 126:abea610beb85 9741 #define DSI_VPCR_VPSIZE7 0x00000080U
AnnaBridge 126:abea610beb85 9742 #define DSI_VPCR_VPSIZE8 0x00000100U
AnnaBridge 126:abea610beb85 9743 #define DSI_VPCR_VPSIZE9 0x00000200U
AnnaBridge 126:abea610beb85 9744 #define DSI_VPCR_VPSIZE10 0x00000400U
AnnaBridge 126:abea610beb85 9745 #define DSI_VPCR_VPSIZE11 0x00000800U
AnnaBridge 126:abea610beb85 9746 #define DSI_VPCR_VPSIZE12 0x00001000U
AnnaBridge 126:abea610beb85 9747 #define DSI_VPCR_VPSIZE13 0x00002000U
AnnaBridge 126:abea610beb85 9748
AnnaBridge 126:abea610beb85 9749 /******************* Bit definition for DSI_VCCR register ***************/
AnnaBridge 126:abea610beb85 9750 #define DSI_VCCR_NUMC 0x00001FFFU /*!< Number of Chunks */
AnnaBridge 126:abea610beb85 9751 #define DSI_VCCR_NUMC0 0x00000001U
AnnaBridge 126:abea610beb85 9752 #define DSI_VCCR_NUMC1 0x00000002U
AnnaBridge 126:abea610beb85 9753 #define DSI_VCCR_NUMC2 0x00000004U
AnnaBridge 126:abea610beb85 9754 #define DSI_VCCR_NUMC3 0x00000008U
AnnaBridge 126:abea610beb85 9755 #define DSI_VCCR_NUMC4 0x00000010U
AnnaBridge 126:abea610beb85 9756 #define DSI_VCCR_NUMC5 0x00000020U
AnnaBridge 126:abea610beb85 9757 #define DSI_VCCR_NUMC6 0x00000040U
AnnaBridge 126:abea610beb85 9758 #define DSI_VCCR_NUMC7 0x00000080U
AnnaBridge 126:abea610beb85 9759 #define DSI_VCCR_NUMC8 0x00000100U
AnnaBridge 126:abea610beb85 9760 #define DSI_VCCR_NUMC9 0x00000200U
AnnaBridge 126:abea610beb85 9761 #define DSI_VCCR_NUMC10 0x00000400U
AnnaBridge 126:abea610beb85 9762 #define DSI_VCCR_NUMC11 0x00000800U
AnnaBridge 126:abea610beb85 9763 #define DSI_VCCR_NUMC12 0x00001000U
AnnaBridge 126:abea610beb85 9764
AnnaBridge 126:abea610beb85 9765 /******************* Bit definition for DSI_VNPCR register **************/
AnnaBridge 126:abea610beb85 9766 #define DSI_VNPCR_NPSIZE 0x00001FFFU /*!< Null Packet Size */
AnnaBridge 126:abea610beb85 9767 #define DSI_VNPCR_NPSIZE0 0x00000001U
AnnaBridge 126:abea610beb85 9768 #define DSI_VNPCR_NPSIZE1 0x00000002U
AnnaBridge 126:abea610beb85 9769 #define DSI_VNPCR_NPSIZE2 0x00000004U
AnnaBridge 126:abea610beb85 9770 #define DSI_VNPCR_NPSIZE3 0x00000008U
AnnaBridge 126:abea610beb85 9771 #define DSI_VNPCR_NPSIZE4 0x00000010U
AnnaBridge 126:abea610beb85 9772 #define DSI_VNPCR_NPSIZE5 0x00000020U
AnnaBridge 126:abea610beb85 9773 #define DSI_VNPCR_NPSIZE6 0x00000040U
AnnaBridge 126:abea610beb85 9774 #define DSI_VNPCR_NPSIZE7 0x00000080U
AnnaBridge 126:abea610beb85 9775 #define DSI_VNPCR_NPSIZE8 0x00000100U
AnnaBridge 126:abea610beb85 9776 #define DSI_VNPCR_NPSIZE9 0x00000200U
AnnaBridge 126:abea610beb85 9777 #define DSI_VNPCR_NPSIZE10 0x00000400U
AnnaBridge 126:abea610beb85 9778 #define DSI_VNPCR_NPSIZE11 0x00000800U
AnnaBridge 126:abea610beb85 9779 #define DSI_VNPCR_NPSIZE12 0x00001000U
AnnaBridge 126:abea610beb85 9780
AnnaBridge 126:abea610beb85 9781 /******************* Bit definition for DSI_VHSACR register *************/
AnnaBridge 126:abea610beb85 9782 #define DSI_VHSACR_HSA 0x00000FFFU /*!< Horizontal Synchronism Active duration */
AnnaBridge 126:abea610beb85 9783 #define DSI_VHSACR_HSA0 0x00000001U
AnnaBridge 126:abea610beb85 9784 #define DSI_VHSACR_HSA1 0x00000002U
AnnaBridge 126:abea610beb85 9785 #define DSI_VHSACR_HSA2 0x00000004U
AnnaBridge 126:abea610beb85 9786 #define DSI_VHSACR_HSA3 0x00000008U
AnnaBridge 126:abea610beb85 9787 #define DSI_VHSACR_HSA4 0x00000010U
AnnaBridge 126:abea610beb85 9788 #define DSI_VHSACR_HSA5 0x00000020U
AnnaBridge 126:abea610beb85 9789 #define DSI_VHSACR_HSA6 0x00000040U
AnnaBridge 126:abea610beb85 9790 #define DSI_VHSACR_HSA7 0x00000080U
AnnaBridge 126:abea610beb85 9791 #define DSI_VHSACR_HSA8 0x00000100U
AnnaBridge 126:abea610beb85 9792 #define DSI_VHSACR_HSA9 0x00000200U
AnnaBridge 126:abea610beb85 9793 #define DSI_VHSACR_HSA10 0x00000400U
AnnaBridge 126:abea610beb85 9794 #define DSI_VHSACR_HSA11 0x00000800U
AnnaBridge 126:abea610beb85 9795
AnnaBridge 126:abea610beb85 9796 /******************* Bit definition for DSI_VHBPCR register *************/
AnnaBridge 126:abea610beb85 9797 #define DSI_VHBPCR_HBP 0x00000FFFU /*!< Horizontal Back-Porch duration */
AnnaBridge 126:abea610beb85 9798 #define DSI_VHBPCR_HBP0 0x00000001U
AnnaBridge 126:abea610beb85 9799 #define DSI_VHBPCR_HBP1 0x00000002U
AnnaBridge 126:abea610beb85 9800 #define DSI_VHBPCR_HBP2 0x00000004U
AnnaBridge 126:abea610beb85 9801 #define DSI_VHBPCR_HBP3 0x00000008U
AnnaBridge 126:abea610beb85 9802 #define DSI_VHBPCR_HBP4 0x00000010U
AnnaBridge 126:abea610beb85 9803 #define DSI_VHBPCR_HBP5 0x00000020U
AnnaBridge 126:abea610beb85 9804 #define DSI_VHBPCR_HBP6 0x00000040U
AnnaBridge 126:abea610beb85 9805 #define DSI_VHBPCR_HBP7 0x00000080U
AnnaBridge 126:abea610beb85 9806 #define DSI_VHBPCR_HBP8 0x00000100U
AnnaBridge 126:abea610beb85 9807 #define DSI_VHBPCR_HBP9 0x00000200U
AnnaBridge 126:abea610beb85 9808 #define DSI_VHBPCR_HBP10 0x00000400U
AnnaBridge 126:abea610beb85 9809 #define DSI_VHBPCR_HBP11 0x00000800U
AnnaBridge 126:abea610beb85 9810
AnnaBridge 126:abea610beb85 9811 /******************* Bit definition for DSI_VLCR register ***************/
AnnaBridge 126:abea610beb85 9812 #define DSI_VLCR_HLINE 0x00007FFFU /*!< Horizontal Line duration */
AnnaBridge 126:abea610beb85 9813 #define DSI_VLCR_HLINE0 0x00000001U
AnnaBridge 126:abea610beb85 9814 #define DSI_VLCR_HLINE1 0x00000002U
AnnaBridge 126:abea610beb85 9815 #define DSI_VLCR_HLINE2 0x00000004U
AnnaBridge 126:abea610beb85 9816 #define DSI_VLCR_HLINE3 0x00000008U
AnnaBridge 126:abea610beb85 9817 #define DSI_VLCR_HLINE4 0x00000010U
AnnaBridge 126:abea610beb85 9818 #define DSI_VLCR_HLINE5 0x00000020U
AnnaBridge 126:abea610beb85 9819 #define DSI_VLCR_HLINE6 0x00000040U
AnnaBridge 126:abea610beb85 9820 #define DSI_VLCR_HLINE7 0x00000080U
AnnaBridge 126:abea610beb85 9821 #define DSI_VLCR_HLINE8 0x00000100U
AnnaBridge 126:abea610beb85 9822 #define DSI_VLCR_HLINE9 0x00000200U
AnnaBridge 126:abea610beb85 9823 #define DSI_VLCR_HLINE10 0x00000400U
AnnaBridge 126:abea610beb85 9824 #define DSI_VLCR_HLINE11 0x00000800U
AnnaBridge 126:abea610beb85 9825 #define DSI_VLCR_HLINE12 0x00001000U
AnnaBridge 126:abea610beb85 9826 #define DSI_VLCR_HLINE13 0x00002000U
AnnaBridge 126:abea610beb85 9827 #define DSI_VLCR_HLINE14 0x00004000U
AnnaBridge 126:abea610beb85 9828
AnnaBridge 126:abea610beb85 9829 /******************* Bit definition for DSI_VVSACR register *************/
AnnaBridge 126:abea610beb85 9830 #define DSI_VVSACR_VSA 0x000003FFU /*!< Vertical Synchronism Active duration */
AnnaBridge 126:abea610beb85 9831 #define DSI_VVSACR_VSA0 0x00000001U
AnnaBridge 126:abea610beb85 9832 #define DSI_VVSACR_VSA1 0x00000002U
AnnaBridge 126:abea610beb85 9833 #define DSI_VVSACR_VSA2 0x00000004U
AnnaBridge 126:abea610beb85 9834 #define DSI_VVSACR_VSA3 0x00000008U
AnnaBridge 126:abea610beb85 9835 #define DSI_VVSACR_VSA4 0x00000010U
AnnaBridge 126:abea610beb85 9836 #define DSI_VVSACR_VSA5 0x00000020U
AnnaBridge 126:abea610beb85 9837 #define DSI_VVSACR_VSA6 0x00000040U
AnnaBridge 126:abea610beb85 9838 #define DSI_VVSACR_VSA7 0x00000080U
AnnaBridge 126:abea610beb85 9839 #define DSI_VVSACR_VSA8 0x00000100U
AnnaBridge 126:abea610beb85 9840 #define DSI_VVSACR_VSA9 0x00000200U
AnnaBridge 126:abea610beb85 9841
AnnaBridge 126:abea610beb85 9842 /******************* Bit definition for DSI_VVBPCR register *************/
AnnaBridge 126:abea610beb85 9843 #define DSI_VVBPCR_VBP 0x000003FFU /*!< Vertical Back-Porch duration */
AnnaBridge 126:abea610beb85 9844 #define DSI_VVBPCR_VBP0 0x00000001U
AnnaBridge 126:abea610beb85 9845 #define DSI_VVBPCR_VBP1 0x00000002U
AnnaBridge 126:abea610beb85 9846 #define DSI_VVBPCR_VBP2 0x00000004U
AnnaBridge 126:abea610beb85 9847 #define DSI_VVBPCR_VBP3 0x00000008U
AnnaBridge 126:abea610beb85 9848 #define DSI_VVBPCR_VBP4 0x00000010U
AnnaBridge 126:abea610beb85 9849 #define DSI_VVBPCR_VBP5 0x00000020U
AnnaBridge 126:abea610beb85 9850 #define DSI_VVBPCR_VBP6 0x00000040U
AnnaBridge 126:abea610beb85 9851 #define DSI_VVBPCR_VBP7 0x00000080U
AnnaBridge 126:abea610beb85 9852 #define DSI_VVBPCR_VBP8 0x00000100U
AnnaBridge 126:abea610beb85 9853 #define DSI_VVBPCR_VBP9 0x00000200U
AnnaBridge 126:abea610beb85 9854
AnnaBridge 126:abea610beb85 9855 /******************* Bit definition for DSI_VVFPCR register *************/
AnnaBridge 126:abea610beb85 9856 #define DSI_VVFPCR_VFP 0x000003FFU /*!< Vertical Front-Porch duration */
AnnaBridge 126:abea610beb85 9857 #define DSI_VVFPCR_VFP0 0x00000001U
AnnaBridge 126:abea610beb85 9858 #define DSI_VVFPCR_VFP1 0x00000002U
AnnaBridge 126:abea610beb85 9859 #define DSI_VVFPCR_VFP2 0x00000004U
AnnaBridge 126:abea610beb85 9860 #define DSI_VVFPCR_VFP3 0x00000008U
AnnaBridge 126:abea610beb85 9861 #define DSI_VVFPCR_VFP4 0x00000010U
AnnaBridge 126:abea610beb85 9862 #define DSI_VVFPCR_VFP5 0x00000020U
AnnaBridge 126:abea610beb85 9863 #define DSI_VVFPCR_VFP6 0x00000040U
AnnaBridge 126:abea610beb85 9864 #define DSI_VVFPCR_VFP7 0x00000080U
AnnaBridge 126:abea610beb85 9865 #define DSI_VVFPCR_VFP8 0x00000100U
AnnaBridge 126:abea610beb85 9866 #define DSI_VVFPCR_VFP9 0x00000200U
AnnaBridge 126:abea610beb85 9867
AnnaBridge 126:abea610beb85 9868 /******************* Bit definition for DSI_VVACR register **************/
AnnaBridge 126:abea610beb85 9869 #define DSI_VVACR_VA 0x00003FFFU /*!< Vertical Active duration */
AnnaBridge 126:abea610beb85 9870 #define DSI_VVACR_VA0 0x00000001U
AnnaBridge 126:abea610beb85 9871 #define DSI_VVACR_VA1 0x00000002U
AnnaBridge 126:abea610beb85 9872 #define DSI_VVACR_VA2 0x00000004U
AnnaBridge 126:abea610beb85 9873 #define DSI_VVACR_VA3 0x00000008U
AnnaBridge 126:abea610beb85 9874 #define DSI_VVACR_VA4 0x00000010U
AnnaBridge 126:abea610beb85 9875 #define DSI_VVACR_VA5 0x00000020U
AnnaBridge 126:abea610beb85 9876 #define DSI_VVACR_VA6 0x00000040U
AnnaBridge 126:abea610beb85 9877 #define DSI_VVACR_VA7 0x00000080U
AnnaBridge 126:abea610beb85 9878 #define DSI_VVACR_VA8 0x00000100U
AnnaBridge 126:abea610beb85 9879 #define DSI_VVACR_VA9 0x00000200U
AnnaBridge 126:abea610beb85 9880 #define DSI_VVACR_VA10 0x00000400U
AnnaBridge 126:abea610beb85 9881 #define DSI_VVACR_VA11 0x00000800U
AnnaBridge 126:abea610beb85 9882 #define DSI_VVACR_VA12 0x00001000U
AnnaBridge 126:abea610beb85 9883 #define DSI_VVACR_VA13 0x00002000U
AnnaBridge 126:abea610beb85 9884
AnnaBridge 126:abea610beb85 9885 /******************* Bit definition for DSI_LCCR register ***************/
AnnaBridge 126:abea610beb85 9886 #define DSI_LCCR_CMDSIZE 0x0000FFFFU /*!< Command Size */
AnnaBridge 126:abea610beb85 9887 #define DSI_LCCR_CMDSIZE0 0x00000001U
AnnaBridge 126:abea610beb85 9888 #define DSI_LCCR_CMDSIZE1 0x00000002U
AnnaBridge 126:abea610beb85 9889 #define DSI_LCCR_CMDSIZE2 0x00000004U
AnnaBridge 126:abea610beb85 9890 #define DSI_LCCR_CMDSIZE3 0x00000008U
AnnaBridge 126:abea610beb85 9891 #define DSI_LCCR_CMDSIZE4 0x00000010U
AnnaBridge 126:abea610beb85 9892 #define DSI_LCCR_CMDSIZE5 0x00000020U
AnnaBridge 126:abea610beb85 9893 #define DSI_LCCR_CMDSIZE6 0x00000040U
AnnaBridge 126:abea610beb85 9894 #define DSI_LCCR_CMDSIZE7 0x00000080U
AnnaBridge 126:abea610beb85 9895 #define DSI_LCCR_CMDSIZE8 0x00000100U
AnnaBridge 126:abea610beb85 9896 #define DSI_LCCR_CMDSIZE9 0x00000200U
AnnaBridge 126:abea610beb85 9897 #define DSI_LCCR_CMDSIZE10 0x00000400U
AnnaBridge 126:abea610beb85 9898 #define DSI_LCCR_CMDSIZE11 0x00000800U
AnnaBridge 126:abea610beb85 9899 #define DSI_LCCR_CMDSIZE12 0x00001000U
AnnaBridge 126:abea610beb85 9900 #define DSI_LCCR_CMDSIZE13 0x00002000U
AnnaBridge 126:abea610beb85 9901 #define DSI_LCCR_CMDSIZE14 0x00004000U
AnnaBridge 126:abea610beb85 9902 #define DSI_LCCR_CMDSIZE15 0x00008000U
AnnaBridge 126:abea610beb85 9903
AnnaBridge 126:abea610beb85 9904 /******************* Bit definition for DSI_CMCR register ***************/
AnnaBridge 126:abea610beb85 9905 #define DSI_CMCR_TEARE 0x00000001U /*!< Tearing Effect Acknowledge Request Enable */
AnnaBridge 126:abea610beb85 9906 #define DSI_CMCR_ARE 0x00000002U /*!< Acknowledge Request Enable */
AnnaBridge 126:abea610beb85 9907 #define DSI_CMCR_GSW0TX 0x00000100U /*!< Generic Short Write Zero parameters Transmission */
AnnaBridge 126:abea610beb85 9908 #define DSI_CMCR_GSW1TX 0x00000200U /*!< Generic Short Write One parameters Transmission */
AnnaBridge 126:abea610beb85 9909 #define DSI_CMCR_GSW2TX 0x00000400U /*!< Generic Short Write Two parameters Transmission */
AnnaBridge 126:abea610beb85 9910 #define DSI_CMCR_GSR0TX 0x00000800U /*!< Generic Short Read Zero parameters Transmission */
AnnaBridge 126:abea610beb85 9911 #define DSI_CMCR_GSR1TX 0x00001000U /*!< Generic Short Read One parameters Transmission */
AnnaBridge 126:abea610beb85 9912 #define DSI_CMCR_GSR2TX 0x00002000U /*!< Generic Short Read Two parameters Transmission */
AnnaBridge 126:abea610beb85 9913 #define DSI_CMCR_GLWTX 0x00004000U /*!< Generic Long Write Transmission */
AnnaBridge 126:abea610beb85 9914 #define DSI_CMCR_DSW0TX 0x00010000U /*!< DCS Short Write Zero parameter Transmission */
AnnaBridge 126:abea610beb85 9915 #define DSI_CMCR_DSW1TX 0x00020000U /*!< DCS Short Read One parameter Transmission */
AnnaBridge 126:abea610beb85 9916 #define DSI_CMCR_DSR0TX 0x00040000U /*!< DCS Short Read Zero parameter Transmission */
AnnaBridge 126:abea610beb85 9917 #define DSI_CMCR_DLWTX 0x00080000U /*!< DCS Long Write Transmission */
AnnaBridge 126:abea610beb85 9918 #define DSI_CMCR_MRDPS 0x01000000U /*!< Maximum Read Packet Size */
AnnaBridge 126:abea610beb85 9919
AnnaBridge 126:abea610beb85 9920 /******************* Bit definition for DSI_GHCR register ***************/
AnnaBridge 126:abea610beb85 9921 #define DSI_GHCR_DT 0x0000003FU /*!< Type */
AnnaBridge 126:abea610beb85 9922 #define DSI_GHCR_DT0 0x00000001U
AnnaBridge 126:abea610beb85 9923 #define DSI_GHCR_DT1 0x00000002U
AnnaBridge 126:abea610beb85 9924 #define DSI_GHCR_DT2 0x00000004U
AnnaBridge 126:abea610beb85 9925 #define DSI_GHCR_DT3 0x00000008U
AnnaBridge 126:abea610beb85 9926 #define DSI_GHCR_DT4 0x00000010U
AnnaBridge 126:abea610beb85 9927 #define DSI_GHCR_DT5 0x00000020U
AnnaBridge 126:abea610beb85 9928
AnnaBridge 126:abea610beb85 9929 #define DSI_GHCR_VCID 0x000000C0U /*!< Channel */
AnnaBridge 126:abea610beb85 9930 #define DSI_GHCR_VCID0 0x00000040U
AnnaBridge 126:abea610beb85 9931 #define DSI_GHCR_VCID1 0x00000080U
AnnaBridge 126:abea610beb85 9932
AnnaBridge 126:abea610beb85 9933 #define DSI_GHCR_WCLSB 0x0000FF00U /*!< WordCount LSB */
AnnaBridge 126:abea610beb85 9934 #define DSI_GHCR_WCLSB0 0x00000100U
AnnaBridge 126:abea610beb85 9935 #define DSI_GHCR_WCLSB1 0x00000200U
AnnaBridge 126:abea610beb85 9936 #define DSI_GHCR_WCLSB2 0x00000400U
AnnaBridge 126:abea610beb85 9937 #define DSI_GHCR_WCLSB3 0x00000800U
AnnaBridge 126:abea610beb85 9938 #define DSI_GHCR_WCLSB4 0x00001000U
AnnaBridge 126:abea610beb85 9939 #define DSI_GHCR_WCLSB5 0x00002000U
AnnaBridge 126:abea610beb85 9940 #define DSI_GHCR_WCLSB6 0x00004000U
AnnaBridge 126:abea610beb85 9941 #define DSI_GHCR_WCLSB7 0x00008000U
AnnaBridge 126:abea610beb85 9942
AnnaBridge 126:abea610beb85 9943 #define DSI_GHCR_WCMSB 0x00FF0000U /*!< WordCount MSB */
AnnaBridge 126:abea610beb85 9944 #define DSI_GHCR_WCMSB0 0x00010000U
AnnaBridge 126:abea610beb85 9945 #define DSI_GHCR_WCMSB1 0x00020000U
AnnaBridge 126:abea610beb85 9946 #define DSI_GHCR_WCMSB2 0x00040000U
AnnaBridge 126:abea610beb85 9947 #define DSI_GHCR_WCMSB3 0x00080000U
AnnaBridge 126:abea610beb85 9948 #define DSI_GHCR_WCMSB4 0x00100000U
AnnaBridge 126:abea610beb85 9949 #define DSI_GHCR_WCMSB5 0x00200000U
AnnaBridge 126:abea610beb85 9950 #define DSI_GHCR_WCMSB6 0x00400000U
AnnaBridge 126:abea610beb85 9951 #define DSI_GHCR_WCMSB7 0x00800000U
AnnaBridge 126:abea610beb85 9952
AnnaBridge 126:abea610beb85 9953 /******************* Bit definition for DSI_GPDR register ***************/
AnnaBridge 126:abea610beb85 9954 #define DSI_GPDR_DATA1 0x000000FFU /*!< Payload Byte 1 */
AnnaBridge 126:abea610beb85 9955 #define DSI_GPDR_DATA1_0 0x00000001U
AnnaBridge 126:abea610beb85 9956 #define DSI_GPDR_DATA1_1 0x00000002U
AnnaBridge 126:abea610beb85 9957 #define DSI_GPDR_DATA1_2 0x00000004U
AnnaBridge 126:abea610beb85 9958 #define DSI_GPDR_DATA1_3 0x00000008U
AnnaBridge 126:abea610beb85 9959 #define DSI_GPDR_DATA1_4 0x00000010U
AnnaBridge 126:abea610beb85 9960 #define DSI_GPDR_DATA1_5 0x00000020U
AnnaBridge 126:abea610beb85 9961 #define DSI_GPDR_DATA1_6 0x00000040U
AnnaBridge 126:abea610beb85 9962 #define DSI_GPDR_DATA1_7 0x00000080U
AnnaBridge 126:abea610beb85 9963
AnnaBridge 126:abea610beb85 9964 #define DSI_GPDR_DATA2 0x0000FF00U /*!< Payload Byte 2 */
AnnaBridge 126:abea610beb85 9965 #define DSI_GPDR_DATA2_0 0x00000100U
AnnaBridge 126:abea610beb85 9966 #define DSI_GPDR_DATA2_1 0x00000200U
AnnaBridge 126:abea610beb85 9967 #define DSI_GPDR_DATA2_2 0x00000400U
AnnaBridge 126:abea610beb85 9968 #define DSI_GPDR_DATA2_3 0x00000800U
AnnaBridge 126:abea610beb85 9969 #define DSI_GPDR_DATA2_4 0x00001000U
AnnaBridge 126:abea610beb85 9970 #define DSI_GPDR_DATA2_5 0x00002000U
AnnaBridge 126:abea610beb85 9971 #define DSI_GPDR_DATA2_6 0x00004000U
AnnaBridge 126:abea610beb85 9972 #define DSI_GPDR_DATA2_7 0x00008000U
AnnaBridge 126:abea610beb85 9973
AnnaBridge 126:abea610beb85 9974 #define DSI_GPDR_DATA3 0x00FF0000U /*!< Payload Byte 3 */
AnnaBridge 126:abea610beb85 9975 #define DSI_GPDR_DATA3_0 0x00010000U
AnnaBridge 126:abea610beb85 9976 #define DSI_GPDR_DATA3_1 0x00020000U
AnnaBridge 126:abea610beb85 9977 #define DSI_GPDR_DATA3_2 0x00040000U
AnnaBridge 126:abea610beb85 9978 #define DSI_GPDR_DATA3_3 0x00080000U
AnnaBridge 126:abea610beb85 9979 #define DSI_GPDR_DATA3_4 0x00100000U
AnnaBridge 126:abea610beb85 9980 #define DSI_GPDR_DATA3_5 0x00200000U
AnnaBridge 126:abea610beb85 9981 #define DSI_GPDR_DATA3_6 0x00400000U
AnnaBridge 126:abea610beb85 9982 #define DSI_GPDR_DATA3_7 0x00800000U
AnnaBridge 126:abea610beb85 9983
AnnaBridge 126:abea610beb85 9984 #define DSI_GPDR_DATA4 0xFF000000U /*!< Payload Byte 4 */
AnnaBridge 126:abea610beb85 9985 #define DSI_GPDR_DATA4_0 0x01000000U
AnnaBridge 126:abea610beb85 9986 #define DSI_GPDR_DATA4_1 0x02000000U
AnnaBridge 126:abea610beb85 9987 #define DSI_GPDR_DATA4_2 0x04000000U
AnnaBridge 126:abea610beb85 9988 #define DSI_GPDR_DATA4_3 0x08000000U
AnnaBridge 126:abea610beb85 9989 #define DSI_GPDR_DATA4_4 0x10000000U
AnnaBridge 126:abea610beb85 9990 #define DSI_GPDR_DATA4_5 0x20000000U
AnnaBridge 126:abea610beb85 9991 #define DSI_GPDR_DATA4_6 0x40000000U
AnnaBridge 126:abea610beb85 9992 #define DSI_GPDR_DATA4_7 0x80000000U
AnnaBridge 126:abea610beb85 9993
AnnaBridge 126:abea610beb85 9994 /******************* Bit definition for DSI_GPSR register ***************/
AnnaBridge 126:abea610beb85 9995 #define DSI_GPSR_CMDFE 0x00000001U /*!< Command FIFO Empty */
AnnaBridge 126:abea610beb85 9996 #define DSI_GPSR_CMDFF 0x00000002U /*!< Command FIFO Full */
AnnaBridge 126:abea610beb85 9997 #define DSI_GPSR_PWRFE 0x00000004U /*!< Payload Write FIFO Empty */
AnnaBridge 126:abea610beb85 9998 #define DSI_GPSR_PWRFF 0x00000008U /*!< Payload Write FIFO Full */
AnnaBridge 126:abea610beb85 9999 #define DSI_GPSR_PRDFE 0x00000010U /*!< Payload Read FIFO Empty */
AnnaBridge 126:abea610beb85 10000 #define DSI_GPSR_PRDFF 0x00000020U /*!< Payload Read FIFO Full */
AnnaBridge 126:abea610beb85 10001 #define DSI_GPSR_RCB 0x00000040U /*!< Read Command Busy */
AnnaBridge 126:abea610beb85 10002
AnnaBridge 126:abea610beb85 10003 /******************* Bit definition for DSI_TCCR0register **************/
AnnaBridge 126:abea610beb85 10004 #define DSI_TCCR0_LPRX_TOCNT 0x0000FFFFU /*!< Low-power Reception Timeout Counter */
AnnaBridge 126:abea610beb85 10005 #define DSI_TCCR0_LPRX_TOCNT0 0x00000001U
AnnaBridge 126:abea610beb85 10006 #define DSI_TCCR0_LPRX_TOCNT1 0x00000002U
AnnaBridge 126:abea610beb85 10007 #define DSI_TCCR0_LPRX_TOCNT2 0x00000004U
AnnaBridge 126:abea610beb85 10008 #define DSI_TCCR0_LPRX_TOCNT3 0x00000008U
AnnaBridge 126:abea610beb85 10009 #define DSI_TCCR0_LPRX_TOCNT4 0x00000010U
AnnaBridge 126:abea610beb85 10010 #define DSI_TCCR0_LPRX_TOCNT5 0x00000020U
AnnaBridge 126:abea610beb85 10011 #define DSI_TCCR0_LPRX_TOCNT6 0x00000040U
AnnaBridge 126:abea610beb85 10012 #define DSI_TCCR0_LPRX_TOCNT7 0x00000080U
AnnaBridge 126:abea610beb85 10013 #define DSI_TCCR0_LPRX_TOCNT8 0x00000100U
AnnaBridge 126:abea610beb85 10014 #define DSI_TCCR0_LPRX_TOCNT9 0x00000200U
AnnaBridge 126:abea610beb85 10015 #define DSI_TCCR0_LPRX_TOCNT10 0x00000400U
AnnaBridge 126:abea610beb85 10016 #define DSI_TCCR0_LPRX_TOCNT11 0x00000800U
AnnaBridge 126:abea610beb85 10017 #define DSI_TCCR0_LPRX_TOCNT12 0x00001000U
AnnaBridge 126:abea610beb85 10018 #define DSI_TCCR0_LPRX_TOCNT13 0x00002000U
AnnaBridge 126:abea610beb85 10019 #define DSI_TCCR0_LPRX_TOCNT14 0x00004000U
AnnaBridge 126:abea610beb85 10020 #define DSI_TCCR0_LPRX_TOCNT15 0x00008000U
AnnaBridge 126:abea610beb85 10021
AnnaBridge 126:abea610beb85 10022 #define DSI_TCCR0_HSTX_TOCNT 0xFFFF0000U /*!< High-Speed Transmission Timeout Counter */
AnnaBridge 126:abea610beb85 10023 #define DSI_TCCR0_HSTX_TOCNT0 0x00010000U
AnnaBridge 126:abea610beb85 10024 #define DSI_TCCR0_HSTX_TOCNT1 0x00020000U
AnnaBridge 126:abea610beb85 10025 #define DSI_TCCR0_HSTX_TOCNT2 0x00040000U
AnnaBridge 126:abea610beb85 10026 #define DSI_TCCR0_HSTX_TOCNT3 0x00080000U
AnnaBridge 126:abea610beb85 10027 #define DSI_TCCR0_HSTX_TOCNT4 0x00100000U
AnnaBridge 126:abea610beb85 10028 #define DSI_TCCR0_HSTX_TOCNT5 0x00200000U
AnnaBridge 126:abea610beb85 10029 #define DSI_TCCR0_HSTX_TOCNT6 0x00400000U
AnnaBridge 126:abea610beb85 10030 #define DSI_TCCR0_HSTX_TOCNT7 0x00800000U
AnnaBridge 126:abea610beb85 10031 #define DSI_TCCR0_HSTX_TOCNT8 0x01000000U
AnnaBridge 126:abea610beb85 10032 #define DSI_TCCR0_HSTX_TOCNT9 0x02000000U
AnnaBridge 126:abea610beb85 10033 #define DSI_TCCR0_HSTX_TOCNT10 0x04000000U
AnnaBridge 126:abea610beb85 10034 #define DSI_TCCR0_HSTX_TOCNT11 0x08000000U
AnnaBridge 126:abea610beb85 10035 #define DSI_TCCR0_HSTX_TOCNT12 0x10000000U
AnnaBridge 126:abea610beb85 10036 #define DSI_TCCR0_HSTX_TOCNT13 0x20000000U
AnnaBridge 126:abea610beb85 10037 #define DSI_TCCR0_HSTX_TOCNT14 0x40000000U
AnnaBridge 126:abea610beb85 10038 #define DSI_TCCR0_HSTX_TOCNT15 0x80000000U
AnnaBridge 126:abea610beb85 10039
AnnaBridge 126:abea610beb85 10040 /******************* Bit definition for DSI_TCCR1register **************/
AnnaBridge 126:abea610beb85 10041 #define DSI_TCCR1_HSRD_TOCNT 0x0000FFFFU /*!< High-Speed Read Timeout Counter */
AnnaBridge 126:abea610beb85 10042 #define DSI_TCCR1_HSRD_TOCNT0 0x00000001U
AnnaBridge 126:abea610beb85 10043 #define DSI_TCCR1_HSRD_TOCNT1 0x00000002U
AnnaBridge 126:abea610beb85 10044 #define DSI_TCCR1_HSRD_TOCNT2 0x00000004U
AnnaBridge 126:abea610beb85 10045 #define DSI_TCCR1_HSRD_TOCNT3 0x00000008U
AnnaBridge 126:abea610beb85 10046 #define DSI_TCCR1_HSRD_TOCNT4 0x00000010U
AnnaBridge 126:abea610beb85 10047 #define DSI_TCCR1_HSRD_TOCNT5 0x00000020U
AnnaBridge 126:abea610beb85 10048 #define DSI_TCCR1_HSRD_TOCNT6 0x00000040U
AnnaBridge 126:abea610beb85 10049 #define DSI_TCCR1_HSRD_TOCNT7 0x00000080U
AnnaBridge 126:abea610beb85 10050 #define DSI_TCCR1_HSRD_TOCNT8 0x00000100U
AnnaBridge 126:abea610beb85 10051 #define DSI_TCCR1_HSRD_TOCNT9 0x00000200U
AnnaBridge 126:abea610beb85 10052 #define DSI_TCCR1_HSRD_TOCNT10 0x00000400U
AnnaBridge 126:abea610beb85 10053 #define DSI_TCCR1_HSRD_TOCNT11 0x00000800U
AnnaBridge 126:abea610beb85 10054 #define DSI_TCCR1_HSRD_TOCNT12 0x00001000U
AnnaBridge 126:abea610beb85 10055 #define DSI_TCCR1_HSRD_TOCNT13 0x00002000U
AnnaBridge 126:abea610beb85 10056 #define DSI_TCCR1_HSRD_TOCNT14 0x00004000U
AnnaBridge 126:abea610beb85 10057 #define DSI_TCCR1_HSRD_TOCNT15 0x00008000U
AnnaBridge 126:abea610beb85 10058
AnnaBridge 126:abea610beb85 10059 /******************* Bit definition for DSI_TCCR2 register **************/
AnnaBridge 126:abea610beb85 10060 #define DSI_TCCR2_LPRD_TOCNT 0x0000FFFFU /*!< Low-Power Read Timeout Counter */
AnnaBridge 126:abea610beb85 10061 #define DSI_TCCR2_LPRD_TOCNT0 0x00000001U
AnnaBridge 126:abea610beb85 10062 #define DSI_TCCR2_LPRD_TOCNT1 0x00000002U
AnnaBridge 126:abea610beb85 10063 #define DSI_TCCR2_LPRD_TOCNT2 0x00000004U
AnnaBridge 126:abea610beb85 10064 #define DSI_TCCR2_LPRD_TOCNT3 0x00000008U
AnnaBridge 126:abea610beb85 10065 #define DSI_TCCR2_LPRD_TOCNT4 0x00000010U
AnnaBridge 126:abea610beb85 10066 #define DSI_TCCR2_LPRD_TOCNT5 0x00000020U
AnnaBridge 126:abea610beb85 10067 #define DSI_TCCR2_LPRD_TOCNT6 0x00000040U
AnnaBridge 126:abea610beb85 10068 #define DSI_TCCR2_LPRD_TOCNT7 0x00000080U
AnnaBridge 126:abea610beb85 10069 #define DSI_TCCR2_LPRD_TOCNT8 0x00000100U
AnnaBridge 126:abea610beb85 10070 #define DSI_TCCR2_LPRD_TOCNT9 0x00000200U
AnnaBridge 126:abea610beb85 10071 #define DSI_TCCR2_LPRD_TOCNT10 0x00000400U
AnnaBridge 126:abea610beb85 10072 #define DSI_TCCR2_LPRD_TOCNT11 0x00000800U
AnnaBridge 126:abea610beb85 10073 #define DSI_TCCR2_LPRD_TOCNT12 0x00001000U
AnnaBridge 126:abea610beb85 10074 #define DSI_TCCR2_LPRD_TOCNT13 0x00002000U
AnnaBridge 126:abea610beb85 10075 #define DSI_TCCR2_LPRD_TOCNT14 0x00004000U
AnnaBridge 126:abea610beb85 10076 #define DSI_TCCR2_LPRD_TOCNT15 0x00008000U
AnnaBridge 126:abea610beb85 10077
AnnaBridge 126:abea610beb85 10078 /******************* Bit definition for DSI_TCCR3 register **************/
AnnaBridge 126:abea610beb85 10079 #define DSI_TCCR3_HSWR_TOCNT 0x0000FFFFU /*!< High-Speed Write Timeout Counter */
AnnaBridge 126:abea610beb85 10080 #define DSI_TCCR3_HSWR_TOCNT0 0x00000001U
AnnaBridge 126:abea610beb85 10081 #define DSI_TCCR3_HSWR_TOCNT1 0x00000002U
AnnaBridge 126:abea610beb85 10082 #define DSI_TCCR3_HSWR_TOCNT2 0x00000004U
AnnaBridge 126:abea610beb85 10083 #define DSI_TCCR3_HSWR_TOCNT3 0x00000008U
AnnaBridge 126:abea610beb85 10084 #define DSI_TCCR3_HSWR_TOCNT4 0x00000010U
AnnaBridge 126:abea610beb85 10085 #define DSI_TCCR3_HSWR_TOCNT5 0x00000020U
AnnaBridge 126:abea610beb85 10086 #define DSI_TCCR3_HSWR_TOCNT6 0x00000040U
AnnaBridge 126:abea610beb85 10087 #define DSI_TCCR3_HSWR_TOCNT7 0x00000080U
AnnaBridge 126:abea610beb85 10088 #define DSI_TCCR3_HSWR_TOCNT8 0x00000100U
AnnaBridge 126:abea610beb85 10089 #define DSI_TCCR3_HSWR_TOCNT9 0x00000200U
AnnaBridge 126:abea610beb85 10090 #define DSI_TCCR3_HSWR_TOCNT10 0x00000400U
AnnaBridge 126:abea610beb85 10091 #define DSI_TCCR3_HSWR_TOCNT11 0x00000800U
AnnaBridge 126:abea610beb85 10092 #define DSI_TCCR3_HSWR_TOCNT12 0x00001000U
AnnaBridge 126:abea610beb85 10093 #define DSI_TCCR3_HSWR_TOCNT13 0x00002000U
AnnaBridge 126:abea610beb85 10094 #define DSI_TCCR3_HSWR_TOCNT14 0x00004000U
AnnaBridge 126:abea610beb85 10095 #define DSI_TCCR3_HSWR_TOCNT15 0x00008000U
AnnaBridge 126:abea610beb85 10096
AnnaBridge 126:abea610beb85 10097 #define DSI_TCCR3_PM 0x01000000U /*!< Presp Mode */
AnnaBridge 126:abea610beb85 10098
AnnaBridge 126:abea610beb85 10099 /******************* Bit definition for DSI_TCCR4 register **************/
AnnaBridge 126:abea610beb85 10100 #define DSI_TCCR4_LPWR_TOCNT 0x0000FFFFU /*!< Low-Power Write Timeout Counter */
AnnaBridge 126:abea610beb85 10101 #define DSI_TCCR4_LPWR_TOCNT0 0x00000001U
AnnaBridge 126:abea610beb85 10102 #define DSI_TCCR4_LPWR_TOCNT1 0x00000002U
AnnaBridge 126:abea610beb85 10103 #define DSI_TCCR4_LPWR_TOCNT2 0x00000004U
AnnaBridge 126:abea610beb85 10104 #define DSI_TCCR4_LPWR_TOCNT3 0x00000008U
AnnaBridge 126:abea610beb85 10105 #define DSI_TCCR4_LPWR_TOCNT4 0x00000010U
AnnaBridge 126:abea610beb85 10106 #define DSI_TCCR4_LPWR_TOCNT5 0x00000020U
AnnaBridge 126:abea610beb85 10107 #define DSI_TCCR4_LPWR_TOCNT6 0x00000040U
AnnaBridge 126:abea610beb85 10108 #define DSI_TCCR4_LPWR_TOCNT7 0x00000080U
AnnaBridge 126:abea610beb85 10109 #define DSI_TCCR4_LPWR_TOCNT8 0x00000100U
AnnaBridge 126:abea610beb85 10110 #define DSI_TCCR4_LPWR_TOCNT9 0x00000200U
AnnaBridge 126:abea610beb85 10111 #define DSI_TCCR4_LPWR_TOCNT10 0x00000400U
AnnaBridge 126:abea610beb85 10112 #define DSI_TCCR4_LPWR_TOCNT11 0x00000800U
AnnaBridge 126:abea610beb85 10113 #define DSI_TCCR4_LPWR_TOCNT12 0x00001000U
AnnaBridge 126:abea610beb85 10114 #define DSI_TCCR4_LPWR_TOCNT13 0x00002000U
AnnaBridge 126:abea610beb85 10115 #define DSI_TCCR4_LPWR_TOCNT14 0x00004000U
AnnaBridge 126:abea610beb85 10116 #define DSI_TCCR4_LPWR_TOCNT15 0x00008000U
AnnaBridge 126:abea610beb85 10117
AnnaBridge 126:abea610beb85 10118 /******************* Bit definition for DSI_TCCR5register **************/
AnnaBridge 126:abea610beb85 10119 #define DSI_TCCR5_BTA_TOCNT 0x0000FFFFU /*!< Bus-Turn-Around Timeout Counter */
AnnaBridge 126:abea610beb85 10120 #define DSI_TCCR5_BTA_TOCNT0 0x00000001U
AnnaBridge 126:abea610beb85 10121 #define DSI_TCCR5_BTA_TOCNT1 0x00000002U
AnnaBridge 126:abea610beb85 10122 #define DSI_TCCR5_BTA_TOCNT2 0x00000004U
AnnaBridge 126:abea610beb85 10123 #define DSI_TCCR5_BTA_TOCNT3 0x00000008U
AnnaBridge 126:abea610beb85 10124 #define DSI_TCCR5_BTA_TOCNT4 0x00000010U
AnnaBridge 126:abea610beb85 10125 #define DSI_TCCR5_BTA_TOCNT5 0x00000020U
AnnaBridge 126:abea610beb85 10126 #define DSI_TCCR5_BTA_TOCNT6 0x00000040U
AnnaBridge 126:abea610beb85 10127 #define DSI_TCCR5_BTA_TOCNT7 0x00000080U
AnnaBridge 126:abea610beb85 10128 #define DSI_TCCR5_BTA_TOCNT8 0x00000100U
AnnaBridge 126:abea610beb85 10129 #define DSI_TCCR5_BTA_TOCNT9 0x00000200U
AnnaBridge 126:abea610beb85 10130 #define DSI_TCCR5_BTA_TOCNT10 0x00000400U
AnnaBridge 126:abea610beb85 10131 #define DSI_TCCR5_BTA_TOCNT11 0x00000800U
AnnaBridge 126:abea610beb85 10132 #define DSI_TCCR5_BTA_TOCNT12 0x00001000U
AnnaBridge 126:abea610beb85 10133 #define DSI_TCCR5_BTA_TOCNT13 0x00002000U
AnnaBridge 126:abea610beb85 10134 #define DSI_TCCR5_BTA_TOCNT14 0x00004000U
AnnaBridge 126:abea610beb85 10135 #define DSI_TCCR5_BTA_TOCNT15 0x00008000U
AnnaBridge 126:abea610beb85 10136
AnnaBridge 126:abea610beb85 10137 /******************* Bit definition for DSI_TDCR register ***************/
AnnaBridge 126:abea610beb85 10138 #define DSI_TDCR_3DM 0x00000003U /*!< 3D Mode */
AnnaBridge 126:abea610beb85 10139 #define DSI_TDCR_3DM0 0x00000001U
AnnaBridge 126:abea610beb85 10140 #define DSI_TDCR_3DM1 0x00000002U
AnnaBridge 126:abea610beb85 10141
AnnaBridge 126:abea610beb85 10142 #define DSI_TDCR_3DF 0x0000000CU /*!< 3D Format */
AnnaBridge 126:abea610beb85 10143 #define DSI_TDCR_3DF0 0x00000004U
AnnaBridge 126:abea610beb85 10144 #define DSI_TDCR_3DF1 0x00000008U
AnnaBridge 126:abea610beb85 10145
AnnaBridge 126:abea610beb85 10146 #define DSI_TDCR_SVS 0x00000010U /*!< Second VSYNC */
AnnaBridge 126:abea610beb85 10147 #define DSI_TDCR_RF 0x00000020U /*!< Right First */
AnnaBridge 126:abea610beb85 10148 #define DSI_TDCR_S3DC 0x00010000U /*!< Send 3D Control */
AnnaBridge 126:abea610beb85 10149
AnnaBridge 126:abea610beb85 10150 /******************* Bit definition for DSI_CLCR register ***************/
AnnaBridge 126:abea610beb85 10151 #define DSI_CLCR_DPCC 0x00000001U /*!< D-PHY Clock Control */
AnnaBridge 126:abea610beb85 10152 #define DSI_CLCR_ACR 0x00000002U /*!< Automatic Clocklane Control */
AnnaBridge 126:abea610beb85 10153
AnnaBridge 126:abea610beb85 10154 /******************* Bit definition for DSI_CLTCR register **************/
AnnaBridge 126:abea610beb85 10155 #define DSI_CLTCR_LP2HS_TIME 0x000003FFU /*!< Low-Power to High-Speed Time */
AnnaBridge 126:abea610beb85 10156 #define DSI_CLTCR_LP2HS_TIME0 0x00000001U
AnnaBridge 126:abea610beb85 10157 #define DSI_CLTCR_LP2HS_TIME1 0x00000002U
AnnaBridge 126:abea610beb85 10158 #define DSI_CLTCR_LP2HS_TIME2 0x00000004U
AnnaBridge 126:abea610beb85 10159 #define DSI_CLTCR_LP2HS_TIME3 0x00000008U
AnnaBridge 126:abea610beb85 10160 #define DSI_CLTCR_LP2HS_TIME4 0x00000010U
AnnaBridge 126:abea610beb85 10161 #define DSI_CLTCR_LP2HS_TIME5 0x00000020U
AnnaBridge 126:abea610beb85 10162 #define DSI_CLTCR_LP2HS_TIME6 0x00000040U
AnnaBridge 126:abea610beb85 10163 #define DSI_CLTCR_LP2HS_TIME7 0x00000080U
AnnaBridge 126:abea610beb85 10164 #define DSI_CLTCR_LP2HS_TIME8 0x00000100U
AnnaBridge 126:abea610beb85 10165 #define DSI_CLTCR_LP2HS_TIME9 0x00000200U
AnnaBridge 126:abea610beb85 10166
AnnaBridge 126:abea610beb85 10167 #define DSI_CLTCR_HS2LP_TIME 0x03FF0000U /*!< High-Speed to Low-Power Time */
AnnaBridge 126:abea610beb85 10168 #define DSI_CLTCR_HS2LP_TIME0 0x00010000U
AnnaBridge 126:abea610beb85 10169 #define DSI_CLTCR_HS2LP_TIME1 0x00020000U
AnnaBridge 126:abea610beb85 10170 #define DSI_CLTCR_HS2LP_TIME2 0x00040000U
AnnaBridge 126:abea610beb85 10171 #define DSI_CLTCR_HS2LP_TIME3 0x00080000U
AnnaBridge 126:abea610beb85 10172 #define DSI_CLTCR_HS2LP_TIME4 0x00100000U
AnnaBridge 126:abea610beb85 10173 #define DSI_CLTCR_HS2LP_TIME5 0x00200000U
AnnaBridge 126:abea610beb85 10174 #define DSI_CLTCR_HS2LP_TIME6 0x00400000U
AnnaBridge 126:abea610beb85 10175 #define DSI_CLTCR_HS2LP_TIME7 0x00800000U
AnnaBridge 126:abea610beb85 10176 #define DSI_CLTCR_HS2LP_TIME8 0x01000000U
AnnaBridge 126:abea610beb85 10177 #define DSI_CLTCR_HS2LP_TIME9 0x02000000U
AnnaBridge 126:abea610beb85 10178
AnnaBridge 126:abea610beb85 10179 /******************* Bit definition for DSI_DLTCR register **************/
AnnaBridge 126:abea610beb85 10180 #define DSI_DLTCR_MRD_TIME 0x00007FFFU /*!< Maximum Read Time */
AnnaBridge 126:abea610beb85 10181 #define DSI_DLTCR_MRD_TIME0 0x00000001U
AnnaBridge 126:abea610beb85 10182 #define DSI_DLTCR_MRD_TIME1 0x00000002U
AnnaBridge 126:abea610beb85 10183 #define DSI_DLTCR_MRD_TIME2 0x00000004U
AnnaBridge 126:abea610beb85 10184 #define DSI_DLTCR_MRD_TIME3 0x00000008U
AnnaBridge 126:abea610beb85 10185 #define DSI_DLTCR_MRD_TIME4 0x00000010U
AnnaBridge 126:abea610beb85 10186 #define DSI_DLTCR_MRD_TIME5 0x00000020U
AnnaBridge 126:abea610beb85 10187 #define DSI_DLTCR_MRD_TIME6 0x00000040U
AnnaBridge 126:abea610beb85 10188 #define DSI_DLTCR_MRD_TIME7 0x00000080U
AnnaBridge 126:abea610beb85 10189 #define DSI_DLTCR_MRD_TIME8 0x00000100U
AnnaBridge 126:abea610beb85 10190 #define DSI_DLTCR_MRD_TIME9 0x00000200U
AnnaBridge 126:abea610beb85 10191 #define DSI_DLTCR_MRD_TIME10 0x00000400U
AnnaBridge 126:abea610beb85 10192 #define DSI_DLTCR_MRD_TIME11 0x00000800U
AnnaBridge 126:abea610beb85 10193 #define DSI_DLTCR_MRD_TIME12 0x00001000U
AnnaBridge 126:abea610beb85 10194 #define DSI_DLTCR_MRD_TIME13 0x00002000U
AnnaBridge 126:abea610beb85 10195 #define DSI_DLTCR_MRD_TIME14 0x00004000U
AnnaBridge 126:abea610beb85 10196
AnnaBridge 126:abea610beb85 10197 #define DSI_DLTCR_LP2HS_TIME 0x00FF0000U /*!< Low-Power To High-Speed Time */
AnnaBridge 126:abea610beb85 10198 #define DSI_DLTCR_LP2HS_TIME0 0x00010000U
AnnaBridge 126:abea610beb85 10199 #define DSI_DLTCR_LP2HS_TIME1 0x00020000U
AnnaBridge 126:abea610beb85 10200 #define DSI_DLTCR_LP2HS_TIME2 0x00040000U
AnnaBridge 126:abea610beb85 10201 #define DSI_DLTCR_LP2HS_TIME3 0x00080000U
AnnaBridge 126:abea610beb85 10202 #define DSI_DLTCR_LP2HS_TIME4 0x00100000U
AnnaBridge 126:abea610beb85 10203 #define DSI_DLTCR_LP2HS_TIME5 0x00200000U
AnnaBridge 126:abea610beb85 10204 #define DSI_DLTCR_LP2HS_TIME6 0x00400000U
AnnaBridge 126:abea610beb85 10205 #define DSI_DLTCR_LP2HS_TIME7 0x00800000U
AnnaBridge 126:abea610beb85 10206
AnnaBridge 126:abea610beb85 10207 #define DSI_DLTCR_HS2LP_TIME 0xFF000000U /*!< High-Speed To Low-Power Time */
AnnaBridge 126:abea610beb85 10208 #define DSI_DLTCR_HS2LP_TIME0 0x01000000U
AnnaBridge 126:abea610beb85 10209 #define DSI_DLTCR_HS2LP_TIME1 0x02000000U
AnnaBridge 126:abea610beb85 10210 #define DSI_DLTCR_HS2LP_TIME2 0x04000000U
AnnaBridge 126:abea610beb85 10211 #define DSI_DLTCR_HS2LP_TIME3 0x08000000U
AnnaBridge 126:abea610beb85 10212 #define DSI_DLTCR_HS2LP_TIME4 0x10000000U
AnnaBridge 126:abea610beb85 10213 #define DSI_DLTCR_HS2LP_TIME5 0x20000000U
AnnaBridge 126:abea610beb85 10214 #define DSI_DLTCR_HS2LP_TIME6 0x40000000U
AnnaBridge 126:abea610beb85 10215 #define DSI_DLTCR_HS2LP_TIME7 0x80000000U
AnnaBridge 126:abea610beb85 10216
AnnaBridge 126:abea610beb85 10217 /******************* Bit definition for DSI_PCTLRregister **************/
AnnaBridge 126:abea610beb85 10218 #define DSI_PCTLR_DEN 0x00000002U /*!< Digital Enable */
AnnaBridge 126:abea610beb85 10219 #define DSI_PCTLR_CKE 0x00000004U /*!< Clock Enable */
AnnaBridge 126:abea610beb85 10220
AnnaBridge 126:abea610beb85 10221 /******************* Bit definition for DSI_PCONFR register *************/
AnnaBridge 126:abea610beb85 10222 #define DSI_PCONFR_NL 0x00000003U /*!< Number of Lanes */
AnnaBridge 126:abea610beb85 10223 #define DSI_PCONFR_NL0 0x00000001U
AnnaBridge 126:abea610beb85 10224 #define DSI_PCONFR_NL1 0x00000002U
AnnaBridge 126:abea610beb85 10225
AnnaBridge 126:abea610beb85 10226 #define DSI_PCONFR_SW_TIME 0x0000FF00U /*!< Stop Wait Time */
AnnaBridge 126:abea610beb85 10227 #define DSI_PCONFR_SW_TIME0 0x00000100U
AnnaBridge 126:abea610beb85 10228 #define DSI_PCONFR_SW_TIME1 0x00000200U
AnnaBridge 126:abea610beb85 10229 #define DSI_PCONFR_SW_TIME2 0x00000400U
AnnaBridge 126:abea610beb85 10230 #define DSI_PCONFR_SW_TIME3 0x00000800U
AnnaBridge 126:abea610beb85 10231 #define DSI_PCONFR_SW_TIME4 0x00001000U
AnnaBridge 126:abea610beb85 10232 #define DSI_PCONFR_SW_TIME5 0x00002000U
AnnaBridge 126:abea610beb85 10233 #define DSI_PCONFR_SW_TIME6 0x00004000U
AnnaBridge 126:abea610beb85 10234 #define DSI_PCONFR_SW_TIME7 0x00008000U
AnnaBridge 126:abea610beb85 10235
AnnaBridge 126:abea610beb85 10236 /******************* Bit definition for DSI_PUCR register ***************/
AnnaBridge 126:abea610beb85 10237 #define DSI_PUCR_URCL 0x00000001U /*!< ULPS Request on Clock Lane */
AnnaBridge 126:abea610beb85 10238 #define DSI_PUCR_UECL 0x00000002U /*!< ULPS Exit on Clock Lane */
AnnaBridge 126:abea610beb85 10239 #define DSI_PUCR_URDL 0x00000004U /*!< ULPS Request on Data Lane */
AnnaBridge 126:abea610beb85 10240 #define DSI_PUCR_UEDL 0x00000008U /*!< ULPS Exit on Data Lane */
AnnaBridge 126:abea610beb85 10241
AnnaBridge 126:abea610beb85 10242 /******************* Bit definition for DSI_PTTCRregister **************/
AnnaBridge 126:abea610beb85 10243 #define DSI_PTTCR_TX_TRIG 0x0000000FU /*!< Transmission Trigger */
AnnaBridge 126:abea610beb85 10244 #define DSI_PTTCR_TX_TRIG0 0x00000001U
AnnaBridge 126:abea610beb85 10245 #define DSI_PTTCR_TX_TRIG1 0x00000002U
AnnaBridge 126:abea610beb85 10246 #define DSI_PTTCR_TX_TRIG2 0x00000004U
AnnaBridge 126:abea610beb85 10247 #define DSI_PTTCR_TX_TRIG3 0x00000008U
AnnaBridge 126:abea610beb85 10248
AnnaBridge 126:abea610beb85 10249 /******************* Bit definition for DSI_PSR register ****************/
AnnaBridge 126:abea610beb85 10250 #define DSI_PSR_PD 0x00000002U /*!< PHY Direction */
AnnaBridge 126:abea610beb85 10251 #define DSI_PSR_PSSC 0x00000004U /*!< PHY Stop State Clock lane */
AnnaBridge 126:abea610beb85 10252 #define DSI_PSR_UANC 0x00000008U /*!< ULPS Active Not Clock lane */
AnnaBridge 126:abea610beb85 10253 #define DSI_PSR_PSS0 0x00000010U /*!< PHY Stop State lane 0 */
AnnaBridge 126:abea610beb85 10254 #define DSI_PSR_UAN0 0x00000020U /*!< ULPS Active Not lane 0 */
AnnaBridge 126:abea610beb85 10255 #define DSI_PSR_RUE0 0x00000040U /*!< RX ULPS Escape lane 0 */
AnnaBridge 126:abea610beb85 10256 #define DSI_PSR_PSS1 0x00000080U /*!< PHY Stop State lane 1 */
AnnaBridge 126:abea610beb85 10257 #define DSI_PSR_UAN1 0x00000100U /*!< ULPS Active Not lane 1 */
AnnaBridge 126:abea610beb85 10258
AnnaBridge 126:abea610beb85 10259 /******************* Bit definition for DSI_ISR0 register ***************/
AnnaBridge 126:abea610beb85 10260 #define DSI_ISR0_AE0 0x00000001U /*!< Acknowledge Error 0 */
AnnaBridge 126:abea610beb85 10261 #define DSI_ISR0_AE1 0x00000002U /*!< Acknowledge Error 1 */
AnnaBridge 126:abea610beb85 10262 #define DSI_ISR0_AE2 0x00000004U /*!< Acknowledge Error 2 */
AnnaBridge 126:abea610beb85 10263 #define DSI_ISR0_AE3 0x00000008U /*!< Acknowledge Error 3 */
AnnaBridge 126:abea610beb85 10264 #define DSI_ISR0_AE4 0x00000010U /*!< Acknowledge Error 4 */
AnnaBridge 126:abea610beb85 10265 #define DSI_ISR0_AE5 0x00000020U /*!< Acknowledge Error 5 */
AnnaBridge 126:abea610beb85 10266 #define DSI_ISR0_AE6 0x00000040U /*!< Acknowledge Error 6 */
AnnaBridge 126:abea610beb85 10267 #define DSI_ISR0_AE7 0x00000080U /*!< Acknowledge Error 7 */
AnnaBridge 126:abea610beb85 10268 #define DSI_ISR0_AE8 0x00000100U /*!< Acknowledge Error 8 */
AnnaBridge 126:abea610beb85 10269 #define DSI_ISR0_AE9 0x00000200U /*!< Acknowledge Error 9 */
AnnaBridge 126:abea610beb85 10270 #define DSI_ISR0_AE10 0x00000400U /*!< Acknowledge Error 10 */
AnnaBridge 126:abea610beb85 10271 #define DSI_ISR0_AE11 0x00000800U /*!< Acknowledge Error 11 */
AnnaBridge 126:abea610beb85 10272 #define DSI_ISR0_AE12 0x00001000U /*!< Acknowledge Error 12 */
AnnaBridge 126:abea610beb85 10273 #define DSI_ISR0_AE13 0x00002000U /*!< Acknowledge Error 13 */
AnnaBridge 126:abea610beb85 10274 #define DSI_ISR0_AE14 0x00004000U /*!< Acknowledge Error 14 */
AnnaBridge 126:abea610beb85 10275 #define DSI_ISR0_AE15 0x00008000U /*!< Acknowledge Error 15 */
AnnaBridge 126:abea610beb85 10276 #define DSI_ISR0_PE0 0x00010000U /*!< PHY Error 0 */
AnnaBridge 126:abea610beb85 10277 #define DSI_ISR0_PE1 0x00020000U /*!< PHY Error 1 */
AnnaBridge 126:abea610beb85 10278 #define DSI_ISR0_PE2 0x00040000U /*!< PHY Error 2 */
AnnaBridge 126:abea610beb85 10279 #define DSI_ISR0_PE3 0x00080000U /*!< PHY Error 3 */
AnnaBridge 126:abea610beb85 10280 #define DSI_ISR0_PE4 0x00100000U /*!< PHY Error 4 */
AnnaBridge 126:abea610beb85 10281
AnnaBridge 126:abea610beb85 10282 /******************* Bit definition for DSI_ISR1 register ***************/
AnnaBridge 126:abea610beb85 10283 #define DSI_ISR1_TOHSTX 0x00000001U /*!< Timeout High-Speed Transmission */
AnnaBridge 126:abea610beb85 10284 #define DSI_ISR1_TOLPRX 0x00000002U /*!< Timeout Low-Power Reception */
AnnaBridge 126:abea610beb85 10285 #define DSI_ISR1_ECCSE 0x00000004U /*!< ECC Single-bit Error */
AnnaBridge 126:abea610beb85 10286 #define DSI_ISR1_ECCME 0x00000008U /*!< ECC Multi-bit Error */
AnnaBridge 126:abea610beb85 10287 #define DSI_ISR1_CRCE 0x00000010U /*!< CRC Error */
AnnaBridge 126:abea610beb85 10288 #define DSI_ISR1_PSE 0x00000020U /*!< Packet Size Error */
AnnaBridge 126:abea610beb85 10289 #define DSI_ISR1_EOTPE 0x00000040U /*!< EoTp Error */
AnnaBridge 126:abea610beb85 10290 #define DSI_ISR1_LPWRE 0x00000080U /*!< LTDC Payload Write Error */
AnnaBridge 126:abea610beb85 10291 #define DSI_ISR1_GCWRE 0x00000100U /*!< Generic Command Write Error */
AnnaBridge 126:abea610beb85 10292 #define DSI_ISR1_GPWRE 0x00000200U /*!< Generic Payload Write Error */
AnnaBridge 126:abea610beb85 10293 #define DSI_ISR1_GPTXE 0x00000400U /*!< Generic Payload Transmit Error */
AnnaBridge 126:abea610beb85 10294 #define DSI_ISR1_GPRDE 0x00000800U /*!< Generic Payload Read Error */
AnnaBridge 126:abea610beb85 10295 #define DSI_ISR1_GPRXE 0x00001000U /*!< Generic Payload Receive Error */
AnnaBridge 126:abea610beb85 10296
AnnaBridge 126:abea610beb85 10297 /******************* Bit definition for DSI_IER0 register ***************/
AnnaBridge 126:abea610beb85 10298 #define DSI_IER0_AE0IE 0x00000001U /*!< Acknowledge Error 0 Interrupt Enable */
AnnaBridge 126:abea610beb85 10299 #define DSI_IER0_AE1IE 0x00000002U /*!< Acknowledge Error 1 Interrupt Enable */
AnnaBridge 126:abea610beb85 10300 #define DSI_IER0_AE2IE 0x00000004U /*!< Acknowledge Error 2 Interrupt Enable */
AnnaBridge 126:abea610beb85 10301 #define DSI_IER0_AE3IE 0x00000008U /*!< Acknowledge Error 3 Interrupt Enable */
AnnaBridge 126:abea610beb85 10302 #define DSI_IER0_AE4IE 0x00000010U /*!< Acknowledge Error 4 Interrupt Enable */
AnnaBridge 126:abea610beb85 10303 #define DSI_IER0_AE5IE 0x00000020U /*!< Acknowledge Error 5 Interrupt Enable */
AnnaBridge 126:abea610beb85 10304 #define DSI_IER0_AE6IE 0x00000040U /*!< Acknowledge Error 6 Interrupt Enable */
AnnaBridge 126:abea610beb85 10305 #define DSI_IER0_AE7IE 0x00000080U /*!< Acknowledge Error 7 Interrupt Enable */
AnnaBridge 126:abea610beb85 10306 #define DSI_IER0_AE8IE 0x00000100U /*!< Acknowledge Error 8 Interrupt Enable */
AnnaBridge 126:abea610beb85 10307 #define DSI_IER0_AE9IE 0x00000200U /*!< Acknowledge Error 9 Interrupt Enable */
AnnaBridge 126:abea610beb85 10308 #define DSI_IER0_AE10IE 0x00000400U /*!< Acknowledge Error 10 Interrupt Enable */
AnnaBridge 126:abea610beb85 10309 #define DSI_IER0_AE11IE 0x00000800U /*!< Acknowledge Error 11 Interrupt Enable */
AnnaBridge 126:abea610beb85 10310 #define DSI_IER0_AE12IE 0x00001000U /*!< Acknowledge Error 12 Interrupt Enable */
AnnaBridge 126:abea610beb85 10311 #define DSI_IER0_AE13IE 0x00002000U /*!< Acknowledge Error 13 Interrupt Enable */
AnnaBridge 126:abea610beb85 10312 #define DSI_IER0_AE14IE 0x00004000U /*!< Acknowledge Error 14 Interrupt Enable */
AnnaBridge 126:abea610beb85 10313 #define DSI_IER0_AE15IE 0x00008000U /*!< Acknowledge Error 15 Interrupt Enable */
AnnaBridge 126:abea610beb85 10314 #define DSI_IER0_PE0IE 0x00010000U /*!< PHY Error 0 Interrupt Enable */
AnnaBridge 126:abea610beb85 10315 #define DSI_IER0_PE1IE 0x00020000U /*!< PHY Error 1 Interrupt Enable */
AnnaBridge 126:abea610beb85 10316 #define DSI_IER0_PE2IE 0x00040000U /*!< PHY Error 2 Interrupt Enable */
AnnaBridge 126:abea610beb85 10317 #define DSI_IER0_PE3IE 0x00080000U /*!< PHY Error 3 Interrupt Enable */
AnnaBridge 126:abea610beb85 10318 #define DSI_IER0_PE4IE 0x00100000U /*!< PHY Error 4 Interrupt Enable */
AnnaBridge 126:abea610beb85 10319
AnnaBridge 126:abea610beb85 10320 /******************* Bit definition for DSI_IER1 register ***************/
AnnaBridge 126:abea610beb85 10321 #define DSI_IER1_TOHSTXIE 0x00000001U /*!< Timeout High-Speed Transmission Interrupt Enable */
AnnaBridge 126:abea610beb85 10322 #define DSI_IER1_TOLPRXIE 0x00000002U /*!< Timeout Low-Power Reception Interrupt Enable */
AnnaBridge 126:abea610beb85 10323 #define DSI_IER1_ECCSEIE 0x00000004U /*!< ECC Single-bit Error Interrupt Enable */
AnnaBridge 126:abea610beb85 10324 #define DSI_IER1_ECCMEIE 0x00000008U /*!< ECC Multi-bit Error Interrupt Enable */
AnnaBridge 126:abea610beb85 10325 #define DSI_IER1_CRCEIE 0x00000010U /*!< CRC Error Interrupt Enable */
AnnaBridge 126:abea610beb85 10326 #define DSI_IER1_PSEIE 0x00000020U /*!< Packet Size Error Interrupt Enable */
AnnaBridge 126:abea610beb85 10327 #define DSI_IER1_EOTPEIE 0x00000040U /*!< EoTp Error Interrupt Enable */
AnnaBridge 126:abea610beb85 10328 #define DSI_IER1_LPWREIE 0x00000080U /*!< LTDC Payload Write Error Interrupt Enable */
AnnaBridge 126:abea610beb85 10329 #define DSI_IER1_GCWREIE 0x00000100U /*!< Generic Command Write Error Interrupt Enable */
AnnaBridge 126:abea610beb85 10330 #define DSI_IER1_GPWREIE 0x00000200U /*!< Generic Payload Write Error Interrupt Enable */
AnnaBridge 126:abea610beb85 10331 #define DSI_IER1_GPTXEIE 0x00000400U /*!< Generic Payload Transmit Error Interrupt Enable */
AnnaBridge 126:abea610beb85 10332 #define DSI_IER1_GPRDEIE 0x00000800U /*!< Generic Payload Read Error Interrupt Enable */
AnnaBridge 126:abea610beb85 10333 #define DSI_IER1_GPRXEIE 0x00001000U /*!< Generic Payload Receive Error Interrupt Enable */
AnnaBridge 126:abea610beb85 10334
AnnaBridge 126:abea610beb85 10335 /******************* Bit definition for DSI_FIR0 register ***************/
AnnaBridge 126:abea610beb85 10336 #define DSI_FIR0_FAE0 0x00000001U /*!< Force Acknowledge Error 0 */
AnnaBridge 126:abea610beb85 10337 #define DSI_FIR0_FAE1 0x00000002U /*!< Force Acknowledge Error 1 */
AnnaBridge 126:abea610beb85 10338 #define DSI_FIR0_FAE2 0x00000004U /*!< Force Acknowledge Error 2 */
AnnaBridge 126:abea610beb85 10339 #define DSI_FIR0_FAE3 0x00000008U /*!< Force Acknowledge Error 3 */
AnnaBridge 126:abea610beb85 10340 #define DSI_FIR0_FAE4 0x00000010U /*!< Force Acknowledge Error 4 */
AnnaBridge 126:abea610beb85 10341 #define DSI_FIR0_FAE5 0x00000020U /*!< Force Acknowledge Error 5 */
AnnaBridge 126:abea610beb85 10342 #define DSI_FIR0_FAE6 0x00000040U /*!< Force Acknowledge Error 6 */
AnnaBridge 126:abea610beb85 10343 #define DSI_FIR0_FAE7 0x00000080U /*!< Force Acknowledge Error 7 */
AnnaBridge 126:abea610beb85 10344 #define DSI_FIR0_FAE8 0x00000100U /*!< Force Acknowledge Error 8 */
AnnaBridge 126:abea610beb85 10345 #define DSI_FIR0_FAE9 0x00000200U /*!< Force Acknowledge Error 9 */
AnnaBridge 126:abea610beb85 10346 #define DSI_FIR0_FAE10 0x00000400U /*!< Force Acknowledge Error 10 */
AnnaBridge 126:abea610beb85 10347 #define DSI_FIR0_FAE11 0x00000800U /*!< Force Acknowledge Error 11 */
AnnaBridge 126:abea610beb85 10348 #define DSI_FIR0_FAE12 0x00001000U /*!< Force Acknowledge Error 12 */
AnnaBridge 126:abea610beb85 10349 #define DSI_FIR0_FAE13 0x00002000U /*!< Force Acknowledge Error 13 */
AnnaBridge 126:abea610beb85 10350 #define DSI_FIR0_FAE14 0x00004000U /*!< Force Acknowledge Error 14 */
AnnaBridge 126:abea610beb85 10351 #define DSI_FIR0_FAE15 0x00008000U /*!< Force Acknowledge Error 15 */
AnnaBridge 126:abea610beb85 10352 #define DSI_FIR0_FPE0 0x00010000U /*!< Force PHY Error 0 */
AnnaBridge 126:abea610beb85 10353 #define DSI_FIR0_FPE1 0x00020000U /*!< Force PHY Error 1 */
AnnaBridge 126:abea610beb85 10354 #define DSI_FIR0_FPE2 0x00040000U /*!< Force PHY Error 2 */
AnnaBridge 126:abea610beb85 10355 #define DSI_FIR0_FPE3 0x00080000U /*!< Force PHY Error 3 */
AnnaBridge 126:abea610beb85 10356 #define DSI_FIR0_FPE4 0x00100000U /*!< Force PHY Error 4 */
AnnaBridge 126:abea610beb85 10357
AnnaBridge 126:abea610beb85 10358 /******************* Bit definition for DSI_FIR1 register ***************/
AnnaBridge 126:abea610beb85 10359 #define DSI_FIR1_FTOHSTX 0x00000001U /*!< Force Timeout High-Speed Transmission */
AnnaBridge 126:abea610beb85 10360 #define DSI_FIR1_FTOLPRX 0x00000002U /*!< Force Timeout Low-Power Reception */
AnnaBridge 126:abea610beb85 10361 #define DSI_FIR1_FECCSE 0x00000004U /*!< Force ECC Single-bit Error */
AnnaBridge 126:abea610beb85 10362 #define DSI_FIR1_FECCME 0x00000008U /*!< Force ECC Multi-bit Error */
AnnaBridge 126:abea610beb85 10363 #define DSI_FIR1_FCRCE 0x00000010U /*!< Force CRC Error */
AnnaBridge 126:abea610beb85 10364 #define DSI_FIR1_FPSE 0x00000020U /*!< Force Packet Size Error */
AnnaBridge 126:abea610beb85 10365 #define DSI_FIR1_FEOTPE 0x00000040U /*!< Force EoTp Error */
AnnaBridge 126:abea610beb85 10366 #define DSI_FIR1_FLPWRE 0x00000080U /*!< Force LTDC Payload Write Error */
AnnaBridge 126:abea610beb85 10367 #define DSI_FIR1_FGCWRE 0x00000100U /*!< Force Generic Command Write Error */
AnnaBridge 126:abea610beb85 10368 #define DSI_FIR1_FGPWRE 0x00000200U /*!< Force Generic Payload Write Error */
AnnaBridge 126:abea610beb85 10369 #define DSI_FIR1_FGPTXE 0x00000400U /*!< Force Generic Payload Transmit Error */
AnnaBridge 126:abea610beb85 10370 #define DSI_FIR1_FGPRDE 0x00000800U /*!< Force Generic Payload Read Error */
AnnaBridge 126:abea610beb85 10371 #define DSI_FIR1_FGPRXE 0x00001000U /*!< Force Generic Payload Receive Error */
AnnaBridge 126:abea610beb85 10372
AnnaBridge 126:abea610beb85 10373 /******************* Bit definition for DSI_VSCR register ***************/
AnnaBridge 126:abea610beb85 10374 #define DSI_VSCR_EN 0x00000001U /*!< Enable */
AnnaBridge 126:abea610beb85 10375 #define DSI_VSCR_UR 0x00000100U /*!< Update Register */
AnnaBridge 126:abea610beb85 10376
AnnaBridge 126:abea610beb85 10377 /******************* Bit definition for DSI_LCVCIDR register ************/
AnnaBridge 126:abea610beb85 10378 #define DSI_LCVCIDR_VCID 0x00000003U /*!< Virtual Channel ID */
AnnaBridge 126:abea610beb85 10379 #define DSI_LCVCIDR_VCID0 0x00000001U
AnnaBridge 126:abea610beb85 10380 #define DSI_LCVCIDR_VCID1 0x00000002U
AnnaBridge 126:abea610beb85 10381
AnnaBridge 126:abea610beb85 10382 /******************* Bit definition for DSI_LCCCR register **************/
AnnaBridge 126:abea610beb85 10383 #define DSI_LCCCR_COLC 0x0000000FU /*!< Color Coding */
AnnaBridge 126:abea610beb85 10384 #define DSI_LCCCR_COLC0 0x00000001U
AnnaBridge 126:abea610beb85 10385 #define DSI_LCCCR_COLC1 0x00000002U
AnnaBridge 126:abea610beb85 10386 #define DSI_LCCCR_COLC2 0x00000004U
AnnaBridge 126:abea610beb85 10387 #define DSI_LCCCR_COLC3 0x00000008U
AnnaBridge 126:abea610beb85 10388
AnnaBridge 126:abea610beb85 10389 #define DSI_LCCCR_LPE 0x00000100U /*!< Loosely Packed Enable */
AnnaBridge 126:abea610beb85 10390
AnnaBridge 126:abea610beb85 10391 /******************* Bit definition for DSI_LPMCCR register *************/
AnnaBridge 126:abea610beb85 10392 #define DSI_LPMCCR_VLPSIZE 0x000000FFU /*!< VACT Largest Packet Size */
AnnaBridge 126:abea610beb85 10393 #define DSI_LPMCCR_VLPSIZE0 0x00000001U
AnnaBridge 126:abea610beb85 10394 #define DSI_LPMCCR_VLPSIZE1 0x00000002U
AnnaBridge 126:abea610beb85 10395 #define DSI_LPMCCR_VLPSIZE2 0x00000004U
AnnaBridge 126:abea610beb85 10396 #define DSI_LPMCCR_VLPSIZE3 0x00000008U
AnnaBridge 126:abea610beb85 10397 #define DSI_LPMCCR_VLPSIZE4 0x00000010U
AnnaBridge 126:abea610beb85 10398 #define DSI_LPMCCR_VLPSIZE5 0x00000020U
AnnaBridge 126:abea610beb85 10399 #define DSI_LPMCCR_VLPSIZE6 0x00000040U
AnnaBridge 126:abea610beb85 10400 #define DSI_LPMCCR_VLPSIZE7 0x00000080U
AnnaBridge 126:abea610beb85 10401
AnnaBridge 126:abea610beb85 10402 #define DSI_LPMCCR_LPSIZE 0x00FF0000U /*!< Largest Packet Size */
AnnaBridge 126:abea610beb85 10403 #define DSI_LPMCCR_LPSIZE0 0x00010000U
AnnaBridge 126:abea610beb85 10404 #define DSI_LPMCCR_LPSIZE1 0x00020000U
AnnaBridge 126:abea610beb85 10405 #define DSI_LPMCCR_LPSIZE2 0x00040000U
AnnaBridge 126:abea610beb85 10406 #define DSI_LPMCCR_LPSIZE3 0x00080000U
AnnaBridge 126:abea610beb85 10407 #define DSI_LPMCCR_LPSIZE4 0x00100000U
AnnaBridge 126:abea610beb85 10408 #define DSI_LPMCCR_LPSIZE5 0x00200000U
AnnaBridge 126:abea610beb85 10409 #define DSI_LPMCCR_LPSIZE6 0x00400000U
AnnaBridge 126:abea610beb85 10410 #define DSI_LPMCCR_LPSIZE7 0x00800000U
AnnaBridge 126:abea610beb85 10411
AnnaBridge 126:abea610beb85 10412 /******************* Bit definition for DSI_VMCCR register **************/
AnnaBridge 126:abea610beb85 10413 #define DSI_VMCCR_VMT 0x00000003U /*!< Video Mode Type */
AnnaBridge 126:abea610beb85 10414 #define DSI_VMCCR_VMT0 0x00000001U
AnnaBridge 126:abea610beb85 10415 #define DSI_VMCCR_VMT1 0x00000002U
AnnaBridge 126:abea610beb85 10416
AnnaBridge 126:abea610beb85 10417 #define DSI_VMCCR_LPVSAE 0x00000100U /*!< Low-power Vertical Sync time Enable */
AnnaBridge 126:abea610beb85 10418 #define DSI_VMCCR_LPVBPE 0x00000200U /*!< Low-power Vertical Back-porch Enable */
AnnaBridge 126:abea610beb85 10419 #define DSI_VMCCR_LPVFPE 0x00000400U /*!< Low-power Vertical Front-porch Enable */
AnnaBridge 126:abea610beb85 10420 #define DSI_VMCCR_LPVAE 0x00000800U /*!< Low-power Vertical Active Enable */
AnnaBridge 126:abea610beb85 10421 #define DSI_VMCCR_LPHBPE 0x00001000U /*!< Low-power Horizontal Back-porch Enable */
AnnaBridge 126:abea610beb85 10422 #define DSI_VMCCR_LPHFE 0x00002000U /*!< Low-power Horizontal Front-porch Enable */
AnnaBridge 126:abea610beb85 10423 #define DSI_VMCCR_FBTAAE 0x00004000U /*!< Frame BTA Acknowledge Enable */
AnnaBridge 126:abea610beb85 10424 #define DSI_VMCCR_LPCE 0x00008000U /*!< Low-power Command Enable */
AnnaBridge 126:abea610beb85 10425
AnnaBridge 126:abea610beb85 10426 /******************* Bit definition for DSI_VPCCR register **************/
AnnaBridge 126:abea610beb85 10427 #define DSI_VPCCR_VPSIZE 0x00003FFFU /*!< Video Packet Size */
AnnaBridge 126:abea610beb85 10428 #define DSI_VPCCR_VPSIZE0 0x00000001U
AnnaBridge 126:abea610beb85 10429 #define DSI_VPCCR_VPSIZE1 0x00000002U
AnnaBridge 126:abea610beb85 10430 #define DSI_VPCCR_VPSIZE2 0x00000004U
AnnaBridge 126:abea610beb85 10431 #define DSI_VPCCR_VPSIZE3 0x00000008U
AnnaBridge 126:abea610beb85 10432 #define DSI_VPCCR_VPSIZE4 0x00000010U
AnnaBridge 126:abea610beb85 10433 #define DSI_VPCCR_VPSIZE5 0x00000020U
AnnaBridge 126:abea610beb85 10434 #define DSI_VPCCR_VPSIZE6 0x00000040U
AnnaBridge 126:abea610beb85 10435 #define DSI_VPCCR_VPSIZE7 0x00000080U
AnnaBridge 126:abea610beb85 10436 #define DSI_VPCCR_VPSIZE8 0x00000100U
AnnaBridge 126:abea610beb85 10437 #define DSI_VPCCR_VPSIZE9 0x00000200U
AnnaBridge 126:abea610beb85 10438 #define DSI_VPCCR_VPSIZE10 0x00000400U
AnnaBridge 126:abea610beb85 10439 #define DSI_VPCCR_VPSIZE11 0x00000800U
AnnaBridge 126:abea610beb85 10440 #define DSI_VPCCR_VPSIZE12 0x00001000U
AnnaBridge 126:abea610beb85 10441 #define DSI_VPCCR_VPSIZE13 0x00002000U
AnnaBridge 126:abea610beb85 10442
AnnaBridge 126:abea610beb85 10443 /******************* Bit definition for DSI_VCCCR register **************/
AnnaBridge 126:abea610beb85 10444 #define DSI_VCCCR_NUMC 0x00001FFFU /*!< Number of Chunks */
AnnaBridge 126:abea610beb85 10445 #define DSI_VCCCR_NUMC0 0x00000001U
AnnaBridge 126:abea610beb85 10446 #define DSI_VCCCR_NUMC1 0x00000002U
AnnaBridge 126:abea610beb85 10447 #define DSI_VCCCR_NUMC2 0x00000004U
AnnaBridge 126:abea610beb85 10448 #define DSI_VCCCR_NUMC3 0x00000008U
AnnaBridge 126:abea610beb85 10449 #define DSI_VCCCR_NUMC4 0x00000010U
AnnaBridge 126:abea610beb85 10450 #define DSI_VCCCR_NUMC5 0x00000020U
AnnaBridge 126:abea610beb85 10451 #define DSI_VCCCR_NUMC6 0x00000040U
AnnaBridge 126:abea610beb85 10452 #define DSI_VCCCR_NUMC7 0x00000080U
AnnaBridge 126:abea610beb85 10453 #define DSI_VCCCR_NUMC8 0x00000100U
AnnaBridge 126:abea610beb85 10454 #define DSI_VCCCR_NUMC9 0x00000200U
AnnaBridge 126:abea610beb85 10455 #define DSI_VCCCR_NUMC10 0x00000400U
AnnaBridge 126:abea610beb85 10456 #define DSI_VCCCR_NUMC11 0x00000800U
AnnaBridge 126:abea610beb85 10457 #define DSI_VCCCR_NUMC12 0x00001000U
AnnaBridge 126:abea610beb85 10458
AnnaBridge 126:abea610beb85 10459 /******************* Bit definition for DSI_VNPCCR register *************/
AnnaBridge 126:abea610beb85 10460 #define DSI_VNPCCR_NPSIZE 0x00001FFFU /*!< Number of Chunks */
AnnaBridge 126:abea610beb85 10461 #define DSI_VNPCCR_NPSIZE0 0x00000001U
AnnaBridge 126:abea610beb85 10462 #define DSI_VNPCCR_NPSIZE1 0x00000002U
AnnaBridge 126:abea610beb85 10463 #define DSI_VNPCCR_NPSIZE2 0x00000004U
AnnaBridge 126:abea610beb85 10464 #define DSI_VNPCCR_NPSIZE3 0x00000008U
AnnaBridge 126:abea610beb85 10465 #define DSI_VNPCCR_NPSIZE4 0x00000010U
AnnaBridge 126:abea610beb85 10466 #define DSI_VNPCCR_NPSIZE5 0x00000020U
AnnaBridge 126:abea610beb85 10467 #define DSI_VNPCCR_NPSIZE6 0x00000040U
AnnaBridge 126:abea610beb85 10468 #define DSI_VNPCCR_NPSIZE7 0x00000080U
AnnaBridge 126:abea610beb85 10469 #define DSI_VNPCCR_NPSIZE8 0x00000100U
AnnaBridge 126:abea610beb85 10470 #define DSI_VNPCCR_NPSIZE9 0x00000200U
AnnaBridge 126:abea610beb85 10471 #define DSI_VNPCCR_NPSIZE10 0x00000400U
AnnaBridge 126:abea610beb85 10472 #define DSI_VNPCCR_NPSIZE11 0x00000800U
AnnaBridge 126:abea610beb85 10473 #define DSI_VNPCCR_NPSIZE12 0x00001000U
AnnaBridge 126:abea610beb85 10474
AnnaBridge 126:abea610beb85 10475 /******************* Bit definition for DSI_VHSACCR register ************/
AnnaBridge 126:abea610beb85 10476 #define DSI_VHSACCR_HSA 0x00000FFFU /*!< Horizontal Synchronism Active duration */
AnnaBridge 126:abea610beb85 10477 #define DSI_VHSACCR_HSA0 0x00000001U
AnnaBridge 126:abea610beb85 10478 #define DSI_VHSACCR_HSA1 0x00000002U
AnnaBridge 126:abea610beb85 10479 #define DSI_VHSACCR_HSA2 0x00000004U
AnnaBridge 126:abea610beb85 10480 #define DSI_VHSACCR_HSA3 0x00000008U
AnnaBridge 126:abea610beb85 10481 #define DSI_VHSACCR_HSA4 0x00000010U
AnnaBridge 126:abea610beb85 10482 #define DSI_VHSACCR_HSA5 0x00000020U
AnnaBridge 126:abea610beb85 10483 #define DSI_VHSACCR_HSA6 0x00000040U
AnnaBridge 126:abea610beb85 10484 #define DSI_VHSACCR_HSA7 0x00000080U
AnnaBridge 126:abea610beb85 10485 #define DSI_VHSACCR_HSA8 0x00000100U
AnnaBridge 126:abea610beb85 10486 #define DSI_VHSACCR_HSA9 0x00000200U
AnnaBridge 126:abea610beb85 10487 #define DSI_VHSACCR_HSA10 0x00000400U
AnnaBridge 126:abea610beb85 10488 #define DSI_VHSACCR_HSA11 0x00000800U
AnnaBridge 126:abea610beb85 10489
AnnaBridge 126:abea610beb85 10490 /******************* Bit definition for DSI_VHBPCCR register ************/
AnnaBridge 126:abea610beb85 10491 #define DSI_VHBPCCR_HBP 0x00000FFFU /*!< Horizontal Back-Porch duration */
AnnaBridge 126:abea610beb85 10492 #define DSI_VHBPCCR_HBP0 0x00000001U
AnnaBridge 126:abea610beb85 10493 #define DSI_VHBPCCR_HBP1 0x00000002U
AnnaBridge 126:abea610beb85 10494 #define DSI_VHBPCCR_HBP2 0x00000004U
AnnaBridge 126:abea610beb85 10495 #define DSI_VHBPCCR_HBP3 0x00000008U
AnnaBridge 126:abea610beb85 10496 #define DSI_VHBPCCR_HBP4 0x00000010U
AnnaBridge 126:abea610beb85 10497 #define DSI_VHBPCCR_HBP5 0x00000020U
AnnaBridge 126:abea610beb85 10498 #define DSI_VHBPCCR_HBP6 0x00000040U
AnnaBridge 126:abea610beb85 10499 #define DSI_VHBPCCR_HBP7 0x00000080U
AnnaBridge 126:abea610beb85 10500 #define DSI_VHBPCCR_HBP8 0x00000100U
AnnaBridge 126:abea610beb85 10501 #define DSI_VHBPCCR_HBP9 0x00000200U
AnnaBridge 126:abea610beb85 10502 #define DSI_VHBPCCR_HBP10 0x00000400U
AnnaBridge 126:abea610beb85 10503 #define DSI_VHBPCCR_HBP11 0x00000800U
AnnaBridge 126:abea610beb85 10504
AnnaBridge 126:abea610beb85 10505 /******************* Bit definition for DSI_VLCCR register **************/
AnnaBridge 126:abea610beb85 10506 #define DSI_VLCCR_HLINE 0x00007FFFU /*!< Horizontal Line duration */
AnnaBridge 126:abea610beb85 10507 #define DSI_VLCCR_HLINE0 0x00000001U
AnnaBridge 126:abea610beb85 10508 #define DSI_VLCCR_HLINE1 0x00000002U
AnnaBridge 126:abea610beb85 10509 #define DSI_VLCCR_HLINE2 0x00000004U
AnnaBridge 126:abea610beb85 10510 #define DSI_VLCCR_HLINE3 0x00000008U
AnnaBridge 126:abea610beb85 10511 #define DSI_VLCCR_HLINE4 0x00000010U
AnnaBridge 126:abea610beb85 10512 #define DSI_VLCCR_HLINE5 0x00000020U
AnnaBridge 126:abea610beb85 10513 #define DSI_VLCCR_HLINE6 0x00000040U
AnnaBridge 126:abea610beb85 10514 #define DSI_VLCCR_HLINE7 0x00000080U
AnnaBridge 126:abea610beb85 10515 #define DSI_VLCCR_HLINE8 0x00000100U
AnnaBridge 126:abea610beb85 10516 #define DSI_VLCCR_HLINE9 0x00000200U
AnnaBridge 126:abea610beb85 10517 #define DSI_VLCCR_HLINE10 0x00000400U
AnnaBridge 126:abea610beb85 10518 #define DSI_VLCCR_HLINE11 0x00000800U
AnnaBridge 126:abea610beb85 10519 #define DSI_VLCCR_HLINE12 0x00001000U
AnnaBridge 126:abea610beb85 10520 #define DSI_VLCCR_HLINE13 0x00002000U
AnnaBridge 126:abea610beb85 10521 #define DSI_VLCCR_HLINE14 0x00004000U
AnnaBridge 126:abea610beb85 10522
AnnaBridge 126:abea610beb85 10523 /******************* Bit definition for DSI_VVSACCR register ***************/
AnnaBridge 126:abea610beb85 10524 #define DSI_VVSACCR_VSA 0x000003FFU /*!< Vertical Synchronism Active duration */
AnnaBridge 126:abea610beb85 10525 #define DSI_VVSACCR_VSA0 0x00000001U
AnnaBridge 126:abea610beb85 10526 #define DSI_VVSACCR_VSA1 0x00000002U
AnnaBridge 126:abea610beb85 10527 #define DSI_VVSACCR_VSA2 0x00000004U
AnnaBridge 126:abea610beb85 10528 #define DSI_VVSACCR_VSA3 0x00000008U
AnnaBridge 126:abea610beb85 10529 #define DSI_VVSACCR_VSA4 0x00000010U
AnnaBridge 126:abea610beb85 10530 #define DSI_VVSACCR_VSA5 0x00000020U
AnnaBridge 126:abea610beb85 10531 #define DSI_VVSACCR_VSA6 0x00000040U
AnnaBridge 126:abea610beb85 10532 #define DSI_VVSACCR_VSA7 0x00000080U
AnnaBridge 126:abea610beb85 10533 #define DSI_VVSACCR_VSA8 0x00000100U
AnnaBridge 126:abea610beb85 10534 #define DSI_VVSACCR_VSA9 0x00000200U
AnnaBridge 126:abea610beb85 10535
AnnaBridge 126:abea610beb85 10536 /******************* Bit definition for DSI_VVBPCCR register ************/
AnnaBridge 126:abea610beb85 10537 #define DSI_VVBPCCR_VBP 0x000003FFU /*!< Vertical Back-Porch duration */
AnnaBridge 126:abea610beb85 10538 #define DSI_VVBPCCR_VBP0 0x00000001U
AnnaBridge 126:abea610beb85 10539 #define DSI_VVBPCCR_VBP1 0x00000002U
AnnaBridge 126:abea610beb85 10540 #define DSI_VVBPCCR_VBP2 0x00000004U
AnnaBridge 126:abea610beb85 10541 #define DSI_VVBPCCR_VBP3 0x00000008U
AnnaBridge 126:abea610beb85 10542 #define DSI_VVBPCCR_VBP4 0x00000010U
AnnaBridge 126:abea610beb85 10543 #define DSI_VVBPCCR_VBP5 0x00000020U
AnnaBridge 126:abea610beb85 10544 #define DSI_VVBPCCR_VBP6 0x00000040U
AnnaBridge 126:abea610beb85 10545 #define DSI_VVBPCCR_VBP7 0x00000080U
AnnaBridge 126:abea610beb85 10546 #define DSI_VVBPCCR_VBP8 0x00000100U
AnnaBridge 126:abea610beb85 10547 #define DSI_VVBPCCR_VBP9 0x00000200U
AnnaBridge 126:abea610beb85 10548
AnnaBridge 126:abea610beb85 10549 /******************* Bit definition for DSI_VVFPCCR register ************/
AnnaBridge 126:abea610beb85 10550 #define DSI_VVFPCCR_VFP 0x000003FFU /*!< Vertical Front-Porch duration */
AnnaBridge 126:abea610beb85 10551 #define DSI_VVFPCCR_VFP0 0x00000001U
AnnaBridge 126:abea610beb85 10552 #define DSI_VVFPCCR_VFP1 0x00000002U
AnnaBridge 126:abea610beb85 10553 #define DSI_VVFPCCR_VFP2 0x00000004U
AnnaBridge 126:abea610beb85 10554 #define DSI_VVFPCCR_VFP3 0x00000008U
AnnaBridge 126:abea610beb85 10555 #define DSI_VVFPCCR_VFP4 0x00000010U
AnnaBridge 126:abea610beb85 10556 #define DSI_VVFPCCR_VFP5 0x00000020U
AnnaBridge 126:abea610beb85 10557 #define DSI_VVFPCCR_VFP6 0x00000040U
AnnaBridge 126:abea610beb85 10558 #define DSI_VVFPCCR_VFP7 0x00000080U
AnnaBridge 126:abea610beb85 10559 #define DSI_VVFPCCR_VFP8 0x00000100U
AnnaBridge 126:abea610beb85 10560 #define DSI_VVFPCCR_VFP9 0x00000200U
AnnaBridge 126:abea610beb85 10561
AnnaBridge 126:abea610beb85 10562 /******************* Bit definition for DSI_VVACCR register *************/
AnnaBridge 126:abea610beb85 10563 #define DSI_VVACCR_VA 0x00003FFFU /*!< Vertical Active duration */
AnnaBridge 126:abea610beb85 10564 #define DSI_VVACCR_VA0 0x00000001U
AnnaBridge 126:abea610beb85 10565 #define DSI_VVACCR_VA1 0x00000002U
AnnaBridge 126:abea610beb85 10566 #define DSI_VVACCR_VA2 0x00000004U
AnnaBridge 126:abea610beb85 10567 #define DSI_VVACCR_VA3 0x00000008U
AnnaBridge 126:abea610beb85 10568 #define DSI_VVACCR_VA4 0x00000010U
AnnaBridge 126:abea610beb85 10569 #define DSI_VVACCR_VA5 0x00000020U
AnnaBridge 126:abea610beb85 10570 #define DSI_VVACCR_VA6 0x00000040U
AnnaBridge 126:abea610beb85 10571 #define DSI_VVACCR_VA7 0x00000080U
AnnaBridge 126:abea610beb85 10572 #define DSI_VVACCR_VA8 0x00000100U
AnnaBridge 126:abea610beb85 10573 #define DSI_VVACCR_VA9 0x00000200U
AnnaBridge 126:abea610beb85 10574 #define DSI_VVACCR_VA10 0x00000400U
AnnaBridge 126:abea610beb85 10575 #define DSI_VVACCR_VA11 0x00000800U
AnnaBridge 126:abea610beb85 10576 #define DSI_VVACCR_VA12 0x00001000U
AnnaBridge 126:abea610beb85 10577 #define DSI_VVACCR_VA13 0x00002000U
AnnaBridge 126:abea610beb85 10578
AnnaBridge 126:abea610beb85 10579 /******************* Bit definition for DSI_TDCCR register **************/
AnnaBridge 126:abea610beb85 10580 #define DSI_TDCCR_3DM 0x00000003U /*!< 3D Mode */
AnnaBridge 126:abea610beb85 10581 #define DSI_TDCCR_3DM0 0x00000001U
AnnaBridge 126:abea610beb85 10582 #define DSI_TDCCR_3DM1 0x00000002U
AnnaBridge 126:abea610beb85 10583
AnnaBridge 126:abea610beb85 10584 #define DSI_TDCCR_3DF 0x0000000CU /*!< 3D Format */
AnnaBridge 126:abea610beb85 10585 #define DSI_TDCCR_3DF0 0x00000004U
AnnaBridge 126:abea610beb85 10586 #define DSI_TDCCR_3DF1 0x00000008U
AnnaBridge 126:abea610beb85 10587
AnnaBridge 126:abea610beb85 10588 #define DSI_TDCCR_SVS 0x00000010U /*!< Second VSYNC */
AnnaBridge 126:abea610beb85 10589 #define DSI_TDCCR_RF 0x00000020U /*!< Right First */
AnnaBridge 126:abea610beb85 10590 #define DSI_TDCCR_S3DC 0x00010000U /*!< Send 3D Control */
AnnaBridge 126:abea610beb85 10591
AnnaBridge 126:abea610beb85 10592 /******************* Bit definition for DSI_WCFGR register ***************/
AnnaBridge 126:abea610beb85 10593 #define DSI_WCFGR_DSIM 0x00000001U /*!< DSI Mode */
AnnaBridge 126:abea610beb85 10594 #define DSI_WCFGR_COLMUX 0x0000000EU /*!< Color Multiplexing */
AnnaBridge 126:abea610beb85 10595 #define DSI_WCFGR_COLMUX0 0x00000002U
AnnaBridge 126:abea610beb85 10596 #define DSI_WCFGR_COLMUX1 0x00000004U
AnnaBridge 126:abea610beb85 10597 #define DSI_WCFGR_COLMUX2 0x00000008U
AnnaBridge 126:abea610beb85 10598
AnnaBridge 126:abea610beb85 10599 #define DSI_WCFGR_TESRC 0x00000010U /*!< Tearing Effect Source */
AnnaBridge 126:abea610beb85 10600 #define DSI_WCFGR_TEPOL 0x00000020U /*!< Tearing Effect Polarity */
AnnaBridge 126:abea610beb85 10601 #define DSI_WCFGR_AR 0x00000040U /*!< Automatic Refresh */
AnnaBridge 126:abea610beb85 10602 #define DSI_WCFGR_VSPOL 0x00000080U /*!< VSync Polarity */
AnnaBridge 126:abea610beb85 10603
AnnaBridge 126:abea610beb85 10604 /******************* Bit definition for DSI_WCR register *****************/
AnnaBridge 126:abea610beb85 10605 #define DSI_WCR_COLM 0x00000001U /*!< Color Mode */
AnnaBridge 126:abea610beb85 10606 #define DSI_WCR_SHTDN 0x00000002U /*!< Shutdown */
AnnaBridge 126:abea610beb85 10607 #define DSI_WCR_LTDCEN 0x00000004U /*!< LTDC Enable */
AnnaBridge 126:abea610beb85 10608 #define DSI_WCR_DSIEN 0x00000008U /*!< DSI Enable */
AnnaBridge 126:abea610beb85 10609
AnnaBridge 126:abea610beb85 10610 /******************* Bit definition for DSI_WIER register ****************/
AnnaBridge 126:abea610beb85 10611 #define DSI_WIER_TEIE 0x00000001U /*!< Tearing Effect Interrupt Enable */
AnnaBridge 126:abea610beb85 10612 #define DSI_WIER_ERIE 0x00000002U /*!< End of Refresh Interrupt Enable */
AnnaBridge 126:abea610beb85 10613 #define DSI_WIER_PLLLIE 0x00000200U /*!< PLL Lock Interrupt Enable */
AnnaBridge 126:abea610beb85 10614 #define DSI_WIER_PLLUIE 0x00000400U /*!< PLL Unlock Interrupt Enable */
AnnaBridge 126:abea610beb85 10615 #define DSI_WIER_RRIE 0x00002000U /*!< Regulator Ready Interrupt Enable */
AnnaBridge 126:abea610beb85 10616
AnnaBridge 126:abea610beb85 10617 /******************* Bit definition for DSI_WISR register ****************/
AnnaBridge 126:abea610beb85 10618 #define DSI_WISR_TEIF 0x00000001U /*!< Tearing Effect Interrupt Flag */
AnnaBridge 126:abea610beb85 10619 #define DSI_WISR_ERIF 0x00000002U /*!< End of Refresh Interrupt Flag */
AnnaBridge 126:abea610beb85 10620 #define DSI_WISR_BUSY 0x00000004U /*!< Busy Flag */
AnnaBridge 126:abea610beb85 10621 #define DSI_WISR_PLLLS 0x00000100U /*!< PLL Lock Status */
AnnaBridge 126:abea610beb85 10622 #define DSI_WISR_PLLLIF 0x00000200U /*!< PLL Lock Interrupt Flag */
AnnaBridge 126:abea610beb85 10623 #define DSI_WISR_PLLUIF 0x00000400U /*!< PLL Unlock Interrupt Flag */
AnnaBridge 126:abea610beb85 10624 #define DSI_WISR_RRS 0x00001000U /*!< Regulator Ready Flag */
AnnaBridge 126:abea610beb85 10625 #define DSI_WISR_RRIF 0x00002000U /*!< Regulator Ready Interrupt Flag */
AnnaBridge 126:abea610beb85 10626
AnnaBridge 126:abea610beb85 10627 /******************* Bit definition for DSI_WIFCR register ***************/
AnnaBridge 126:abea610beb85 10628 #define DSI_WIFCR_CTEIF 0x00000001U /*!< Clear Tearing Effect Interrupt Flag */
AnnaBridge 126:abea610beb85 10629 #define DSI_WIFCR_CERIF 0x00000002U /*!< Clear End of Refresh Interrupt Flag */
AnnaBridge 126:abea610beb85 10630 #define DSI_WIFCR_CPLLLIF 0x00000200U /*!< Clear PLL Lock Interrupt Flag */
AnnaBridge 126:abea610beb85 10631 #define DSI_WIFCR_CPLLUIF 0x00000400U /*!< Clear PLL Unlock Interrupt Flag */
AnnaBridge 126:abea610beb85 10632 #define DSI_WIFCR_CRRIF 0x00002000U /*!< Clear Regulator Ready Interrupt Flag */
AnnaBridge 126:abea610beb85 10633
AnnaBridge 126:abea610beb85 10634 /******************* Bit definition for DSI_WPCR0 register ***************/
AnnaBridge 126:abea610beb85 10635 #define DSI_WPCR0_UIX4 0x0000003FU /*!< Unit Interval multiplied by 4 */
AnnaBridge 126:abea610beb85 10636 #define DSI_WPCR0_UIX4_0 0x00000001U
AnnaBridge 126:abea610beb85 10637 #define DSI_WPCR0_UIX4_1 0x00000002U
AnnaBridge 126:abea610beb85 10638 #define DSI_WPCR0_UIX4_2 0x00000004U
AnnaBridge 126:abea610beb85 10639 #define DSI_WPCR0_UIX4_3 0x00000008U
AnnaBridge 126:abea610beb85 10640 #define DSI_WPCR0_UIX4_4 0x00000010U
AnnaBridge 126:abea610beb85 10641 #define DSI_WPCR0_UIX4_5 0x00000020U
AnnaBridge 126:abea610beb85 10642
AnnaBridge 126:abea610beb85 10643 #define DSI_WPCR0_SWCL 0x00000040U /*!< Swap pins on clock lane */
AnnaBridge 126:abea610beb85 10644 #define DSI_WPCR0_SWDL0 0x00000080U /*!< Swap pins on data lane 1 */
AnnaBridge 126:abea610beb85 10645 #define DSI_WPCR0_SWDL1 0x00000100U /*!< Swap pins on data lane 2 */
AnnaBridge 126:abea610beb85 10646 #define DSI_WPCR0_HSICL 0x00000200U /*!< Invert the high-speed data signal on clock lane */
AnnaBridge 126:abea610beb85 10647 #define DSI_WPCR0_HSIDL0 0x00000400U /*!< Invert the high-speed data signal on lane 1 */
AnnaBridge 126:abea610beb85 10648 #define DSI_WPCR0_HSIDL1 0x00000800U /*!< Invert the high-speed data signal on lane 2 */
AnnaBridge 126:abea610beb85 10649 #define DSI_WPCR0_FTXSMCL 0x00001000U /*!< Force clock lane in TX stop mode */
AnnaBridge 126:abea610beb85 10650 #define DSI_WPCR0_FTXSMDL 0x00002000U /*!< Force data lanes in TX stop mode */
AnnaBridge 126:abea610beb85 10651 #define DSI_WPCR0_CDOFFDL 0x00004000U /*!< Contention detection OFF */
AnnaBridge 126:abea610beb85 10652 #define DSI_WPCR0_TDDL 0x00010000U /*!< Turn Disable Data Lanes */
AnnaBridge 126:abea610beb85 10653 #define DSI_WPCR0_PDEN 0x00040000U /*!< Pull-Down Enable */
AnnaBridge 126:abea610beb85 10654 #define DSI_WPCR0_TCLKPREPEN 0x00080000U /*!< Timer for t-CLKPREP Enable */
AnnaBridge 126:abea610beb85 10655 #define DSI_WPCR0_TCLKZEROEN 0x00100000U /*!< Timer for t-CLKZERO Enable */
AnnaBridge 126:abea610beb85 10656 #define DSI_WPCR0_THSPREPEN 0x00200000U /*!< Timer for t-HSPREP Enable */
AnnaBridge 126:abea610beb85 10657 #define DSI_WPCR0_THSTRAILEN 0x00400000U /*!< Timer for t-HSTRAIL Enable */
AnnaBridge 126:abea610beb85 10658 #define DSI_WPCR0_THSZEROEN 0x00800000U /*!< Timer for t-HSZERO Enable */
AnnaBridge 126:abea610beb85 10659 #define DSI_WPCR0_TLPXDEN 0x01000000U /*!< Timer for t-LPXD Enable */
AnnaBridge 126:abea610beb85 10660 #define DSI_WPCR0_THSEXITEN 0x02000000U /*!< Timer for t-HSEXIT Enable */
AnnaBridge 126:abea610beb85 10661 #define DSI_WPCR0_TLPXCEN 0x04000000U /*!< Timer for t-LPXC Enable */
AnnaBridge 126:abea610beb85 10662 #define DSI_WPCR0_TCLKPOSTEN 0x08000000U /*!< Timer for t-CLKPOST Enable */
AnnaBridge 126:abea610beb85 10663
AnnaBridge 126:abea610beb85 10664 /******************* Bit definition for DSI_WPCR1 register ***************/
AnnaBridge 126:abea610beb85 10665 #define DSI_WPCR1_HSTXDCL 0x00000003U /*!< High-Speed Transmission Delay on Clock Lane */
AnnaBridge 126:abea610beb85 10666 #define DSI_WPCR1_HSTXDCL0 0x00000001U
AnnaBridge 126:abea610beb85 10667 #define DSI_WPCR1_HSTXDCL1 0x00000002U
AnnaBridge 126:abea610beb85 10668
AnnaBridge 126:abea610beb85 10669 #define DSI_WPCR1_HSTXDDL 0x0000000CU /*!< High-Speed Transmission Delay on Data Lane */
AnnaBridge 126:abea610beb85 10670 #define DSI_WPCR1_HSTXDDL0 0x00000004U
AnnaBridge 126:abea610beb85 10671 #define DSI_WPCR1_HSTXDDL1 0x00000008U
AnnaBridge 126:abea610beb85 10672
AnnaBridge 126:abea610beb85 10673 #define DSI_WPCR1_LPSRCCL 0x000000C0U /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
AnnaBridge 126:abea610beb85 10674 #define DSI_WPCR1_LPSRCCL0 0x00000040U
AnnaBridge 126:abea610beb85 10675 #define DSI_WPCR1_LPSRCCL1 0x00000080U
AnnaBridge 126:abea610beb85 10676
AnnaBridge 126:abea610beb85 10677 #define DSI_WPCR1_LPSRCDL 0x00000300U /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
AnnaBridge 126:abea610beb85 10678 #define DSI_WPCR1_LPSRCDL0 0x00000100U
AnnaBridge 126:abea610beb85 10679 #define DSI_WPCR1_LPSRCDL1 0x00000200U
AnnaBridge 126:abea610beb85 10680
AnnaBridge 126:abea610beb85 10681 #define DSI_WPCR1_SDDC 0x00001000U /*!< SDD Control */
AnnaBridge 126:abea610beb85 10682
AnnaBridge 126:abea610beb85 10683 #define DSI_WPCR1_LPRXVCDL 0x0000C000U /*!< Low-Power Reception V-IL Compensation on Data Lanes */
AnnaBridge 126:abea610beb85 10684 #define DSI_WPCR1_LPRXVCDL0 0x00004000U
AnnaBridge 126:abea610beb85 10685 #define DSI_WPCR1_LPRXVCDL1 0x00008000U
AnnaBridge 126:abea610beb85 10686
AnnaBridge 126:abea610beb85 10687 #define DSI_WPCR1_HSTXSRCCL 0x00030000U /*!< High-Speed Transmission Delay on Clock Lane */
AnnaBridge 126:abea610beb85 10688 #define DSI_WPCR1_HSTXSRCCL0 0x00010000U
AnnaBridge 126:abea610beb85 10689 #define DSI_WPCR1_HSTXSRCCL1 0x00020000U
AnnaBridge 126:abea610beb85 10690
AnnaBridge 126:abea610beb85 10691 #define DSI_WPCR1_HSTXSRCDL 0x000C0000U /*!< High-Speed Transmission Delay on Data Lane */
AnnaBridge 126:abea610beb85 10692 #define DSI_WPCR1_HSTXSRCDL0 0x00040000U
AnnaBridge 126:abea610beb85 10693 #define DSI_WPCR1_HSTXSRCDL1 0x00080000U
AnnaBridge 126:abea610beb85 10694
AnnaBridge 126:abea610beb85 10695 #define DSI_WPCR1_FLPRXLPM 0x00400000U /*!< Forces LP Receiver in Low-Power Mode */
AnnaBridge 126:abea610beb85 10696
AnnaBridge 126:abea610beb85 10697 #define DSI_WPCR1_LPRXFT 0x06000000U /*!< Low-Power RX low-pass Filtering Tuning */
AnnaBridge 126:abea610beb85 10698 #define DSI_WPCR1_LPRXFT0 0x02000000U
AnnaBridge 126:abea610beb85 10699 #define DSI_WPCR1_LPRXFT1 0x04000000U
AnnaBridge 126:abea610beb85 10700
AnnaBridge 126:abea610beb85 10701 /******************* Bit definition for DSI_WPCR2 register ***************/
AnnaBridge 126:abea610beb85 10702 #define DSI_WPCR2_TCLKPREP 0x000000FFU /*!< t-CLKPREP */
AnnaBridge 126:abea610beb85 10703 #define DSI_WPCR2_TCLKPREP0 0x00000001U
AnnaBridge 126:abea610beb85 10704 #define DSI_WPCR2_TCLKPREP1 0x00000002U
AnnaBridge 126:abea610beb85 10705 #define DSI_WPCR2_TCLKPREP2 0x00000004U
AnnaBridge 126:abea610beb85 10706 #define DSI_WPCR2_TCLKPREP3 0x00000008U
AnnaBridge 126:abea610beb85 10707 #define DSI_WPCR2_TCLKPREP4 0x00000010U
AnnaBridge 126:abea610beb85 10708 #define DSI_WPCR2_TCLKPREP5 0x00000020U
AnnaBridge 126:abea610beb85 10709 #define DSI_WPCR2_TCLKPREP6 0x00000040U
AnnaBridge 126:abea610beb85 10710 #define DSI_WPCR2_TCLKPREP7 0x00000080U
AnnaBridge 126:abea610beb85 10711
AnnaBridge 126:abea610beb85 10712 #define DSI_WPCR2_TCLKZERO 0x0000FF00U /*!< t-CLKZERO */
AnnaBridge 126:abea610beb85 10713 #define DSI_WPCR2_TCLKZERO0 0x00000100U
AnnaBridge 126:abea610beb85 10714 #define DSI_WPCR2_TCLKZERO1 0x00000200U
AnnaBridge 126:abea610beb85 10715 #define DSI_WPCR2_TCLKZERO2 0x00000400U
AnnaBridge 126:abea610beb85 10716 #define DSI_WPCR2_TCLKZERO3 0x00000800U
AnnaBridge 126:abea610beb85 10717 #define DSI_WPCR2_TCLKZERO4 0x00001000U
AnnaBridge 126:abea610beb85 10718 #define DSI_WPCR2_TCLKZERO5 0x00002000U
AnnaBridge 126:abea610beb85 10719 #define DSI_WPCR2_TCLKZERO6 0x00004000U
AnnaBridge 126:abea610beb85 10720 #define DSI_WPCR2_TCLKZERO7 0x00008000U
AnnaBridge 126:abea610beb85 10721
AnnaBridge 126:abea610beb85 10722 #define DSI_WPCR2_THSPREP 0x00FF0000U /*!< t-HSPREP */
AnnaBridge 126:abea610beb85 10723 #define DSI_WPCR2_THSPREP0 0x00010000U
AnnaBridge 126:abea610beb85 10724 #define DSI_WPCR2_THSPREP1 0x00020000U
AnnaBridge 126:abea610beb85 10725 #define DSI_WPCR2_THSPREP2 0x00040000U
AnnaBridge 126:abea610beb85 10726 #define DSI_WPCR2_THSPREP3 0x00080000U
AnnaBridge 126:abea610beb85 10727 #define DSI_WPCR2_THSPREP4 0x00100000U
AnnaBridge 126:abea610beb85 10728 #define DSI_WPCR2_THSPREP5 0x00200000U
AnnaBridge 126:abea610beb85 10729 #define DSI_WPCR2_THSPREP6 0x00400000U
AnnaBridge 126:abea610beb85 10730 #define DSI_WPCR2_THSPREP7 0x00800000U
AnnaBridge 126:abea610beb85 10731
AnnaBridge 126:abea610beb85 10732 #define DSI_WPCR2_THSTRAIL 0xFF000000U /*!< t-HSTRAIL */
AnnaBridge 126:abea610beb85 10733 #define DSI_WPCR2_THSTRAIL0 0x01000000U
AnnaBridge 126:abea610beb85 10734 #define DSI_WPCR2_THSTRAIL1 0x02000000U
AnnaBridge 126:abea610beb85 10735 #define DSI_WPCR2_THSTRAIL2 0x04000000U
AnnaBridge 126:abea610beb85 10736 #define DSI_WPCR2_THSTRAIL3 0x08000000U
AnnaBridge 126:abea610beb85 10737 #define DSI_WPCR2_THSTRAIL4 0x10000000U
AnnaBridge 126:abea610beb85 10738 #define DSI_WPCR2_THSTRAIL5 0x20000000U
AnnaBridge 126:abea610beb85 10739 #define DSI_WPCR2_THSTRAIL6 0x40000000U
AnnaBridge 126:abea610beb85 10740 #define DSI_WPCR2_THSTRAIL7 0x80000000U
AnnaBridge 126:abea610beb85 10741
AnnaBridge 126:abea610beb85 10742 /******************* Bit definition for DSI_WPCR3 register ***************/
AnnaBridge 126:abea610beb85 10743 #define DSI_WPCR3_THSZERO 0x000000FFU /*!< t-HSZERO */
AnnaBridge 126:abea610beb85 10744 #define DSI_WPCR3_THSZERO0 0x00000001U
AnnaBridge 126:abea610beb85 10745 #define DSI_WPCR3_THSZERO1 0x00000002U
AnnaBridge 126:abea610beb85 10746 #define DSI_WPCR3_THSZERO2 0x00000004U
AnnaBridge 126:abea610beb85 10747 #define DSI_WPCR3_THSZERO3 0x00000008U
AnnaBridge 126:abea610beb85 10748 #define DSI_WPCR3_THSZERO4 0x00000010U
AnnaBridge 126:abea610beb85 10749 #define DSI_WPCR3_THSZERO5 0x00000020U
AnnaBridge 126:abea610beb85 10750 #define DSI_WPCR3_THSZERO6 0x00000040U
AnnaBridge 126:abea610beb85 10751 #define DSI_WPCR3_THSZERO7 0x00000080U
AnnaBridge 126:abea610beb85 10752
AnnaBridge 126:abea610beb85 10753 #define DSI_WPCR3_TLPXD 0x0000FF00U /*!< t-LPXD */
AnnaBridge 126:abea610beb85 10754 #define DSI_WPCR3_TLPXD0 0x00000100U
AnnaBridge 126:abea610beb85 10755 #define DSI_WPCR3_TLPXD1 0x00000200U
AnnaBridge 126:abea610beb85 10756 #define DSI_WPCR3_TLPXD2 0x00000400U
AnnaBridge 126:abea610beb85 10757 #define DSI_WPCR3_TLPXD3 0x00000800U
AnnaBridge 126:abea610beb85 10758 #define DSI_WPCR3_TLPXD4 0x00001000U
AnnaBridge 126:abea610beb85 10759 #define DSI_WPCR3_TLPXD5 0x00002000U
AnnaBridge 126:abea610beb85 10760 #define DSI_WPCR3_TLPXD6 0x00004000U
AnnaBridge 126:abea610beb85 10761 #define DSI_WPCR3_TLPXD7 0x00008000U
AnnaBridge 126:abea610beb85 10762
AnnaBridge 126:abea610beb85 10763 #define DSI_WPCR3_THSEXIT 0x00FF0000U /*!< t-HSEXIT */
AnnaBridge 126:abea610beb85 10764 #define DSI_WPCR3_THSEXIT0 0x00010000U
AnnaBridge 126:abea610beb85 10765 #define DSI_WPCR3_THSEXIT1 0x00020000U
AnnaBridge 126:abea610beb85 10766 #define DSI_WPCR3_THSEXIT2 0x00040000U
AnnaBridge 126:abea610beb85 10767 #define DSI_WPCR3_THSEXIT3 0x00080000U
AnnaBridge 126:abea610beb85 10768 #define DSI_WPCR3_THSEXIT4 0x00100000U
AnnaBridge 126:abea610beb85 10769 #define DSI_WPCR3_THSEXIT5 0x00200000U
AnnaBridge 126:abea610beb85 10770 #define DSI_WPCR3_THSEXIT6 0x00400000U
AnnaBridge 126:abea610beb85 10771 #define DSI_WPCR3_THSEXIT7 0x00800000U
AnnaBridge 126:abea610beb85 10772
AnnaBridge 126:abea610beb85 10773 #define DSI_WPCR3_TLPXC 0xFF000000U /*!< t-LPXC */
AnnaBridge 126:abea610beb85 10774 #define DSI_WPCR3_TLPXC0 0x01000000U
AnnaBridge 126:abea610beb85 10775 #define DSI_WPCR3_TLPXC1 0x02000000U
AnnaBridge 126:abea610beb85 10776 #define DSI_WPCR3_TLPXC2 0x04000000U
AnnaBridge 126:abea610beb85 10777 #define DSI_WPCR3_TLPXC3 0x08000000U
AnnaBridge 126:abea610beb85 10778 #define DSI_WPCR3_TLPXC4 0x10000000U
AnnaBridge 126:abea610beb85 10779 #define DSI_WPCR3_TLPXC5 0x20000000U
AnnaBridge 126:abea610beb85 10780 #define DSI_WPCR3_TLPXC6 0x40000000U
AnnaBridge 126:abea610beb85 10781 #define DSI_WPCR3_TLPXC7 0x80000000U
AnnaBridge 126:abea610beb85 10782
AnnaBridge 126:abea610beb85 10783 /******************* Bit definition for DSI_WPCR4 register ***************/
AnnaBridge 126:abea610beb85 10784 #define DSI_WPCR4_TCLKPOST 0x000000FFU /*!< t-CLKPOST */
AnnaBridge 126:abea610beb85 10785 #define DSI_WPCR4_TCLKPOST0 0x00000001U
AnnaBridge 126:abea610beb85 10786 #define DSI_WPCR4_TCLKPOST1 0x00000002U
AnnaBridge 126:abea610beb85 10787 #define DSI_WPCR4_TCLKPOST2 0x00000004U
AnnaBridge 126:abea610beb85 10788 #define DSI_WPCR4_TCLKPOST3 0x00000008U
AnnaBridge 126:abea610beb85 10789 #define DSI_WPCR4_TCLKPOST4 0x00000010U
AnnaBridge 126:abea610beb85 10790 #define DSI_WPCR4_TCLKPOST5 0x00000020U
AnnaBridge 126:abea610beb85 10791 #define DSI_WPCR4_TCLKPOST6 0x00000040U
AnnaBridge 126:abea610beb85 10792 #define DSI_WPCR4_TCLKPOST7 0x00000080U
AnnaBridge 126:abea610beb85 10793
AnnaBridge 126:abea610beb85 10794 /******************* Bit definition for DSI_WRPCR register ***************/
AnnaBridge 126:abea610beb85 10795 #define DSI_WRPCR_PLLEN 0x00000001U /*!< PLL Enable */
AnnaBridge 126:abea610beb85 10796 #define DSI_WRPCR_PLL_NDIV 0x000001FCU /*!< PLL Loop Division Factor */
AnnaBridge 126:abea610beb85 10797 #define DSI_WRPCR_PLL_NDIV0 0x00000004U
AnnaBridge 126:abea610beb85 10798 #define DSI_WRPCR_PLL_NDIV1 0x00000008U
AnnaBridge 126:abea610beb85 10799 #define DSI_WRPCR_PLL_NDIV2 0x00000010U
AnnaBridge 126:abea610beb85 10800 #define DSI_WRPCR_PLL_NDIV3 0x00000020U
AnnaBridge 126:abea610beb85 10801 #define DSI_WRPCR_PLL_NDIV4 0x00000040U
AnnaBridge 126:abea610beb85 10802 #define DSI_WRPCR_PLL_NDIV5 0x00000080U
AnnaBridge 126:abea610beb85 10803 #define DSI_WRPCR_PLL_NDIV6 0x00000100U
AnnaBridge 126:abea610beb85 10804
AnnaBridge 126:abea610beb85 10805 #define DSI_WRPCR_PLL_IDF 0x00007800U /*!< PLL Input Division Factor */
AnnaBridge 126:abea610beb85 10806 #define DSI_WRPCR_PLL_IDF0 0x00000800U
AnnaBridge 126:abea610beb85 10807 #define DSI_WRPCR_PLL_IDF1 0x00001000U
AnnaBridge 126:abea610beb85 10808 #define DSI_WRPCR_PLL_IDF2 0x00002000U
AnnaBridge 126:abea610beb85 10809 #define DSI_WRPCR_PLL_IDF3 0x00004000U
AnnaBridge 126:abea610beb85 10810
AnnaBridge 126:abea610beb85 10811 #define DSI_WRPCR_PLL_ODF 0x00030000U /*!< PLL Output Division Factor */
AnnaBridge 126:abea610beb85 10812 #define DSI_WRPCR_PLL_ODF0 0x00010000U
AnnaBridge 126:abea610beb85 10813 #define DSI_WRPCR_PLL_ODF1 0x00020000U
AnnaBridge 126:abea610beb85 10814
AnnaBridge 126:abea610beb85 10815 #define DSI_WRPCR_REGEN 0x01000000U /*!< Regulator Enable */
AnnaBridge 126:abea610beb85 10816
AnnaBridge 126:abea610beb85 10817 /**
AnnaBridge 126:abea610beb85 10818 * @}
AnnaBridge 126:abea610beb85 10819 */
AnnaBridge 126:abea610beb85 10820
AnnaBridge 126:abea610beb85 10821 /**
AnnaBridge 126:abea610beb85 10822 * @}
AnnaBridge 126:abea610beb85 10823 */
AnnaBridge 126:abea610beb85 10824
AnnaBridge 126:abea610beb85 10825 /** @addtogroup Exported_macros
AnnaBridge 126:abea610beb85 10826 * @{
AnnaBridge 126:abea610beb85 10827 */
AnnaBridge 126:abea610beb85 10828
AnnaBridge 126:abea610beb85 10829 /******************************* ADC Instances ********************************/
AnnaBridge 126:abea610beb85 10830 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
AnnaBridge 126:abea610beb85 10831 ((__INSTANCE__) == ADC2) || \
AnnaBridge 126:abea610beb85 10832 ((__INSTANCE__) == ADC3))
AnnaBridge 126:abea610beb85 10833
AnnaBridge 126:abea610beb85 10834 /******************************* CAN Instances ********************************/
AnnaBridge 126:abea610beb85 10835 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
AnnaBridge 126:abea610beb85 10836 ((__INSTANCE__) == CAN2) || \
AnnaBridge 126:abea610beb85 10837 ((__INSTANCE__) == CAN3))
AnnaBridge 126:abea610beb85 10838 /******************************* CRC Instances ********************************/
AnnaBridge 126:abea610beb85 10839 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
AnnaBridge 126:abea610beb85 10840
AnnaBridge 126:abea610beb85 10841 /******************************* DAC Instances ********************************/
AnnaBridge 126:abea610beb85 10842 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
AnnaBridge 126:abea610beb85 10843
AnnaBridge 126:abea610beb85 10844 /******************************* DCMI Instances *******************************/
AnnaBridge 126:abea610beb85 10845 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
AnnaBridge 126:abea610beb85 10846
AnnaBridge 126:abea610beb85 10847 /****************************** DFSDM Instances *******************************/
AnnaBridge 126:abea610beb85 10848 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
AnnaBridge 126:abea610beb85 10849 ((INSTANCE) == DFSDM1_Filter1) || \
AnnaBridge 126:abea610beb85 10850 ((INSTANCE) == DFSDM1_Filter2) || \
AnnaBridge 126:abea610beb85 10851 ((INSTANCE) == DFSDM1_Filter3))
AnnaBridge 126:abea610beb85 10852
AnnaBridge 126:abea610beb85 10853 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
AnnaBridge 126:abea610beb85 10854 ((INSTANCE) == DFSDM1_Channel1) || \
AnnaBridge 126:abea610beb85 10855 ((INSTANCE) == DFSDM1_Channel2) || \
AnnaBridge 126:abea610beb85 10856 ((INSTANCE) == DFSDM1_Channel3) || \
AnnaBridge 126:abea610beb85 10857 ((INSTANCE) == DFSDM1_Channel4) || \
AnnaBridge 126:abea610beb85 10858 ((INSTANCE) == DFSDM1_Channel5) || \
AnnaBridge 126:abea610beb85 10859 ((INSTANCE) == DFSDM1_Channel6) || \
AnnaBridge 126:abea610beb85 10860 ((INSTANCE) == DFSDM1_Channel7))
AnnaBridge 126:abea610beb85 10861
AnnaBridge 126:abea610beb85 10862 /******************************* DMA2D Instances *******************************/
AnnaBridge 126:abea610beb85 10863 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
AnnaBridge 126:abea610beb85 10864
AnnaBridge 126:abea610beb85 10865 /******************************** DMA Instances *******************************/
AnnaBridge 126:abea610beb85 10866 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
AnnaBridge 126:abea610beb85 10867 ((__INSTANCE__) == DMA1_Stream1) || \
AnnaBridge 126:abea610beb85 10868 ((__INSTANCE__) == DMA1_Stream2) || \
AnnaBridge 126:abea610beb85 10869 ((__INSTANCE__) == DMA1_Stream3) || \
AnnaBridge 126:abea610beb85 10870 ((__INSTANCE__) == DMA1_Stream4) || \
AnnaBridge 126:abea610beb85 10871 ((__INSTANCE__) == DMA1_Stream5) || \
AnnaBridge 126:abea610beb85 10872 ((__INSTANCE__) == DMA1_Stream6) || \
AnnaBridge 126:abea610beb85 10873 ((__INSTANCE__) == DMA1_Stream7) || \
AnnaBridge 126:abea610beb85 10874 ((__INSTANCE__) == DMA2_Stream0) || \
AnnaBridge 126:abea610beb85 10875 ((__INSTANCE__) == DMA2_Stream1) || \
AnnaBridge 126:abea610beb85 10876 ((__INSTANCE__) == DMA2_Stream2) || \
AnnaBridge 126:abea610beb85 10877 ((__INSTANCE__) == DMA2_Stream3) || \
AnnaBridge 126:abea610beb85 10878 ((__INSTANCE__) == DMA2_Stream4) || \
AnnaBridge 126:abea610beb85 10879 ((__INSTANCE__) == DMA2_Stream5) || \
AnnaBridge 126:abea610beb85 10880 ((__INSTANCE__) == DMA2_Stream6) || \
AnnaBridge 126:abea610beb85 10881 ((__INSTANCE__) == DMA2_Stream7))
AnnaBridge 126:abea610beb85 10882
AnnaBridge 126:abea610beb85 10883 /******************************* GPIO Instances *******************************/
AnnaBridge 126:abea610beb85 10884 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
AnnaBridge 126:abea610beb85 10885 ((__INSTANCE__) == GPIOB) || \
AnnaBridge 126:abea610beb85 10886 ((__INSTANCE__) == GPIOC) || \
AnnaBridge 126:abea610beb85 10887 ((__INSTANCE__) == GPIOD) || \
AnnaBridge 126:abea610beb85 10888 ((__INSTANCE__) == GPIOE) || \
AnnaBridge 126:abea610beb85 10889 ((__INSTANCE__) == GPIOF) || \
AnnaBridge 126:abea610beb85 10890 ((__INSTANCE__) == GPIOG) || \
AnnaBridge 126:abea610beb85 10891 ((__INSTANCE__) == GPIOH) || \
AnnaBridge 126:abea610beb85 10892 ((__INSTANCE__) == GPIOI) || \
AnnaBridge 126:abea610beb85 10893 ((__INSTANCE__) == GPIOJ) || \
AnnaBridge 126:abea610beb85 10894 ((__INSTANCE__) == GPIOK))
AnnaBridge 126:abea610beb85 10895
AnnaBridge 126:abea610beb85 10896 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
AnnaBridge 126:abea610beb85 10897 ((__INSTANCE__) == GPIOB) || \
AnnaBridge 126:abea610beb85 10898 ((__INSTANCE__) == GPIOC) || \
AnnaBridge 126:abea610beb85 10899 ((__INSTANCE__) == GPIOD) || \
AnnaBridge 126:abea610beb85 10900 ((__INSTANCE__) == GPIOE) || \
AnnaBridge 126:abea610beb85 10901 ((__INSTANCE__) == GPIOF) || \
AnnaBridge 126:abea610beb85 10902 ((__INSTANCE__) == GPIOG) || \
AnnaBridge 126:abea610beb85 10903 ((__INSTANCE__) == GPIOH) || \
AnnaBridge 126:abea610beb85 10904 ((__INSTANCE__) == GPIOI) || \
AnnaBridge 126:abea610beb85 10905 ((__INSTANCE__) == GPIOJ) || \
AnnaBridge 126:abea610beb85 10906 ((__INSTANCE__) == GPIOK))
AnnaBridge 126:abea610beb85 10907
AnnaBridge 126:abea610beb85 10908 /****************************** CEC Instances *********************************/
AnnaBridge 126:abea610beb85 10909 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
AnnaBridge 126:abea610beb85 10910
AnnaBridge 126:abea610beb85 10911 /****************************** QSPI Instances *********************************/
AnnaBridge 126:abea610beb85 10912 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
AnnaBridge 126:abea610beb85 10913
AnnaBridge 126:abea610beb85 10914
AnnaBridge 126:abea610beb85 10915 /******************************** I2C Instances *******************************/
AnnaBridge 126:abea610beb85 10916 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
AnnaBridge 126:abea610beb85 10917 ((__INSTANCE__) == I2C2) || \
AnnaBridge 126:abea610beb85 10918 ((__INSTANCE__) == I2C3) || \
AnnaBridge 126:abea610beb85 10919 ((__INSTANCE__) == I2C4))
AnnaBridge 126:abea610beb85 10920
AnnaBridge 126:abea610beb85 10921 /******************************** I2S Instances *******************************/
AnnaBridge 126:abea610beb85 10922 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
AnnaBridge 126:abea610beb85 10923 ((__INSTANCE__) == SPI2) || \
AnnaBridge 126:abea610beb85 10924 ((__INSTANCE__) == SPI3))
AnnaBridge 126:abea610beb85 10925
AnnaBridge 126:abea610beb85 10926 /******************************* LPTIM Instances ********************************/
AnnaBridge 126:abea610beb85 10927 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
AnnaBridge 126:abea610beb85 10928
AnnaBridge 126:abea610beb85 10929 /****************************** LTDC Instances ********************************/
AnnaBridge 126:abea610beb85 10930 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
AnnaBridge 126:abea610beb85 10931
AnnaBridge 126:abea610beb85 10932 /****************************** MDIOS Instances ********************************/
AnnaBridge 126:abea610beb85 10933 #define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS)
AnnaBridge 126:abea610beb85 10934
AnnaBridge 126:abea610beb85 10935 /****************************** MDIOS Instances ********************************/
AnnaBridge 126:abea610beb85 10936 #define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)
AnnaBridge 126:abea610beb85 10937
AnnaBridge 126:abea610beb85 10938 /******************************* RNG Instances ********************************/
AnnaBridge 126:abea610beb85 10939 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
AnnaBridge 126:abea610beb85 10940
AnnaBridge 126:abea610beb85 10941 /****************************** RTC Instances *********************************/
AnnaBridge 126:abea610beb85 10942 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
AnnaBridge 126:abea610beb85 10943
AnnaBridge 126:abea610beb85 10944 /******************************* SAI Instances ********************************/
AnnaBridge 126:abea610beb85 10945 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
AnnaBridge 126:abea610beb85 10946 ((__PERIPH__) == SAI1_Block_B) || \
AnnaBridge 126:abea610beb85 10947 ((__PERIPH__) == SAI2_Block_A) || \
AnnaBridge 126:abea610beb85 10948 ((__PERIPH__) == SAI2_Block_B))
AnnaBridge 126:abea610beb85 10949 /* Legacy define */
AnnaBridge 126:abea610beb85 10950 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
AnnaBridge 126:abea610beb85 10951
AnnaBridge 126:abea610beb85 10952 /******************************** SDMMC Instances *******************************/
AnnaBridge 126:abea610beb85 10953 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
AnnaBridge 126:abea610beb85 10954 ((__INSTANCE__) == SDMMC2))
AnnaBridge 126:abea610beb85 10955
AnnaBridge 126:abea610beb85 10956 /****************************** SPDIFRX Instances *********************************/
AnnaBridge 126:abea610beb85 10957 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
AnnaBridge 126:abea610beb85 10958
AnnaBridge 126:abea610beb85 10959 /******************************** SPI Instances *******************************/
AnnaBridge 126:abea610beb85 10960 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
AnnaBridge 126:abea610beb85 10961 ((__INSTANCE__) == SPI2) || \
AnnaBridge 126:abea610beb85 10962 ((__INSTANCE__) == SPI3) || \
AnnaBridge 126:abea610beb85 10963 ((__INSTANCE__) == SPI4) || \
AnnaBridge 126:abea610beb85 10964 ((__INSTANCE__) == SPI5) || \
AnnaBridge 126:abea610beb85 10965 ((__INSTANCE__) == SPI6))
AnnaBridge 126:abea610beb85 10966
AnnaBridge 126:abea610beb85 10967 /****************** TIM Instances : All supported instances *******************/
AnnaBridge 126:abea610beb85 10968 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 10969 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 10970 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 10971 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 10972 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 10973 ((__INSTANCE__) == TIM6) || \
AnnaBridge 126:abea610beb85 10974 ((__INSTANCE__) == TIM7) || \
AnnaBridge 126:abea610beb85 10975 ((__INSTANCE__) == TIM8) || \
AnnaBridge 126:abea610beb85 10976 ((__INSTANCE__) == TIM9) || \
AnnaBridge 126:abea610beb85 10977 ((__INSTANCE__) == TIM10) || \
AnnaBridge 126:abea610beb85 10978 ((__INSTANCE__) == TIM11) || \
AnnaBridge 126:abea610beb85 10979 ((__INSTANCE__) == TIM12) || \
AnnaBridge 126:abea610beb85 10980 ((__INSTANCE__) == TIM13) || \
AnnaBridge 126:abea610beb85 10981 ((__INSTANCE__) == TIM14))
AnnaBridge 126:abea610beb85 10982
AnnaBridge 126:abea610beb85 10983 /************* TIM Instances : at least 1 capture/compare channel *************/
AnnaBridge 126:abea610beb85 10984 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 10985 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 10986 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 10987 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 10988 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 10989 ((__INSTANCE__) == TIM8) || \
AnnaBridge 126:abea610beb85 10990 ((__INSTANCE__) == TIM9) || \
AnnaBridge 126:abea610beb85 10991 ((__INSTANCE__) == TIM10) || \
AnnaBridge 126:abea610beb85 10992 ((__INSTANCE__) == TIM11) || \
AnnaBridge 126:abea610beb85 10993 ((__INSTANCE__) == TIM12) || \
AnnaBridge 126:abea610beb85 10994 ((__INSTANCE__) == TIM13) || \
AnnaBridge 126:abea610beb85 10995 ((__INSTANCE__) == TIM14))
AnnaBridge 126:abea610beb85 10996
AnnaBridge 126:abea610beb85 10997 /************ TIM Instances : at least 2 capture/compare channels *************/
AnnaBridge 126:abea610beb85 10998 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 10999 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11000 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11001 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11002 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11003 ((__INSTANCE__) == TIM8) || \
AnnaBridge 126:abea610beb85 11004 ((__INSTANCE__) == TIM9) || \
AnnaBridge 126:abea610beb85 11005 ((__INSTANCE__) == TIM12))
AnnaBridge 126:abea610beb85 11006
AnnaBridge 126:abea610beb85 11007 /************ TIM Instances : at least 3 capture/compare channels *************/
AnnaBridge 126:abea610beb85 11008 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11009 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11010 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11011 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11012 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11013 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11014
AnnaBridge 126:abea610beb85 11015 /************ TIM Instances : at least 4 capture/compare channels *************/
AnnaBridge 126:abea610beb85 11016 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11017 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11018 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11019 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11020 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11021 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11022
AnnaBridge 126:abea610beb85 11023 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
AnnaBridge 126:abea610beb85 11024 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
AnnaBridge 126:abea610beb85 11025 (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11026 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11027
AnnaBridge 126:abea610beb85 11028 /****************** TIM Instances : supporting OCxREF clear *******************/
AnnaBridge 126:abea610beb85 11029 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
AnnaBridge 126:abea610beb85 11030 (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11031 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11032 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11033 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11034 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11035
AnnaBridge 126:abea610beb85 11036 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
AnnaBridge 126:abea610beb85 11037 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
AnnaBridge 126:abea610beb85 11038 (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11039 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11040 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11041 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11042 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11043 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11044
AnnaBridge 126:abea610beb85 11045 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
AnnaBridge 126:abea610beb85 11046 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
AnnaBridge 126:abea610beb85 11047 (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11048 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11049 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11050 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11051 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11052 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11053 /****************** TIM Instances : at least 5 capture/compare channels *******/
AnnaBridge 126:abea610beb85 11054 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
AnnaBridge 126:abea610beb85 11055 (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11056 ((__INSTANCE__) == TIM8) )
AnnaBridge 126:abea610beb85 11057
AnnaBridge 126:abea610beb85 11058 /****************** TIM Instances : at least 6 capture/compare channels *******/
AnnaBridge 126:abea610beb85 11059 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
AnnaBridge 126:abea610beb85 11060 (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11061 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11062
AnnaBridge 126:abea610beb85 11063
AnnaBridge 126:abea610beb85 11064 /******************** TIM Instances : Advanced-control timers *****************/
AnnaBridge 126:abea610beb85 11065 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11066 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11067
AnnaBridge 126:abea610beb85 11068 /****************** TIM Instances : supporting 2 break inputs *****************/
AnnaBridge 126:abea610beb85 11069 #define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
AnnaBridge 126:abea610beb85 11070 (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11071 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11072
AnnaBridge 126:abea610beb85 11073 /******************* TIM Instances : Timer input XOR function *****************/
AnnaBridge 126:abea610beb85 11074 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11075 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11076 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11077 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11078 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11079 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11080
AnnaBridge 126:abea610beb85 11081 /****************** TIM Instances : DMA requests generation (UDE) *************/
AnnaBridge 126:abea610beb85 11082 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11083 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11084 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11085 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11086 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11087 ((__INSTANCE__) == TIM6) || \
AnnaBridge 126:abea610beb85 11088 ((__INSTANCE__) == TIM7) || \
AnnaBridge 126:abea610beb85 11089 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11090
AnnaBridge 126:abea610beb85 11091 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
AnnaBridge 126:abea610beb85 11092 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11093 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11094 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11095 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11096 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11097 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11098
AnnaBridge 126:abea610beb85 11099 /************ TIM Instances : DMA requests generation (COMDE) *****************/
AnnaBridge 126:abea610beb85 11100 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11101 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11102 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11103 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11104 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11105 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11106
AnnaBridge 126:abea610beb85 11107 /******************** TIM Instances : DMA burst feature ***********************/
AnnaBridge 126:abea610beb85 11108 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11109 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11110 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11111 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11112 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11113 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11114
AnnaBridge 126:abea610beb85 11115 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
AnnaBridge 126:abea610beb85 11116 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11117 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11118 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11119 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11120 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11121 ((__INSTANCE__) == TIM6) || \
AnnaBridge 126:abea610beb85 11122 ((__INSTANCE__) == TIM7) || \
AnnaBridge 126:abea610beb85 11123 ((__INSTANCE__) == TIM8) || \
AnnaBridge 126:abea610beb85 11124 ((__INSTANCE__) == TIM13) || \
AnnaBridge 126:abea610beb85 11125 ((__INSTANCE__) == TIM14))
AnnaBridge 126:abea610beb85 11126
AnnaBridge 126:abea610beb85 11127 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
AnnaBridge 126:abea610beb85 11128 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11129 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11130 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11131 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11132 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11133 ((__INSTANCE__) == TIM8) || \
AnnaBridge 126:abea610beb85 11134 ((__INSTANCE__) == TIM9) || \
AnnaBridge 126:abea610beb85 11135 ((__INSTANCE__) == TIM12))
AnnaBridge 126:abea610beb85 11136
AnnaBridge 126:abea610beb85 11137 /********************** TIM Instances : 32 bit Counter ************************/
AnnaBridge 126:abea610beb85 11138 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11139 ((__INSTANCE__) == TIM5))
AnnaBridge 126:abea610beb85 11140
AnnaBridge 126:abea610beb85 11141 /***************** TIM Instances : external trigger input available ************/
AnnaBridge 126:abea610beb85 11142 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11143 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11144 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11145 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11146 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11147 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11148
AnnaBridge 126:abea610beb85 11149 /****************** TIM Instances : remapping capability **********************/
AnnaBridge 126:abea610beb85 11150 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11151 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11152 ((__INSTANCE__) == TIM11))
AnnaBridge 126:abea610beb85 11153
AnnaBridge 126:abea610beb85 11154 /******************* TIM Instances : output(s) available **********************/
AnnaBridge 126:abea610beb85 11155 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
AnnaBridge 126:abea610beb85 11156 ((((__INSTANCE__) == TIM1) && \
AnnaBridge 126:abea610beb85 11157 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 126:abea610beb85 11158 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 126:abea610beb85 11159 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 126:abea610beb85 11160 ((__CHANNEL__) == TIM_CHANNEL_4))) \
AnnaBridge 126:abea610beb85 11161 || \
AnnaBridge 126:abea610beb85 11162 (((__INSTANCE__) == TIM2) && \
AnnaBridge 126:abea610beb85 11163 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 126:abea610beb85 11164 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 126:abea610beb85 11165 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 126:abea610beb85 11166 ((__CHANNEL__) == TIM_CHANNEL_4))) \
AnnaBridge 126:abea610beb85 11167 || \
AnnaBridge 126:abea610beb85 11168 (((__INSTANCE__) == TIM3) && \
AnnaBridge 126:abea610beb85 11169 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 126:abea610beb85 11170 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 126:abea610beb85 11171 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 126:abea610beb85 11172 ((__CHANNEL__) == TIM_CHANNEL_4))) \
AnnaBridge 126:abea610beb85 11173 || \
AnnaBridge 126:abea610beb85 11174 (((__INSTANCE__) == TIM4) && \
AnnaBridge 126:abea610beb85 11175 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 126:abea610beb85 11176 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 126:abea610beb85 11177 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 126:abea610beb85 11178 ((__CHANNEL__) == TIM_CHANNEL_4))) \
AnnaBridge 126:abea610beb85 11179 || \
AnnaBridge 126:abea610beb85 11180 (((__INSTANCE__) == TIM5) && \
AnnaBridge 126:abea610beb85 11181 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 126:abea610beb85 11182 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 126:abea610beb85 11183 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 126:abea610beb85 11184 ((__CHANNEL__) == TIM_CHANNEL_4))) \
AnnaBridge 126:abea610beb85 11185 || \
AnnaBridge 126:abea610beb85 11186 (((__INSTANCE__) == TIM8) && \
AnnaBridge 126:abea610beb85 11187 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 126:abea610beb85 11188 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 126:abea610beb85 11189 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 126:abea610beb85 11190 ((__CHANNEL__) == TIM_CHANNEL_4))) \
AnnaBridge 126:abea610beb85 11191 || \
AnnaBridge 126:abea610beb85 11192 (((__INSTANCE__) == TIM9) && \
AnnaBridge 126:abea610beb85 11193 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 126:abea610beb85 11194 ((__CHANNEL__) == TIM_CHANNEL_2))) \
AnnaBridge 126:abea610beb85 11195 || \
AnnaBridge 126:abea610beb85 11196 (((__INSTANCE__) == TIM10) && \
AnnaBridge 126:abea610beb85 11197 (((__CHANNEL__) == TIM_CHANNEL_1))) \
AnnaBridge 126:abea610beb85 11198 || \
AnnaBridge 126:abea610beb85 11199 (((__INSTANCE__) == TIM11) && \
AnnaBridge 126:abea610beb85 11200 (((__CHANNEL__) == TIM_CHANNEL_1))) \
AnnaBridge 126:abea610beb85 11201 || \
AnnaBridge 126:abea610beb85 11202 (((__INSTANCE__) == TIM12) && \
AnnaBridge 126:abea610beb85 11203 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 126:abea610beb85 11204 ((__CHANNEL__) == TIM_CHANNEL_2))) \
AnnaBridge 126:abea610beb85 11205 || \
AnnaBridge 126:abea610beb85 11206 (((__INSTANCE__) == TIM13) && \
AnnaBridge 126:abea610beb85 11207 (((__CHANNEL__) == TIM_CHANNEL_1))) \
AnnaBridge 126:abea610beb85 11208 || \
AnnaBridge 126:abea610beb85 11209 (((__INSTANCE__) == TIM14) && \
AnnaBridge 126:abea610beb85 11210 (((__CHANNEL__) == TIM_CHANNEL_1))))
AnnaBridge 126:abea610beb85 11211
AnnaBridge 126:abea610beb85 11212 /************ TIM Instances : complementary output(s) available ***************/
AnnaBridge 126:abea610beb85 11213 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
AnnaBridge 126:abea610beb85 11214 ((((__INSTANCE__) == TIM1) && \
AnnaBridge 126:abea610beb85 11215 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 126:abea610beb85 11216 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 126:abea610beb85 11217 ((__CHANNEL__) == TIM_CHANNEL_3))) \
AnnaBridge 126:abea610beb85 11218 || \
AnnaBridge 126:abea610beb85 11219 (((__INSTANCE__) == TIM8) && \
AnnaBridge 126:abea610beb85 11220 (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 126:abea610beb85 11221 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 126:abea610beb85 11222 ((__CHANNEL__) == TIM_CHANNEL_3))))
AnnaBridge 126:abea610beb85 11223
AnnaBridge 126:abea610beb85 11224 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
AnnaBridge 126:abea610beb85 11225 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
AnnaBridge 126:abea610beb85 11226 (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11227 ((__INSTANCE__) == TIM8) )
AnnaBridge 126:abea610beb85 11228
AnnaBridge 126:abea610beb85 11229 /****************** TIM Instances : supporting synchronization ****************/
AnnaBridge 126:abea610beb85 11230 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
AnnaBridge 126:abea610beb85 11231 (((__INSTANCE__) == TIM1) || \
AnnaBridge 126:abea610beb85 11232 ((__INSTANCE__) == TIM2) || \
AnnaBridge 126:abea610beb85 11233 ((__INSTANCE__) == TIM3) || \
AnnaBridge 126:abea610beb85 11234 ((__INSTANCE__) == TIM4) || \
AnnaBridge 126:abea610beb85 11235 ((__INSTANCE__) == TIM5) || \
AnnaBridge 126:abea610beb85 11236 ((__INSTANCE__) == TIM6) || \
AnnaBridge 126:abea610beb85 11237 ((__INSTANCE__) == TIM7) || \
AnnaBridge 126:abea610beb85 11238 ((__INSTANCE__) == TIM8))
AnnaBridge 126:abea610beb85 11239
AnnaBridge 126:abea610beb85 11240 /******************** USART Instances : Synchronous mode **********************/
AnnaBridge 126:abea610beb85 11241 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 126:abea610beb85 11242 ((__INSTANCE__) == USART2) || \
AnnaBridge 126:abea610beb85 11243 ((__INSTANCE__) == USART3) || \
AnnaBridge 126:abea610beb85 11244 ((__INSTANCE__) == USART6))
AnnaBridge 126:abea610beb85 11245
AnnaBridge 126:abea610beb85 11246 /******************** UART Instances : Asynchronous mode **********************/
AnnaBridge 126:abea610beb85 11247 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 126:abea610beb85 11248 ((__INSTANCE__) == USART2) || \
AnnaBridge 126:abea610beb85 11249 ((__INSTANCE__) == USART3) || \
AnnaBridge 126:abea610beb85 11250 ((__INSTANCE__) == UART4) || \
AnnaBridge 126:abea610beb85 11251 ((__INSTANCE__) == UART5) || \
AnnaBridge 126:abea610beb85 11252 ((__INSTANCE__) == USART6) || \
AnnaBridge 126:abea610beb85 11253 ((__INSTANCE__) == UART7) || \
AnnaBridge 126:abea610beb85 11254 ((__INSTANCE__) == UART8))
AnnaBridge 126:abea610beb85 11255
AnnaBridge 126:abea610beb85 11256 /****************** UART Instances : Driver Enable *****************/
AnnaBridge 126:abea610beb85 11257 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 126:abea610beb85 11258 ((__INSTANCE__) == USART2) || \
AnnaBridge 126:abea610beb85 11259 ((__INSTANCE__) == USART3) || \
AnnaBridge 126:abea610beb85 11260 ((__INSTANCE__) == UART4) || \
AnnaBridge 126:abea610beb85 11261 ((__INSTANCE__) == UART5) || \
AnnaBridge 126:abea610beb85 11262 ((__INSTANCE__) == USART6) || \
AnnaBridge 126:abea610beb85 11263 ((__INSTANCE__) == UART7) || \
AnnaBridge 126:abea610beb85 11264 ((__INSTANCE__) == UART8))
AnnaBridge 126:abea610beb85 11265
AnnaBridge 126:abea610beb85 11266 /****************** UART Instances : Hardware Flow control ********************/
AnnaBridge 126:abea610beb85 11267 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 126:abea610beb85 11268 ((__INSTANCE__) == USART2) || \
AnnaBridge 126:abea610beb85 11269 ((__INSTANCE__) == USART3) || \
AnnaBridge 126:abea610beb85 11270 ((__INSTANCE__) == UART4) || \
AnnaBridge 126:abea610beb85 11271 ((__INSTANCE__) == UART5) || \
AnnaBridge 126:abea610beb85 11272 ((__INSTANCE__) == USART6) || \
AnnaBridge 126:abea610beb85 11273 ((__INSTANCE__) == UART7) || \
AnnaBridge 126:abea610beb85 11274 ((__INSTANCE__) == UART8))
AnnaBridge 126:abea610beb85 11275
AnnaBridge 126:abea610beb85 11276 /********************* UART Instances : Smart card mode ***********************/
AnnaBridge 126:abea610beb85 11277 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 126:abea610beb85 11278 ((__INSTANCE__) == USART2) || \
AnnaBridge 126:abea610beb85 11279 ((__INSTANCE__) == USART3) || \
AnnaBridge 126:abea610beb85 11280 ((__INSTANCE__) == USART6))
AnnaBridge 126:abea610beb85 11281
AnnaBridge 126:abea610beb85 11282 /*********************** UART Instances : IRDA mode ***************************/
AnnaBridge 126:abea610beb85 11283 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
AnnaBridge 126:abea610beb85 11284 ((__INSTANCE__) == USART2) || \
AnnaBridge 126:abea610beb85 11285 ((__INSTANCE__) == USART3) || \
AnnaBridge 126:abea610beb85 11286 ((__INSTANCE__) == UART4) || \
AnnaBridge 126:abea610beb85 11287 ((__INSTANCE__) == UART5) || \
AnnaBridge 126:abea610beb85 11288 ((__INSTANCE__) == USART6) || \
AnnaBridge 126:abea610beb85 11289 ((__INSTANCE__) == UART7) || \
AnnaBridge 126:abea610beb85 11290 ((__INSTANCE__) == UART8))
AnnaBridge 126:abea610beb85 11291
AnnaBridge 126:abea610beb85 11292 /****************************** IWDG Instances ********************************/
AnnaBridge 126:abea610beb85 11293 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
AnnaBridge 126:abea610beb85 11294
AnnaBridge 126:abea610beb85 11295 /****************************** WWDG Instances ********************************/
AnnaBridge 126:abea610beb85 11296 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
AnnaBridge 126:abea610beb85 11297
AnnaBridge 126:abea610beb85 11298
AnnaBridge 126:abea610beb85 11299 /******************************************************************************/
AnnaBridge 126:abea610beb85 11300 /* For a painless codes migration between the STM32F7xx device product */
AnnaBridge 126:abea610beb85 11301 /* lines, the aliases defined below are put in place to overcome the */
AnnaBridge 126:abea610beb85 11302 /* differences in the interrupt handlers and IRQn definitions. */
AnnaBridge 126:abea610beb85 11303 /* No need to update developed interrupt code when moving across */
AnnaBridge 126:abea610beb85 11304 /* product lines within the same STM32F7 Family */
AnnaBridge 126:abea610beb85 11305 /******************************************************************************/
AnnaBridge 126:abea610beb85 11306
AnnaBridge 126:abea610beb85 11307 /* Aliases for __IRQn */
AnnaBridge 126:abea610beb85 11308 #define HASH_RNG_IRQn RNG_IRQn
AnnaBridge 126:abea610beb85 11309
AnnaBridge 126:abea610beb85 11310 /* Aliases for __IRQHandler */
AnnaBridge 126:abea610beb85 11311 #define HASH_RNG_IRQHandler RNG_IRQHandler
AnnaBridge 126:abea610beb85 11312
AnnaBridge 126:abea610beb85 11313 /**
AnnaBridge 126:abea610beb85 11314 * @}
AnnaBridge 126:abea610beb85 11315 */
AnnaBridge 126:abea610beb85 11316
AnnaBridge 126:abea610beb85 11317 /**
AnnaBridge 126:abea610beb85 11318 * @}
AnnaBridge 126:abea610beb85 11319 */
AnnaBridge 126:abea610beb85 11320
AnnaBridge 126:abea610beb85 11321 /**
AnnaBridge 126:abea610beb85 11322 * @}
AnnaBridge 126:abea610beb85 11323 */
AnnaBridge 126:abea610beb85 11324
AnnaBridge 126:abea610beb85 11325 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 11326 }
AnnaBridge 126:abea610beb85 11327 #endif /* __cplusplus */
AnnaBridge 126:abea610beb85 11328
AnnaBridge 126:abea610beb85 11329 #endif /* __STM32F769xx_H */
AnnaBridge 126:abea610beb85 11330
AnnaBridge 126:abea610beb85 11331
AnnaBridge 126:abea610beb85 11332 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/