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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_L053R8/stm32l0xx_hal_adc.h@119:aae6fcc7d9bb, 2016-04-27 (annotated)

Committer:
Kojto
Date:
Wed Apr 27 12:10:56 2016 -0500
Revision:
119:aae6fcc7d9bb
Parent:
96:487b796308b0 
Release 119 of the mbed library



Changes:

- new targets - EFM32PG_STK3401, NUCLEO_L031K6

- ST - hwflwctl support for NUCLEO_L476RG

     - Update STM32CUBE_L0 from v1.2 to v1.5

     - STM32F7 - bugfix - The weak function HAL_Delay is overwritten to use us ticker API.

- Maxim - Fixing the send break for the MAXWSNENV and MAX32600MBED

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l0xx_hal_adc.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
Kojto 119:aae6fcc7d9bb 5 * @version V1.5.0
Kojto 119:aae6fcc7d9bb 6 * @date 8-January-2016
bogdanm 84:0b3ab51c8877 7 * @brief This file contains all the functions prototypes for the ADC firmware
bogdanm 84:0b3ab51c8877 8 * library.
bogdanm 84:0b3ab51c8877 9 ******************************************************************************
bogdanm 84:0b3ab51c8877 10 * @attention
bogdanm 84:0b3ab51c8877 11 *
Kojto 119:aae6fcc7d9bb 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 13 *
bogdanm 84:0b3ab51c8877 14 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 15 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 17 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 20 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 22 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 23 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 24 *
bogdanm 84:0b3ab51c8877 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 35 *
bogdanm 84:0b3ab51c8877 36 ******************************************************************************
bogdanm 84:0b3ab51c8877 37 */
bogdanm 84:0b3ab51c8877 38
bogdanm 84:0b3ab51c8877 39 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 84:0b3ab51c8877 40 #ifndef __STM32L0xx_ADC_H
bogdanm 84:0b3ab51c8877 41 #define __STM32L0xx_ADC_H
bogdanm 84:0b3ab51c8877 42
bogdanm 84:0b3ab51c8877 43 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 44 extern "C" {
bogdanm 84:0b3ab51c8877 45 #endif
bogdanm 84:0b3ab51c8877 46
bogdanm 84:0b3ab51c8877 47 /* Includes ------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 48 #include "stm32l0xx_hal_def.h"
bogdanm 84:0b3ab51c8877 49
bogdanm 84:0b3ab51c8877 50 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 84:0b3ab51c8877 51 * @{
bogdanm 84:0b3ab51c8877 52 */
bogdanm 84:0b3ab51c8877 53
Kojto 119:aae6fcc7d9bb 54 /** @defgroup ADC ADC
bogdanm 84:0b3ab51c8877 55 * @{
bogdanm 84:0b3ab51c8877 56 */
bogdanm 84:0b3ab51c8877 57
Kojto 119:aae6fcc7d9bb 58 /** @defgroup ADC_Exported_Types ADC Exported Types
Kojto 119:aae6fcc7d9bb 59 * @{
Kojto 119:aae6fcc7d9bb 60 */
Kojto 119:aae6fcc7d9bb 61
bogdanm 84:0b3ab51c8877 62 /* Exported types ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 63 /**
Kojto 119:aae6fcc7d9bb 64 * @brief HAL ADC state machine: ADC states definition (bitfields)
bogdanm 84:0b3ab51c8877 65 */
Kojto 119:aae6fcc7d9bb 66 /* States of ADC global scope */
Kojto 119:aae6fcc7d9bb 67 #define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
Kojto 119:aae6fcc7d9bb 68 #define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
Kojto 119:aae6fcc7d9bb 69 #define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
Kojto 119:aae6fcc7d9bb 70 #define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
Kojto 119:aae6fcc7d9bb 71
Kojto 119:aae6fcc7d9bb 72 /* States of ADC errors */
Kojto 119:aae6fcc7d9bb 73 #define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
Kojto 119:aae6fcc7d9bb 74 #define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
Kojto 119:aae6fcc7d9bb 75 #define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
Kojto 119:aae6fcc7d9bb 76
Kojto 119:aae6fcc7d9bb 77 /* States of ADC group regular */
Kojto 119:aae6fcc7d9bb 78 #define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
Kojto 119:aae6fcc7d9bb 79 external trigger, low power auto power-on, multimode ADC master control) */
Kojto 119:aae6fcc7d9bb 80 #define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
Kojto 119:aae6fcc7d9bb 81 #define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
Kojto 119:aae6fcc7d9bb 82 #define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F0 device: End Of Sampling flag raised */
Kojto 119:aae6fcc7d9bb 83
Kojto 119:aae6fcc7d9bb 84 /* States of ADC group injected */
Kojto 119:aae6fcc7d9bb 85 #define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
Kojto 119:aae6fcc7d9bb 86 external trigger, low power auto power-on, multimode ADC master control) */
Kojto 119:aae6fcc7d9bb 87 #define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Not available on STM32F0 device: Conversion data available on group injected */
Kojto 119:aae6fcc7d9bb 88 #define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */
Kojto 119:aae6fcc7d9bb 89
Kojto 119:aae6fcc7d9bb 90 /* States of ADC analog watchdogs */
Kojto 119:aae6fcc7d9bb 91 #define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
Kojto 119:aae6fcc7d9bb 92 #define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */
Kojto 119:aae6fcc7d9bb 93 #define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */
Kojto 119:aae6fcc7d9bb 94
Kojto 119:aae6fcc7d9bb 95 /* States of ADC multi-mode */
Kojto 119:aae6fcc7d9bb 96 #define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */
bogdanm 84:0b3ab51c8877 97
bogdanm 84:0b3ab51c8877 98
bogdanm 84:0b3ab51c8877 99 /**
bogdanm 84:0b3ab51c8877 100 * @brief ADC Oversampler structure definition
bogdanm 84:0b3ab51c8877 101 */
bogdanm 84:0b3ab51c8877 102 typedef struct
bogdanm 84:0b3ab51c8877 103 {
bogdanm 84:0b3ab51c8877 104 uint32_t Ratio; /*!< Configures the oversampling ratio.
bogdanm 84:0b3ab51c8877 105 This parameter can be a value of @ref ADC_Oversampling_Ratio */
bogdanm 84:0b3ab51c8877 106 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
bogdanm 84:0b3ab51c8877 107 This parameter can be a value of @ref ADC_Right_Bit_Shift */
bogdanm 84:0b3ab51c8877 108 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode
bogdanm 84:0b3ab51c8877 109 This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
bogdanm 84:0b3ab51c8877 110
bogdanm 84:0b3ab51c8877 111 }ADC_OversamplingTypeDef;
bogdanm 84:0b3ab51c8877 112
bogdanm 84:0b3ab51c8877 113 /**
bogdanm 84:0b3ab51c8877 114 * @brief ADC Init structure definition
bogdanm 84:0b3ab51c8877 115 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned by the ADC state.
bogdanm 84:0b3ab51c8877 116 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
bogdanm 84:0b3ab51c8877 117 * without error reporting (as it can be the expected behaviour in case of intended action to update antother parameter (which fullfills the ADC state condition) on the fly).
bogdanm 84:0b3ab51c8877 118 */
bogdanm 84:0b3ab51c8877 119 typedef struct
bogdanm 84:0b3ab51c8877 120 {
bogdanm 84:0b3ab51c8877 121 uint32_t OversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled
bogdanm 84:0b3ab51c8877 122 This parameter can be set to ENABLE or DISABLE.
bogdanm 84:0b3ab51c8877 123 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 84:0b3ab51c8877 124 ADC_OversamplingTypeDef Oversample; /*!< Specifies the Oversampling parameters
bogdanm 84:0b3ab51c8877 125 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 84:0b3ab51c8877 126 uint32_t ClockPrescaler; /*!< Selects the ADC clock frequency.
bogdanm 84:0b3ab51c8877 127 This parameter can be a value of @ref ADC_ClockPrescaler
Kojto 119:aae6fcc7d9bb 128 Note: This parameter can be modified only if ADC is disabled.
Kojto 119:aae6fcc7d9bb 129 Note: In case of Synchronous clock mode divided by 1, this configuration must be enabled only
Kojto 119:aae6fcc7d9bb 130 if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC
Kojto 119:aae6fcc7d9bb 131 must be bypassed and the system clock must by 50% duty cycle). Refer to reference manual for details */
bogdanm 84:0b3ab51c8877 132 uint32_t Resolution; /*!< Configures the ADC resolution mode.
bogdanm 84:0b3ab51c8877 133 This parameter can be a value of @ref ADC_Resolution
bogdanm 84:0b3ab51c8877 134 Note: This parameter can be modified only if ADC is disabled. */
bogdanm 84:0b3ab51c8877 135 uint32_t SamplingTime; /*!< The sample time value to be set for all channels.
bogdanm 92:4fc01daae5a5 136 This parameter can be a value of @ref ADC_sampling_times
bogdanm 92:4fc01daae5a5 137 Note: This parameter can be modified only if there is no conversion ongoing. */
Kojto 96:487b796308b0 138 uint32_t ScanConvMode; /*!< The scan sequence direction.
Kojto 119:aae6fcc7d9bb 139 If several channels are set: Conversions are performed in sequence mode
Kojto 119:aae6fcc7d9bb 140 (ranks defined by each channel number: channel 0 fixed on rank 0,
Kojto 119:aae6fcc7d9bb 141 channel 1 fixed on rank1, ...).
Kojto 96:487b796308b0 142 This parameter can be a value of @ref ADC_Scan_mode
bogdanm 84:0b3ab51c8877 143 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 84:0b3ab51c8877 144 uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
bogdanm 92:4fc01daae5a5 145 This parameter can be a value of @ref ADC_data_align
bogdanm 84:0b3ab51c8877 146 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 84:0b3ab51c8877 147 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
bogdanm 84:0b3ab51c8877 148 This parameter can be set to ENABLE or DISABLE.
bogdanm 84:0b3ab51c8877 149 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 84:0b3ab51c8877 150 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed
bogdanm 84:0b3ab51c8877 151 in Complete-sequence/Discontinuous-sequence.
bogdanm 84:0b3ab51c8877 152 Discontinuous mode can be enabled only if continuous mode is disabled.
bogdanm 84:0b3ab51c8877 153 This parameter can be set to ENABLE or DISABLE.
bogdanm 84:0b3ab51c8877 154 Note: This parameter can be modified only if there is no conversion is ongoing. */
Kojto 119:aae6fcc7d9bb 155 uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion.
Kojto 119:aae6fcc7d9bb 156 If set to ADC_SOFTWARE_START, external triggers are disabled.
Kojto 119:aae6fcc7d9bb 157 This parameter can be a value of @ref ADC_External_trigger_Source
bogdanm 84:0b3ab51c8877 158 Note: This parameter can be modified only if there is no conversion is ongoing. */
Kojto 119:aae6fcc7d9bb 159 uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger.
Kojto 119:aae6fcc7d9bb 160 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
Kojto 119:aae6fcc7d9bb 161 This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge
bogdanm 84:0b3ab51c8877 162 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 84:0b3ab51c8877 163 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
bogdanm 84:0b3ab51c8877 164 or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
bogdanm 84:0b3ab51c8877 165 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer max pointer is reached.
bogdanm 84:0b3ab51c8877 166 This parameter can be set to ENABLE or DISABLE.
bogdanm 84:0b3ab51c8877 167 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 84:0b3ab51c8877 168 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion polling and interruption:
bogdanm 84:0b3ab51c8877 169 end of single channel conversion or end of channels conversions sequence.
bogdanm 92:4fc01daae5a5 170 This parameter can be a value of @ref ADC_EOCSelection */
bogdanm 84:0b3ab51c8877 171 uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten
bogdanm 84:0b3ab51c8877 172 This parameter has an effect on regular channels only, including in DMA mode.
bogdanm 92:4fc01daae5a5 173 This parameter can be a value of @ref ADC_Overrun
bogdanm 84:0b3ab51c8877 174 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 84:0b3ab51c8877 175 uint32_t LowPowerAutoWait; /*!< Specifies the usage of dynamic low power Auto Delay: new conversion start only
bogdanm 84:0b3ab51c8877 176 when the previous conversion (for regular channel) is completed.
bogdanm 84:0b3ab51c8877 177 This avoids risk of overrun for low frequency application.
bogdanm 84:0b3ab51c8877 178 This parameter can be set to ENABLE or DISABLE.
bogdanm 84:0b3ab51c8877 179 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 84:0b3ab51c8877 180 uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz,
bogdanm 84:0b3ab51c8877 181 it is mandatory to first enable the Low Frequency Mode.
bogdanm 84:0b3ab51c8877 182 This parameter can be set to ENABLE or DISABLE.
bogdanm 84:0b3ab51c8877 183 Note: This parameter can be modified only if there is no conversion is ongoing. */
Kojto 96:487b796308b0 184 uint32_t LowPowerAutoPowerOff; /*!< When setting the AutoOff feature, the ADC is always powered off when not converting and automatically
bogdanm 84:0b3ab51c8877 185 wakes-up when a conversion is started (by software or hardware trigger).
bogdanm 84:0b3ab51c8877 186 This parameter can be set to ENABLE or DISABLE.
bogdanm 84:0b3ab51c8877 187 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 84:0b3ab51c8877 188 }ADC_InitTypeDef;
bogdanm 84:0b3ab51c8877 189
bogdanm 84:0b3ab51c8877 190 /**
bogdanm 84:0b3ab51c8877 191 * @brief ADC handle Structure definition
bogdanm 84:0b3ab51c8877 192 */
Kojto 119:aae6fcc7d9bb 193 typedef struct
bogdanm 84:0b3ab51c8877 194 {
bogdanm 84:0b3ab51c8877 195 ADC_TypeDef *Instance; /*!< Register base address */
bogdanm 84:0b3ab51c8877 196
bogdanm 84:0b3ab51c8877 197 ADC_InitTypeDef Init; /*!< ADC required parameters */
bogdanm 84:0b3ab51c8877 198
bogdanm 84:0b3ab51c8877 199 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
bogdanm 84:0b3ab51c8877 200
bogdanm 84:0b3ab51c8877 201 HAL_LockTypeDef Lock; /*!< ADC locking object */
bogdanm 84:0b3ab51c8877 202
Kojto 119:aae6fcc7d9bb 203 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
bogdanm 84:0b3ab51c8877 204
bogdanm 84:0b3ab51c8877 205 __IO uint32_t ErrorCode; /*!< ADC Error code */
bogdanm 84:0b3ab51c8877 206 }ADC_HandleTypeDef;
bogdanm 84:0b3ab51c8877 207
bogdanm 84:0b3ab51c8877 208 /**
bogdanm 84:0b3ab51c8877 209 * @brief ADC Configuration regular Channel structure definition
bogdanm 84:0b3ab51c8877 210 */
bogdanm 84:0b3ab51c8877 211 typedef struct
bogdanm 84:0b3ab51c8877 212 {
bogdanm 84:0b3ab51c8877 213 uint32_t Channel; /*!< the ADC channel to configure
bogdanm 84:0b3ab51c8877 214 This parameter can be a value of @ref ADC_channels */
Kojto 119:aae6fcc7d9bb 215
Kojto 119:aae6fcc7d9bb 216 uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
Kojto 119:aae6fcc7d9bb 217 On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number
Kojto 119:aae6fcc7d9bb 218 (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
Kojto 119:aae6fcc7d9bb 219 Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
Kojto 119:aae6fcc7d9bb 220 This parameter can be a value of @ref ADC_rank */
bogdanm 84:0b3ab51c8877 221 }ADC_ChannelConfTypeDef;
bogdanm 84:0b3ab51c8877 222
bogdanm 84:0b3ab51c8877 223
bogdanm 84:0b3ab51c8877 224 /**
bogdanm 84:0b3ab51c8877 225 * @brief ADC Configuration analog watchdog definition
bogdanm 84:0b3ab51c8877 226 */
bogdanm 84:0b3ab51c8877 227 typedef struct
bogdanm 84:0b3ab51c8877 228 {
bogdanm 84:0b3ab51c8877 229 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels.
bogdanm 92:4fc01daae5a5 230 This parameter can be a value of @ref ADC_analog_watchdog_mode */
bogdanm 84:0b3ab51c8877 231 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
bogdanm 84:0b3ab51c8877 232 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
bogdanm 92:4fc01daae5a5 233 This parameter can be a value of @ref ADC_channels */
bogdanm 84:0b3ab51c8877 234 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
bogdanm 84:0b3ab51c8877 235 This parameter can be set to ENABLE or DISABLE */
bogdanm 84:0b3ab51c8877 236 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm 84:0b3ab51c8877 237 Depending of ADC resolution selected (12, 10, 8 or 6 bits),
bogdanm 84:0b3ab51c8877 238 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
bogdanm 84:0b3ab51c8877 239 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm 84:0b3ab51c8877 240 Depending of ADC resolution selected (12, 10, 8 or 6 bits),
bogdanm 84:0b3ab51c8877 241 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
bogdanm 84:0b3ab51c8877 242 }ADC_AnalogWDGConfTypeDef;
bogdanm 84:0b3ab51c8877 243
Kojto 119:aae6fcc7d9bb 244 /**
Kojto 119:aae6fcc7d9bb 245 * @}
Kojto 119:aae6fcc7d9bb 246 */
Kojto 119:aae6fcc7d9bb 247
bogdanm 84:0b3ab51c8877 248
bogdanm 84:0b3ab51c8877 249 /* Exported constants --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 250
Kojto 119:aae6fcc7d9bb 251 /** @defgroup ADC_Exported_Constants ADC Exported Constants
bogdanm 84:0b3ab51c8877 252 * @{
bogdanm 84:0b3ab51c8877 253 */
bogdanm 84:0b3ab51c8877 254
Kojto 119:aae6fcc7d9bb 255 /** @defgroup ADC_Error_Code ADC Error Code
bogdanm 84:0b3ab51c8877 256 * @{
bogdanm 84:0b3ab51c8877 257 */
bogdanm 84:0b3ab51c8877 258 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
bogdanm 84:0b3ab51c8877 259 #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
bogdanm 84:0b3ab51c8877 260 enable/disable, erroneous state */
Kojto 96:487b796308b0 261 #define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< OVR error */
Kojto 119:aae6fcc7d9bb 262 #define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
bogdanm 84:0b3ab51c8877 263 /**
bogdanm 84:0b3ab51c8877 264 * @}
bogdanm 84:0b3ab51c8877 265 */
bogdanm 84:0b3ab51c8877 266
Kojto 119:aae6fcc7d9bb 267 /** @defgroup ADC_TimeOut_Values ADC TimeOut Values
bogdanm 84:0b3ab51c8877 268 * @{
bogdanm 84:0b3ab51c8877 269 */
bogdanm 84:0b3ab51c8877 270
bogdanm 84:0b3ab51c8877 271 /* Fixed timeout values for ADC calibration, enable settling time, disable */
bogdanm 84:0b3ab51c8877 272 /* settling time. */
bogdanm 84:0b3ab51c8877 273 /* Values defined to be higher than worst cases: low clocks freq, */
bogdanm 84:0b3ab51c8877 274 /* maximum prescalers. */
bogdanm 84:0b3ab51c8877 275 /* Unit: ms */
bogdanm 84:0b3ab51c8877 276 #define ADC_ENABLE_TIMEOUT 10
bogdanm 84:0b3ab51c8877 277 #define ADC_DISABLE_TIMEOUT 10
bogdanm 84:0b3ab51c8877 278 #define ADC_STOP_CONVERSION_TIMEOUT 10
bogdanm 84:0b3ab51c8877 279
bogdanm 84:0b3ab51c8877 280 /* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */
bogdanm 84:0b3ab51c8877 281 /* the minimum number of CPU cycles to fulfill this delay */
bogdanm 84:0b3ab51c8877 282 #define ADC_DELAY_10US_MIN_CPU_CYCLES 1800
bogdanm 84:0b3ab51c8877 283 /**
bogdanm 84:0b3ab51c8877 284 * @}
bogdanm 84:0b3ab51c8877 285 */
bogdanm 84:0b3ab51c8877 286
Kojto 119:aae6fcc7d9bb 287 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
bogdanm 84:0b3ab51c8877 288 * @{
bogdanm 84:0b3ab51c8877 289 */
bogdanm 84:0b3ab51c8877 290 #define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode divided by 1 */
bogdanm 84:0b3ab51c8877 291 #define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 84:0b3ab51c8877 292 #define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 84:0b3ab51c8877 293 #define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 84:0b3ab51c8877 294 #define ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 84:0b3ab51c8877 295 #define ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 84:0b3ab51c8877 296 #define ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 84:0b3ab51c8877 297 #define ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 84:0b3ab51c8877 298 #define ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 84:0b3ab51c8877 299 #define ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 84:0b3ab51c8877 300 #define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 84:0b3ab51c8877 301 #define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 84:0b3ab51c8877 302
Kojto 119:aae6fcc7d9bb 303 #define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 1
Kojto 96:487b796308b0 304 This configuration must be enabled only if PCLK has a 50%
Kojto 96:487b796308b0 305 duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
Kojto 96:487b796308b0 306 must by 50% duty cycle)*/
Kojto 119:aae6fcc7d9bb 307 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 2 */
Kojto 119:aae6fcc7d9bb 308 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< Synchronous clock mode divided by 4 */
bogdanm 84:0b3ab51c8877 309
bogdanm 84:0b3ab51c8877 310 /**
bogdanm 84:0b3ab51c8877 311 * @}
bogdanm 84:0b3ab51c8877 312 */
bogdanm 84:0b3ab51c8877 313
Kojto 119:aae6fcc7d9bb 314 /** @defgroup ADC_Resolution ADC Resolution
bogdanm 84:0b3ab51c8877 315 * @{
bogdanm 84:0b3ab51c8877 316 */
Kojto 96:487b796308b0 317 #define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
Kojto 96:487b796308b0 318 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */
Kojto 96:487b796308b0 319 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */
Kojto 96:487b796308b0 320 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */
bogdanm 84:0b3ab51c8877 321 /**
bogdanm 84:0b3ab51c8877 322 * @}
bogdanm 84:0b3ab51c8877 323 */
bogdanm 84:0b3ab51c8877 324
Kojto 119:aae6fcc7d9bb 325 /** @defgroup ADC_data_align ADC Data Align
bogdanm 84:0b3ab51c8877 326 * @{
bogdanm 84:0b3ab51c8877 327 */
bogdanm 84:0b3ab51c8877 328 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 329 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
bogdanm 84:0b3ab51c8877 330
bogdanm 84:0b3ab51c8877 331 /**
bogdanm 84:0b3ab51c8877 332 * @}
bogdanm 84:0b3ab51c8877 333 */
bogdanm 84:0b3ab51c8877 334
Kojto 96:487b796308b0 335 /** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group
bogdanm 84:0b3ab51c8877 336 * @{
bogdanm 84:0b3ab51c8877 337 */
Kojto 96:487b796308b0 338 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
Kojto 96:487b796308b0 339 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
Kojto 96:487b796308b0 340 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
Kojto 96:487b796308b0 341 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
Kojto 119:aae6fcc7d9bb 342 /**
Kojto 119:aae6fcc7d9bb 343 * @}
Kojto 119:aae6fcc7d9bb 344 */
bogdanm 84:0b3ab51c8877 345
Kojto 119:aae6fcc7d9bb 346 /** @defgroup ADC_EOCSelection ADC EOC Selection
Kojto 119:aae6fcc7d9bb 347 * @{
Kojto 119:aae6fcc7d9bb 348 */
Kojto 119:aae6fcc7d9bb 349 #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
Kojto 119:aae6fcc7d9bb 350 #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
Kojto 119:aae6fcc7d9bb 351 #define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
bogdanm 84:0b3ab51c8877 352 /**
bogdanm 84:0b3ab51c8877 353 * @}
bogdanm 84:0b3ab51c8877 354 */
bogdanm 84:0b3ab51c8877 355
Kojto 119:aae6fcc7d9bb 356 /** @defgroup ADC_Overrun ADC Overrun
bogdanm 84:0b3ab51c8877 357 * @{
Kojto 119:aae6fcc7d9bb 358 */
Kojto 119:aae6fcc7d9bb 359 #define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)
Kojto 119:aae6fcc7d9bb 360 #define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
bogdanm 84:0b3ab51c8877 361 /**
bogdanm 84:0b3ab51c8877 362 * @}
bogdanm 84:0b3ab51c8877 363 */
bogdanm 84:0b3ab51c8877 364
Kojto 119:aae6fcc7d9bb 365
Kojto 119:aae6fcc7d9bb 366 /** @defgroup ADC_rank ADC rank
bogdanm 84:0b3ab51c8877 367 * @{
bogdanm 84:0b3ab51c8877 368 */
Kojto 119:aae6fcc7d9bb 369 #define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
Kojto 119:aae6fcc7d9bb 370 #define ADC_RANK_NONE ((uint32_t)0x00001001) /*!< Disable the selected rank (selected channel) from sequencer */
bogdanm 84:0b3ab51c8877 371 /**
bogdanm 84:0b3ab51c8877 372 * @}
Kojto 119:aae6fcc7d9bb 373 */
bogdanm 84:0b3ab51c8877 374
bogdanm 84:0b3ab51c8877 375
Kojto 119:aae6fcc7d9bb 376 /** @defgroup ADC_channels ADC_Channels
bogdanm 84:0b3ab51c8877 377 * @{
bogdanm 84:0b3ab51c8877 378 */
bogdanm 84:0b3ab51c8877 379 #define ADC_CHANNEL_0 ((uint32_t)(ADC_CHSELR_CHSEL0))
bogdanm 84:0b3ab51c8877 380 #define ADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) | ADC_CFGR1_AWDCH_0)
bogdanm 84:0b3ab51c8877 381 #define ADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) | ADC_CFGR1_AWDCH_1)
bogdanm 84:0b3ab51c8877 382 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
bogdanm 84:0b3ab51c8877 383 #define ADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)| ADC_CFGR1_AWDCH_2)
bogdanm 84:0b3ab51c8877 384 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
bogdanm 84:0b3ab51c8877 385 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
bogdanm 84:0b3ab51c8877 386 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
bogdanm 84:0b3ab51c8877 387 #define ADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)| ADC_CFGR1_AWDCH_3)
bogdanm 84:0b3ab51c8877 388 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_0)
bogdanm 84:0b3ab51c8877 389 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1)
bogdanm 84:0b3ab51c8877 390 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
bogdanm 84:0b3ab51c8877 391 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2)
bogdanm 84:0b3ab51c8877 392 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
bogdanm 84:0b3ab51c8877 393 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
bogdanm 84:0b3ab51c8877 394 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
Kojto 119:aae6fcc7d9bb 395 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
bogdanm 84:0b3ab51c8877 396 #define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)| ADC_CFGR1_AWDCH_4)
Kojto 119:aae6fcc7d9bb 397 #endif
bogdanm 84:0b3ab51c8877 398 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_0)
bogdanm 84:0b3ab51c8877 399 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_1)
bogdanm 84:0b3ab51c8877 400
bogdanm 84:0b3ab51c8877 401 /* Internal channels */
Kojto 119:aae6fcc7d9bb 402 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
bogdanm 92:4fc01daae5a5 403 #define ADC_CHANNEL_VLCD ADC_CHANNEL_16
Kojto 119:aae6fcc7d9bb 404 #endif
bogdanm 84:0b3ab51c8877 405 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
bogdanm 92:4fc01daae5a5 406 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
bogdanm 84:0b3ab51c8877 407 /**
bogdanm 84:0b3ab51c8877 408 * @}
bogdanm 84:0b3ab51c8877 409 */
bogdanm 84:0b3ab51c8877 410
Kojto 119:aae6fcc7d9bb 411 /** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks
bogdanm 84:0b3ab51c8877 412 * @{
bogdanm 84:0b3ab51c8877 413 */
bogdanm 84:0b3ab51c8877 414 #define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFF)
bogdanm 84:0b3ab51c8877 415 #define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000)
bogdanm 84:0b3ab51c8877 416 /**
bogdanm 84:0b3ab51c8877 417 * @}
bogdanm 84:0b3ab51c8877 418 */
bogdanm 84:0b3ab51c8877 419
bogdanm 84:0b3ab51c8877 420
Kojto 119:aae6fcc7d9bb 421 /** @defgroup ADC_sampling_times ADC Sampling Cycles
bogdanm 84:0b3ab51c8877 422 * @{
bogdanm 84:0b3ab51c8877 423 */
bogdanm 84:0b3ab51c8877 424
bogdanm 84:0b3ab51c8877 425 #define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< ADC sampling time 1.5 cycle */
bogdanm 84:0b3ab51c8877 426 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /*!< ADC sampling time 7.5 CYCLES */
bogdanm 84:0b3ab51c8877 427 #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /*!< ADC sampling time 13.5 CYCLES */
bogdanm 84:0b3ab51c8877 428 #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 28.5 CYCLES */
bogdanm 84:0b3ab51c8877 429 #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /*!< ADC sampling time 41.5 CYCLES */
bogdanm 84:0b3ab51c8877 430 #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 55.5 CYCLES */
bogdanm 84:0b3ab51c8877 431 #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!< ADC sampling time 71.5 CYCLES */
bogdanm 84:0b3ab51c8877 432 #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /*!< ADC sampling time 239.5 CYCLES */
bogdanm 84:0b3ab51c8877 433 /**
bogdanm 84:0b3ab51c8877 434 * @}
bogdanm 84:0b3ab51c8877 435 */
bogdanm 84:0b3ab51c8877 436
Kojto 96:487b796308b0 437
Kojto 96:487b796308b0 438 /** @defgroup ADC_Scan_mode ADC Scan mode
bogdanm 84:0b3ab51c8877 439 * @{
Kojto 96:487b796308b0 440 */
Kojto 96:487b796308b0 441 /* Note: Scan mode values must be compatible with other STM32 devices having */
Kojto 96:487b796308b0 442 /* a configurable sequencer. */
Kojto 96:487b796308b0 443 /* Scan direction setting values are defined by taking in account */
Kojto 96:487b796308b0 444 /* already defined values for other STM32 devices: */
Kojto 96:487b796308b0 445 /* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */
Kojto 96:487b796308b0 446 /* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */
Kojto 96:487b796308b0 447 /* Scan direction forward is considered as default setting equivalent */
Kojto 96:487b796308b0 448 /* to scan enable. */
Kojto 96:487b796308b0 449 /* Scan direction backward is considered as additional setting. */
Kojto 96:487b796308b0 450 /* In case of migration from another STM32 device, the user will be */
Kojto 96:487b796308b0 451 /* warned of change of setting choices with assert check. */
Kojto 96:487b796308b0 452 #define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001) /*!< Scan direction forward: from channel 0 to channel 18 */
Kojto 96:487b796308b0 453 #define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002) /*!< Scan direction backward: from channel 18 to channel 0 */
bogdanm 84:0b3ab51c8877 454
Kojto 96:487b796308b0 455 #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
bogdanm 84:0b3ab51c8877 456 /**
bogdanm 84:0b3ab51c8877 457 * @}
bogdanm 84:0b3ab51c8877 458 */
bogdanm 84:0b3ab51c8877 459
Kojto 119:aae6fcc7d9bb 460 /** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio
bogdanm 84:0b3ab51c8877 461 * @{
bogdanm 84:0b3ab51c8877 462 */
bogdanm 84:0b3ab51c8877 463
bogdanm 84:0b3ab51c8877 464 #define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /*!< ADC Oversampling ratio 2x */
bogdanm 84:0b3ab51c8877 465 #define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004) /*!< ADC Oversampling ratio 4x */
bogdanm 84:0b3ab51c8877 466 #define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008) /*!< ADC Oversampling ratio 8x */
bogdanm 84:0b3ab51c8877 467 #define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000C) /*!< ADC Oversampling ratio 16x */
bogdanm 84:0b3ab51c8877 468 #define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010) /*!< ADC Oversampling ratio 32x */
bogdanm 84:0b3ab51c8877 469 #define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014) /*!< ADC Oversampling ratio 64x */
bogdanm 84:0b3ab51c8877 470 #define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018) /*!< ADC Oversampling ratio 128x */
bogdanm 84:0b3ab51c8877 471 #define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001C) /*!< ADC Oversampling ratio 256x */
bogdanm 84:0b3ab51c8877 472 /**
bogdanm 84:0b3ab51c8877 473 * @}
bogdanm 84:0b3ab51c8877 474 */
bogdanm 84:0b3ab51c8877 475
Kojto 119:aae6fcc7d9bb 476 /** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift
bogdanm 84:0b3ab51c8877 477 * @{
bogdanm 84:0b3ab51c8877 478 */
bogdanm 84:0b3ab51c8877 479 #define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */
bogdanm 84:0b3ab51c8877 480 #define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020) /*!< ADC 1 bit shift for oversampling */
bogdanm 84:0b3ab51c8877 481 #define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040) /*!< ADC 2 bits shift for oversampling */
bogdanm 84:0b3ab51c8877 482 #define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060) /*!< ADC 3 bits shift for oversampling */
bogdanm 84:0b3ab51c8877 483 #define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080) /*!< ADC 4 bits shift for oversampling */
bogdanm 84:0b3ab51c8877 484 #define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0) /*!< ADC 5 bits shift for oversampling */
bogdanm 84:0b3ab51c8877 485 #define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0) /*!< ADC 6 bits shift for oversampling */
bogdanm 84:0b3ab51c8877 486 #define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0) /*!< ADC 7 bits shift for oversampling */
bogdanm 84:0b3ab51c8877 487 #define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100) /*!< ADC 8 bits shift for oversampling */
bogdanm 84:0b3ab51c8877 488 /**
bogdanm 84:0b3ab51c8877 489 * @}
bogdanm 84:0b3ab51c8877 490 */
bogdanm 84:0b3ab51c8877 491
Kojto 119:aae6fcc7d9bb 492 /** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode
bogdanm 84:0b3ab51c8877 493 * @{
bogdanm 84:0b3ab51c8877 494 */
bogdanm 84:0b3ab51c8877 495 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */
bogdanm 84:0b3ab51c8877 496 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200) /*!< ADC No bit shift for oversampling */
bogdanm 84:0b3ab51c8877 497 /**
bogdanm 84:0b3ab51c8877 498 * @}
bogdanm 84:0b3ab51c8877 499 */
bogdanm 84:0b3ab51c8877 500
Kojto 119:aae6fcc7d9bb 501 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
bogdanm 84:0b3ab51c8877 502 * @{
bogdanm 84:0b3ab51c8877 503 */
bogdanm 84:0b3ab51c8877 504 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
bogdanm 84:0b3ab51c8877 505 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
bogdanm 84:0b3ab51c8877 506 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
bogdanm 84:0b3ab51c8877 507 /**
bogdanm 84:0b3ab51c8877 508 * @}
bogdanm 84:0b3ab51c8877 509 */
bogdanm 84:0b3ab51c8877 510
Kojto 119:aae6fcc7d9bb 511 /** @defgroup ADC_conversion_type ADC Conversion Group
bogdanm 84:0b3ab51c8877 512 * @{
bogdanm 84:0b3ab51c8877 513 */
Kojto 96:487b796308b0 514 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
bogdanm 84:0b3ab51c8877 515 /**
bogdanm 84:0b3ab51c8877 516 * @}
bogdanm 84:0b3ab51c8877 517 */
bogdanm 84:0b3ab51c8877 518
Kojto 119:aae6fcc7d9bb 519 /** @defgroup ADC_Event_type ADC Event
bogdanm 84:0b3ab51c8877 520 * @{
bogdanm 84:0b3ab51c8877 521 */
Kojto 96:487b796308b0 522 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
Kojto 96:487b796308b0 523 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
bogdanm 84:0b3ab51c8877 524 /**
bogdanm 84:0b3ab51c8877 525 * @}
bogdanm 84:0b3ab51c8877 526 */
bogdanm 84:0b3ab51c8877 527
Kojto 119:aae6fcc7d9bb 528 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition
bogdanm 84:0b3ab51c8877 529 * @{
bogdanm 84:0b3ab51c8877 530 */
bogdanm 84:0b3ab51c8877 531 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready (ADRDY) interrupt source */
bogdanm 84:0b3ab51c8877 532 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */
bogdanm 84:0b3ab51c8877 533 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */
bogdanm 84:0b3ab51c8877 534 #define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */
bogdanm 84:0b3ab51c8877 535 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
bogdanm 84:0b3ab51c8877 536 #define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog 1 interrupt source */
bogdanm 84:0b3ab51c8877 537 #define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */
bogdanm 84:0b3ab51c8877 538 /**
bogdanm 84:0b3ab51c8877 539 * @}
bogdanm 84:0b3ab51c8877 540 */
bogdanm 84:0b3ab51c8877 541
bogdanm 84:0b3ab51c8877 542
bogdanm 84:0b3ab51c8877 543
Kojto 119:aae6fcc7d9bb 544 /** @defgroup ADC_flags_definition ADC Flags Definition
bogdanm 84:0b3ab51c8877 545 * @{
bogdanm 84:0b3ab51c8877 546 */
bogdanm 84:0b3ab51c8877 547 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready (ADRDY) flag */
bogdanm 84:0b3ab51c8877 548 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
bogdanm 84:0b3ab51c8877 549 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
bogdanm 84:0b3ab51c8877 550 #define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */
bogdanm 84:0b3ab51c8877 551 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
bogdanm 84:0b3ab51c8877 552 #define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */
bogdanm 84:0b3ab51c8877 553 #define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC Enf Of Calibration flag */
bogdanm 84:0b3ab51c8877 554
bogdanm 84:0b3ab51c8877 555
bogdanm 84:0b3ab51c8877 556 #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
bogdanm 84:0b3ab51c8877 557 ADC_FLAG_OVR | ADC_FLAG_AWD | ADC_FLAG_EOCAL)
bogdanm 84:0b3ab51c8877 558 /**
bogdanm 84:0b3ab51c8877 559 * @}
bogdanm 84:0b3ab51c8877 560 */
bogdanm 84:0b3ab51c8877 561
bogdanm 84:0b3ab51c8877 562 /**
bogdanm 84:0b3ab51c8877 563 * @}
bogdanm 84:0b3ab51c8877 564 */
bogdanm 84:0b3ab51c8877 565 /* Exported macro ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 566
Kojto 119:aae6fcc7d9bb 567 /** @defgroup ADC_Exported_Macro ADC Exported Macro
bogdanm 84:0b3ab51c8877 568 * @{
bogdanm 84:0b3ab51c8877 569 */
bogdanm 84:0b3ab51c8877 570 /** @brief Reset ADC handle state
bogdanm 84:0b3ab51c8877 571 * @param __HANDLE__: ADC handle
bogdanm 84:0b3ab51c8877 572 * @retval None
bogdanm 84:0b3ab51c8877 573 */
bogdanm 84:0b3ab51c8877 574 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
bogdanm 84:0b3ab51c8877 575
bogdanm 84:0b3ab51c8877 576 /**
bogdanm 84:0b3ab51c8877 577 * @brief Enable the ADC peripheral
bogdanm 84:0b3ab51c8877 578 * @param __HANDLE__: ADC handle
bogdanm 84:0b3ab51c8877 579 * @retval None
bogdanm 84:0b3ab51c8877 580 */
bogdanm 84:0b3ab51c8877 581 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
bogdanm 84:0b3ab51c8877 582
bogdanm 84:0b3ab51c8877 583 /**
bogdanm 84:0b3ab51c8877 584 * @brief Verification of hardware constraints before ADC can be enabled
bogdanm 84:0b3ab51c8877 585 * @param __HANDLE__: ADC handle
bogdanm 84:0b3ab51c8877 586 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
bogdanm 84:0b3ab51c8877 587 */
Kojto 96:487b796308b0 588 #define ADC_ENABLING_CONDITIONS(__HANDLE__) \
bogdanm 84:0b3ab51c8877 589 (( ( ((__HANDLE__)->Instance->CR) & \
bogdanm 84:0b3ab51c8877 590 (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | \
bogdanm 84:0b3ab51c8877 591 ADC_CR_ADDIS | ADC_CR_ADEN ) \
bogdanm 84:0b3ab51c8877 592 ) == RESET \
bogdanm 84:0b3ab51c8877 593 ) ? SET : RESET)
bogdanm 84:0b3ab51c8877 594
bogdanm 84:0b3ab51c8877 595 /**
bogdanm 84:0b3ab51c8877 596 * @brief Disable the ADC peripheral
bogdanm 84:0b3ab51c8877 597 * @param __HANDLE__: ADC handle
bogdanm 84:0b3ab51c8877 598 * @retval None
bogdanm 84:0b3ab51c8877 599 */
bogdanm 84:0b3ab51c8877 600 #define __HAL_ADC_DISABLE(__HANDLE__) \
bogdanm 84:0b3ab51c8877 601 do{ \
bogdanm 84:0b3ab51c8877 602 (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \
bogdanm 84:0b3ab51c8877 603 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
bogdanm 84:0b3ab51c8877 604 } while(0)
bogdanm 84:0b3ab51c8877 605
bogdanm 84:0b3ab51c8877 606 /**
bogdanm 84:0b3ab51c8877 607 * @brief Verification of hardware constraints before ADC can be disabled
bogdanm 84:0b3ab51c8877 608 * @param __HANDLE__: ADC handle
bogdanm 84:0b3ab51c8877 609 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
bogdanm 84:0b3ab51c8877 610 */
Kojto 96:487b796308b0 611 #define ADC_DISABLING_CONDITIONS(__HANDLE__) \
bogdanm 84:0b3ab51c8877 612 (( ( ((__HANDLE__)->Instance->CR) & \
bogdanm 84:0b3ab51c8877 613 (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
bogdanm 84:0b3ab51c8877 614 ) ? SET : RESET)
bogdanm 84:0b3ab51c8877 615
bogdanm 84:0b3ab51c8877 616 /**
bogdanm 84:0b3ab51c8877 617 * @brief Verification of ADC state: enabled or disabled
bogdanm 84:0b3ab51c8877 618 * @param __HANDLE__: ADC handle
bogdanm 84:0b3ab51c8877 619 * @retval SET (ADC enabled) or RESET (ADC disabled)
bogdanm 84:0b3ab51c8877 620 */
Kojto 96:487b796308b0 621 #define ADC_IS_ENABLE(__HANDLE__) \
bogdanm 84:0b3ab51c8877 622 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
bogdanm 84:0b3ab51c8877 623 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
bogdanm 84:0b3ab51c8877 624 ) ? SET : RESET)
bogdanm 84:0b3ab51c8877 625
bogdanm 84:0b3ab51c8877 626 /**
bogdanm 84:0b3ab51c8877 627 * @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution.
bogdanm 84:0b3ab51c8877 628 * @param __HANDLE__: ADC handle
bogdanm 84:0b3ab51c8877 629 * @retval None
bogdanm 84:0b3ab51c8877 630 */
Kojto 96:487b796308b0 631 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
Kojto 119:aae6fcc7d9bb 632 /**
Kojto 119:aae6fcc7d9bb 633 * @brief Test if conversion trigger of regular group is software start
Kojto 119:aae6fcc7d9bb 634 * or external trigger.
Kojto 119:aae6fcc7d9bb 635 * @param __HANDLE__: ADC handle
Kojto 119:aae6fcc7d9bb 636 * @retval SET (software start) or RESET (external trigger)
Kojto 119:aae6fcc7d9bb 637 */
Kojto 119:aae6fcc7d9bb 638 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
Kojto 119:aae6fcc7d9bb 639 (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
Kojto 119:aae6fcc7d9bb 640
Kojto 119:aae6fcc7d9bb 641
bogdanm 84:0b3ab51c8877 642
bogdanm 84:0b3ab51c8877 643 /**
Kojto 119:aae6fcc7d9bb 644 * @brief Check if no conversion on going on regular group
bogdanm 84:0b3ab51c8877 645 * @param __HANDLE__: ADC handle
bogdanm 84:0b3ab51c8877 646 * @retval SET (conversion is on going) or RESET (no conversion is on going)
bogdanm 84:0b3ab51c8877 647 */
Kojto 119:aae6fcc7d9bb 648 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
Kojto 119:aae6fcc7d9bb 649 (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
Kojto 119:aae6fcc7d9bb 650 ) ? RESET : SET)
bogdanm 84:0b3ab51c8877 651
bogdanm 84:0b3ab51c8877 652 /**
bogdanm 84:0b3ab51c8877 653 * @brief Enable ADC continuous conversion mode.
bogdanm 84:0b3ab51c8877 654 * @param _CONTINUOUS_MODE_: Continuous mode.
bogdanm 84:0b3ab51c8877 655 * @retval None
bogdanm 84:0b3ab51c8877 656 */
Kojto 96:487b796308b0 657 #define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13)
Kojto 96:487b796308b0 658
Kojto 96:487b796308b0 659 /**
Kojto 96:487b796308b0 660 * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
Kojto 96:487b796308b0 661 * @param _SCAN_MODE_: Scan conversion mode.
Kojto 96:487b796308b0 662 * @retval None
Kojto 96:487b796308b0 663 */
Kojto 96:487b796308b0 664 #define ADC_SCANDIR(_SCAN_MODE_) \
Kojto 96:487b796308b0 665 ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \
Kojto 96:487b796308b0 666 )? (ADC_CFGR1_SCANDIR) : (0x00000000) \
Kojto 96:487b796308b0 667 )
bogdanm 84:0b3ab51c8877 668
bogdanm 84:0b3ab51c8877 669 /**
bogdanm 84:0b3ab51c8877 670 * @brief Configures the number of discontinuous conversions for the regular group channels.
bogdanm 84:0b3ab51c8877 671 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
bogdanm 84:0b3ab51c8877 672 * @retval None
bogdanm 84:0b3ab51c8877 673 */
bogdanm 84:0b3ab51c8877 674 #define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << 17)
bogdanm 84:0b3ab51c8877 675
bogdanm 84:0b3ab51c8877 676 /**
bogdanm 84:0b3ab51c8877 677 * @brief Enable the ADC DMA continuous request.
bogdanm 84:0b3ab51c8877 678 * @param _DMAContReq_MODE_: DMA continuous request mode.
bogdanm 84:0b3ab51c8877 679 * @retval None
bogdanm 84:0b3ab51c8877 680 */
Kojto 96:487b796308b0 681 #define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1)
bogdanm 84:0b3ab51c8877 682
bogdanm 84:0b3ab51c8877 683 /**
bogdanm 84:0b3ab51c8877 684 * @brief Enable the ADC Auto Delay.
bogdanm 84:0b3ab51c8877 685 * @param _AutoDelay_: Auto delay bit enable or disable.
bogdanm 84:0b3ab51c8877 686 * @retval None
bogdanm 84:0b3ab51c8877 687 */
bogdanm 84:0b3ab51c8877 688 #define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14)
bogdanm 84:0b3ab51c8877 689
bogdanm 84:0b3ab51c8877 690 /**
Kojto 96:487b796308b0 691 * @brief Enable the ADC LowPowerAutoPowerOff.
bogdanm 84:0b3ab51c8877 692 * @param _AUTOFF_: AutoOff bit enable or disable.
bogdanm 84:0b3ab51c8877 693 * @retval None
bogdanm 84:0b3ab51c8877 694 */
bogdanm 84:0b3ab51c8877 695 #define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15)
bogdanm 84:0b3ab51c8877 696
bogdanm 84:0b3ab51c8877 697 /**
bogdanm 84:0b3ab51c8877 698 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
bogdanm 84:0b3ab51c8877 699 * @param _Threshold_: Threshold value
bogdanm 84:0b3ab51c8877 700 * @retval None
bogdanm 84:0b3ab51c8877 701 */
Kojto 96:487b796308b0 702 #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
bogdanm 84:0b3ab51c8877 703
Kojto 119:aae6fcc7d9bb 704 /**
bogdanm 84:0b3ab51c8877 705 * @brief Enable the ADC Low Frequency mode.
bogdanm 84:0b3ab51c8877 706 * @param _LOW_FREQUENCY_MODE_: Low Frequency mode.
bogdanm 84:0b3ab51c8877 707 * @retval None
bogdanm 84:0b3ab51c8877 708 */
bogdanm 84:0b3ab51c8877 709 #define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25)
bogdanm 84:0b3ab51c8877 710
bogdanm 84:0b3ab51c8877 711 /**
bogdanm 84:0b3ab51c8877 712 * @brief Shift the offset in function of the selected ADC resolution.
bogdanm 84:0b3ab51c8877 713 * Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
bogdanm 84:0b3ab51c8877 714 * If resolution 12 bits, no shift.
bogdanm 84:0b3ab51c8877 715 * If resolution 10 bits, shift of 2 ranks on the right.
bogdanm 84:0b3ab51c8877 716 * If resolution 8 bits, shift of 4 ranks on the right.
bogdanm 84:0b3ab51c8877 717 * If resolution 6 bits, shift of 6 ranks on the right.
bogdanm 84:0b3ab51c8877 718 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
bogdanm 84:0b3ab51c8877 719 * @param __HANDLE__: ADC handle.
bogdanm 84:0b3ab51c8877 720 * @param _Offset_: Value to be shifted
bogdanm 84:0b3ab51c8877 721 * @retval None
bogdanm 84:0b3ab51c8877 722 */
Kojto 96:487b796308b0 723 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
bogdanm 84:0b3ab51c8877 724 ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3)*2))
bogdanm 84:0b3ab51c8877 725
bogdanm 84:0b3ab51c8877 726 /**
bogdanm 84:0b3ab51c8877 727 * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
bogdanm 84:0b3ab51c8877 728 * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0
bogdanm 84:0b3ab51c8877 729 * If resolution 12 bits, no shift.
bogdanm 84:0b3ab51c8877 730 * If resolution 10 bits, shift of 2 ranks on the right.
bogdanm 84:0b3ab51c8877 731 * If resolution 8 bits, shift of 4 ranks on the right.
bogdanm 84:0b3ab51c8877 732 * If resolution 6 bits, shift of 6 ranks on the right.
bogdanm 84:0b3ab51c8877 733 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
bogdanm 84:0b3ab51c8877 734 * @param __HANDLE__: ADC handle.
bogdanm 84:0b3ab51c8877 735 * @param _Threshold_: Value to be shifted
bogdanm 84:0b3ab51c8877 736 * @retval None
bogdanm 84:0b3ab51c8877 737 */
Kojto 96:487b796308b0 738 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
bogdanm 84:0b3ab51c8877 739 ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2))
bogdanm 84:0b3ab51c8877 740
bogdanm 84:0b3ab51c8877 741 /**
bogdanm 84:0b3ab51c8877 742 * @brief Shift the value on the left, less significant are set to 0.
bogdanm 84:0b3ab51c8877 743 * @param _Value_: Value to be shifted
bogdanm 84:0b3ab51c8877 744 * @param _Shift_: Number of shift to be done
bogdanm 84:0b3ab51c8877 745 * @retval None
bogdanm 84:0b3ab51c8877 746 */
bogdanm 84:0b3ab51c8877 747 #define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_))
bogdanm 84:0b3ab51c8877 748
bogdanm 84:0b3ab51c8877 749
bogdanm 84:0b3ab51c8877 750 /**
bogdanm 84:0b3ab51c8877 751 * @brief Enable the ADC end of conversion interrupt.
bogdanm 84:0b3ab51c8877 752 * @param __HANDLE__: ADC handle.
bogdanm 84:0b3ab51c8877 753 * @param __INTERRUPT__: ADC Interrupt.
bogdanm 84:0b3ab51c8877 754 * @retval None
bogdanm 84:0b3ab51c8877 755 */
Kojto 119:aae6fcc7d9bb 756 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
Kojto 119:aae6fcc7d9bb 757 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 758
bogdanm 84:0b3ab51c8877 759 /**
bogdanm 84:0b3ab51c8877 760 * @brief Disable the ADC end of conversion interrupt.
bogdanm 84:0b3ab51c8877 761 * @param __HANDLE__: ADC handle.
bogdanm 84:0b3ab51c8877 762 * @param __INTERRUPT__: ADC interrupt.
bogdanm 84:0b3ab51c8877 763 * @retval None
bogdanm 84:0b3ab51c8877 764 */
Kojto 119:aae6fcc7d9bb 765 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
Kojto 119:aae6fcc7d9bb 766 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
bogdanm 84:0b3ab51c8877 767
bogdanm 84:0b3ab51c8877 768 /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
Kojto 119:aae6fcc7d9bb 769 * @param __HANDLE__: ADC handle
Kojto 119:aae6fcc7d9bb 770 * @param __INTERRUPT__: ADC interrupt source to check
Kojto 119:aae6fcc7d9bb 771 * @arg ...
Kojto 119:aae6fcc7d9bb 772 * @arg ...
Kojto 119:aae6fcc7d9bb 773 * @retval State of interruption (TRUE or FALSE)
bogdanm 84:0b3ab51c8877 774 */
Kojto 119:aae6fcc7d9bb 775 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
Kojto 119:aae6fcc7d9bb 776 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 777
bogdanm 84:0b3ab51c8877 778 /**
bogdanm 84:0b3ab51c8877 779 * @brief Clear the ADC's pending flags
bogdanm 84:0b3ab51c8877 780 * @param __HANDLE__: ADC handle.
bogdanm 84:0b3ab51c8877 781 * @param __FLAG__: ADC flag.
bogdanm 84:0b3ab51c8877 782 * @retval None
bogdanm 84:0b3ab51c8877 783 */
bogdanm 84:0b3ab51c8877 784 /* Note: bit cleared bit by writing 1 */
Kojto 119:aae6fcc7d9bb 785 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
Kojto 119:aae6fcc7d9bb 786 (((__HANDLE__)->Instance->ISR) = (__FLAG__))
bogdanm 84:0b3ab51c8877 787
bogdanm 84:0b3ab51c8877 788 /**
bogdanm 84:0b3ab51c8877 789 * @brief Get the selected ADC's flag status.
bogdanm 84:0b3ab51c8877 790 * @param __HANDLE__: ADC handle.
bogdanm 84:0b3ab51c8877 791 * @param __FLAG__: ADC flag.
bogdanm 84:0b3ab51c8877 792 * @retval None
bogdanm 84:0b3ab51c8877 793 */
Kojto 119:aae6fcc7d9bb 794 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
Kojto 119:aae6fcc7d9bb 795 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Kojto 119:aae6fcc7d9bb 796
Kojto 119:aae6fcc7d9bb 797
Kojto 119:aae6fcc7d9bb 798 /**
Kojto 119:aae6fcc7d9bb 799 * @brief Simultaneously clears and sets specific bits of the handle State
Kojto 119:aae6fcc7d9bb 800 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
Kojto 119:aae6fcc7d9bb 801 * the first parameter is the ADC handle State, the second parameter is the
Kojto 119:aae6fcc7d9bb 802 * bit field to clear, the third and last parameter is the bit field to set.
Kojto 119:aae6fcc7d9bb 803 * @retval None
Kojto 119:aae6fcc7d9bb 804 */
Kojto 119:aae6fcc7d9bb 805 #define ADC_STATE_CLR_SET MODIFY_REG
Kojto 119:aae6fcc7d9bb 806
Kojto 119:aae6fcc7d9bb 807 /**
Kojto 119:aae6fcc7d9bb 808 * @brief Clear ADC error code (set it to error code: "no error")
Kojto 119:aae6fcc7d9bb 809 * @param __HANDLE__: ADC handle
Kojto 119:aae6fcc7d9bb 810 * @retval None
Kojto 119:aae6fcc7d9bb 811 */
Kojto 119:aae6fcc7d9bb 812 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
Kojto 119:aae6fcc7d9bb 813 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Kojto 119:aae6fcc7d9bb 814
bogdanm 84:0b3ab51c8877 815
bogdanm 84:0b3ab51c8877 816
bogdanm 84:0b3ab51c8877 817
bogdanm 84:0b3ab51c8877 818 /**
bogdanm 84:0b3ab51c8877 819 * @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler
bogdanm 84:0b3ab51c8877 820 * @param __HANDLE__: ADC handle
bogdanm 84:0b3ab51c8877 821 * @retval None
bogdanm 84:0b3ab51c8877 822 */
bogdanm 84:0b3ab51c8877 823
bogdanm 84:0b3ab51c8877 824 #define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__) \
bogdanm 84:0b3ab51c8877 825 do{ \
Kojto 96:487b796308b0 826 if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
Kojto 96:487b796308b0 827 (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
Kojto 96:487b796308b0 828 (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) \
bogdanm 84:0b3ab51c8877 829 { \
bogdanm 84:0b3ab51c8877 830 (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
bogdanm 84:0b3ab51c8877 831 (__HANDLE__)->Instance->CFGR2 |= (__HANDLE__)->Init.ClockPrescaler; \
bogdanm 84:0b3ab51c8877 832 } \
bogdanm 84:0b3ab51c8877 833 else \
bogdanm 84:0b3ab51c8877 834 { \
bogdanm 84:0b3ab51c8877 835 /* CKMOD bits must be reset */ \
bogdanm 84:0b3ab51c8877 836 (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
bogdanm 84:0b3ab51c8877 837 ADC->CCR &= ~(ADC_CCR_PRESC); \
bogdanm 84:0b3ab51c8877 838 ADC->CCR |= (__HANDLE__)->Init.ClockPrescaler; \
bogdanm 84:0b3ab51c8877 839 } \
bogdanm 84:0b3ab51c8877 840 } while(0)
bogdanm 84:0b3ab51c8877 841
Kojto 119:aae6fcc7d9bb 842
Kojto 119:aae6fcc7d9bb 843 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\
Kojto 119:aae6fcc7d9bb 844 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
Kojto 119:aae6fcc7d9bb 845 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
Kojto 119:aae6fcc7d9bb 846 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
Kojto 119:aae6fcc7d9bb 847 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\
Kojto 119:aae6fcc7d9bb 848 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\
Kojto 119:aae6fcc7d9bb 849 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\
Kojto 119:aae6fcc7d9bb 850 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\
Kojto 119:aae6fcc7d9bb 851 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\
Kojto 119:aae6fcc7d9bb 852 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\
Kojto 119:aae6fcc7d9bb 853 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\
Kojto 119:aae6fcc7d9bb 854 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\
Kojto 119:aae6fcc7d9bb 855 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\
Kojto 119:aae6fcc7d9bb 856 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\
Kojto 119:aae6fcc7d9bb 857 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\
Kojto 119:aae6fcc7d9bb 858 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
Kojto 119:aae6fcc7d9bb 859
Kojto 119:aae6fcc7d9bb 860 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
Kojto 119:aae6fcc7d9bb 861 ((RESOLUTION) == ADC_RESOLUTION_10B) || \
Kojto 119:aae6fcc7d9bb 862 ((RESOLUTION) == ADC_RESOLUTION_8B) || \
Kojto 119:aae6fcc7d9bb 863 ((RESOLUTION) == ADC_RESOLUTION_6B))
Kojto 119:aae6fcc7d9bb 864
Kojto 119:aae6fcc7d9bb 865 #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
Kojto 119:aae6fcc7d9bb 866 ((RESOLUTION) == ADC_RESOLUTION_6B))
Kojto 119:aae6fcc7d9bb 867
Kojto 119:aae6fcc7d9bb 868 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
Kojto 119:aae6fcc7d9bb 869 ((ALIGN) == ADC_DATAALIGN_LEFT))
Kojto 119:aae6fcc7d9bb 870
Kojto 119:aae6fcc7d9bb 871 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
Kojto 119:aae6fcc7d9bb 872 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
Kojto 119:aae6fcc7d9bb 873 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
Kojto 119:aae6fcc7d9bb 874 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
Kojto 119:aae6fcc7d9bb 875
Kojto 119:aae6fcc7d9bb 876 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
Kojto 119:aae6fcc7d9bb 877 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \
Kojto 119:aae6fcc7d9bb 878 ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV))
Kojto 119:aae6fcc7d9bb 879
Kojto 119:aae6fcc7d9bb 880 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
Kojto 119:aae6fcc7d9bb 881 ((OVR) == ADC_OVR_DATA_OVERWRITTEN))
Kojto 119:aae6fcc7d9bb 882
Kojto 119:aae6fcc7d9bb 883 #define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
Kojto 119:aae6fcc7d9bb 884 ((WATCHDOG) == ADC_RANK_NONE))
Kojto 119:aae6fcc7d9bb 885
Kojto 119:aae6fcc7d9bb 886 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
Kojto 119:aae6fcc7d9bb 887 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
Kojto 119:aae6fcc7d9bb 888 ((CHANNEL) == ADC_CHANNEL_1) || \
Kojto 119:aae6fcc7d9bb 889 ((CHANNEL) == ADC_CHANNEL_2) || \
Kojto 119:aae6fcc7d9bb 890 ((CHANNEL) == ADC_CHANNEL_3) || \
Kojto 119:aae6fcc7d9bb 891 ((CHANNEL) == ADC_CHANNEL_4) || \
Kojto 119:aae6fcc7d9bb 892 ((CHANNEL) == ADC_CHANNEL_5) || \
Kojto 119:aae6fcc7d9bb 893 ((CHANNEL) == ADC_CHANNEL_6) || \
Kojto 119:aae6fcc7d9bb 894 ((CHANNEL) == ADC_CHANNEL_7) || \
Kojto 119:aae6fcc7d9bb 895 ((CHANNEL) == ADC_CHANNEL_8) || \
Kojto 119:aae6fcc7d9bb 896 ((CHANNEL) == ADC_CHANNEL_9) || \
Kojto 119:aae6fcc7d9bb 897 ((CHANNEL) == ADC_CHANNEL_10) || \
Kojto 119:aae6fcc7d9bb 898 ((CHANNEL) == ADC_CHANNEL_11) || \
Kojto 119:aae6fcc7d9bb 899 ((CHANNEL) == ADC_CHANNEL_12) || \
Kojto 119:aae6fcc7d9bb 900 ((CHANNEL) == ADC_CHANNEL_13) || \
Kojto 119:aae6fcc7d9bb 901 ((CHANNEL) == ADC_CHANNEL_14) || \
Kojto 119:aae6fcc7d9bb 902 ((CHANNEL) == ADC_CHANNEL_15) || \
Kojto 119:aae6fcc7d9bb 903 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
Kojto 119:aae6fcc7d9bb 904 ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
Kojto 119:aae6fcc7d9bb 905 ((CHANNEL) == ADC_CHANNEL_VLCD))
Kojto 119:aae6fcc7d9bb 906 #else
Kojto 119:aae6fcc7d9bb 907 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
Kojto 119:aae6fcc7d9bb 908 ((CHANNEL) == ADC_CHANNEL_1) || \
Kojto 119:aae6fcc7d9bb 909 ((CHANNEL) == ADC_CHANNEL_2) || \
Kojto 119:aae6fcc7d9bb 910 ((CHANNEL) == ADC_CHANNEL_3) || \
Kojto 119:aae6fcc7d9bb 911 ((CHANNEL) == ADC_CHANNEL_4) || \
Kojto 119:aae6fcc7d9bb 912 ((CHANNEL) == ADC_CHANNEL_5) || \
Kojto 119:aae6fcc7d9bb 913 ((CHANNEL) == ADC_CHANNEL_6) || \
Kojto 119:aae6fcc7d9bb 914 ((CHANNEL) == ADC_CHANNEL_7) || \
Kojto 119:aae6fcc7d9bb 915 ((CHANNEL) == ADC_CHANNEL_8) || \
Kojto 119:aae6fcc7d9bb 916 ((CHANNEL) == ADC_CHANNEL_9) || \
Kojto 119:aae6fcc7d9bb 917 ((CHANNEL) == ADC_CHANNEL_10) || \
Kojto 119:aae6fcc7d9bb 918 ((CHANNEL) == ADC_CHANNEL_11) || \
Kojto 119:aae6fcc7d9bb 919 ((CHANNEL) == ADC_CHANNEL_12) || \
Kojto 119:aae6fcc7d9bb 920 ((CHANNEL) == ADC_CHANNEL_13) || \
Kojto 119:aae6fcc7d9bb 921 ((CHANNEL) == ADC_CHANNEL_14) || \
Kojto 119:aae6fcc7d9bb 922 ((CHANNEL) == ADC_CHANNEL_15) || \
Kojto 119:aae6fcc7d9bb 923 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
Kojto 119:aae6fcc7d9bb 924 ((CHANNEL) == ADC_CHANNEL_VREFINT))
Kojto 119:aae6fcc7d9bb 925 #endif
Kojto 119:aae6fcc7d9bb 926
Kojto 119:aae6fcc7d9bb 927 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || \
Kojto 119:aae6fcc7d9bb 928 ((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || \
Kojto 119:aae6fcc7d9bb 929 ((TIME) == ADC_SAMPLETIME_13CYCLES_5 ) || \
Kojto 119:aae6fcc7d9bb 930 ((TIME) == ADC_SAMPLETIME_28CYCLES_5 ) || \
Kojto 119:aae6fcc7d9bb 931 ((TIME) == ADC_SAMPLETIME_41CYCLES_5 ) || \
Kojto 119:aae6fcc7d9bb 932 ((TIME) == ADC_SAMPLETIME_55CYCLES_5 ) || \
Kojto 119:aae6fcc7d9bb 933 ((TIME) == ADC_SAMPLETIME_71CYCLES_5 ) || \
Kojto 119:aae6fcc7d9bb 934 ((TIME) == ADC_SAMPLETIME_239CYCLES_5))
Kojto 119:aae6fcc7d9bb 935
Kojto 119:aae6fcc7d9bb 936 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
Kojto 119:aae6fcc7d9bb 937 ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
Kojto 119:aae6fcc7d9bb 938
Kojto 119:aae6fcc7d9bb 939 #define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) || \
Kojto 119:aae6fcc7d9bb 940 ((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) || \
Kojto 119:aae6fcc7d9bb 941 ((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) || \
Kojto 119:aae6fcc7d9bb 942 ((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) || \
Kojto 119:aae6fcc7d9bb 943 ((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) || \
Kojto 119:aae6fcc7d9bb 944 ((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) || \
Kojto 119:aae6fcc7d9bb 945 ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || \
Kojto 119:aae6fcc7d9bb 946 ((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
Kojto 119:aae6fcc7d9bb 947
Kojto 119:aae6fcc7d9bb 948 #define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \
Kojto 119:aae6fcc7d9bb 949 ((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || \
Kojto 119:aae6fcc7d9bb 950 ((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || \
Kojto 119:aae6fcc7d9bb 951 ((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || \
Kojto 119:aae6fcc7d9bb 952 ((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || \
Kojto 119:aae6fcc7d9bb 953 ((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || \
Kojto 119:aae6fcc7d9bb 954 ((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || \
Kojto 119:aae6fcc7d9bb 955 ((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || \
Kojto 119:aae6fcc7d9bb 956 ((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
Kojto 119:aae6fcc7d9bb 957
Kojto 119:aae6fcc7d9bb 958 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
Kojto 119:aae6fcc7d9bb 959 ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
Kojto 119:aae6fcc7d9bb 960
Kojto 119:aae6fcc7d9bb 961 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) || \
Kojto 119:aae6fcc7d9bb 962 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
Kojto 119:aae6fcc7d9bb 963 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))
Kojto 119:aae6fcc7d9bb 964
Kojto 119:aae6fcc7d9bb 965 #define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)
Kojto 119:aae6fcc7d9bb 966
Kojto 119:aae6fcc7d9bb 967 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
Kojto 119:aae6fcc7d9bb 968 ((EVENT) == ADC_OVR_EVENT))
Kojto 119:aae6fcc7d9bb 969
Kojto 119:aae6fcc7d9bb 970
Kojto 119:aae6fcc7d9bb 971 /** @defgroup ADC_range_verification ADC Range Verification
Kojto 119:aae6fcc7d9bb 972 * in function of ADC resolution selected (12, 10, 8 or 6 bits)
Kojto 119:aae6fcc7d9bb 973 * @{
Kojto 119:aae6fcc7d9bb 974 */
Kojto 119:aae6fcc7d9bb 975 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
Kojto 119:aae6fcc7d9bb 976 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
Kojto 119:aae6fcc7d9bb 977 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
Kojto 119:aae6fcc7d9bb 978 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
Kojto 119:aae6fcc7d9bb 979 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
Kojto 119:aae6fcc7d9bb 980 /**
Kojto 119:aae6fcc7d9bb 981 * @}
Kojto 119:aae6fcc7d9bb 982 */
Kojto 119:aae6fcc7d9bb 983
Kojto 119:aae6fcc7d9bb 984 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification
Kojto 119:aae6fcc7d9bb 985 * @{
Kojto 119:aae6fcc7d9bb 986 */
Kojto 119:aae6fcc7d9bb 987 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
Kojto 119:aae6fcc7d9bb 988 /**
Kojto 119:aae6fcc7d9bb 989 * @}
Kojto 119:aae6fcc7d9bb 990 */
Kojto 119:aae6fcc7d9bb 991
bogdanm 84:0b3ab51c8877 992 /**
bogdanm 84:0b3ab51c8877 993 * @}
bogdanm 84:0b3ab51c8877 994 */
bogdanm 84:0b3ab51c8877 995
bogdanm 84:0b3ab51c8877 996 /* Include ADC HAL Extension module */
bogdanm 84:0b3ab51c8877 997 #include "stm32l0xx_hal_adc_ex.h"
bogdanm 84:0b3ab51c8877 998
bogdanm 84:0b3ab51c8877 999 /* Exported functions --------------------------------------------------------*/
Kojto 119:aae6fcc7d9bb 1000 /** @defgroup ADC_Exported_Functions ADC Exported Functions
Kojto 119:aae6fcc7d9bb 1001 * @{
Kojto 119:aae6fcc7d9bb 1002 */
bogdanm 84:0b3ab51c8877 1003 /* Initialization and de-initialization functions **********************************/
Kojto 119:aae6fcc7d9bb 1004 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 119:aae6fcc7d9bb 1005 * @brief Initialization and de-initialization functions
Kojto 119:aae6fcc7d9bb 1006 * @{
Kojto 119:aae6fcc7d9bb 1007 */
bogdanm 84:0b3ab51c8877 1008 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
bogdanm 84:0b3ab51c8877 1009 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
bogdanm 84:0b3ab51c8877 1010 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
bogdanm 84:0b3ab51c8877 1011 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
Kojto 119:aae6fcc7d9bb 1012 /**
Kojto 119:aae6fcc7d9bb 1013 * @}
Kojto 119:aae6fcc7d9bb 1014 */
bogdanm 84:0b3ab51c8877 1015
bogdanm 84:0b3ab51c8877 1016 /* IO operation functions *****************************************************/
Kojto 119:aae6fcc7d9bb 1017 /** @defgroup ADC_Exported_Functions_Group2 I/O operation functions
Kojto 119:aae6fcc7d9bb 1018 * @{
Kojto 119:aae6fcc7d9bb 1019 */
bogdanm 84:0b3ab51c8877 1020 /* Blocking mode: Polling */
bogdanm 84:0b3ab51c8877 1021 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
bogdanm 84:0b3ab51c8877 1022 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
bogdanm 84:0b3ab51c8877 1023 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
bogdanm 84:0b3ab51c8877 1024 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
bogdanm 84:0b3ab51c8877 1025
bogdanm 84:0b3ab51c8877 1026 /* Non-blocking mode: Interruption */
bogdanm 84:0b3ab51c8877 1027 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
bogdanm 84:0b3ab51c8877 1028 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
bogdanm 84:0b3ab51c8877 1029
bogdanm 84:0b3ab51c8877 1030 /* Non-blocking mode: DMA */
bogdanm 84:0b3ab51c8877 1031 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
bogdanm 84:0b3ab51c8877 1032 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
bogdanm 84:0b3ab51c8877 1033
bogdanm 84:0b3ab51c8877 1034 /* ADC retrieve conversion value intended to be used with polling or interruption */
bogdanm 84:0b3ab51c8877 1035 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
bogdanm 84:0b3ab51c8877 1036
bogdanm 84:0b3ab51c8877 1037 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
Kojto 119:aae6fcc7d9bb 1038 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
bogdanm 84:0b3ab51c8877 1039 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm 84:0b3ab51c8877 1040 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm 84:0b3ab51c8877 1041 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
bogdanm 84:0b3ab51c8877 1042 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
Kojto 119:aae6fcc7d9bb 1043 /**
Kojto 119:aae6fcc7d9bb 1044 * @}
Kojto 119:aae6fcc7d9bb 1045 */
bogdanm 84:0b3ab51c8877 1046
bogdanm 84:0b3ab51c8877 1047 /* Peripheral Control functions ***********************************************/
Kojto 119:aae6fcc7d9bb 1048 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
Kojto 119:aae6fcc7d9bb 1049 * @{
Kojto 119:aae6fcc7d9bb 1050 */
bogdanm 84:0b3ab51c8877 1051 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
bogdanm 84:0b3ab51c8877 1052 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
Kojto 119:aae6fcc7d9bb 1053 /**
Kojto 119:aae6fcc7d9bb 1054 * @}
Kojto 119:aae6fcc7d9bb 1055 */
bogdanm 84:0b3ab51c8877 1056
bogdanm 84:0b3ab51c8877 1057 /* Peripheral State functions *************************************************/
Kojto 119:aae6fcc7d9bb 1058 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
Kojto 119:aae6fcc7d9bb 1059 * @{
Kojto 119:aae6fcc7d9bb 1060 */
Kojto 119:aae6fcc7d9bb 1061 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
bogdanm 84:0b3ab51c8877 1062 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
Kojto 119:aae6fcc7d9bb 1063 /**
Kojto 119:aae6fcc7d9bb 1064 * @}
Kojto 119:aae6fcc7d9bb 1065 */
bogdanm 84:0b3ab51c8877 1066
bogdanm 84:0b3ab51c8877 1067
bogdanm 84:0b3ab51c8877 1068 /**
bogdanm 84:0b3ab51c8877 1069 * @}
bogdanm 84:0b3ab51c8877 1070 */
bogdanm 84:0b3ab51c8877 1071
Kojto 119:aae6fcc7d9bb 1072 /* Define the private group ***********************************/
Kojto 119:aae6fcc7d9bb 1073 /**************************************************************/
Kojto 119:aae6fcc7d9bb 1074 /** @defgroup ADC_Private ADC Private
Kojto 119:aae6fcc7d9bb 1075 * @{
Kojto 119:aae6fcc7d9bb 1076 */
Kojto 119:aae6fcc7d9bb 1077 /**
Kojto 119:aae6fcc7d9bb 1078 * @}
Kojto 119:aae6fcc7d9bb 1079 */
Kojto 119:aae6fcc7d9bb 1080 /**************************************************************/
Kojto 119:aae6fcc7d9bb 1081
Kojto 119:aae6fcc7d9bb 1082 /**
Kojto 119:aae6fcc7d9bb 1083 * @}
Kojto 119:aae6fcc7d9bb 1084 */
Kojto 119:aae6fcc7d9bb 1085
bogdanm 84:0b3ab51c8877 1086 /**
bogdanm 84:0b3ab51c8877 1087 * @}
bogdanm 84:0b3ab51c8877 1088 */
bogdanm 84:0b3ab51c8877 1089
bogdanm 84:0b3ab51c8877 1090 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 1091 }
bogdanm 84:0b3ab51c8877 1092 #endif
bogdanm 84:0b3ab51c8877 1093
bogdanm 84:0b3ab51c8877 1094 #endif /*__STM32L0xx_ADC_H */
bogdanm 84:0b3ab51c8877 1095
bogdanm 84:0b3ab51c8877 1096
bogdanm 84:0b3ab51c8877 1097 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/