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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_DISCO_L053C8/stm32l0xx_hal_pwr.h@119:aae6fcc7d9bb, 2016-04-27 (annotated)

Committer:
Kojto
Date:
Wed Apr 27 12:10:56 2016 -0500
Revision:
119:aae6fcc7d9bb
Parent:
99:dbbf35b96557 
Release 119 of the mbed library



Changes:

- new targets - EFM32PG_STK3401, NUCLEO_L031K6

- ST - hwflwctl support for NUCLEO_L476RG

     - Update STM32CUBE_L0 from v1.2 to v1.5

     - STM32F7 - bugfix - The weak function HAL_Delay is overwritten to use us ticker API.

- Maxim - Fixing the send break for the MAXWSNENV and MAX32600MBED

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 99:dbbf35b96557 1 /**
Kojto 99:dbbf35b96557 2 ******************************************************************************
Kojto 99:dbbf35b96557 3 * @file stm32l0xx_hal_pwr.h
Kojto 99:dbbf35b96557 4 * @author MCD Application Team
Kojto 119:aae6fcc7d9bb 5 * @version V1.5.0
Kojto 119:aae6fcc7d9bb 6 * @date 8-January-2016
Kojto 99:dbbf35b96557 7 * @brief Header file of PWR HAL module.
Kojto 99:dbbf35b96557 8 ******************************************************************************
Kojto 99:dbbf35b96557 9 * @attention
Kojto 99:dbbf35b96557 10 *
Kojto 119:aae6fcc7d9bb 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 99:dbbf35b96557 12 *
Kojto 99:dbbf35b96557 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 99:dbbf35b96557 14 * are permitted provided that the following conditions are met:
Kojto 99:dbbf35b96557 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 99:dbbf35b96557 16 * this list of conditions and the following disclaimer.
Kojto 99:dbbf35b96557 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 99:dbbf35b96557 18 * this list of conditions and the following disclaimer in the documentation
Kojto 99:dbbf35b96557 19 * and/or other materials provided with the distribution.
Kojto 99:dbbf35b96557 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 99:dbbf35b96557 21 * may be used to endorse or promote products derived from this software
Kojto 99:dbbf35b96557 22 * without specific prior written permission.
Kojto 99:dbbf35b96557 23 *
Kojto 99:dbbf35b96557 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 99:dbbf35b96557 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 99:dbbf35b96557 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 99:dbbf35b96557 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 99:dbbf35b96557 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 99:dbbf35b96557 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 99:dbbf35b96557 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 99:dbbf35b96557 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 99:dbbf35b96557 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 99:dbbf35b96557 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 99:dbbf35b96557 34 *
Kojto 99:dbbf35b96557 35 ******************************************************************************
Kojto 99:dbbf35b96557 36 */
Kojto 99:dbbf35b96557 37
Kojto 99:dbbf35b96557 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 99:dbbf35b96557 39 #ifndef __STM32L0xx_HAL_PWR_H
Kojto 99:dbbf35b96557 40 #define __STM32L0xx_HAL_PWR_H
Kojto 99:dbbf35b96557 41
Kojto 99:dbbf35b96557 42 #ifdef __cplusplus
Kojto 99:dbbf35b96557 43 extern "C" {
Kojto 99:dbbf35b96557 44 #endif
Kojto 99:dbbf35b96557 45
Kojto 99:dbbf35b96557 46 /* Includes ------------------------------------------------------------------*/
Kojto 99:dbbf35b96557 47 #include "stm32l0xx_hal_def.h"
Kojto 99:dbbf35b96557 48
Kojto 99:dbbf35b96557 49 /** @addtogroup STM32L0xx_HAL_Driver
Kojto 99:dbbf35b96557 50 * @{
Kojto 99:dbbf35b96557 51 */
Kojto 99:dbbf35b96557 52
Kojto 119:aae6fcc7d9bb 53 /** @defgroup PWR PWR
Kojto 99:dbbf35b96557 54 * @{
Kojto 99:dbbf35b96557 55 */
Kojto 99:dbbf35b96557 56
Kojto 99:dbbf35b96557 57 /** @defgroup PWR_Exported_Types PWR Exported Types
Kojto 99:dbbf35b96557 58 * @{
Kojto 99:dbbf35b96557 59 */
Kojto 99:dbbf35b96557 60
Kojto 99:dbbf35b96557 61 /**
Kojto 99:dbbf35b96557 62 * @brief PWR PVD configuration structure definition
Kojto 99:dbbf35b96557 63 */
Kojto 99:dbbf35b96557 64 typedef struct
Kojto 99:dbbf35b96557 65 {
Kojto 99:dbbf35b96557 66 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
Kojto 99:dbbf35b96557 67 This parameter can be a value of @ref PWR_PVD_detection_level */
Kojto 99:dbbf35b96557 68
Kojto 99:dbbf35b96557 69 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
Kojto 99:dbbf35b96557 70 This parameter can be a value of @ref PWR_PVD_Mode */
Kojto 99:dbbf35b96557 71 }PWR_PVDTypeDef;
Kojto 99:dbbf35b96557 72
Kojto 99:dbbf35b96557 73 /**
Kojto 99:dbbf35b96557 74 * @}
Kojto 99:dbbf35b96557 75 */
Kojto 99:dbbf35b96557 76
Kojto 119:aae6fcc7d9bb 77 /** @addtogroup PWR_Private
Kojto 99:dbbf35b96557 78 * @{
Kojto 99:dbbf35b96557 79 */
Kojto 99:dbbf35b96557 80
Kojto 99:dbbf35b96557 81 #define PWR_EXTI_LINE_PVD EXTI_FTSR_TR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */
Kojto 99:dbbf35b96557 82
Kojto 99:dbbf35b96557 83 /**
Kojto 99:dbbf35b96557 84 * @}
Kojto 99:dbbf35b96557 85 */
Kojto 99:dbbf35b96557 86
Kojto 99:dbbf35b96557 87 /** @defgroup PWR_Exported_Constants PWR Exported Constants
Kojto 99:dbbf35b96557 88 * @{
Kojto 99:dbbf35b96557 89 */
Kojto 99:dbbf35b96557 90
Kojto 99:dbbf35b96557 91 /** @defgroup PWR_register_alias_address PWR Register alias address
Kojto 99:dbbf35b96557 92 * @{
Kojto 99:dbbf35b96557 93 */
Kojto 99:dbbf35b96557 94 #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1
Kojto 99:dbbf35b96557 95 #define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2
Kojto 119:aae6fcc7d9bb 96 #if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L071xx) || \
Kojto 119:aae6fcc7d9bb 97 defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
Kojto 99:dbbf35b96557 98 #define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3
Kojto 99:dbbf35b96557 99 #endif
Kojto 99:dbbf35b96557 100 /**
Kojto 99:dbbf35b96557 101 * @}
Kojto 99:dbbf35b96557 102 */
Kojto 99:dbbf35b96557 103
Kojto 99:dbbf35b96557 104 /** @defgroup PWR_PVD_detection_level PVD detection level
Kojto 99:dbbf35b96557 105 * @{
Kojto 99:dbbf35b96557 106 */
Kojto 99:dbbf35b96557 107 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
Kojto 99:dbbf35b96557 108 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
Kojto 99:dbbf35b96557 109 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
Kojto 99:dbbf35b96557 110 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
Kojto 99:dbbf35b96557 111 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
Kojto 99:dbbf35b96557 112 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
Kojto 99:dbbf35b96557 113 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
Kojto 99:dbbf35b96557 114 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage
Kojto 99:dbbf35b96557 115 (Compare internally to VREFINT) */
Kojto 99:dbbf35b96557 116 /**
Kojto 99:dbbf35b96557 117 * @}
Kojto 99:dbbf35b96557 118 */
Kojto 99:dbbf35b96557 119
Kojto 99:dbbf35b96557 120 /** @defgroup PWR_PVD_Mode PWR PVD Mode
Kojto 99:dbbf35b96557 121 * @{
Kojto 99:dbbf35b96557 122 */
Kojto 99:dbbf35b96557 123 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
Kojto 99:dbbf35b96557 124 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
Kojto 99:dbbf35b96557 125 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
Kojto 99:dbbf35b96557 126 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
Kojto 99:dbbf35b96557 127 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
Kojto 99:dbbf35b96557 128 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
Kojto 99:dbbf35b96557 129 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
Kojto 99:dbbf35b96557 130
Kojto 99:dbbf35b96557 131 /**
Kojto 99:dbbf35b96557 132 * @}
Kojto 99:dbbf35b96557 133 */
Kojto 99:dbbf35b96557 134
Kojto 99:dbbf35b96557 135 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
Kojto 99:dbbf35b96557 136 * @{
Kojto 99:dbbf35b96557 137 */
Kojto 99:dbbf35b96557 138 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 139 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR
Kojto 99:dbbf35b96557 140
Kojto 99:dbbf35b96557 141 /**
Kojto 99:dbbf35b96557 142 * @}
Kojto 99:dbbf35b96557 143 */
Kojto 99:dbbf35b96557 144
Kojto 99:dbbf35b96557 145 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
Kojto 99:dbbf35b96557 146 * @{
Kojto 99:dbbf35b96557 147 */
Kojto 99:dbbf35b96557 148 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
Kojto 99:dbbf35b96557 149 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
Kojto 99:dbbf35b96557 150 /**
Kojto 99:dbbf35b96557 151 * @}
Kojto 99:dbbf35b96557 152 */
Kojto 99:dbbf35b96557 153
Kojto 99:dbbf35b96557 154 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
Kojto 99:dbbf35b96557 155 * @{
Kojto 99:dbbf35b96557 156 */
Kojto 99:dbbf35b96557 157 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
Kojto 99:dbbf35b96557 158 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
Kojto 99:dbbf35b96557 159 /**
Kojto 99:dbbf35b96557 160 * @}
Kojto 99:dbbf35b96557 161 */
Kojto 99:dbbf35b96557 162
Kojto 99:dbbf35b96557 163 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
Kojto 99:dbbf35b96557 164 * @{
Kojto 99:dbbf35b96557 165 */
Kojto 99:dbbf35b96557 166
Kojto 99:dbbf35b96557 167 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0
Kojto 99:dbbf35b96557 168 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1
Kojto 99:dbbf35b96557 169 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS
Kojto 99:dbbf35b96557 170
Kojto 99:dbbf35b96557 171 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
Kojto 99:dbbf35b96557 172 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
Kojto 99:dbbf35b96557 173 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
Kojto 99:dbbf35b96557 174 /**
Kojto 99:dbbf35b96557 175 * @}
Kojto 99:dbbf35b96557 176 */
Kojto 99:dbbf35b96557 177
Kojto 99:dbbf35b96557 178 /** @defgroup PWR_Flag PWR Flag
Kojto 99:dbbf35b96557 179 * @{
Kojto 99:dbbf35b96557 180 */
Kojto 99:dbbf35b96557 181 #define PWR_FLAG_WU PWR_CSR_WUF
Kojto 99:dbbf35b96557 182 #define PWR_FLAG_SB PWR_CSR_SBF
Kojto 99:dbbf35b96557 183 #define PWR_FLAG_PVDO PWR_CSR_PVDO
Kojto 99:dbbf35b96557 184 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
Kojto 99:dbbf35b96557 185 #define PWR_FLAG_VOS PWR_CSR_VOSF
Kojto 99:dbbf35b96557 186 #define PWR_FLAG_REGLP PWR_CSR_REGLPF
Kojto 99:dbbf35b96557 187
Kojto 119:aae6fcc7d9bb 188
Kojto 99:dbbf35b96557 189 /**
Kojto 99:dbbf35b96557 190 * @}
Kojto 99:dbbf35b96557 191 */
Kojto 99:dbbf35b96557 192
Kojto 99:dbbf35b96557 193 /**
Kojto 99:dbbf35b96557 194 * @}
Kojto 99:dbbf35b96557 195 */
Kojto 99:dbbf35b96557 196
Kojto 119:aae6fcc7d9bb 197 /** @defgroup PWR_Exported_Macro PWR Exported Macros
Kojto 99:dbbf35b96557 198 * @{
Kojto 99:dbbf35b96557 199 */
Kojto 99:dbbf35b96557 200 /** @brief macros configure the main internal regulator output voltage.
Kojto 119:aae6fcc7d9bb 201 * When exiting Low Power Run Mode or during dynamic voltage scaling configuration,
Kojto 119:aae6fcc7d9bb 202 * the reference manual recommends to poll PWR_FLAG_REGLP bit to wait for the regulator
Kojto 119:aae6fcc7d9bb 203 * to reach main mode (resp. to get stabilized) for a transition from 0 to 1.
Kojto 119:aae6fcc7d9bb 204 * Only then the clock can be increased.
Kojto 119:aae6fcc7d9bb 205 *
Kojto 99:dbbf35b96557 206 * @param __REGULATOR__: specifies the regulator output voltage to achieve
Kojto 99:dbbf35b96557 207 * a tradeoff between performance and power consumption when the device does
Kojto 99:dbbf35b96557 208 * not operate at the maximum frequency (refer to the datasheets for more details).
Kojto 99:dbbf35b96557 209 * This parameter can be one of the following values:
Kojto 99:dbbf35b96557 210 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,
Kojto 99:dbbf35b96557 211 * System frequency up to 32 MHz.
Kojto 99:dbbf35b96557 212 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,
Kojto 99:dbbf35b96557 213 * System frequency up to 16 MHz.
Kojto 99:dbbf35b96557 214 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,
Kojto 99:dbbf35b96557 215 * System frequency up to 4.2 MHz
Kojto 99:dbbf35b96557 216 * @retval None
Kojto 99:dbbf35b96557 217 */
Kojto 99:dbbf35b96557 218 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
Kojto 99:dbbf35b96557 219
Kojto 99:dbbf35b96557 220 /** @brief Check PWR flag is set or not.
Kojto 99:dbbf35b96557 221 * @param __FLAG__: specifies the flag to check.
Kojto 99:dbbf35b96557 222 * This parameter can be one of the following values:
Kojto 99:dbbf35b96557 223 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
Kojto 99:dbbf35b96557 224 * was received from the WKUP pin or from the RTC alarm (Alarm B),
Kojto 99:dbbf35b96557 225 * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
Kojto 99:dbbf35b96557 226 * An additional wakeup event is detected if the WKUP pin is enabled
Kojto 99:dbbf35b96557 227 * (by setting the EWUP bit) when the WKUP pin level is already high.
Kojto 99:dbbf35b96557 228 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
Kojto 99:dbbf35b96557 229 * resumed from StandBy mode.
Kojto 99:dbbf35b96557 230 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
Kojto 99:dbbf35b96557 231 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
Kojto 99:dbbf35b96557 232 * For this reason, this bit is equal to 0 after Standby or reset
Kojto 99:dbbf35b96557 233 * until the PVDE bit is set.
Kojto 99:dbbf35b96557 234 * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.
Kojto 99:dbbf35b96557 235 * This bit indicates the state of the internal voltage reference, VREFINT.
Kojto 99:dbbf35b96557 236 * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
Kojto 99:dbbf35b96557 237 * the internal regulator to be ready after the voltage range is changed.
Kojto 99:dbbf35b96557 238 * The VOSF bit indicates that the regulator has reached the voltage level
Kojto 99:dbbf35b96557 239 * defined with bits VOS of PWR_CR register.
Kojto 99:dbbf35b96557 240 * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run
Kojto 99:dbbf35b96557 241 * mode, this bit stays at 1 until the regulator is ready in main mode.
Kojto 99:dbbf35b96557 242 * A polling on this bit is recommended to wait for the regulator main mode.
Kojto 99:dbbf35b96557 243 * This bit is reset by hardware when the regulator is ready.
Kojto 99:dbbf35b96557 244 * @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto 99:dbbf35b96557 245 */
Kojto 99:dbbf35b96557 246 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
Kojto 99:dbbf35b96557 247
Kojto 119:aae6fcc7d9bb 248 /** @brief Clear the PWR pending flags.
Kojto 99:dbbf35b96557 249 * @param __FLAG__: specifies the flag to clear.
Kojto 99:dbbf35b96557 250 * This parameter can be one of the following values:
Kojto 99:dbbf35b96557 251 * @arg PWR_FLAG_WU: Wake Up flag
Kojto 99:dbbf35b96557 252 * @arg PWR_FLAG_SB: StandBy flag
Kojto 99:dbbf35b96557 253 */
Kojto 99:dbbf35b96557 254 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2)
Kojto 99:dbbf35b96557 255
Kojto 99:dbbf35b96557 256 /**
Kojto 99:dbbf35b96557 257 * @brief Enable interrupt on PVD Exti Line 16.
Kojto 99:dbbf35b96557 258 * @retval None.
Kojto 99:dbbf35b96557 259 */
Kojto 99:dbbf35b96557 260 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 261
Kojto 99:dbbf35b96557 262 /**
Kojto 99:dbbf35b96557 263 * @brief Disable interrupt on PVD Exti Line 16.
Kojto 99:dbbf35b96557 264 * @retval None.
Kojto 99:dbbf35b96557 265 */
Kojto 99:dbbf35b96557 266 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 267
Kojto 99:dbbf35b96557 268 /**
Kojto 99:dbbf35b96557 269 * @brief Enable event on PVD Exti Line 16.
Kojto 99:dbbf35b96557 270 * @retval None.
Kojto 99:dbbf35b96557 271 */
Kojto 99:dbbf35b96557 272 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 273
Kojto 99:dbbf35b96557 274 /**
Kojto 99:dbbf35b96557 275 * @brief Disable event on PVD Exti Line 16.
Kojto 99:dbbf35b96557 276 * @retval None.
Kojto 99:dbbf35b96557 277 */
Kojto 99:dbbf35b96557 278 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 279
Kojto 99:dbbf35b96557 280
Kojto 99:dbbf35b96557 281 /**
Kojto 99:dbbf35b96557 282 * @brief PVD EXTI line configuration: set falling edge trigger.
Kojto 99:dbbf35b96557 283 * @retval None.
Kojto 99:dbbf35b96557 284 */
Kojto 99:dbbf35b96557 285 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 286
Kojto 99:dbbf35b96557 287
Kojto 99:dbbf35b96557 288 /**
Kojto 99:dbbf35b96557 289 * @brief Disable the PVD Extended Interrupt Falling Trigger.
Kojto 99:dbbf35b96557 290 * @retval None.
Kojto 99:dbbf35b96557 291 */
Kojto 99:dbbf35b96557 292 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 293
Kojto 99:dbbf35b96557 294
Kojto 99:dbbf35b96557 295 /**
Kojto 99:dbbf35b96557 296 * @brief PVD EXTI line configuration: set rising edge trigger.
Kojto 99:dbbf35b96557 297 * @retval None.
Kojto 99:dbbf35b96557 298 */
Kojto 99:dbbf35b96557 299 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 300
Kojto 99:dbbf35b96557 301 /**
Kojto 99:dbbf35b96557 302 * @brief Disable the PVD Extended Interrupt Rising Trigger.
Kojto 99:dbbf35b96557 303 * This parameter can be:
Kojto 99:dbbf35b96557 304 * @retval None.
Kojto 99:dbbf35b96557 305 */
Kojto 99:dbbf35b96557 306 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 307
Kojto 99:dbbf35b96557 308 /**
Kojto 99:dbbf35b96557 309 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
Kojto 99:dbbf35b96557 310 * @retval None.
Kojto 99:dbbf35b96557 311 */
Kojto 119:aae6fcc7d9bb 312 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } while(0);
Kojto 99:dbbf35b96557 313
Kojto 99:dbbf35b96557 314 /**
Kojto 99:dbbf35b96557 315 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
Kojto 99:dbbf35b96557 316 * This parameter can be:
Kojto 99:dbbf35b96557 317 * @retval None.
Kojto 99:dbbf35b96557 318 */
Kojto 119:aae6fcc7d9bb 319 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0);
Kojto 99:dbbf35b96557 320
Kojto 99:dbbf35b96557 321
Kojto 99:dbbf35b96557 322
Kojto 99:dbbf35b96557 323 /**
Kojto 99:dbbf35b96557 324 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
Kojto 99:dbbf35b96557 325 * @retval EXTI PVD Line Status.
Kojto 99:dbbf35b96557 326 */
Kojto 99:dbbf35b96557 327 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
Kojto 99:dbbf35b96557 328
Kojto 99:dbbf35b96557 329 /**
Kojto 99:dbbf35b96557 330 * @brief Clear the PVD EXTI flag.
Kojto 99:dbbf35b96557 331 * @retval None.
Kojto 99:dbbf35b96557 332 */
Kojto 99:dbbf35b96557 333 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Kojto 99:dbbf35b96557 334
Kojto 99:dbbf35b96557 335 /**
Kojto 99:dbbf35b96557 336 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 99:dbbf35b96557 337 * @retval None.
Kojto 99:dbbf35b96557 338 */
Kojto 99:dbbf35b96557 339 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 340
Kojto 99:dbbf35b96557 341 /**
Kojto 99:dbbf35b96557 342 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 99:dbbf35b96557 343 * @retval None.
Kojto 99:dbbf35b96557 344 */
Kojto 99:dbbf35b96557 345 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 346
Kojto 99:dbbf35b96557 347 /**
Kojto 99:dbbf35b96557 348 * @}
Kojto 99:dbbf35b96557 349 */
Kojto 99:dbbf35b96557 350
Kojto 119:aae6fcc7d9bb 351 /** @addtogroup PWR_Private
Kojto 99:dbbf35b96557 352 * @{
Kojto 99:dbbf35b96557 353 */
Kojto 99:dbbf35b96557 354 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
Kojto 99:dbbf35b96557 355 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
Kojto 99:dbbf35b96557 356 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
Kojto 99:dbbf35b96557 357 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
Kojto 99:dbbf35b96557 358
Kojto 99:dbbf35b96557 359 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
Kojto 99:dbbf35b96557 360 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
Kojto 99:dbbf35b96557 361 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
Kojto 99:dbbf35b96557 362 ((MODE) == PWR_PVD_MODE_NORMAL))
Kojto 99:dbbf35b96557 363
Kojto 99:dbbf35b96557 364 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
Kojto 99:dbbf35b96557 365 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
Kojto 99:dbbf35b96557 366 ((PIN) == PWR_WAKEUP_PIN2) || \
Kojto 99:dbbf35b96557 367 ((PIN) == PWR_WAKEUP_PIN3))
Kojto 119:aae6fcc7d9bb 368 #elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx)
Kojto 99:dbbf35b96557 369 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
Kojto 99:dbbf35b96557 370 ((PIN) == PWR_WAKEUP_PIN2))
Kojto 119:aae6fcc7d9bb 371 #elif defined (STM32L031xx) || defined (STM32L041xx)
Kojto 119:aae6fcc7d9bb 372 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
Kojto 119:aae6fcc7d9bb 373 ((PIN) == PWR_WAKEUP_PIN2))
Kojto 119:aae6fcc7d9bb 374 #elif defined (STM32L011xx) || defined (STM32L021xx)
Kojto 119:aae6fcc7d9bb 375 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
Kojto 119:aae6fcc7d9bb 376 ((PIN) == PWR_WAKEUP_PIN3))
Kojto 99:dbbf35b96557 377 #endif
Kojto 99:dbbf35b96557 378
Kojto 99:dbbf35b96557 379 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
Kojto 99:dbbf35b96557 380 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
Kojto 99:dbbf35b96557 381 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
Kojto 99:dbbf35b96557 382
Kojto 99:dbbf35b96557 383 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
Kojto 99:dbbf35b96557 384
Kojto 99:dbbf35b96557 385 /**
Kojto 99:dbbf35b96557 386 * @}
Kojto 99:dbbf35b96557 387 */
Kojto 99:dbbf35b96557 388
Kojto 99:dbbf35b96557 389 /* Include PWR HAL Extension module */
Kojto 99:dbbf35b96557 390 #include "stm32l0xx_hal_pwr_ex.h"
Kojto 99:dbbf35b96557 391
Kojto 99:dbbf35b96557 392 /** @defgroup PWR_Exported_Functions PWR Exported Functions
Kojto 99:dbbf35b96557 393 * @{
Kojto 99:dbbf35b96557 394 */
Kojto 99:dbbf35b96557 395
Kojto 99:dbbf35b96557 396 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 99:dbbf35b96557 397 * @{
Kojto 99:dbbf35b96557 398 */
Kojto 99:dbbf35b96557 399 void HAL_PWR_DeInit(void);
Kojto 99:dbbf35b96557 400 void HAL_PWR_EnableBkUpAccess(void);
Kojto 99:dbbf35b96557 401 void HAL_PWR_DisableBkUpAccess(void);
Kojto 99:dbbf35b96557 402 /**
Kojto 99:dbbf35b96557 403 * @}
Kojto 99:dbbf35b96557 404 */
Kojto 99:dbbf35b96557 405
Kojto 99:dbbf35b96557 406 /** @defgroup PWR_Exported_Functions_Group2 Low Power modes configuration functions
Kojto 99:dbbf35b96557 407 * @{
Kojto 99:dbbf35b96557 408 */
Kojto 99:dbbf35b96557 409
Kojto 99:dbbf35b96557 410 /* PVD control functions ************************************************/
Kojto 99:dbbf35b96557 411 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
Kojto 99:dbbf35b96557 412 void HAL_PWR_EnablePVD(void);
Kojto 99:dbbf35b96557 413 void HAL_PWR_DisablePVD(void);
Kojto 99:dbbf35b96557 414 void HAL_PWR_PVD_IRQHandler(void);
Kojto 99:dbbf35b96557 415 void HAL_PWR_PVDCallback(void);
Kojto 99:dbbf35b96557 416
Kojto 99:dbbf35b96557 417 /* WakeUp pins configuration functions ****************************************/
Kojto 99:dbbf35b96557 418 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
Kojto 99:dbbf35b96557 419 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
Kojto 99:dbbf35b96557 420
Kojto 99:dbbf35b96557 421 /* Low Power modes configuration functions ************************************/
Kojto 99:dbbf35b96557 422 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
Kojto 99:dbbf35b96557 423 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
Kojto 99:dbbf35b96557 424 void HAL_PWR_EnterSTANDBYMode(void);
Kojto 99:dbbf35b96557 425
Kojto 99:dbbf35b96557 426 void HAL_PWR_EnableSleepOnExit(void);
Kojto 99:dbbf35b96557 427 void HAL_PWR_DisableSleepOnExit(void);
Kojto 99:dbbf35b96557 428 void HAL_PWR_EnableSEVOnPend(void);
Kojto 99:dbbf35b96557 429 void HAL_PWR_DisableSEVOnPend(void);
Kojto 99:dbbf35b96557 430
Kojto 99:dbbf35b96557 431 /**
Kojto 99:dbbf35b96557 432 * @}
Kojto 99:dbbf35b96557 433 */
Kojto 99:dbbf35b96557 434
Kojto 99:dbbf35b96557 435 /**
Kojto 99:dbbf35b96557 436 * @}
Kojto 99:dbbf35b96557 437 */
Kojto 99:dbbf35b96557 438
Kojto 119:aae6fcc7d9bb 439 /* Define the private group ***********************************/
Kojto 119:aae6fcc7d9bb 440 /**************************************************************/
Kojto 119:aae6fcc7d9bb 441 /** @defgroup PWR_Private PWR Private
Kojto 119:aae6fcc7d9bb 442 * @{
Kojto 119:aae6fcc7d9bb 443 */
Kojto 119:aae6fcc7d9bb 444 /**
Kojto 119:aae6fcc7d9bb 445 * @}
Kojto 119:aae6fcc7d9bb 446 */
Kojto 119:aae6fcc7d9bb 447 /**************************************************************/
Kojto 119:aae6fcc7d9bb 448
Kojto 99:dbbf35b96557 449 /**
Kojto 99:dbbf35b96557 450 * @}
Kojto 99:dbbf35b96557 451 */
Kojto 99:dbbf35b96557 452
Kojto 99:dbbf35b96557 453 /**
Kojto 99:dbbf35b96557 454 * @}
Kojto 99:dbbf35b96557 455 */
Kojto 99:dbbf35b96557 456
Kojto 99:dbbf35b96557 457 #ifdef __cplusplus
Kojto 99:dbbf35b96557 458 }
Kojto 99:dbbf35b96557 459 #endif
Kojto 99:dbbf35b96557 460
Kojto 99:dbbf35b96557 461
Kojto 99:dbbf35b96557 462 #endif /* __STM32L0xx_HAL_PWR_H */
Kojto 99:dbbf35b96557 463
Kojto 99:dbbf35b96557 464 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 99:dbbf35b96557 465