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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_DISCO_L053C8/stm32l0xx_hal_dma.h@119:aae6fcc7d9bb, 2016-04-27 (annotated)

Committer:
Kojto
Date:
Wed Apr 27 12:10:56 2016 -0500
Revision:
119:aae6fcc7d9bb
Parent:
99:dbbf35b96557 
Release 119 of the mbed library



Changes:

- new targets - EFM32PG_STK3401, NUCLEO_L031K6

- ST - hwflwctl support for NUCLEO_L476RG

     - Update STM32CUBE_L0 from v1.2 to v1.5

     - STM32F7 - bugfix - The weak function HAL_Delay is overwritten to use us ticker API.

- Maxim - Fixing the send break for the MAXWSNENV and MAX32600MBED

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 99:dbbf35b96557 1 /**
Kojto 99:dbbf35b96557 2 ******************************************************************************
Kojto 99:dbbf35b96557 3 * @file stm32l0xx_hal_dma.h
Kojto 99:dbbf35b96557 4 * @author MCD Application Team
Kojto 119:aae6fcc7d9bb 5 * @version V1.5.0
Kojto 119:aae6fcc7d9bb 6 * @date 8-January-2016
Kojto 99:dbbf35b96557 7 * @brief Header file of DMA HAL module.
Kojto 99:dbbf35b96557 8 ******************************************************************************
Kojto 99:dbbf35b96557 9 * @attention
Kojto 99:dbbf35b96557 10 *
Kojto 119:aae6fcc7d9bb 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 99:dbbf35b96557 12 *
Kojto 99:dbbf35b96557 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 99:dbbf35b96557 14 * are permitted provided that the following conditions are met:
Kojto 99:dbbf35b96557 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 99:dbbf35b96557 16 * this list of conditions and the following disclaimer.
Kojto 99:dbbf35b96557 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 99:dbbf35b96557 18 * this list of conditions and the following disclaimer in the documentation
Kojto 99:dbbf35b96557 19 * and/or other materials provided with the distribution.
Kojto 99:dbbf35b96557 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 99:dbbf35b96557 21 * may be used to endorse or promote products derived from this software
Kojto 99:dbbf35b96557 22 * without specific prior written permission.
Kojto 99:dbbf35b96557 23 *
Kojto 99:dbbf35b96557 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 99:dbbf35b96557 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 99:dbbf35b96557 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 99:dbbf35b96557 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 99:dbbf35b96557 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 99:dbbf35b96557 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 99:dbbf35b96557 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 99:dbbf35b96557 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 99:dbbf35b96557 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 99:dbbf35b96557 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 99:dbbf35b96557 34 *
Kojto 99:dbbf35b96557 35 ******************************************************************************
Kojto 99:dbbf35b96557 36 */
Kojto 99:dbbf35b96557 37
Kojto 99:dbbf35b96557 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 99:dbbf35b96557 39 #ifndef __STM32L0xx_HAL_DMA_H
Kojto 99:dbbf35b96557 40 #define __STM32L0xx_HAL_DMA_H
Kojto 99:dbbf35b96557 41
Kojto 99:dbbf35b96557 42 #ifdef __cplusplus
Kojto 99:dbbf35b96557 43 extern "C" {
Kojto 99:dbbf35b96557 44 #endif
Kojto 99:dbbf35b96557 45
Kojto 99:dbbf35b96557 46 /* Includes ------------------------------------------------------------------*/
Kojto 99:dbbf35b96557 47 #include "stm32l0xx_hal_def.h"
Kojto 99:dbbf35b96557 48
Kojto 99:dbbf35b96557 49 /** @addtogroup STM32L0xx_HAL_Driver
Kojto 99:dbbf35b96557 50 * @{
Kojto 99:dbbf35b96557 51 */
Kojto 99:dbbf35b96557 52
Kojto 99:dbbf35b96557 53 /** @defgroup DMA DMA
Kojto 99:dbbf35b96557 54 * @{
Kojto 99:dbbf35b96557 55 */
Kojto 99:dbbf35b96557 56
Kojto 119:aae6fcc7d9bb 57 /** @defgroup DMA_Exported_Types DMA Exported Types
Kojto 119:aae6fcc7d9bb 58 * @{
Kojto 119:aae6fcc7d9bb 59 */
Kojto 99:dbbf35b96557 60 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 61
Kojto 99:dbbf35b96557 62 /**
Kojto 99:dbbf35b96557 63 * @brief DMA Configuration Structure definition
Kojto 99:dbbf35b96557 64 */
Kojto 99:dbbf35b96557 65 typedef struct
Kojto 99:dbbf35b96557 66 {
Kojto 99:dbbf35b96557 67 uint32_t Request; /*!< Specifies the request selected for the specified channel.
Kojto 99:dbbf35b96557 68 This parameter can be a value of @ref DMA_request */
Kojto 99:dbbf35b96557 69
Kojto 99:dbbf35b96557 70 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
Kojto 99:dbbf35b96557 71 from memory to memory or from peripheral to memory.
Kojto 99:dbbf35b96557 72 This parameter can be a value of @ref DMA_Data_transfer_direction */
Kojto 99:dbbf35b96557 73
Kojto 99:dbbf35b96557 74 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
Kojto 99:dbbf35b96557 75 When Memory to Memory transfer is used, this is the Source Increment mode
Kojto 99:dbbf35b96557 76 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
Kojto 99:dbbf35b96557 77
Kojto 99:dbbf35b96557 78 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
Kojto 99:dbbf35b96557 79 When Memory to Memory transfer is used, this is the Destination Increment mode
Kojto 99:dbbf35b96557 80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
Kojto 99:dbbf35b96557 81
Kojto 99:dbbf35b96557 82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
Kojto 99:dbbf35b96557 83 When Memory to Memory transfer is used, this is the Source Alignment format
Kojto 99:dbbf35b96557 84 This parameter can be a value of @ref DMA_Peripheral_data_size */
Kojto 99:dbbf35b96557 85
Kojto 99:dbbf35b96557 86 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
Kojto 99:dbbf35b96557 87 When Memory to Memory transfer is used, this is the Destination Alignment format
Kojto 99:dbbf35b96557 88 This parameter can be a value of @ref DMA_Memory_data_size */
Kojto 99:dbbf35b96557 89
Kojto 99:dbbf35b96557 90 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx (Normal or Circular).
Kojto 99:dbbf35b96557 91 This parameter can be a value of @ref DMA_mode
Kojto 99:dbbf35b96557 92 @note The circular buffer mode cannot be used if the memory-to-memory
Kojto 99:dbbf35b96557 93 data transfer is configured on the selected Channel */
Kojto 99:dbbf35b96557 94
Kojto 99:dbbf35b96557 95 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
Kojto 99:dbbf35b96557 96 This parameter can be a value of @ref DMA_Priority_level */
Kojto 99:dbbf35b96557 97 } DMA_InitTypeDef;
Kojto 99:dbbf35b96557 98
Kojto 99:dbbf35b96557 99 /**
Kojto 99:dbbf35b96557 100 * @brief DMA Configuration enumeration values definition
Kojto 99:dbbf35b96557 101 */
Kojto 99:dbbf35b96557 102 typedef enum
Kojto 99:dbbf35b96557 103 {
Kojto 99:dbbf35b96557 104 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
Kojto 99:dbbf35b96557 105 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
Kojto 99:dbbf35b96557 106
Kojto 99:dbbf35b96557 107 } DMA_ControlTypeDef;
Kojto 99:dbbf35b96557 108
Kojto 99:dbbf35b96557 109 /**
Kojto 99:dbbf35b96557 110 * @brief HAL DMA State structures definition
Kojto 99:dbbf35b96557 111 */
Kojto 99:dbbf35b96557 112 typedef enum
Kojto 99:dbbf35b96557 113 {
Kojto 99:dbbf35b96557 114 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
Kojto 99:dbbf35b96557 115 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
Kojto 99:dbbf35b96557 116 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
Kojto 99:dbbf35b96557 117 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
Kojto 99:dbbf35b96557 118 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
Kojto 99:dbbf35b96557 119 HAL_DMA_STATE_READY_HALF = 0x05, /*!< DMA Half process success */
Kojto 99:dbbf35b96557 120 }HAL_DMA_StateTypeDef;
Kojto 99:dbbf35b96557 121
Kojto 99:dbbf35b96557 122 /**
Kojto 99:dbbf35b96557 123 * @brief HAL DMA Error Code structure definition
Kojto 99:dbbf35b96557 124 */
Kojto 99:dbbf35b96557 125 typedef enum
Kojto 99:dbbf35b96557 126 {
Kojto 99:dbbf35b96557 127 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
Kojto 99:dbbf35b96557 128 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
Kojto 99:dbbf35b96557 129
Kojto 99:dbbf35b96557 130 }HAL_DMA_LevelCompleteTypeDef;
Kojto 99:dbbf35b96557 131
Kojto 99:dbbf35b96557 132
Kojto 99:dbbf35b96557 133 /**
Kojto 99:dbbf35b96557 134 * @brief DMA handle Structure definition
Kojto 99:dbbf35b96557 135 */
Kojto 99:dbbf35b96557 136 typedef struct __DMA_HandleTypeDef
Kojto 99:dbbf35b96557 137 {
Kojto 99:dbbf35b96557 138 DMA_Channel_TypeDef *Instance; /*!< Register base address */
Kojto 99:dbbf35b96557 139
Kojto 99:dbbf35b96557 140 DMA_InitTypeDef Init; /*!< DMA communication parameters */
Kojto 99:dbbf35b96557 141
Kojto 99:dbbf35b96557 142 HAL_LockTypeDef Lock; /*!< DMA locking object */
Kojto 99:dbbf35b96557 143
Kojto 99:dbbf35b96557 144 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
Kojto 99:dbbf35b96557 145
Kojto 99:dbbf35b96557 146 void *Parent; /*!< Parent object state */
Kojto 99:dbbf35b96557 147
Kojto 99:dbbf35b96557 148 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
Kojto 99:dbbf35b96557 149
Kojto 99:dbbf35b96557 150 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
Kojto 99:dbbf35b96557 151
Kojto 99:dbbf35b96557 152 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
Kojto 99:dbbf35b96557 153
Kojto 99:dbbf35b96557 154 __IO uint32_t ErrorCode; /*!< DMA Error code */
Kojto 99:dbbf35b96557 155
Kojto 99:dbbf35b96557 156 } DMA_HandleTypeDef;
Kojto 99:dbbf35b96557 157
Kojto 119:aae6fcc7d9bb 158 /**
Kojto 119:aae6fcc7d9bb 159 * @}
Kojto 119:aae6fcc7d9bb 160 */
Kojto 119:aae6fcc7d9bb 161
Kojto 99:dbbf35b96557 162 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 163
Kojto 99:dbbf35b96557 164 /** @defgroup DMA_Exported_Constants DMA Exported Constants
Kojto 99:dbbf35b96557 165 * @{
Kojto 99:dbbf35b96557 166 */
Kojto 99:dbbf35b96557 167
Kojto 99:dbbf35b96557 168 /** @defgroup DMA_Error_Code DMA Error Codes
Kojto 99:dbbf35b96557 169 * @{
Kojto 99:dbbf35b96557 170 */
Kojto 99:dbbf35b96557 171 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
Kojto 99:dbbf35b96557 172 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
Kojto 99:dbbf35b96557 173 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
Kojto 99:dbbf35b96557 174
Kojto 119:aae6fcc7d9bb 175 #if defined (STM32L011xx) || defined (STM32L021xx)
Kojto 119:aae6fcc7d9bb 176 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 119:aae6fcc7d9bb 177 ((INSTANCE) == DMA1_Channel2) || \
Kojto 119:aae6fcc7d9bb 178 ((INSTANCE) == DMA1_Channel3) || \
Kojto 119:aae6fcc7d9bb 179 ((INSTANCE) == DMA1_Channel4) || \
Kojto 119:aae6fcc7d9bb 180 ((INSTANCE) == DMA1_Channel5))
Kojto 119:aae6fcc7d9bb 181 #else
Kojto 119:aae6fcc7d9bb 182 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 119:aae6fcc7d9bb 183 ((INSTANCE) == DMA1_Channel2) || \
Kojto 119:aae6fcc7d9bb 184 ((INSTANCE) == DMA1_Channel3) || \
Kojto 119:aae6fcc7d9bb 185 ((INSTANCE) == DMA1_Channel4) || \
Kojto 119:aae6fcc7d9bb 186 ((INSTANCE) == DMA1_Channel5) || \
Kojto 119:aae6fcc7d9bb 187 ((INSTANCE) == DMA1_Channel6) || \
Kojto 119:aae6fcc7d9bb 188 ((INSTANCE) == DMA1_Channel7))
Kojto 99:dbbf35b96557 189
Kojto 119:aae6fcc7d9bb 190 #endif
Kojto 99:dbbf35b96557 191 #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1))
Kojto 99:dbbf35b96557 192
Kojto 99:dbbf35b96557 193 /**
Kojto 99:dbbf35b96557 194 * @}
Kojto 99:dbbf35b96557 195 */
Kojto 99:dbbf35b96557 196
Kojto 99:dbbf35b96557 197 /** @defgroup DMA_request DMA request defintiions
Kojto 99:dbbf35b96557 198 * @{
Kojto 99:dbbf35b96557 199 */
Kojto 99:dbbf35b96557 200
Kojto 99:dbbf35b96557 201 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
Kojto 99:dbbf35b96557 202
Kojto 99:dbbf35b96557 203 #define DMA_REQUEST_0 ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 204 #define DMA_REQUEST_1 ((uint32_t)0x00000001)
Kojto 99:dbbf35b96557 205 #define DMA_REQUEST_2 ((uint32_t)0x00000002)
Kojto 99:dbbf35b96557 206 #define DMA_REQUEST_3 ((uint32_t)0x00000003)
Kojto 99:dbbf35b96557 207 #define DMA_REQUEST_4 ((uint32_t)0x00000004)
Kojto 99:dbbf35b96557 208 #define DMA_REQUEST_5 ((uint32_t)0x00000005)
Kojto 99:dbbf35b96557 209 #define DMA_REQUEST_6 ((uint32_t)0x00000006)
Kojto 99:dbbf35b96557 210 #define DMA_REQUEST_7 ((uint32_t)0x00000007)
Kojto 99:dbbf35b96557 211 #define DMA_REQUEST_8 ((uint32_t)0x00000008)
Kojto 99:dbbf35b96557 212 #define DMA_REQUEST_9 ((uint32_t)0x00000009)
Kojto 99:dbbf35b96557 213 #define DMA_REQUEST_10 ((uint32_t)0x0000000A)
Kojto 99:dbbf35b96557 214 #define DMA_REQUEST_11 ((uint32_t)0x0000000B)
Kojto 99:dbbf35b96557 215 #define DMA_REQUEST_12 ((uint32_t)0x0000000C)
Kojto 99:dbbf35b96557 216 #define DMA_REQUEST_13 ((uint32_t)0x0000000D)
Kojto 99:dbbf35b96557 217 #define DMA_REQUEST_14 ((uint32_t)0x0000000E)
Kojto 99:dbbf35b96557 218 #define DMA_REQUEST_15 ((uint32_t)0x0000000F)
Kojto 99:dbbf35b96557 219
Kojto 99:dbbf35b96557 220 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
Kojto 99:dbbf35b96557 221 ((REQUEST) == DMA_REQUEST_1) || \
Kojto 99:dbbf35b96557 222 ((REQUEST) == DMA_REQUEST_2) || \
Kojto 99:dbbf35b96557 223 ((REQUEST) == DMA_REQUEST_3) || \
Kojto 99:dbbf35b96557 224 ((REQUEST) == DMA_REQUEST_4) || \
Kojto 99:dbbf35b96557 225 ((REQUEST) == DMA_REQUEST_5) || \
Kojto 99:dbbf35b96557 226 ((REQUEST) == DMA_REQUEST_6) || \
Kojto 99:dbbf35b96557 227 ((REQUEST) == DMA_REQUEST_7) || \
Kojto 99:dbbf35b96557 228 ((REQUEST) == DMA_REQUEST_8) || \
Kojto 99:dbbf35b96557 229 ((REQUEST) == DMA_REQUEST_9) || \
Kojto 99:dbbf35b96557 230 ((REQUEST) == DMA_REQUEST_10) || \
Kojto 99:dbbf35b96557 231 ((REQUEST) == DMA_REQUEST_11) || \
Kojto 99:dbbf35b96557 232 ((REQUEST) == DMA_REQUEST_12) || \
Kojto 99:dbbf35b96557 233 ((REQUEST) == DMA_REQUEST_13) || \
Kojto 99:dbbf35b96557 234 ((REQUEST) == DMA_REQUEST_14) || \
Kojto 99:dbbf35b96557 235 ((REQUEST) == DMA_REQUEST_15))
Kojto 99:dbbf35b96557 236
Kojto 99:dbbf35b96557 237 #else /* #if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
Kojto 99:dbbf35b96557 238
Kojto 99:dbbf35b96557 239 #define DMA_REQUEST_0 ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 240 #define DMA_REQUEST_1 ((uint32_t)0x00000001)
Kojto 99:dbbf35b96557 241 #define DMA_REQUEST_2 ((uint32_t)0x00000002)
Kojto 99:dbbf35b96557 242 #define DMA_REQUEST_3 ((uint32_t)0x00000003)
Kojto 99:dbbf35b96557 243 #define DMA_REQUEST_4 ((uint32_t)0x00000004)
Kojto 99:dbbf35b96557 244 #define DMA_REQUEST_5 ((uint32_t)0x00000005)
Kojto 99:dbbf35b96557 245 #define DMA_REQUEST_6 ((uint32_t)0x00000006)
Kojto 99:dbbf35b96557 246 #define DMA_REQUEST_7 ((uint32_t)0x00000007)
Kojto 99:dbbf35b96557 247 #define DMA_REQUEST_8 ((uint32_t)0x00000008)
Kojto 99:dbbf35b96557 248 #define DMA_REQUEST_9 ((uint32_t)0x00000009)
Kojto 99:dbbf35b96557 249 #define DMA_REQUEST_11 ((uint32_t)0x0000000B)
Kojto 99:dbbf35b96557 250
Kojto 99:dbbf35b96557 251 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
Kojto 99:dbbf35b96557 252 ((REQUEST) == DMA_REQUEST_1) || \
Kojto 99:dbbf35b96557 253 ((REQUEST) == DMA_REQUEST_2) || \
Kojto 99:dbbf35b96557 254 ((REQUEST) == DMA_REQUEST_3) || \
Kojto 99:dbbf35b96557 255 ((REQUEST) == DMA_REQUEST_4) || \
Kojto 99:dbbf35b96557 256 ((REQUEST) == DMA_REQUEST_5) || \
Kojto 99:dbbf35b96557 257 ((REQUEST) == DMA_REQUEST_6) || \
Kojto 99:dbbf35b96557 258 ((REQUEST) == DMA_REQUEST_7) || \
Kojto 99:dbbf35b96557 259 ((REQUEST) == DMA_REQUEST_8) || \
Kojto 99:dbbf35b96557 260 ((REQUEST) == DMA_REQUEST_9) || \
Kojto 99:dbbf35b96557 261 ((REQUEST) == DMA_REQUEST_11))
Kojto 99:dbbf35b96557 262 #endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */
Kojto 99:dbbf35b96557 263
Kojto 99:dbbf35b96557 264 /**
Kojto 99:dbbf35b96557 265 * @}
Kojto 99:dbbf35b96557 266 */
Kojto 99:dbbf35b96557 267
Kojto 99:dbbf35b96557 268 /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions
Kojto 99:dbbf35b96557 269 * @{
Kojto 99:dbbf35b96557 270 */
Kojto 99:dbbf35b96557 271 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
Kojto 99:dbbf35b96557 272 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
Kojto 99:dbbf35b96557 273 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
Kojto 99:dbbf35b96557 274
Kojto 99:dbbf35b96557 275 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
Kojto 99:dbbf35b96557 276 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
Kojto 99:dbbf35b96557 277 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto 99:dbbf35b96557 278 /**
Kojto 99:dbbf35b96557 279 * @}
Kojto 99:dbbf35b96557 280 */
Kojto 99:dbbf35b96557 281
Kojto 119:aae6fcc7d9bb 282 /** @defgroup DMA_Data_buffer_size DMA Data Buffer Size Check
Kojto 99:dbbf35b96557 283 * @{
Kojto 99:dbbf35b96557 284 */
Kojto 99:dbbf35b96557 285 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
Kojto 99:dbbf35b96557 286 /**
Kojto 99:dbbf35b96557 287 * @}
Kojto 99:dbbf35b96557 288 */
Kojto 99:dbbf35b96557 289
Kojto 119:aae6fcc7d9bb 290 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral Incremented Mode
Kojto 99:dbbf35b96557 291 * @{
Kojto 99:dbbf35b96557 292 */
Kojto 99:dbbf35b96557 293 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
Kojto 99:dbbf35b96557 294 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
Kojto 99:dbbf35b96557 295
Kojto 99:dbbf35b96557 296 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
Kojto 99:dbbf35b96557 297 ((STATE) == DMA_PINC_DISABLE))
Kojto 99:dbbf35b96557 298 /**
Kojto 99:dbbf35b96557 299 * @}
Kojto 99:dbbf35b96557 300 */
Kojto 99:dbbf35b96557 301
Kojto 119:aae6fcc7d9bb 302 /** @defgroup DMA_Memory_incremented_mode DMA Memory Incremented Mode
Kojto 99:dbbf35b96557 303 * @{
Kojto 99:dbbf35b96557 304 */
Kojto 99:dbbf35b96557 305 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
Kojto 99:dbbf35b96557 306 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
Kojto 99:dbbf35b96557 307
Kojto 99:dbbf35b96557 308 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
Kojto 99:dbbf35b96557 309 ((STATE) == DMA_MINC_DISABLE))
Kojto 99:dbbf35b96557 310 /**
Kojto 99:dbbf35b96557 311 * @}
Kojto 99:dbbf35b96557 312 */
Kojto 99:dbbf35b96557 313
Kojto 119:aae6fcc7d9bb 314 /** @defgroup DMA_Peripheral_data_size DMA Peripheral Data Size Alignment
Kojto 99:dbbf35b96557 315 * @{
Kojto 99:dbbf35b96557 316 */
Kojto 99:dbbf35b96557 317 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
Kojto 99:dbbf35b96557 318 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
Kojto 99:dbbf35b96557 319 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
Kojto 99:dbbf35b96557 320
Kojto 99:dbbf35b96557 321 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
Kojto 99:dbbf35b96557 322 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
Kojto 99:dbbf35b96557 323 ((SIZE) == DMA_PDATAALIGN_WORD))
Kojto 99:dbbf35b96557 324 /**
Kojto 99:dbbf35b96557 325 * @}
Kojto 99:dbbf35b96557 326 */
Kojto 99:dbbf35b96557 327
Kojto 99:dbbf35b96557 328
Kojto 119:aae6fcc7d9bb 329 /** @defgroup DMA_Memory_data_size DMA Memory Data Size Alignment
Kojto 99:dbbf35b96557 330 * @{
Kojto 99:dbbf35b96557 331 */
Kojto 99:dbbf35b96557 332 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
Kojto 99:dbbf35b96557 333 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
Kojto 99:dbbf35b96557 334 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
Kojto 99:dbbf35b96557 335
Kojto 99:dbbf35b96557 336 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
Kojto 99:dbbf35b96557 337 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
Kojto 99:dbbf35b96557 338 ((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto 99:dbbf35b96557 339 /**
Kojto 99:dbbf35b96557 340 * @}
Kojto 99:dbbf35b96557 341 */
Kojto 99:dbbf35b96557 342
Kojto 119:aae6fcc7d9bb 343 /** @defgroup DMA_mode DMA Mode
Kojto 99:dbbf35b96557 344 * @{
Kojto 99:dbbf35b96557 345 */
Kojto 99:dbbf35b96557 346 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
Kojto 99:dbbf35b96557 347 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
Kojto 99:dbbf35b96557 348
Kojto 99:dbbf35b96557 349 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
Kojto 99:dbbf35b96557 350 ((MODE) == DMA_CIRCULAR))
Kojto 99:dbbf35b96557 351 /**
Kojto 99:dbbf35b96557 352 * @}
Kojto 99:dbbf35b96557 353 */
Kojto 99:dbbf35b96557 354
Kojto 119:aae6fcc7d9bb 355 /** @defgroup DMA_Priority_level DMA Priority Level
Kojto 99:dbbf35b96557 356 * @{
Kojto 99:dbbf35b96557 357 */
Kojto 99:dbbf35b96557 358 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
Kojto 99:dbbf35b96557 359 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
Kojto 99:dbbf35b96557 360 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
Kojto 99:dbbf35b96557 361 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
Kojto 99:dbbf35b96557 362
Kojto 99:dbbf35b96557 363 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
Kojto 99:dbbf35b96557 364 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
Kojto 99:dbbf35b96557 365 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
Kojto 99:dbbf35b96557 366 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto 99:dbbf35b96557 367 /**
Kojto 99:dbbf35b96557 368 * @}
Kojto 99:dbbf35b96557 369 */
Kojto 99:dbbf35b96557 370
Kojto 99:dbbf35b96557 371
Kojto 119:aae6fcc7d9bb 372 /** @defgroup DMA_interrupt_enable_definitions DMA Interrupt Definitions
Kojto 99:dbbf35b96557 373 * @{
Kojto 99:dbbf35b96557 374 */
Kojto 99:dbbf35b96557 375
Kojto 99:dbbf35b96557 376 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
Kojto 99:dbbf35b96557 377 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
Kojto 99:dbbf35b96557 378 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
Kojto 99:dbbf35b96557 379
Kojto 99:dbbf35b96557 380 /**
Kojto 99:dbbf35b96557 381 * @}
Kojto 99:dbbf35b96557 382 */
Kojto 99:dbbf35b96557 383
Kojto 119:aae6fcc7d9bb 384 /** @defgroup DMA_flag_definitions DMA Flag Definitions
Kojto 99:dbbf35b96557 385 * @{
Kojto 99:dbbf35b96557 386 */
Kojto 99:dbbf35b96557 387
Kojto 99:dbbf35b96557 388 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
Kojto 99:dbbf35b96557 389 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
Kojto 99:dbbf35b96557 390 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
Kojto 99:dbbf35b96557 391 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
Kojto 99:dbbf35b96557 392 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
Kojto 99:dbbf35b96557 393 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
Kojto 99:dbbf35b96557 394 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
Kojto 99:dbbf35b96557 395 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
Kojto 99:dbbf35b96557 396 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
Kojto 99:dbbf35b96557 397 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
Kojto 99:dbbf35b96557 398 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
Kojto 99:dbbf35b96557 399 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
Kojto 99:dbbf35b96557 400 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
Kojto 99:dbbf35b96557 401 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
Kojto 99:dbbf35b96557 402 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
Kojto 99:dbbf35b96557 403 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
Kojto 99:dbbf35b96557 404 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
Kojto 99:dbbf35b96557 405 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
Kojto 99:dbbf35b96557 406 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
Kojto 99:dbbf35b96557 407 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
Kojto 99:dbbf35b96557 408 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
Kojto 99:dbbf35b96557 409 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
Kojto 99:dbbf35b96557 410 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
Kojto 99:dbbf35b96557 411 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
Kojto 99:dbbf35b96557 412 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
Kojto 99:dbbf35b96557 413 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
Kojto 99:dbbf35b96557 414 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
Kojto 99:dbbf35b96557 415 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
Kojto 99:dbbf35b96557 416
Kojto 99:dbbf35b96557 417
Kojto 99:dbbf35b96557 418 /**
Kojto 99:dbbf35b96557 419 * @}
Kojto 99:dbbf35b96557 420 */
Kojto 99:dbbf35b96557 421
Kojto 99:dbbf35b96557 422 /**
Kojto 99:dbbf35b96557 423 * @}
Kojto 99:dbbf35b96557 424 */
Kojto 99:dbbf35b96557 425
Kojto 99:dbbf35b96557 426 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 427
Kojto 99:dbbf35b96557 428 /** @defgroup DMA_Exported_Macros DMA Exported Macros
Kojto 99:dbbf35b96557 429 * @{
Kojto 99:dbbf35b96557 430 */
Kojto 99:dbbf35b96557 431
Kojto 99:dbbf35b96557 432 /** @brief Reset DMA handle state
Kojto 99:dbbf35b96557 433 * @param __HANDLE__: DMA handle
Kojto 99:dbbf35b96557 434 * @retval None
Kojto 99:dbbf35b96557 435 */
Kojto 99:dbbf35b96557 436 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Kojto 99:dbbf35b96557 437
Kojto 99:dbbf35b96557 438 /**
Kojto 99:dbbf35b96557 439 * @brief Enable the specified DMA Channel.
Kojto 99:dbbf35b96557 440 * @param __HANDLE__: DMA handle
Kojto 99:dbbf35b96557 441 * @retval None.
Kojto 99:dbbf35b96557 442 */
Kojto 99:dbbf35b96557 443 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
Kojto 99:dbbf35b96557 444
Kojto 99:dbbf35b96557 445 /**
Kojto 99:dbbf35b96557 446 * @brief Disable the specified DMA Channel.
Kojto 99:dbbf35b96557 447 * @param __HANDLE__: DMA handle
Kojto 99:dbbf35b96557 448 * @retval None.
Kojto 99:dbbf35b96557 449 */
Kojto 99:dbbf35b96557 450 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
Kojto 99:dbbf35b96557 451
Kojto 99:dbbf35b96557 452
Kojto 99:dbbf35b96557 453 /* Interrupt & Flag management */
Kojto 99:dbbf35b96557 454
Kojto 99:dbbf35b96557 455 /**
Kojto 99:dbbf35b96557 456 * @brief Returns the current DMA Channel transfer complete flag.
Kojto 99:dbbf35b96557 457 * @param __HANDLE__: DMA handle
Kojto 99:dbbf35b96557 458 * @retval The specified transfer complete flag index.
Kojto 99:dbbf35b96557 459 */
Kojto 99:dbbf35b96557 460
Kojto 119:aae6fcc7d9bb 461 #if defined (STM32L011xx) || defined (STM32L021xx)
Kojto 119:aae6fcc7d9bb 462 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
Kojto 119:aae6fcc7d9bb 463 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
Kojto 119:aae6fcc7d9bb 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
Kojto 119:aae6fcc7d9bb 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
Kojto 119:aae6fcc7d9bb 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
Kojto 119:aae6fcc7d9bb 467 DMA_FLAG_TC5)
Kojto 119:aae6fcc7d9bb 468 #else
Kojto 99:dbbf35b96557 469 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
Kojto 99:dbbf35b96557 470 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
Kojto 99:dbbf35b96557 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
Kojto 99:dbbf35b96557 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
Kojto 99:dbbf35b96557 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
Kojto 99:dbbf35b96557 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
Kojto 99:dbbf35b96557 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
Kojto 119:aae6fcc7d9bb 476 DMA_FLAG_TC7)
Kojto 119:aae6fcc7d9bb 477 #endif
Kojto 99:dbbf35b96557 478 /**
Kojto 99:dbbf35b96557 479 * @brief Returns the current DMA Channel half transfer complete flag.
Kojto 99:dbbf35b96557 480 * @param __HANDLE__: DMA handle
Kojto 99:dbbf35b96557 481 * @retval The specified half transfer complete flag index.
Kojto 119:aae6fcc7d9bb 482 */
Kojto 119:aae6fcc7d9bb 483 #if defined (STM32L011xx) || defined (STM32L021xx)
Kojto 119:aae6fcc7d9bb 484 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
Kojto 119:aae6fcc7d9bb 485 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
Kojto 119:aae6fcc7d9bb 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
Kojto 119:aae6fcc7d9bb 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
Kojto 119:aae6fcc7d9bb 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
Kojto 119:aae6fcc7d9bb 489 DMA_FLAG_HT5)
Kojto 119:aae6fcc7d9bb 490 #else
Kojto 99:dbbf35b96557 491 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
Kojto 99:dbbf35b96557 492 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
Kojto 99:dbbf35b96557 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
Kojto 99:dbbf35b96557 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
Kojto 99:dbbf35b96557 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
Kojto 99:dbbf35b96557 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
Kojto 99:dbbf35b96557 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
Kojto 99:dbbf35b96557 498 DMA_FLAG_HT7)
Kojto 119:aae6fcc7d9bb 499 #endif
Kojto 99:dbbf35b96557 500 /**
Kojto 99:dbbf35b96557 501 * @brief Returns the current DMA Channel transfer error flag.
Kojto 99:dbbf35b96557 502 * @param __HANDLE__: DMA handle
Kojto 99:dbbf35b96557 503 * @retval The specified transfer error flag index.
Kojto 99:dbbf35b96557 504 */
Kojto 119:aae6fcc7d9bb 505 #if defined (STM32L011xx) || defined (STM32L021xx)
Kojto 119:aae6fcc7d9bb 506 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
Kojto 119:aae6fcc7d9bb 507 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
Kojto 119:aae6fcc7d9bb 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
Kojto 119:aae6fcc7d9bb 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
Kojto 119:aae6fcc7d9bb 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
Kojto 119:aae6fcc7d9bb 511 DMA_FLAG_TE5)
Kojto 119:aae6fcc7d9bb 512 #else
Kojto 99:dbbf35b96557 513 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
Kojto 99:dbbf35b96557 514 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
Kojto 99:dbbf35b96557 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
Kojto 99:dbbf35b96557 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
Kojto 99:dbbf35b96557 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
Kojto 99:dbbf35b96557 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
Kojto 99:dbbf35b96557 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
Kojto 99:dbbf35b96557 520 DMA_FLAG_TE7)
Kojto 119:aae6fcc7d9bb 521 #endif
Kojto 99:dbbf35b96557 522 /**
Kojto 99:dbbf35b96557 523 * @brief Returns the current DMA Channel Global interrupt flag.
Kojto 99:dbbf35b96557 524 * @param __HANDLE__: DMA handle
Kojto 99:dbbf35b96557 525 * @retval The specified transfer error flag index.
Kojto 99:dbbf35b96557 526 */
Kojto 119:aae6fcc7d9bb 527 #if defined (STM32L011xx) || defined (STM32L021xx)
Kojto 119:aae6fcc7d9bb 528 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
Kojto 119:aae6fcc7d9bb 529 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
Kojto 119:aae6fcc7d9bb 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
Kojto 119:aae6fcc7d9bb 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
Kojto 119:aae6fcc7d9bb 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
Kojto 119:aae6fcc7d9bb 533 DMA_ISR_GIF5)
Kojto 119:aae6fcc7d9bb 534 #else
Kojto 99:dbbf35b96557 535 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
Kojto 99:dbbf35b96557 536 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
Kojto 99:dbbf35b96557 537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
Kojto 99:dbbf35b96557 538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
Kojto 99:dbbf35b96557 539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
Kojto 99:dbbf35b96557 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
Kojto 99:dbbf35b96557 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
Kojto 99:dbbf35b96557 542 DMA_ISR_GIF7)
Kojto 119:aae6fcc7d9bb 543 #endif
Kojto 99:dbbf35b96557 544 /**
Kojto 99:dbbf35b96557 545 * @brief Get the DMA Channel pending flags.
Kojto 99:dbbf35b96557 546 * @param __HANDLE__: DMA handle
Kojto 99:dbbf35b96557 547 * @param __FLAG__: Get the specified flag.
Kojto 99:dbbf35b96557 548 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 549 * @arg DMA_FLAG_TCIFx: Transfer complete flag
Kojto 99:dbbf35b96557 550 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
Kojto 99:dbbf35b96557 551 * @arg DMA_FLAG_TEIFx: Transfer error flag
Kojto 99:dbbf35b96557 552 * @arg DMA_ISR_GIFx: Global interrupt flag
Kojto 99:dbbf35b96557 553 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
Kojto 99:dbbf35b96557 554 * @retval The state of FLAG (SET or RESET).
Kojto 99:dbbf35b96557 555 */
Kojto 99:dbbf35b96557 556 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
Kojto 99:dbbf35b96557 557
Kojto 99:dbbf35b96557 558 /**
Kojto 99:dbbf35b96557 559 * @brief Clears the DMA Channel pending flags.
Kojto 99:dbbf35b96557 560 * @param __HANDLE__: DMA handle
Kojto 99:dbbf35b96557 561 * @param __FLAG__: specifies the flag to clear.
Kojto 99:dbbf35b96557 562 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 563 * @arg DMA_FLAG_TCIFx: Transfer complete flag
Kojto 99:dbbf35b96557 564 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
Kojto 99:dbbf35b96557 565 * @arg DMA_FLAG_TEIFx: Transfer error flag
Kojto 99:dbbf35b96557 566 * @arg DMA_ISR_GIFx: Global interrupt flag
Kojto 99:dbbf35b96557 567 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
Kojto 99:dbbf35b96557 568 * @retval None
Kojto 99:dbbf35b96557 569 */
Kojto 99:dbbf35b96557 570 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
Kojto 99:dbbf35b96557 571
Kojto 99:dbbf35b96557 572 /**
Kojto 99:dbbf35b96557 573 * @brief Enables the specified DMA Channel interrupts.
Kojto 99:dbbf35b96557 574 * @param __HANDLE__: DMA handle
Kojto 99:dbbf35b96557 575 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 99:dbbf35b96557 576 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 577 * @arg DMA_IT_TC: Transfer complete interrupt mask
Kojto 99:dbbf35b96557 578 * @arg DMA_IT_HT: Half transfer complete interrupt mask
Kojto 99:dbbf35b96557 579 * @arg DMA_IT_TE: Transfer error interrupt mask
Kojto 99:dbbf35b96557 580 * @retval None
Kojto 99:dbbf35b96557 581 */
Kojto 99:dbbf35b96557 582 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Kojto 99:dbbf35b96557 583
Kojto 99:dbbf35b96557 584 /**
Kojto 99:dbbf35b96557 585 * @brief Disables the specified DMA Channel interrupts.
Kojto 99:dbbf35b96557 586 * @param __HANDLE__: DMA handle
Kojto 99:dbbf35b96557 587 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 99:dbbf35b96557 588 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 589 * @arg DMA_IT_TC: Transfer complete interrupt mask
Kojto 99:dbbf35b96557 590 * @arg DMA_IT_HT: Half transfer complete interrupt mask
Kojto 99:dbbf35b96557 591 * @arg DMA_IT_TE: Transfer error interrupt mask
Kojto 99:dbbf35b96557 592 * @retval None
Kojto 99:dbbf35b96557 593 */
Kojto 99:dbbf35b96557 594 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Kojto 99:dbbf35b96557 595
Kojto 99:dbbf35b96557 596 /**
Kojto 119:aae6fcc7d9bb 597 * @brief Checks whether the specified DMA Channel interrupt is enabled or not.
Kojto 99:dbbf35b96557 598 * @param __HANDLE__: DMA handle
Kojto 99:dbbf35b96557 599 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
Kojto 99:dbbf35b96557 600 * This parameter can be one of the following values:
Kojto 99:dbbf35b96557 601 * @arg DMA_IT_TC: Transfer complete interrupt mask
Kojto 99:dbbf35b96557 602 * @arg DMA_IT_HT: Half transfer complete interrupt mask
Kojto 99:dbbf35b96557 603 * @arg DMA_IT_TE: Transfer error interrupt mask
Kojto 99:dbbf35b96557 604 * @retval The state of DMA_IT (SET or RESET).
Kojto 99:dbbf35b96557 605 */
Kojto 99:dbbf35b96557 606 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Kojto 99:dbbf35b96557 607
Kojto 99:dbbf35b96557 608 /**
Kojto 99:dbbf35b96557 609 * @}
Kojto 99:dbbf35b96557 610 */
Kojto 99:dbbf35b96557 611
Kojto 99:dbbf35b96557 612 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 613
Kojto 99:dbbf35b96557 614 /** @defgroup DMA_Exported_Functions DMA Exported Functions
Kojto 99:dbbf35b96557 615 * @{
Kojto 99:dbbf35b96557 616 */
Kojto 99:dbbf35b96557 617
Kojto 99:dbbf35b96557 618 /** @defgroup DMA_Exported_Functions_Group1 Initialization/de-initialization functions
Kojto 99:dbbf35b96557 619 * @{
Kojto 99:dbbf35b96557 620 */
Kojto 99:dbbf35b96557 621
Kojto 99:dbbf35b96557 622 /* Initialization and de-initialization functions *****************************/
Kojto 99:dbbf35b96557 623 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 624 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 625
Kojto 99:dbbf35b96557 626 /**
Kojto 99:dbbf35b96557 627 * @}
Kojto 99:dbbf35b96557 628 */
Kojto 99:dbbf35b96557 629
Kojto 99:dbbf35b96557 630 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
Kojto 99:dbbf35b96557 631 * @{
Kojto 99:dbbf35b96557 632 */
Kojto 99:dbbf35b96557 633
Kojto 99:dbbf35b96557 634 /* IO operation functions *****************************************************/
Kojto 99:dbbf35b96557 635 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 99:dbbf35b96557 636 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 99:dbbf35b96557 637 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 638 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
Kojto 99:dbbf35b96557 639 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 640 /**
Kojto 99:dbbf35b96557 641 * @}
Kojto 99:dbbf35b96557 642 */
Kojto 99:dbbf35b96557 643
Kojto 99:dbbf35b96557 644 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
Kojto 99:dbbf35b96557 645 * @{
Kojto 99:dbbf35b96557 646 */
Kojto 99:dbbf35b96557 647
Kojto 99:dbbf35b96557 648 /* Peripheral State and Error functions ***************************************/
Kojto 99:dbbf35b96557 649 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 650 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 651
Kojto 99:dbbf35b96557 652 /**
Kojto 99:dbbf35b96557 653 * @}
Kojto 99:dbbf35b96557 654 */
Kojto 99:dbbf35b96557 655
Kojto 99:dbbf35b96557 656 /**
Kojto 99:dbbf35b96557 657 * @}
Kojto 99:dbbf35b96557 658 */
Kojto 119:aae6fcc7d9bb 659 /* Define the private group ***********************************/
Kojto 119:aae6fcc7d9bb 660 /**************************************************************/
Kojto 119:aae6fcc7d9bb 661 /** @defgroup DMA_Private DMA Private
Kojto 119:aae6fcc7d9bb 662 * @{
Kojto 119:aae6fcc7d9bb 663 */
Kojto 119:aae6fcc7d9bb 664 /**
Kojto 119:aae6fcc7d9bb 665 * @}
Kojto 119:aae6fcc7d9bb 666 */
Kojto 119:aae6fcc7d9bb 667 /**************************************************************/
Kojto 99:dbbf35b96557 668
Kojto 99:dbbf35b96557 669 /**
Kojto 99:dbbf35b96557 670 * @}
Kojto 99:dbbf35b96557 671 */
Kojto 99:dbbf35b96557 672
Kojto 99:dbbf35b96557 673 /**
Kojto 99:dbbf35b96557 674 * @}
Kojto 99:dbbf35b96557 675 */
Kojto 99:dbbf35b96557 676
Kojto 99:dbbf35b96557 677 #ifdef __cplusplus
Kojto 99:dbbf35b96557 678 }
Kojto 99:dbbf35b96557 679 #endif
Kojto 99:dbbf35b96557 680
Kojto 99:dbbf35b96557 681 #endif /* __STM32L0xx_HAL_DMA_H */
Kojto 99:dbbf35b96557 682
Kojto 99:dbbf35b96557 683 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 99:dbbf35b96557 684