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TARGET_DISCO_F407VG/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h@161:aa5281ff4a02, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:16:41 2018 +0000
Revision:
161:aa5281ff4a02
Child:
163:e59c8e839560
mbed library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 161:aa5281ff4a02 1 /**
AnnaBridge 161:aa5281ff4a02 2 ******************************************************************************
AnnaBridge 161:aa5281ff4a02 3 * @file stm32f4xx_ll_i2c.h
AnnaBridge 161:aa5281ff4a02 4 * @author MCD Application Team
AnnaBridge 161:aa5281ff4a02 5 * @version V1.7.1
AnnaBridge 161:aa5281ff4a02 6 * @date 14-April-2017
AnnaBridge 161:aa5281ff4a02 7 * @brief Header file of I2C LL module.
AnnaBridge 161:aa5281ff4a02 8 ******************************************************************************
AnnaBridge 161:aa5281ff4a02 9 * @attention
AnnaBridge 161:aa5281ff4a02 10 *
AnnaBridge 161:aa5281ff4a02 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 161:aa5281ff4a02 12 *
AnnaBridge 161:aa5281ff4a02 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 161:aa5281ff4a02 14 * are permitted provided that the following conditions are met:
AnnaBridge 161:aa5281ff4a02 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 161:aa5281ff4a02 16 * this list of conditions and the following disclaimer.
AnnaBridge 161:aa5281ff4a02 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 161:aa5281ff4a02 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 161:aa5281ff4a02 19 * and/or other materials provided with the distribution.
AnnaBridge 161:aa5281ff4a02 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 161:aa5281ff4a02 21 * may be used to endorse or promote products derived from this software
AnnaBridge 161:aa5281ff4a02 22 * without specific prior written permission.
AnnaBridge 161:aa5281ff4a02 23 *
AnnaBridge 161:aa5281ff4a02 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 161:aa5281ff4a02 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 161:aa5281ff4a02 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 161:aa5281ff4a02 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 161:aa5281ff4a02 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 161:aa5281ff4a02 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 161:aa5281ff4a02 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 161:aa5281ff4a02 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 161:aa5281ff4a02 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 161:aa5281ff4a02 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 161:aa5281ff4a02 34 *
AnnaBridge 161:aa5281ff4a02 35 ******************************************************************************
AnnaBridge 161:aa5281ff4a02 36 */
AnnaBridge 161:aa5281ff4a02 37
AnnaBridge 161:aa5281ff4a02 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 161:aa5281ff4a02 39 #ifndef __STM32F4xx_LL_I2C_H
AnnaBridge 161:aa5281ff4a02 40 #define __STM32F4xx_LL_I2C_H
AnnaBridge 161:aa5281ff4a02 41
AnnaBridge 161:aa5281ff4a02 42 #ifdef __cplusplus
AnnaBridge 161:aa5281ff4a02 43 extern "C" {
AnnaBridge 161:aa5281ff4a02 44 #endif
AnnaBridge 161:aa5281ff4a02 45
AnnaBridge 161:aa5281ff4a02 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 47 #include "stm32f4xx.h"
AnnaBridge 161:aa5281ff4a02 48
AnnaBridge 161:aa5281ff4a02 49 /** @addtogroup STM32F4xx_LL_Driver
AnnaBridge 161:aa5281ff4a02 50 * @{
AnnaBridge 161:aa5281ff4a02 51 */
AnnaBridge 161:aa5281ff4a02 52
AnnaBridge 161:aa5281ff4a02 53 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
AnnaBridge 161:aa5281ff4a02 54
AnnaBridge 161:aa5281ff4a02 55 /** @defgroup I2C_LL I2C
AnnaBridge 161:aa5281ff4a02 56 * @{
AnnaBridge 161:aa5281ff4a02 57 */
AnnaBridge 161:aa5281ff4a02 58
AnnaBridge 161:aa5281ff4a02 59 /* Private types -------------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 60 /* Private variables ---------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 61
AnnaBridge 161:aa5281ff4a02 62 /* Private constants ---------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 63 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
AnnaBridge 161:aa5281ff4a02 64 * @{
AnnaBridge 161:aa5281ff4a02 65 */
AnnaBridge 161:aa5281ff4a02 66
AnnaBridge 161:aa5281ff4a02 67 /* Defines used to perform compute and check in the macros */
AnnaBridge 161:aa5281ff4a02 68 #define LL_I2C_MAX_SPEED_STANDARD 100000U
AnnaBridge 161:aa5281ff4a02 69 #define LL_I2C_MAX_SPEED_FAST 400000U
AnnaBridge 161:aa5281ff4a02 70 /**
AnnaBridge 161:aa5281ff4a02 71 * @}
AnnaBridge 161:aa5281ff4a02 72 */
AnnaBridge 161:aa5281ff4a02 73
AnnaBridge 161:aa5281ff4a02 74 /* Private macros ------------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 75 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 161:aa5281ff4a02 76 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
AnnaBridge 161:aa5281ff4a02 77 * @{
AnnaBridge 161:aa5281ff4a02 78 */
AnnaBridge 161:aa5281ff4a02 79 /**
AnnaBridge 161:aa5281ff4a02 80 * @}
AnnaBridge 161:aa5281ff4a02 81 */
AnnaBridge 161:aa5281ff4a02 82 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 161:aa5281ff4a02 83
AnnaBridge 161:aa5281ff4a02 84 /* Exported types ------------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 85 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 161:aa5281ff4a02 86 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
AnnaBridge 161:aa5281ff4a02 87 * @{
AnnaBridge 161:aa5281ff4a02 88 */
AnnaBridge 161:aa5281ff4a02 89 typedef struct
AnnaBridge 161:aa5281ff4a02 90 {
AnnaBridge 161:aa5281ff4a02 91 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
AnnaBridge 161:aa5281ff4a02 92 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
AnnaBridge 161:aa5281ff4a02 93
AnnaBridge 161:aa5281ff4a02 94 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
AnnaBridge 161:aa5281ff4a02 95
AnnaBridge 161:aa5281ff4a02 96 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
AnnaBridge 161:aa5281ff4a02 97 This parameter must be set to a value lower than 400kHz (in Hz)
AnnaBridge 161:aa5281ff4a02 98
AnnaBridge 161:aa5281ff4a02 99 This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
AnnaBridge 161:aa5281ff4a02 100 or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
AnnaBridge 161:aa5281ff4a02 101
AnnaBridge 161:aa5281ff4a02 102 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
AnnaBridge 161:aa5281ff4a02 103 This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
AnnaBridge 161:aa5281ff4a02 104
AnnaBridge 161:aa5281ff4a02 105 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
AnnaBridge 161:aa5281ff4a02 106
AnnaBridge 161:aa5281ff4a02 107 #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
AnnaBridge 161:aa5281ff4a02 108 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
AnnaBridge 161:aa5281ff4a02 109 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
AnnaBridge 161:aa5281ff4a02 110
AnnaBridge 161:aa5281ff4a02 111 This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
AnnaBridge 161:aa5281ff4a02 112
AnnaBridge 161:aa5281ff4a02 113 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
AnnaBridge 161:aa5281ff4a02 114 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
AnnaBridge 161:aa5281ff4a02 115
AnnaBridge 161:aa5281ff4a02 116 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
AnnaBridge 161:aa5281ff4a02 117
AnnaBridge 161:aa5281ff4a02 118 #endif
AnnaBridge 161:aa5281ff4a02 119 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
AnnaBridge 161:aa5281ff4a02 120 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
AnnaBridge 161:aa5281ff4a02 121
AnnaBridge 161:aa5281ff4a02 122 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
AnnaBridge 161:aa5281ff4a02 123
AnnaBridge 161:aa5281ff4a02 124 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
AnnaBridge 161:aa5281ff4a02 125 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
AnnaBridge 161:aa5281ff4a02 126
AnnaBridge 161:aa5281ff4a02 127 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
AnnaBridge 161:aa5281ff4a02 128
AnnaBridge 161:aa5281ff4a02 129 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
AnnaBridge 161:aa5281ff4a02 130 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
AnnaBridge 161:aa5281ff4a02 131
AnnaBridge 161:aa5281ff4a02 132 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
AnnaBridge 161:aa5281ff4a02 133 } LL_I2C_InitTypeDef;
AnnaBridge 161:aa5281ff4a02 134 /**
AnnaBridge 161:aa5281ff4a02 135 * @}
AnnaBridge 161:aa5281ff4a02 136 */
AnnaBridge 161:aa5281ff4a02 137 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 161:aa5281ff4a02 138
AnnaBridge 161:aa5281ff4a02 139 /* Exported constants --------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 140 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
AnnaBridge 161:aa5281ff4a02 141 * @{
AnnaBridge 161:aa5281ff4a02 142 */
AnnaBridge 161:aa5281ff4a02 143
AnnaBridge 161:aa5281ff4a02 144 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 161:aa5281ff4a02 145 * @brief Flags defines which can be used with LL_I2C_ReadReg function
AnnaBridge 161:aa5281ff4a02 146 * @{
AnnaBridge 161:aa5281ff4a02 147 */
AnnaBridge 161:aa5281ff4a02 148 #define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
AnnaBridge 161:aa5281ff4a02 149 #define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
AnnaBridge 161:aa5281ff4a02 150 Address matched flag (slave mode) */
AnnaBridge 161:aa5281ff4a02 151 #define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
AnnaBridge 161:aa5281ff4a02 152 #define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
AnnaBridge 161:aa5281ff4a02 153 #define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
AnnaBridge 161:aa5281ff4a02 154 #define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
AnnaBridge 161:aa5281ff4a02 155 #define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
AnnaBridge 161:aa5281ff4a02 156 #define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
AnnaBridge 161:aa5281ff4a02 157 #define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
AnnaBridge 161:aa5281ff4a02 158 #define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
AnnaBridge 161:aa5281ff4a02 159 #define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
AnnaBridge 161:aa5281ff4a02 160 #define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
AnnaBridge 161:aa5281ff4a02 161 #define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
AnnaBridge 161:aa5281ff4a02 162 #define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
AnnaBridge 161:aa5281ff4a02 163 #define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
AnnaBridge 161:aa5281ff4a02 164 #define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
AnnaBridge 161:aa5281ff4a02 165 #define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
AnnaBridge 161:aa5281ff4a02 166 #define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
AnnaBridge 161:aa5281ff4a02 167 #define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
AnnaBridge 161:aa5281ff4a02 168 #define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
AnnaBridge 161:aa5281ff4a02 169 #define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
AnnaBridge 161:aa5281ff4a02 170 /**
AnnaBridge 161:aa5281ff4a02 171 * @}
AnnaBridge 161:aa5281ff4a02 172 */
AnnaBridge 161:aa5281ff4a02 173
AnnaBridge 161:aa5281ff4a02 174 /** @defgroup I2C_LL_EC_IT IT Defines
AnnaBridge 161:aa5281ff4a02 175 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
AnnaBridge 161:aa5281ff4a02 176 * @{
AnnaBridge 161:aa5281ff4a02 177 */
AnnaBridge 161:aa5281ff4a02 178 #define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
AnnaBridge 161:aa5281ff4a02 179 #define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
AnnaBridge 161:aa5281ff4a02 180 #define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
AnnaBridge 161:aa5281ff4a02 181 /**
AnnaBridge 161:aa5281ff4a02 182 * @}
AnnaBridge 161:aa5281ff4a02 183 */
AnnaBridge 161:aa5281ff4a02 184
AnnaBridge 161:aa5281ff4a02 185 #if defined(I2C_FLTR_ANOFF)
AnnaBridge 161:aa5281ff4a02 186 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
AnnaBridge 161:aa5281ff4a02 187 * @{
AnnaBridge 161:aa5281ff4a02 188 */
AnnaBridge 161:aa5281ff4a02 189 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
AnnaBridge 161:aa5281ff4a02 190 #define LL_I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF /*!< Analog filter is disabled.*/
AnnaBridge 161:aa5281ff4a02 191 /**
AnnaBridge 161:aa5281ff4a02 192 * @}
AnnaBridge 161:aa5281ff4a02 193 */
AnnaBridge 161:aa5281ff4a02 194
AnnaBridge 161:aa5281ff4a02 195 #endif
AnnaBridge 161:aa5281ff4a02 196 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
AnnaBridge 161:aa5281ff4a02 197 * @{
AnnaBridge 161:aa5281ff4a02 198 */
AnnaBridge 161:aa5281ff4a02 199 #define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
AnnaBridge 161:aa5281ff4a02 200 #define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
AnnaBridge 161:aa5281ff4a02 201 /**
AnnaBridge 161:aa5281ff4a02 202 * @}
AnnaBridge 161:aa5281ff4a02 203 */
AnnaBridge 161:aa5281ff4a02 204
AnnaBridge 161:aa5281ff4a02 205 /** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
AnnaBridge 161:aa5281ff4a02 206 * @{
AnnaBridge 161:aa5281ff4a02 207 */
AnnaBridge 161:aa5281ff4a02 208 #define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
AnnaBridge 161:aa5281ff4a02 209 #define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
AnnaBridge 161:aa5281ff4a02 210 /**
AnnaBridge 161:aa5281ff4a02 211 * @}
AnnaBridge 161:aa5281ff4a02 212 */
AnnaBridge 161:aa5281ff4a02 213
AnnaBridge 161:aa5281ff4a02 214 /** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
AnnaBridge 161:aa5281ff4a02 215 * @{
AnnaBridge 161:aa5281ff4a02 216 */
AnnaBridge 161:aa5281ff4a02 217 #define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
AnnaBridge 161:aa5281ff4a02 218 #define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
AnnaBridge 161:aa5281ff4a02 219 /**
AnnaBridge 161:aa5281ff4a02 220 * @}
AnnaBridge 161:aa5281ff4a02 221 */
AnnaBridge 161:aa5281ff4a02 222
AnnaBridge 161:aa5281ff4a02 223 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
AnnaBridge 161:aa5281ff4a02 224 * @{
AnnaBridge 161:aa5281ff4a02 225 */
AnnaBridge 161:aa5281ff4a02 226 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
AnnaBridge 161:aa5281ff4a02 227 #define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
AnnaBridge 161:aa5281ff4a02 228 #define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
AnnaBridge 161:aa5281ff4a02 229 #define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
AnnaBridge 161:aa5281ff4a02 230 /**
AnnaBridge 161:aa5281ff4a02 231 * @}
AnnaBridge 161:aa5281ff4a02 232 */
AnnaBridge 161:aa5281ff4a02 233
AnnaBridge 161:aa5281ff4a02 234 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
AnnaBridge 161:aa5281ff4a02 235 * @{
AnnaBridge 161:aa5281ff4a02 236 */
AnnaBridge 161:aa5281ff4a02 237 #define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
AnnaBridge 161:aa5281ff4a02 238 #define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
AnnaBridge 161:aa5281ff4a02 239 /**
AnnaBridge 161:aa5281ff4a02 240 * @}
AnnaBridge 161:aa5281ff4a02 241 */
AnnaBridge 161:aa5281ff4a02 242
AnnaBridge 161:aa5281ff4a02 243 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
AnnaBridge 161:aa5281ff4a02 244 * @{
AnnaBridge 161:aa5281ff4a02 245 */
AnnaBridge 161:aa5281ff4a02 246 #define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
AnnaBridge 161:aa5281ff4a02 247 #define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
AnnaBridge 161:aa5281ff4a02 248 /**
AnnaBridge 161:aa5281ff4a02 249 * @}
AnnaBridge 161:aa5281ff4a02 250 */
AnnaBridge 161:aa5281ff4a02 251
AnnaBridge 161:aa5281ff4a02 252 /**
AnnaBridge 161:aa5281ff4a02 253 * @}
AnnaBridge 161:aa5281ff4a02 254 */
AnnaBridge 161:aa5281ff4a02 255
AnnaBridge 161:aa5281ff4a02 256 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 257 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
AnnaBridge 161:aa5281ff4a02 258 * @{
AnnaBridge 161:aa5281ff4a02 259 */
AnnaBridge 161:aa5281ff4a02 260
AnnaBridge 161:aa5281ff4a02 261 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge 161:aa5281ff4a02 262 * @{
AnnaBridge 161:aa5281ff4a02 263 */
AnnaBridge 161:aa5281ff4a02 264
AnnaBridge 161:aa5281ff4a02 265 /**
AnnaBridge 161:aa5281ff4a02 266 * @brief Write a value in I2C register
AnnaBridge 161:aa5281ff4a02 267 * @param __INSTANCE__ I2C Instance
AnnaBridge 161:aa5281ff4a02 268 * @param __REG__ Register to be written
AnnaBridge 161:aa5281ff4a02 269 * @param __VALUE__ Value to be written in the register
AnnaBridge 161:aa5281ff4a02 270 * @retval None
AnnaBridge 161:aa5281ff4a02 271 */
AnnaBridge 161:aa5281ff4a02 272 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 161:aa5281ff4a02 273
AnnaBridge 161:aa5281ff4a02 274 /**
AnnaBridge 161:aa5281ff4a02 275 * @brief Read a value in I2C register
AnnaBridge 161:aa5281ff4a02 276 * @param __INSTANCE__ I2C Instance
AnnaBridge 161:aa5281ff4a02 277 * @param __REG__ Register to be read
AnnaBridge 161:aa5281ff4a02 278 * @retval Register value
AnnaBridge 161:aa5281ff4a02 279 */
AnnaBridge 161:aa5281ff4a02 280 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 161:aa5281ff4a02 281 /**
AnnaBridge 161:aa5281ff4a02 282 * @}
AnnaBridge 161:aa5281ff4a02 283 */
AnnaBridge 161:aa5281ff4a02 284
AnnaBridge 161:aa5281ff4a02 285 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
AnnaBridge 161:aa5281ff4a02 286 * @{
AnnaBridge 161:aa5281ff4a02 287 */
AnnaBridge 161:aa5281ff4a02 288
AnnaBridge 161:aa5281ff4a02 289 /**
AnnaBridge 161:aa5281ff4a02 290 * @brief Convert Peripheral Clock Frequency in Mhz.
AnnaBridge 161:aa5281ff4a02 291 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge 161:aa5281ff4a02 292 * @retval Value of peripheral clock (in Mhz)
AnnaBridge 161:aa5281ff4a02 293 */
AnnaBridge 161:aa5281ff4a02 294 #define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
AnnaBridge 161:aa5281ff4a02 295
AnnaBridge 161:aa5281ff4a02 296 /**
AnnaBridge 161:aa5281ff4a02 297 * @brief Convert Peripheral Clock Frequency in Hz.
AnnaBridge 161:aa5281ff4a02 298 * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
AnnaBridge 161:aa5281ff4a02 299 * @retval Value of peripheral clock (in Hz)
AnnaBridge 161:aa5281ff4a02 300 */
AnnaBridge 161:aa5281ff4a02 301 #define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
AnnaBridge 161:aa5281ff4a02 302
AnnaBridge 161:aa5281ff4a02 303 /**
AnnaBridge 161:aa5281ff4a02 304 * @brief Compute I2C Clock rising time.
AnnaBridge 161:aa5281ff4a02 305 * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
AnnaBridge 161:aa5281ff4a02 306 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge 161:aa5281ff4a02 307 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
AnnaBridge 161:aa5281ff4a02 308 */
AnnaBridge 161:aa5281ff4a02 309 #define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
AnnaBridge 161:aa5281ff4a02 310
AnnaBridge 161:aa5281ff4a02 311 /**
AnnaBridge 161:aa5281ff4a02 312 * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge 161:aa5281ff4a02 313 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge 161:aa5281ff4a02 314 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge 161:aa5281ff4a02 315 * @param __DUTYCYCLE__ This parameter can be one of the following values:
AnnaBridge 161:aa5281ff4a02 316 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 161:aa5281ff4a02 317 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 161:aa5281ff4a02 318 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge 161:aa5281ff4a02 319 */
AnnaBridge 161:aa5281ff4a02 320 #define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
AnnaBridge 161:aa5281ff4a02 321 (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
AnnaBridge 161:aa5281ff4a02 322 (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
AnnaBridge 161:aa5281ff4a02 323
AnnaBridge 161:aa5281ff4a02 324 /**
AnnaBridge 161:aa5281ff4a02 325 * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge 161:aa5281ff4a02 326 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge 161:aa5281ff4a02 327 * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
AnnaBridge 161:aa5281ff4a02 328 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
AnnaBridge 161:aa5281ff4a02 329 */
AnnaBridge 161:aa5281ff4a02 330 #define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
AnnaBridge 161:aa5281ff4a02 331
AnnaBridge 161:aa5281ff4a02 332 /**
AnnaBridge 161:aa5281ff4a02 333 * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge 161:aa5281ff4a02 334 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge 161:aa5281ff4a02 335 * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
AnnaBridge 161:aa5281ff4a02 336 * @param __DUTYCYCLE__ This parameter can be one of the following values:
AnnaBridge 161:aa5281ff4a02 337 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 161:aa5281ff4a02 338 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 161:aa5281ff4a02 339 * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
AnnaBridge 161:aa5281ff4a02 340 */
AnnaBridge 161:aa5281ff4a02 341 #define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
AnnaBridge 161:aa5281ff4a02 342 (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
AnnaBridge 161:aa5281ff4a02 343 (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
AnnaBridge 161:aa5281ff4a02 344
AnnaBridge 161:aa5281ff4a02 345 /**
AnnaBridge 161:aa5281ff4a02 346 * @brief Get the Least significant bits of a 10-Bits address.
AnnaBridge 161:aa5281ff4a02 347 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge 161:aa5281ff4a02 348 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 161:aa5281ff4a02 349 */
AnnaBridge 161:aa5281ff4a02 350 #define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
AnnaBridge 161:aa5281ff4a02 351
AnnaBridge 161:aa5281ff4a02 352 /**
AnnaBridge 161:aa5281ff4a02 353 * @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
AnnaBridge 161:aa5281ff4a02 354 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge 161:aa5281ff4a02 355 * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
AnnaBridge 161:aa5281ff4a02 356 */
AnnaBridge 161:aa5281ff4a02 357 #define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
AnnaBridge 161:aa5281ff4a02 358
AnnaBridge 161:aa5281ff4a02 359 /**
AnnaBridge 161:aa5281ff4a02 360 * @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
AnnaBridge 161:aa5281ff4a02 361 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge 161:aa5281ff4a02 362 * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
AnnaBridge 161:aa5281ff4a02 363 */
AnnaBridge 161:aa5281ff4a02 364 #define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
AnnaBridge 161:aa5281ff4a02 365
AnnaBridge 161:aa5281ff4a02 366 /**
AnnaBridge 161:aa5281ff4a02 367 * @}
AnnaBridge 161:aa5281ff4a02 368 */
AnnaBridge 161:aa5281ff4a02 369
AnnaBridge 161:aa5281ff4a02 370 /**
AnnaBridge 161:aa5281ff4a02 371 * @}
AnnaBridge 161:aa5281ff4a02 372 */
AnnaBridge 161:aa5281ff4a02 373
AnnaBridge 161:aa5281ff4a02 374 /* Exported functions --------------------------------------------------------*/
AnnaBridge 161:aa5281ff4a02 375
AnnaBridge 161:aa5281ff4a02 376 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
AnnaBridge 161:aa5281ff4a02 377 * @{
AnnaBridge 161:aa5281ff4a02 378 */
AnnaBridge 161:aa5281ff4a02 379
AnnaBridge 161:aa5281ff4a02 380 /** @defgroup I2C_LL_EF_Configuration Configuration
AnnaBridge 161:aa5281ff4a02 381 * @{
AnnaBridge 161:aa5281ff4a02 382 */
AnnaBridge 161:aa5281ff4a02 383
AnnaBridge 161:aa5281ff4a02 384 /**
AnnaBridge 161:aa5281ff4a02 385 * @brief Enable I2C peripheral (PE = 1).
AnnaBridge 161:aa5281ff4a02 386 * @rmtoll CR1 PE LL_I2C_Enable
AnnaBridge 161:aa5281ff4a02 387 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 388 * @retval None
AnnaBridge 161:aa5281ff4a02 389 */
AnnaBridge 161:aa5281ff4a02 390 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 391 {
AnnaBridge 161:aa5281ff4a02 392 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge 161:aa5281ff4a02 393 }
AnnaBridge 161:aa5281ff4a02 394
AnnaBridge 161:aa5281ff4a02 395 /**
AnnaBridge 161:aa5281ff4a02 396 * @brief Disable I2C peripheral (PE = 0).
AnnaBridge 161:aa5281ff4a02 397 * @rmtoll CR1 PE LL_I2C_Disable
AnnaBridge 161:aa5281ff4a02 398 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 399 * @retval None
AnnaBridge 161:aa5281ff4a02 400 */
AnnaBridge 161:aa5281ff4a02 401 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 402 {
AnnaBridge 161:aa5281ff4a02 403 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge 161:aa5281ff4a02 404 }
AnnaBridge 161:aa5281ff4a02 405
AnnaBridge 161:aa5281ff4a02 406 /**
AnnaBridge 161:aa5281ff4a02 407 * @brief Check if the I2C peripheral is enabled or disabled.
AnnaBridge 161:aa5281ff4a02 408 * @rmtoll CR1 PE LL_I2C_IsEnabled
AnnaBridge 161:aa5281ff4a02 409 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 410 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 411 */
AnnaBridge 161:aa5281ff4a02 412 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 413 {
AnnaBridge 161:aa5281ff4a02 414 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
AnnaBridge 161:aa5281ff4a02 415 }
AnnaBridge 161:aa5281ff4a02 416
AnnaBridge 161:aa5281ff4a02 417 #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
AnnaBridge 161:aa5281ff4a02 418 /**
AnnaBridge 161:aa5281ff4a02 419 * @brief Configure Noise Filters (Analog and Digital).
AnnaBridge 161:aa5281ff4a02 420 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
AnnaBridge 161:aa5281ff4a02 421 * The filters can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 161:aa5281ff4a02 422 * @rmtoll FLTR ANOFF LL_I2C_ConfigFilters\n
AnnaBridge 161:aa5281ff4a02 423 * FLTR DNF LL_I2C_ConfigFilters
AnnaBridge 161:aa5281ff4a02 424 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 425 * @param AnalogFilter This parameter can be one of the following values:
AnnaBridge 161:aa5281ff4a02 426 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
AnnaBridge 161:aa5281ff4a02 427 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
AnnaBridge 161:aa5281ff4a02 428 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
AnnaBridge 161:aa5281ff4a02 429 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
AnnaBridge 161:aa5281ff4a02 430 * @retval None
AnnaBridge 161:aa5281ff4a02 431 */
AnnaBridge 161:aa5281ff4a02 432 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
AnnaBridge 161:aa5281ff4a02 433 {
AnnaBridge 161:aa5281ff4a02 434 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_ANOFF | I2C_FLTR_DNF, AnalogFilter | DigitalFilter);
AnnaBridge 161:aa5281ff4a02 435 }
AnnaBridge 161:aa5281ff4a02 436 #endif
AnnaBridge 161:aa5281ff4a02 437 #if defined(I2C_FLTR_DNF)
AnnaBridge 161:aa5281ff4a02 438
AnnaBridge 161:aa5281ff4a02 439 /**
AnnaBridge 161:aa5281ff4a02 440 * @brief Configure Digital Noise Filter.
AnnaBridge 161:aa5281ff4a02 441 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
AnnaBridge 161:aa5281ff4a02 442 * This filter can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 161:aa5281ff4a02 443 * @rmtoll FLTR DNF LL_I2C_SetDigitalFilter
AnnaBridge 161:aa5281ff4a02 444 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 445 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
AnnaBridge 161:aa5281ff4a02 446 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
AnnaBridge 161:aa5281ff4a02 447 * @retval None
AnnaBridge 161:aa5281ff4a02 448 */
AnnaBridge 161:aa5281ff4a02 449 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
AnnaBridge 161:aa5281ff4a02 450 {
AnnaBridge 161:aa5281ff4a02 451 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_DNF, DigitalFilter);
AnnaBridge 161:aa5281ff4a02 452 }
AnnaBridge 161:aa5281ff4a02 453
AnnaBridge 161:aa5281ff4a02 454 /**
AnnaBridge 161:aa5281ff4a02 455 * @brief Get the current Digital Noise Filter configuration.
AnnaBridge 161:aa5281ff4a02 456 * @rmtoll FLTR DNF LL_I2C_GetDigitalFilter
AnnaBridge 161:aa5281ff4a02 457 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 458 * @retval Value between Min_Data=0x0 and Max_Data=0xF
AnnaBridge 161:aa5281ff4a02 459 */
AnnaBridge 161:aa5281ff4a02 460 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 461 {
AnnaBridge 161:aa5281ff4a02 462 return (uint32_t)(READ_BIT(I2Cx->FLTR, I2C_FLTR_DNF));
AnnaBridge 161:aa5281ff4a02 463 }
AnnaBridge 161:aa5281ff4a02 464 #endif
AnnaBridge 161:aa5281ff4a02 465 #if defined(I2C_FLTR_ANOFF)
AnnaBridge 161:aa5281ff4a02 466
AnnaBridge 161:aa5281ff4a02 467 /**
AnnaBridge 161:aa5281ff4a02 468 * @brief Enable Analog Noise Filter.
AnnaBridge 161:aa5281ff4a02 469 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 161:aa5281ff4a02 470 * @rmtoll FLTR ANOFF LL_I2C_EnableAnalogFilter
AnnaBridge 161:aa5281ff4a02 471 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 472 * @retval None
AnnaBridge 161:aa5281ff4a02 473 */
AnnaBridge 161:aa5281ff4a02 474 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 475 {
AnnaBridge 161:aa5281ff4a02 476 CLEAR_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
AnnaBridge 161:aa5281ff4a02 477 }
AnnaBridge 161:aa5281ff4a02 478
AnnaBridge 161:aa5281ff4a02 479 /**
AnnaBridge 161:aa5281ff4a02 480 * @brief Disable Analog Noise Filter.
AnnaBridge 161:aa5281ff4a02 481 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 161:aa5281ff4a02 482 * @rmtoll FLTR ANOFF LL_I2C_DisableAnalogFilter
AnnaBridge 161:aa5281ff4a02 483 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 484 * @retval None
AnnaBridge 161:aa5281ff4a02 485 */
AnnaBridge 161:aa5281ff4a02 486 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 487 {
AnnaBridge 161:aa5281ff4a02 488 SET_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
AnnaBridge 161:aa5281ff4a02 489 }
AnnaBridge 161:aa5281ff4a02 490
AnnaBridge 161:aa5281ff4a02 491 /**
AnnaBridge 161:aa5281ff4a02 492 * @brief Check if Analog Noise Filter is enabled or disabled.
AnnaBridge 161:aa5281ff4a02 493 * @rmtoll FLTR ANOFF LL_I2C_IsEnabledAnalogFilter
AnnaBridge 161:aa5281ff4a02 494 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 495 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 496 */
AnnaBridge 161:aa5281ff4a02 497 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 498 {
AnnaBridge 161:aa5281ff4a02 499 return (READ_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF) == (I2C_FLTR_ANOFF));
AnnaBridge 161:aa5281ff4a02 500 }
AnnaBridge 161:aa5281ff4a02 501 #endif
AnnaBridge 161:aa5281ff4a02 502
AnnaBridge 161:aa5281ff4a02 503 /**
AnnaBridge 161:aa5281ff4a02 504 * @brief Enable DMA transmission requests.
AnnaBridge 161:aa5281ff4a02 505 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
AnnaBridge 161:aa5281ff4a02 506 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 507 * @retval None
AnnaBridge 161:aa5281ff4a02 508 */
AnnaBridge 161:aa5281ff4a02 509 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 510 {
AnnaBridge 161:aa5281ff4a02 511 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge 161:aa5281ff4a02 512 }
AnnaBridge 161:aa5281ff4a02 513
AnnaBridge 161:aa5281ff4a02 514 /**
AnnaBridge 161:aa5281ff4a02 515 * @brief Disable DMA transmission requests.
AnnaBridge 161:aa5281ff4a02 516 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
AnnaBridge 161:aa5281ff4a02 517 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 518 * @retval None
AnnaBridge 161:aa5281ff4a02 519 */
AnnaBridge 161:aa5281ff4a02 520 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 521 {
AnnaBridge 161:aa5281ff4a02 522 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge 161:aa5281ff4a02 523 }
AnnaBridge 161:aa5281ff4a02 524
AnnaBridge 161:aa5281ff4a02 525 /**
AnnaBridge 161:aa5281ff4a02 526 * @brief Check if DMA transmission requests are enabled or disabled.
AnnaBridge 161:aa5281ff4a02 527 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
AnnaBridge 161:aa5281ff4a02 528 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 529 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 530 */
AnnaBridge 161:aa5281ff4a02 531 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 532 {
AnnaBridge 161:aa5281ff4a02 533 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
AnnaBridge 161:aa5281ff4a02 534 }
AnnaBridge 161:aa5281ff4a02 535
AnnaBridge 161:aa5281ff4a02 536 /**
AnnaBridge 161:aa5281ff4a02 537 * @brief Enable DMA reception requests.
AnnaBridge 161:aa5281ff4a02 538 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
AnnaBridge 161:aa5281ff4a02 539 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 540 * @retval None
AnnaBridge 161:aa5281ff4a02 541 */
AnnaBridge 161:aa5281ff4a02 542 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 543 {
AnnaBridge 161:aa5281ff4a02 544 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge 161:aa5281ff4a02 545 }
AnnaBridge 161:aa5281ff4a02 546
AnnaBridge 161:aa5281ff4a02 547 /**
AnnaBridge 161:aa5281ff4a02 548 * @brief Disable DMA reception requests.
AnnaBridge 161:aa5281ff4a02 549 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
AnnaBridge 161:aa5281ff4a02 550 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 551 * @retval None
AnnaBridge 161:aa5281ff4a02 552 */
AnnaBridge 161:aa5281ff4a02 553 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 554 {
AnnaBridge 161:aa5281ff4a02 555 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge 161:aa5281ff4a02 556 }
AnnaBridge 161:aa5281ff4a02 557
AnnaBridge 161:aa5281ff4a02 558 /**
AnnaBridge 161:aa5281ff4a02 559 * @brief Check if DMA reception requests are enabled or disabled.
AnnaBridge 161:aa5281ff4a02 560 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
AnnaBridge 161:aa5281ff4a02 561 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 562 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 563 */
AnnaBridge 161:aa5281ff4a02 564 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 565 {
AnnaBridge 161:aa5281ff4a02 566 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
AnnaBridge 161:aa5281ff4a02 567 }
AnnaBridge 161:aa5281ff4a02 568
AnnaBridge 161:aa5281ff4a02 569 /**
AnnaBridge 161:aa5281ff4a02 570 * @brief Get the data register address used for DMA transfer.
AnnaBridge 161:aa5281ff4a02 571 * @rmtoll DR DR LL_I2C_DMA_GetRegAddr
AnnaBridge 161:aa5281ff4a02 572 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 573 * @retval Address of data register
AnnaBridge 161:aa5281ff4a02 574 */
AnnaBridge 161:aa5281ff4a02 575 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 576 {
AnnaBridge 161:aa5281ff4a02 577 return (uint32_t) & (I2Cx->DR);
AnnaBridge 161:aa5281ff4a02 578 }
AnnaBridge 161:aa5281ff4a02 579
AnnaBridge 161:aa5281ff4a02 580 /**
AnnaBridge 161:aa5281ff4a02 581 * @brief Enable Clock stretching.
AnnaBridge 161:aa5281ff4a02 582 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 161:aa5281ff4a02 583 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
AnnaBridge 161:aa5281ff4a02 584 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 585 * @retval None
AnnaBridge 161:aa5281ff4a02 586 */
AnnaBridge 161:aa5281ff4a02 587 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 588 {
AnnaBridge 161:aa5281ff4a02 589 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
AnnaBridge 161:aa5281ff4a02 590 }
AnnaBridge 161:aa5281ff4a02 591
AnnaBridge 161:aa5281ff4a02 592 /**
AnnaBridge 161:aa5281ff4a02 593 * @brief Disable Clock stretching.
AnnaBridge 161:aa5281ff4a02 594 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 161:aa5281ff4a02 595 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
AnnaBridge 161:aa5281ff4a02 596 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 597 * @retval None
AnnaBridge 161:aa5281ff4a02 598 */
AnnaBridge 161:aa5281ff4a02 599 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 600 {
AnnaBridge 161:aa5281ff4a02 601 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
AnnaBridge 161:aa5281ff4a02 602 }
AnnaBridge 161:aa5281ff4a02 603
AnnaBridge 161:aa5281ff4a02 604 /**
AnnaBridge 161:aa5281ff4a02 605 * @brief Check if Clock stretching is enabled or disabled.
AnnaBridge 161:aa5281ff4a02 606 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
AnnaBridge 161:aa5281ff4a02 607 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 608 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 609 */
AnnaBridge 161:aa5281ff4a02 610 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 611 {
AnnaBridge 161:aa5281ff4a02 612 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
AnnaBridge 161:aa5281ff4a02 613 }
AnnaBridge 161:aa5281ff4a02 614
AnnaBridge 161:aa5281ff4a02 615 /**
AnnaBridge 161:aa5281ff4a02 616 * @brief Enable General Call.
AnnaBridge 161:aa5281ff4a02 617 * @note When enabled the Address 0x00 is ACKed.
AnnaBridge 161:aa5281ff4a02 618 * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
AnnaBridge 161:aa5281ff4a02 619 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 620 * @retval None
AnnaBridge 161:aa5281ff4a02 621 */
AnnaBridge 161:aa5281ff4a02 622 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 623 {
AnnaBridge 161:aa5281ff4a02 624 SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
AnnaBridge 161:aa5281ff4a02 625 }
AnnaBridge 161:aa5281ff4a02 626
AnnaBridge 161:aa5281ff4a02 627 /**
AnnaBridge 161:aa5281ff4a02 628 * @brief Disable General Call.
AnnaBridge 161:aa5281ff4a02 629 * @note When disabled the Address 0x00 is NACKed.
AnnaBridge 161:aa5281ff4a02 630 * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
AnnaBridge 161:aa5281ff4a02 631 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 632 * @retval None
AnnaBridge 161:aa5281ff4a02 633 */
AnnaBridge 161:aa5281ff4a02 634 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 635 {
AnnaBridge 161:aa5281ff4a02 636 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
AnnaBridge 161:aa5281ff4a02 637 }
AnnaBridge 161:aa5281ff4a02 638
AnnaBridge 161:aa5281ff4a02 639 /**
AnnaBridge 161:aa5281ff4a02 640 * @brief Check if General Call is enabled or disabled.
AnnaBridge 161:aa5281ff4a02 641 * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
AnnaBridge 161:aa5281ff4a02 642 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 643 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 644 */
AnnaBridge 161:aa5281ff4a02 645 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 646 {
AnnaBridge 161:aa5281ff4a02 647 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
AnnaBridge 161:aa5281ff4a02 648 }
AnnaBridge 161:aa5281ff4a02 649
AnnaBridge 161:aa5281ff4a02 650 /**
AnnaBridge 161:aa5281ff4a02 651 * @brief Set the Own Address1.
AnnaBridge 161:aa5281ff4a02 652 * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
AnnaBridge 161:aa5281ff4a02 653 * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
AnnaBridge 161:aa5281ff4a02 654 * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
AnnaBridge 161:aa5281ff4a02 655 * OAR1 ADDMODE LL_I2C_SetOwnAddress1
AnnaBridge 161:aa5281ff4a02 656 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 657 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
AnnaBridge 161:aa5281ff4a02 658 * @param OwnAddrSize This parameter can be one of the following values:
AnnaBridge 161:aa5281ff4a02 659 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
AnnaBridge 161:aa5281ff4a02 660 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
AnnaBridge 161:aa5281ff4a02 661 * @retval None
AnnaBridge 161:aa5281ff4a02 662 */
AnnaBridge 161:aa5281ff4a02 663 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
AnnaBridge 161:aa5281ff4a02 664 {
AnnaBridge 161:aa5281ff4a02 665 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
AnnaBridge 161:aa5281ff4a02 666 }
AnnaBridge 161:aa5281ff4a02 667
AnnaBridge 161:aa5281ff4a02 668 /**
AnnaBridge 161:aa5281ff4a02 669 * @brief Set the 7bits Own Address2.
AnnaBridge 161:aa5281ff4a02 670 * @note This action has no effect if own address2 is enabled.
AnnaBridge 161:aa5281ff4a02 671 * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
AnnaBridge 161:aa5281ff4a02 672 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 673 * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
AnnaBridge 161:aa5281ff4a02 674 * @retval None
AnnaBridge 161:aa5281ff4a02 675 */
AnnaBridge 161:aa5281ff4a02 676 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
AnnaBridge 161:aa5281ff4a02 677 {
AnnaBridge 161:aa5281ff4a02 678 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
AnnaBridge 161:aa5281ff4a02 679 }
AnnaBridge 161:aa5281ff4a02 680
AnnaBridge 161:aa5281ff4a02 681 /**
AnnaBridge 161:aa5281ff4a02 682 * @brief Enable acknowledge on Own Address2 match address.
AnnaBridge 161:aa5281ff4a02 683 * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
AnnaBridge 161:aa5281ff4a02 684 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 685 * @retval None
AnnaBridge 161:aa5281ff4a02 686 */
AnnaBridge 161:aa5281ff4a02 687 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 688 {
AnnaBridge 161:aa5281ff4a02 689 SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
AnnaBridge 161:aa5281ff4a02 690 }
AnnaBridge 161:aa5281ff4a02 691
AnnaBridge 161:aa5281ff4a02 692 /**
AnnaBridge 161:aa5281ff4a02 693 * @brief Disable acknowledge on Own Address2 match address.
AnnaBridge 161:aa5281ff4a02 694 * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
AnnaBridge 161:aa5281ff4a02 695 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 696 * @retval None
AnnaBridge 161:aa5281ff4a02 697 */
AnnaBridge 161:aa5281ff4a02 698 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 699 {
AnnaBridge 161:aa5281ff4a02 700 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
AnnaBridge 161:aa5281ff4a02 701 }
AnnaBridge 161:aa5281ff4a02 702
AnnaBridge 161:aa5281ff4a02 703 /**
AnnaBridge 161:aa5281ff4a02 704 * @brief Check if Own Address1 acknowledge is enabled or disabled.
AnnaBridge 161:aa5281ff4a02 705 * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
AnnaBridge 161:aa5281ff4a02 706 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 707 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 708 */
AnnaBridge 161:aa5281ff4a02 709 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 710 {
AnnaBridge 161:aa5281ff4a02 711 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
AnnaBridge 161:aa5281ff4a02 712 }
AnnaBridge 161:aa5281ff4a02 713
AnnaBridge 161:aa5281ff4a02 714 /**
AnnaBridge 161:aa5281ff4a02 715 * @brief Configure the Peripheral clock frequency.
AnnaBridge 161:aa5281ff4a02 716 * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
AnnaBridge 161:aa5281ff4a02 717 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 718 * @param PeriphClock Peripheral Clock (in Hz)
AnnaBridge 161:aa5281ff4a02 719 * @retval None
AnnaBridge 161:aa5281ff4a02 720 */
AnnaBridge 161:aa5281ff4a02 721 __STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
AnnaBridge 161:aa5281ff4a02 722 {
AnnaBridge 161:aa5281ff4a02 723 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
AnnaBridge 161:aa5281ff4a02 724 }
AnnaBridge 161:aa5281ff4a02 725
AnnaBridge 161:aa5281ff4a02 726 /**
AnnaBridge 161:aa5281ff4a02 727 * @brief Get the Peripheral clock frequency.
AnnaBridge 161:aa5281ff4a02 728 * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
AnnaBridge 161:aa5281ff4a02 729 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 730 * @retval Value of Peripheral Clock (in Hz)
AnnaBridge 161:aa5281ff4a02 731 */
AnnaBridge 161:aa5281ff4a02 732 __STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 733 {
AnnaBridge 161:aa5281ff4a02 734 return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
AnnaBridge 161:aa5281ff4a02 735 }
AnnaBridge 161:aa5281ff4a02 736
AnnaBridge 161:aa5281ff4a02 737 /**
AnnaBridge 161:aa5281ff4a02 738 * @brief Configure the Duty cycle (Fast mode only).
AnnaBridge 161:aa5281ff4a02 739 * @rmtoll CCR DUTY LL_I2C_SetDutyCycle
AnnaBridge 161:aa5281ff4a02 740 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 741 * @param DutyCycle This parameter can be one of the following values:
AnnaBridge 161:aa5281ff4a02 742 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 161:aa5281ff4a02 743 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 161:aa5281ff4a02 744 * @retval None
AnnaBridge 161:aa5281ff4a02 745 */
AnnaBridge 161:aa5281ff4a02 746 __STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
AnnaBridge 161:aa5281ff4a02 747 {
AnnaBridge 161:aa5281ff4a02 748 MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
AnnaBridge 161:aa5281ff4a02 749 }
AnnaBridge 161:aa5281ff4a02 750
AnnaBridge 161:aa5281ff4a02 751 /**
AnnaBridge 161:aa5281ff4a02 752 * @brief Get the Duty cycle (Fast mode only).
AnnaBridge 161:aa5281ff4a02 753 * @rmtoll CCR DUTY LL_I2C_GetDutyCycle
AnnaBridge 161:aa5281ff4a02 754 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 755 * @retval Returned value can be one of the following values:
AnnaBridge 161:aa5281ff4a02 756 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 161:aa5281ff4a02 757 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 161:aa5281ff4a02 758 */
AnnaBridge 161:aa5281ff4a02 759 __STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 760 {
AnnaBridge 161:aa5281ff4a02 761 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
AnnaBridge 161:aa5281ff4a02 762 }
AnnaBridge 161:aa5281ff4a02 763
AnnaBridge 161:aa5281ff4a02 764 /**
AnnaBridge 161:aa5281ff4a02 765 * @brief Configure the I2C master clock speed mode.
AnnaBridge 161:aa5281ff4a02 766 * @rmtoll CCR FS LL_I2C_SetClockSpeedMode
AnnaBridge 161:aa5281ff4a02 767 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 768 * @param ClockSpeedMode This parameter can be one of the following values:
AnnaBridge 161:aa5281ff4a02 769 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
AnnaBridge 161:aa5281ff4a02 770 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
AnnaBridge 161:aa5281ff4a02 771 * @retval None
AnnaBridge 161:aa5281ff4a02 772 */
AnnaBridge 161:aa5281ff4a02 773 __STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
AnnaBridge 161:aa5281ff4a02 774 {
AnnaBridge 161:aa5281ff4a02 775 MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
AnnaBridge 161:aa5281ff4a02 776 }
AnnaBridge 161:aa5281ff4a02 777
AnnaBridge 161:aa5281ff4a02 778 /**
AnnaBridge 161:aa5281ff4a02 779 * @brief Get the the I2C master speed mode.
AnnaBridge 161:aa5281ff4a02 780 * @rmtoll CCR FS LL_I2C_GetClockSpeedMode
AnnaBridge 161:aa5281ff4a02 781 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 782 * @retval Returned value can be one of the following values:
AnnaBridge 161:aa5281ff4a02 783 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
AnnaBridge 161:aa5281ff4a02 784 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
AnnaBridge 161:aa5281ff4a02 785 */
AnnaBridge 161:aa5281ff4a02 786 __STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 787 {
AnnaBridge 161:aa5281ff4a02 788 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
AnnaBridge 161:aa5281ff4a02 789 }
AnnaBridge 161:aa5281ff4a02 790
AnnaBridge 161:aa5281ff4a02 791 /**
AnnaBridge 161:aa5281ff4a02 792 * @brief Configure the SCL, SDA rising time.
AnnaBridge 161:aa5281ff4a02 793 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 161:aa5281ff4a02 794 * @rmtoll TRISE TRISE LL_I2C_SetRiseTime
AnnaBridge 161:aa5281ff4a02 795 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 796 * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
AnnaBridge 161:aa5281ff4a02 797 * @retval None
AnnaBridge 161:aa5281ff4a02 798 */
AnnaBridge 161:aa5281ff4a02 799 __STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
AnnaBridge 161:aa5281ff4a02 800 {
AnnaBridge 161:aa5281ff4a02 801 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
AnnaBridge 161:aa5281ff4a02 802 }
AnnaBridge 161:aa5281ff4a02 803
AnnaBridge 161:aa5281ff4a02 804 /**
AnnaBridge 161:aa5281ff4a02 805 * @brief Get the SCL, SDA rising time.
AnnaBridge 161:aa5281ff4a02 806 * @rmtoll TRISE TRISE LL_I2C_GetRiseTime
AnnaBridge 161:aa5281ff4a02 807 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 808 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
AnnaBridge 161:aa5281ff4a02 809 */
AnnaBridge 161:aa5281ff4a02 810 __STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 811 {
AnnaBridge 161:aa5281ff4a02 812 return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
AnnaBridge 161:aa5281ff4a02 813 }
AnnaBridge 161:aa5281ff4a02 814
AnnaBridge 161:aa5281ff4a02 815 /**
AnnaBridge 161:aa5281ff4a02 816 * @brief Configure the SCL high and low period.
AnnaBridge 161:aa5281ff4a02 817 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 161:aa5281ff4a02 818 * @rmtoll CCR CCR LL_I2C_SetClockPeriod
AnnaBridge 161:aa5281ff4a02 819 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 820 * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge 161:aa5281ff4a02 821 * @retval None
AnnaBridge 161:aa5281ff4a02 822 */
AnnaBridge 161:aa5281ff4a02 823 __STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
AnnaBridge 161:aa5281ff4a02 824 {
AnnaBridge 161:aa5281ff4a02 825 MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
AnnaBridge 161:aa5281ff4a02 826 }
AnnaBridge 161:aa5281ff4a02 827
AnnaBridge 161:aa5281ff4a02 828 /**
AnnaBridge 161:aa5281ff4a02 829 * @brief Get the SCL high and low period.
AnnaBridge 161:aa5281ff4a02 830 * @rmtoll CCR CCR LL_I2C_GetClockPeriod
AnnaBridge 161:aa5281ff4a02 831 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 832 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge 161:aa5281ff4a02 833 */
AnnaBridge 161:aa5281ff4a02 834 __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 835 {
AnnaBridge 161:aa5281ff4a02 836 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
AnnaBridge 161:aa5281ff4a02 837 }
AnnaBridge 161:aa5281ff4a02 838
AnnaBridge 161:aa5281ff4a02 839 /**
AnnaBridge 161:aa5281ff4a02 840 * @brief Configure the SCL speed.
AnnaBridge 161:aa5281ff4a02 841 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 161:aa5281ff4a02 842 * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
AnnaBridge 161:aa5281ff4a02 843 * TRISE TRISE LL_I2C_ConfigSpeed\n
AnnaBridge 161:aa5281ff4a02 844 * CCR FS LL_I2C_ConfigSpeed\n
AnnaBridge 161:aa5281ff4a02 845 * CCR DUTY LL_I2C_ConfigSpeed\n
AnnaBridge 161:aa5281ff4a02 846 * CCR CCR LL_I2C_ConfigSpeed
AnnaBridge 161:aa5281ff4a02 847 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 848 * @param PeriphClock Peripheral Clock (in Hz)
AnnaBridge 161:aa5281ff4a02 849 * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge 161:aa5281ff4a02 850 * @param DutyCycle This parameter can be one of the following values:
AnnaBridge 161:aa5281ff4a02 851 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 161:aa5281ff4a02 852 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 161:aa5281ff4a02 853 * @retval None
AnnaBridge 161:aa5281ff4a02 854 */
AnnaBridge 161:aa5281ff4a02 855 __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
AnnaBridge 161:aa5281ff4a02 856 uint32_t DutyCycle)
AnnaBridge 161:aa5281ff4a02 857 {
AnnaBridge 161:aa5281ff4a02 858 register uint32_t freqrange = 0x0U;
AnnaBridge 161:aa5281ff4a02 859 register uint32_t clockconfig = 0x0U;
AnnaBridge 161:aa5281ff4a02 860
AnnaBridge 161:aa5281ff4a02 861 /* Compute frequency range */
AnnaBridge 161:aa5281ff4a02 862 freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
AnnaBridge 161:aa5281ff4a02 863
AnnaBridge 161:aa5281ff4a02 864 /* Configure I2Cx: Frequency range register */
AnnaBridge 161:aa5281ff4a02 865 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
AnnaBridge 161:aa5281ff4a02 866
AnnaBridge 161:aa5281ff4a02 867 /* Configure I2Cx: Rise Time register */
AnnaBridge 161:aa5281ff4a02 868 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
AnnaBridge 161:aa5281ff4a02 869
AnnaBridge 161:aa5281ff4a02 870 /* Configure Speed mode, Duty Cycle and Clock control register value */
AnnaBridge 161:aa5281ff4a02 871 if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
AnnaBridge 161:aa5281ff4a02 872 {
AnnaBridge 161:aa5281ff4a02 873 /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
AnnaBridge 161:aa5281ff4a02 874 clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
AnnaBridge 161:aa5281ff4a02 875 __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
AnnaBridge 161:aa5281ff4a02 876 DutyCycle;
AnnaBridge 161:aa5281ff4a02 877 }
AnnaBridge 161:aa5281ff4a02 878 else
AnnaBridge 161:aa5281ff4a02 879 {
AnnaBridge 161:aa5281ff4a02 880 /* Set Speed mode at standard for Clock Speed request in standard clock range */
AnnaBridge 161:aa5281ff4a02 881 clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
AnnaBridge 161:aa5281ff4a02 882 __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
AnnaBridge 161:aa5281ff4a02 883 }
AnnaBridge 161:aa5281ff4a02 884
AnnaBridge 161:aa5281ff4a02 885 /* Configure I2Cx: Clock control register */
AnnaBridge 161:aa5281ff4a02 886 MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
AnnaBridge 161:aa5281ff4a02 887 }
AnnaBridge 161:aa5281ff4a02 888
AnnaBridge 161:aa5281ff4a02 889 /**
AnnaBridge 161:aa5281ff4a02 890 * @brief Configure peripheral mode.
AnnaBridge 161:aa5281ff4a02 891 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 892 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 893 * @rmtoll CR1 SMBUS LL_I2C_SetMode\n
AnnaBridge 161:aa5281ff4a02 894 * CR1 SMBTYPE LL_I2C_SetMode\n
AnnaBridge 161:aa5281ff4a02 895 * CR1 ENARP LL_I2C_SetMode
AnnaBridge 161:aa5281ff4a02 896 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 897 * @param PeripheralMode This parameter can be one of the following values:
AnnaBridge 161:aa5281ff4a02 898 * @arg @ref LL_I2C_MODE_I2C
AnnaBridge 161:aa5281ff4a02 899 * @arg @ref LL_I2C_MODE_SMBUS_HOST
AnnaBridge 161:aa5281ff4a02 900 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
AnnaBridge 161:aa5281ff4a02 901 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
AnnaBridge 161:aa5281ff4a02 902 * @retval None
AnnaBridge 161:aa5281ff4a02 903 */
AnnaBridge 161:aa5281ff4a02 904 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
AnnaBridge 161:aa5281ff4a02 905 {
AnnaBridge 161:aa5281ff4a02 906 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
AnnaBridge 161:aa5281ff4a02 907 }
AnnaBridge 161:aa5281ff4a02 908
AnnaBridge 161:aa5281ff4a02 909 /**
AnnaBridge 161:aa5281ff4a02 910 * @brief Get peripheral mode.
AnnaBridge 161:aa5281ff4a02 911 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 912 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 913 * @rmtoll CR1 SMBUS LL_I2C_GetMode\n
AnnaBridge 161:aa5281ff4a02 914 * CR1 SMBTYPE LL_I2C_GetMode\n
AnnaBridge 161:aa5281ff4a02 915 * CR1 ENARP LL_I2C_GetMode
AnnaBridge 161:aa5281ff4a02 916 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 917 * @retval Returned value can be one of the following values:
AnnaBridge 161:aa5281ff4a02 918 * @arg @ref LL_I2C_MODE_I2C
AnnaBridge 161:aa5281ff4a02 919 * @arg @ref LL_I2C_MODE_SMBUS_HOST
AnnaBridge 161:aa5281ff4a02 920 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
AnnaBridge 161:aa5281ff4a02 921 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
AnnaBridge 161:aa5281ff4a02 922 */
AnnaBridge 161:aa5281ff4a02 923 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 924 {
AnnaBridge 161:aa5281ff4a02 925 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
AnnaBridge 161:aa5281ff4a02 926 }
AnnaBridge 161:aa5281ff4a02 927
AnnaBridge 161:aa5281ff4a02 928 /**
AnnaBridge 161:aa5281ff4a02 929 * @brief Enable SMBus alert (Host or Device mode)
AnnaBridge 161:aa5281ff4a02 930 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 931 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 932 * @note SMBus Device mode:
AnnaBridge 161:aa5281ff4a02 933 * - SMBus Alert pin is drived low and
AnnaBridge 161:aa5281ff4a02 934 * Alert Response Address Header acknowledge is enabled.
AnnaBridge 161:aa5281ff4a02 935 * SMBus Host mode:
AnnaBridge 161:aa5281ff4a02 936 * - SMBus Alert pin management is supported.
AnnaBridge 161:aa5281ff4a02 937 * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
AnnaBridge 161:aa5281ff4a02 938 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 939 * @retval None
AnnaBridge 161:aa5281ff4a02 940 */
AnnaBridge 161:aa5281ff4a02 941 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 942 {
AnnaBridge 161:aa5281ff4a02 943 SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
AnnaBridge 161:aa5281ff4a02 944 }
AnnaBridge 161:aa5281ff4a02 945
AnnaBridge 161:aa5281ff4a02 946 /**
AnnaBridge 161:aa5281ff4a02 947 * @brief Disable SMBus alert (Host or Device mode)
AnnaBridge 161:aa5281ff4a02 948 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 949 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 950 * @note SMBus Device mode:
AnnaBridge 161:aa5281ff4a02 951 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
AnnaBridge 161:aa5281ff4a02 952 * Alert Response Address Header acknowledge is disabled.
AnnaBridge 161:aa5281ff4a02 953 * SMBus Host mode:
AnnaBridge 161:aa5281ff4a02 954 * - SMBus Alert pin management is not supported.
AnnaBridge 161:aa5281ff4a02 955 * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
AnnaBridge 161:aa5281ff4a02 956 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 957 * @retval None
AnnaBridge 161:aa5281ff4a02 958 */
AnnaBridge 161:aa5281ff4a02 959 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 960 {
AnnaBridge 161:aa5281ff4a02 961 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
AnnaBridge 161:aa5281ff4a02 962 }
AnnaBridge 161:aa5281ff4a02 963
AnnaBridge 161:aa5281ff4a02 964 /**
AnnaBridge 161:aa5281ff4a02 965 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
AnnaBridge 161:aa5281ff4a02 966 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 967 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 968 * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
AnnaBridge 161:aa5281ff4a02 969 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 970 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 971 */
AnnaBridge 161:aa5281ff4a02 972 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 973 {
AnnaBridge 161:aa5281ff4a02 974 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
AnnaBridge 161:aa5281ff4a02 975 }
AnnaBridge 161:aa5281ff4a02 976
AnnaBridge 161:aa5281ff4a02 977 /**
AnnaBridge 161:aa5281ff4a02 978 * @brief Enable SMBus Packet Error Calculation (PEC).
AnnaBridge 161:aa5281ff4a02 979 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 980 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 981 * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
AnnaBridge 161:aa5281ff4a02 982 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 983 * @retval None
AnnaBridge 161:aa5281ff4a02 984 */
AnnaBridge 161:aa5281ff4a02 985 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 986 {
AnnaBridge 161:aa5281ff4a02 987 SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
AnnaBridge 161:aa5281ff4a02 988 }
AnnaBridge 161:aa5281ff4a02 989
AnnaBridge 161:aa5281ff4a02 990 /**
AnnaBridge 161:aa5281ff4a02 991 * @brief Disable SMBus Packet Error Calculation (PEC).
AnnaBridge 161:aa5281ff4a02 992 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 993 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 994 * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
AnnaBridge 161:aa5281ff4a02 995 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 996 * @retval None
AnnaBridge 161:aa5281ff4a02 997 */
AnnaBridge 161:aa5281ff4a02 998 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 999 {
AnnaBridge 161:aa5281ff4a02 1000 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
AnnaBridge 161:aa5281ff4a02 1001 }
AnnaBridge 161:aa5281ff4a02 1002
AnnaBridge 161:aa5281ff4a02 1003 /**
AnnaBridge 161:aa5281ff4a02 1004 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
AnnaBridge 161:aa5281ff4a02 1005 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1006 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1007 * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
AnnaBridge 161:aa5281ff4a02 1008 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1009 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1010 */
AnnaBridge 161:aa5281ff4a02 1011 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1012 {
AnnaBridge 161:aa5281ff4a02 1013 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
AnnaBridge 161:aa5281ff4a02 1014 }
AnnaBridge 161:aa5281ff4a02 1015
AnnaBridge 161:aa5281ff4a02 1016 /**
AnnaBridge 161:aa5281ff4a02 1017 * @}
AnnaBridge 161:aa5281ff4a02 1018 */
AnnaBridge 161:aa5281ff4a02 1019
AnnaBridge 161:aa5281ff4a02 1020 /** @defgroup I2C_LL_EF_IT_Management IT_Management
AnnaBridge 161:aa5281ff4a02 1021 * @{
AnnaBridge 161:aa5281ff4a02 1022 */
AnnaBridge 161:aa5281ff4a02 1023
AnnaBridge 161:aa5281ff4a02 1024 /**
AnnaBridge 161:aa5281ff4a02 1025 * @brief Enable TXE interrupt.
AnnaBridge 161:aa5281ff4a02 1026 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
AnnaBridge 161:aa5281ff4a02 1027 * CR2 ITBUFEN LL_I2C_EnableIT_TX
AnnaBridge 161:aa5281ff4a02 1028 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1029 * @retval None
AnnaBridge 161:aa5281ff4a02 1030 */
AnnaBridge 161:aa5281ff4a02 1031 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1032 {
AnnaBridge 161:aa5281ff4a02 1033 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
AnnaBridge 161:aa5281ff4a02 1034 }
AnnaBridge 161:aa5281ff4a02 1035
AnnaBridge 161:aa5281ff4a02 1036 /**
AnnaBridge 161:aa5281ff4a02 1037 * @brief Disable TXE interrupt.
AnnaBridge 161:aa5281ff4a02 1038 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
AnnaBridge 161:aa5281ff4a02 1039 * CR2 ITBUFEN LL_I2C_DisableIT_TX
AnnaBridge 161:aa5281ff4a02 1040 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1041 * @retval None
AnnaBridge 161:aa5281ff4a02 1042 */
AnnaBridge 161:aa5281ff4a02 1043 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1044 {
AnnaBridge 161:aa5281ff4a02 1045 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
AnnaBridge 161:aa5281ff4a02 1046 }
AnnaBridge 161:aa5281ff4a02 1047
AnnaBridge 161:aa5281ff4a02 1048 /**
AnnaBridge 161:aa5281ff4a02 1049 * @brief Check if the TXE Interrupt is enabled or disabled.
AnnaBridge 161:aa5281ff4a02 1050 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
AnnaBridge 161:aa5281ff4a02 1051 * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
AnnaBridge 161:aa5281ff4a02 1052 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1053 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1054 */
AnnaBridge 161:aa5281ff4a02 1055 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1056 {
AnnaBridge 161:aa5281ff4a02 1057 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
AnnaBridge 161:aa5281ff4a02 1058 }
AnnaBridge 161:aa5281ff4a02 1059
AnnaBridge 161:aa5281ff4a02 1060 /**
AnnaBridge 161:aa5281ff4a02 1061 * @brief Enable RXNE interrupt.
AnnaBridge 161:aa5281ff4a02 1062 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
AnnaBridge 161:aa5281ff4a02 1063 * CR2 ITBUFEN LL_I2C_EnableIT_RX
AnnaBridge 161:aa5281ff4a02 1064 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1065 * @retval None
AnnaBridge 161:aa5281ff4a02 1066 */
AnnaBridge 161:aa5281ff4a02 1067 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1068 {
AnnaBridge 161:aa5281ff4a02 1069 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
AnnaBridge 161:aa5281ff4a02 1070 }
AnnaBridge 161:aa5281ff4a02 1071
AnnaBridge 161:aa5281ff4a02 1072 /**
AnnaBridge 161:aa5281ff4a02 1073 * @brief Disable RXNE interrupt.
AnnaBridge 161:aa5281ff4a02 1074 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
AnnaBridge 161:aa5281ff4a02 1075 * CR2 ITBUFEN LL_I2C_DisableIT_RX
AnnaBridge 161:aa5281ff4a02 1076 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1077 * @retval None
AnnaBridge 161:aa5281ff4a02 1078 */
AnnaBridge 161:aa5281ff4a02 1079 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1080 {
AnnaBridge 161:aa5281ff4a02 1081 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
AnnaBridge 161:aa5281ff4a02 1082 }
AnnaBridge 161:aa5281ff4a02 1083
AnnaBridge 161:aa5281ff4a02 1084 /**
AnnaBridge 161:aa5281ff4a02 1085 * @brief Check if the RXNE Interrupt is enabled or disabled.
AnnaBridge 161:aa5281ff4a02 1086 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
AnnaBridge 161:aa5281ff4a02 1087 * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
AnnaBridge 161:aa5281ff4a02 1088 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1089 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1090 */
AnnaBridge 161:aa5281ff4a02 1091 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1092 {
AnnaBridge 161:aa5281ff4a02 1093 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
AnnaBridge 161:aa5281ff4a02 1094 }
AnnaBridge 161:aa5281ff4a02 1095
AnnaBridge 161:aa5281ff4a02 1096 /**
AnnaBridge 161:aa5281ff4a02 1097 * @brief Enable Events interrupts.
AnnaBridge 161:aa5281ff4a02 1098 * @note Any of these events will generate interrupt :
AnnaBridge 161:aa5281ff4a02 1099 * Start Bit (SB)
AnnaBridge 161:aa5281ff4a02 1100 * Address sent, Address matched (ADDR)
AnnaBridge 161:aa5281ff4a02 1101 * 10-bit header sent (ADD10)
AnnaBridge 161:aa5281ff4a02 1102 * Stop detection (STOPF)
AnnaBridge 161:aa5281ff4a02 1103 * Byte transfer finished (BTF)
AnnaBridge 161:aa5281ff4a02 1104 *
AnnaBridge 161:aa5281ff4a02 1105 * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
AnnaBridge 161:aa5281ff4a02 1106 * Receive buffer not empty (RXNE)
AnnaBridge 161:aa5281ff4a02 1107 * Transmit buffer empty (TXE)
AnnaBridge 161:aa5281ff4a02 1108 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
AnnaBridge 161:aa5281ff4a02 1109 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1110 * @retval None
AnnaBridge 161:aa5281ff4a02 1111 */
AnnaBridge 161:aa5281ff4a02 1112 __STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1113 {
AnnaBridge 161:aa5281ff4a02 1114 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
AnnaBridge 161:aa5281ff4a02 1115 }
AnnaBridge 161:aa5281ff4a02 1116
AnnaBridge 161:aa5281ff4a02 1117 /**
AnnaBridge 161:aa5281ff4a02 1118 * @brief Disable Events interrupts.
AnnaBridge 161:aa5281ff4a02 1119 * @note Any of these events will generate interrupt :
AnnaBridge 161:aa5281ff4a02 1120 * Start Bit (SB)
AnnaBridge 161:aa5281ff4a02 1121 * Address sent, Address matched (ADDR)
AnnaBridge 161:aa5281ff4a02 1122 * 10-bit header sent (ADD10)
AnnaBridge 161:aa5281ff4a02 1123 * Stop detection (STOPF)
AnnaBridge 161:aa5281ff4a02 1124 * Byte transfer finished (BTF)
AnnaBridge 161:aa5281ff4a02 1125 * Receive buffer not empty (RXNE)
AnnaBridge 161:aa5281ff4a02 1126 * Transmit buffer empty (TXE)
AnnaBridge 161:aa5281ff4a02 1127 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
AnnaBridge 161:aa5281ff4a02 1128 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1129 * @retval None
AnnaBridge 161:aa5281ff4a02 1130 */
AnnaBridge 161:aa5281ff4a02 1131 __STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1132 {
AnnaBridge 161:aa5281ff4a02 1133 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
AnnaBridge 161:aa5281ff4a02 1134 }
AnnaBridge 161:aa5281ff4a02 1135
AnnaBridge 161:aa5281ff4a02 1136 /**
AnnaBridge 161:aa5281ff4a02 1137 * @brief Check if Events interrupts are enabled or disabled.
AnnaBridge 161:aa5281ff4a02 1138 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
AnnaBridge 161:aa5281ff4a02 1139 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1140 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1141 */
AnnaBridge 161:aa5281ff4a02 1142 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1143 {
AnnaBridge 161:aa5281ff4a02 1144 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
AnnaBridge 161:aa5281ff4a02 1145 }
AnnaBridge 161:aa5281ff4a02 1146
AnnaBridge 161:aa5281ff4a02 1147 /**
AnnaBridge 161:aa5281ff4a02 1148 * @brief Enable Buffer interrupts.
AnnaBridge 161:aa5281ff4a02 1149 * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
AnnaBridge 161:aa5281ff4a02 1150 * Receive buffer not empty (RXNE)
AnnaBridge 161:aa5281ff4a02 1151 * Transmit buffer empty (TXE)
AnnaBridge 161:aa5281ff4a02 1152 * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
AnnaBridge 161:aa5281ff4a02 1153 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1154 * @retval None
AnnaBridge 161:aa5281ff4a02 1155 */
AnnaBridge 161:aa5281ff4a02 1156 __STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1157 {
AnnaBridge 161:aa5281ff4a02 1158 SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
AnnaBridge 161:aa5281ff4a02 1159 }
AnnaBridge 161:aa5281ff4a02 1160
AnnaBridge 161:aa5281ff4a02 1161 /**
AnnaBridge 161:aa5281ff4a02 1162 * @brief Disable Buffer interrupts.
AnnaBridge 161:aa5281ff4a02 1163 * @note Any of these Buffer events will generate interrupt :
AnnaBridge 161:aa5281ff4a02 1164 * Receive buffer not empty (RXNE)
AnnaBridge 161:aa5281ff4a02 1165 * Transmit buffer empty (TXE)
AnnaBridge 161:aa5281ff4a02 1166 * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
AnnaBridge 161:aa5281ff4a02 1167 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1168 * @retval None
AnnaBridge 161:aa5281ff4a02 1169 */
AnnaBridge 161:aa5281ff4a02 1170 __STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1171 {
AnnaBridge 161:aa5281ff4a02 1172 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
AnnaBridge 161:aa5281ff4a02 1173 }
AnnaBridge 161:aa5281ff4a02 1174
AnnaBridge 161:aa5281ff4a02 1175 /**
AnnaBridge 161:aa5281ff4a02 1176 * @brief Check if Buffer interrupts are enabled or disabled.
AnnaBridge 161:aa5281ff4a02 1177 * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
AnnaBridge 161:aa5281ff4a02 1178 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1179 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1180 */
AnnaBridge 161:aa5281ff4a02 1181 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1182 {
AnnaBridge 161:aa5281ff4a02 1183 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
AnnaBridge 161:aa5281ff4a02 1184 }
AnnaBridge 161:aa5281ff4a02 1185
AnnaBridge 161:aa5281ff4a02 1186 /**
AnnaBridge 161:aa5281ff4a02 1187 * @brief Enable Error interrupts.
AnnaBridge 161:aa5281ff4a02 1188 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1189 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1190 * @note Any of these errors will generate interrupt :
AnnaBridge 161:aa5281ff4a02 1191 * Bus Error detection (BERR)
AnnaBridge 161:aa5281ff4a02 1192 * Arbitration Loss (ARLO)
AnnaBridge 161:aa5281ff4a02 1193 * Acknowledge Failure(AF)
AnnaBridge 161:aa5281ff4a02 1194 * Overrun/Underrun (OVR)
AnnaBridge 161:aa5281ff4a02 1195 * SMBus Timeout detection (TIMEOUT)
AnnaBridge 161:aa5281ff4a02 1196 * SMBus PEC error detection (PECERR)
AnnaBridge 161:aa5281ff4a02 1197 * SMBus Alert pin event detection (SMBALERT)
AnnaBridge 161:aa5281ff4a02 1198 * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
AnnaBridge 161:aa5281ff4a02 1199 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1200 * @retval None
AnnaBridge 161:aa5281ff4a02 1201 */
AnnaBridge 161:aa5281ff4a02 1202 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1203 {
AnnaBridge 161:aa5281ff4a02 1204 SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
AnnaBridge 161:aa5281ff4a02 1205 }
AnnaBridge 161:aa5281ff4a02 1206
AnnaBridge 161:aa5281ff4a02 1207 /**
AnnaBridge 161:aa5281ff4a02 1208 * @brief Disable Error interrupts.
AnnaBridge 161:aa5281ff4a02 1209 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1210 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1211 * @note Any of these errors will generate interrupt :
AnnaBridge 161:aa5281ff4a02 1212 * Bus Error detection (BERR)
AnnaBridge 161:aa5281ff4a02 1213 * Arbitration Loss (ARLO)
AnnaBridge 161:aa5281ff4a02 1214 * Acknowledge Failure(AF)
AnnaBridge 161:aa5281ff4a02 1215 * Overrun/Underrun (OVR)
AnnaBridge 161:aa5281ff4a02 1216 * SMBus Timeout detection (TIMEOUT)
AnnaBridge 161:aa5281ff4a02 1217 * SMBus PEC error detection (PECERR)
AnnaBridge 161:aa5281ff4a02 1218 * SMBus Alert pin event detection (SMBALERT)
AnnaBridge 161:aa5281ff4a02 1219 * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
AnnaBridge 161:aa5281ff4a02 1220 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1221 * @retval None
AnnaBridge 161:aa5281ff4a02 1222 */
AnnaBridge 161:aa5281ff4a02 1223 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1224 {
AnnaBridge 161:aa5281ff4a02 1225 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
AnnaBridge 161:aa5281ff4a02 1226 }
AnnaBridge 161:aa5281ff4a02 1227
AnnaBridge 161:aa5281ff4a02 1228 /**
AnnaBridge 161:aa5281ff4a02 1229 * @brief Check if Error interrupts are enabled or disabled.
AnnaBridge 161:aa5281ff4a02 1230 * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
AnnaBridge 161:aa5281ff4a02 1231 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1232 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1233 */
AnnaBridge 161:aa5281ff4a02 1234 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1235 {
AnnaBridge 161:aa5281ff4a02 1236 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
AnnaBridge 161:aa5281ff4a02 1237 }
AnnaBridge 161:aa5281ff4a02 1238
AnnaBridge 161:aa5281ff4a02 1239 /**
AnnaBridge 161:aa5281ff4a02 1240 * @}
AnnaBridge 161:aa5281ff4a02 1241 */
AnnaBridge 161:aa5281ff4a02 1242
AnnaBridge 161:aa5281ff4a02 1243 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
AnnaBridge 161:aa5281ff4a02 1244 * @{
AnnaBridge 161:aa5281ff4a02 1245 */
AnnaBridge 161:aa5281ff4a02 1246
AnnaBridge 161:aa5281ff4a02 1247 /**
AnnaBridge 161:aa5281ff4a02 1248 * @brief Indicate the status of Transmit data register empty flag.
AnnaBridge 161:aa5281ff4a02 1249 * @note RESET: When next data is written in Transmit data register.
AnnaBridge 161:aa5281ff4a02 1250 * SET: When Transmit data register is empty.
AnnaBridge 161:aa5281ff4a02 1251 * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
AnnaBridge 161:aa5281ff4a02 1252 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1253 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1254 */
AnnaBridge 161:aa5281ff4a02 1255 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1256 {
AnnaBridge 161:aa5281ff4a02 1257 return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
AnnaBridge 161:aa5281ff4a02 1258 }
AnnaBridge 161:aa5281ff4a02 1259
AnnaBridge 161:aa5281ff4a02 1260 /**
AnnaBridge 161:aa5281ff4a02 1261 * @brief Indicate the status of Byte Transfer Finished flag.
AnnaBridge 161:aa5281ff4a02 1262 * RESET: When Data byte transfer not done.
AnnaBridge 161:aa5281ff4a02 1263 * SET: When Data byte transfer succeeded.
AnnaBridge 161:aa5281ff4a02 1264 * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
AnnaBridge 161:aa5281ff4a02 1265 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1266 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1267 */
AnnaBridge 161:aa5281ff4a02 1268 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1269 {
AnnaBridge 161:aa5281ff4a02 1270 return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
AnnaBridge 161:aa5281ff4a02 1271 }
AnnaBridge 161:aa5281ff4a02 1272
AnnaBridge 161:aa5281ff4a02 1273 /**
AnnaBridge 161:aa5281ff4a02 1274 * @brief Indicate the status of Receive data register not empty flag.
AnnaBridge 161:aa5281ff4a02 1275 * @note RESET: When Receive data register is read.
AnnaBridge 161:aa5281ff4a02 1276 * SET: When the received data is copied in Receive data register.
AnnaBridge 161:aa5281ff4a02 1277 * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
AnnaBridge 161:aa5281ff4a02 1278 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1279 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1280 */
AnnaBridge 161:aa5281ff4a02 1281 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1282 {
AnnaBridge 161:aa5281ff4a02 1283 return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
AnnaBridge 161:aa5281ff4a02 1284 }
AnnaBridge 161:aa5281ff4a02 1285
AnnaBridge 161:aa5281ff4a02 1286 /**
AnnaBridge 161:aa5281ff4a02 1287 * @brief Indicate the status of Start Bit (master mode).
AnnaBridge 161:aa5281ff4a02 1288 * @note RESET: When No Start condition.
AnnaBridge 161:aa5281ff4a02 1289 * SET: When Start condition is generated.
AnnaBridge 161:aa5281ff4a02 1290 * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
AnnaBridge 161:aa5281ff4a02 1291 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1292 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1293 */
AnnaBridge 161:aa5281ff4a02 1294 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1295 {
AnnaBridge 161:aa5281ff4a02 1296 return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
AnnaBridge 161:aa5281ff4a02 1297 }
AnnaBridge 161:aa5281ff4a02 1298
AnnaBridge 161:aa5281ff4a02 1299 /**
AnnaBridge 161:aa5281ff4a02 1300 * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
AnnaBridge 161:aa5281ff4a02 1301 * @note RESET: Clear default value.
AnnaBridge 161:aa5281ff4a02 1302 * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
AnnaBridge 161:aa5281ff4a02 1303 * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
AnnaBridge 161:aa5281ff4a02 1304 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1305 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1306 */
AnnaBridge 161:aa5281ff4a02 1307 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1308 {
AnnaBridge 161:aa5281ff4a02 1309 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
AnnaBridge 161:aa5281ff4a02 1310 }
AnnaBridge 161:aa5281ff4a02 1311
AnnaBridge 161:aa5281ff4a02 1312 /**
AnnaBridge 161:aa5281ff4a02 1313 * @brief Indicate the status of 10-bit header sent (master mode).
AnnaBridge 161:aa5281ff4a02 1314 * @note RESET: When no ADD10 event occured.
AnnaBridge 161:aa5281ff4a02 1315 * SET: When the master has sent the first address byte (header).
AnnaBridge 161:aa5281ff4a02 1316 * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
AnnaBridge 161:aa5281ff4a02 1317 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1318 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1319 */
AnnaBridge 161:aa5281ff4a02 1320 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1321 {
AnnaBridge 161:aa5281ff4a02 1322 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
AnnaBridge 161:aa5281ff4a02 1323 }
AnnaBridge 161:aa5281ff4a02 1324
AnnaBridge 161:aa5281ff4a02 1325 /**
AnnaBridge 161:aa5281ff4a02 1326 * @brief Indicate the status of Acknowledge failure flag.
AnnaBridge 161:aa5281ff4a02 1327 * @note RESET: No acknowledge failure.
AnnaBridge 161:aa5281ff4a02 1328 * SET: When an acknowledge failure is received after a byte transmission.
AnnaBridge 161:aa5281ff4a02 1329 * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
AnnaBridge 161:aa5281ff4a02 1330 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1331 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1332 */
AnnaBridge 161:aa5281ff4a02 1333 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1334 {
AnnaBridge 161:aa5281ff4a02 1335 return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
AnnaBridge 161:aa5281ff4a02 1336 }
AnnaBridge 161:aa5281ff4a02 1337
AnnaBridge 161:aa5281ff4a02 1338 /**
AnnaBridge 161:aa5281ff4a02 1339 * @brief Indicate the status of Stop detection flag (slave mode).
AnnaBridge 161:aa5281ff4a02 1340 * @note RESET: Clear default value.
AnnaBridge 161:aa5281ff4a02 1341 * SET: When a Stop condition is detected.
AnnaBridge 161:aa5281ff4a02 1342 * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
AnnaBridge 161:aa5281ff4a02 1343 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1344 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1345 */
AnnaBridge 161:aa5281ff4a02 1346 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1347 {
AnnaBridge 161:aa5281ff4a02 1348 return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
AnnaBridge 161:aa5281ff4a02 1349 }
AnnaBridge 161:aa5281ff4a02 1350
AnnaBridge 161:aa5281ff4a02 1351 /**
AnnaBridge 161:aa5281ff4a02 1352 * @brief Indicate the status of Bus error flag.
AnnaBridge 161:aa5281ff4a02 1353 * @note RESET: Clear default value.
AnnaBridge 161:aa5281ff4a02 1354 * SET: When a misplaced Start or Stop condition is detected.
AnnaBridge 161:aa5281ff4a02 1355 * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
AnnaBridge 161:aa5281ff4a02 1356 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1357 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1358 */
AnnaBridge 161:aa5281ff4a02 1359 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1360 {
AnnaBridge 161:aa5281ff4a02 1361 return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
AnnaBridge 161:aa5281ff4a02 1362 }
AnnaBridge 161:aa5281ff4a02 1363
AnnaBridge 161:aa5281ff4a02 1364 /**
AnnaBridge 161:aa5281ff4a02 1365 * @brief Indicate the status of Arbitration lost flag.
AnnaBridge 161:aa5281ff4a02 1366 * @note RESET: Clear default value.
AnnaBridge 161:aa5281ff4a02 1367 * SET: When arbitration lost.
AnnaBridge 161:aa5281ff4a02 1368 * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
AnnaBridge 161:aa5281ff4a02 1369 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1370 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1371 */
AnnaBridge 161:aa5281ff4a02 1372 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1373 {
AnnaBridge 161:aa5281ff4a02 1374 return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
AnnaBridge 161:aa5281ff4a02 1375 }
AnnaBridge 161:aa5281ff4a02 1376
AnnaBridge 161:aa5281ff4a02 1377 /**
AnnaBridge 161:aa5281ff4a02 1378 * @brief Indicate the status of Overrun/Underrun flag.
AnnaBridge 161:aa5281ff4a02 1379 * @note RESET: Clear default value.
AnnaBridge 161:aa5281ff4a02 1380 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
AnnaBridge 161:aa5281ff4a02 1381 * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
AnnaBridge 161:aa5281ff4a02 1382 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1383 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1384 */
AnnaBridge 161:aa5281ff4a02 1385 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1386 {
AnnaBridge 161:aa5281ff4a02 1387 return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
AnnaBridge 161:aa5281ff4a02 1388 }
AnnaBridge 161:aa5281ff4a02 1389
AnnaBridge 161:aa5281ff4a02 1390 /**
AnnaBridge 161:aa5281ff4a02 1391 * @brief Indicate the status of SMBus PEC error flag in reception.
AnnaBridge 161:aa5281ff4a02 1392 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1393 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1394 * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
AnnaBridge 161:aa5281ff4a02 1395 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1396 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1397 */
AnnaBridge 161:aa5281ff4a02 1398 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1399 {
AnnaBridge 161:aa5281ff4a02 1400 return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
AnnaBridge 161:aa5281ff4a02 1401 }
AnnaBridge 161:aa5281ff4a02 1402
AnnaBridge 161:aa5281ff4a02 1403 /**
AnnaBridge 161:aa5281ff4a02 1404 * @brief Indicate the status of SMBus Timeout detection flag.
AnnaBridge 161:aa5281ff4a02 1405 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1406 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1407 * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
AnnaBridge 161:aa5281ff4a02 1408 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1409 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1410 */
AnnaBridge 161:aa5281ff4a02 1411 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1412 {
AnnaBridge 161:aa5281ff4a02 1413 return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
AnnaBridge 161:aa5281ff4a02 1414 }
AnnaBridge 161:aa5281ff4a02 1415
AnnaBridge 161:aa5281ff4a02 1416 /**
AnnaBridge 161:aa5281ff4a02 1417 * @brief Indicate the status of SMBus alert flag.
AnnaBridge 161:aa5281ff4a02 1418 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1419 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1420 * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
AnnaBridge 161:aa5281ff4a02 1421 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1422 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1423 */
AnnaBridge 161:aa5281ff4a02 1424 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1425 {
AnnaBridge 161:aa5281ff4a02 1426 return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
AnnaBridge 161:aa5281ff4a02 1427 }
AnnaBridge 161:aa5281ff4a02 1428
AnnaBridge 161:aa5281ff4a02 1429 /**
AnnaBridge 161:aa5281ff4a02 1430 * @brief Indicate the status of Bus Busy flag.
AnnaBridge 161:aa5281ff4a02 1431 * @note RESET: Clear default value.
AnnaBridge 161:aa5281ff4a02 1432 * SET: When a Start condition is detected.
AnnaBridge 161:aa5281ff4a02 1433 * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
AnnaBridge 161:aa5281ff4a02 1434 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1435 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1436 */
AnnaBridge 161:aa5281ff4a02 1437 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1438 {
AnnaBridge 161:aa5281ff4a02 1439 return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
AnnaBridge 161:aa5281ff4a02 1440 }
AnnaBridge 161:aa5281ff4a02 1441
AnnaBridge 161:aa5281ff4a02 1442 /**
AnnaBridge 161:aa5281ff4a02 1443 * @brief Indicate the status of Dual flag.
AnnaBridge 161:aa5281ff4a02 1444 * @note RESET: Received address matched with OAR1.
AnnaBridge 161:aa5281ff4a02 1445 * SET: Received address matched with OAR2.
AnnaBridge 161:aa5281ff4a02 1446 * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
AnnaBridge 161:aa5281ff4a02 1447 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1448 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1449 */
AnnaBridge 161:aa5281ff4a02 1450 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1451 {
AnnaBridge 161:aa5281ff4a02 1452 return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
AnnaBridge 161:aa5281ff4a02 1453 }
AnnaBridge 161:aa5281ff4a02 1454
AnnaBridge 161:aa5281ff4a02 1455 /**
AnnaBridge 161:aa5281ff4a02 1456 * @brief Indicate the status of SMBus Host address reception (Slave mode).
AnnaBridge 161:aa5281ff4a02 1457 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1458 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1459 * @note RESET: No SMBus Host address
AnnaBridge 161:aa5281ff4a02 1460 * SET: SMBus Host address received.
AnnaBridge 161:aa5281ff4a02 1461 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge 161:aa5281ff4a02 1462 * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
AnnaBridge 161:aa5281ff4a02 1463 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1464 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1465 */
AnnaBridge 161:aa5281ff4a02 1466 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1467 {
AnnaBridge 161:aa5281ff4a02 1468 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
AnnaBridge 161:aa5281ff4a02 1469 }
AnnaBridge 161:aa5281ff4a02 1470
AnnaBridge 161:aa5281ff4a02 1471 /**
AnnaBridge 161:aa5281ff4a02 1472 * @brief Indicate the status of SMBus Device default address reception (Slave mode).
AnnaBridge 161:aa5281ff4a02 1473 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1474 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1475 * @note RESET: No SMBus Device default address
AnnaBridge 161:aa5281ff4a02 1476 * SET: SMBus Device default address received.
AnnaBridge 161:aa5281ff4a02 1477 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge 161:aa5281ff4a02 1478 * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
AnnaBridge 161:aa5281ff4a02 1479 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1480 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1481 */
AnnaBridge 161:aa5281ff4a02 1482 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1483 {
AnnaBridge 161:aa5281ff4a02 1484 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
AnnaBridge 161:aa5281ff4a02 1485 }
AnnaBridge 161:aa5281ff4a02 1486
AnnaBridge 161:aa5281ff4a02 1487 /**
AnnaBridge 161:aa5281ff4a02 1488 * @brief Indicate the status of General call address reception (Slave mode).
AnnaBridge 161:aa5281ff4a02 1489 * @note RESET: No Generall call address
AnnaBridge 161:aa5281ff4a02 1490 * SET: General call address received.
AnnaBridge 161:aa5281ff4a02 1491 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge 161:aa5281ff4a02 1492 * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
AnnaBridge 161:aa5281ff4a02 1493 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1494 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1495 */
AnnaBridge 161:aa5281ff4a02 1496 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1497 {
AnnaBridge 161:aa5281ff4a02 1498 return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
AnnaBridge 161:aa5281ff4a02 1499 }
AnnaBridge 161:aa5281ff4a02 1500
AnnaBridge 161:aa5281ff4a02 1501 /**
AnnaBridge 161:aa5281ff4a02 1502 * @brief Indicate the status of Master/Slave flag.
AnnaBridge 161:aa5281ff4a02 1503 * @note RESET: Slave Mode.
AnnaBridge 161:aa5281ff4a02 1504 * SET: Master Mode.
AnnaBridge 161:aa5281ff4a02 1505 * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
AnnaBridge 161:aa5281ff4a02 1506 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1507 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1508 */
AnnaBridge 161:aa5281ff4a02 1509 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1510 {
AnnaBridge 161:aa5281ff4a02 1511 return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
AnnaBridge 161:aa5281ff4a02 1512 }
AnnaBridge 161:aa5281ff4a02 1513
AnnaBridge 161:aa5281ff4a02 1514 /**
AnnaBridge 161:aa5281ff4a02 1515 * @brief Clear Address Matched flag.
AnnaBridge 161:aa5281ff4a02 1516 * @note Clearing this flag is done by a read access to the I2Cx_SR1
AnnaBridge 161:aa5281ff4a02 1517 * register followed by a read access to the I2Cx_SR2 register.
AnnaBridge 161:aa5281ff4a02 1518 * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
AnnaBridge 161:aa5281ff4a02 1519 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1520 * @retval None
AnnaBridge 161:aa5281ff4a02 1521 */
AnnaBridge 161:aa5281ff4a02 1522 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1523 {
AnnaBridge 161:aa5281ff4a02 1524 __IO uint32_t tmpreg;
AnnaBridge 161:aa5281ff4a02 1525 tmpreg = I2Cx->SR1;
AnnaBridge 161:aa5281ff4a02 1526 (void) tmpreg;
AnnaBridge 161:aa5281ff4a02 1527 tmpreg = I2Cx->SR2;
AnnaBridge 161:aa5281ff4a02 1528 (void) tmpreg;
AnnaBridge 161:aa5281ff4a02 1529 }
AnnaBridge 161:aa5281ff4a02 1530
AnnaBridge 161:aa5281ff4a02 1531 /**
AnnaBridge 161:aa5281ff4a02 1532 * @brief Clear Acknowledge failure flag.
AnnaBridge 161:aa5281ff4a02 1533 * @rmtoll SR1 AF LL_I2C_ClearFlag_AF
AnnaBridge 161:aa5281ff4a02 1534 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1535 * @retval None
AnnaBridge 161:aa5281ff4a02 1536 */
AnnaBridge 161:aa5281ff4a02 1537 __STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1538 {
AnnaBridge 161:aa5281ff4a02 1539 CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
AnnaBridge 161:aa5281ff4a02 1540 }
AnnaBridge 161:aa5281ff4a02 1541
AnnaBridge 161:aa5281ff4a02 1542 /**
AnnaBridge 161:aa5281ff4a02 1543 * @brief Clear Stop detection flag.
AnnaBridge 161:aa5281ff4a02 1544 * @note Clearing this flag is done by a read access to the I2Cx_SR1
AnnaBridge 161:aa5281ff4a02 1545 * register followed by a write access to I2Cx_CR1 register.
AnnaBridge 161:aa5281ff4a02 1546 * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
AnnaBridge 161:aa5281ff4a02 1547 * CR1 PE LL_I2C_ClearFlag_STOP
AnnaBridge 161:aa5281ff4a02 1548 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1549 * @retval None
AnnaBridge 161:aa5281ff4a02 1550 */
AnnaBridge 161:aa5281ff4a02 1551 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1552 {
AnnaBridge 161:aa5281ff4a02 1553 __IO uint32_t tmpreg;
AnnaBridge 161:aa5281ff4a02 1554 tmpreg = I2Cx->SR1;
AnnaBridge 161:aa5281ff4a02 1555 (void) tmpreg;
AnnaBridge 161:aa5281ff4a02 1556 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge 161:aa5281ff4a02 1557 }
AnnaBridge 161:aa5281ff4a02 1558
AnnaBridge 161:aa5281ff4a02 1559 /**
AnnaBridge 161:aa5281ff4a02 1560 * @brief Clear Bus error flag.
AnnaBridge 161:aa5281ff4a02 1561 * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
AnnaBridge 161:aa5281ff4a02 1562 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1563 * @retval None
AnnaBridge 161:aa5281ff4a02 1564 */
AnnaBridge 161:aa5281ff4a02 1565 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1566 {
AnnaBridge 161:aa5281ff4a02 1567 CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
AnnaBridge 161:aa5281ff4a02 1568 }
AnnaBridge 161:aa5281ff4a02 1569
AnnaBridge 161:aa5281ff4a02 1570 /**
AnnaBridge 161:aa5281ff4a02 1571 * @brief Clear Arbitration lost flag.
AnnaBridge 161:aa5281ff4a02 1572 * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
AnnaBridge 161:aa5281ff4a02 1573 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1574 * @retval None
AnnaBridge 161:aa5281ff4a02 1575 */
AnnaBridge 161:aa5281ff4a02 1576 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1577 {
AnnaBridge 161:aa5281ff4a02 1578 CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
AnnaBridge 161:aa5281ff4a02 1579 }
AnnaBridge 161:aa5281ff4a02 1580
AnnaBridge 161:aa5281ff4a02 1581 /**
AnnaBridge 161:aa5281ff4a02 1582 * @brief Clear Overrun/Underrun flag.
AnnaBridge 161:aa5281ff4a02 1583 * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
AnnaBridge 161:aa5281ff4a02 1584 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1585 * @retval None
AnnaBridge 161:aa5281ff4a02 1586 */
AnnaBridge 161:aa5281ff4a02 1587 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1588 {
AnnaBridge 161:aa5281ff4a02 1589 CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
AnnaBridge 161:aa5281ff4a02 1590 }
AnnaBridge 161:aa5281ff4a02 1591
AnnaBridge 161:aa5281ff4a02 1592 /**
AnnaBridge 161:aa5281ff4a02 1593 * @brief Clear SMBus PEC error flag.
AnnaBridge 161:aa5281ff4a02 1594 * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
AnnaBridge 161:aa5281ff4a02 1595 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1596 * @retval None
AnnaBridge 161:aa5281ff4a02 1597 */
AnnaBridge 161:aa5281ff4a02 1598 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1599 {
AnnaBridge 161:aa5281ff4a02 1600 CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
AnnaBridge 161:aa5281ff4a02 1601 }
AnnaBridge 161:aa5281ff4a02 1602
AnnaBridge 161:aa5281ff4a02 1603 /**
AnnaBridge 161:aa5281ff4a02 1604 * @brief Clear SMBus Timeout detection flag.
AnnaBridge 161:aa5281ff4a02 1605 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1606 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1607 * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
AnnaBridge 161:aa5281ff4a02 1608 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1609 * @retval None
AnnaBridge 161:aa5281ff4a02 1610 */
AnnaBridge 161:aa5281ff4a02 1611 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1612 {
AnnaBridge 161:aa5281ff4a02 1613 CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
AnnaBridge 161:aa5281ff4a02 1614 }
AnnaBridge 161:aa5281ff4a02 1615
AnnaBridge 161:aa5281ff4a02 1616 /**
AnnaBridge 161:aa5281ff4a02 1617 * @brief Clear SMBus Alert flag.
AnnaBridge 161:aa5281ff4a02 1618 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1619 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1620 * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
AnnaBridge 161:aa5281ff4a02 1621 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1622 * @retval None
AnnaBridge 161:aa5281ff4a02 1623 */
AnnaBridge 161:aa5281ff4a02 1624 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1625 {
AnnaBridge 161:aa5281ff4a02 1626 CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
AnnaBridge 161:aa5281ff4a02 1627 }
AnnaBridge 161:aa5281ff4a02 1628
AnnaBridge 161:aa5281ff4a02 1629 /**
AnnaBridge 161:aa5281ff4a02 1630 * @}
AnnaBridge 161:aa5281ff4a02 1631 */
AnnaBridge 161:aa5281ff4a02 1632
AnnaBridge 161:aa5281ff4a02 1633 /** @defgroup I2C_LL_EF_Data_Management Data_Management
AnnaBridge 161:aa5281ff4a02 1634 * @{
AnnaBridge 161:aa5281ff4a02 1635 */
AnnaBridge 161:aa5281ff4a02 1636
AnnaBridge 161:aa5281ff4a02 1637 /**
AnnaBridge 161:aa5281ff4a02 1638 * @brief Enable Reset of I2C peripheral.
AnnaBridge 161:aa5281ff4a02 1639 * @rmtoll CR1 SWRST LL_I2C_EnableReset
AnnaBridge 161:aa5281ff4a02 1640 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1641 * @retval None
AnnaBridge 161:aa5281ff4a02 1642 */
AnnaBridge 161:aa5281ff4a02 1643 __STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1644 {
AnnaBridge 161:aa5281ff4a02 1645 SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
AnnaBridge 161:aa5281ff4a02 1646 }
AnnaBridge 161:aa5281ff4a02 1647
AnnaBridge 161:aa5281ff4a02 1648 /**
AnnaBridge 161:aa5281ff4a02 1649 * @brief Disable Reset of I2C peripheral.
AnnaBridge 161:aa5281ff4a02 1650 * @rmtoll CR1 SWRST LL_I2C_DisableReset
AnnaBridge 161:aa5281ff4a02 1651 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1652 * @retval None
AnnaBridge 161:aa5281ff4a02 1653 */
AnnaBridge 161:aa5281ff4a02 1654 __STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1655 {
AnnaBridge 161:aa5281ff4a02 1656 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
AnnaBridge 161:aa5281ff4a02 1657 }
AnnaBridge 161:aa5281ff4a02 1658
AnnaBridge 161:aa5281ff4a02 1659 /**
AnnaBridge 161:aa5281ff4a02 1660 * @brief Check if the I2C peripheral is under reset state or not.
AnnaBridge 161:aa5281ff4a02 1661 * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
AnnaBridge 161:aa5281ff4a02 1662 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1663 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1664 */
AnnaBridge 161:aa5281ff4a02 1665 __STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1666 {
AnnaBridge 161:aa5281ff4a02 1667 return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
AnnaBridge 161:aa5281ff4a02 1668 }
AnnaBridge 161:aa5281ff4a02 1669
AnnaBridge 161:aa5281ff4a02 1670 /**
AnnaBridge 161:aa5281ff4a02 1671 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
AnnaBridge 161:aa5281ff4a02 1672 * @note Usage in Slave or Master mode.
AnnaBridge 161:aa5281ff4a02 1673 * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
AnnaBridge 161:aa5281ff4a02 1674 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1675 * @param TypeAcknowledge This parameter can be one of the following values:
AnnaBridge 161:aa5281ff4a02 1676 * @arg @ref LL_I2C_ACK
AnnaBridge 161:aa5281ff4a02 1677 * @arg @ref LL_I2C_NACK
AnnaBridge 161:aa5281ff4a02 1678 * @retval None
AnnaBridge 161:aa5281ff4a02 1679 */
AnnaBridge 161:aa5281ff4a02 1680 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
AnnaBridge 161:aa5281ff4a02 1681 {
AnnaBridge 161:aa5281ff4a02 1682 MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
AnnaBridge 161:aa5281ff4a02 1683 }
AnnaBridge 161:aa5281ff4a02 1684
AnnaBridge 161:aa5281ff4a02 1685 /**
AnnaBridge 161:aa5281ff4a02 1686 * @brief Generate a START or RESTART condition
AnnaBridge 161:aa5281ff4a02 1687 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
AnnaBridge 161:aa5281ff4a02 1688 * This action has no effect when RELOAD is set.
AnnaBridge 161:aa5281ff4a02 1689 * @rmtoll CR1 START LL_I2C_GenerateStartCondition
AnnaBridge 161:aa5281ff4a02 1690 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1691 * @retval None
AnnaBridge 161:aa5281ff4a02 1692 */
AnnaBridge 161:aa5281ff4a02 1693 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1694 {
AnnaBridge 161:aa5281ff4a02 1695 SET_BIT(I2Cx->CR1, I2C_CR1_START);
AnnaBridge 161:aa5281ff4a02 1696 }
AnnaBridge 161:aa5281ff4a02 1697
AnnaBridge 161:aa5281ff4a02 1698 /**
AnnaBridge 161:aa5281ff4a02 1699 * @brief Generate a STOP condition after the current byte transfer (master mode).
AnnaBridge 161:aa5281ff4a02 1700 * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
AnnaBridge 161:aa5281ff4a02 1701 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1702 * @retval None
AnnaBridge 161:aa5281ff4a02 1703 */
AnnaBridge 161:aa5281ff4a02 1704 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1705 {
AnnaBridge 161:aa5281ff4a02 1706 SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
AnnaBridge 161:aa5281ff4a02 1707 }
AnnaBridge 161:aa5281ff4a02 1708
AnnaBridge 161:aa5281ff4a02 1709 /**
AnnaBridge 161:aa5281ff4a02 1710 * @brief Enable bit POS (master/host mode).
AnnaBridge 161:aa5281ff4a02 1711 * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
AnnaBridge 161:aa5281ff4a02 1712 * @rmtoll CR1 POS LL_I2C_EnableBitPOS
AnnaBridge 161:aa5281ff4a02 1713 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1714 * @retval None
AnnaBridge 161:aa5281ff4a02 1715 */
AnnaBridge 161:aa5281ff4a02 1716 __STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1717 {
AnnaBridge 161:aa5281ff4a02 1718 SET_BIT(I2Cx->CR1, I2C_CR1_POS);
AnnaBridge 161:aa5281ff4a02 1719 }
AnnaBridge 161:aa5281ff4a02 1720
AnnaBridge 161:aa5281ff4a02 1721 /**
AnnaBridge 161:aa5281ff4a02 1722 * @brief Disable bit POS (master/host mode).
AnnaBridge 161:aa5281ff4a02 1723 * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
AnnaBridge 161:aa5281ff4a02 1724 * @rmtoll CR1 POS LL_I2C_DisableBitPOS
AnnaBridge 161:aa5281ff4a02 1725 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1726 * @retval None
AnnaBridge 161:aa5281ff4a02 1727 */
AnnaBridge 161:aa5281ff4a02 1728 __STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1729 {
AnnaBridge 161:aa5281ff4a02 1730 CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
AnnaBridge 161:aa5281ff4a02 1731 }
AnnaBridge 161:aa5281ff4a02 1732
AnnaBridge 161:aa5281ff4a02 1733 /**
AnnaBridge 161:aa5281ff4a02 1734 * @brief Check if bit POS is enabled or disabled.
AnnaBridge 161:aa5281ff4a02 1735 * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
AnnaBridge 161:aa5281ff4a02 1736 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1737 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1738 */
AnnaBridge 161:aa5281ff4a02 1739 __STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1740 {
AnnaBridge 161:aa5281ff4a02 1741 return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
AnnaBridge 161:aa5281ff4a02 1742 }
AnnaBridge 161:aa5281ff4a02 1743
AnnaBridge 161:aa5281ff4a02 1744 /**
AnnaBridge 161:aa5281ff4a02 1745 * @brief Indicate the value of transfer direction.
AnnaBridge 161:aa5281ff4a02 1746 * @note RESET: Bus is in read transfer (peripheral point of view).
AnnaBridge 161:aa5281ff4a02 1747 * SET: Bus is in write transfer (peripheral point of view).
AnnaBridge 161:aa5281ff4a02 1748 * @rmtoll SR2 TRA LL_I2C_GetTransferDirection
AnnaBridge 161:aa5281ff4a02 1749 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1750 * @retval Returned value can be one of the following values:
AnnaBridge 161:aa5281ff4a02 1751 * @arg @ref LL_I2C_DIRECTION_WRITE
AnnaBridge 161:aa5281ff4a02 1752 * @arg @ref LL_I2C_DIRECTION_READ
AnnaBridge 161:aa5281ff4a02 1753 */
AnnaBridge 161:aa5281ff4a02 1754 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1755 {
AnnaBridge 161:aa5281ff4a02 1756 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
AnnaBridge 161:aa5281ff4a02 1757 }
AnnaBridge 161:aa5281ff4a02 1758
AnnaBridge 161:aa5281ff4a02 1759 /**
AnnaBridge 161:aa5281ff4a02 1760 * @brief Enable DMA last transfer.
AnnaBridge 161:aa5281ff4a02 1761 * @note This action mean that next DMA EOT is the last transfer.
AnnaBridge 161:aa5281ff4a02 1762 * @rmtoll CR2 LAST LL_I2C_EnableLastDMA
AnnaBridge 161:aa5281ff4a02 1763 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1764 * @retval None
AnnaBridge 161:aa5281ff4a02 1765 */
AnnaBridge 161:aa5281ff4a02 1766 __STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1767 {
AnnaBridge 161:aa5281ff4a02 1768 SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
AnnaBridge 161:aa5281ff4a02 1769 }
AnnaBridge 161:aa5281ff4a02 1770
AnnaBridge 161:aa5281ff4a02 1771 /**
AnnaBridge 161:aa5281ff4a02 1772 * @brief Disable DMA last transfer.
AnnaBridge 161:aa5281ff4a02 1773 * @note This action mean that next DMA EOT is not the last transfer.
AnnaBridge 161:aa5281ff4a02 1774 * @rmtoll CR2 LAST LL_I2C_DisableLastDMA
AnnaBridge 161:aa5281ff4a02 1775 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1776 * @retval None
AnnaBridge 161:aa5281ff4a02 1777 */
AnnaBridge 161:aa5281ff4a02 1778 __STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1779 {
AnnaBridge 161:aa5281ff4a02 1780 CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
AnnaBridge 161:aa5281ff4a02 1781 }
AnnaBridge 161:aa5281ff4a02 1782
AnnaBridge 161:aa5281ff4a02 1783 /**
AnnaBridge 161:aa5281ff4a02 1784 * @brief Check if DMA last transfer is enabled or disabled.
AnnaBridge 161:aa5281ff4a02 1785 * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
AnnaBridge 161:aa5281ff4a02 1786 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1787 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1788 */
AnnaBridge 161:aa5281ff4a02 1789 __STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1790 {
AnnaBridge 161:aa5281ff4a02 1791 return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
AnnaBridge 161:aa5281ff4a02 1792 }
AnnaBridge 161:aa5281ff4a02 1793
AnnaBridge 161:aa5281ff4a02 1794 /**
AnnaBridge 161:aa5281ff4a02 1795 * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
AnnaBridge 161:aa5281ff4a02 1796 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1797 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1798 * @note This feature is cleared by hardware when the PEC byte is transferred or compared,
AnnaBridge 161:aa5281ff4a02 1799 * or by a START or STOP condition, it is also cleared by software.
AnnaBridge 161:aa5281ff4a02 1800 * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
AnnaBridge 161:aa5281ff4a02 1801 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1802 * @retval None
AnnaBridge 161:aa5281ff4a02 1803 */
AnnaBridge 161:aa5281ff4a02 1804 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1805 {
AnnaBridge 161:aa5281ff4a02 1806 SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
AnnaBridge 161:aa5281ff4a02 1807 }
AnnaBridge 161:aa5281ff4a02 1808
AnnaBridge 161:aa5281ff4a02 1809 /**
AnnaBridge 161:aa5281ff4a02 1810 * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
AnnaBridge 161:aa5281ff4a02 1811 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1812 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1813 * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
AnnaBridge 161:aa5281ff4a02 1814 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1815 * @retval None
AnnaBridge 161:aa5281ff4a02 1816 */
AnnaBridge 161:aa5281ff4a02 1817 __STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1818 {
AnnaBridge 161:aa5281ff4a02 1819 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
AnnaBridge 161:aa5281ff4a02 1820 }
AnnaBridge 161:aa5281ff4a02 1821
AnnaBridge 161:aa5281ff4a02 1822 /**
AnnaBridge 161:aa5281ff4a02 1823 * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
AnnaBridge 161:aa5281ff4a02 1824 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1825 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1826 * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
AnnaBridge 161:aa5281ff4a02 1827 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1828 * @retval State of bit (1 or 0).
AnnaBridge 161:aa5281ff4a02 1829 */
AnnaBridge 161:aa5281ff4a02 1830 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1831 {
AnnaBridge 161:aa5281ff4a02 1832 return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
AnnaBridge 161:aa5281ff4a02 1833 }
AnnaBridge 161:aa5281ff4a02 1834
AnnaBridge 161:aa5281ff4a02 1835 /**
AnnaBridge 161:aa5281ff4a02 1836 * @brief Get the SMBus Packet Error byte calculated.
AnnaBridge 161:aa5281ff4a02 1837 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 161:aa5281ff4a02 1838 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 161:aa5281ff4a02 1839 * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
AnnaBridge 161:aa5281ff4a02 1840 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1841 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 161:aa5281ff4a02 1842 */
AnnaBridge 161:aa5281ff4a02 1843 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1844 {
AnnaBridge 161:aa5281ff4a02 1845 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
AnnaBridge 161:aa5281ff4a02 1846 }
AnnaBridge 161:aa5281ff4a02 1847
AnnaBridge 161:aa5281ff4a02 1848 /**
AnnaBridge 161:aa5281ff4a02 1849 * @brief Read Receive Data register.
AnnaBridge 161:aa5281ff4a02 1850 * @rmtoll DR DR LL_I2C_ReceiveData8
AnnaBridge 161:aa5281ff4a02 1851 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1852 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
AnnaBridge 161:aa5281ff4a02 1853 */
AnnaBridge 161:aa5281ff4a02 1854 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
AnnaBridge 161:aa5281ff4a02 1855 {
AnnaBridge 161:aa5281ff4a02 1856 return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
AnnaBridge 161:aa5281ff4a02 1857 }
AnnaBridge 161:aa5281ff4a02 1858
AnnaBridge 161:aa5281ff4a02 1859 /**
AnnaBridge 161:aa5281ff4a02 1860 * @brief Write in Transmit Data Register .
AnnaBridge 161:aa5281ff4a02 1861 * @rmtoll DR DR LL_I2C_TransmitData8
AnnaBridge 161:aa5281ff4a02 1862 * @param I2Cx I2C Instance.
AnnaBridge 161:aa5281ff4a02 1863 * @param Data Value between Min_Data=0x0 and Max_Data=0xFF
AnnaBridge 161:aa5281ff4a02 1864 * @retval None
AnnaBridge 161:aa5281ff4a02 1865 */
AnnaBridge 161:aa5281ff4a02 1866 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
AnnaBridge 161:aa5281ff4a02 1867 {
AnnaBridge 161:aa5281ff4a02 1868 MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
AnnaBridge 161:aa5281ff4a02 1869 }
AnnaBridge 161:aa5281ff4a02 1870
AnnaBridge 161:aa5281ff4a02 1871 /**
AnnaBridge 161:aa5281ff4a02 1872 * @}
AnnaBridge 161:aa5281ff4a02 1873 */
AnnaBridge 161:aa5281ff4a02 1874
AnnaBridge 161:aa5281ff4a02 1875 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 161:aa5281ff4a02 1876 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 161:aa5281ff4a02 1877 * @{
AnnaBridge 161:aa5281ff4a02 1878 */
AnnaBridge 161:aa5281ff4a02 1879
AnnaBridge 161:aa5281ff4a02 1880 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
AnnaBridge 161:aa5281ff4a02 1881 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
AnnaBridge 161:aa5281ff4a02 1882 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
AnnaBridge 161:aa5281ff4a02 1883
AnnaBridge 161:aa5281ff4a02 1884
AnnaBridge 161:aa5281ff4a02 1885 /**
AnnaBridge 161:aa5281ff4a02 1886 * @}
AnnaBridge 161:aa5281ff4a02 1887 */
AnnaBridge 161:aa5281ff4a02 1888 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 161:aa5281ff4a02 1889
AnnaBridge 161:aa5281ff4a02 1890 /**
AnnaBridge 161:aa5281ff4a02 1891 * @}
AnnaBridge 161:aa5281ff4a02 1892 */
AnnaBridge 161:aa5281ff4a02 1893
AnnaBridge 161:aa5281ff4a02 1894 /**
AnnaBridge 161:aa5281ff4a02 1895 * @}
AnnaBridge 161:aa5281ff4a02 1896 */
AnnaBridge 161:aa5281ff4a02 1897
AnnaBridge 161:aa5281ff4a02 1898 #endif /* I2C1 || I2C2 || I2C3 */
AnnaBridge 161:aa5281ff4a02 1899
AnnaBridge 161:aa5281ff4a02 1900 /**
AnnaBridge 161:aa5281ff4a02 1901 * @}
AnnaBridge 161:aa5281ff4a02 1902 */
AnnaBridge 161:aa5281ff4a02 1903
AnnaBridge 161:aa5281ff4a02 1904 #ifdef __cplusplus
AnnaBridge 161:aa5281ff4a02 1905 }
AnnaBridge 161:aa5281ff4a02 1906 #endif
AnnaBridge 161:aa5281ff4a02 1907
AnnaBridge 161:aa5281ff4a02 1908 #endif /* __STM32F4xx_LL_I2C_H */
AnnaBridge 161:aa5281ff4a02 1909
AnnaBridge 161:aa5281ff4a02 1910 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/