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TARGET_B96B_F446VE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:: Anna Bridge
Date:: Fri Jun 22 15:38:59 2018 +0100
Revision:: 169:a7c7b631e539
Parent:: 163:e59c8e839560

mbed library. Release version 162

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	156:ff21514d8981	1	/**
AnnaBridge	156:ff21514d8981	2	******************************************************************************
AnnaBridge	156:ff21514d8981	3	* @file stm32f4xx_ll_fsmc.h
AnnaBridge	156:ff21514d8981	4	* @author MCD Application Team
AnnaBridge	156:ff21514d8981	5	* @brief Header file of FSMC HAL module.
AnnaBridge	156:ff21514d8981	6	******************************************************************************
AnnaBridge	156:ff21514d8981	7	* @attention
AnnaBridge	156:ff21514d8981	8	*
AnnaBridge	156:ff21514d8981	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	156:ff21514d8981	10	*
AnnaBridge	156:ff21514d8981	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	156:ff21514d8981	12	* are permitted provided that the following conditions are met:
AnnaBridge	156:ff21514d8981	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	156:ff21514d8981	14	* this list of conditions and the following disclaimer.
AnnaBridge	156:ff21514d8981	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	156:ff21514d8981	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	156:ff21514d8981	17	* and/or other materials provided with the distribution.
AnnaBridge	156:ff21514d8981	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	156:ff21514d8981	19	* may be used to endorse or promote products derived from this software
AnnaBridge	156:ff21514d8981	20	* without specific prior written permission.
AnnaBridge	156:ff21514d8981	21	*
AnnaBridge	156:ff21514d8981	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	156:ff21514d8981	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	156:ff21514d8981	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	156:ff21514d8981	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	156:ff21514d8981	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	156:ff21514d8981	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	156:ff21514d8981	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	156:ff21514d8981	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	156:ff21514d8981	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	156:ff21514d8981	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	156:ff21514d8981	32	*
AnnaBridge	156:ff21514d8981	33	******************************************************************************
AnnaBridge	156:ff21514d8981	34	*/
AnnaBridge	156:ff21514d8981	35
AnnaBridge	156:ff21514d8981	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	156:ff21514d8981	37	#ifndef __STM32F4xx_LL_FSMC_H
AnnaBridge	156:ff21514d8981	38	#define __STM32F4xx_LL_FSMC_H
AnnaBridge	156:ff21514d8981	39
AnnaBridge	156:ff21514d8981	40	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	41	extern "C" {
AnnaBridge	156:ff21514d8981	42	#endif
AnnaBridge	156:ff21514d8981	43
AnnaBridge	156:ff21514d8981	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	45	#include "stm32f4xx_hal_def.h"
AnnaBridge	156:ff21514d8981	46
AnnaBridge	156:ff21514d8981	47	/** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge	156:ff21514d8981	48	* @{
AnnaBridge	156:ff21514d8981	49	*/
AnnaBridge	156:ff21514d8981	50
AnnaBridge	156:ff21514d8981	51	/** @addtogroup FSMC_LL
AnnaBridge	156:ff21514d8981	52	* @{
AnnaBridge	156:ff21514d8981	53	*/
AnnaBridge	156:ff21514d8981	54
AnnaBridge	156:ff21514d8981	55	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F412Zx) \|\|\
AnnaBridge	156:ff21514d8981	56	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	58	/** @defgroup FSMC_LL_Private_Types FSMC Private Types
AnnaBridge	156:ff21514d8981	59	* @{
AnnaBridge	156:ff21514d8981	60	*/
AnnaBridge	156:ff21514d8981	61
AnnaBridge	156:ff21514d8981	62	/**
AnnaBridge	156:ff21514d8981	63	* @brief FSMC NORSRAM Configuration Structure definition
AnnaBridge	156:ff21514d8981	64	*/
AnnaBridge	156:ff21514d8981	65	typedef struct
AnnaBridge	156:ff21514d8981	66	{
AnnaBridge	156:ff21514d8981	67	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
AnnaBridge	156:ff21514d8981	68	This parameter can be a value of @ref FSMC_NORSRAM_Bank */
AnnaBridge	156:ff21514d8981	69
AnnaBridge	156:ff21514d8981	70	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
AnnaBridge	156:ff21514d8981	71	multiplexed on the data bus or not.
AnnaBridge	156:ff21514d8981	72	This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
AnnaBridge	156:ff21514d8981	73
AnnaBridge	156:ff21514d8981	74	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
AnnaBridge	156:ff21514d8981	75	the corresponding memory device.
AnnaBridge	156:ff21514d8981	76	This parameter can be a value of @ref FSMC_Memory_Type */
AnnaBridge	156:ff21514d8981	77
AnnaBridge	156:ff21514d8981	78	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	156:ff21514d8981	79	This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
AnnaBridge	156:ff21514d8981	80
AnnaBridge	156:ff21514d8981	81	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
AnnaBridge	156:ff21514d8981	82	valid only with synchronous burst Flash memories.
AnnaBridge	156:ff21514d8981	83	This parameter can be a value of @ref FSMC_Burst_Access_Mode */
AnnaBridge	156:ff21514d8981	84
AnnaBridge	156:ff21514d8981	85	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
AnnaBridge	156:ff21514d8981	86	the Flash memory in burst mode.
AnnaBridge	156:ff21514d8981	87	This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
AnnaBridge	156:ff21514d8981	88
AnnaBridge	156:ff21514d8981	89	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
AnnaBridge	156:ff21514d8981	90	memory, valid only when accessing Flash memories in burst mode.
AnnaBridge	156:ff21514d8981	91	This parameter can be a value of @ref FSMC_Wrap_Mode
AnnaBridge	156:ff21514d8981	92	This mode is available only for the STM32F405/407/4015/417xx devices */
AnnaBridge	156:ff21514d8981	93
AnnaBridge	156:ff21514d8981	94	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
AnnaBridge	156:ff21514d8981	95	clock cycle before the wait state or during the wait state,
AnnaBridge	156:ff21514d8981	96	valid only when accessing memories in burst mode.
AnnaBridge	156:ff21514d8981	97	This parameter can be a value of @ref FSMC_Wait_Timing */
AnnaBridge	156:ff21514d8981	98
AnnaBridge	156:ff21514d8981	99	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
AnnaBridge	156:ff21514d8981	100	This parameter can be a value of @ref FSMC_Write_Operation */
AnnaBridge	156:ff21514d8981	101
AnnaBridge	156:ff21514d8981	102	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
AnnaBridge	156:ff21514d8981	103	signal, valid for Flash memory access in burst mode.
AnnaBridge	156:ff21514d8981	104	This parameter can be a value of @ref FSMC_Wait_Signal */
AnnaBridge	156:ff21514d8981	105
AnnaBridge	156:ff21514d8981	106	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
AnnaBridge	156:ff21514d8981	107	This parameter can be a value of @ref FSMC_Extended_Mode */
AnnaBridge	156:ff21514d8981	108
AnnaBridge	156:ff21514d8981	109	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
AnnaBridge	156:ff21514d8981	110	valid only with asynchronous Flash memories.
AnnaBridge	156:ff21514d8981	111	This parameter can be a value of @ref FSMC_AsynchronousWait */
AnnaBridge	156:ff21514d8981	112
AnnaBridge	156:ff21514d8981	113	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
AnnaBridge	156:ff21514d8981	114	This parameter can be a value of @ref FSMC_Write_Burst */
AnnaBridge	156:ff21514d8981	115
AnnaBridge	156:ff21514d8981	116	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
AnnaBridge	156:ff21514d8981	117	This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge	156:ff21514d8981	118	through FMC_BCR2..4 registers.
AnnaBridge	156:ff21514d8981	119	This parameter can be a value of @ref FMC_Continous_Clock
AnnaBridge	156:ff21514d8981	120	This mode is available only for the STM32F412Vx/Zx/Rx devices */
AnnaBridge	156:ff21514d8981	121
AnnaBridge	156:ff21514d8981	122	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
AnnaBridge	156:ff21514d8981	123	This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge	156:ff21514d8981	124	through FMC_BCR2..4 registers.
AnnaBridge	156:ff21514d8981	125	This parameter can be a value of @ref FMC_Write_FIFO
AnnaBridge	156:ff21514d8981	126	This mode is available only for the STM32F412Vx/Vx devices */
AnnaBridge	156:ff21514d8981	127
AnnaBridge	156:ff21514d8981	128	uint32_t PageSize; /*!< Specifies the memory page size.
AnnaBridge	156:ff21514d8981	129	This parameter can be a value of @ref FMC_Page_Size */
AnnaBridge	156:ff21514d8981	130	}FSMC_NORSRAM_InitTypeDef;
AnnaBridge	156:ff21514d8981	131
AnnaBridge	156:ff21514d8981	132	/**
AnnaBridge	156:ff21514d8981	133	* @brief FSMC NORSRAM Timing parameters structure definition
AnnaBridge	156:ff21514d8981	134	*/
AnnaBridge	156:ff21514d8981	135	typedef struct
AnnaBridge	156:ff21514d8981	136	{
AnnaBridge	156:ff21514d8981	137	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	156:ff21514d8981	138	the duration of the address setup time.
AnnaBridge	156:ff21514d8981	139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	140	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	156:ff21514d8981	141
AnnaBridge	156:ff21514d8981	142	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	156:ff21514d8981	143	the duration of the address hold time.
AnnaBridge	156:ff21514d8981	144	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	145	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	156:ff21514d8981	146
AnnaBridge	156:ff21514d8981	147	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	156:ff21514d8981	148	the duration of the data setup time.
AnnaBridge	156:ff21514d8981	149	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
AnnaBridge	156:ff21514d8981	150	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
AnnaBridge	156:ff21514d8981	151	NOR Flash memories. */
AnnaBridge	156:ff21514d8981	152
AnnaBridge	156:ff21514d8981	153	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	156:ff21514d8981	154	the duration of the bus turnaround.
AnnaBridge	156:ff21514d8981	155	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	156	@note This parameter is only used for multiplexed NOR Flash memories. */
AnnaBridge	156:ff21514d8981	157
AnnaBridge	156:ff21514d8981	158	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
AnnaBridge	156:ff21514d8981	159	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
AnnaBridge	156:ff21514d8981	160	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
AnnaBridge	156:ff21514d8981	161	accesses. */
AnnaBridge	156:ff21514d8981	162
AnnaBridge	156:ff21514d8981	163	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
AnnaBridge	156:ff21514d8981	164	to the memory before getting the first data.
AnnaBridge	156:ff21514d8981	165	The parameter value depends on the memory type as shown below:
AnnaBridge	156:ff21514d8981	166	- It must be set to 0 in case of a CRAM
AnnaBridge	156:ff21514d8981	167	- It is don't care in asynchronous NOR, SRAM or ROM accesses
AnnaBridge	156:ff21514d8981	168	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
AnnaBridge	156:ff21514d8981	169	with synchronous burst mode enable */
AnnaBridge	156:ff21514d8981	170
AnnaBridge	156:ff21514d8981	171	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
AnnaBridge	156:ff21514d8981	172	This parameter can be a value of @ref FSMC_Access_Mode */
AnnaBridge	156:ff21514d8981	173
AnnaBridge	156:ff21514d8981	174	}FSMC_NORSRAM_TimingTypeDef;
AnnaBridge	156:ff21514d8981	175
AnnaBridge	156:ff21514d8981	176	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	177	/**
AnnaBridge	156:ff21514d8981	178	* @brief FSMC NAND Configuration Structure definition
AnnaBridge	156:ff21514d8981	179	*/
AnnaBridge	156:ff21514d8981	180	typedef struct
AnnaBridge	156:ff21514d8981	181	{
AnnaBridge	156:ff21514d8981	182	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
AnnaBridge	156:ff21514d8981	183	This parameter can be a value of @ref FSMC_NAND_Bank */
AnnaBridge	156:ff21514d8981	184
AnnaBridge	156:ff21514d8981	185	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
AnnaBridge	156:ff21514d8981	186	This parameter can be any value of @ref FSMC_Wait_feature */
AnnaBridge	156:ff21514d8981	187
AnnaBridge	156:ff21514d8981	188	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	156:ff21514d8981	189	This parameter can be any value of @ref FSMC_NAND_Data_Width */
AnnaBridge	156:ff21514d8981	190
AnnaBridge	156:ff21514d8981	191	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
AnnaBridge	156:ff21514d8981	192	This parameter can be any value of @ref FSMC_ECC */
AnnaBridge	156:ff21514d8981	193
AnnaBridge	156:ff21514d8981	194	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
AnnaBridge	156:ff21514d8981	195	This parameter can be any value of @ref FSMC_ECC_Page_Size */
AnnaBridge	156:ff21514d8981	196
AnnaBridge	156:ff21514d8981	197	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	156:ff21514d8981	198	delay between CLE low and RE low.
AnnaBridge	156:ff21514d8981	199	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	200
AnnaBridge	156:ff21514d8981	201	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	156:ff21514d8981	202	delay between ALE low and RE low.
AnnaBridge	156:ff21514d8981	203	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	204
AnnaBridge	156:ff21514d8981	205	}FSMC_NAND_InitTypeDef;
AnnaBridge	156:ff21514d8981	206
AnnaBridge	156:ff21514d8981	207	/**
AnnaBridge	156:ff21514d8981	208	* @brief FSMC NAND/PCCARD Timing parameters structure definition
AnnaBridge	156:ff21514d8981	209	*/
AnnaBridge	156:ff21514d8981	210	typedef struct
AnnaBridge	156:ff21514d8981	211	{
AnnaBridge	156:ff21514d8981	212	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
AnnaBridge	156:ff21514d8981	213	the command assertion for NAND-Flash read or write access
AnnaBridge	156:ff21514d8981	214	to common/Attribute or I/O memory space (depending on
AnnaBridge	156:ff21514d8981	215	the memory space timing to be configured).
AnnaBridge	156:ff21514d8981	216	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	217
AnnaBridge	156:ff21514d8981	218	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
AnnaBridge	156:ff21514d8981	219	command for NAND-Flash read or write access to
AnnaBridge	156:ff21514d8981	220	common/Attribute or I/O memory space (depending on the
AnnaBridge	156:ff21514d8981	221	memory space timing to be configured).
AnnaBridge	156:ff21514d8981	222	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	223
AnnaBridge	156:ff21514d8981	224	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
AnnaBridge	156:ff21514d8981	225	(and data for write access) after the command de-assertion
AnnaBridge	156:ff21514d8981	226	for NAND-Flash read or write access to common/Attribute
AnnaBridge	156:ff21514d8981	227	or I/O memory space (depending on the memory space timing
AnnaBridge	156:ff21514d8981	228	to be configured).
AnnaBridge	156:ff21514d8981	229	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	230
AnnaBridge	156:ff21514d8981	231	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
AnnaBridge	156:ff21514d8981	232	data bus is kept in HiZ after the start of a NAND-Flash
AnnaBridge	156:ff21514d8981	233	write access to common/Attribute or I/O memory space (depending
AnnaBridge	156:ff21514d8981	234	on the memory space timing to be configured).
AnnaBridge	156:ff21514d8981	235	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	236
AnnaBridge	156:ff21514d8981	237	}FSMC_NAND_PCC_TimingTypeDef;
AnnaBridge	156:ff21514d8981	238
AnnaBridge	156:ff21514d8981	239	/**
AnnaBridge	156:ff21514d8981	240	* @brief FSMC NAND Configuration Structure definition
AnnaBridge	156:ff21514d8981	241	*/
AnnaBridge	156:ff21514d8981	242	typedef struct
AnnaBridge	156:ff21514d8981	243	{
AnnaBridge	156:ff21514d8981	244	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
AnnaBridge	156:ff21514d8981	245	This parameter can be any value of @ref FSMC_Wait_feature */
AnnaBridge	156:ff21514d8981	246
AnnaBridge	156:ff21514d8981	247	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	156:ff21514d8981	248	delay between CLE low and RE low.
AnnaBridge	156:ff21514d8981	249	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	250
AnnaBridge	156:ff21514d8981	251	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	156:ff21514d8981	252	delay between ALE low and RE low.
AnnaBridge	156:ff21514d8981	253	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	254
AnnaBridge	156:ff21514d8981	255	}FSMC_PCCARD_InitTypeDef;
AnnaBridge	156:ff21514d8981	256	/**
AnnaBridge	156:ff21514d8981	257	* @}
AnnaBridge	156:ff21514d8981	258	*/
AnnaBridge	156:ff21514d8981	259	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	260
AnnaBridge	156:ff21514d8981	261	/* Private constants ---------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	262	/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
AnnaBridge	156:ff21514d8981	263	* @{
AnnaBridge	156:ff21514d8981	264	*/
AnnaBridge	156:ff21514d8981	265
AnnaBridge	156:ff21514d8981	266	/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
AnnaBridge	156:ff21514d8981	267	* @{
AnnaBridge	156:ff21514d8981	268	*/
AnnaBridge	156:ff21514d8981	269	/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
AnnaBridge	156:ff21514d8981	270	* @{
AnnaBridge	156:ff21514d8981	271	*/
AnnaBridge	156:ff21514d8981	272	#define FSMC_NORSRAM_BANK1 0x00000000U
AnnaBridge	156:ff21514d8981	273	#define FSMC_NORSRAM_BANK2 0x00000002U
AnnaBridge	156:ff21514d8981	274	#define FSMC_NORSRAM_BANK3 0x00000004U
AnnaBridge	156:ff21514d8981	275	#define FSMC_NORSRAM_BANK4 0x00000006U
AnnaBridge	156:ff21514d8981	276	/**
AnnaBridge	156:ff21514d8981	277	* @}
AnnaBridge	156:ff21514d8981	278	*/
AnnaBridge	156:ff21514d8981	279
AnnaBridge	156:ff21514d8981	280	/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
AnnaBridge	156:ff21514d8981	281	* @{
AnnaBridge	156:ff21514d8981	282	*/
AnnaBridge	156:ff21514d8981	283	#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	284	#define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
AnnaBridge	156:ff21514d8981	285	/**
AnnaBridge	156:ff21514d8981	286	* @}
AnnaBridge	156:ff21514d8981	287	*/
AnnaBridge	156:ff21514d8981	288
AnnaBridge	156:ff21514d8981	289	/** @defgroup FSMC_Memory_Type FSMC Memory Type
AnnaBridge	156:ff21514d8981	290	* @{
AnnaBridge	156:ff21514d8981	291	*/
AnnaBridge	156:ff21514d8981	292	#define FSMC_MEMORY_TYPE_SRAM 0x00000000U
AnnaBridge	156:ff21514d8981	293	#define FSMC_MEMORY_TYPE_PSRAM 0x00000004U
AnnaBridge	156:ff21514d8981	294	#define FSMC_MEMORY_TYPE_NOR 0x00000008U
AnnaBridge	156:ff21514d8981	295	/**
AnnaBridge	156:ff21514d8981	296	* @}
AnnaBridge	156:ff21514d8981	297	*/
AnnaBridge	156:ff21514d8981	298
AnnaBridge	156:ff21514d8981	299	/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
AnnaBridge	156:ff21514d8981	300	* @{
AnnaBridge	156:ff21514d8981	301	*/
AnnaBridge	156:ff21514d8981	302	#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	156:ff21514d8981	303	#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
AnnaBridge	156:ff21514d8981	304	#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
AnnaBridge	156:ff21514d8981	305	/**
AnnaBridge	156:ff21514d8981	306	* @}
AnnaBridge	156:ff21514d8981	307	*/
AnnaBridge	156:ff21514d8981	308
AnnaBridge	156:ff21514d8981	309	/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
AnnaBridge	156:ff21514d8981	310	* @{
AnnaBridge	156:ff21514d8981	311	*/
AnnaBridge	156:ff21514d8981	312	#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
AnnaBridge	156:ff21514d8981	313	#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	314	/**
AnnaBridge	156:ff21514d8981	315	* @}
AnnaBridge	156:ff21514d8981	316	*/
AnnaBridge	156:ff21514d8981	317
AnnaBridge	156:ff21514d8981	318	/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
AnnaBridge	156:ff21514d8981	319	* @{
AnnaBridge	156:ff21514d8981	320	*/
AnnaBridge	156:ff21514d8981	321	#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	322	#define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
AnnaBridge	156:ff21514d8981	323	/**
AnnaBridge	156:ff21514d8981	324	* @}
AnnaBridge	156:ff21514d8981	325	*/
AnnaBridge	156:ff21514d8981	326
AnnaBridge	156:ff21514d8981	327	/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
AnnaBridge	156:ff21514d8981	328	* @{
AnnaBridge	156:ff21514d8981	329	*/
AnnaBridge	156:ff21514d8981	330	#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
AnnaBridge	156:ff21514d8981	331	#define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
AnnaBridge	156:ff21514d8981	332	/**
AnnaBridge	156:ff21514d8981	333	* @}
AnnaBridge	156:ff21514d8981	334	*/
AnnaBridge	156:ff21514d8981	335
AnnaBridge	156:ff21514d8981	336	/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
AnnaBridge	156:ff21514d8981	337	* @note These values are available only for the STM32F405/415/407/417xx devices.
AnnaBridge	156:ff21514d8981	338	* @{
AnnaBridge	156:ff21514d8981	339	*/
AnnaBridge	156:ff21514d8981	340	#define FSMC_WRAP_MODE_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	341	#define FSMC_WRAP_MODE_ENABLE 0x00000400U
AnnaBridge	156:ff21514d8981	342	/**
AnnaBridge	156:ff21514d8981	343	* @}
AnnaBridge	156:ff21514d8981	344	*/
AnnaBridge	156:ff21514d8981	345
AnnaBridge	156:ff21514d8981	346	/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
AnnaBridge	156:ff21514d8981	347	* @{
AnnaBridge	156:ff21514d8981	348	*/
AnnaBridge	156:ff21514d8981	349	#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
AnnaBridge	156:ff21514d8981	350	#define FSMC_WAIT_TIMING_DURING_WS 0x00000800U
AnnaBridge	156:ff21514d8981	351	/**
AnnaBridge	156:ff21514d8981	352	* @}
AnnaBridge	156:ff21514d8981	353	*/
AnnaBridge	156:ff21514d8981	354
AnnaBridge	156:ff21514d8981	355	/** @defgroup FSMC_Write_Operation FSMC Write Operation
AnnaBridge	156:ff21514d8981	356	* @{
AnnaBridge	156:ff21514d8981	357	*/
AnnaBridge	156:ff21514d8981	358	#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	359	#define FSMC_WRITE_OPERATION_ENABLE 0x00001000U
AnnaBridge	156:ff21514d8981	360	/**
AnnaBridge	156:ff21514d8981	361	* @}
AnnaBridge	156:ff21514d8981	362	*/
AnnaBridge	156:ff21514d8981	363
AnnaBridge	156:ff21514d8981	364	/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
AnnaBridge	156:ff21514d8981	365	* @{
AnnaBridge	156:ff21514d8981	366	*/
AnnaBridge	156:ff21514d8981	367	#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	368	#define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U
AnnaBridge	156:ff21514d8981	369	/**
AnnaBridge	156:ff21514d8981	370	* @}
AnnaBridge	156:ff21514d8981	371	*/
AnnaBridge	156:ff21514d8981	372
AnnaBridge	156:ff21514d8981	373	/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
AnnaBridge	156:ff21514d8981	374	* @{
AnnaBridge	156:ff21514d8981	375	*/
AnnaBridge	156:ff21514d8981	376	#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	377	#define FSMC_EXTENDED_MODE_ENABLE 0x00004000U
AnnaBridge	156:ff21514d8981	378	/**
AnnaBridge	156:ff21514d8981	379	* @}
AnnaBridge	156:ff21514d8981	380	*/
AnnaBridge	156:ff21514d8981	381
AnnaBridge	156:ff21514d8981	382	/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
AnnaBridge	156:ff21514d8981	383	* @{
AnnaBridge	156:ff21514d8981	384	*/
AnnaBridge	156:ff21514d8981	385	#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	386	#define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
AnnaBridge	156:ff21514d8981	387	/**
AnnaBridge	156:ff21514d8981	388	* @}
AnnaBridge	156:ff21514d8981	389	*/
AnnaBridge	156:ff21514d8981	390
AnnaBridge	156:ff21514d8981	391	/** @defgroup FSMC_Page_Size FSMC Page Size
AnnaBridge	156:ff21514d8981	392	* @{
AnnaBridge	156:ff21514d8981	393	*/
AnnaBridge	156:ff21514d8981	394	#define FSMC_PAGE_SIZE_NONE 0x00000000U
AnnaBridge	156:ff21514d8981	395	#define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
AnnaBridge	156:ff21514d8981	396	#define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
AnnaBridge	156:ff21514d8981	397	#define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 \| FSMC_BCR1_CPSIZE_1))
AnnaBridge	156:ff21514d8981	398	#define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2)
AnnaBridge	156:ff21514d8981	399	/**
AnnaBridge	156:ff21514d8981	400	* @}
AnnaBridge	156:ff21514d8981	401	*/
AnnaBridge	156:ff21514d8981	402
AnnaBridge	156:ff21514d8981	403	/** @defgroup FSMC_Write_FIFO FSMC Write FIFO
AnnaBridge	156:ff21514d8981	404	* @note These values are available only for the STM32F412Vx/Zx/Rx devices.
AnnaBridge	156:ff21514d8981	405	* @{
AnnaBridge	156:ff21514d8981	406	*/
AnnaBridge	156:ff21514d8981	407	#define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
AnnaBridge	156:ff21514d8981	408	#define FSMC_WRITE_FIFO_ENABLE 0x00000000U
AnnaBridge	156:ff21514d8981	409	/**
AnnaBridge	156:ff21514d8981	410	* @}
AnnaBridge	156:ff21514d8981	411	*/
AnnaBridge	156:ff21514d8981	412
AnnaBridge	156:ff21514d8981	413	/** @defgroup FSMC_Write_Burst FSMC Write Burst
AnnaBridge	156:ff21514d8981	414	* @{
AnnaBridge	156:ff21514d8981	415	*/
AnnaBridge	156:ff21514d8981	416	#define FSMC_WRITE_BURST_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	417	#define FSMC_WRITE_BURST_ENABLE 0x00080000U
AnnaBridge	156:ff21514d8981	418	/**
AnnaBridge	156:ff21514d8981	419	* @}
AnnaBridge	156:ff21514d8981	420	*/
AnnaBridge	156:ff21514d8981	421
AnnaBridge	156:ff21514d8981	422	/** @defgroup FSMC_Continous_Clock FSMC Continous Clock
AnnaBridge	156:ff21514d8981	423	* @note These values are available only for the STM32F412Vx/Zx/Rx devices.
AnnaBridge	156:ff21514d8981	424	* @{
AnnaBridge	156:ff21514d8981	425	*/
AnnaBridge	156:ff21514d8981	426	#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
AnnaBridge	156:ff21514d8981	427	#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
AnnaBridge	156:ff21514d8981	428	/**
AnnaBridge	156:ff21514d8981	429	* @}
AnnaBridge	156:ff21514d8981	430	*/
AnnaBridge	156:ff21514d8981	431
AnnaBridge	156:ff21514d8981	432	/** @defgroup FSMC_Access_Mode FSMC Access Mode
AnnaBridge	156:ff21514d8981	433	* @{
AnnaBridge	156:ff21514d8981	434	*/
AnnaBridge	156:ff21514d8981	435	#define FSMC_ACCESS_MODE_A 0x00000000U
AnnaBridge	156:ff21514d8981	436	#define FSMC_ACCESS_MODE_B 0x10000000U
AnnaBridge	156:ff21514d8981	437	#define FSMC_ACCESS_MODE_C 0x20000000U
AnnaBridge	156:ff21514d8981	438	#define FSMC_ACCESS_MODE_D 0x30000000U
AnnaBridge	156:ff21514d8981	439	/**
AnnaBridge	156:ff21514d8981	440	* @}
AnnaBridge	156:ff21514d8981	441	*/
AnnaBridge	156:ff21514d8981	442	/**
AnnaBridge	156:ff21514d8981	443	* @}
AnnaBridge	156:ff21514d8981	444	*/
AnnaBridge	156:ff21514d8981	445
AnnaBridge	156:ff21514d8981	446	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	447	/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
AnnaBridge	156:ff21514d8981	448	* @{
AnnaBridge	156:ff21514d8981	449	*/
AnnaBridge	156:ff21514d8981	450	/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
AnnaBridge	156:ff21514d8981	451	* @{
AnnaBridge	156:ff21514d8981	452	*/
AnnaBridge	156:ff21514d8981	453	#define FSMC_NAND_BANK2 0x00000010U
AnnaBridge	156:ff21514d8981	454	#define FSMC_NAND_BANK3 0x00000100U
AnnaBridge	156:ff21514d8981	455	/**
AnnaBridge	156:ff21514d8981	456	* @}
AnnaBridge	156:ff21514d8981	457	*/
AnnaBridge	156:ff21514d8981	458
AnnaBridge	156:ff21514d8981	459	/** @defgroup FSMC_Wait_feature FSMC Wait feature
AnnaBridge	156:ff21514d8981	460	* @{
AnnaBridge	156:ff21514d8981	461	*/
AnnaBridge	156:ff21514d8981	462	#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	463	#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
AnnaBridge	156:ff21514d8981	464	/**
AnnaBridge	156:ff21514d8981	465	* @}
AnnaBridge	156:ff21514d8981	466	*/
AnnaBridge	156:ff21514d8981	467
AnnaBridge	156:ff21514d8981	468	/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
AnnaBridge	156:ff21514d8981	469	* @{
AnnaBridge	156:ff21514d8981	470	*/
AnnaBridge	156:ff21514d8981	471	#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
AnnaBridge	156:ff21514d8981	472	#define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U
AnnaBridge	156:ff21514d8981	473	/**
AnnaBridge	156:ff21514d8981	474	* @}
AnnaBridge	156:ff21514d8981	475	*/
AnnaBridge	156:ff21514d8981	476
AnnaBridge	156:ff21514d8981	477	/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
AnnaBridge	156:ff21514d8981	478	* @{
AnnaBridge	156:ff21514d8981	479	*/
AnnaBridge	156:ff21514d8981	480	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	156:ff21514d8981	481	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
AnnaBridge	156:ff21514d8981	482	/**
AnnaBridge	156:ff21514d8981	483	* @}
AnnaBridge	156:ff21514d8981	484	*/
AnnaBridge	156:ff21514d8981	485
AnnaBridge	156:ff21514d8981	486	/** @defgroup FSMC_ECC FSMC ECC
AnnaBridge	156:ff21514d8981	487	* @{
AnnaBridge	156:ff21514d8981	488	*/
AnnaBridge	156:ff21514d8981	489	#define FSMC_NAND_ECC_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	490	#define FSMC_NAND_ECC_ENABLE 0x00000040U
AnnaBridge	156:ff21514d8981	491	/**
AnnaBridge	156:ff21514d8981	492	* @}
AnnaBridge	156:ff21514d8981	493	*/
AnnaBridge	156:ff21514d8981	494
AnnaBridge	156:ff21514d8981	495	/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
AnnaBridge	156:ff21514d8981	496	* @{
AnnaBridge	156:ff21514d8981	497	*/
AnnaBridge	156:ff21514d8981	498	#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
AnnaBridge	156:ff21514d8981	499	#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
AnnaBridge	156:ff21514d8981	500	#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
AnnaBridge	156:ff21514d8981	501	#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
AnnaBridge	156:ff21514d8981	502	#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
AnnaBridge	156:ff21514d8981	503	#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
AnnaBridge	156:ff21514d8981	504	/**
AnnaBridge	156:ff21514d8981	505	* @}
AnnaBridge	156:ff21514d8981	506	*/
AnnaBridge	156:ff21514d8981	507	/**
AnnaBridge	156:ff21514d8981	508	* @}
AnnaBridge	156:ff21514d8981	509	*/
AnnaBridge	156:ff21514d8981	510	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	511
AnnaBridge	156:ff21514d8981	512	/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
AnnaBridge	156:ff21514d8981	513	* @{
AnnaBridge	156:ff21514d8981	514	*/
AnnaBridge	156:ff21514d8981	515	#define FSMC_IT_RISING_EDGE 0x00000008U
AnnaBridge	156:ff21514d8981	516	#define FSMC_IT_LEVEL 0x00000010U
AnnaBridge	156:ff21514d8981	517	#define FSMC_IT_FALLING_EDGE 0x00000020U
AnnaBridge	156:ff21514d8981	518	#define FSMC_IT_REFRESH_ERROR 0x00004000U
AnnaBridge	156:ff21514d8981	519	/**
AnnaBridge	156:ff21514d8981	520	* @}
AnnaBridge	156:ff21514d8981	521	*/
AnnaBridge	156:ff21514d8981	522
AnnaBridge	156:ff21514d8981	523	/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
AnnaBridge	156:ff21514d8981	524	* @{
AnnaBridge	156:ff21514d8981	525	*/
AnnaBridge	156:ff21514d8981	526	#define FSMC_FLAG_RISING_EDGE 0x00000001U
AnnaBridge	156:ff21514d8981	527	#define FSMC_FLAG_LEVEL 0x00000002U
AnnaBridge	156:ff21514d8981	528	#define FSMC_FLAG_FALLING_EDGE 0x00000004U
AnnaBridge	156:ff21514d8981	529	#define FSMC_FLAG_FEMPT 0x00000040U
AnnaBridge	156:ff21514d8981	530	/**
AnnaBridge	156:ff21514d8981	531	* @}
AnnaBridge	156:ff21514d8981	532	*/
AnnaBridge	156:ff21514d8981	533
AnnaBridge	156:ff21514d8981	534	/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
AnnaBridge	156:ff21514d8981	535	* @{
AnnaBridge	156:ff21514d8981	536	*/
AnnaBridge	156:ff21514d8981	537	#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
AnnaBridge	156:ff21514d8981	538	#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
AnnaBridge	156:ff21514d8981	539	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	540	#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
AnnaBridge	156:ff21514d8981	541	#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
AnnaBridge	156:ff21514d8981	542	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	543
AnnaBridge	156:ff21514d8981	544	#define FSMC_NORSRAM_DEVICE FSMC_Bank1
AnnaBridge	156:ff21514d8981	545	#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
AnnaBridge	156:ff21514d8981	546	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	547	#define FSMC_NAND_DEVICE FSMC_Bank2_3
AnnaBridge	156:ff21514d8981	548	#define FSMC_PCCARD_DEVICE FSMC_Bank4
AnnaBridge	156:ff21514d8981	549	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	550
AnnaBridge	156:ff21514d8981	551	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
AnnaBridge	156:ff21514d8981	552	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
AnnaBridge	156:ff21514d8981	553	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
AnnaBridge	156:ff21514d8981	554
AnnaBridge	156:ff21514d8981	555	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
AnnaBridge	156:ff21514d8981	556	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
AnnaBridge	156:ff21514d8981	557	#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
AnnaBridge	156:ff21514d8981	558	#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
AnnaBridge	156:ff21514d8981	559
AnnaBridge	156:ff21514d8981	560	#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
AnnaBridge	156:ff21514d8981	561	#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
AnnaBridge	156:ff21514d8981	562	#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
AnnaBridge	156:ff21514d8981	563	#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
AnnaBridge	156:ff21514d8981	564	#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
AnnaBridge	156:ff21514d8981	565	#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
AnnaBridge	156:ff21514d8981	566
AnnaBridge	156:ff21514d8981	567	#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
AnnaBridge	156:ff21514d8981	568	#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
AnnaBridge	156:ff21514d8981	569
AnnaBridge	156:ff21514d8981	570	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	571	#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
AnnaBridge	156:ff21514d8981	572	#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
AnnaBridge	156:ff21514d8981	573	#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
AnnaBridge	156:ff21514d8981	574
AnnaBridge	156:ff21514d8981	575	#define FMC_NAND_Init FSMC_NAND_Init
AnnaBridge	156:ff21514d8981	576	#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
AnnaBridge	156:ff21514d8981	577	#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
AnnaBridge	156:ff21514d8981	578	#define FMC_NAND_DeInit FSMC_NAND_DeInit
AnnaBridge	156:ff21514d8981	579	#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
AnnaBridge	156:ff21514d8981	580	#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
AnnaBridge	156:ff21514d8981	581	#define FMC_NAND_GetECC FSMC_NAND_GetECC
AnnaBridge	156:ff21514d8981	582	#define FMC_PCCARD_Init FSMC_PCCARD_Init
AnnaBridge	156:ff21514d8981	583	#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
AnnaBridge	156:ff21514d8981	584	#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
AnnaBridge	156:ff21514d8981	585	#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
AnnaBridge	156:ff21514d8981	586	#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
AnnaBridge	156:ff21514d8981	587
AnnaBridge	156:ff21514d8981	588	#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
AnnaBridge	156:ff21514d8981	589	#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
AnnaBridge	156:ff21514d8981	590	#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
AnnaBridge	156:ff21514d8981	591	#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
AnnaBridge	156:ff21514d8981	592	#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
AnnaBridge	156:ff21514d8981	593	#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
AnnaBridge	156:ff21514d8981	594	#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
AnnaBridge	156:ff21514d8981	595	#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
AnnaBridge	156:ff21514d8981	596	#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
AnnaBridge	156:ff21514d8981	597	#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
AnnaBridge	156:ff21514d8981	598	#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
AnnaBridge	156:ff21514d8981	599	#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
AnnaBridge	156:ff21514d8981	600	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	601
AnnaBridge	156:ff21514d8981	602	#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
AnnaBridge	156:ff21514d8981	603	#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
AnnaBridge	156:ff21514d8981	604	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	605	#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
AnnaBridge	156:ff21514d8981	606	#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
AnnaBridge	156:ff21514d8981	607	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	608
AnnaBridge	156:ff21514d8981	609	#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
AnnaBridge	156:ff21514d8981	610	#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
AnnaBridge	156:ff21514d8981	611	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	612	#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
AnnaBridge	156:ff21514d8981	613	#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
AnnaBridge	156:ff21514d8981	614
AnnaBridge	156:ff21514d8981	615	#define FMC_NAND_BANK2 FSMC_NAND_BANK2
AnnaBridge	156:ff21514d8981	616	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	617
AnnaBridge	156:ff21514d8981	618	#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
AnnaBridge	156:ff21514d8981	619	#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
AnnaBridge	156:ff21514d8981	620	#define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
AnnaBridge	156:ff21514d8981	621
AnnaBridge	156:ff21514d8981	622	#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
AnnaBridge	156:ff21514d8981	623	#define FMC_IT_LEVEL FSMC_IT_LEVEL
AnnaBridge	156:ff21514d8981	624	#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
AnnaBridge	156:ff21514d8981	625	#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
AnnaBridge	156:ff21514d8981	626
AnnaBridge	156:ff21514d8981	627	#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
AnnaBridge	156:ff21514d8981	628	#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
AnnaBridge	156:ff21514d8981	629	#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
AnnaBridge	156:ff21514d8981	630	#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
AnnaBridge	156:ff21514d8981	631	/**
AnnaBridge	156:ff21514d8981	632	* @}
AnnaBridge	156:ff21514d8981	633	*/
AnnaBridge	156:ff21514d8981	634
AnnaBridge	156:ff21514d8981	635	/**
AnnaBridge	156:ff21514d8981	636	* @}
AnnaBridge	156:ff21514d8981	637	*/
AnnaBridge	156:ff21514d8981	638
AnnaBridge	156:ff21514d8981	639	/* Private macro -------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	640	/** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
AnnaBridge	156:ff21514d8981	641	* @{
AnnaBridge	156:ff21514d8981	642	*/
AnnaBridge	156:ff21514d8981	643
AnnaBridge	156:ff21514d8981	644	/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
AnnaBridge	156:ff21514d8981	645	* @brief macros to handle NOR device enable/disable and read/write operations
AnnaBridge	156:ff21514d8981	646	* @{
AnnaBridge	156:ff21514d8981	647	*/
AnnaBridge	156:ff21514d8981	648	/**
AnnaBridge	156:ff21514d8981	649	* @brief Enable the NORSRAM device access.
AnnaBridge	163:e59c8e839560	650	* @param __INSTANCE__ FSMC_NORSRAM Instance
AnnaBridge	163:e59c8e839560	651	* @param __BANK__ FSMC_NORSRAM Bank
AnnaBridge	156:ff21514d8981	652	* @retval none
AnnaBridge	156:ff21514d8981	653	*/
AnnaBridge	156:ff21514d8981	654	#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FSMC_BCR1_MBKEN)
AnnaBridge	156:ff21514d8981	655
AnnaBridge	156:ff21514d8981	656	/**
AnnaBridge	156:ff21514d8981	657	* @brief Disable the NORSRAM device access.
AnnaBridge	163:e59c8e839560	658	* @param __INSTANCE__ FSMC_NORSRAM Instance
AnnaBridge	163:e59c8e839560	659	* @param __BANK__ FSMC_NORSRAM Bank
AnnaBridge	156:ff21514d8981	660	* @retval none
AnnaBridge	156:ff21514d8981	661	*/
AnnaBridge	156:ff21514d8981	662	#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
AnnaBridge	156:ff21514d8981	663	/**
AnnaBridge	156:ff21514d8981	664	* @}
AnnaBridge	156:ff21514d8981	665	*/
AnnaBridge	156:ff21514d8981	666
AnnaBridge	156:ff21514d8981	667	/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
AnnaBridge	156:ff21514d8981	668	* @brief macros to handle NAND device enable/disable
AnnaBridge	156:ff21514d8981	669	* @{
AnnaBridge	156:ff21514d8981	670	*/
AnnaBridge	156:ff21514d8981	671	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	672	/**
AnnaBridge	156:ff21514d8981	673	* @brief Enable the NAND device access.
AnnaBridge	163:e59c8e839560	674	* @param __INSTANCE__ FSMC_NAND Instance
AnnaBridge	163:e59c8e839560	675	* @param __BANK__ FSMC_NAND Bank
AnnaBridge	156:ff21514d8981	676	* @retval none
AnnaBridge	156:ff21514d8981	677	*/
AnnaBridge	156:ff21514d8981	678	#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FSMC_PCR2_PBKEN): \
AnnaBridge	156:ff21514d8981	679	((__INSTANCE__)->PCR3 \|= FSMC_PCR3_PBKEN))
AnnaBridge	156:ff21514d8981	680
AnnaBridge	156:ff21514d8981	681	/**
AnnaBridge	156:ff21514d8981	682	* @brief Disable the NAND device access.
AnnaBridge	163:e59c8e839560	683	* @param __INSTANCE__ FSMC_NAND Instance
AnnaBridge	163:e59c8e839560	684	* @param __BANK__ FSMC_NAND Bank
AnnaBridge	156:ff21514d8981	685	* @retval none
AnnaBridge	156:ff21514d8981	686	*/
AnnaBridge	156:ff21514d8981	687	#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
AnnaBridge	156:ff21514d8981	688	((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
AnnaBridge	156:ff21514d8981	689	/**
AnnaBridge	156:ff21514d8981	690	* @}
AnnaBridge	156:ff21514d8981	691	*/
AnnaBridge	156:ff21514d8981	692
AnnaBridge	156:ff21514d8981	693	/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
AnnaBridge	156:ff21514d8981	694	* @brief macros to handle SRAM read/write operations
AnnaBridge	156:ff21514d8981	695	* @{
AnnaBridge	156:ff21514d8981	696	*/
AnnaBridge	156:ff21514d8981	697	/**
AnnaBridge	156:ff21514d8981	698	* @brief Enable the PCCARD device access.
AnnaBridge	163:e59c8e839560	699	* @param __INSTANCE__ FSMC_PCCARD Instance
AnnaBridge	156:ff21514d8981	700	* @retval none
AnnaBridge	156:ff21514d8981	701	*/
AnnaBridge	156:ff21514d8981	702	#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FSMC_PCR4_PBKEN)
AnnaBridge	156:ff21514d8981	703
AnnaBridge	156:ff21514d8981	704	/**
AnnaBridge	156:ff21514d8981	705	* @brief Disable the PCCARD device access.
AnnaBridge	163:e59c8e839560	706	* @param __INSTANCE__ FSMC_PCCARD Instance
AnnaBridge	156:ff21514d8981	707	* @retval none
AnnaBridge	156:ff21514d8981	708	*/
AnnaBridge	156:ff21514d8981	709	#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
AnnaBridge	156:ff21514d8981	710	/**
AnnaBridge	156:ff21514d8981	711	* @}
AnnaBridge	156:ff21514d8981	712	*/
AnnaBridge	156:ff21514d8981	713
AnnaBridge	156:ff21514d8981	714	/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
AnnaBridge	156:ff21514d8981	715	* @brief macros to handle FSMC flags and interrupts
AnnaBridge	156:ff21514d8981	716	* @{
AnnaBridge	156:ff21514d8981	717	*/
AnnaBridge	156:ff21514d8981	718	/**
AnnaBridge	156:ff21514d8981	719	* @brief Enable the NAND device interrupt.
AnnaBridge	163:e59c8e839560	720	* @param __INSTANCE__ FSMC_NAND Instance
AnnaBridge	163:e59c8e839560	721	* @param __BANK__ FSMC_NAND Bank
AnnaBridge	163:e59c8e839560	722	* @param __INTERRUPT__ FSMC_NAND interrupt
AnnaBridge	156:ff21514d8981	723	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	724	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	156:ff21514d8981	725	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	156:ff21514d8981	726	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	156:ff21514d8981	727	* @retval None
AnnaBridge	156:ff21514d8981	728	*/
AnnaBridge	156:ff21514d8981	729	#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
AnnaBridge	156:ff21514d8981	730	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
AnnaBridge	156:ff21514d8981	731
AnnaBridge	156:ff21514d8981	732	/**
AnnaBridge	156:ff21514d8981	733	* @brief Disable the NAND device interrupt.
AnnaBridge	163:e59c8e839560	734	* @param __INSTANCE__ FSMC_NAND Instance
AnnaBridge	163:e59c8e839560	735	* @param __BANK__ FSMC_NAND Bank
AnnaBridge	163:e59c8e839560	736	* @param __INTERRUPT__ FSMC_NAND interrupt
AnnaBridge	156:ff21514d8981	737	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	738	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	156:ff21514d8981	739	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	156:ff21514d8981	740	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	156:ff21514d8981	741	* @retval None
AnnaBridge	156:ff21514d8981	742	*/
AnnaBridge	156:ff21514d8981	743	#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
AnnaBridge	156:ff21514d8981	744	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
AnnaBridge	156:ff21514d8981	745
AnnaBridge	156:ff21514d8981	746	/**
AnnaBridge	156:ff21514d8981	747	* @brief Get flag status of the NAND device.
AnnaBridge	163:e59c8e839560	748	* @param __INSTANCE__ FSMC_NAND Instance
AnnaBridge	163:e59c8e839560	749	* @param __BANK__ FSMC_NAND Bank
AnnaBridge	163:e59c8e839560	750	* @param __FLAG__ FSMC_NAND flag
AnnaBridge	156:ff21514d8981	751	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	752	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	156:ff21514d8981	753	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	156:ff21514d8981	754	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	156:ff21514d8981	755	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	156:ff21514d8981	756	* @retval The state of FLAG (SET or RESET).
AnnaBridge	156:ff21514d8981	757	*/
AnnaBridge	156:ff21514d8981	758	#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
AnnaBridge	156:ff21514d8981	759	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
AnnaBridge	156:ff21514d8981	760
AnnaBridge	156:ff21514d8981	761	/**
AnnaBridge	156:ff21514d8981	762	* @brief Clear flag status of the NAND device.
AnnaBridge	163:e59c8e839560	763	* @param __INSTANCE__ FSMC_NAND Instance
AnnaBridge	163:e59c8e839560	764	* @param __BANK__ FSMC_NAND Bank
AnnaBridge	163:e59c8e839560	765	* @param __FLAG__ FSMC_NAND flag
AnnaBridge	156:ff21514d8981	766	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	767	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	156:ff21514d8981	768	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	156:ff21514d8981	769	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	156:ff21514d8981	770	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	156:ff21514d8981	771	* @retval None
AnnaBridge	156:ff21514d8981	772	*/
AnnaBridge	156:ff21514d8981	773	#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
AnnaBridge	156:ff21514d8981	774	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
AnnaBridge	156:ff21514d8981	775
AnnaBridge	156:ff21514d8981	776	/**
AnnaBridge	156:ff21514d8981	777	* @brief Enable the PCCARD device interrupt.
AnnaBridge	163:e59c8e839560	778	* @param __INSTANCE__ FSMC_PCCARD Instance
AnnaBridge	163:e59c8e839560	779	* @param __INTERRUPT__ FSMC_PCCARD interrupt
AnnaBridge	156:ff21514d8981	780	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	781	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	156:ff21514d8981	782	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	156:ff21514d8981	783	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	156:ff21514d8981	784	* @retval None
AnnaBridge	156:ff21514d8981	785	*/
AnnaBridge	156:ff21514d8981	786	#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
AnnaBridge	156:ff21514d8981	787
AnnaBridge	156:ff21514d8981	788	/**
AnnaBridge	156:ff21514d8981	789	* @brief Disable the PCCARD device interrupt.
AnnaBridge	163:e59c8e839560	790	* @param __INSTANCE__ FSMC_PCCARD Instance
AnnaBridge	163:e59c8e839560	791	* @param __INTERRUPT__ FSMC_PCCARD interrupt
AnnaBridge	156:ff21514d8981	792	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	793	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	156:ff21514d8981	794	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	156:ff21514d8981	795	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	156:ff21514d8981	796	* @retval None
AnnaBridge	156:ff21514d8981	797	*/
AnnaBridge	156:ff21514d8981	798	#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
AnnaBridge	156:ff21514d8981	799
AnnaBridge	156:ff21514d8981	800	/**
AnnaBridge	156:ff21514d8981	801	* @brief Get flag status of the PCCARD device.
AnnaBridge	163:e59c8e839560	802	* @param __INSTANCE__ FSMC_PCCARD Instance
AnnaBridge	163:e59c8e839560	803	* @param __FLAG__ FSMC_PCCARD flag
AnnaBridge	156:ff21514d8981	804	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	805	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	156:ff21514d8981	806	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	156:ff21514d8981	807	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	156:ff21514d8981	808	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	156:ff21514d8981	809	* @retval The state of FLAG (SET or RESET).
AnnaBridge	156:ff21514d8981	810	*/
AnnaBridge	156:ff21514d8981	811	#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
AnnaBridge	156:ff21514d8981	812
AnnaBridge	156:ff21514d8981	813	/**
AnnaBridge	156:ff21514d8981	814	* @brief Clear flag status of the PCCARD device.
AnnaBridge	163:e59c8e839560	815	* @param __INSTANCE__ FSMC_PCCARD Instance
AnnaBridge	163:e59c8e839560	816	* @param __FLAG__ FSMC_PCCARD flag
AnnaBridge	156:ff21514d8981	817	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	818	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	156:ff21514d8981	819	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	156:ff21514d8981	820	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	156:ff21514d8981	821	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	156:ff21514d8981	822	* @retval None
AnnaBridge	156:ff21514d8981	823	*/
AnnaBridge	156:ff21514d8981	824	#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
AnnaBridge	156:ff21514d8981	825	/**
AnnaBridge	156:ff21514d8981	826	* @}
AnnaBridge	156:ff21514d8981	827	*/
AnnaBridge	156:ff21514d8981	828	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	829
AnnaBridge	156:ff21514d8981	830	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
AnnaBridge	156:ff21514d8981	831	* @{
AnnaBridge	156:ff21514d8981	832	*/
AnnaBridge	156:ff21514d8981	833	#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) \|\| \
AnnaBridge	156:ff21514d8981	834	((__BANK__) == FSMC_NORSRAM_BANK2) \|\| \
AnnaBridge	156:ff21514d8981	835	((__BANK__) == FSMC_NORSRAM_BANK3) \|\| \
AnnaBridge	156:ff21514d8981	836	((__BANK__) == FSMC_NORSRAM_BANK4))
AnnaBridge	156:ff21514d8981	837
AnnaBridge	156:ff21514d8981	838	#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	839	((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
AnnaBridge	156:ff21514d8981	840
AnnaBridge	156:ff21514d8981	841	#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) \|\| \
AnnaBridge	156:ff21514d8981	842	((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)\|\| \
AnnaBridge	156:ff21514d8981	843	((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
AnnaBridge	156:ff21514d8981	844
AnnaBridge	156:ff21514d8981	845	#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	156:ff21514d8981	846	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
AnnaBridge	156:ff21514d8981	847	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
AnnaBridge	156:ff21514d8981	848
AnnaBridge	156:ff21514d8981	849	#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) \|\| \
AnnaBridge	156:ff21514d8981	850	((__MODE__) == FSMC_ACCESS_MODE_B) \|\| \
AnnaBridge	156:ff21514d8981	851	((__MODE__) == FSMC_ACCESS_MODE_C) \|\| \
AnnaBridge	156:ff21514d8981	852	((__MODE__) == FSMC_ACCESS_MODE_D))
AnnaBridge	156:ff21514d8981	853
AnnaBridge	156:ff21514d8981	854	#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) \|\| \
AnnaBridge	156:ff21514d8981	855	((BANK) == FSMC_NAND_BANK3))
AnnaBridge	156:ff21514d8981	856
AnnaBridge	156:ff21514d8981	857	#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	858	((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
AnnaBridge	156:ff21514d8981	859
AnnaBridge	156:ff21514d8981	860	#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	156:ff21514d8981	861	((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
AnnaBridge	156:ff21514d8981	862
AnnaBridge	156:ff21514d8981	863	#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	864	((STATE) == FSMC_NAND_ECC_ENABLE))
AnnaBridge	156:ff21514d8981	865
AnnaBridge	156:ff21514d8981	866	#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
AnnaBridge	156:ff21514d8981	867	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
AnnaBridge	156:ff21514d8981	868	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
AnnaBridge	156:ff21514d8981	869	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
AnnaBridge	156:ff21514d8981	870	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
AnnaBridge	156:ff21514d8981	871	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
AnnaBridge	156:ff21514d8981	872
AnnaBridge	156:ff21514d8981	873	#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	156:ff21514d8981	874
AnnaBridge	156:ff21514d8981	875	#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	156:ff21514d8981	876
AnnaBridge	156:ff21514d8981	877	#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	156:ff21514d8981	878
AnnaBridge	156:ff21514d8981	879	#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	156:ff21514d8981	880
AnnaBridge	156:ff21514d8981	881	#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	156:ff21514d8981	882
AnnaBridge	156:ff21514d8981	883	#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	156:ff21514d8981	884
AnnaBridge	156:ff21514d8981	885	#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
AnnaBridge	156:ff21514d8981	886
AnnaBridge	156:ff21514d8981	887	#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
AnnaBridge	156:ff21514d8981	888
AnnaBridge	156:ff21514d8981	889	#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
AnnaBridge	156:ff21514d8981	890
AnnaBridge	156:ff21514d8981	891	#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
AnnaBridge	156:ff21514d8981	892
AnnaBridge	156:ff21514d8981	893	#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	894	((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
AnnaBridge	156:ff21514d8981	895
AnnaBridge	156:ff21514d8981	896	#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
AnnaBridge	156:ff21514d8981	897	((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
AnnaBridge	156:ff21514d8981	898
AnnaBridge	156:ff21514d8981	899	#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	900	((__MODE__) == FSMC_WRAP_MODE_ENABLE))
AnnaBridge	156:ff21514d8981	901
AnnaBridge	156:ff21514d8981	902	#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) \|\| \
AnnaBridge	156:ff21514d8981	903	((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
AnnaBridge	156:ff21514d8981	904
AnnaBridge	156:ff21514d8981	905	#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	906	((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
AnnaBridge	156:ff21514d8981	907
AnnaBridge	156:ff21514d8981	908	#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	909	((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
AnnaBridge	156:ff21514d8981	910
AnnaBridge	156:ff21514d8981	911	#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	912	((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
AnnaBridge	156:ff21514d8981	913
AnnaBridge	156:ff21514d8981	914	#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	915	((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
AnnaBridge	156:ff21514d8981	916
AnnaBridge	156:ff21514d8981	917	#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
AnnaBridge	156:ff21514d8981	918
AnnaBridge	156:ff21514d8981	919	#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	920	((__BURST__) == FSMC_WRITE_BURST_ENABLE))
AnnaBridge	156:ff21514d8981	921
AnnaBridge	156:ff21514d8981	922	#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	156:ff21514d8981	923
AnnaBridge	156:ff21514d8981	924	#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
AnnaBridge	156:ff21514d8981	925
AnnaBridge	156:ff21514d8981	926	#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
AnnaBridge	156:ff21514d8981	927
AnnaBridge	156:ff21514d8981	928	#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	156:ff21514d8981	929
AnnaBridge	156:ff21514d8981	930	#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
AnnaBridge	156:ff21514d8981	931	((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
AnnaBridge	156:ff21514d8981	932
AnnaBridge	156:ff21514d8981	933	#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
AnnaBridge	156:ff21514d8981	934
AnnaBridge	156:ff21514d8981	935	#define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) \|\| \
AnnaBridge	156:ff21514d8981	936	((SIZE) == FSMC_PAGE_SIZE_128) \|\| \
AnnaBridge	156:ff21514d8981	937	((SIZE) == FSMC_PAGE_SIZE_256) \|\| \
AnnaBridge	156:ff21514d8981	938	((SIZE) == FSMC_PAGE_SIZE_512) \|\| \
AnnaBridge	156:ff21514d8981	939	((SIZE) == FSMC_PAGE_SIZE_1024))
AnnaBridge	156:ff21514d8981	940
AnnaBridge	156:ff21514d8981	941	#define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	942	((FIFO) == FSMC_WRITE_FIFO_ENABLE))
AnnaBridge	156:ff21514d8981	943
AnnaBridge	156:ff21514d8981	944	/**
AnnaBridge	156:ff21514d8981	945	* @}
AnnaBridge	156:ff21514d8981	946	*/
AnnaBridge	156:ff21514d8981	947	/**
AnnaBridge	156:ff21514d8981	948	* @}
AnnaBridge	156:ff21514d8981	949	*/
AnnaBridge	156:ff21514d8981	950
AnnaBridge	156:ff21514d8981	951	/* Private functions ---------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	952	/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
AnnaBridge	156:ff21514d8981	953	* @{
AnnaBridge	156:ff21514d8981	954	*/
AnnaBridge	156:ff21514d8981	955
AnnaBridge	156:ff21514d8981	956	/** @defgroup FSMC_LL_NORSRAM NOR SRAM
AnnaBridge	156:ff21514d8981	957	* @{
AnnaBridge	156:ff21514d8981	958	*/
AnnaBridge	156:ff21514d8981	959
AnnaBridge	156:ff21514d8981	960	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
AnnaBridge	156:ff21514d8981	961	* @{
AnnaBridge	156:ff21514d8981	962	*/
AnnaBridge	156:ff21514d8981	963	HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_InitTypeDef Init);
AnnaBridge	156:ff21514d8981	964	HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	156:ff21514d8981	965	HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
AnnaBridge	156:ff21514d8981	966	HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
AnnaBridge	156:ff21514d8981	967	/**
AnnaBridge	156:ff21514d8981	968	* @}
AnnaBridge	156:ff21514d8981	969	*/
AnnaBridge	156:ff21514d8981	970
AnnaBridge	156:ff21514d8981	971	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
AnnaBridge	156:ff21514d8981	972	* @{
AnnaBridge	156:ff21514d8981	973	*/
AnnaBridge	156:ff21514d8981	974	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	975	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	976	/**
AnnaBridge	156:ff21514d8981	977	* @}
AnnaBridge	156:ff21514d8981	978	*/
AnnaBridge	156:ff21514d8981	979	/**
AnnaBridge	156:ff21514d8981	980	* @}
AnnaBridge	156:ff21514d8981	981	*/
AnnaBridge	156:ff21514d8981	982
AnnaBridge	156:ff21514d8981	983	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	984	/** @defgroup FSMC_LL_NAND NAND
AnnaBridge	156:ff21514d8981	985	* @{
AnnaBridge	156:ff21514d8981	986	*/
AnnaBridge	156:ff21514d8981	987	/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
AnnaBridge	156:ff21514d8981	988	* @{
AnnaBridge	156:ff21514d8981	989	*/
AnnaBridge	156:ff21514d8981	990	HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_InitTypeDef Init);
AnnaBridge	156:ff21514d8981	991	HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	156:ff21514d8981	992	HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	156:ff21514d8981	993	HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	994	/**
AnnaBridge	156:ff21514d8981	995	* @}
AnnaBridge	156:ff21514d8981	996	*/
AnnaBridge	156:ff21514d8981	997
AnnaBridge	156:ff21514d8981	998	/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
AnnaBridge	156:ff21514d8981	999	* @{
AnnaBridge	156:ff21514d8981	1000	*/
AnnaBridge	156:ff21514d8981	1001	HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1002	HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1003	HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
AnnaBridge	156:ff21514d8981	1004	/**
AnnaBridge	156:ff21514d8981	1005	* @}
AnnaBridge	156:ff21514d8981	1006	*/
AnnaBridge	156:ff21514d8981	1007	/**
AnnaBridge	156:ff21514d8981	1008	* @}
AnnaBridge	156:ff21514d8981	1009	*/
AnnaBridge	156:ff21514d8981	1010
AnnaBridge	156:ff21514d8981	1011	/** @defgroup FSMC_LL_PCCARD PCCARD
AnnaBridge	156:ff21514d8981	1012	* @{
AnnaBridge	156:ff21514d8981	1013	*/
AnnaBridge	156:ff21514d8981	1014	/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
AnnaBridge	156:ff21514d8981	1015	* @{
AnnaBridge	156:ff21514d8981	1016	*/
AnnaBridge	156:ff21514d8981	1017	HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef Device, FSMC_PCCARD_InitTypeDef Init);
AnnaBridge	156:ff21514d8981	1018	HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	156:ff21514d8981	1019	HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	156:ff21514d8981	1020	HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	156:ff21514d8981	1021	HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
AnnaBridge	156:ff21514d8981	1022	/**
AnnaBridge	156:ff21514d8981	1023	* @}
AnnaBridge	156:ff21514d8981	1024	*/
AnnaBridge	156:ff21514d8981	1025	/**
AnnaBridge	156:ff21514d8981	1026	* @}
AnnaBridge	156:ff21514d8981	1027	*/
AnnaBridge	156:ff21514d8981	1028	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	1029
AnnaBridge	156:ff21514d8981	1030	/**
AnnaBridge	156:ff21514d8981	1031	* @}
AnnaBridge	156:ff21514d8981	1032	*/
AnnaBridge	156:ff21514d8981	1033	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	1034
AnnaBridge	156:ff21514d8981	1035	/**
AnnaBridge	156:ff21514d8981	1036	* @}
AnnaBridge	156:ff21514d8981	1037	*/
AnnaBridge	156:ff21514d8981	1038
AnnaBridge	156:ff21514d8981	1039	/**
AnnaBridge	156:ff21514d8981	1040	* @}
AnnaBridge	156:ff21514d8981	1041	*/
AnnaBridge	156:ff21514d8981	1042
AnnaBridge	156:ff21514d8981	1043	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	1044	}
AnnaBridge	156:ff21514d8981	1045	#endif
AnnaBridge	156:ff21514d8981	1046
AnnaBridge	156:ff21514d8981	1047	#endif /* __STM32F4xx_LL_FSMC_H */
AnnaBridge	156:ff21514d8981	1048
AnnaBridge	156:ff21514d8981	1049	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/