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TARGET_B96B_F446VE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:: Anna Bridge
Date:: Fri Jun 22 15:38:59 2018 +0100
Revision:: 169:a7c7b631e539
Parent:: 163:e59c8e839560

mbed library. Release version 162

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	156:ff21514d8981	1	/**
AnnaBridge	156:ff21514d8981	2	******************************************************************************
AnnaBridge	156:ff21514d8981	3	* @file stm32f4xx_ll_fmc.h
AnnaBridge	156:ff21514d8981	4	* @author MCD Application Team
AnnaBridge	156:ff21514d8981	5	* @brief Header file of FMC HAL module.
AnnaBridge	156:ff21514d8981	6	******************************************************************************
AnnaBridge	156:ff21514d8981	7	* @attention
AnnaBridge	156:ff21514d8981	8	*
AnnaBridge	156:ff21514d8981	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	156:ff21514d8981	10	*
AnnaBridge	156:ff21514d8981	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	156:ff21514d8981	12	* are permitted provided that the following conditions are met:
AnnaBridge	156:ff21514d8981	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	156:ff21514d8981	14	* this list of conditions and the following disclaimer.
AnnaBridge	156:ff21514d8981	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	156:ff21514d8981	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	156:ff21514d8981	17	* and/or other materials provided with the distribution.
AnnaBridge	156:ff21514d8981	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	156:ff21514d8981	19	* may be used to endorse or promote products derived from this software
AnnaBridge	156:ff21514d8981	20	* without specific prior written permission.
AnnaBridge	156:ff21514d8981	21	*
AnnaBridge	156:ff21514d8981	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	156:ff21514d8981	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	156:ff21514d8981	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	156:ff21514d8981	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	156:ff21514d8981	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	156:ff21514d8981	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	156:ff21514d8981	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	156:ff21514d8981	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	156:ff21514d8981	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	156:ff21514d8981	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	156:ff21514d8981	32	*
AnnaBridge	156:ff21514d8981	33	******************************************************************************
AnnaBridge	156:ff21514d8981	34	*/
AnnaBridge	156:ff21514d8981	35
AnnaBridge	156:ff21514d8981	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	156:ff21514d8981	37	#ifndef __STM32F4xx_LL_FMC_H
AnnaBridge	156:ff21514d8981	38	#define __STM32F4xx_LL_FMC_H
AnnaBridge	156:ff21514d8981	39
AnnaBridge	156:ff21514d8981	40	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	41	extern "C" {
AnnaBridge	156:ff21514d8981	42	#endif
AnnaBridge	156:ff21514d8981	43
AnnaBridge	156:ff21514d8981	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	45	#include "stm32f4xx_hal_def.h"
AnnaBridge	156:ff21514d8981	46
AnnaBridge	156:ff21514d8981	47	/** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge	156:ff21514d8981	48	* @{
AnnaBridge	156:ff21514d8981	49	*/
AnnaBridge	156:ff21514d8981	50
AnnaBridge	156:ff21514d8981	51	/** @addtogroup FMC_LL
AnnaBridge	156:ff21514d8981	52	* @{
AnnaBridge	156:ff21514d8981	53	*/
AnnaBridge	156:ff21514d8981	54	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	156:ff21514d8981	55	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	56	/* Private types -------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	57	/** @defgroup FMC_LL_Private_Types FMC Private Types
AnnaBridge	156:ff21514d8981	58	* @{
AnnaBridge	156:ff21514d8981	59	*/
AnnaBridge	156:ff21514d8981	60
AnnaBridge	156:ff21514d8981	61	/**
AnnaBridge	156:ff21514d8981	62	* @brief FMC NORSRAM Configuration Structure definition
AnnaBridge	156:ff21514d8981	63	*/
AnnaBridge	156:ff21514d8981	64	typedef struct
AnnaBridge	156:ff21514d8981	65	{
AnnaBridge	156:ff21514d8981	66	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
AnnaBridge	156:ff21514d8981	67	This parameter can be a value of @ref FMC_NORSRAM_Bank */
AnnaBridge	156:ff21514d8981	68
AnnaBridge	156:ff21514d8981	69	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
AnnaBridge	156:ff21514d8981	70	multiplexed on the data bus or not.
AnnaBridge	156:ff21514d8981	71	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
AnnaBridge	156:ff21514d8981	72
AnnaBridge	156:ff21514d8981	73	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
AnnaBridge	156:ff21514d8981	74	the corresponding memory device.
AnnaBridge	156:ff21514d8981	75	This parameter can be a value of @ref FMC_Memory_Type */
AnnaBridge	156:ff21514d8981	76
AnnaBridge	156:ff21514d8981	77	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	156:ff21514d8981	78	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
AnnaBridge	156:ff21514d8981	79
AnnaBridge	156:ff21514d8981	80	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
AnnaBridge	156:ff21514d8981	81	valid only with synchronous burst Flash memories.
AnnaBridge	156:ff21514d8981	82	This parameter can be a value of @ref FMC_Burst_Access_Mode */
AnnaBridge	156:ff21514d8981	83
AnnaBridge	156:ff21514d8981	84	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
AnnaBridge	156:ff21514d8981	85	the Flash memory in burst mode.
AnnaBridge	156:ff21514d8981	86	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
AnnaBridge	156:ff21514d8981	87
AnnaBridge	156:ff21514d8981	88	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
AnnaBridge	156:ff21514d8981	89	memory, valid only when accessing Flash memories in burst mode.
AnnaBridge	156:ff21514d8981	90	This parameter can be a value of @ref FMC_Wrap_Mode
AnnaBridge	156:ff21514d8981	91	This mode is not available for the STM32F446/467/479xx devices */
AnnaBridge	156:ff21514d8981	92
AnnaBridge	156:ff21514d8981	93	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
AnnaBridge	156:ff21514d8981	94	clock cycle before the wait state or during the wait state,
AnnaBridge	156:ff21514d8981	95	valid only when accessing memories in burst mode.
AnnaBridge	156:ff21514d8981	96	This parameter can be a value of @ref FMC_Wait_Timing */
AnnaBridge	156:ff21514d8981	97
AnnaBridge	156:ff21514d8981	98	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
AnnaBridge	156:ff21514d8981	99	This parameter can be a value of @ref FMC_Write_Operation */
AnnaBridge	156:ff21514d8981	100
AnnaBridge	156:ff21514d8981	101	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
AnnaBridge	156:ff21514d8981	102	signal, valid for Flash memory access in burst mode.
AnnaBridge	156:ff21514d8981	103	This parameter can be a value of @ref FMC_Wait_Signal */
AnnaBridge	156:ff21514d8981	104
AnnaBridge	156:ff21514d8981	105	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
AnnaBridge	156:ff21514d8981	106	This parameter can be a value of @ref FMC_Extended_Mode */
AnnaBridge	156:ff21514d8981	107
AnnaBridge	156:ff21514d8981	108	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
AnnaBridge	156:ff21514d8981	109	valid only with asynchronous Flash memories.
AnnaBridge	156:ff21514d8981	110	This parameter can be a value of @ref FMC_AsynchronousWait */
AnnaBridge	156:ff21514d8981	111
AnnaBridge	156:ff21514d8981	112	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
AnnaBridge	156:ff21514d8981	113	This parameter can be a value of @ref FMC_Write_Burst */
AnnaBridge	156:ff21514d8981	114
AnnaBridge	156:ff21514d8981	115	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
AnnaBridge	156:ff21514d8981	116	This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge	156:ff21514d8981	117	through FMC_BCR2..4 registers.
AnnaBridge	156:ff21514d8981	118	This parameter can be a value of @ref FMC_Continous_Clock */
AnnaBridge	156:ff21514d8981	119
AnnaBridge	156:ff21514d8981	120	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
AnnaBridge	156:ff21514d8981	121	This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge	156:ff21514d8981	122	through FMC_BCR2..4 registers.
AnnaBridge	156:ff21514d8981	123	This parameter can be a value of @ref FMC_Write_FIFO
AnnaBridge	156:ff21514d8981	124	This mode is available only for the STM32F446/469/479xx devices */
AnnaBridge	156:ff21514d8981	125
AnnaBridge	156:ff21514d8981	126	uint32_t PageSize; /*!< Specifies the memory page size.
AnnaBridge	156:ff21514d8981	127	This parameter can be a value of @ref FMC_Page_Size */
AnnaBridge	156:ff21514d8981	128	}FMC_NORSRAM_InitTypeDef;
AnnaBridge	156:ff21514d8981	129
AnnaBridge	156:ff21514d8981	130	/**
AnnaBridge	156:ff21514d8981	131	* @brief FMC NORSRAM Timing parameters structure definition
AnnaBridge	156:ff21514d8981	132	*/
AnnaBridge	156:ff21514d8981	133	typedef struct
AnnaBridge	156:ff21514d8981	134	{
AnnaBridge	156:ff21514d8981	135	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	156:ff21514d8981	136	the duration of the address setup time.
AnnaBridge	156:ff21514d8981	137	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	138	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	156:ff21514d8981	139
AnnaBridge	156:ff21514d8981	140	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	156:ff21514d8981	141	the duration of the address hold time.
AnnaBridge	156:ff21514d8981	142	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	143	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	156:ff21514d8981	144
AnnaBridge	156:ff21514d8981	145	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	156:ff21514d8981	146	the duration of the data setup time.
AnnaBridge	156:ff21514d8981	147	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
AnnaBridge	156:ff21514d8981	148	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
AnnaBridge	156:ff21514d8981	149	NOR Flash memories. */
AnnaBridge	156:ff21514d8981	150
AnnaBridge	156:ff21514d8981	151	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	156:ff21514d8981	152	the duration of the bus turnaround.
AnnaBridge	156:ff21514d8981	153	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	154	@note This parameter is only used for multiplexed NOR Flash memories. */
AnnaBridge	156:ff21514d8981	155
AnnaBridge	156:ff21514d8981	156	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
AnnaBridge	156:ff21514d8981	157	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
AnnaBridge	156:ff21514d8981	158	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
AnnaBridge	156:ff21514d8981	159	accesses. */
AnnaBridge	156:ff21514d8981	160
AnnaBridge	156:ff21514d8981	161	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
AnnaBridge	156:ff21514d8981	162	to the memory before getting the first data.
AnnaBridge	156:ff21514d8981	163	The parameter value depends on the memory type as shown below:
AnnaBridge	156:ff21514d8981	164	- It must be set to 0 in case of a CRAM
AnnaBridge	156:ff21514d8981	165	- It is don't care in asynchronous NOR, SRAM or ROM accesses
AnnaBridge	156:ff21514d8981	166	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
AnnaBridge	156:ff21514d8981	167	with synchronous burst mode enable */
AnnaBridge	156:ff21514d8981	168
AnnaBridge	156:ff21514d8981	169	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
AnnaBridge	156:ff21514d8981	170	This parameter can be a value of @ref FMC_Access_Mode */
AnnaBridge	156:ff21514d8981	171	}FMC_NORSRAM_TimingTypeDef;
AnnaBridge	156:ff21514d8981	172
AnnaBridge	156:ff21514d8981	173	/**
AnnaBridge	156:ff21514d8981	174	* @brief FMC NAND Configuration Structure definition
AnnaBridge	156:ff21514d8981	175	*/
AnnaBridge	156:ff21514d8981	176	typedef struct
AnnaBridge	156:ff21514d8981	177	{
AnnaBridge	156:ff21514d8981	178	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
AnnaBridge	156:ff21514d8981	179	This parameter can be a value of @ref FMC_NAND_Bank */
AnnaBridge	156:ff21514d8981	180
AnnaBridge	156:ff21514d8981	181	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
AnnaBridge	156:ff21514d8981	182	This parameter can be any value of @ref FMC_Wait_feature */
AnnaBridge	156:ff21514d8981	183
AnnaBridge	156:ff21514d8981	184	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	156:ff21514d8981	185	This parameter can be any value of @ref FMC_NAND_Data_Width */
AnnaBridge	156:ff21514d8981	186
AnnaBridge	156:ff21514d8981	187	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
AnnaBridge	156:ff21514d8981	188	This parameter can be any value of @ref FMC_ECC */
AnnaBridge	156:ff21514d8981	189
AnnaBridge	156:ff21514d8981	190	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
AnnaBridge	156:ff21514d8981	191	This parameter can be any value of @ref FMC_ECC_Page_Size */
AnnaBridge	156:ff21514d8981	192
AnnaBridge	156:ff21514d8981	193	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	156:ff21514d8981	194	delay between CLE low and RE low.
AnnaBridge	156:ff21514d8981	195	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	196
AnnaBridge	156:ff21514d8981	197	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	156:ff21514d8981	198	delay between ALE low and RE low.
AnnaBridge	156:ff21514d8981	199	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	200	}FMC_NAND_InitTypeDef;
AnnaBridge	156:ff21514d8981	201
AnnaBridge	156:ff21514d8981	202	/**
AnnaBridge	156:ff21514d8981	203	* @brief FMC NAND/PCCARD Timing parameters structure definition
AnnaBridge	156:ff21514d8981	204	*/
AnnaBridge	156:ff21514d8981	205	typedef struct
AnnaBridge	156:ff21514d8981	206	{
AnnaBridge	156:ff21514d8981	207	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
AnnaBridge	156:ff21514d8981	208	the command assertion for NAND-Flash read or write access
AnnaBridge	156:ff21514d8981	209	to common/Attribute or I/O memory space (depending on
AnnaBridge	156:ff21514d8981	210	the memory space timing to be configured).
AnnaBridge	156:ff21514d8981	211	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	212
AnnaBridge	156:ff21514d8981	213	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
AnnaBridge	156:ff21514d8981	214	command for NAND-Flash read or write access to
AnnaBridge	156:ff21514d8981	215	common/Attribute or I/O memory space (depending on the
AnnaBridge	156:ff21514d8981	216	memory space timing to be configured).
AnnaBridge	156:ff21514d8981	217	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	218
AnnaBridge	156:ff21514d8981	219	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
AnnaBridge	156:ff21514d8981	220	(and data for write access) after the command de-assertion
AnnaBridge	156:ff21514d8981	221	for NAND-Flash read or write access to common/Attribute
AnnaBridge	156:ff21514d8981	222	or I/O memory space (depending on the memory space timing
AnnaBridge	156:ff21514d8981	223	to be configured).
AnnaBridge	156:ff21514d8981	224	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	225
AnnaBridge	156:ff21514d8981	226	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
AnnaBridge	156:ff21514d8981	227	data bus is kept in HiZ after the start of a NAND-Flash
AnnaBridge	156:ff21514d8981	228	write access to common/Attribute or I/O memory space (depending
AnnaBridge	156:ff21514d8981	229	on the memory space timing to be configured).
AnnaBridge	156:ff21514d8981	230	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	231	}FMC_NAND_PCC_TimingTypeDef;
AnnaBridge	156:ff21514d8981	232
AnnaBridge	156:ff21514d8981	233	/**
AnnaBridge	156:ff21514d8981	234	* @brief FMC NAND Configuration Structure definition
AnnaBridge	156:ff21514d8981	235	*/
AnnaBridge	156:ff21514d8981	236	typedef struct
AnnaBridge	156:ff21514d8981	237	{
AnnaBridge	156:ff21514d8981	238	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
AnnaBridge	156:ff21514d8981	239	This parameter can be any value of @ref FMC_Wait_feature */
AnnaBridge	156:ff21514d8981	240
AnnaBridge	156:ff21514d8981	241	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	156:ff21514d8981	242	delay between CLE low and RE low.
AnnaBridge	156:ff21514d8981	243	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	244
AnnaBridge	156:ff21514d8981	245	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	156:ff21514d8981	246	delay between ALE low and RE low.
AnnaBridge	156:ff21514d8981	247	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	248	}FMC_PCCARD_InitTypeDef;
AnnaBridge	156:ff21514d8981	249
AnnaBridge	156:ff21514d8981	250	/**
AnnaBridge	156:ff21514d8981	251	* @brief FMC SDRAM Configuration Structure definition
AnnaBridge	156:ff21514d8981	252	*/
AnnaBridge	156:ff21514d8981	253	typedef struct
AnnaBridge	156:ff21514d8981	254	{
AnnaBridge	156:ff21514d8981	255	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
AnnaBridge	156:ff21514d8981	256	This parameter can be a value of @ref FMC_SDRAM_Bank */
AnnaBridge	156:ff21514d8981	257
AnnaBridge	156:ff21514d8981	258	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
AnnaBridge	156:ff21514d8981	259	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
AnnaBridge	156:ff21514d8981	260
AnnaBridge	156:ff21514d8981	261	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
AnnaBridge	156:ff21514d8981	262	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
AnnaBridge	156:ff21514d8981	263
AnnaBridge	156:ff21514d8981	264	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
AnnaBridge	156:ff21514d8981	265	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
AnnaBridge	156:ff21514d8981	266
AnnaBridge	156:ff21514d8981	267	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
AnnaBridge	156:ff21514d8981	268	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
AnnaBridge	156:ff21514d8981	269
AnnaBridge	156:ff21514d8981	270	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
AnnaBridge	156:ff21514d8981	271	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
AnnaBridge	156:ff21514d8981	272
AnnaBridge	156:ff21514d8981	273	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
AnnaBridge	156:ff21514d8981	274	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
AnnaBridge	156:ff21514d8981	275
AnnaBridge	156:ff21514d8981	276	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
AnnaBridge	156:ff21514d8981	277	to disable the clock before changing frequency.
AnnaBridge	156:ff21514d8981	278	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
AnnaBridge	156:ff21514d8981	279
AnnaBridge	156:ff21514d8981	280	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
AnnaBridge	156:ff21514d8981	281	commands during the CAS latency and stores data in the Read FIFO.
AnnaBridge	156:ff21514d8981	282	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
AnnaBridge	156:ff21514d8981	283
AnnaBridge	156:ff21514d8981	284	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
AnnaBridge	156:ff21514d8981	285	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
AnnaBridge	156:ff21514d8981	286	}FMC_SDRAM_InitTypeDef;
AnnaBridge	156:ff21514d8981	287
AnnaBridge	156:ff21514d8981	288	/**
AnnaBridge	156:ff21514d8981	289	* @brief FMC SDRAM Timing parameters structure definition
AnnaBridge	156:ff21514d8981	290	*/
AnnaBridge	156:ff21514d8981	291	typedef struct
AnnaBridge	156:ff21514d8981	292	{
AnnaBridge	156:ff21514d8981	293	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
AnnaBridge	156:ff21514d8981	294	an active or Refresh command in number of memory clock cycles.
AnnaBridge	156:ff21514d8981	295	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	156:ff21514d8981	296
AnnaBridge	156:ff21514d8981	297	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
AnnaBridge	156:ff21514d8981	298	issuing the Activate command in number of memory clock cycles.
AnnaBridge	156:ff21514d8981	299	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	156:ff21514d8981	300
AnnaBridge	156:ff21514d8981	301	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
AnnaBridge	156:ff21514d8981	302	cycles.
AnnaBridge	156:ff21514d8981	303	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	156:ff21514d8981	304
AnnaBridge	156:ff21514d8981	305	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
AnnaBridge	156:ff21514d8981	306	and the delay between two consecutive Refresh commands in number of
AnnaBridge	156:ff21514d8981	307	memory clock cycles.
AnnaBridge	156:ff21514d8981	308	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	156:ff21514d8981	309
AnnaBridge	156:ff21514d8981	310	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
AnnaBridge	156:ff21514d8981	311	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	156:ff21514d8981	312
AnnaBridge	156:ff21514d8981	313	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
AnnaBridge	156:ff21514d8981	314	in number of memory clock cycles.
AnnaBridge	156:ff21514d8981	315	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	156:ff21514d8981	316
AnnaBridge	156:ff21514d8981	317	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
AnnaBridge	156:ff21514d8981	318	command in number of memory clock cycles.
AnnaBridge	156:ff21514d8981	319	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	156:ff21514d8981	320	}FMC_SDRAM_TimingTypeDef;
AnnaBridge	156:ff21514d8981	321
AnnaBridge	156:ff21514d8981	322	/**
AnnaBridge	156:ff21514d8981	323	* @brief SDRAM command parameters structure definition
AnnaBridge	156:ff21514d8981	324	*/
AnnaBridge	156:ff21514d8981	325	typedef struct
AnnaBridge	156:ff21514d8981	326	{
AnnaBridge	156:ff21514d8981	327	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
AnnaBridge	156:ff21514d8981	328	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
AnnaBridge	156:ff21514d8981	329
AnnaBridge	156:ff21514d8981	330	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
AnnaBridge	156:ff21514d8981	331	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
AnnaBridge	156:ff21514d8981	332
AnnaBridge	156:ff21514d8981	333	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
AnnaBridge	156:ff21514d8981	334	in auto refresh mode.
AnnaBridge	156:ff21514d8981	335	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	156:ff21514d8981	336	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
AnnaBridge	156:ff21514d8981	337	}FMC_SDRAM_CommandTypeDef;
AnnaBridge	156:ff21514d8981	338	/**
AnnaBridge	156:ff21514d8981	339	* @}
AnnaBridge	156:ff21514d8981	340	*/
AnnaBridge	156:ff21514d8981	341
AnnaBridge	156:ff21514d8981	342	/* Private constants ---------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	343	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
AnnaBridge	156:ff21514d8981	344	* @{
AnnaBridge	156:ff21514d8981	345	*/
AnnaBridge	156:ff21514d8981	346
AnnaBridge	156:ff21514d8981	347	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
AnnaBridge	156:ff21514d8981	348	* @{
AnnaBridge	156:ff21514d8981	349	*/
AnnaBridge	156:ff21514d8981	350	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
AnnaBridge	156:ff21514d8981	351	* @{
AnnaBridge	156:ff21514d8981	352	*/
AnnaBridge	156:ff21514d8981	353	#define FMC_NORSRAM_BANK1 0x00000000U
AnnaBridge	156:ff21514d8981	354	#define FMC_NORSRAM_BANK2 0x00000002U
AnnaBridge	156:ff21514d8981	355	#define FMC_NORSRAM_BANK3 0x00000004U
AnnaBridge	156:ff21514d8981	356	#define FMC_NORSRAM_BANK4 0x00000006U
AnnaBridge	156:ff21514d8981	357	/**
AnnaBridge	156:ff21514d8981	358	* @}
AnnaBridge	156:ff21514d8981	359	*/
AnnaBridge	156:ff21514d8981	360
AnnaBridge	156:ff21514d8981	361	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
AnnaBridge	156:ff21514d8981	362	* @{
AnnaBridge	156:ff21514d8981	363	*/
AnnaBridge	156:ff21514d8981	364	#define FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	365	#define FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
AnnaBridge	156:ff21514d8981	366	/**
AnnaBridge	156:ff21514d8981	367	* @}
AnnaBridge	156:ff21514d8981	368	*/
AnnaBridge	156:ff21514d8981	369
AnnaBridge	156:ff21514d8981	370	/** @defgroup FMC_Memory_Type FMC Memory Type
AnnaBridge	156:ff21514d8981	371	* @{
AnnaBridge	156:ff21514d8981	372	*/
AnnaBridge	156:ff21514d8981	373	#define FMC_MEMORY_TYPE_SRAM 0x00000000U
AnnaBridge	156:ff21514d8981	374	#define FMC_MEMORY_TYPE_PSRAM 0x00000004U
AnnaBridge	156:ff21514d8981	375	#define FMC_MEMORY_TYPE_NOR 0x00000008U
AnnaBridge	156:ff21514d8981	376	/**
AnnaBridge	156:ff21514d8981	377	* @}
AnnaBridge	156:ff21514d8981	378	*/
AnnaBridge	156:ff21514d8981	379
AnnaBridge	156:ff21514d8981	380	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
AnnaBridge	156:ff21514d8981	381	* @{
AnnaBridge	156:ff21514d8981	382	*/
AnnaBridge	156:ff21514d8981	383	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	156:ff21514d8981	384	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
AnnaBridge	156:ff21514d8981	385	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
AnnaBridge	156:ff21514d8981	386	/**
AnnaBridge	156:ff21514d8981	387	* @}
AnnaBridge	156:ff21514d8981	388	*/
AnnaBridge	156:ff21514d8981	389
AnnaBridge	156:ff21514d8981	390	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
AnnaBridge	156:ff21514d8981	391	* @{
AnnaBridge	156:ff21514d8981	392	*/
AnnaBridge	156:ff21514d8981	393	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
AnnaBridge	156:ff21514d8981	394	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	395	/**
AnnaBridge	156:ff21514d8981	396	* @}
AnnaBridge	156:ff21514d8981	397	*/
AnnaBridge	156:ff21514d8981	398
AnnaBridge	156:ff21514d8981	399	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
AnnaBridge	156:ff21514d8981	400	* @{
AnnaBridge	156:ff21514d8981	401	*/
AnnaBridge	156:ff21514d8981	402	#define FMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	403	#define FMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
AnnaBridge	156:ff21514d8981	404	/**
AnnaBridge	156:ff21514d8981	405	* @}
AnnaBridge	156:ff21514d8981	406	*/
AnnaBridge	156:ff21514d8981	407
AnnaBridge	156:ff21514d8981	408	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
AnnaBridge	156:ff21514d8981	409	* @{
AnnaBridge	156:ff21514d8981	410	*/
AnnaBridge	156:ff21514d8981	411	#define FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
AnnaBridge	156:ff21514d8981	412	#define FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
AnnaBridge	156:ff21514d8981	413	/**
AnnaBridge	156:ff21514d8981	414	* @}
AnnaBridge	156:ff21514d8981	415	*/
AnnaBridge	156:ff21514d8981	416
AnnaBridge	156:ff21514d8981	417	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
AnnaBridge	156:ff21514d8981	418	* @{
AnnaBridge	156:ff21514d8981	419	*/
AnnaBridge	156:ff21514d8981	420	/** @note This mode is not available for the STM32F446/469/479xx devices
AnnaBridge	156:ff21514d8981	421	*/
AnnaBridge	156:ff21514d8981	422	#define FMC_WRAP_MODE_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	423	#define FMC_WRAP_MODE_ENABLE 0x00000400U
AnnaBridge	156:ff21514d8981	424	/**
AnnaBridge	156:ff21514d8981	425	* @}
AnnaBridge	156:ff21514d8981	426	*/
AnnaBridge	156:ff21514d8981	427
AnnaBridge	156:ff21514d8981	428	/** @defgroup FMC_Wait_Timing FMC Wait Timing
AnnaBridge	156:ff21514d8981	429	* @{
AnnaBridge	156:ff21514d8981	430	*/
AnnaBridge	156:ff21514d8981	431	#define FMC_WAIT_TIMING_BEFORE_WS 0x00000000U
AnnaBridge	156:ff21514d8981	432	#define FMC_WAIT_TIMING_DURING_WS 0x00000800U
AnnaBridge	156:ff21514d8981	433	/**
AnnaBridge	156:ff21514d8981	434	* @}
AnnaBridge	156:ff21514d8981	435	*/
AnnaBridge	156:ff21514d8981	436
AnnaBridge	156:ff21514d8981	437	/** @defgroup FMC_Write_Operation FMC Write Operation
AnnaBridge	156:ff21514d8981	438	* @{
AnnaBridge	156:ff21514d8981	439	*/
AnnaBridge	156:ff21514d8981	440	#define FMC_WRITE_OPERATION_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	441	#define FMC_WRITE_OPERATION_ENABLE 0x00001000U
AnnaBridge	156:ff21514d8981	442	/**
AnnaBridge	156:ff21514d8981	443	* @}
AnnaBridge	156:ff21514d8981	444	*/
AnnaBridge	156:ff21514d8981	445
AnnaBridge	156:ff21514d8981	446	/** @defgroup FMC_Wait_Signal FMC Wait Signal
AnnaBridge	156:ff21514d8981	447	* @{
AnnaBridge	156:ff21514d8981	448	*/
AnnaBridge	156:ff21514d8981	449	#define FMC_WAIT_SIGNAL_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	450	#define FMC_WAIT_SIGNAL_ENABLE 0x00002000U
AnnaBridge	156:ff21514d8981	451	/**
AnnaBridge	156:ff21514d8981	452	* @}
AnnaBridge	156:ff21514d8981	453	*/
AnnaBridge	156:ff21514d8981	454
AnnaBridge	156:ff21514d8981	455	/** @defgroup FMC_Extended_Mode FMC Extended Mode
AnnaBridge	156:ff21514d8981	456	* @{
AnnaBridge	156:ff21514d8981	457	*/
AnnaBridge	156:ff21514d8981	458	#define FMC_EXTENDED_MODE_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	459	#define FMC_EXTENDED_MODE_ENABLE 0x00004000U
AnnaBridge	156:ff21514d8981	460	/**
AnnaBridge	156:ff21514d8981	461	* @}
AnnaBridge	156:ff21514d8981	462	*/
AnnaBridge	156:ff21514d8981	463
AnnaBridge	156:ff21514d8981	464	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
AnnaBridge	156:ff21514d8981	465	* @{
AnnaBridge	156:ff21514d8981	466	*/
AnnaBridge	156:ff21514d8981	467	#define FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	468	#define FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
AnnaBridge	156:ff21514d8981	469	/**
AnnaBridge	156:ff21514d8981	470	* @}
AnnaBridge	156:ff21514d8981	471	*/
AnnaBridge	156:ff21514d8981	472
AnnaBridge	156:ff21514d8981	473	/** @defgroup FMC_Page_Size FMC Page Size
AnnaBridge	156:ff21514d8981	474	* @{
AnnaBridge	156:ff21514d8981	475	*/
AnnaBridge	156:ff21514d8981	476	#define FMC_PAGE_SIZE_NONE 0x00000000U
AnnaBridge	156:ff21514d8981	477	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
AnnaBridge	156:ff21514d8981	478	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
AnnaBridge	156:ff21514d8981	479	#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 \| FMC_BCR1_CPSIZE_1))
AnnaBridge	156:ff21514d8981	480	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
AnnaBridge	156:ff21514d8981	481	/**
AnnaBridge	156:ff21514d8981	482	* @}
AnnaBridge	156:ff21514d8981	483	*/
AnnaBridge	156:ff21514d8981	484
AnnaBridge	156:ff21514d8981	485	/** @defgroup FMC_Write_FIFO FMC Write FIFO
AnnaBridge	156:ff21514d8981	486	* @note These values are available only for the STM32F446/469/479xx devices.
AnnaBridge	156:ff21514d8981	487	* @{
AnnaBridge	156:ff21514d8981	488	*/
AnnaBridge	156:ff21514d8981	489	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
AnnaBridge	156:ff21514d8981	490	#define FMC_WRITE_FIFO_ENABLE 0x00000000U
AnnaBridge	156:ff21514d8981	491	/**
AnnaBridge	156:ff21514d8981	492	* @}
AnnaBridge	156:ff21514d8981	493	*/
AnnaBridge	156:ff21514d8981	494
AnnaBridge	156:ff21514d8981	495	/** @defgroup FMC_Write_Burst FMC Write Burst
AnnaBridge	156:ff21514d8981	496	* @{
AnnaBridge	156:ff21514d8981	497	*/
AnnaBridge	156:ff21514d8981	498	#define FMC_WRITE_BURST_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	499	#define FMC_WRITE_BURST_ENABLE 0x00080000U
AnnaBridge	156:ff21514d8981	500	/**
AnnaBridge	156:ff21514d8981	501	* @}
AnnaBridge	156:ff21514d8981	502	*/
AnnaBridge	156:ff21514d8981	503
AnnaBridge	156:ff21514d8981	504	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
AnnaBridge	156:ff21514d8981	505	* @{
AnnaBridge	156:ff21514d8981	506	*/
AnnaBridge	156:ff21514d8981	507	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
AnnaBridge	156:ff21514d8981	508	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
AnnaBridge	156:ff21514d8981	509	/**
AnnaBridge	156:ff21514d8981	510	* @}
AnnaBridge	156:ff21514d8981	511	*/
AnnaBridge	156:ff21514d8981	512
AnnaBridge	156:ff21514d8981	513	/** @defgroup FMC_Access_Mode FMC Access Mode
AnnaBridge	156:ff21514d8981	514	* @{
AnnaBridge	156:ff21514d8981	515	*/
AnnaBridge	156:ff21514d8981	516	#define FMC_ACCESS_MODE_A 0x00000000U
AnnaBridge	156:ff21514d8981	517	#define FMC_ACCESS_MODE_B 0x10000000U
AnnaBridge	156:ff21514d8981	518	#define FMC_ACCESS_MODE_C 0x20000000U
AnnaBridge	156:ff21514d8981	519	#define FMC_ACCESS_MODE_D 0x30000000U
AnnaBridge	156:ff21514d8981	520	/**
AnnaBridge	156:ff21514d8981	521	* @}
AnnaBridge	156:ff21514d8981	522	*/
AnnaBridge	156:ff21514d8981	523
AnnaBridge	156:ff21514d8981	524	/**
AnnaBridge	156:ff21514d8981	525	* @}
AnnaBridge	156:ff21514d8981	526	*/
AnnaBridge	156:ff21514d8981	527
AnnaBridge	156:ff21514d8981	528	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
AnnaBridge	156:ff21514d8981	529	* @{
AnnaBridge	156:ff21514d8981	530	*/
AnnaBridge	156:ff21514d8981	531	/** @defgroup FMC_NAND_Bank FMC NAND Bank
AnnaBridge	156:ff21514d8981	532	* @{
AnnaBridge	156:ff21514d8981	533	*/
AnnaBridge	156:ff21514d8981	534	#define FMC_NAND_BANK2 0x00000010U
AnnaBridge	156:ff21514d8981	535	#define FMC_NAND_BANK3 0x00000100U
AnnaBridge	156:ff21514d8981	536	/**
AnnaBridge	156:ff21514d8981	537	* @}
AnnaBridge	156:ff21514d8981	538	*/
AnnaBridge	156:ff21514d8981	539
AnnaBridge	156:ff21514d8981	540	/** @defgroup FMC_Wait_feature FMC Wait feature
AnnaBridge	156:ff21514d8981	541	* @{
AnnaBridge	156:ff21514d8981	542	*/
AnnaBridge	156:ff21514d8981	543	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	544	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
AnnaBridge	156:ff21514d8981	545	/**
AnnaBridge	156:ff21514d8981	546	* @}
AnnaBridge	156:ff21514d8981	547	*/
AnnaBridge	156:ff21514d8981	548
AnnaBridge	156:ff21514d8981	549	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
AnnaBridge	156:ff21514d8981	550	* @{
AnnaBridge	156:ff21514d8981	551	*/
AnnaBridge	156:ff21514d8981	552	#define FMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
AnnaBridge	156:ff21514d8981	553	#define FMC_PCR_MEMORY_TYPE_NAND 0x00000008U
AnnaBridge	156:ff21514d8981	554	/**
AnnaBridge	156:ff21514d8981	555	* @}
AnnaBridge	156:ff21514d8981	556	*/
AnnaBridge	156:ff21514d8981	557
AnnaBridge	156:ff21514d8981	558	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
AnnaBridge	156:ff21514d8981	559	* @{
AnnaBridge	156:ff21514d8981	560	*/
AnnaBridge	156:ff21514d8981	561	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	156:ff21514d8981	562	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
AnnaBridge	156:ff21514d8981	563	/**
AnnaBridge	156:ff21514d8981	564	* @}
AnnaBridge	156:ff21514d8981	565	*/
AnnaBridge	156:ff21514d8981	566
AnnaBridge	156:ff21514d8981	567	/** @defgroup FMC_ECC FMC ECC
AnnaBridge	156:ff21514d8981	568	* @{
AnnaBridge	156:ff21514d8981	569	*/
AnnaBridge	156:ff21514d8981	570	#define FMC_NAND_ECC_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	571	#define FMC_NAND_ECC_ENABLE 0x00000040U
AnnaBridge	156:ff21514d8981	572	/**
AnnaBridge	156:ff21514d8981	573	* @}
AnnaBridge	156:ff21514d8981	574	*/
AnnaBridge	156:ff21514d8981	575
AnnaBridge	156:ff21514d8981	576	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
AnnaBridge	156:ff21514d8981	577	* @{
AnnaBridge	156:ff21514d8981	578	*/
AnnaBridge	156:ff21514d8981	579	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
AnnaBridge	156:ff21514d8981	580	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
AnnaBridge	156:ff21514d8981	581	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
AnnaBridge	156:ff21514d8981	582	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
AnnaBridge	156:ff21514d8981	583	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
AnnaBridge	156:ff21514d8981	584	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
AnnaBridge	156:ff21514d8981	585	/**
AnnaBridge	156:ff21514d8981	586	* @}
AnnaBridge	156:ff21514d8981	587	*/
AnnaBridge	156:ff21514d8981	588
AnnaBridge	156:ff21514d8981	589	/**
AnnaBridge	156:ff21514d8981	590	* @}
AnnaBridge	156:ff21514d8981	591	*/
AnnaBridge	156:ff21514d8981	592
AnnaBridge	156:ff21514d8981	593	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
AnnaBridge	156:ff21514d8981	594	* @{
AnnaBridge	156:ff21514d8981	595	*/
AnnaBridge	156:ff21514d8981	596	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
AnnaBridge	156:ff21514d8981	597	* @{
AnnaBridge	156:ff21514d8981	598	*/
AnnaBridge	156:ff21514d8981	599	#define FMC_SDRAM_BANK1 0x00000000U
AnnaBridge	156:ff21514d8981	600	#define FMC_SDRAM_BANK2 0x00000001U
AnnaBridge	156:ff21514d8981	601	/**
AnnaBridge	156:ff21514d8981	602	* @}
AnnaBridge	156:ff21514d8981	603	*/
AnnaBridge	156:ff21514d8981	604
AnnaBridge	156:ff21514d8981	605	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
AnnaBridge	156:ff21514d8981	606	* @{
AnnaBridge	156:ff21514d8981	607	*/
AnnaBridge	156:ff21514d8981	608	#define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000U
AnnaBridge	156:ff21514d8981	609	#define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001U
AnnaBridge	156:ff21514d8981	610	#define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002U
AnnaBridge	156:ff21514d8981	611	#define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003U
AnnaBridge	156:ff21514d8981	612	/**
AnnaBridge	156:ff21514d8981	613	* @}
AnnaBridge	156:ff21514d8981	614	*/
AnnaBridge	156:ff21514d8981	615
AnnaBridge	156:ff21514d8981	616	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
AnnaBridge	156:ff21514d8981	617	* @{
AnnaBridge	156:ff21514d8981	618	*/
AnnaBridge	156:ff21514d8981	619	#define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000U
AnnaBridge	156:ff21514d8981	620	#define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004U
AnnaBridge	156:ff21514d8981	621	#define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008U
AnnaBridge	156:ff21514d8981	622	/**
AnnaBridge	156:ff21514d8981	623	* @}
AnnaBridge	156:ff21514d8981	624	*/
AnnaBridge	156:ff21514d8981	625
AnnaBridge	156:ff21514d8981	626	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
AnnaBridge	156:ff21514d8981	627	* @{
AnnaBridge	156:ff21514d8981	628	*/
AnnaBridge	156:ff21514d8981	629	#define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	156:ff21514d8981	630	#define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010U
AnnaBridge	156:ff21514d8981	631	#define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020U
AnnaBridge	156:ff21514d8981	632	/**
AnnaBridge	156:ff21514d8981	633	* @}
AnnaBridge	156:ff21514d8981	634	*/
AnnaBridge	156:ff21514d8981	635
AnnaBridge	156:ff21514d8981	636	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
AnnaBridge	156:ff21514d8981	637	* @{
AnnaBridge	156:ff21514d8981	638	*/
AnnaBridge	156:ff21514d8981	639	#define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000U
AnnaBridge	156:ff21514d8981	640	#define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040U
AnnaBridge	156:ff21514d8981	641	/**
AnnaBridge	156:ff21514d8981	642	* @}
AnnaBridge	156:ff21514d8981	643	*/
AnnaBridge	156:ff21514d8981	644
AnnaBridge	156:ff21514d8981	645	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
AnnaBridge	156:ff21514d8981	646	* @{
AnnaBridge	156:ff21514d8981	647	*/
AnnaBridge	156:ff21514d8981	648	#define FMC_SDRAM_CAS_LATENCY_1 0x00000080U
AnnaBridge	156:ff21514d8981	649	#define FMC_SDRAM_CAS_LATENCY_2 0x00000100U
AnnaBridge	156:ff21514d8981	650	#define FMC_SDRAM_CAS_LATENCY_3 0x00000180U
AnnaBridge	156:ff21514d8981	651	/**
AnnaBridge	156:ff21514d8981	652	* @}
AnnaBridge	156:ff21514d8981	653	*/
AnnaBridge	156:ff21514d8981	654
AnnaBridge	156:ff21514d8981	655	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
AnnaBridge	156:ff21514d8981	656	* @{
AnnaBridge	156:ff21514d8981	657	*/
AnnaBridge	156:ff21514d8981	658	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	659	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200U
AnnaBridge	156:ff21514d8981	660
AnnaBridge	156:ff21514d8981	661	/**
AnnaBridge	156:ff21514d8981	662	* @}
AnnaBridge	156:ff21514d8981	663	*/
AnnaBridge	156:ff21514d8981	664
AnnaBridge	156:ff21514d8981	665	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
AnnaBridge	156:ff21514d8981	666	* @{
AnnaBridge	156:ff21514d8981	667	*/
AnnaBridge	156:ff21514d8981	668	#define FMC_SDRAM_CLOCK_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	669	#define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800U
AnnaBridge	156:ff21514d8981	670	#define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00U
AnnaBridge	156:ff21514d8981	671	/**
AnnaBridge	156:ff21514d8981	672	* @}
AnnaBridge	156:ff21514d8981	673	*/
AnnaBridge	156:ff21514d8981	674
AnnaBridge	156:ff21514d8981	675	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
AnnaBridge	156:ff21514d8981	676	* @{
AnnaBridge	156:ff21514d8981	677	*/
AnnaBridge	156:ff21514d8981	678	#define FMC_SDRAM_RBURST_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	679	#define FMC_SDRAM_RBURST_ENABLE 0x00001000U
AnnaBridge	156:ff21514d8981	680	/**
AnnaBridge	156:ff21514d8981	681	* @}
AnnaBridge	156:ff21514d8981	682	*/
AnnaBridge	156:ff21514d8981	683
AnnaBridge	156:ff21514d8981	684	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
AnnaBridge	156:ff21514d8981	685	* @{
AnnaBridge	156:ff21514d8981	686	*/
AnnaBridge	156:ff21514d8981	687	#define FMC_SDRAM_RPIPE_DELAY_0 0x00000000U
AnnaBridge	156:ff21514d8981	688	#define FMC_SDRAM_RPIPE_DELAY_1 0x00002000U
AnnaBridge	156:ff21514d8981	689	#define FMC_SDRAM_RPIPE_DELAY_2 0x00004000U
AnnaBridge	156:ff21514d8981	690	/**
AnnaBridge	156:ff21514d8981	691	* @}
AnnaBridge	156:ff21514d8981	692	*/
AnnaBridge	156:ff21514d8981	693
AnnaBridge	156:ff21514d8981	694	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
AnnaBridge	156:ff21514d8981	695	* @{
AnnaBridge	156:ff21514d8981	696	*/
AnnaBridge	156:ff21514d8981	697	#define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000U
AnnaBridge	156:ff21514d8981	698	#define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001U
AnnaBridge	156:ff21514d8981	699	#define FMC_SDRAM_CMD_PALL 0x00000002U
AnnaBridge	156:ff21514d8981	700	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003U
AnnaBridge	156:ff21514d8981	701	#define FMC_SDRAM_CMD_LOAD_MODE 0x00000004U
AnnaBridge	156:ff21514d8981	702	#define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005U
AnnaBridge	156:ff21514d8981	703	#define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006U
AnnaBridge	156:ff21514d8981	704	/**
AnnaBridge	156:ff21514d8981	705	* @}
AnnaBridge	156:ff21514d8981	706	*/
AnnaBridge	156:ff21514d8981	707
AnnaBridge	156:ff21514d8981	708	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
AnnaBridge	156:ff21514d8981	709	* @{
AnnaBridge	156:ff21514d8981	710	*/
AnnaBridge	156:ff21514d8981	711	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
AnnaBridge	156:ff21514d8981	712	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
AnnaBridge	156:ff21514d8981	713	#define FMC_SDRAM_CMD_TARGET_BANK1_2 0x00000018U
AnnaBridge	156:ff21514d8981	714	/**
AnnaBridge	156:ff21514d8981	715	* @}
AnnaBridge	156:ff21514d8981	716	*/
AnnaBridge	156:ff21514d8981	717
AnnaBridge	156:ff21514d8981	718	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
AnnaBridge	156:ff21514d8981	719	* @{
AnnaBridge	156:ff21514d8981	720	*/
AnnaBridge	156:ff21514d8981	721	#define FMC_SDRAM_NORMAL_MODE 0x00000000U
AnnaBridge	156:ff21514d8981	722	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
AnnaBridge	156:ff21514d8981	723	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
AnnaBridge	156:ff21514d8981	724	/**
AnnaBridge	156:ff21514d8981	725	* @}
AnnaBridge	156:ff21514d8981	726	*/
AnnaBridge	156:ff21514d8981	727
AnnaBridge	156:ff21514d8981	728	/**
AnnaBridge	156:ff21514d8981	729	* @}
AnnaBridge	156:ff21514d8981	730	*/
AnnaBridge	156:ff21514d8981	731
AnnaBridge	156:ff21514d8981	732	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
AnnaBridge	156:ff21514d8981	733	* @{
AnnaBridge	156:ff21514d8981	734	*/
AnnaBridge	156:ff21514d8981	735	#define FMC_IT_RISING_EDGE 0x00000008U
AnnaBridge	156:ff21514d8981	736	#define FMC_IT_LEVEL 0x00000010U
AnnaBridge	156:ff21514d8981	737	#define FMC_IT_FALLING_EDGE 0x00000020U
AnnaBridge	156:ff21514d8981	738	#define FMC_IT_REFRESH_ERROR 0x00004000U
AnnaBridge	156:ff21514d8981	739	/**
AnnaBridge	156:ff21514d8981	740	* @}
AnnaBridge	156:ff21514d8981	741	*/
AnnaBridge	156:ff21514d8981	742
AnnaBridge	156:ff21514d8981	743	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
AnnaBridge	156:ff21514d8981	744	* @{
AnnaBridge	156:ff21514d8981	745	*/
AnnaBridge	156:ff21514d8981	746	#define FMC_FLAG_RISING_EDGE 0x00000001U
AnnaBridge	156:ff21514d8981	747	#define FMC_FLAG_LEVEL 0x00000002U
AnnaBridge	156:ff21514d8981	748	#define FMC_FLAG_FALLING_EDGE 0x00000004U
AnnaBridge	156:ff21514d8981	749	#define FMC_FLAG_FEMPT 0x00000040U
AnnaBridge	156:ff21514d8981	750	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
AnnaBridge	156:ff21514d8981	751	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
AnnaBridge	156:ff21514d8981	752	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
AnnaBridge	156:ff21514d8981	753	/**
AnnaBridge	156:ff21514d8981	754	* @}
AnnaBridge	156:ff21514d8981	755	*/
AnnaBridge	156:ff21514d8981	756
AnnaBridge	156:ff21514d8981	757	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
AnnaBridge	156:ff21514d8981	758	* @{
AnnaBridge	156:ff21514d8981	759	*/
AnnaBridge	156:ff21514d8981	760	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	761	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
AnnaBridge	156:ff21514d8981	762	#else
AnnaBridge	156:ff21514d8981	763	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
AnnaBridge	156:ff21514d8981	764	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
AnnaBridge	156:ff21514d8981	765	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	766	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
AnnaBridge	156:ff21514d8981	767	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
AnnaBridge	156:ff21514d8981	768	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
AnnaBridge	156:ff21514d8981	769
AnnaBridge	156:ff21514d8981	770
AnnaBridge	156:ff21514d8981	771	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	772	#define FMC_NAND_DEVICE FMC_Bank3
AnnaBridge	156:ff21514d8981	773	#else
AnnaBridge	156:ff21514d8981	774	#define FMC_NAND_DEVICE FMC_Bank2_3
AnnaBridge	156:ff21514d8981	775	#define FMC_PCCARD_DEVICE FMC_Bank4
AnnaBridge	156:ff21514d8981	776	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	777	#define FMC_NORSRAM_DEVICE FMC_Bank1
AnnaBridge	156:ff21514d8981	778	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
AnnaBridge	156:ff21514d8981	779	#define FMC_SDRAM_DEVICE FMC_Bank5_6
AnnaBridge	156:ff21514d8981	780	/**
AnnaBridge	156:ff21514d8981	781	* @}
AnnaBridge	156:ff21514d8981	782	*/
AnnaBridge	156:ff21514d8981	783
AnnaBridge	156:ff21514d8981	784	/**
AnnaBridge	156:ff21514d8981	785	* @}
AnnaBridge	156:ff21514d8981	786	*/
AnnaBridge	156:ff21514d8981	787
AnnaBridge	156:ff21514d8981	788	/* Private macro -------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	789	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
AnnaBridge	156:ff21514d8981	790	* @{
AnnaBridge	156:ff21514d8981	791	*/
AnnaBridge	156:ff21514d8981	792
AnnaBridge	156:ff21514d8981	793	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
AnnaBridge	156:ff21514d8981	794	* @brief macros to handle NOR device enable/disable and read/write operations
AnnaBridge	156:ff21514d8981	795	* @{
AnnaBridge	156:ff21514d8981	796	*/
AnnaBridge	156:ff21514d8981	797	/**
AnnaBridge	156:ff21514d8981	798	* @brief Enable the NORSRAM device access.
AnnaBridge	163:e59c8e839560	799	* @param __INSTANCE__ FMC_NORSRAM Instance
AnnaBridge	163:e59c8e839560	800	* @param __BANK__ FMC_NORSRAM Bank
AnnaBridge	156:ff21514d8981	801	* @retval None
AnnaBridge	156:ff21514d8981	802	*/
AnnaBridge	156:ff21514d8981	803	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
AnnaBridge	156:ff21514d8981	804
AnnaBridge	156:ff21514d8981	805	/**
AnnaBridge	156:ff21514d8981	806	* @brief Disable the NORSRAM device access.
AnnaBridge	163:e59c8e839560	807	* @param __INSTANCE__ FMC_NORSRAM Instance
AnnaBridge	163:e59c8e839560	808	* @param __BANK__ FMC_NORSRAM Bank
AnnaBridge	156:ff21514d8981	809	* @retval None
AnnaBridge	156:ff21514d8981	810	*/
AnnaBridge	156:ff21514d8981	811	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
AnnaBridge	156:ff21514d8981	812	/**
AnnaBridge	156:ff21514d8981	813	* @}
AnnaBridge	156:ff21514d8981	814	*/
AnnaBridge	156:ff21514d8981	815
AnnaBridge	156:ff21514d8981	816	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
AnnaBridge	156:ff21514d8981	817	* @brief macros to handle NAND device enable/disable
AnnaBridge	156:ff21514d8981	818	* @{
AnnaBridge	156:ff21514d8981	819	*/
AnnaBridge	156:ff21514d8981	820	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	821	/**
AnnaBridge	156:ff21514d8981	822	* @brief Enable the NAND device access.
AnnaBridge	163:e59c8e839560	823	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	824	* @param __BANK__ FMC_NAND Bank
AnnaBridge	156:ff21514d8981	825	* @retval None
AnnaBridge	156:ff21514d8981	826	*/
AnnaBridge	156:ff21514d8981	827	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
AnnaBridge	156:ff21514d8981	828
AnnaBridge	156:ff21514d8981	829	/**
AnnaBridge	156:ff21514d8981	830	* @brief Disable the NAND device access.
AnnaBridge	163:e59c8e839560	831	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	832	* @param __BANK__ FMC_NAND Bank
AnnaBridge	156:ff21514d8981	833	* @retval None
AnnaBridge	156:ff21514d8981	834	*/
AnnaBridge	156:ff21514d8981	835	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
AnnaBridge	156:ff21514d8981	836	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
AnnaBridge	156:ff21514d8981	837	/**
AnnaBridge	156:ff21514d8981	838	* @brief Enable the NAND device access.
AnnaBridge	163:e59c8e839560	839	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	840	* @param __BANK__ FMC_NAND Bank
AnnaBridge	156:ff21514d8981	841	* @retval None
AnnaBridge	156:ff21514d8981	842	*/
AnnaBridge	156:ff21514d8981	843	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
AnnaBridge	156:ff21514d8981	844	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
AnnaBridge	156:ff21514d8981	845
AnnaBridge	156:ff21514d8981	846	/**
AnnaBridge	156:ff21514d8981	847	* @brief Disable the NAND device access.
AnnaBridge	163:e59c8e839560	848	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	849	* @param __BANK__ FMC_NAND Bank
AnnaBridge	156:ff21514d8981	850	* @retval None
AnnaBridge	156:ff21514d8981	851	*/
AnnaBridge	156:ff21514d8981	852	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
AnnaBridge	156:ff21514d8981	853	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
AnnaBridge	156:ff21514d8981	854
AnnaBridge	156:ff21514d8981	855	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
AnnaBridge	156:ff21514d8981	856	/**
AnnaBridge	156:ff21514d8981	857	* @}
AnnaBridge	156:ff21514d8981	858	*/
AnnaBridge	156:ff21514d8981	859	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
AnnaBridge	156:ff21514d8981	860	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
AnnaBridge	156:ff21514d8981	861	* @brief macros to handle SRAM read/write operations
AnnaBridge	156:ff21514d8981	862	* @{
AnnaBridge	156:ff21514d8981	863	*/
AnnaBridge	156:ff21514d8981	864	/**
AnnaBridge	156:ff21514d8981	865	* @brief Enable the PCCARD device access.
AnnaBridge	163:e59c8e839560	866	* @param __INSTANCE__ FMC_PCCARD Instance
AnnaBridge	156:ff21514d8981	867	* @retval None
AnnaBridge	156:ff21514d8981	868	*/
AnnaBridge	156:ff21514d8981	869	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
AnnaBridge	156:ff21514d8981	870
AnnaBridge	156:ff21514d8981	871	/**
AnnaBridge	156:ff21514d8981	872	* @brief Disable the PCCARD device access.
AnnaBridge	163:e59c8e839560	873	* @param __INSTANCE__ FMC_PCCARD Instance
AnnaBridge	156:ff21514d8981	874	* @retval None
AnnaBridge	156:ff21514d8981	875	*/
AnnaBridge	156:ff21514d8981	876	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
AnnaBridge	156:ff21514d8981	877	/**
AnnaBridge	156:ff21514d8981	878	* @}
AnnaBridge	156:ff21514d8981	879	*/
AnnaBridge	156:ff21514d8981	880	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
AnnaBridge	156:ff21514d8981	881
AnnaBridge	156:ff21514d8981	882	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
AnnaBridge	156:ff21514d8981	883	* @brief macros to handle FMC flags and interrupts
AnnaBridge	156:ff21514d8981	884	* @{
AnnaBridge	156:ff21514d8981	885	*/
AnnaBridge	156:ff21514d8981	886	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	887	/**
AnnaBridge	156:ff21514d8981	888	* @brief Enable the NAND device interrupt.
AnnaBridge	163:e59c8e839560	889	* @param __INSTANCE__ FMC_NAND instance
AnnaBridge	163:e59c8e839560	890	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	891	* @param __INTERRUPT__ FMC_NAND interrupt
AnnaBridge	156:ff21514d8981	892	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	893	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	156:ff21514d8981	894	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	156:ff21514d8981	895	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	156:ff21514d8981	896	* @retval None
AnnaBridge	156:ff21514d8981	897	*/
AnnaBridge	156:ff21514d8981	898	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
AnnaBridge	156:ff21514d8981	899
AnnaBridge	156:ff21514d8981	900	/**
AnnaBridge	156:ff21514d8981	901	* @brief Disable the NAND device interrupt.
AnnaBridge	163:e59c8e839560	902	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	903	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	904	* @param __INTERRUPT__ FMC_NAND interrupt
AnnaBridge	156:ff21514d8981	905	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	906	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	156:ff21514d8981	907	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	156:ff21514d8981	908	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	156:ff21514d8981	909	* @retval None
AnnaBridge	156:ff21514d8981	910	*/
AnnaBridge	156:ff21514d8981	911	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
AnnaBridge	156:ff21514d8981	912
AnnaBridge	156:ff21514d8981	913	/**
AnnaBridge	156:ff21514d8981	914	* @brief Get flag status of the NAND device.
AnnaBridge	163:e59c8e839560	915	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	916	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	917	* @param __FLAG__ FMC_NAND flag
AnnaBridge	156:ff21514d8981	918	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	919	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	156:ff21514d8981	920	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	156:ff21514d8981	921	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	156:ff21514d8981	922	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	156:ff21514d8981	923	* @retval The state of FLAG (SET or RESET).
AnnaBridge	156:ff21514d8981	924	*/
AnnaBridge	156:ff21514d8981	925	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge	156:ff21514d8981	926	/**
AnnaBridge	156:ff21514d8981	927	* @brief Clear flag status of the NAND device.
AnnaBridge	163:e59c8e839560	928	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	929	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	930	* @param __FLAG__ FMC_NAND flag
AnnaBridge	156:ff21514d8981	931	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	932	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	156:ff21514d8981	933	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	156:ff21514d8981	934	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	156:ff21514d8981	935	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	156:ff21514d8981	936	* @retval None
AnnaBridge	156:ff21514d8981	937	*/
AnnaBridge	156:ff21514d8981	938	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
AnnaBridge	156:ff21514d8981	939	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
AnnaBridge	156:ff21514d8981	940	/**
AnnaBridge	156:ff21514d8981	941	* @brief Enable the NAND device interrupt.
AnnaBridge	163:e59c8e839560	942	* @param __INSTANCE__ FMC_NAND instance
AnnaBridge	163:e59c8e839560	943	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	944	* @param __INTERRUPT__ FMC_NAND interrupt
AnnaBridge	156:ff21514d8981	945	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	946	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	156:ff21514d8981	947	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	156:ff21514d8981	948	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	156:ff21514d8981	949	* @retval None
AnnaBridge	156:ff21514d8981	950	*/
AnnaBridge	156:ff21514d8981	951	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
AnnaBridge	156:ff21514d8981	952	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
AnnaBridge	156:ff21514d8981	953
AnnaBridge	156:ff21514d8981	954	/**
AnnaBridge	156:ff21514d8981	955	* @brief Disable the NAND device interrupt.
AnnaBridge	163:e59c8e839560	956	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	957	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	958	* @param __INTERRUPT__ FMC_NAND interrupt
AnnaBridge	156:ff21514d8981	959	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	960	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	156:ff21514d8981	961	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	156:ff21514d8981	962	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	156:ff21514d8981	963	* @retval None
AnnaBridge	156:ff21514d8981	964	*/
AnnaBridge	156:ff21514d8981	965	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
AnnaBridge	156:ff21514d8981	966	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
AnnaBridge	156:ff21514d8981	967
AnnaBridge	156:ff21514d8981	968	/**
AnnaBridge	156:ff21514d8981	969	* @brief Get flag status of the NAND device.
AnnaBridge	163:e59c8e839560	970	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	971	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	972	* @param __FLAG__ FMC_NAND flag
AnnaBridge	156:ff21514d8981	973	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	974	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	156:ff21514d8981	975	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	156:ff21514d8981	976	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	156:ff21514d8981	977	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	156:ff21514d8981	978	* @retval The state of FLAG (SET or RESET).
AnnaBridge	156:ff21514d8981	979	*/
AnnaBridge	156:ff21514d8981	980	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
AnnaBridge	156:ff21514d8981	981	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
AnnaBridge	156:ff21514d8981	982	/**
AnnaBridge	156:ff21514d8981	983	* @brief Clear flag status of the NAND device.
AnnaBridge	163:e59c8e839560	984	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	163:e59c8e839560	985	* @param __BANK__ FMC_NAND Bank
AnnaBridge	163:e59c8e839560	986	* @param __FLAG__ FMC_NAND flag
AnnaBridge	156:ff21514d8981	987	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	988	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	156:ff21514d8981	989	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	156:ff21514d8981	990	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	156:ff21514d8981	991	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	156:ff21514d8981	992	* @retval None
AnnaBridge	156:ff21514d8981	993	*/
AnnaBridge	156:ff21514d8981	994	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
AnnaBridge	156:ff21514d8981	995	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
AnnaBridge	156:ff21514d8981	996	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
AnnaBridge	156:ff21514d8981	997
AnnaBridge	156:ff21514d8981	998	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
AnnaBridge	156:ff21514d8981	999	/**
AnnaBridge	156:ff21514d8981	1000	* @brief Enable the PCCARD device interrupt.
AnnaBridge	163:e59c8e839560	1001	* @param __INSTANCE__ FMC_PCCARD instance
AnnaBridge	163:e59c8e839560	1002	* @param __INTERRUPT__ FMC_PCCARD interrupt
AnnaBridge	156:ff21514d8981	1003	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	1004	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	156:ff21514d8981	1005	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	156:ff21514d8981	1006	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	156:ff21514d8981	1007	* @retval None
AnnaBridge	156:ff21514d8981	1008	*/
AnnaBridge	156:ff21514d8981	1009	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
AnnaBridge	156:ff21514d8981	1010
AnnaBridge	156:ff21514d8981	1011	/**
AnnaBridge	156:ff21514d8981	1012	* @brief Disable the PCCARD device interrupt.
AnnaBridge	163:e59c8e839560	1013	* @param __INSTANCE__ FMC_PCCARD instance
AnnaBridge	163:e59c8e839560	1014	* @param __INTERRUPT__ FMC_PCCARD interrupt
AnnaBridge	156:ff21514d8981	1015	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	1016	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	156:ff21514d8981	1017	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	156:ff21514d8981	1018	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	156:ff21514d8981	1019	* @retval None
AnnaBridge	156:ff21514d8981	1020	*/
AnnaBridge	156:ff21514d8981	1021	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
AnnaBridge	156:ff21514d8981	1022
AnnaBridge	156:ff21514d8981	1023	/**
AnnaBridge	156:ff21514d8981	1024	* @brief Get flag status of the PCCARD device.
AnnaBridge	163:e59c8e839560	1025	* @param __INSTANCE__ FMC_PCCARD instance
AnnaBridge	163:e59c8e839560	1026	* @param __FLAG__ FMC_PCCARD flag
AnnaBridge	156:ff21514d8981	1027	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	1028	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	156:ff21514d8981	1029	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	156:ff21514d8981	1030	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	156:ff21514d8981	1031	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	156:ff21514d8981	1032	* @retval The state of FLAG (SET or RESET).
AnnaBridge	156:ff21514d8981	1033	*/
AnnaBridge	156:ff21514d8981	1034	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
AnnaBridge	156:ff21514d8981	1035
AnnaBridge	156:ff21514d8981	1036	/**
AnnaBridge	156:ff21514d8981	1037	* @brief Clear flag status of the PCCARD device.
AnnaBridge	163:e59c8e839560	1038	* @param __INSTANCE__ FMC_PCCARD instance
AnnaBridge	163:e59c8e839560	1039	* @param __FLAG__ FMC_PCCARD flag
AnnaBridge	156:ff21514d8981	1040	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	1041	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	156:ff21514d8981	1042	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	156:ff21514d8981	1043	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	156:ff21514d8981	1044	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	156:ff21514d8981	1045	* @retval None
AnnaBridge	156:ff21514d8981	1046	*/
AnnaBridge	156:ff21514d8981	1047	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
AnnaBridge	156:ff21514d8981	1048	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
AnnaBridge	156:ff21514d8981	1049
AnnaBridge	156:ff21514d8981	1050	/**
AnnaBridge	156:ff21514d8981	1051	* @brief Enable the SDRAM device interrupt.
AnnaBridge	163:e59c8e839560	1052	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	163:e59c8e839560	1053	* @param __INTERRUPT__ FMC_SDRAM interrupt
AnnaBridge	156:ff21514d8981	1054	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	1055	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
AnnaBridge	156:ff21514d8981	1056	* @retval None
AnnaBridge	156:ff21514d8981	1057	*/
AnnaBridge	156:ff21514d8981	1058	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
AnnaBridge	156:ff21514d8981	1059
AnnaBridge	156:ff21514d8981	1060	/**
AnnaBridge	156:ff21514d8981	1061	* @brief Disable the SDRAM device interrupt.
AnnaBridge	163:e59c8e839560	1062	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	163:e59c8e839560	1063	* @param __INTERRUPT__ FMC_SDRAM interrupt
AnnaBridge	156:ff21514d8981	1064	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	1065	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
AnnaBridge	156:ff21514d8981	1066	* @retval None
AnnaBridge	156:ff21514d8981	1067	*/
AnnaBridge	156:ff21514d8981	1068	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
AnnaBridge	156:ff21514d8981	1069
AnnaBridge	156:ff21514d8981	1070	/**
AnnaBridge	156:ff21514d8981	1071	* @brief Get flag status of the SDRAM device.
AnnaBridge	163:e59c8e839560	1072	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	163:e59c8e839560	1073	* @param __FLAG__ FMC_SDRAM flag
AnnaBridge	156:ff21514d8981	1074	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	1075	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
AnnaBridge	156:ff21514d8981	1076	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
AnnaBridge	156:ff21514d8981	1077	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
AnnaBridge	156:ff21514d8981	1078	* @retval The state of FLAG (SET or RESET).
AnnaBridge	156:ff21514d8981	1079	*/
AnnaBridge	156:ff21514d8981	1080	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
AnnaBridge	156:ff21514d8981	1081
AnnaBridge	156:ff21514d8981	1082	/**
AnnaBridge	156:ff21514d8981	1083	* @brief Clear flag status of the SDRAM device.
AnnaBridge	163:e59c8e839560	1084	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	163:e59c8e839560	1085	* @param __FLAG__ FMC_SDRAM flag
AnnaBridge	156:ff21514d8981	1086	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	1087	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
AnnaBridge	156:ff21514d8981	1088	* @retval None
AnnaBridge	156:ff21514d8981	1089	*/
AnnaBridge	156:ff21514d8981	1090	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
AnnaBridge	156:ff21514d8981	1091	/**
AnnaBridge	156:ff21514d8981	1092	* @}
AnnaBridge	156:ff21514d8981	1093	*/
AnnaBridge	156:ff21514d8981	1094
AnnaBridge	156:ff21514d8981	1095	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
AnnaBridge	156:ff21514d8981	1096	* @{
AnnaBridge	156:ff21514d8981	1097	*/
AnnaBridge	156:ff21514d8981	1098	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
AnnaBridge	156:ff21514d8981	1099	((BANK) == FMC_NORSRAM_BANK2) \|\| \
AnnaBridge	156:ff21514d8981	1100	((BANK) == FMC_NORSRAM_BANK3) \|\| \
AnnaBridge	156:ff21514d8981	1101	((BANK) == FMC_NORSRAM_BANK4))
AnnaBridge	156:ff21514d8981	1102
AnnaBridge	156:ff21514d8981	1103	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1104	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
AnnaBridge	156:ff21514d8981	1105
AnnaBridge	156:ff21514d8981	1106	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
AnnaBridge	156:ff21514d8981	1107	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
AnnaBridge	156:ff21514d8981	1108	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
AnnaBridge	156:ff21514d8981	1109
AnnaBridge	156:ff21514d8981	1110	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	156:ff21514d8981	1111	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
AnnaBridge	156:ff21514d8981	1112	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
AnnaBridge	156:ff21514d8981	1113
AnnaBridge	156:ff21514d8981	1114	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
AnnaBridge	156:ff21514d8981	1115	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
AnnaBridge	156:ff21514d8981	1116	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
AnnaBridge	156:ff21514d8981	1117	((__MODE__) == FMC_ACCESS_MODE_D))
AnnaBridge	156:ff21514d8981	1118
AnnaBridge	156:ff21514d8981	1119	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
AnnaBridge	156:ff21514d8981	1120	((BANK) == FMC_NAND_BANK3))
AnnaBridge	156:ff21514d8981	1121
AnnaBridge	156:ff21514d8981	1122	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1123	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
AnnaBridge	156:ff21514d8981	1124
AnnaBridge	156:ff21514d8981	1125	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	156:ff21514d8981	1126	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
AnnaBridge	156:ff21514d8981	1127
AnnaBridge	156:ff21514d8981	1128	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1129	((STATE) == FMC_NAND_ECC_ENABLE))
AnnaBridge	156:ff21514d8981	1130
AnnaBridge	156:ff21514d8981	1131	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
AnnaBridge	156:ff21514d8981	1132	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
AnnaBridge	156:ff21514d8981	1133	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
AnnaBridge	156:ff21514d8981	1134	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
AnnaBridge	156:ff21514d8981	1135	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
AnnaBridge	156:ff21514d8981	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
AnnaBridge	156:ff21514d8981	1137
AnnaBridge	156:ff21514d8981	1138	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	156:ff21514d8981	1139
AnnaBridge	156:ff21514d8981	1140	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	156:ff21514d8981	1141
AnnaBridge	156:ff21514d8981	1142	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	156:ff21514d8981	1143
AnnaBridge	156:ff21514d8981	1144	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	156:ff21514d8981	1145
AnnaBridge	156:ff21514d8981	1146	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	156:ff21514d8981	1147
AnnaBridge	156:ff21514d8981	1148	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	156:ff21514d8981	1149
AnnaBridge	156:ff21514d8981	1150	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
AnnaBridge	156:ff21514d8981	1151
AnnaBridge	156:ff21514d8981	1152	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
AnnaBridge	156:ff21514d8981	1153
AnnaBridge	156:ff21514d8981	1154	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
AnnaBridge	156:ff21514d8981	1155
AnnaBridge	156:ff21514d8981	1156	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
AnnaBridge	156:ff21514d8981	1157
AnnaBridge	156:ff21514d8981	1158	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1159	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
AnnaBridge	156:ff21514d8981	1160
AnnaBridge	156:ff21514d8981	1161	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
AnnaBridge	156:ff21514d8981	1162	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
AnnaBridge	156:ff21514d8981	1163
AnnaBridge	156:ff21514d8981	1164	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
AnnaBridge	156:ff21514d8981	1165	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1166	((__MODE__) == FMC_WRAP_MODE_ENABLE))
AnnaBridge	156:ff21514d8981	1167	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
AnnaBridge	156:ff21514d8981	1168
AnnaBridge	156:ff21514d8981	1169	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
AnnaBridge	156:ff21514d8981	1170	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
AnnaBridge	156:ff21514d8981	1171
AnnaBridge	156:ff21514d8981	1172	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1173	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
AnnaBridge	156:ff21514d8981	1174
AnnaBridge	156:ff21514d8981	1175	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1176	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
AnnaBridge	156:ff21514d8981	1177
AnnaBridge	156:ff21514d8981	1178	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1179	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
AnnaBridge	156:ff21514d8981	1180
AnnaBridge	156:ff21514d8981	1181	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1182	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
AnnaBridge	156:ff21514d8981	1183
AnnaBridge	156:ff21514d8981	1184	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1185	((__BURST__) == FMC_WRITE_BURST_ENABLE))
AnnaBridge	156:ff21514d8981	1186
AnnaBridge	156:ff21514d8981	1187	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
AnnaBridge	156:ff21514d8981	1188	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
AnnaBridge	156:ff21514d8981	1189
AnnaBridge	156:ff21514d8981	1190	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	156:ff21514d8981	1191
AnnaBridge	156:ff21514d8981	1192	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
AnnaBridge	156:ff21514d8981	1193
AnnaBridge	156:ff21514d8981	1194	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
AnnaBridge	156:ff21514d8981	1195
AnnaBridge	156:ff21514d8981	1196	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	156:ff21514d8981	1197
AnnaBridge	156:ff21514d8981	1198	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
AnnaBridge	156:ff21514d8981	1199
AnnaBridge	156:ff21514d8981	1200	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
AnnaBridge	156:ff21514d8981	1201
AnnaBridge	156:ff21514d8981	1202	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
AnnaBridge	156:ff21514d8981	1203	((BANK) == FMC_SDRAM_BANK2))
AnnaBridge	156:ff21514d8981	1204
AnnaBridge	156:ff21514d8981	1205	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
AnnaBridge	156:ff21514d8981	1206	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
AnnaBridge	156:ff21514d8981	1207	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
AnnaBridge	156:ff21514d8981	1208	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
AnnaBridge	156:ff21514d8981	1209
AnnaBridge	156:ff21514d8981	1210	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
AnnaBridge	156:ff21514d8981	1211	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
AnnaBridge	156:ff21514d8981	1212	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
AnnaBridge	156:ff21514d8981	1213
AnnaBridge	156:ff21514d8981	1214	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	156:ff21514d8981	1215	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
AnnaBridge	156:ff21514d8981	1216	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
AnnaBridge	156:ff21514d8981	1217
AnnaBridge	156:ff21514d8981	1218	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
AnnaBridge	156:ff21514d8981	1219	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
AnnaBridge	156:ff21514d8981	1220
AnnaBridge	156:ff21514d8981	1221
AnnaBridge	156:ff21514d8981	1222	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
AnnaBridge	156:ff21514d8981	1223	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
AnnaBridge	156:ff21514d8981	1224	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
AnnaBridge	156:ff21514d8981	1225
AnnaBridge	156:ff21514d8981	1226	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1227	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
AnnaBridge	156:ff21514d8981	1228	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
AnnaBridge	156:ff21514d8981	1229
AnnaBridge	156:ff21514d8981	1230	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1231	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
AnnaBridge	156:ff21514d8981	1232
AnnaBridge	156:ff21514d8981	1233
AnnaBridge	156:ff21514d8981	1234	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
AnnaBridge	156:ff21514d8981	1235	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
AnnaBridge	156:ff21514d8981	1236	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
AnnaBridge	156:ff21514d8981	1237
AnnaBridge	156:ff21514d8981	1238	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
AnnaBridge	156:ff21514d8981	1239
AnnaBridge	156:ff21514d8981	1240	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
AnnaBridge	156:ff21514d8981	1241
AnnaBridge	156:ff21514d8981	1242	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
AnnaBridge	156:ff21514d8981	1243
AnnaBridge	156:ff21514d8981	1244	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
AnnaBridge	156:ff21514d8981	1245
AnnaBridge	156:ff21514d8981	1246	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
AnnaBridge	156:ff21514d8981	1247
AnnaBridge	156:ff21514d8981	1248	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
AnnaBridge	156:ff21514d8981	1249
AnnaBridge	156:ff21514d8981	1250	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
AnnaBridge	156:ff21514d8981	1251
AnnaBridge	156:ff21514d8981	1252	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
AnnaBridge	156:ff21514d8981	1253	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
AnnaBridge	156:ff21514d8981	1254	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
AnnaBridge	156:ff21514d8981	1255	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
AnnaBridge	156:ff21514d8981	1256	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
AnnaBridge	156:ff21514d8981	1257	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
AnnaBridge	156:ff21514d8981	1258	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
AnnaBridge	156:ff21514d8981	1259
AnnaBridge	156:ff21514d8981	1260	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
AnnaBridge	156:ff21514d8981	1261	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
AnnaBridge	156:ff21514d8981	1262	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
AnnaBridge	156:ff21514d8981	1263
AnnaBridge	156:ff21514d8981	1264	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
AnnaBridge	156:ff21514d8981	1265
AnnaBridge	156:ff21514d8981	1266	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
AnnaBridge	156:ff21514d8981	1267
AnnaBridge	156:ff21514d8981	1268	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
AnnaBridge	156:ff21514d8981	1269
AnnaBridge	156:ff21514d8981	1270	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
AnnaBridge	156:ff21514d8981	1271
AnnaBridge	156:ff21514d8981	1272	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1273	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
AnnaBridge	156:ff21514d8981	1274
AnnaBridge	156:ff21514d8981	1275	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
AnnaBridge	156:ff21514d8981	1276	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
AnnaBridge	156:ff21514d8981	1277	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
AnnaBridge	156:ff21514d8981	1278	((SIZE) == FMC_PAGE_SIZE_512) \|\| \
AnnaBridge	156:ff21514d8981	1279	((SIZE) == FMC_PAGE_SIZE_1024))
AnnaBridge	156:ff21514d8981	1280
AnnaBridge	156:ff21514d8981	1281	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1282	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	1283	((FIFO) == FMC_WRITE_FIFO_ENABLE))
AnnaBridge	156:ff21514d8981	1284	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1285
AnnaBridge	156:ff21514d8981	1286	/**
AnnaBridge	156:ff21514d8981	1287	* @}
AnnaBridge	156:ff21514d8981	1288	*/
AnnaBridge	156:ff21514d8981	1289
AnnaBridge	156:ff21514d8981	1290	/**
AnnaBridge	156:ff21514d8981	1291	* @}
AnnaBridge	156:ff21514d8981	1292	*/
AnnaBridge	156:ff21514d8981	1293
AnnaBridge	156:ff21514d8981	1294	/* Private functions ---------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	1295	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
AnnaBridge	156:ff21514d8981	1296	* @{
AnnaBridge	156:ff21514d8981	1297	*/
AnnaBridge	156:ff21514d8981	1298
AnnaBridge	156:ff21514d8981	1299	/** @defgroup FMC_LL_NORSRAM NOR SRAM
AnnaBridge	156:ff21514d8981	1300	* @{
AnnaBridge	156:ff21514d8981	1301	*/
AnnaBridge	156:ff21514d8981	1302	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
AnnaBridge	156:ff21514d8981	1303	* @{
AnnaBridge	156:ff21514d8981	1304	*/
AnnaBridge	156:ff21514d8981	1305	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
AnnaBridge	156:ff21514d8981	1306	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1307	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
AnnaBridge	156:ff21514d8981	1308	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1309	/**
AnnaBridge	156:ff21514d8981	1310	* @}
AnnaBridge	156:ff21514d8981	1311	*/
AnnaBridge	156:ff21514d8981	1312
AnnaBridge	156:ff21514d8981	1313	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
AnnaBridge	156:ff21514d8981	1314	* @{
AnnaBridge	156:ff21514d8981	1315	*/
AnnaBridge	156:ff21514d8981	1316	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1317	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1318	/**
AnnaBridge	156:ff21514d8981	1319	* @}
AnnaBridge	156:ff21514d8981	1320	*/
AnnaBridge	156:ff21514d8981	1321	/**
AnnaBridge	156:ff21514d8981	1322	* @}
AnnaBridge	156:ff21514d8981	1323	*/
AnnaBridge	156:ff21514d8981	1324
AnnaBridge	156:ff21514d8981	1325	/** @defgroup FMC_LL_NAND NAND
AnnaBridge	156:ff21514d8981	1326	* @{
AnnaBridge	156:ff21514d8981	1327	*/
AnnaBridge	156:ff21514d8981	1328	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
AnnaBridge	156:ff21514d8981	1329	* @{
AnnaBridge	156:ff21514d8981	1330	*/
AnnaBridge	156:ff21514d8981	1331	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
AnnaBridge	156:ff21514d8981	1332	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1333	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1334	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1335	/**
AnnaBridge	156:ff21514d8981	1336	* @}
AnnaBridge	156:ff21514d8981	1337	*/
AnnaBridge	156:ff21514d8981	1338
AnnaBridge	156:ff21514d8981	1339	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
AnnaBridge	156:ff21514d8981	1340	* @{
AnnaBridge	156:ff21514d8981	1341	*/
AnnaBridge	156:ff21514d8981	1342	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1343	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1344	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
AnnaBridge	156:ff21514d8981	1345
AnnaBridge	156:ff21514d8981	1346	/**
AnnaBridge	156:ff21514d8981	1347	* @}
AnnaBridge	156:ff21514d8981	1348	*/
AnnaBridge	156:ff21514d8981	1349	/**
AnnaBridge	156:ff21514d8981	1350	* @}
AnnaBridge	156:ff21514d8981	1351	*/
AnnaBridge	156:ff21514d8981	1352	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
AnnaBridge	156:ff21514d8981	1353	/** @defgroup FMC_LL_PCCARD PCCARD
AnnaBridge	156:ff21514d8981	1354	* @{
AnnaBridge	156:ff21514d8981	1355	*/
AnnaBridge	156:ff21514d8981	1356	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
AnnaBridge	156:ff21514d8981	1357	* @{
AnnaBridge	156:ff21514d8981	1358	*/
AnnaBridge	156:ff21514d8981	1359	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
AnnaBridge	156:ff21514d8981	1360	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	156:ff21514d8981	1361	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	156:ff21514d8981	1362	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	156:ff21514d8981	1363	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
AnnaBridge	156:ff21514d8981	1364	/**
AnnaBridge	156:ff21514d8981	1365	* @}
AnnaBridge	156:ff21514d8981	1366	*/
AnnaBridge	156:ff21514d8981	1367	/**
AnnaBridge	156:ff21514d8981	1368	* @}
AnnaBridge	156:ff21514d8981	1369	*/
AnnaBridge	156:ff21514d8981	1370	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
AnnaBridge	156:ff21514d8981	1371
AnnaBridge	156:ff21514d8981	1372	/** @defgroup FMC_LL_SDRAM SDRAM
AnnaBridge	156:ff21514d8981	1373	* @{
AnnaBridge	156:ff21514d8981	1374	*/
AnnaBridge	156:ff21514d8981	1375	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
AnnaBridge	156:ff21514d8981	1376	* @{
AnnaBridge	156:ff21514d8981	1377	*/
AnnaBridge	156:ff21514d8981	1378	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
AnnaBridge	156:ff21514d8981	1379	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1380	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1381	/**
AnnaBridge	156:ff21514d8981	1382	* @}
AnnaBridge	156:ff21514d8981	1383	*/
AnnaBridge	156:ff21514d8981	1384
AnnaBridge	156:ff21514d8981	1385	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
AnnaBridge	156:ff21514d8981	1386	* @{
AnnaBridge	156:ff21514d8981	1387	*/
AnnaBridge	156:ff21514d8981	1388	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1389	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1390	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
AnnaBridge	156:ff21514d8981	1391	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
AnnaBridge	156:ff21514d8981	1392	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
AnnaBridge	156:ff21514d8981	1393	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	156:ff21514d8981	1394	/**
AnnaBridge	156:ff21514d8981	1395	* @}
AnnaBridge	156:ff21514d8981	1396	*/
AnnaBridge	156:ff21514d8981	1397	/**
AnnaBridge	156:ff21514d8981	1398	* @}
AnnaBridge	156:ff21514d8981	1399	*/
AnnaBridge	156:ff21514d8981	1400
AnnaBridge	156:ff21514d8981	1401	/**
AnnaBridge	156:ff21514d8981	1402	* @}
AnnaBridge	156:ff21514d8981	1403	*/
AnnaBridge	156:ff21514d8981	1404
AnnaBridge	156:ff21514d8981	1405	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1406	/**
AnnaBridge	156:ff21514d8981	1407	* @}
AnnaBridge	156:ff21514d8981	1408	*/
AnnaBridge	156:ff21514d8981	1409
AnnaBridge	156:ff21514d8981	1410	/**
AnnaBridge	156:ff21514d8981	1411	* @}
AnnaBridge	156:ff21514d8981	1412	*/
AnnaBridge	156:ff21514d8981	1413	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	1414	}
AnnaBridge	156:ff21514d8981	1415	#endif
AnnaBridge	156:ff21514d8981	1416
AnnaBridge	156:ff21514d8981	1417	#endif /* __STM32F4xx_LL_FMC_H */
AnnaBridge	156:ff21514d8981	1418
AnnaBridge	156:ff21514d8981	1419	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/