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mbed 2

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TARGET_B96B_F446VE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
163:e59c8e839560 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file stm32f4xx_hal_sdram.h
AnnaBridge 156:ff21514d8981 4 * @author MCD Application Team
AnnaBridge 156:ff21514d8981 5 * @brief Header file of SDRAM HAL module.
AnnaBridge 156:ff21514d8981 6 ******************************************************************************
AnnaBridge 156:ff21514d8981 7 * @attention
AnnaBridge 156:ff21514d8981 8 *
AnnaBridge 156:ff21514d8981 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 156:ff21514d8981 10 *
AnnaBridge 156:ff21514d8981 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 156:ff21514d8981 12 * are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 156:ff21514d8981 14 * this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 156:ff21514d8981 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 156:ff21514d8981 17 * and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 156:ff21514d8981 19 * may be used to endorse or promote products derived from this software
AnnaBridge 156:ff21514d8981 20 * without specific prior written permission.
AnnaBridge 156:ff21514d8981 21 *
AnnaBridge 156:ff21514d8981 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 156:ff21514d8981 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 156:ff21514d8981 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 156:ff21514d8981 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 156:ff21514d8981 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 156:ff21514d8981 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 156:ff21514d8981 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 156:ff21514d8981 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 32 *
AnnaBridge 156:ff21514d8981 33 ******************************************************************************
AnnaBridge 156:ff21514d8981 34 */
AnnaBridge 156:ff21514d8981 35
AnnaBridge 156:ff21514d8981 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 156:ff21514d8981 37 #ifndef __STM32F4xx_HAL_SDRAM_H
AnnaBridge 156:ff21514d8981 38 #define __STM32F4xx_HAL_SDRAM_H
AnnaBridge 156:ff21514d8981 39
AnnaBridge 156:ff21514d8981 40 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 41 extern "C" {
AnnaBridge 156:ff21514d8981 42 #endif
AnnaBridge 156:ff21514d8981 43
AnnaBridge 156:ff21514d8981 44 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
AnnaBridge 156:ff21514d8981 45 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
AnnaBridge 156:ff21514d8981 46
AnnaBridge 156:ff21514d8981 47 /* Includes ------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 48 #include "stm32f4xx_ll_fmc.h"
AnnaBridge 156:ff21514d8981 49
AnnaBridge 156:ff21514d8981 50 /** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge 156:ff21514d8981 51 * @{
AnnaBridge 156:ff21514d8981 52 */
AnnaBridge 156:ff21514d8981 53
AnnaBridge 156:ff21514d8981 54 /** @addtogroup SDRAM
AnnaBridge 156:ff21514d8981 55 * @{
AnnaBridge 156:ff21514d8981 56 */
AnnaBridge 156:ff21514d8981 57
AnnaBridge 156:ff21514d8981 58 /* Exported typedef ----------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 59 /** @defgroup SDRAM_Exported_Types SDRAM Exported Types
AnnaBridge 156:ff21514d8981 60 * @{
AnnaBridge 156:ff21514d8981 61 */
AnnaBridge 156:ff21514d8981 62
AnnaBridge 156:ff21514d8981 63 /**
AnnaBridge 156:ff21514d8981 64 * @brief HAL SDRAM State structure definition
AnnaBridge 156:ff21514d8981 65 */
AnnaBridge 156:ff21514d8981 66 typedef enum
AnnaBridge 156:ff21514d8981 67 {
AnnaBridge 156:ff21514d8981 68 HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */
AnnaBridge 156:ff21514d8981 69 HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */
AnnaBridge 156:ff21514d8981 70 HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */
AnnaBridge 156:ff21514d8981 71 HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */
AnnaBridge 156:ff21514d8981 72 HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */
AnnaBridge 156:ff21514d8981 73 HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */
AnnaBridge 156:ff21514d8981 74
AnnaBridge 156:ff21514d8981 75 }HAL_SDRAM_StateTypeDef;
AnnaBridge 156:ff21514d8981 76
AnnaBridge 156:ff21514d8981 77 /**
AnnaBridge 156:ff21514d8981 78 * @brief SDRAM handle Structure definition
AnnaBridge 156:ff21514d8981 79 */
AnnaBridge 156:ff21514d8981 80 typedef struct
AnnaBridge 156:ff21514d8981 81 {
AnnaBridge 156:ff21514d8981 82 FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
AnnaBridge 156:ff21514d8981 83
AnnaBridge 156:ff21514d8981 84 FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
AnnaBridge 156:ff21514d8981 85
AnnaBridge 156:ff21514d8981 86 __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
AnnaBridge 156:ff21514d8981 87
AnnaBridge 156:ff21514d8981 88 HAL_LockTypeDef Lock; /*!< SDRAM locking object */
AnnaBridge 156:ff21514d8981 89
AnnaBridge 156:ff21514d8981 90 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
AnnaBridge 156:ff21514d8981 91
AnnaBridge 156:ff21514d8981 92 }SDRAM_HandleTypeDef;
AnnaBridge 156:ff21514d8981 93 /**
AnnaBridge 156:ff21514d8981 94 * @}
AnnaBridge 156:ff21514d8981 95 */
AnnaBridge 156:ff21514d8981 96
AnnaBridge 156:ff21514d8981 97 /* Exported constants --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 98 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 99 /** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
AnnaBridge 156:ff21514d8981 100 * @{
AnnaBridge 156:ff21514d8981 101 */
AnnaBridge 156:ff21514d8981 102
AnnaBridge 156:ff21514d8981 103 /** @brief Reset SDRAM handle state
AnnaBridge 163:e59c8e839560 104 * @param __HANDLE__ specifies the SDRAM handle.
AnnaBridge 156:ff21514d8981 105 * @retval None
AnnaBridge 156:ff21514d8981 106 */
AnnaBridge 156:ff21514d8981 107 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
AnnaBridge 156:ff21514d8981 108 /**
AnnaBridge 156:ff21514d8981 109 * @}
AnnaBridge 156:ff21514d8981 110 */
AnnaBridge 156:ff21514d8981 111
AnnaBridge 156:ff21514d8981 112 /* Exported functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 113 /** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
AnnaBridge 156:ff21514d8981 114 * @{
AnnaBridge 156:ff21514d8981 115 */
AnnaBridge 156:ff21514d8981 116
AnnaBridge 156:ff21514d8981 117 /** @addtogroup SDRAM_Exported_Functions_Group1
AnnaBridge 156:ff21514d8981 118 * @{
AnnaBridge 156:ff21514d8981 119 */
AnnaBridge 156:ff21514d8981 120
AnnaBridge 156:ff21514d8981 121 /* Initialization/de-initialization functions *********************************/
AnnaBridge 156:ff21514d8981 122 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
AnnaBridge 156:ff21514d8981 123 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
AnnaBridge 156:ff21514d8981 124 void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
AnnaBridge 156:ff21514d8981 125 void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
AnnaBridge 156:ff21514d8981 126
AnnaBridge 156:ff21514d8981 127 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
AnnaBridge 156:ff21514d8981 128 void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
AnnaBridge 156:ff21514d8981 129 void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 130 void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 131 /**
AnnaBridge 156:ff21514d8981 132 * @}
AnnaBridge 156:ff21514d8981 133 */
AnnaBridge 156:ff21514d8981 134
AnnaBridge 156:ff21514d8981 135 /** @addtogroup SDRAM_Exported_Functions_Group2
AnnaBridge 156:ff21514d8981 136 * @{
AnnaBridge 156:ff21514d8981 137 */
AnnaBridge 156:ff21514d8981 138 /* I/O operation functions ****************************************************/
AnnaBridge 156:ff21514d8981 139 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 156:ff21514d8981 140 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 156:ff21514d8981 141 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 156:ff21514d8981 142 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 156:ff21514d8981 143 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 156:ff21514d8981 144 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 156:ff21514d8981 145
AnnaBridge 156:ff21514d8981 146 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 156:ff21514d8981 147 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 156:ff21514d8981 148 /**
AnnaBridge 156:ff21514d8981 149 * @}
AnnaBridge 156:ff21514d8981 150 */
AnnaBridge 156:ff21514d8981 151
AnnaBridge 156:ff21514d8981 152 /** @addtogroup SDRAM_Exported_Functions_Group3
AnnaBridge 156:ff21514d8981 153 * @{
AnnaBridge 156:ff21514d8981 154 */
AnnaBridge 156:ff21514d8981 155 /* SDRAM Control functions *****************************************************/
AnnaBridge 156:ff21514d8981 156 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
AnnaBridge 156:ff21514d8981 157 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
AnnaBridge 156:ff21514d8981 158 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
AnnaBridge 156:ff21514d8981 159 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
AnnaBridge 156:ff21514d8981 160 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
AnnaBridge 156:ff21514d8981 161 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
AnnaBridge 156:ff21514d8981 162 /**
AnnaBridge 156:ff21514d8981 163 * @}
AnnaBridge 156:ff21514d8981 164 */
AnnaBridge 156:ff21514d8981 165
AnnaBridge 156:ff21514d8981 166 /** @addtogroup SDRAM_Exported_Functions_Group4
AnnaBridge 156:ff21514d8981 167 * @{
AnnaBridge 156:ff21514d8981 168 */
AnnaBridge 156:ff21514d8981 169 /* SDRAM State functions ********************************************************/
AnnaBridge 156:ff21514d8981 170 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
AnnaBridge 156:ff21514d8981 171 /**
AnnaBridge 156:ff21514d8981 172 * @}
AnnaBridge 156:ff21514d8981 173 */
AnnaBridge 156:ff21514d8981 174
AnnaBridge 156:ff21514d8981 175 /**
AnnaBridge 156:ff21514d8981 176 * @}
AnnaBridge 156:ff21514d8981 177 */
AnnaBridge 156:ff21514d8981 178
AnnaBridge 156:ff21514d8981 179 /**
AnnaBridge 156:ff21514d8981 180 * @}
AnnaBridge 156:ff21514d8981 181 */
AnnaBridge 156:ff21514d8981 182
AnnaBridge 156:ff21514d8981 183 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
AnnaBridge 156:ff21514d8981 184
AnnaBridge 156:ff21514d8981 185 /**
AnnaBridge 156:ff21514d8981 186 * @}
AnnaBridge 156:ff21514d8981 187 */
AnnaBridge 156:ff21514d8981 188
AnnaBridge 156:ff21514d8981 189 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 190 }
AnnaBridge 156:ff21514d8981 191 #endif
AnnaBridge 156:ff21514d8981 192
AnnaBridge 156:ff21514d8981 193 #endif /* __STM32F4xx_HAL_SDRAM_H */
AnnaBridge 156:ff21514d8981 194
AnnaBridge 156:ff21514d8981 195 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/