mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_B96B_F446VE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
163:e59c8e839560 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file stm32f4xx_hal_rcc.h
AnnaBridge 156:ff21514d8981 4 * @author MCD Application Team
AnnaBridge 156:ff21514d8981 5 * @brief Header file of RCC HAL module.
AnnaBridge 156:ff21514d8981 6 ******************************************************************************
AnnaBridge 156:ff21514d8981 7 * @attention
AnnaBridge 156:ff21514d8981 8 *
AnnaBridge 156:ff21514d8981 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 156:ff21514d8981 10 *
AnnaBridge 156:ff21514d8981 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 156:ff21514d8981 12 * are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 156:ff21514d8981 14 * this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 156:ff21514d8981 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 156:ff21514d8981 17 * and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 156:ff21514d8981 19 * may be used to endorse or promote products derived from this software
AnnaBridge 156:ff21514d8981 20 * without specific prior written permission.
AnnaBridge 156:ff21514d8981 21 *
AnnaBridge 156:ff21514d8981 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 156:ff21514d8981 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 156:ff21514d8981 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 156:ff21514d8981 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 156:ff21514d8981 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 156:ff21514d8981 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 156:ff21514d8981 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 156:ff21514d8981 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 32 *
AnnaBridge 156:ff21514d8981 33 ******************************************************************************
AnnaBridge 156:ff21514d8981 34 */
AnnaBridge 156:ff21514d8981 35
AnnaBridge 156:ff21514d8981 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 156:ff21514d8981 37 #ifndef __STM32F4xx_HAL_RCC_H
AnnaBridge 156:ff21514d8981 38 #define __STM32F4xx_HAL_RCC_H
AnnaBridge 156:ff21514d8981 39
AnnaBridge 156:ff21514d8981 40 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 41 extern "C" {
AnnaBridge 156:ff21514d8981 42 #endif
AnnaBridge 156:ff21514d8981 43
AnnaBridge 156:ff21514d8981 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 45 #include "stm32f4xx_hal_def.h"
AnnaBridge 156:ff21514d8981 46
AnnaBridge 156:ff21514d8981 47 /* Include RCC HAL Extended module */
AnnaBridge 156:ff21514d8981 48 /* (include on top of file since RCC structures are defined in extended file) */
AnnaBridge 156:ff21514d8981 49 #include "stm32f4xx_hal_rcc_ex.h"
AnnaBridge 156:ff21514d8981 50
AnnaBridge 156:ff21514d8981 51 /** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge 156:ff21514d8981 52 * @{
AnnaBridge 156:ff21514d8981 53 */
AnnaBridge 156:ff21514d8981 54
AnnaBridge 163:e59c8e839560 55 /** @addtogroup RCC
AnnaBridge 156:ff21514d8981 56 * @{
AnnaBridge 156:ff21514d8981 57 */
AnnaBridge 156:ff21514d8981 58
AnnaBridge 156:ff21514d8981 59 /* Exported types ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 60 /** @defgroup RCC_Exported_Types RCC Exported Types
AnnaBridge 156:ff21514d8981 61 * @{
AnnaBridge 156:ff21514d8981 62 */
AnnaBridge 163:e59c8e839560 63
AnnaBridge 156:ff21514d8981 64 /**
AnnaBridge 163:e59c8e839560 65 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
AnnaBridge 156:ff21514d8981 66 */
AnnaBridge 156:ff21514d8981 67 typedef struct
AnnaBridge 156:ff21514d8981 68 {
AnnaBridge 156:ff21514d8981 69 uint32_t OscillatorType; /*!< The oscillators to be configured.
AnnaBridge 156:ff21514d8981 70 This parameter can be a value of @ref RCC_Oscillator_Type */
AnnaBridge 156:ff21514d8981 71
AnnaBridge 156:ff21514d8981 72 uint32_t HSEState; /*!< The new state of the HSE.
AnnaBridge 156:ff21514d8981 73 This parameter can be a value of @ref RCC_HSE_Config */
AnnaBridge 156:ff21514d8981 74
AnnaBridge 156:ff21514d8981 75 uint32_t LSEState; /*!< The new state of the LSE.
AnnaBridge 156:ff21514d8981 76 This parameter can be a value of @ref RCC_LSE_Config */
AnnaBridge 156:ff21514d8981 77
AnnaBridge 156:ff21514d8981 78 uint32_t HSIState; /*!< The new state of the HSI.
AnnaBridge 156:ff21514d8981 79 This parameter can be a value of @ref RCC_HSI_Config */
AnnaBridge 156:ff21514d8981 80
AnnaBridge 156:ff21514d8981 81 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge 156:ff21514d8981 82 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
AnnaBridge 156:ff21514d8981 83
AnnaBridge 156:ff21514d8981 84 uint32_t LSIState; /*!< The new state of the LSI.
AnnaBridge 156:ff21514d8981 85 This parameter can be a value of @ref RCC_LSI_Config */
AnnaBridge 156:ff21514d8981 86
AnnaBridge 156:ff21514d8981 87 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
AnnaBridge 156:ff21514d8981 88 }RCC_OscInitTypeDef;
AnnaBridge 156:ff21514d8981 89
AnnaBridge 156:ff21514d8981 90 /**
AnnaBridge 163:e59c8e839560 91 * @brief RCC System, AHB and APB busses clock configuration structure definition
AnnaBridge 156:ff21514d8981 92 */
AnnaBridge 156:ff21514d8981 93 typedef struct
AnnaBridge 156:ff21514d8981 94 {
AnnaBridge 156:ff21514d8981 95 uint32_t ClockType; /*!< The clock to be configured.
AnnaBridge 156:ff21514d8981 96 This parameter can be a value of @ref RCC_System_Clock_Type */
AnnaBridge 156:ff21514d8981 97
AnnaBridge 156:ff21514d8981 98 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
AnnaBridge 156:ff21514d8981 99 This parameter can be a value of @ref RCC_System_Clock_Source */
AnnaBridge 156:ff21514d8981 100
AnnaBridge 156:ff21514d8981 101 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
AnnaBridge 156:ff21514d8981 102 This parameter can be a value of @ref RCC_AHB_Clock_Source */
AnnaBridge 156:ff21514d8981 103
AnnaBridge 156:ff21514d8981 104 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge 156:ff21514d8981 105 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge 156:ff21514d8981 106
AnnaBridge 156:ff21514d8981 107 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge 156:ff21514d8981 108 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge 156:ff21514d8981 109
AnnaBridge 156:ff21514d8981 110 }RCC_ClkInitTypeDef;
AnnaBridge 156:ff21514d8981 111
AnnaBridge 156:ff21514d8981 112 /**
AnnaBridge 156:ff21514d8981 113 * @}
AnnaBridge 156:ff21514d8981 114 */
AnnaBridge 156:ff21514d8981 115
AnnaBridge 156:ff21514d8981 116 /* Exported constants --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 117 /** @defgroup RCC_Exported_Constants RCC Exported Constants
AnnaBridge 156:ff21514d8981 118 * @{
AnnaBridge 156:ff21514d8981 119 */
AnnaBridge 156:ff21514d8981 120
AnnaBridge 156:ff21514d8981 121 /** @defgroup RCC_Oscillator_Type Oscillator Type
AnnaBridge 156:ff21514d8981 122 * @{
AnnaBridge 156:ff21514d8981 123 */
AnnaBridge 156:ff21514d8981 124 #define RCC_OSCILLATORTYPE_NONE 0x00000000U
AnnaBridge 156:ff21514d8981 125 #define RCC_OSCILLATORTYPE_HSE 0x00000001U
AnnaBridge 156:ff21514d8981 126 #define RCC_OSCILLATORTYPE_HSI 0x00000002U
AnnaBridge 156:ff21514d8981 127 #define RCC_OSCILLATORTYPE_LSE 0x00000004U
AnnaBridge 156:ff21514d8981 128 #define RCC_OSCILLATORTYPE_LSI 0x00000008U
AnnaBridge 156:ff21514d8981 129 /**
AnnaBridge 156:ff21514d8981 130 * @}
AnnaBridge 156:ff21514d8981 131 */
AnnaBridge 156:ff21514d8981 132
AnnaBridge 156:ff21514d8981 133 /** @defgroup RCC_HSE_Config HSE Config
AnnaBridge 156:ff21514d8981 134 * @{
AnnaBridge 156:ff21514d8981 135 */
AnnaBridge 156:ff21514d8981 136 #define RCC_HSE_OFF 0x00000000U
AnnaBridge 156:ff21514d8981 137 #define RCC_HSE_ON RCC_CR_HSEON
AnnaBridge 156:ff21514d8981 138 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
AnnaBridge 156:ff21514d8981 139 /**
AnnaBridge 156:ff21514d8981 140 * @}
AnnaBridge 156:ff21514d8981 141 */
AnnaBridge 156:ff21514d8981 142
AnnaBridge 156:ff21514d8981 143 /** @defgroup RCC_LSE_Config LSE Config
AnnaBridge 156:ff21514d8981 144 * @{
AnnaBridge 156:ff21514d8981 145 */
AnnaBridge 156:ff21514d8981 146 #define RCC_LSE_OFF 0x00000000U
AnnaBridge 156:ff21514d8981 147 #define RCC_LSE_ON RCC_BDCR_LSEON
AnnaBridge 156:ff21514d8981 148 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
AnnaBridge 156:ff21514d8981 149 /**
AnnaBridge 156:ff21514d8981 150 * @}
AnnaBridge 156:ff21514d8981 151 */
AnnaBridge 156:ff21514d8981 152
AnnaBridge 156:ff21514d8981 153 /** @defgroup RCC_HSI_Config HSI Config
AnnaBridge 156:ff21514d8981 154 * @{
AnnaBridge 156:ff21514d8981 155 */
AnnaBridge 156:ff21514d8981 156 #define RCC_HSI_OFF ((uint8_t)0x00)
AnnaBridge 156:ff21514d8981 157 #define RCC_HSI_ON ((uint8_t)0x01)
AnnaBridge 156:ff21514d8981 158
AnnaBridge 156:ff21514d8981 159 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
AnnaBridge 156:ff21514d8981 160 /**
AnnaBridge 156:ff21514d8981 161 * @}
AnnaBridge 156:ff21514d8981 162 */
AnnaBridge 156:ff21514d8981 163
AnnaBridge 156:ff21514d8981 164 /** @defgroup RCC_LSI_Config LSI Config
AnnaBridge 156:ff21514d8981 165 * @{
AnnaBridge 156:ff21514d8981 166 */
AnnaBridge 156:ff21514d8981 167 #define RCC_LSI_OFF ((uint8_t)0x00)
AnnaBridge 156:ff21514d8981 168 #define RCC_LSI_ON ((uint8_t)0x01)
AnnaBridge 156:ff21514d8981 169 /**
AnnaBridge 156:ff21514d8981 170 * @}
AnnaBridge 156:ff21514d8981 171 */
AnnaBridge 156:ff21514d8981 172
AnnaBridge 156:ff21514d8981 173 /** @defgroup RCC_PLL_Config PLL Config
AnnaBridge 156:ff21514d8981 174 * @{
AnnaBridge 156:ff21514d8981 175 */
AnnaBridge 156:ff21514d8981 176 #define RCC_PLL_NONE ((uint8_t)0x00)
AnnaBridge 156:ff21514d8981 177 #define RCC_PLL_OFF ((uint8_t)0x01)
AnnaBridge 156:ff21514d8981 178 #define RCC_PLL_ON ((uint8_t)0x02)
AnnaBridge 156:ff21514d8981 179 /**
AnnaBridge 156:ff21514d8981 180 * @}
AnnaBridge 156:ff21514d8981 181 */
AnnaBridge 156:ff21514d8981 182
AnnaBridge 156:ff21514d8981 183 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
AnnaBridge 156:ff21514d8981 184 * @{
AnnaBridge 156:ff21514d8981 185 */
AnnaBridge 156:ff21514d8981 186 #define RCC_PLLP_DIV2 0x00000002U
AnnaBridge 156:ff21514d8981 187 #define RCC_PLLP_DIV4 0x00000004U
AnnaBridge 156:ff21514d8981 188 #define RCC_PLLP_DIV6 0x00000006U
AnnaBridge 156:ff21514d8981 189 #define RCC_PLLP_DIV8 0x00000008U
AnnaBridge 156:ff21514d8981 190 /**
AnnaBridge 156:ff21514d8981 191 * @}
AnnaBridge 156:ff21514d8981 192 */
AnnaBridge 156:ff21514d8981 193
AnnaBridge 156:ff21514d8981 194 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
AnnaBridge 156:ff21514d8981 195 * @{
AnnaBridge 156:ff21514d8981 196 */
AnnaBridge 156:ff21514d8981 197 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
AnnaBridge 156:ff21514d8981 198 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
AnnaBridge 156:ff21514d8981 199 /**
AnnaBridge 156:ff21514d8981 200 * @}
AnnaBridge 156:ff21514d8981 201 */
AnnaBridge 156:ff21514d8981 202
AnnaBridge 156:ff21514d8981 203 /** @defgroup RCC_System_Clock_Type System Clock Type
AnnaBridge 156:ff21514d8981 204 * @{
AnnaBridge 156:ff21514d8981 205 */
AnnaBridge 156:ff21514d8981 206 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U
AnnaBridge 156:ff21514d8981 207 #define RCC_CLOCKTYPE_HCLK 0x00000002U
AnnaBridge 156:ff21514d8981 208 #define RCC_CLOCKTYPE_PCLK1 0x00000004U
AnnaBridge 156:ff21514d8981 209 #define RCC_CLOCKTYPE_PCLK2 0x00000008U
AnnaBridge 156:ff21514d8981 210 /**
AnnaBridge 156:ff21514d8981 211 * @}
AnnaBridge 156:ff21514d8981 212 */
AnnaBridge 163:e59c8e839560 213
AnnaBridge 163:e59c8e839560 214 /** @defgroup RCC_System_Clock_Source System Clock Source
AnnaBridge 156:ff21514d8981 215 * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
AnnaBridge 156:ff21514d8981 216 * STM32F446xx devices.
AnnaBridge 156:ff21514d8981 217 * @{
AnnaBridge 156:ff21514d8981 218 */
AnnaBridge 156:ff21514d8981 219 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
AnnaBridge 156:ff21514d8981 220 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
AnnaBridge 156:ff21514d8981 221 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
AnnaBridge 156:ff21514d8981 222 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
AnnaBridge 156:ff21514d8981 223 /**
AnnaBridge 156:ff21514d8981 224 * @}
AnnaBridge 156:ff21514d8981 225 */
AnnaBridge 156:ff21514d8981 226
AnnaBridge 156:ff21514d8981 227 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
AnnaBridge 156:ff21514d8981 228 * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
AnnaBridge 156:ff21514d8981 229 * STM32F446xx devices.
AnnaBridge 156:ff21514d8981 230 * @{
AnnaBridge 156:ff21514d8981 231 */
AnnaBridge 156:ff21514d8981 232 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
AnnaBridge 156:ff21514d8981 233 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
AnnaBridge 156:ff21514d8981 234 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
AnnaBridge 156:ff21514d8981 235 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */
AnnaBridge 156:ff21514d8981 236 /**
AnnaBridge 156:ff21514d8981 237 * @}
AnnaBridge 156:ff21514d8981 238 */
AnnaBridge 156:ff21514d8981 239
AnnaBridge 156:ff21514d8981 240 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
AnnaBridge 156:ff21514d8981 241 * @{
AnnaBridge 156:ff21514d8981 242 */
AnnaBridge 156:ff21514d8981 243 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
AnnaBridge 156:ff21514d8981 244 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
AnnaBridge 156:ff21514d8981 245 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
AnnaBridge 156:ff21514d8981 246 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
AnnaBridge 156:ff21514d8981 247 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
AnnaBridge 156:ff21514d8981 248 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
AnnaBridge 156:ff21514d8981 249 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
AnnaBridge 156:ff21514d8981 250 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
AnnaBridge 156:ff21514d8981 251 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
AnnaBridge 156:ff21514d8981 252 /**
AnnaBridge 156:ff21514d8981 253 * @}
AnnaBridge 163:e59c8e839560 254 */
AnnaBridge 163:e59c8e839560 255
AnnaBridge 156:ff21514d8981 256 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
AnnaBridge 156:ff21514d8981 257 * @{
AnnaBridge 156:ff21514d8981 258 */
AnnaBridge 156:ff21514d8981 259 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
AnnaBridge 156:ff21514d8981 260 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
AnnaBridge 156:ff21514d8981 261 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
AnnaBridge 156:ff21514d8981 262 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
AnnaBridge 156:ff21514d8981 263 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
AnnaBridge 156:ff21514d8981 264 /**
AnnaBridge 156:ff21514d8981 265 * @}
AnnaBridge 163:e59c8e839560 266 */
AnnaBridge 156:ff21514d8981 267
AnnaBridge 156:ff21514d8981 268 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
AnnaBridge 156:ff21514d8981 269 * @{
AnnaBridge 156:ff21514d8981 270 */
AnnaBridge 163:e59c8e839560 271 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
AnnaBridge 156:ff21514d8981 272 #define RCC_RTCCLKSOURCE_LSE 0x00000100U
AnnaBridge 156:ff21514d8981 273 #define RCC_RTCCLKSOURCE_LSI 0x00000200U
AnnaBridge 163:e59c8e839560 274 #define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U
AnnaBridge 156:ff21514d8981 275 #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
AnnaBridge 156:ff21514d8981 276 #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
AnnaBridge 156:ff21514d8981 277 #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
AnnaBridge 156:ff21514d8981 278 #define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
AnnaBridge 156:ff21514d8981 279 #define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
AnnaBridge 156:ff21514d8981 280 #define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
AnnaBridge 156:ff21514d8981 281 #define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
AnnaBridge 156:ff21514d8981 282 #define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
AnnaBridge 156:ff21514d8981 283 #define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
AnnaBridge 156:ff21514d8981 284 #define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
AnnaBridge 156:ff21514d8981 285 #define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
AnnaBridge 156:ff21514d8981 286 #define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
AnnaBridge 156:ff21514d8981 287 #define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
AnnaBridge 156:ff21514d8981 288 #define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
AnnaBridge 156:ff21514d8981 289 #define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
AnnaBridge 156:ff21514d8981 290 #define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
AnnaBridge 156:ff21514d8981 291 #define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
AnnaBridge 156:ff21514d8981 292 #define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
AnnaBridge 156:ff21514d8981 293 #define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
AnnaBridge 156:ff21514d8981 294 #define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
AnnaBridge 156:ff21514d8981 295 #define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
AnnaBridge 156:ff21514d8981 296 #define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
AnnaBridge 156:ff21514d8981 297 #define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
AnnaBridge 156:ff21514d8981 298 #define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
AnnaBridge 156:ff21514d8981 299 #define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
AnnaBridge 156:ff21514d8981 300 #define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
AnnaBridge 156:ff21514d8981 301 #define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
AnnaBridge 156:ff21514d8981 302 #define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
AnnaBridge 156:ff21514d8981 303 #define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
AnnaBridge 156:ff21514d8981 304 #define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
AnnaBridge 156:ff21514d8981 305 /**
AnnaBridge 156:ff21514d8981 306 * @}
AnnaBridge 156:ff21514d8981 307 */
AnnaBridge 156:ff21514d8981 308
AnnaBridge 156:ff21514d8981 309 /** @defgroup RCC_MCO_Index MCO Index
AnnaBridge 156:ff21514d8981 310 * @{
AnnaBridge 156:ff21514d8981 311 */
AnnaBridge 156:ff21514d8981 312 #define RCC_MCO1 0x00000000U
AnnaBridge 156:ff21514d8981 313 #define RCC_MCO2 0x00000001U
AnnaBridge 156:ff21514d8981 314 /**
AnnaBridge 156:ff21514d8981 315 * @}
AnnaBridge 156:ff21514d8981 316 */
AnnaBridge 156:ff21514d8981 317
AnnaBridge 156:ff21514d8981 318 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
AnnaBridge 156:ff21514d8981 319 * @{
AnnaBridge 156:ff21514d8981 320 */
AnnaBridge 156:ff21514d8981 321 #define RCC_MCO1SOURCE_HSI 0x00000000U
AnnaBridge 156:ff21514d8981 322 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
AnnaBridge 156:ff21514d8981 323 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
AnnaBridge 156:ff21514d8981 324 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
AnnaBridge 156:ff21514d8981 325 /**
AnnaBridge 156:ff21514d8981 326 * @}
AnnaBridge 156:ff21514d8981 327 */
AnnaBridge 156:ff21514d8981 328
AnnaBridge 156:ff21514d8981 329 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
AnnaBridge 156:ff21514d8981 330 * @{
AnnaBridge 156:ff21514d8981 331 */
AnnaBridge 156:ff21514d8981 332 #define RCC_MCODIV_1 0x00000000U
AnnaBridge 156:ff21514d8981 333 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
AnnaBridge 156:ff21514d8981 334 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
AnnaBridge 156:ff21514d8981 335 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
AnnaBridge 156:ff21514d8981 336 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
AnnaBridge 156:ff21514d8981 337 /**
AnnaBridge 156:ff21514d8981 338 * @}
AnnaBridge 156:ff21514d8981 339 */
AnnaBridge 156:ff21514d8981 340
AnnaBridge 156:ff21514d8981 341 /** @defgroup RCC_Interrupt Interrupts
AnnaBridge 156:ff21514d8981 342 * @{
AnnaBridge 156:ff21514d8981 343 */
AnnaBridge 156:ff21514d8981 344 #define RCC_IT_LSIRDY ((uint8_t)0x01)
AnnaBridge 156:ff21514d8981 345 #define RCC_IT_LSERDY ((uint8_t)0x02)
AnnaBridge 156:ff21514d8981 346 #define RCC_IT_HSIRDY ((uint8_t)0x04)
AnnaBridge 156:ff21514d8981 347 #define RCC_IT_HSERDY ((uint8_t)0x08)
AnnaBridge 156:ff21514d8981 348 #define RCC_IT_PLLRDY ((uint8_t)0x10)
AnnaBridge 156:ff21514d8981 349 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
AnnaBridge 156:ff21514d8981 350 #define RCC_IT_CSS ((uint8_t)0x80)
AnnaBridge 156:ff21514d8981 351 /**
AnnaBridge 156:ff21514d8981 352 * @}
AnnaBridge 156:ff21514d8981 353 */
AnnaBridge 163:e59c8e839560 354
AnnaBridge 156:ff21514d8981 355 /** @defgroup RCC_Flag Flags
AnnaBridge 156:ff21514d8981 356 * Elements values convention: 0XXYYYYYb
AnnaBridge 156:ff21514d8981 357 * - YYYYY : Flag position in the register
AnnaBridge 156:ff21514d8981 358 * - 0XX : Register index
AnnaBridge 156:ff21514d8981 359 * - 01: CR register
AnnaBridge 156:ff21514d8981 360 * - 10: BDCR register
AnnaBridge 156:ff21514d8981 361 * - 11: CSR register
AnnaBridge 156:ff21514d8981 362 * @{
AnnaBridge 156:ff21514d8981 363 */
AnnaBridge 156:ff21514d8981 364 /* Flags in the CR register */
AnnaBridge 156:ff21514d8981 365 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
AnnaBridge 156:ff21514d8981 366 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
AnnaBridge 156:ff21514d8981 367 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
AnnaBridge 156:ff21514d8981 368 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
AnnaBridge 156:ff21514d8981 369
AnnaBridge 156:ff21514d8981 370 /* Flags in the BDCR register */
AnnaBridge 156:ff21514d8981 371 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
AnnaBridge 156:ff21514d8981 372
AnnaBridge 156:ff21514d8981 373 /* Flags in the CSR register */
AnnaBridge 156:ff21514d8981 374 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
AnnaBridge 156:ff21514d8981 375 #define RCC_FLAG_BORRST ((uint8_t)0x79)
AnnaBridge 156:ff21514d8981 376 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
AnnaBridge 156:ff21514d8981 377 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
AnnaBridge 156:ff21514d8981 378 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
AnnaBridge 156:ff21514d8981 379 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
AnnaBridge 156:ff21514d8981 380 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
AnnaBridge 156:ff21514d8981 381 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
AnnaBridge 156:ff21514d8981 382 /**
AnnaBridge 156:ff21514d8981 383 * @}
AnnaBridge 163:e59c8e839560 384 */
AnnaBridge 156:ff21514d8981 385
AnnaBridge 156:ff21514d8981 386 /**
AnnaBridge 156:ff21514d8981 387 * @}
AnnaBridge 156:ff21514d8981 388 */
AnnaBridge 156:ff21514d8981 389
AnnaBridge 156:ff21514d8981 390 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 391 /** @defgroup RCC_Exported_Macros RCC Exported Macros
AnnaBridge 156:ff21514d8981 392 * @{
AnnaBridge 156:ff21514d8981 393 */
AnnaBridge 156:ff21514d8981 394
AnnaBridge 156:ff21514d8981 395 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge 156:ff21514d8981 396 * @brief Enable or disable the AHB1 peripheral clock.
AnnaBridge 156:ff21514d8981 397 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 163:e59c8e839560 398 * is disabled and the application software has to enable this clock before
AnnaBridge 163:e59c8e839560 399 * using it.
AnnaBridge 156:ff21514d8981 400 * @{
AnnaBridge 156:ff21514d8981 401 */
AnnaBridge 156:ff21514d8981 402 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 403 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 404 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
AnnaBridge 156:ff21514d8981 405 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 406 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
AnnaBridge 156:ff21514d8981 407 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 408 } while(0U)
AnnaBridge 156:ff21514d8981 409 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 410 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 411 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
AnnaBridge 156:ff21514d8981 412 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 413 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
AnnaBridge 156:ff21514d8981 414 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 415 } while(0U)
AnnaBridge 156:ff21514d8981 416 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 417 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 418 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
AnnaBridge 156:ff21514d8981 419 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 420 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
AnnaBridge 156:ff21514d8981 421 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 422 } while(0U)
AnnaBridge 156:ff21514d8981 423 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 424 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 425 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
AnnaBridge 156:ff21514d8981 426 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 427 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
AnnaBridge 156:ff21514d8981 428 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 429 } while(0U)
AnnaBridge 156:ff21514d8981 430 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 431 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 432 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
AnnaBridge 156:ff21514d8981 433 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 434 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
AnnaBridge 156:ff21514d8981 435 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 436 } while(0U)
AnnaBridge 156:ff21514d8981 437 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 438 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 439 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
AnnaBridge 156:ff21514d8981 440 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 441 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
AnnaBridge 156:ff21514d8981 442 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 443 } while(0U)
AnnaBridge 156:ff21514d8981 444
AnnaBridge 156:ff21514d8981 445 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
AnnaBridge 156:ff21514d8981 446 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
AnnaBridge 156:ff21514d8981 447 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
AnnaBridge 156:ff21514d8981 448 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
AnnaBridge 156:ff21514d8981 449 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
AnnaBridge 156:ff21514d8981 450 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
AnnaBridge 156:ff21514d8981 451 /**
AnnaBridge 156:ff21514d8981 452 * @}
AnnaBridge 156:ff21514d8981 453 */
AnnaBridge 156:ff21514d8981 454
AnnaBridge 156:ff21514d8981 455 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge 156:ff21514d8981 456 * @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge 156:ff21514d8981 457 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 156:ff21514d8981 458 * is disabled and the application software has to enable this clock before
AnnaBridge 156:ff21514d8981 459 * using it.
AnnaBridge 156:ff21514d8981 460 * @{
AnnaBridge 156:ff21514d8981 461 */
AnnaBridge 163:e59c8e839560 462 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
AnnaBridge 163:e59c8e839560 463 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
AnnaBridge 163:e59c8e839560 464 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
AnnaBridge 163:e59c8e839560 465 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
AnnaBridge 163:e59c8e839560 466 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
AnnaBridge 163:e59c8e839560 467 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
AnnaBridge 156:ff21514d8981 468
AnnaBridge 163:e59c8e839560 469 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
AnnaBridge 163:e59c8e839560 470 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
AnnaBridge 156:ff21514d8981 471 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
AnnaBridge 163:e59c8e839560 472 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
AnnaBridge 156:ff21514d8981 473 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
AnnaBridge 163:e59c8e839560 474 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
AnnaBridge 156:ff21514d8981 475 /**
AnnaBridge 156:ff21514d8981 476 * @}
AnnaBridge 163:e59c8e839560 477 */
AnnaBridge 163:e59c8e839560 478
AnnaBridge 156:ff21514d8981 479 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge 156:ff21514d8981 480 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge 156:ff21514d8981 481 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 156:ff21514d8981 482 * is disabled and the application software has to enable this clock before
AnnaBridge 156:ff21514d8981 483 * using it.
AnnaBridge 156:ff21514d8981 484 * @{
AnnaBridge 156:ff21514d8981 485 */
AnnaBridge 156:ff21514d8981 486 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 487 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 488 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge 156:ff21514d8981 489 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 490 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge 156:ff21514d8981 491 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 492 } while(0U)
AnnaBridge 156:ff21514d8981 493 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 494 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 495 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge 156:ff21514d8981 496 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 497 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge 156:ff21514d8981 498 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 499 } while(0U)
AnnaBridge 156:ff21514d8981 500 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 501 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 502 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge 156:ff21514d8981 503 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 504 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge 156:ff21514d8981 505 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 506 } while(0U)
AnnaBridge 156:ff21514d8981 507 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 508 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 509 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge 156:ff21514d8981 510 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 511 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge 156:ff21514d8981 512 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 513 } while(0U)
AnnaBridge 156:ff21514d8981 514 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 515 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 516 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge 156:ff21514d8981 517 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 518 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge 156:ff21514d8981 519 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 520 } while(0U)
AnnaBridge 156:ff21514d8981 521 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 522 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 523 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge 156:ff21514d8981 524 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 525 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge 156:ff21514d8981 526 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 527 } while(0U)
AnnaBridge 156:ff21514d8981 528 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 529 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 530 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge 156:ff21514d8981 531 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 532 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge 156:ff21514d8981 533 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 534 } while(0U)
AnnaBridge 156:ff21514d8981 535
AnnaBridge 156:ff21514d8981 536 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
AnnaBridge 156:ff21514d8981 537 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
AnnaBridge 156:ff21514d8981 538 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
AnnaBridge 156:ff21514d8981 539 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
AnnaBridge 156:ff21514d8981 540 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
AnnaBridge 156:ff21514d8981 541 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
AnnaBridge 163:e59c8e839560 542 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
AnnaBridge 156:ff21514d8981 543 /**
AnnaBridge 156:ff21514d8981 544 * @}
AnnaBridge 156:ff21514d8981 545 */
AnnaBridge 156:ff21514d8981 546
AnnaBridge 156:ff21514d8981 547 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge 156:ff21514d8981 548 * @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge 156:ff21514d8981 549 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 156:ff21514d8981 550 * is disabled and the application software has to enable this clock before
AnnaBridge 156:ff21514d8981 551 * using it.
AnnaBridge 156:ff21514d8981 552 * @{
AnnaBridge 156:ff21514d8981 553 */
AnnaBridge 156:ff21514d8981 554 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
AnnaBridge 156:ff21514d8981 555 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
AnnaBridge 156:ff21514d8981 556 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
AnnaBridge 156:ff21514d8981 557 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
AnnaBridge 156:ff21514d8981 558 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
AnnaBridge 156:ff21514d8981 559 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
AnnaBridge 156:ff21514d8981 560 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
AnnaBridge 156:ff21514d8981 561
AnnaBridge 156:ff21514d8981 562 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
AnnaBridge 156:ff21514d8981 563 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
AnnaBridge 156:ff21514d8981 564 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
AnnaBridge 156:ff21514d8981 565 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
AnnaBridge 156:ff21514d8981 566 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
AnnaBridge 156:ff21514d8981 567 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
AnnaBridge 163:e59c8e839560 568 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
AnnaBridge 156:ff21514d8981 569 /**
AnnaBridge 156:ff21514d8981 570 * @}
AnnaBridge 163:e59c8e839560 571 */
AnnaBridge 163:e59c8e839560 572
AnnaBridge 156:ff21514d8981 573 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge 156:ff21514d8981 574 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge 156:ff21514d8981 575 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 163:e59c8e839560 576 * is disabled and the application software has to enable this clock before
AnnaBridge 156:ff21514d8981 577 * using it.
AnnaBridge 156:ff21514d8981 578 * @{
AnnaBridge 156:ff21514d8981 579 */
AnnaBridge 156:ff21514d8981 580 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 581 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 582 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge 156:ff21514d8981 583 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 584 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge 156:ff21514d8981 585 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 586 } while(0U)
AnnaBridge 156:ff21514d8981 587 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 588 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 589 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge 156:ff21514d8981 590 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 591 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge 156:ff21514d8981 592 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 593 } while(0U)
AnnaBridge 156:ff21514d8981 594 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 595 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 596 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
AnnaBridge 156:ff21514d8981 597 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 598 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
AnnaBridge 156:ff21514d8981 599 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 600 } while(0U)
AnnaBridge 156:ff21514d8981 601 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 602 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 603 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge 156:ff21514d8981 604 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 605 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge 156:ff21514d8981 606 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 607 } while(0U)
AnnaBridge 156:ff21514d8981 608 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 609 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 610 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge 156:ff21514d8981 611 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 612 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge 156:ff21514d8981 613 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 614 } while(0U)
AnnaBridge 156:ff21514d8981 615 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 616 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 617 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge 156:ff21514d8981 618 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 619 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge 156:ff21514d8981 620 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 621 } while(0U)
AnnaBridge 156:ff21514d8981 622 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 623 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 624 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
AnnaBridge 156:ff21514d8981 625 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 626 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
AnnaBridge 156:ff21514d8981 627 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 628 } while(0U)
AnnaBridge 156:ff21514d8981 629 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
AnnaBridge 156:ff21514d8981 630 __IO uint32_t tmpreg = 0x00U; \
AnnaBridge 156:ff21514d8981 631 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
AnnaBridge 156:ff21514d8981 632 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 156:ff21514d8981 633 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
AnnaBridge 156:ff21514d8981 634 UNUSED(tmpreg); \
AnnaBridge 156:ff21514d8981 635 } while(0U)
AnnaBridge 156:ff21514d8981 636
AnnaBridge 156:ff21514d8981 637 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
AnnaBridge 156:ff21514d8981 638 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
AnnaBridge 156:ff21514d8981 639 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
AnnaBridge 156:ff21514d8981 640 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
AnnaBridge 156:ff21514d8981 641 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
AnnaBridge 156:ff21514d8981 642 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
AnnaBridge 156:ff21514d8981 643 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
AnnaBridge 156:ff21514d8981 644 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
AnnaBridge 156:ff21514d8981 645 /**
AnnaBridge 156:ff21514d8981 646 * @}
AnnaBridge 156:ff21514d8981 647 */
AnnaBridge 156:ff21514d8981 648
AnnaBridge 156:ff21514d8981 649 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge 156:ff21514d8981 650 * @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge 156:ff21514d8981 651 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 156:ff21514d8981 652 * is disabled and the application software has to enable this clock before
AnnaBridge 156:ff21514d8981 653 * using it.
AnnaBridge 156:ff21514d8981 654 * @{
AnnaBridge 156:ff21514d8981 655 */
AnnaBridge 156:ff21514d8981 656 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
AnnaBridge 156:ff21514d8981 657 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
AnnaBridge 156:ff21514d8981 658 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
AnnaBridge 156:ff21514d8981 659 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
AnnaBridge 156:ff21514d8981 660 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
AnnaBridge 156:ff21514d8981 661 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
AnnaBridge 156:ff21514d8981 662 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
AnnaBridge 163:e59c8e839560 663 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
AnnaBridge 156:ff21514d8981 664
AnnaBridge 156:ff21514d8981 665 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
AnnaBridge 156:ff21514d8981 666 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
AnnaBridge 156:ff21514d8981 667 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
AnnaBridge 156:ff21514d8981 668 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
AnnaBridge 156:ff21514d8981 669 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
AnnaBridge 156:ff21514d8981 670 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
AnnaBridge 156:ff21514d8981 671 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
AnnaBridge 163:e59c8e839560 672 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
AnnaBridge 156:ff21514d8981 673 /**
AnnaBridge 156:ff21514d8981 674 * @}
AnnaBridge 163:e59c8e839560 675 */
AnnaBridge 163:e59c8e839560 676
AnnaBridge 163:e59c8e839560 677 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge 156:ff21514d8981 678 * @brief Force or release AHB1 peripheral reset.
AnnaBridge 156:ff21514d8981 679 * @{
AnnaBridge 163:e59c8e839560 680 */
AnnaBridge 156:ff21514d8981 681 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
AnnaBridge 156:ff21514d8981 682 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
AnnaBridge 156:ff21514d8981 683 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
AnnaBridge 156:ff21514d8981 684 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
AnnaBridge 156:ff21514d8981 685 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
AnnaBridge 156:ff21514d8981 686 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
AnnaBridge 156:ff21514d8981 687 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
AnnaBridge 156:ff21514d8981 688
AnnaBridge 156:ff21514d8981 689 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
AnnaBridge 156:ff21514d8981 690 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
AnnaBridge 156:ff21514d8981 691 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
AnnaBridge 156:ff21514d8981 692 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
AnnaBridge 156:ff21514d8981 693 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
AnnaBridge 156:ff21514d8981 694 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
AnnaBridge 156:ff21514d8981 695 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
AnnaBridge 156:ff21514d8981 696 /**
AnnaBridge 156:ff21514d8981 697 * @}
AnnaBridge 156:ff21514d8981 698 */
AnnaBridge 156:ff21514d8981 699
AnnaBridge 163:e59c8e839560 700 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge 156:ff21514d8981 701 * @brief Force or release APB1 peripheral reset.
AnnaBridge 156:ff21514d8981 702 * @{
AnnaBridge 156:ff21514d8981 703 */
AnnaBridge 163:e59c8e839560 704 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
AnnaBridge 156:ff21514d8981 705 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
AnnaBridge 156:ff21514d8981 706 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
AnnaBridge 156:ff21514d8981 707 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
AnnaBridge 156:ff21514d8981 708 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
AnnaBridge 156:ff21514d8981 709 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
AnnaBridge 156:ff21514d8981 710 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
AnnaBridge 156:ff21514d8981 711 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
AnnaBridge 156:ff21514d8981 712
AnnaBridge 163:e59c8e839560 713 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
AnnaBridge 156:ff21514d8981 714 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
AnnaBridge 156:ff21514d8981 715 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
AnnaBridge 156:ff21514d8981 716 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
AnnaBridge 156:ff21514d8981 717 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
AnnaBridge 156:ff21514d8981 718 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
AnnaBridge 156:ff21514d8981 719 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
AnnaBridge 156:ff21514d8981 720 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
AnnaBridge 156:ff21514d8981 721 /**
AnnaBridge 156:ff21514d8981 722 * @}
AnnaBridge 156:ff21514d8981 723 */
AnnaBridge 156:ff21514d8981 724
AnnaBridge 163:e59c8e839560 725 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge 156:ff21514d8981 726 * @brief Force or release APB2 peripheral reset.
AnnaBridge 156:ff21514d8981 727 * @{
AnnaBridge 156:ff21514d8981 728 */
AnnaBridge 163:e59c8e839560 729 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
AnnaBridge 156:ff21514d8981 730 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
AnnaBridge 156:ff21514d8981 731 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
AnnaBridge 156:ff21514d8981 732 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
AnnaBridge 156:ff21514d8981 733 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
AnnaBridge 156:ff21514d8981 734 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
AnnaBridge 156:ff21514d8981 735 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
AnnaBridge 156:ff21514d8981 736 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
AnnaBridge 156:ff21514d8981 737 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
AnnaBridge 156:ff21514d8981 738
AnnaBridge 156:ff21514d8981 739 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
AnnaBridge 156:ff21514d8981 740 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
AnnaBridge 156:ff21514d8981 741 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
AnnaBridge 156:ff21514d8981 742 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
AnnaBridge 156:ff21514d8981 743 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
AnnaBridge 156:ff21514d8981 744 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
AnnaBridge 156:ff21514d8981 745 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
AnnaBridge 156:ff21514d8981 746 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
AnnaBridge 156:ff21514d8981 747 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
AnnaBridge 156:ff21514d8981 748 /**
AnnaBridge 156:ff21514d8981 749 * @}
AnnaBridge 156:ff21514d8981 750 */
AnnaBridge 156:ff21514d8981 751
AnnaBridge 163:e59c8e839560 752 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge 156:ff21514d8981 753 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 156:ff21514d8981 754 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 156:ff21514d8981 755 * power consumption.
AnnaBridge 156:ff21514d8981 756 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 156:ff21514d8981 757 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 156:ff21514d8981 758 * @{
AnnaBridge 156:ff21514d8981 759 */
AnnaBridge 156:ff21514d8981 760 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
AnnaBridge 156:ff21514d8981 761 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
AnnaBridge 156:ff21514d8981 762 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
AnnaBridge 156:ff21514d8981 763 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
AnnaBridge 156:ff21514d8981 764 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
AnnaBridge 156:ff21514d8981 765 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
AnnaBridge 156:ff21514d8981 766
AnnaBridge 156:ff21514d8981 767 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
AnnaBridge 156:ff21514d8981 768 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
AnnaBridge 156:ff21514d8981 769 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
AnnaBridge 156:ff21514d8981 770 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
AnnaBridge 156:ff21514d8981 771 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
AnnaBridge 156:ff21514d8981 772 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
AnnaBridge 156:ff21514d8981 773 /**
AnnaBridge 156:ff21514d8981 774 * @}
AnnaBridge 156:ff21514d8981 775 */
AnnaBridge 156:ff21514d8981 776
AnnaBridge 156:ff21514d8981 777 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge 156:ff21514d8981 778 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 156:ff21514d8981 779 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 156:ff21514d8981 780 * power consumption.
AnnaBridge 156:ff21514d8981 781 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 156:ff21514d8981 782 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 156:ff21514d8981 783 * @{
AnnaBridge 156:ff21514d8981 784 */
AnnaBridge 156:ff21514d8981 785 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
AnnaBridge 156:ff21514d8981 786 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
AnnaBridge 156:ff21514d8981 787 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
AnnaBridge 156:ff21514d8981 788 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
AnnaBridge 156:ff21514d8981 789 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
AnnaBridge 156:ff21514d8981 790 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
AnnaBridge 156:ff21514d8981 791 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
AnnaBridge 156:ff21514d8981 792
AnnaBridge 156:ff21514d8981 793 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
AnnaBridge 156:ff21514d8981 794 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
AnnaBridge 156:ff21514d8981 795 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
AnnaBridge 156:ff21514d8981 796 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
AnnaBridge 156:ff21514d8981 797 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
AnnaBridge 156:ff21514d8981 798 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
AnnaBridge 156:ff21514d8981 799 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
AnnaBridge 156:ff21514d8981 800 /**
AnnaBridge 156:ff21514d8981 801 * @}
AnnaBridge 156:ff21514d8981 802 */
AnnaBridge 156:ff21514d8981 803
AnnaBridge 156:ff21514d8981 804 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge 156:ff21514d8981 805 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 156:ff21514d8981 806 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 156:ff21514d8981 807 * power consumption.
AnnaBridge 156:ff21514d8981 808 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 156:ff21514d8981 809 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 156:ff21514d8981 810 * @{
AnnaBridge 156:ff21514d8981 811 */
AnnaBridge 156:ff21514d8981 812 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
AnnaBridge 156:ff21514d8981 813 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
AnnaBridge 156:ff21514d8981 814 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
AnnaBridge 156:ff21514d8981 815 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
AnnaBridge 156:ff21514d8981 816 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
AnnaBridge 156:ff21514d8981 817 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
AnnaBridge 156:ff21514d8981 818 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
AnnaBridge 156:ff21514d8981 819 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
AnnaBridge 156:ff21514d8981 820
AnnaBridge 156:ff21514d8981 821 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
AnnaBridge 156:ff21514d8981 822 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
AnnaBridge 156:ff21514d8981 823 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
AnnaBridge 156:ff21514d8981 824 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
AnnaBridge 156:ff21514d8981 825 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
AnnaBridge 156:ff21514d8981 826 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
AnnaBridge 156:ff21514d8981 827 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
AnnaBridge 156:ff21514d8981 828 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
AnnaBridge 156:ff21514d8981 829 /**
AnnaBridge 156:ff21514d8981 830 * @}
AnnaBridge 156:ff21514d8981 831 */
AnnaBridge 156:ff21514d8981 832
AnnaBridge 156:ff21514d8981 833 /** @defgroup RCC_HSI_Configuration HSI Configuration
AnnaBridge 163:e59c8e839560 834 * @{
AnnaBridge 163:e59c8e839560 835 */
AnnaBridge 163:e59c8e839560 836
AnnaBridge 156:ff21514d8981 837 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
AnnaBridge 156:ff21514d8981 838 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge 156:ff21514d8981 839 * It is used (enabled by hardware) as system clock source after startup
AnnaBridge 156:ff21514d8981 840 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
AnnaBridge 156:ff21514d8981 841 * of the HSE used directly or indirectly as system clock (if the Clock
AnnaBridge 163:e59c8e839560 842 * Security System CSS is enabled).
AnnaBridge 156:ff21514d8981 843 * @note HSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge 163:e59c8e839560 844 * you have to select another source of the system clock then stop the HSI.
AnnaBridge 156:ff21514d8981 845 * @note After enabling the HSI, the application software should wait on HSIRDY
AnnaBridge 156:ff21514d8981 846 * flag to be set indicating that HSI clock is stable and can be used as
AnnaBridge 163:e59c8e839560 847 * system clock source.
AnnaBridge 156:ff21514d8981 848 * This parameter can be: ENABLE or DISABLE.
AnnaBridge 156:ff21514d8981 849 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge 163:e59c8e839560 850 * clock cycles.
AnnaBridge 156:ff21514d8981 851 */
AnnaBridge 156:ff21514d8981 852 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
AnnaBridge 156:ff21514d8981 853 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
AnnaBridge 156:ff21514d8981 854
AnnaBridge 156:ff21514d8981 855 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
AnnaBridge 156:ff21514d8981 856 * @note The calibration is used to compensate for the variations in voltage
AnnaBridge 156:ff21514d8981 857 * and temperature that influence the frequency of the internal HSI RC.
AnnaBridge 163:e59c8e839560 858 * @param __HSICalibrationValue__ specifies the calibration trimming value.
AnnaBridge 156:ff21514d8981 859 * (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge 156:ff21514d8981 860 * This parameter must be a number between 0 and 0x1F.
AnnaBridge 156:ff21514d8981 861 */
AnnaBridge 156:ff21514d8981 862 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
AnnaBridge 163:e59c8e839560 863 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
AnnaBridge 156:ff21514d8981 864 /**
AnnaBridge 156:ff21514d8981 865 * @}
AnnaBridge 156:ff21514d8981 866 */
AnnaBridge 156:ff21514d8981 867
AnnaBridge 156:ff21514d8981 868 /** @defgroup RCC_LSI_Configuration LSI Configuration
AnnaBridge 163:e59c8e839560 869 * @{
AnnaBridge 163:e59c8e839560 870 */
AnnaBridge 156:ff21514d8981 871
AnnaBridge 156:ff21514d8981 872 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
AnnaBridge 163:e59c8e839560 873 * @note After enabling the LSI, the application software should wait on
AnnaBridge 156:ff21514d8981 874 * LSIRDY flag to be set indicating that LSI clock is stable and can
AnnaBridge 156:ff21514d8981 875 * be used to clock the IWDG and/or the RTC.
AnnaBridge 156:ff21514d8981 876 * @note LSI can not be disabled if the IWDG is running.
AnnaBridge 156:ff21514d8981 877 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
AnnaBridge 163:e59c8e839560 878 * clock cycles.
AnnaBridge 156:ff21514d8981 879 */
AnnaBridge 156:ff21514d8981 880 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
AnnaBridge 156:ff21514d8981 881 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
AnnaBridge 156:ff21514d8981 882 /**
AnnaBridge 156:ff21514d8981 883 * @}
AnnaBridge 156:ff21514d8981 884 */
AnnaBridge 156:ff21514d8981 885
AnnaBridge 156:ff21514d8981 886 /** @defgroup RCC_HSE_Configuration HSE Configuration
AnnaBridge 163:e59c8e839560 887 * @{
AnnaBridge 163:e59c8e839560 888 */
AnnaBridge 156:ff21514d8981 889
AnnaBridge 156:ff21514d8981 890 /**
AnnaBridge 156:ff21514d8981 891 * @brief Macro to configure the External High Speed oscillator (HSE).
AnnaBridge 163:e59c8e839560 892 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
AnnaBridge 156:ff21514d8981 893 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
AnnaBridge 156:ff21514d8981 894 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
AnnaBridge 156:ff21514d8981 895 * software should wait on HSERDY flag to be set indicating that HSE clock
AnnaBridge 156:ff21514d8981 896 * is stable and can be used to clock the PLL and/or system clock.
AnnaBridge 156:ff21514d8981 897 * @note HSE state can not be changed if it is used directly or through the
AnnaBridge 156:ff21514d8981 898 * PLL as system clock. In this case, you have to select another source
AnnaBridge 156:ff21514d8981 899 * of the system clock then change the HSE state (ex. disable it).
AnnaBridge 163:e59c8e839560 900 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge 156:ff21514d8981 901 * @note This function reset the CSSON bit, so if the clock security system(CSS)
AnnaBridge 156:ff21514d8981 902 * was previously enabled you have to enable it again after calling this
AnnaBridge 163:e59c8e839560 903 * function.
AnnaBridge 163:e59c8e839560 904 * @param __STATE__ specifies the new state of the HSE.
AnnaBridge 156:ff21514d8981 905 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 906 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
AnnaBridge 156:ff21514d8981 907 * 6 HSE oscillator clock cycles.
AnnaBridge 156:ff21514d8981 908 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
AnnaBridge 156:ff21514d8981 909 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
AnnaBridge 156:ff21514d8981 910 */
AnnaBridge 156:ff21514d8981 911 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
AnnaBridge 156:ff21514d8981 912 do { \
AnnaBridge 156:ff21514d8981 913 if ((__STATE__) == RCC_HSE_ON) \
AnnaBridge 156:ff21514d8981 914 { \
AnnaBridge 156:ff21514d8981 915 SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 156:ff21514d8981 916 } \
AnnaBridge 156:ff21514d8981 917 else if ((__STATE__) == RCC_HSE_BYPASS) \
AnnaBridge 156:ff21514d8981 918 { \
AnnaBridge 156:ff21514d8981 919 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 156:ff21514d8981 920 SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 156:ff21514d8981 921 } \
AnnaBridge 156:ff21514d8981 922 else \
AnnaBridge 156:ff21514d8981 923 { \
AnnaBridge 156:ff21514d8981 924 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 156:ff21514d8981 925 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 156:ff21514d8981 926 } \
AnnaBridge 156:ff21514d8981 927 } while(0U)
AnnaBridge 156:ff21514d8981 928 /**
AnnaBridge 156:ff21514d8981 929 * @}
AnnaBridge 156:ff21514d8981 930 */
AnnaBridge 156:ff21514d8981 931
AnnaBridge 156:ff21514d8981 932 /** @defgroup RCC_LSE_Configuration LSE Configuration
AnnaBridge 163:e59c8e839560 933 * @{
AnnaBridge 156:ff21514d8981 934 */
AnnaBridge 156:ff21514d8981 935
AnnaBridge 156:ff21514d8981 936 /**
AnnaBridge 156:ff21514d8981 937 * @brief Macro to configure the External Low Speed oscillator (LSE).
AnnaBridge 163:e59c8e839560 938 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
AnnaBridge 156:ff21514d8981 939 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
AnnaBridge 156:ff21514d8981 940 * @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge 163:e59c8e839560 941 * this domain after reset, you have to enable write access using
AnnaBridge 156:ff21514d8981 942 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge 163:e59c8e839560 943 * (to be done once after reset).
AnnaBridge 156:ff21514d8981 944 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
AnnaBridge 156:ff21514d8981 945 * software should wait on LSERDY flag to be set indicating that LSE clock
AnnaBridge 156:ff21514d8981 946 * is stable and can be used to clock the RTC.
AnnaBridge 163:e59c8e839560 947 * @param __STATE__ specifies the new state of the LSE.
AnnaBridge 156:ff21514d8981 948 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 949 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
AnnaBridge 156:ff21514d8981 950 * 6 LSE oscillator clock cycles.
AnnaBridge 156:ff21514d8981 951 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
AnnaBridge 156:ff21514d8981 952 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
AnnaBridge 156:ff21514d8981 953 */
AnnaBridge 156:ff21514d8981 954 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
AnnaBridge 156:ff21514d8981 955 do { \
AnnaBridge 156:ff21514d8981 956 if((__STATE__) == RCC_LSE_ON) \
AnnaBridge 156:ff21514d8981 957 { \
AnnaBridge 156:ff21514d8981 958 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 156:ff21514d8981 959 } \
AnnaBridge 156:ff21514d8981 960 else if((__STATE__) == RCC_LSE_BYPASS) \
AnnaBridge 156:ff21514d8981 961 { \
AnnaBridge 156:ff21514d8981 962 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 156:ff21514d8981 963 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 156:ff21514d8981 964 } \
AnnaBridge 156:ff21514d8981 965 else \
AnnaBridge 156:ff21514d8981 966 { \
AnnaBridge 156:ff21514d8981 967 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 156:ff21514d8981 968 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 156:ff21514d8981 969 } \
AnnaBridge 156:ff21514d8981 970 } while(0U)
AnnaBridge 156:ff21514d8981 971 /**
AnnaBridge 156:ff21514d8981 972 * @}
AnnaBridge 156:ff21514d8981 973 */
AnnaBridge 156:ff21514d8981 974
AnnaBridge 156:ff21514d8981 975 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
AnnaBridge 163:e59c8e839560 976 * @{
AnnaBridge 156:ff21514d8981 977 */
AnnaBridge 156:ff21514d8981 978
AnnaBridge 156:ff21514d8981 979 /** @brief Macros to enable or disable the RTC clock.
AnnaBridge 156:ff21514d8981 980 * @note These macros must be used only after the RTC clock source was selected.
AnnaBridge 156:ff21514d8981 981 */
AnnaBridge 156:ff21514d8981 982 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
AnnaBridge 156:ff21514d8981 983 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
AnnaBridge 156:ff21514d8981 984
AnnaBridge 156:ff21514d8981 985 /** @brief Macros to configure the RTC clock (RTCCLK).
AnnaBridge 156:ff21514d8981 986 * @note As the RTC clock configuration bits are in the Backup domain and write
AnnaBridge 156:ff21514d8981 987 * access is denied to this domain after reset, you have to enable write
AnnaBridge 156:ff21514d8981 988 * access using the Power Backup Access macro before to configure
AnnaBridge 163:e59c8e839560 989 * the RTC clock source (to be done once after reset).
AnnaBridge 163:e59c8e839560 990 * @note Once the RTC clock is configured it can't be changed unless the
AnnaBridge 156:ff21514d8981 991 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
AnnaBridge 156:ff21514d8981 992 * a Power On Reset (POR).
AnnaBridge 163:e59c8e839560 993 * @param __RTCCLKSource__ specifies the RTC clock source.
AnnaBridge 156:ff21514d8981 994 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 995 @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.
AnnaBridge 163:e59c8e839560 996 * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
AnnaBridge 163:e59c8e839560 997 * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
AnnaBridge 163:e59c8e839560 998 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
AnnaBridge 163:e59c8e839560 999 * as RTC clock, where x:[2,31]
AnnaBridge 156:ff21514d8981 1000 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
AnnaBridge 156:ff21514d8981 1001 * work in STOP and STANDBY modes, and can be used as wake-up source.
AnnaBridge 156:ff21514d8981 1002 * However, when the HSE clock is used as RTC clock source, the RTC
AnnaBridge 163:e59c8e839560 1003 * cannot be used in STOP and STANDBY modes.
AnnaBridge 156:ff21514d8981 1004 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
AnnaBridge 156:ff21514d8981 1005 * RTC clock source).
AnnaBridge 156:ff21514d8981 1006 */
AnnaBridge 156:ff21514d8981 1007 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
AnnaBridge 156:ff21514d8981 1008 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
AnnaBridge 163:e59c8e839560 1009
AnnaBridge 156:ff21514d8981 1010 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
AnnaBridge 156:ff21514d8981 1011 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
AnnaBridge 156:ff21514d8981 1012 } while(0U)
AnnaBridge 156:ff21514d8981 1013
AnnaBridge 163:e59c8e839560 1014 /** @brief Macro to get the RTC clock source.
AnnaBridge 163:e59c8e839560 1015 * @retval The clock source can be one of the following values:
AnnaBridge 163:e59c8e839560 1016 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge 163:e59c8e839560 1017 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge 163:e59c8e839560 1018 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge 163:e59c8e839560 1019 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
AnnaBridge 163:e59c8e839560 1020 */
AnnaBridge 163:e59c8e839560 1021 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
AnnaBridge 163:e59c8e839560 1022
AnnaBridge 163:e59c8e839560 1023 /**
AnnaBridge 163:e59c8e839560 1024 * @brief Get the RTC and HSE clock divider (RTCPRE).
AnnaBridge 163:e59c8e839560 1025 * @retval Returned value can be one of the following values:
AnnaBridge 163:e59c8e839560 1026 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
AnnaBridge 163:e59c8e839560 1027 * as RTC clock, where x:[2,31]
AnnaBridge 163:e59c8e839560 1028 */
AnnaBridge 163:e59c8e839560 1029 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
AnnaBridge 163:e59c8e839560 1030
AnnaBridge 156:ff21514d8981 1031 /** @brief Macros to force or release the Backup domain reset.
AnnaBridge 156:ff21514d8981 1032 * @note This function resets the RTC peripheral (including the backup registers)
AnnaBridge 156:ff21514d8981 1033 * and the RTC clock source selection in RCC_CSR register.
AnnaBridge 163:e59c8e839560 1034 * @note The BKPSRAM is not affected by this reset.
AnnaBridge 156:ff21514d8981 1035 */
AnnaBridge 156:ff21514d8981 1036 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
AnnaBridge 156:ff21514d8981 1037 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
AnnaBridge 156:ff21514d8981 1038 /**
AnnaBridge 156:ff21514d8981 1039 * @}
AnnaBridge 156:ff21514d8981 1040 */
AnnaBridge 156:ff21514d8981 1041
AnnaBridge 156:ff21514d8981 1042 /** @defgroup RCC_PLL_Configuration PLL Configuration
AnnaBridge 163:e59c8e839560 1043 * @{
AnnaBridge 156:ff21514d8981 1044 */
AnnaBridge 156:ff21514d8981 1045
AnnaBridge 156:ff21514d8981 1046 /** @brief Macros to enable or disable the main PLL.
AnnaBridge 163:e59c8e839560 1047 * @note After enabling the main PLL, the application software should wait on
AnnaBridge 156:ff21514d8981 1048 * PLLRDY flag to be set indicating that PLL clock is stable and can
AnnaBridge 156:ff21514d8981 1049 * be used as system clock source.
AnnaBridge 156:ff21514d8981 1050 * @note The main PLL can not be disabled if it is used as system clock source
AnnaBridge 156:ff21514d8981 1051 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge 156:ff21514d8981 1052 */
AnnaBridge 156:ff21514d8981 1053 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
AnnaBridge 156:ff21514d8981 1054 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
AnnaBridge 156:ff21514d8981 1055
AnnaBridge 156:ff21514d8981 1056 /** @brief Macro to configure the PLL clock source.
AnnaBridge 156:ff21514d8981 1057 * @note This function must be used only when the main PLL is disabled.
AnnaBridge 163:e59c8e839560 1058 * @param __PLLSOURCE__ specifies the PLL entry clock source.
AnnaBridge 156:ff21514d8981 1059 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1060 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
AnnaBridge 156:ff21514d8981 1061 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
AnnaBridge 163:e59c8e839560 1062 *
AnnaBridge 156:ff21514d8981 1063 */
AnnaBridge 156:ff21514d8981 1064 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
AnnaBridge 156:ff21514d8981 1065
AnnaBridge 156:ff21514d8981 1066 /** @brief Macro to configure the PLL multiplication factor.
AnnaBridge 156:ff21514d8981 1067 * @note This function must be used only when the main PLL is disabled.
AnnaBridge 163:e59c8e839560 1068 * @param __PLLM__ specifies the division factor for PLL VCO input clock
AnnaBridge 156:ff21514d8981 1069 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge 156:ff21514d8981 1070 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge 156:ff21514d8981 1071 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge 156:ff21514d8981 1072 * of 2 MHz to limit PLL jitter.
AnnaBridge 163:e59c8e839560 1073 *
AnnaBridge 156:ff21514d8981 1074 */
AnnaBridge 156:ff21514d8981 1075 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
AnnaBridge 156:ff21514d8981 1076 /**
AnnaBridge 156:ff21514d8981 1077 * @}
AnnaBridge 156:ff21514d8981 1078 */
AnnaBridge 156:ff21514d8981 1079
AnnaBridge 156:ff21514d8981 1080 /** @defgroup RCC_Get_Clock_source Get Clock source
AnnaBridge 163:e59c8e839560 1081 * @{
AnnaBridge 156:ff21514d8981 1082 */
AnnaBridge 156:ff21514d8981 1083 /**
AnnaBridge 156:ff21514d8981 1084 * @brief Macro to configure the system clock source.
AnnaBridge 163:e59c8e839560 1085 * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
AnnaBridge 156:ff21514d8981 1086 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1087 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
AnnaBridge 156:ff21514d8981 1088 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
AnnaBridge 156:ff21514d8981 1089 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
AnnaBridge 163:e59c8e839560 1090 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
AnnaBridge 156:ff21514d8981 1091 * parameter is available only for STM32F446xx devices.
AnnaBridge 156:ff21514d8981 1092 */
AnnaBridge 156:ff21514d8981 1093 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
AnnaBridge 156:ff21514d8981 1094
AnnaBridge 156:ff21514d8981 1095 /** @brief Macro to get the clock source used as system clock.
AnnaBridge 156:ff21514d8981 1096 * @retval The clock source used as system clock. The returned value can be one
AnnaBridge 156:ff21514d8981 1097 * of the following:
AnnaBridge 156:ff21514d8981 1098 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
AnnaBridge 156:ff21514d8981 1099 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
AnnaBridge 156:ff21514d8981 1100 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
AnnaBridge 156:ff21514d8981 1101 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter
AnnaBridge 156:ff21514d8981 1102 * is available only for STM32F446xx devices.
AnnaBridge 163:e59c8e839560 1103 */
AnnaBridge 163:e59c8e839560 1104 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
AnnaBridge 156:ff21514d8981 1105
AnnaBridge 156:ff21514d8981 1106 /** @brief Macro to get the oscillator used as PLL clock source.
AnnaBridge 156:ff21514d8981 1107 * @retval The oscillator used as PLL clock source. The returned value can be one
AnnaBridge 156:ff21514d8981 1108 * of the following:
AnnaBridge 156:ff21514d8981 1109 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
AnnaBridge 156:ff21514d8981 1110 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
AnnaBridge 156:ff21514d8981 1111 */
AnnaBridge 156:ff21514d8981 1112 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
AnnaBridge 156:ff21514d8981 1113 /**
AnnaBridge 156:ff21514d8981 1114 * @}
AnnaBridge 156:ff21514d8981 1115 */
AnnaBridge 156:ff21514d8981 1116
AnnaBridge 156:ff21514d8981 1117 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
AnnaBridge 163:e59c8e839560 1118 * @{
AnnaBridge 163:e59c8e839560 1119 */
AnnaBridge 163:e59c8e839560 1120
AnnaBridge 156:ff21514d8981 1121 /** @brief Macro to configure the MCO1 clock.
AnnaBridge 156:ff21514d8981 1122 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge 156:ff21514d8981 1123 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1124 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
AnnaBridge 156:ff21514d8981 1125 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
AnnaBridge 156:ff21514d8981 1126 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
AnnaBridge 156:ff21514d8981 1127 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
AnnaBridge 156:ff21514d8981 1128 * @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge 156:ff21514d8981 1129 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1130 * @arg RCC_MCODIV_1: no division applied to MCOx clock
AnnaBridge 156:ff21514d8981 1131 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
AnnaBridge 156:ff21514d8981 1132 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
AnnaBridge 156:ff21514d8981 1133 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
AnnaBridge 156:ff21514d8981 1134 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
AnnaBridge 156:ff21514d8981 1135 */
AnnaBridge 156:ff21514d8981 1136 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge 156:ff21514d8981 1137 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
AnnaBridge 156:ff21514d8981 1138
AnnaBridge 156:ff21514d8981 1139 /** @brief Macro to configure the MCO2 clock.
AnnaBridge 156:ff21514d8981 1140 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge 156:ff21514d8981 1141 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1142 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
AnnaBridge 163:e59c8e839560 1143 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
AnnaBridge 163:e59c8e839560 1144 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
AnnaBridge 156:ff21514d8981 1145 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
AnnaBridge 156:ff21514d8981 1146 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
AnnaBridge 156:ff21514d8981 1147 * @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge 156:ff21514d8981 1148 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1149 * @arg RCC_MCODIV_1: no division applied to MCOx clock
AnnaBridge 156:ff21514d8981 1150 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
AnnaBridge 156:ff21514d8981 1151 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
AnnaBridge 156:ff21514d8981 1152 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
AnnaBridge 156:ff21514d8981 1153 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
AnnaBridge 156:ff21514d8981 1154 * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
AnnaBridge 156:ff21514d8981 1155 * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
AnnaBridge 156:ff21514d8981 1156 */
AnnaBridge 156:ff21514d8981 1157 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge 156:ff21514d8981 1158 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
AnnaBridge 156:ff21514d8981 1159 /**
AnnaBridge 156:ff21514d8981 1160 * @}
AnnaBridge 156:ff21514d8981 1161 */
AnnaBridge 163:e59c8e839560 1162
AnnaBridge 156:ff21514d8981 1163 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge 156:ff21514d8981 1164 * @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge 156:ff21514d8981 1165 * @{
AnnaBridge 156:ff21514d8981 1166 */
AnnaBridge 156:ff21514d8981 1167
AnnaBridge 156:ff21514d8981 1168 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
AnnaBridge 156:ff21514d8981 1169 * the selected interrupts).
AnnaBridge 163:e59c8e839560 1170 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
AnnaBridge 156:ff21514d8981 1171 * This parameter can be any combination of the following values:
AnnaBridge 156:ff21514d8981 1172 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
AnnaBridge 156:ff21514d8981 1173 * @arg RCC_IT_LSERDY: LSE ready interrupt.
AnnaBridge 156:ff21514d8981 1174 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
AnnaBridge 156:ff21514d8981 1175 * @arg RCC_IT_HSERDY: HSE ready interrupt.
AnnaBridge 156:ff21514d8981 1176 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
AnnaBridge 156:ff21514d8981 1177 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
AnnaBridge 156:ff21514d8981 1178 */
AnnaBridge 156:ff21514d8981 1179 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
AnnaBridge 156:ff21514d8981 1180
AnnaBridge 163:e59c8e839560 1181 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
AnnaBridge 156:ff21514d8981 1182 * the selected interrupts).
AnnaBridge 163:e59c8e839560 1183 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
AnnaBridge 156:ff21514d8981 1184 * This parameter can be any combination of the following values:
AnnaBridge 156:ff21514d8981 1185 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
AnnaBridge 156:ff21514d8981 1186 * @arg RCC_IT_LSERDY: LSE ready interrupt.
AnnaBridge 156:ff21514d8981 1187 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
AnnaBridge 156:ff21514d8981 1188 * @arg RCC_IT_HSERDY: HSE ready interrupt.
AnnaBridge 156:ff21514d8981 1189 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
AnnaBridge 156:ff21514d8981 1190 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
AnnaBridge 156:ff21514d8981 1191 */
AnnaBridge 156:ff21514d8981 1192 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
AnnaBridge 156:ff21514d8981 1193
AnnaBridge 156:ff21514d8981 1194 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
AnnaBridge 156:ff21514d8981 1195 * bits to clear the selected interrupt pending bits.
AnnaBridge 163:e59c8e839560 1196 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge 156:ff21514d8981 1197 * This parameter can be any combination of the following values:
AnnaBridge 156:ff21514d8981 1198 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
AnnaBridge 156:ff21514d8981 1199 * @arg RCC_IT_LSERDY: LSE ready interrupt.
AnnaBridge 156:ff21514d8981 1200 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
AnnaBridge 156:ff21514d8981 1201 * @arg RCC_IT_HSERDY: HSE ready interrupt.
AnnaBridge 156:ff21514d8981 1202 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
AnnaBridge 163:e59c8e839560 1203 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
AnnaBridge 156:ff21514d8981 1204 * @arg RCC_IT_CSS: Clock Security System interrupt
AnnaBridge 156:ff21514d8981 1205 */
AnnaBridge 156:ff21514d8981 1206 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
AnnaBridge 156:ff21514d8981 1207
AnnaBridge 156:ff21514d8981 1208 /** @brief Check the RCC's interrupt has occurred or not.
AnnaBridge 163:e59c8e839560 1209 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
AnnaBridge 156:ff21514d8981 1210 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1211 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
AnnaBridge 156:ff21514d8981 1212 * @arg RCC_IT_LSERDY: LSE ready interrupt.
AnnaBridge 156:ff21514d8981 1213 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
AnnaBridge 156:ff21514d8981 1214 * @arg RCC_IT_HSERDY: HSE ready interrupt.
AnnaBridge 156:ff21514d8981 1215 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
AnnaBridge 156:ff21514d8981 1216 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
AnnaBridge 156:ff21514d8981 1217 * @arg RCC_IT_CSS: Clock Security System interrupt
AnnaBridge 156:ff21514d8981 1218 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge 156:ff21514d8981 1219 */
AnnaBridge 156:ff21514d8981 1220 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 156:ff21514d8981 1221
AnnaBridge 163:e59c8e839560 1222 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
AnnaBridge 156:ff21514d8981 1223 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
AnnaBridge 156:ff21514d8981 1224 */
AnnaBridge 156:ff21514d8981 1225 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
AnnaBridge 156:ff21514d8981 1226
AnnaBridge 156:ff21514d8981 1227 /** @brief Check RCC flag is set or not.
AnnaBridge 163:e59c8e839560 1228 * @param __FLAG__ specifies the flag to check.
AnnaBridge 156:ff21514d8981 1229 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1230 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
AnnaBridge 156:ff21514d8981 1231 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
AnnaBridge 156:ff21514d8981 1232 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
AnnaBridge 156:ff21514d8981 1233 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
AnnaBridge 156:ff21514d8981 1234 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
AnnaBridge 156:ff21514d8981 1235 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
AnnaBridge 156:ff21514d8981 1236 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
AnnaBridge 156:ff21514d8981 1237 * @arg RCC_FLAG_PINRST: Pin reset.
AnnaBridge 156:ff21514d8981 1238 * @arg RCC_FLAG_PORRST: POR/PDR reset.
AnnaBridge 156:ff21514d8981 1239 * @arg RCC_FLAG_SFTRST: Software reset.
AnnaBridge 156:ff21514d8981 1240 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
AnnaBridge 156:ff21514d8981 1241 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
AnnaBridge 156:ff21514d8981 1242 * @arg RCC_FLAG_LPWRRST: Low Power reset.
AnnaBridge 156:ff21514d8981 1243 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 156:ff21514d8981 1244 */
AnnaBridge 156:ff21514d8981 1245 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
AnnaBridge 156:ff21514d8981 1246 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
AnnaBridge 156:ff21514d8981 1247
AnnaBridge 156:ff21514d8981 1248 /**
AnnaBridge 156:ff21514d8981 1249 * @}
AnnaBridge 156:ff21514d8981 1250 */
AnnaBridge 163:e59c8e839560 1251
AnnaBridge 156:ff21514d8981 1252 /**
AnnaBridge 156:ff21514d8981 1253 * @}
AnnaBridge 156:ff21514d8981 1254 */
AnnaBridge 156:ff21514d8981 1255
AnnaBridge 156:ff21514d8981 1256 /* Exported functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1257 /** @addtogroup RCC_Exported_Functions
AnnaBridge 156:ff21514d8981 1258 * @{
AnnaBridge 156:ff21514d8981 1259 */
AnnaBridge 156:ff21514d8981 1260
AnnaBridge 156:ff21514d8981 1261 /** @addtogroup RCC_Exported_Functions_Group1
AnnaBridge 156:ff21514d8981 1262 * @{
AnnaBridge 163:e59c8e839560 1263 */
AnnaBridge 156:ff21514d8981 1264 /* Initialization and de-initialization functions ******************************/
AnnaBridge 163:e59c8e839560 1265 HAL_StatusTypeDef HAL_RCC_DeInit(void);
AnnaBridge 156:ff21514d8981 1266 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge 156:ff21514d8981 1267 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
AnnaBridge 156:ff21514d8981 1268 /**
AnnaBridge 156:ff21514d8981 1269 * @}
AnnaBridge 156:ff21514d8981 1270 */
AnnaBridge 156:ff21514d8981 1271
AnnaBridge 156:ff21514d8981 1272 /** @addtogroup RCC_Exported_Functions_Group2
AnnaBridge 156:ff21514d8981 1273 * @{
AnnaBridge 156:ff21514d8981 1274 */
AnnaBridge 156:ff21514d8981 1275 /* Peripheral Control functions ************************************************/
AnnaBridge 156:ff21514d8981 1276 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
AnnaBridge 156:ff21514d8981 1277 void HAL_RCC_EnableCSS(void);
AnnaBridge 156:ff21514d8981 1278 void HAL_RCC_DisableCSS(void);
AnnaBridge 156:ff21514d8981 1279 uint32_t HAL_RCC_GetSysClockFreq(void);
AnnaBridge 156:ff21514d8981 1280 uint32_t HAL_RCC_GetHCLKFreq(void);
AnnaBridge 156:ff21514d8981 1281 uint32_t HAL_RCC_GetPCLK1Freq(void);
AnnaBridge 156:ff21514d8981 1282 uint32_t HAL_RCC_GetPCLK2Freq(void);
AnnaBridge 156:ff21514d8981 1283 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge 156:ff21514d8981 1284 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
AnnaBridge 156:ff21514d8981 1285
AnnaBridge 156:ff21514d8981 1286 /* CSS NMI IRQ handler */
AnnaBridge 156:ff21514d8981 1287 void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge 156:ff21514d8981 1288
AnnaBridge 163:e59c8e839560 1289 /* User Callbacks in non blocking mode (IT mode) */
AnnaBridge 156:ff21514d8981 1290 void HAL_RCC_CSSCallback(void);
AnnaBridge 156:ff21514d8981 1291
AnnaBridge 156:ff21514d8981 1292 /**
AnnaBridge 156:ff21514d8981 1293 * @}
AnnaBridge 156:ff21514d8981 1294 */
AnnaBridge 156:ff21514d8981 1295
AnnaBridge 156:ff21514d8981 1296 /**
AnnaBridge 156:ff21514d8981 1297 * @}
AnnaBridge 156:ff21514d8981 1298 */
AnnaBridge 156:ff21514d8981 1299
AnnaBridge 156:ff21514d8981 1300 /* Private types -------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1301 /* Private variables ---------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1302 /* Private constants ---------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1303 /** @defgroup RCC_Private_Constants RCC Private Constants
AnnaBridge 156:ff21514d8981 1304 * @{
AnnaBridge 156:ff21514d8981 1305 */
AnnaBridge 156:ff21514d8981 1306
AnnaBridge 156:ff21514d8981 1307 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
AnnaBridge 156:ff21514d8981 1308 * @brief RCC registers bit address in the alias region
AnnaBridge 156:ff21514d8981 1309 * @{
AnnaBridge 156:ff21514d8981 1310 */
AnnaBridge 156:ff21514d8981 1311 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
AnnaBridge 163:e59c8e839560 1312 /* --- CR Register --- */
AnnaBridge 156:ff21514d8981 1313 /* Alias word address of HSION bit */
AnnaBridge 156:ff21514d8981 1314 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
AnnaBridge 156:ff21514d8981 1315 #define RCC_HSION_BIT_NUMBER 0x00U
AnnaBridge 156:ff21514d8981 1316 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
AnnaBridge 156:ff21514d8981 1317 /* Alias word address of CSSON bit */
AnnaBridge 156:ff21514d8981 1318 #define RCC_CSSON_BIT_NUMBER 0x13U
AnnaBridge 156:ff21514d8981 1319 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
AnnaBridge 156:ff21514d8981 1320 /* Alias word address of PLLON bit */
AnnaBridge 156:ff21514d8981 1321 #define RCC_PLLON_BIT_NUMBER 0x18U
AnnaBridge 156:ff21514d8981 1322 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
AnnaBridge 156:ff21514d8981 1323
AnnaBridge 163:e59c8e839560 1324 /* --- BDCR Register --- */
AnnaBridge 156:ff21514d8981 1325 /* Alias word address of RTCEN bit */
AnnaBridge 156:ff21514d8981 1326 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
AnnaBridge 156:ff21514d8981 1327 #define RCC_RTCEN_BIT_NUMBER 0x0FU
AnnaBridge 156:ff21514d8981 1328 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
AnnaBridge 156:ff21514d8981 1329 /* Alias word address of BDRST bit */
AnnaBridge 156:ff21514d8981 1330 #define RCC_BDRST_BIT_NUMBER 0x10U
AnnaBridge 156:ff21514d8981 1331 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
AnnaBridge 156:ff21514d8981 1332
AnnaBridge 163:e59c8e839560 1333 /* --- CSR Register --- */
AnnaBridge 156:ff21514d8981 1334 /* Alias word address of LSION bit */
AnnaBridge 156:ff21514d8981 1335 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
AnnaBridge 156:ff21514d8981 1336 #define RCC_LSION_BIT_NUMBER 0x00U
AnnaBridge 156:ff21514d8981 1337 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
AnnaBridge 156:ff21514d8981 1338
AnnaBridge 156:ff21514d8981 1339 /* CR register byte 3 (Bits[23:16]) base address */
AnnaBridge 156:ff21514d8981 1340 #define RCC_CR_BYTE2_ADDRESS 0x40023802U
AnnaBridge 156:ff21514d8981 1341
AnnaBridge 156:ff21514d8981 1342 /* CIR register byte 2 (Bits[15:8]) base address */
AnnaBridge 156:ff21514d8981 1343 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
AnnaBridge 156:ff21514d8981 1344
AnnaBridge 156:ff21514d8981 1345 /* CIR register byte 3 (Bits[23:16]) base address */
AnnaBridge 156:ff21514d8981 1346 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
AnnaBridge 156:ff21514d8981 1347
AnnaBridge 156:ff21514d8981 1348 /* BDCR register base address */
AnnaBridge 156:ff21514d8981 1349 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
AnnaBridge 156:ff21514d8981 1350
AnnaBridge 156:ff21514d8981 1351 #define RCC_DBP_TIMEOUT_VALUE 2U
AnnaBridge 156:ff21514d8981 1352 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge 156:ff21514d8981 1353
AnnaBridge 156:ff21514d8981 1354 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
AnnaBridge 156:ff21514d8981 1355 #define HSI_TIMEOUT_VALUE 2U /* 2 ms */
AnnaBridge 156:ff21514d8981 1356 #define LSI_TIMEOUT_VALUE 2U /* 2 ms */
AnnaBridge 163:e59c8e839560 1357 #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
AnnaBridge 156:ff21514d8981 1358
AnnaBridge 156:ff21514d8981 1359 /**
AnnaBridge 156:ff21514d8981 1360 * @}
AnnaBridge 156:ff21514d8981 1361 */
AnnaBridge 156:ff21514d8981 1362
AnnaBridge 156:ff21514d8981 1363 /**
AnnaBridge 156:ff21514d8981 1364 * @}
AnnaBridge 156:ff21514d8981 1365 */
AnnaBridge 156:ff21514d8981 1366
AnnaBridge 156:ff21514d8981 1367 /* Private macros ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1368 /** @defgroup RCC_Private_Macros RCC Private Macros
AnnaBridge 156:ff21514d8981 1369 * @{
AnnaBridge 156:ff21514d8981 1370 */
AnnaBridge 163:e59c8e839560 1371
AnnaBridge 156:ff21514d8981 1372 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
AnnaBridge 156:ff21514d8981 1373 * @{
AnnaBridge 163:e59c8e839560 1374 */
AnnaBridge 156:ff21514d8981 1375 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
AnnaBridge 156:ff21514d8981 1376
AnnaBridge 156:ff21514d8981 1377 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
AnnaBridge 156:ff21514d8981 1378 ((HSE) == RCC_HSE_BYPASS))
AnnaBridge 156:ff21514d8981 1379
AnnaBridge 156:ff21514d8981 1380 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
AnnaBridge 156:ff21514d8981 1381 ((LSE) == RCC_LSE_BYPASS))
AnnaBridge 156:ff21514d8981 1382
AnnaBridge 156:ff21514d8981 1383 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
AnnaBridge 156:ff21514d8981 1384
AnnaBridge 156:ff21514d8981 1385 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
AnnaBridge 156:ff21514d8981 1386
AnnaBridge 156:ff21514d8981 1387 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
AnnaBridge 156:ff21514d8981 1388
AnnaBridge 156:ff21514d8981 1389 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
AnnaBridge 156:ff21514d8981 1390 ((SOURCE) == RCC_PLLSOURCE_HSE))
AnnaBridge 156:ff21514d8981 1391
AnnaBridge 156:ff21514d8981 1392 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
AnnaBridge 156:ff21514d8981 1393 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
AnnaBridge 156:ff21514d8981 1394 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
AnnaBridge 156:ff21514d8981 1395 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
AnnaBridge 156:ff21514d8981 1396
AnnaBridge 156:ff21514d8981 1397 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
AnnaBridge 156:ff21514d8981 1398 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
AnnaBridge 156:ff21514d8981 1399 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
AnnaBridge 156:ff21514d8981 1400 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
AnnaBridge 156:ff21514d8981 1401 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
AnnaBridge 156:ff21514d8981 1402 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
AnnaBridge 156:ff21514d8981 1403 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
AnnaBridge 156:ff21514d8981 1404 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
AnnaBridge 156:ff21514d8981 1405 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
AnnaBridge 156:ff21514d8981 1406 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
AnnaBridge 156:ff21514d8981 1407 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
AnnaBridge 156:ff21514d8981 1408 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
AnnaBridge 156:ff21514d8981 1409 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
AnnaBridge 156:ff21514d8981 1410 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
AnnaBridge 156:ff21514d8981 1411 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
AnnaBridge 156:ff21514d8981 1412 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
AnnaBridge 156:ff21514d8981 1413 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
AnnaBridge 156:ff21514d8981 1414 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
AnnaBridge 156:ff21514d8981 1415 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
AnnaBridge 156:ff21514d8981 1416 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
AnnaBridge 156:ff21514d8981 1417 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
AnnaBridge 156:ff21514d8981 1418 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
AnnaBridge 156:ff21514d8981 1419 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
AnnaBridge 156:ff21514d8981 1420 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
AnnaBridge 156:ff21514d8981 1421 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
AnnaBridge 156:ff21514d8981 1422 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
AnnaBridge 156:ff21514d8981 1423 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
AnnaBridge 156:ff21514d8981 1424 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
AnnaBridge 156:ff21514d8981 1425 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
AnnaBridge 156:ff21514d8981 1426 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
AnnaBridge 156:ff21514d8981 1427 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
AnnaBridge 156:ff21514d8981 1428 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
AnnaBridge 163:e59c8e839560 1429
AnnaBridge 156:ff21514d8981 1430 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
AnnaBridge 156:ff21514d8981 1431
AnnaBridge 156:ff21514d8981 1432 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
AnnaBridge 156:ff21514d8981 1433
AnnaBridge 156:ff21514d8981 1434 #define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
AnnaBridge 156:ff21514d8981 1435
AnnaBridge 156:ff21514d8981 1436 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
AnnaBridge 156:ff21514d8981 1437 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
AnnaBridge 156:ff21514d8981 1438 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
AnnaBridge 156:ff21514d8981 1439 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
AnnaBridge 156:ff21514d8981 1440 ((HCLK) == RCC_SYSCLK_DIV512))
AnnaBridge 156:ff21514d8981 1441
AnnaBridge 156:ff21514d8981 1442 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
AnnaBridge 156:ff21514d8981 1443
AnnaBridge 156:ff21514d8981 1444 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
AnnaBridge 156:ff21514d8981 1445 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
AnnaBridge 156:ff21514d8981 1446 ((PCLK) == RCC_HCLK_DIV16))
AnnaBridge 156:ff21514d8981 1447
AnnaBridge 156:ff21514d8981 1448 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
AnnaBridge 156:ff21514d8981 1449
AnnaBridge 156:ff21514d8981 1450 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
AnnaBridge 156:ff21514d8981 1451 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
AnnaBridge 156:ff21514d8981 1452
AnnaBridge 156:ff21514d8981 1453 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
AnnaBridge 156:ff21514d8981 1454 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
AnnaBridge 163:e59c8e839560 1455 ((DIV) == RCC_MCODIV_5))
AnnaBridge 156:ff21514d8981 1456 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
AnnaBridge 156:ff21514d8981 1457
AnnaBridge 156:ff21514d8981 1458 /**
AnnaBridge 156:ff21514d8981 1459 * @}
AnnaBridge 156:ff21514d8981 1460 */
AnnaBridge 156:ff21514d8981 1461
AnnaBridge 156:ff21514d8981 1462 /**
AnnaBridge 156:ff21514d8981 1463 * @}
AnnaBridge 156:ff21514d8981 1464 */
AnnaBridge 156:ff21514d8981 1465
AnnaBridge 156:ff21514d8981 1466 /**
AnnaBridge 156:ff21514d8981 1467 * @}
AnnaBridge 163:e59c8e839560 1468 */
AnnaBridge 156:ff21514d8981 1469
AnnaBridge 156:ff21514d8981 1470 /**
AnnaBridge 156:ff21514d8981 1471 * @}
AnnaBridge 156:ff21514d8981 1472 */
AnnaBridge 156:ff21514d8981 1473
AnnaBridge 156:ff21514d8981 1474 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 1475 }
AnnaBridge 156:ff21514d8981 1476 #endif
AnnaBridge 156:ff21514d8981 1477
AnnaBridge 156:ff21514d8981 1478 #endif /* __STM32F4xx_HAL_RCC_H */
AnnaBridge 156:ff21514d8981 1479
AnnaBridge 156:ff21514d8981 1480 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/