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mbed 2

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TARGET_B96B_F446VE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
163:e59c8e839560 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file stm32f4xx_hal_qspi.h
AnnaBridge 156:ff21514d8981 4 * @author MCD Application Team
AnnaBridge 156:ff21514d8981 5 * @brief Header file of QSPI HAL module.
AnnaBridge 156:ff21514d8981 6 ******************************************************************************
AnnaBridge 156:ff21514d8981 7 * @attention
AnnaBridge 156:ff21514d8981 8 *
AnnaBridge 156:ff21514d8981 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 156:ff21514d8981 10 *
AnnaBridge 156:ff21514d8981 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 156:ff21514d8981 12 * are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 156:ff21514d8981 14 * this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 156:ff21514d8981 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 156:ff21514d8981 17 * and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 156:ff21514d8981 19 * may be used to endorse or promote products derived from this software
AnnaBridge 156:ff21514d8981 20 * without specific prior written permission.
AnnaBridge 156:ff21514d8981 21 *
AnnaBridge 156:ff21514d8981 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 156:ff21514d8981 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 156:ff21514d8981 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 156:ff21514d8981 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 156:ff21514d8981 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 156:ff21514d8981 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 156:ff21514d8981 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 156:ff21514d8981 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 32 *
AnnaBridge 156:ff21514d8981 33 ******************************************************************************
AnnaBridge 156:ff21514d8981 34 */
AnnaBridge 156:ff21514d8981 35
AnnaBridge 156:ff21514d8981 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 156:ff21514d8981 37 #ifndef __STM32F4xx_HAL_QSPI_H
AnnaBridge 156:ff21514d8981 38 #define __STM32F4xx_HAL_QSPI_H
AnnaBridge 156:ff21514d8981 39
AnnaBridge 156:ff21514d8981 40 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 41 extern "C" {
AnnaBridge 156:ff21514d8981 42 #endif
AnnaBridge 156:ff21514d8981 43
AnnaBridge 156:ff21514d8981 44 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
AnnaBridge 156:ff21514d8981 45 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
AnnaBridge 156:ff21514d8981 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 47 #include "stm32f4xx_hal_def.h"
AnnaBridge 156:ff21514d8981 48
AnnaBridge 156:ff21514d8981 49 /** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge 156:ff21514d8981 50 * @{
AnnaBridge 156:ff21514d8981 51 */
AnnaBridge 156:ff21514d8981 52
AnnaBridge 156:ff21514d8981 53 /** @addtogroup QSPI
AnnaBridge 156:ff21514d8981 54 * @{
AnnaBridge 156:ff21514d8981 55 */
AnnaBridge 156:ff21514d8981 56
AnnaBridge 156:ff21514d8981 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 58 /** @defgroup QSPI_Exported_Types QSPI Exported Types
AnnaBridge 156:ff21514d8981 59 * @{
AnnaBridge 156:ff21514d8981 60 */
AnnaBridge 156:ff21514d8981 61
AnnaBridge 156:ff21514d8981 62 /**
AnnaBridge 156:ff21514d8981 63 * @brief QSPI Init structure definition
AnnaBridge 156:ff21514d8981 64 */
AnnaBridge 156:ff21514d8981 65
AnnaBridge 156:ff21514d8981 66 typedef struct
AnnaBridge 156:ff21514d8981 67 {
AnnaBridge 156:ff21514d8981 68 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
AnnaBridge 156:ff21514d8981 69 This parameter can be a number between 0 and 255 */
AnnaBridge 156:ff21514d8981 70
AnnaBridge 156:ff21514d8981 71 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
AnnaBridge 156:ff21514d8981 72 This parameter can be a value between 1 and 32 */
AnnaBridge 156:ff21514d8981 73
AnnaBridge 156:ff21514d8981 74 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
AnnaBridge 156:ff21514d8981 75 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
AnnaBridge 156:ff21514d8981 76 This parameter can be a value of @ref QSPI_SampleShifting */
AnnaBridge 156:ff21514d8981 77
AnnaBridge 156:ff21514d8981 78 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
AnnaBridge 156:ff21514d8981 79 required to address the flash memory. The flash capacity can be up to 4GB
AnnaBridge 156:ff21514d8981 80 (addressed using 32 bits) in indirect mode, but the addressable space in
AnnaBridge 156:ff21514d8981 81 memory-mapped mode is limited to 256MB
AnnaBridge 156:ff21514d8981 82 This parameter can be a number between 0 and 31 */
AnnaBridge 156:ff21514d8981 83
AnnaBridge 156:ff21514d8981 84 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
AnnaBridge 156:ff21514d8981 85 of clock cycles which the chip select must remain high between commands.
AnnaBridge 156:ff21514d8981 86 This parameter can be a value of @ref QSPI_ChipSelectHighTime */
AnnaBridge 156:ff21514d8981 87
AnnaBridge 156:ff21514d8981 88 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
AnnaBridge 156:ff21514d8981 89 This parameter can be a value of @ref QSPI_ClockMode */
AnnaBridge 156:ff21514d8981 90
AnnaBridge 156:ff21514d8981 91 uint32_t FlashID; /* Specifies the Flash which will be used,
AnnaBridge 156:ff21514d8981 92 This parameter can be a value of @ref QSPI_Flash_Select */
AnnaBridge 156:ff21514d8981 93
AnnaBridge 156:ff21514d8981 94 uint32_t DualFlash; /* Specifies the Dual Flash Mode State
AnnaBridge 156:ff21514d8981 95 This parameter can be a value of @ref QSPI_DualFlash_Mode */
AnnaBridge 156:ff21514d8981 96 }QSPI_InitTypeDef;
AnnaBridge 156:ff21514d8981 97
AnnaBridge 156:ff21514d8981 98 /**
AnnaBridge 156:ff21514d8981 99 * @brief HAL QSPI State structures definition
AnnaBridge 156:ff21514d8981 100 */
AnnaBridge 156:ff21514d8981 101 typedef enum
AnnaBridge 156:ff21514d8981 102 {
AnnaBridge 156:ff21514d8981 103 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
AnnaBridge 156:ff21514d8981 104 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
AnnaBridge 156:ff21514d8981 105 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
AnnaBridge 156:ff21514d8981 106 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
AnnaBridge 156:ff21514d8981 107 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
AnnaBridge 156:ff21514d8981 108 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
AnnaBridge 156:ff21514d8981 109 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
AnnaBridge 156:ff21514d8981 110 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
AnnaBridge 156:ff21514d8981 111 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
AnnaBridge 156:ff21514d8981 112 }HAL_QSPI_StateTypeDef;
AnnaBridge 156:ff21514d8981 113
AnnaBridge 156:ff21514d8981 114 /**
AnnaBridge 156:ff21514d8981 115 * @brief QSPI Handle Structure definition
AnnaBridge 156:ff21514d8981 116 */
AnnaBridge 156:ff21514d8981 117 typedef struct
AnnaBridge 156:ff21514d8981 118 {
AnnaBridge 156:ff21514d8981 119 QUADSPI_TypeDef *Instance; /* QSPI registers base address */
AnnaBridge 156:ff21514d8981 120 QSPI_InitTypeDef Init; /* QSPI communication parameters */
AnnaBridge 156:ff21514d8981 121 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
AnnaBridge 156:ff21514d8981 122 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
AnnaBridge 156:ff21514d8981 123 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
AnnaBridge 156:ff21514d8981 124 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
AnnaBridge 156:ff21514d8981 125 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
AnnaBridge 156:ff21514d8981 126 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
AnnaBridge 156:ff21514d8981 127 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
AnnaBridge 156:ff21514d8981 128 __IO HAL_LockTypeDef Lock; /* Locking object */
AnnaBridge 156:ff21514d8981 129 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
AnnaBridge 156:ff21514d8981 130 __IO uint32_t ErrorCode; /* QSPI Error code */
AnnaBridge 156:ff21514d8981 131 uint32_t Timeout; /* Timeout for the QSPI memory access */
AnnaBridge 156:ff21514d8981 132 }QSPI_HandleTypeDef;
AnnaBridge 156:ff21514d8981 133
AnnaBridge 156:ff21514d8981 134 /**
AnnaBridge 156:ff21514d8981 135 * @brief QSPI Command structure definition
AnnaBridge 156:ff21514d8981 136 */
AnnaBridge 156:ff21514d8981 137 typedef struct
AnnaBridge 156:ff21514d8981 138 {
AnnaBridge 156:ff21514d8981 139 uint32_t Instruction; /* Specifies the Instruction to be sent
AnnaBridge 156:ff21514d8981 140 This parameter can be a value (8-bit) between 0x00 and 0xFF */
AnnaBridge 156:ff21514d8981 141 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
AnnaBridge 156:ff21514d8981 142 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
AnnaBridge 156:ff21514d8981 143 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
AnnaBridge 156:ff21514d8981 144 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
AnnaBridge 156:ff21514d8981 145 uint32_t AddressSize; /* Specifies the Address Size
AnnaBridge 156:ff21514d8981 146 This parameter can be a value of @ref QSPI_AddressSize */
AnnaBridge 156:ff21514d8981 147 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
AnnaBridge 156:ff21514d8981 148 This parameter can be a value of @ref QSPI_AlternateBytesSize */
AnnaBridge 156:ff21514d8981 149 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
AnnaBridge 156:ff21514d8981 150 This parameter can be a number between 0 and 31 */
AnnaBridge 156:ff21514d8981 151 uint32_t InstructionMode; /* Specifies the Instruction Mode
AnnaBridge 156:ff21514d8981 152 This parameter can be a value of @ref QSPI_InstructionMode */
AnnaBridge 156:ff21514d8981 153 uint32_t AddressMode; /* Specifies the Address Mode
AnnaBridge 156:ff21514d8981 154 This parameter can be a value of @ref QSPI_AddressMode */
AnnaBridge 156:ff21514d8981 155 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
AnnaBridge 156:ff21514d8981 156 This parameter can be a value of @ref QSPI_AlternateBytesMode */
AnnaBridge 156:ff21514d8981 157 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
AnnaBridge 156:ff21514d8981 158 This parameter can be a value of @ref QSPI_DataMode */
AnnaBridge 156:ff21514d8981 159 uint32_t NbData; /* Specifies the number of data to transfer.
AnnaBridge 156:ff21514d8981 160 This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length
AnnaBridge 156:ff21514d8981 161 until end of memory)*/
AnnaBridge 156:ff21514d8981 162 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
AnnaBridge 156:ff21514d8981 163 This parameter can be a value of @ref QSPI_DdrMode */
AnnaBridge 156:ff21514d8981 164 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
AnnaBridge 156:ff21514d8981 165 system clock in DDR mode.
AnnaBridge 156:ff21514d8981 166 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
AnnaBridge 156:ff21514d8981 167 uint32_t SIOOMode; /* Specifies the send instruction only once mode
AnnaBridge 156:ff21514d8981 168 This parameter can be a value of @ref QSPI_SIOOMode */
AnnaBridge 156:ff21514d8981 169 }QSPI_CommandTypeDef;
AnnaBridge 156:ff21514d8981 170
AnnaBridge 156:ff21514d8981 171 /**
AnnaBridge 156:ff21514d8981 172 * @brief QSPI Auto Polling mode configuration structure definition
AnnaBridge 156:ff21514d8981 173 */
AnnaBridge 156:ff21514d8981 174 typedef struct
AnnaBridge 156:ff21514d8981 175 {
AnnaBridge 156:ff21514d8981 176 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
AnnaBridge 156:ff21514d8981 177 This parameter can be any value between 0 and 0xFFFFFFFFU */
AnnaBridge 156:ff21514d8981 178 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
AnnaBridge 156:ff21514d8981 179 This parameter can be any value between 0 and 0xFFFFFFFFU */
AnnaBridge 156:ff21514d8981 180 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
AnnaBridge 156:ff21514d8981 181 This parameter can be any value between 0 and 0xFFFFU */
AnnaBridge 156:ff21514d8981 182 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
AnnaBridge 156:ff21514d8981 183 This parameter can be any value between 1 and 4 */
AnnaBridge 156:ff21514d8981 184 uint32_t MatchMode; /* Specifies the method used for determining a match.
AnnaBridge 156:ff21514d8981 185 This parameter can be a value of @ref QSPI_MatchMode */
AnnaBridge 156:ff21514d8981 186 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
AnnaBridge 156:ff21514d8981 187 This parameter can be a value of @ref QSPI_AutomaticStop */
AnnaBridge 156:ff21514d8981 188 }QSPI_AutoPollingTypeDef;
AnnaBridge 156:ff21514d8981 189
AnnaBridge 156:ff21514d8981 190 /**
AnnaBridge 156:ff21514d8981 191 * @brief QSPI Memory Mapped mode configuration structure definition
AnnaBridge 156:ff21514d8981 192 */
AnnaBridge 156:ff21514d8981 193 typedef struct
AnnaBridge 156:ff21514d8981 194 {
AnnaBridge 156:ff21514d8981 195 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
AnnaBridge 156:ff21514d8981 196 This parameter can be any value between 0 and 0xFFFFU */
AnnaBridge 156:ff21514d8981 197 uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
AnnaBridge 156:ff21514d8981 198 This parameter can be a value of @ref QSPI_TimeOutActivation */
AnnaBridge 156:ff21514d8981 199 }QSPI_MemoryMappedTypeDef;
AnnaBridge 156:ff21514d8981 200 /**
AnnaBridge 156:ff21514d8981 201 * @}
AnnaBridge 156:ff21514d8981 202 */
AnnaBridge 156:ff21514d8981 203
AnnaBridge 156:ff21514d8981 204 /* Exported constants --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 205 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
AnnaBridge 156:ff21514d8981 206 * @{
AnnaBridge 156:ff21514d8981 207 */
AnnaBridge 156:ff21514d8981 208 /** @defgroup QSPI_ErrorCode QSPI Error Code
AnnaBridge 156:ff21514d8981 209 * @{
AnnaBridge 156:ff21514d8981 210 */
AnnaBridge 156:ff21514d8981 211 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 156:ff21514d8981 212 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
AnnaBridge 156:ff21514d8981 213 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
AnnaBridge 156:ff21514d8981 214 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
AnnaBridge 156:ff21514d8981 215 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
AnnaBridge 156:ff21514d8981 216 /**
AnnaBridge 156:ff21514d8981 217 * @}
AnnaBridge 156:ff21514d8981 218 */
AnnaBridge 156:ff21514d8981 219
AnnaBridge 156:ff21514d8981 220 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
AnnaBridge 156:ff21514d8981 221 * @{
AnnaBridge 156:ff21514d8981 222 */
AnnaBridge 156:ff21514d8981 223 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
AnnaBridge 156:ff21514d8981 224 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
AnnaBridge 156:ff21514d8981 225 /**
AnnaBridge 156:ff21514d8981 226 * @}
AnnaBridge 156:ff21514d8981 227 */
AnnaBridge 156:ff21514d8981 228
AnnaBridge 156:ff21514d8981 229 /** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
AnnaBridge 156:ff21514d8981 230 * @{
AnnaBridge 156:ff21514d8981 231 */
AnnaBridge 156:ff21514d8981 232 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
AnnaBridge 156:ff21514d8981 233 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
AnnaBridge 156:ff21514d8981 234 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
AnnaBridge 156:ff21514d8981 235 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
AnnaBridge 156:ff21514d8981 236 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
AnnaBridge 156:ff21514d8981 237 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
AnnaBridge 156:ff21514d8981 238 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
AnnaBridge 156:ff21514d8981 239 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
AnnaBridge 156:ff21514d8981 240 /**
AnnaBridge 156:ff21514d8981 241 * @}
AnnaBridge 156:ff21514d8981 242 */
AnnaBridge 156:ff21514d8981 243
AnnaBridge 156:ff21514d8981 244 /** @defgroup QSPI_ClockMode QSPI Clock Mode
AnnaBridge 156:ff21514d8981 245 * @{
AnnaBridge 156:ff21514d8981 246 */
AnnaBridge 156:ff21514d8981 247 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
AnnaBridge 156:ff21514d8981 248 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
AnnaBridge 156:ff21514d8981 249 /**
AnnaBridge 156:ff21514d8981 250 * @}
AnnaBridge 156:ff21514d8981 251 */
AnnaBridge 156:ff21514d8981 252
AnnaBridge 156:ff21514d8981 253 /** @defgroup QSPI_Flash_Select QSPI Flash Select
AnnaBridge 156:ff21514d8981 254 * @{
AnnaBridge 156:ff21514d8981 255 */
AnnaBridge 156:ff21514d8981 256 #define QSPI_FLASH_ID_1 0x00000000U
AnnaBridge 156:ff21514d8981 257 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
AnnaBridge 156:ff21514d8981 258 /**
AnnaBridge 156:ff21514d8981 259 * @}
AnnaBridge 156:ff21514d8981 260 */
AnnaBridge 156:ff21514d8981 261
AnnaBridge 156:ff21514d8981 262 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
AnnaBridge 156:ff21514d8981 263 * @{
AnnaBridge 156:ff21514d8981 264 */
AnnaBridge 156:ff21514d8981 265 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
AnnaBridge 156:ff21514d8981 266 #define QSPI_DUALFLASH_DISABLE 0x00000000U
AnnaBridge 156:ff21514d8981 267 /**
AnnaBridge 156:ff21514d8981 268 * @}
AnnaBridge 156:ff21514d8981 269 */
AnnaBridge 156:ff21514d8981 270
AnnaBridge 156:ff21514d8981 271 /** @defgroup QSPI_AddressSize QSPI Address Size
AnnaBridge 156:ff21514d8981 272 * @{
AnnaBridge 156:ff21514d8981 273 */
AnnaBridge 156:ff21514d8981 274 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
AnnaBridge 156:ff21514d8981 275 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
AnnaBridge 156:ff21514d8981 276 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
AnnaBridge 156:ff21514d8981 277 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
AnnaBridge 156:ff21514d8981 278 /**
AnnaBridge 156:ff21514d8981 279 * @}
AnnaBridge 156:ff21514d8981 280 */
AnnaBridge 156:ff21514d8981 281
AnnaBridge 156:ff21514d8981 282 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
AnnaBridge 156:ff21514d8981 283 * @{
AnnaBridge 156:ff21514d8981 284 */
AnnaBridge 156:ff21514d8981 285 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
AnnaBridge 156:ff21514d8981 286 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
AnnaBridge 156:ff21514d8981 287 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
AnnaBridge 156:ff21514d8981 288 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
AnnaBridge 156:ff21514d8981 289 /**
AnnaBridge 156:ff21514d8981 290 * @}
AnnaBridge 156:ff21514d8981 291 */
AnnaBridge 156:ff21514d8981 292
AnnaBridge 156:ff21514d8981 293 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
AnnaBridge 156:ff21514d8981 294 * @{
AnnaBridge 156:ff21514d8981 295 */
AnnaBridge 156:ff21514d8981 296 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
AnnaBridge 156:ff21514d8981 297 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
AnnaBridge 156:ff21514d8981 298 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
AnnaBridge 156:ff21514d8981 299 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
AnnaBridge 156:ff21514d8981 300 /**
AnnaBridge 156:ff21514d8981 301 * @}
AnnaBridge 156:ff21514d8981 302 */
AnnaBridge 156:ff21514d8981 303
AnnaBridge 156:ff21514d8981 304 /** @defgroup QSPI_AddressMode QSPI Address Mode
AnnaBridge 156:ff21514d8981 305 * @{
AnnaBridge 156:ff21514d8981 306 */
AnnaBridge 156:ff21514d8981 307 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
AnnaBridge 156:ff21514d8981 308 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
AnnaBridge 156:ff21514d8981 309 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
AnnaBridge 156:ff21514d8981 310 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
AnnaBridge 156:ff21514d8981 311 /**
AnnaBridge 156:ff21514d8981 312 * @}
AnnaBridge 156:ff21514d8981 313 */
AnnaBridge 156:ff21514d8981 314
AnnaBridge 156:ff21514d8981 315 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
AnnaBridge 156:ff21514d8981 316 * @{
AnnaBridge 156:ff21514d8981 317 */
AnnaBridge 156:ff21514d8981 318 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
AnnaBridge 156:ff21514d8981 319 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
AnnaBridge 156:ff21514d8981 320 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
AnnaBridge 156:ff21514d8981 321 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
AnnaBridge 156:ff21514d8981 322 /**
AnnaBridge 156:ff21514d8981 323 * @}
AnnaBridge 156:ff21514d8981 324 */
AnnaBridge 156:ff21514d8981 325
AnnaBridge 156:ff21514d8981 326 /** @defgroup QSPI_DataMode QSPI Data Mode
AnnaBridge 156:ff21514d8981 327 * @{
AnnaBridge 156:ff21514d8981 328 */
AnnaBridge 156:ff21514d8981 329 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/
AnnaBridge 156:ff21514d8981 330 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
AnnaBridge 156:ff21514d8981 331 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
AnnaBridge 156:ff21514d8981 332 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
AnnaBridge 156:ff21514d8981 333 /**
AnnaBridge 156:ff21514d8981 334 * @}
AnnaBridge 156:ff21514d8981 335 */
AnnaBridge 156:ff21514d8981 336
AnnaBridge 156:ff21514d8981 337 /** @defgroup QSPI_DdrMode QSPI Ddr Mode
AnnaBridge 156:ff21514d8981 338 * @{
AnnaBridge 156:ff21514d8981 339 */
AnnaBridge 156:ff21514d8981 340 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
AnnaBridge 156:ff21514d8981 341 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
AnnaBridge 156:ff21514d8981 342 /**
AnnaBridge 156:ff21514d8981 343 * @}
AnnaBridge 156:ff21514d8981 344 */
AnnaBridge 156:ff21514d8981 345
AnnaBridge 156:ff21514d8981 346 /** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
AnnaBridge 156:ff21514d8981 347 * @{
AnnaBridge 156:ff21514d8981 348 */
AnnaBridge 156:ff21514d8981 349 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
AnnaBridge 156:ff21514d8981 350 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
AnnaBridge 156:ff21514d8981 351 /**
AnnaBridge 156:ff21514d8981 352 * @}
AnnaBridge 156:ff21514d8981 353 */
AnnaBridge 156:ff21514d8981 354
AnnaBridge 156:ff21514d8981 355 /** @defgroup QSPI_SIOOMode QSPI SIOO Mode
AnnaBridge 156:ff21514d8981 356 * @{
AnnaBridge 156:ff21514d8981 357 */
AnnaBridge 156:ff21514d8981 358 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
AnnaBridge 156:ff21514d8981 359 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
AnnaBridge 156:ff21514d8981 360 /**
AnnaBridge 156:ff21514d8981 361 * @}
AnnaBridge 156:ff21514d8981 362 */
AnnaBridge 156:ff21514d8981 363
AnnaBridge 156:ff21514d8981 364 /** @defgroup QSPI_MatchMode QSPI Match Mode
AnnaBridge 156:ff21514d8981 365 * @{
AnnaBridge 156:ff21514d8981 366 */
AnnaBridge 156:ff21514d8981 367 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
AnnaBridge 156:ff21514d8981 368 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
AnnaBridge 156:ff21514d8981 369 /**
AnnaBridge 156:ff21514d8981 370 * @}
AnnaBridge 156:ff21514d8981 371 */
AnnaBridge 156:ff21514d8981 372
AnnaBridge 156:ff21514d8981 373 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
AnnaBridge 156:ff21514d8981 374 * @{
AnnaBridge 156:ff21514d8981 375 */
AnnaBridge 156:ff21514d8981 376 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
AnnaBridge 156:ff21514d8981 377 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
AnnaBridge 156:ff21514d8981 378 /**
AnnaBridge 156:ff21514d8981 379 * @}
AnnaBridge 156:ff21514d8981 380 */
AnnaBridge 156:ff21514d8981 381
AnnaBridge 156:ff21514d8981 382 /** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
AnnaBridge 156:ff21514d8981 383 * @{
AnnaBridge 156:ff21514d8981 384 */
AnnaBridge 156:ff21514d8981 385 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
AnnaBridge 156:ff21514d8981 386 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
AnnaBridge 156:ff21514d8981 387 /**
AnnaBridge 156:ff21514d8981 388 * @}
AnnaBridge 156:ff21514d8981 389 */
AnnaBridge 156:ff21514d8981 390
AnnaBridge 156:ff21514d8981 391 /** @defgroup QSPI_Flags QSPI Flags
AnnaBridge 156:ff21514d8981 392 * @{
AnnaBridge 156:ff21514d8981 393 */
AnnaBridge 156:ff21514d8981 394 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
AnnaBridge 156:ff21514d8981 395 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
AnnaBridge 156:ff21514d8981 396 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
AnnaBridge 156:ff21514d8981 397 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
AnnaBridge 156:ff21514d8981 398 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
AnnaBridge 156:ff21514d8981 399 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
AnnaBridge 156:ff21514d8981 400 /**
AnnaBridge 156:ff21514d8981 401 * @}
AnnaBridge 156:ff21514d8981 402 */
AnnaBridge 156:ff21514d8981 403
AnnaBridge 156:ff21514d8981 404 /** @defgroup QSPI_Interrupts QSPI Interrupts
AnnaBridge 156:ff21514d8981 405 * @{
AnnaBridge 156:ff21514d8981 406 */
AnnaBridge 156:ff21514d8981 407 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
AnnaBridge 156:ff21514d8981 408 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
AnnaBridge 156:ff21514d8981 409 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
AnnaBridge 156:ff21514d8981 410 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
AnnaBridge 156:ff21514d8981 411 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
AnnaBridge 156:ff21514d8981 412 /**
AnnaBridge 156:ff21514d8981 413 * @}
AnnaBridge 156:ff21514d8981 414 */
AnnaBridge 156:ff21514d8981 415
AnnaBridge 156:ff21514d8981 416 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
AnnaBridge 156:ff21514d8981 417 * @{
AnnaBridge 156:ff21514d8981 418 */
AnnaBridge 156:ff21514d8981 419 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
AnnaBridge 156:ff21514d8981 420 /**
AnnaBridge 156:ff21514d8981 421 * @}
AnnaBridge 156:ff21514d8981 422 */
AnnaBridge 156:ff21514d8981 423
AnnaBridge 156:ff21514d8981 424 /**
AnnaBridge 156:ff21514d8981 425 * @}
AnnaBridge 156:ff21514d8981 426 */
AnnaBridge 156:ff21514d8981 427
AnnaBridge 156:ff21514d8981 428 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 429 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
AnnaBridge 156:ff21514d8981 430 * @{
AnnaBridge 156:ff21514d8981 431 */
AnnaBridge 156:ff21514d8981 432
AnnaBridge 156:ff21514d8981 433 /** @brief Reset QSPI handle state
AnnaBridge 163:e59c8e839560 434 * @param __HANDLE__ QSPI handle.
AnnaBridge 156:ff21514d8981 435 * @retval None
AnnaBridge 156:ff21514d8981 436 */
AnnaBridge 156:ff21514d8981 437 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
AnnaBridge 156:ff21514d8981 438
AnnaBridge 156:ff21514d8981 439 /** @brief Enable QSPI
AnnaBridge 163:e59c8e839560 440 * @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge 156:ff21514d8981 441 * @retval None
AnnaBridge 156:ff21514d8981 442 */
AnnaBridge 156:ff21514d8981 443 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
AnnaBridge 156:ff21514d8981 444
AnnaBridge 156:ff21514d8981 445 /** @brief Disable QSPI
AnnaBridge 163:e59c8e839560 446 * @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge 156:ff21514d8981 447 * @retval None
AnnaBridge 156:ff21514d8981 448 */
AnnaBridge 156:ff21514d8981 449 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
AnnaBridge 156:ff21514d8981 450
AnnaBridge 156:ff21514d8981 451 /** @brief Enables the specified QSPI interrupt.
AnnaBridge 163:e59c8e839560 452 * @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge 163:e59c8e839560 453 * @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
AnnaBridge 156:ff21514d8981 454 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 455 * @arg QSPI_IT_TO: QSPI Time out interrupt
AnnaBridge 156:ff21514d8981 456 * @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge 156:ff21514d8981 457 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge 156:ff21514d8981 458 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge 156:ff21514d8981 459 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge 156:ff21514d8981 460 * @retval None
AnnaBridge 156:ff21514d8981 461 */
AnnaBridge 156:ff21514d8981 462 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
AnnaBridge 156:ff21514d8981 463
AnnaBridge 156:ff21514d8981 464
AnnaBridge 156:ff21514d8981 465 /** @brief Disables the specified QSPI interrupt.
AnnaBridge 163:e59c8e839560 466 * @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge 163:e59c8e839560 467 * @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
AnnaBridge 156:ff21514d8981 468 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 469 * @arg QSPI_IT_TO: QSPI Timeout interrupt
AnnaBridge 156:ff21514d8981 470 * @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge 156:ff21514d8981 471 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge 156:ff21514d8981 472 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge 156:ff21514d8981 473 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge 156:ff21514d8981 474 * @retval None
AnnaBridge 156:ff21514d8981 475 */
AnnaBridge 156:ff21514d8981 476 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
AnnaBridge 156:ff21514d8981 477
AnnaBridge 156:ff21514d8981 478 /** @brief Checks whether the specified QSPI interrupt source is enabled.
AnnaBridge 163:e59c8e839560 479 * @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge 163:e59c8e839560 480 * @param __INTERRUPT__ specifies the QSPI interrupt source to check.
AnnaBridge 156:ff21514d8981 481 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 482 * @arg QSPI_IT_TO: QSPI Time out interrupt
AnnaBridge 156:ff21514d8981 483 * @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge 156:ff21514d8981 484 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge 156:ff21514d8981 485 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge 156:ff21514d8981 486 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge 156:ff21514d8981 487 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge 156:ff21514d8981 488 */
AnnaBridge 156:ff21514d8981 489 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 156:ff21514d8981 490
AnnaBridge 156:ff21514d8981 491 /**
AnnaBridge 156:ff21514d8981 492 * @brief Get the selected QSPI's flag status.
AnnaBridge 163:e59c8e839560 493 * @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge 163:e59c8e839560 494 * @param __FLAG__ specifies the QSPI flag to check.
AnnaBridge 156:ff21514d8981 495 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 496 * @arg QSPI_FLAG_BUSY: QSPI Busy flag
AnnaBridge 156:ff21514d8981 497 * @arg QSPI_FLAG_TO: QSPI Time out flag
AnnaBridge 156:ff21514d8981 498 * @arg QSPI_FLAG_SM: QSPI Status match flag
AnnaBridge 156:ff21514d8981 499 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
AnnaBridge 156:ff21514d8981 500 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
AnnaBridge 156:ff21514d8981 501 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
AnnaBridge 156:ff21514d8981 502 * @retval None
AnnaBridge 156:ff21514d8981 503 */
AnnaBridge 156:ff21514d8981 504 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U)
AnnaBridge 156:ff21514d8981 505
AnnaBridge 156:ff21514d8981 506 /** @brief Clears the specified QSPI's flag status.
AnnaBridge 163:e59c8e839560 507 * @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge 163:e59c8e839560 508 * @param __FLAG__ specifies the QSPI clear register flag that needs to be set
AnnaBridge 156:ff21514d8981 509 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 510 * @arg QSPI_FLAG_TO: QSPI Time out flag
AnnaBridge 156:ff21514d8981 511 * @arg QSPI_FLAG_SM: QSPI Status match flag
AnnaBridge 156:ff21514d8981 512 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
AnnaBridge 156:ff21514d8981 513 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
AnnaBridge 156:ff21514d8981 514 * @retval None
AnnaBridge 156:ff21514d8981 515 */
AnnaBridge 156:ff21514d8981 516 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
AnnaBridge 156:ff21514d8981 517 /**
AnnaBridge 156:ff21514d8981 518 * @}
AnnaBridge 156:ff21514d8981 519 */
AnnaBridge 156:ff21514d8981 520
AnnaBridge 156:ff21514d8981 521 /* Exported functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 522 /** @addtogroup QSPI_Exported_Functions
AnnaBridge 156:ff21514d8981 523 * @{
AnnaBridge 156:ff21514d8981 524 */
AnnaBridge 156:ff21514d8981 525
AnnaBridge 156:ff21514d8981 526 /** @addtogroup QSPI_Exported_Functions_Group1
AnnaBridge 156:ff21514d8981 527 * @{
AnnaBridge 156:ff21514d8981 528 */
AnnaBridge 156:ff21514d8981 529 /* Initialization/de-initialization functions ********************************/
AnnaBridge 156:ff21514d8981 530 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 531 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 532 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 533 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 534 /**
AnnaBridge 156:ff21514d8981 535 * @}
AnnaBridge 156:ff21514d8981 536 */
AnnaBridge 156:ff21514d8981 537
AnnaBridge 156:ff21514d8981 538 /** @addtogroup QSPI_Exported_Functions_Group2
AnnaBridge 156:ff21514d8981 539 * @{
AnnaBridge 156:ff21514d8981 540 */
AnnaBridge 156:ff21514d8981 541 /* IO operation functions *****************************************************/
AnnaBridge 156:ff21514d8981 542 /* QSPI IRQ handler method */
AnnaBridge 156:ff21514d8981 543 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 544
AnnaBridge 156:ff21514d8981 545 /* QSPI indirect mode */
AnnaBridge 156:ff21514d8981 546 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
AnnaBridge 156:ff21514d8981 547 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
AnnaBridge 156:ff21514d8981 548 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
AnnaBridge 156:ff21514d8981 549 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
AnnaBridge 156:ff21514d8981 550 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 156:ff21514d8981 551 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 156:ff21514d8981 552 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 156:ff21514d8981 553 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 156:ff21514d8981 554
AnnaBridge 156:ff21514d8981 555 /* QSPI status flag polling mode */
AnnaBridge 156:ff21514d8981 556 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
AnnaBridge 156:ff21514d8981 557 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
AnnaBridge 156:ff21514d8981 558
AnnaBridge 156:ff21514d8981 559 /* QSPI memory-mapped mode */
AnnaBridge 156:ff21514d8981 560 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
AnnaBridge 156:ff21514d8981 561 /**
AnnaBridge 156:ff21514d8981 562 * @}
AnnaBridge 156:ff21514d8981 563 */
AnnaBridge 156:ff21514d8981 564
AnnaBridge 156:ff21514d8981 565 /** @addtogroup QSPI_Exported_Functions_Group3
AnnaBridge 156:ff21514d8981 566 * @{
AnnaBridge 156:ff21514d8981 567 */
AnnaBridge 156:ff21514d8981 568 /* Callback functions in non-blocking modes ***********************************/
AnnaBridge 156:ff21514d8981 569 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 570 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 571 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 572
AnnaBridge 156:ff21514d8981 573 /* QSPI indirect mode */
AnnaBridge 156:ff21514d8981 574 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 575 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 576 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 577 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 578 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 579
AnnaBridge 156:ff21514d8981 580 /* QSPI status flag polling mode */
AnnaBridge 156:ff21514d8981 581 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 582
AnnaBridge 156:ff21514d8981 583 /* QSPI memory-mapped mode */
AnnaBridge 156:ff21514d8981 584 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 585 /**
AnnaBridge 156:ff21514d8981 586 * @}
AnnaBridge 156:ff21514d8981 587 */
AnnaBridge 156:ff21514d8981 588
AnnaBridge 156:ff21514d8981 589 /** @addtogroup QSPI_Exported_Functions_Group4
AnnaBridge 156:ff21514d8981 590 * @{
AnnaBridge 156:ff21514d8981 591 */
AnnaBridge 156:ff21514d8981 592 /* Peripheral Control and State functions ************************************/
AnnaBridge 156:ff21514d8981 593 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 594 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 595 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 596 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 597 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
AnnaBridge 156:ff21514d8981 598 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
AnnaBridge 156:ff21514d8981 599 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
AnnaBridge 156:ff21514d8981 600 /**
AnnaBridge 156:ff21514d8981 601 * @}
AnnaBridge 156:ff21514d8981 602 */
AnnaBridge 156:ff21514d8981 603
AnnaBridge 156:ff21514d8981 604 /* Private macros ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 605 /** @defgroup QSPI_Private_Macros QSPI Private Macros
AnnaBridge 156:ff21514d8981 606 * @{
AnnaBridge 156:ff21514d8981 607 */
AnnaBridge 156:ff21514d8981 608 /** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
AnnaBridge 156:ff21514d8981 609 * @{
AnnaBridge 156:ff21514d8981 610 */
AnnaBridge 156:ff21514d8981 611 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
AnnaBridge 156:ff21514d8981 612 /**
AnnaBridge 156:ff21514d8981 613 * @}
AnnaBridge 156:ff21514d8981 614 */
AnnaBridge 156:ff21514d8981 615
AnnaBridge 156:ff21514d8981 616 /** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
AnnaBridge 156:ff21514d8981 617 * @{
AnnaBridge 156:ff21514d8981 618 */
AnnaBridge 156:ff21514d8981 619 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
AnnaBridge 156:ff21514d8981 620 /**
AnnaBridge 156:ff21514d8981 621 * @}
AnnaBridge 156:ff21514d8981 622 */
AnnaBridge 156:ff21514d8981 623
AnnaBridge 156:ff21514d8981 624 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
AnnaBridge 156:ff21514d8981 625 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
AnnaBridge 156:ff21514d8981 626
AnnaBridge 156:ff21514d8981 627 /** @defgroup QSPI_FlashSize QSPI Flash Size
AnnaBridge 156:ff21514d8981 628 * @{
AnnaBridge 156:ff21514d8981 629 */
AnnaBridge 156:ff21514d8981 630 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
AnnaBridge 156:ff21514d8981 631 /**
AnnaBridge 156:ff21514d8981 632 * @}
AnnaBridge 156:ff21514d8981 633 */
AnnaBridge 156:ff21514d8981 634
AnnaBridge 156:ff21514d8981 635 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
AnnaBridge 156:ff21514d8981 636 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
AnnaBridge 156:ff21514d8981 637 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
AnnaBridge 156:ff21514d8981 638 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
AnnaBridge 156:ff21514d8981 639 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
AnnaBridge 156:ff21514d8981 640 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
AnnaBridge 156:ff21514d8981 641 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
AnnaBridge 156:ff21514d8981 642 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
AnnaBridge 156:ff21514d8981 643
AnnaBridge 156:ff21514d8981 644 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
AnnaBridge 156:ff21514d8981 645 ((CLKMODE) == QSPI_CLOCK_MODE_3))
AnnaBridge 156:ff21514d8981 646
AnnaBridge 156:ff21514d8981 647 #define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
AnnaBridge 156:ff21514d8981 648 ((FLA) == QSPI_FLASH_ID_2))
AnnaBridge 156:ff21514d8981 649
AnnaBridge 156:ff21514d8981 650 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
AnnaBridge 156:ff21514d8981 651 ((MODE) == QSPI_DUALFLASH_DISABLE))
AnnaBridge 156:ff21514d8981 652
AnnaBridge 156:ff21514d8981 653
AnnaBridge 156:ff21514d8981 654 /** @defgroup QSPI_Instruction QSPI Instruction
AnnaBridge 156:ff21514d8981 655 * @{
AnnaBridge 156:ff21514d8981 656 */
AnnaBridge 156:ff21514d8981 657 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
AnnaBridge 156:ff21514d8981 658 /**
AnnaBridge 156:ff21514d8981 659 * @}
AnnaBridge 156:ff21514d8981 660 */
AnnaBridge 156:ff21514d8981 661
AnnaBridge 156:ff21514d8981 662 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
AnnaBridge 156:ff21514d8981 663 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
AnnaBridge 156:ff21514d8981 664 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
AnnaBridge 156:ff21514d8981 665 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
AnnaBridge 156:ff21514d8981 666
AnnaBridge 156:ff21514d8981 667 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
AnnaBridge 156:ff21514d8981 668 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
AnnaBridge 156:ff21514d8981 669 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
AnnaBridge 156:ff21514d8981 670 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
AnnaBridge 156:ff21514d8981 671
AnnaBridge 156:ff21514d8981 672
AnnaBridge 156:ff21514d8981 673 /** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
AnnaBridge 156:ff21514d8981 674 * @{
AnnaBridge 156:ff21514d8981 675 */
AnnaBridge 156:ff21514d8981 676 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
AnnaBridge 156:ff21514d8981 677 /**
AnnaBridge 156:ff21514d8981 678 * @}
AnnaBridge 156:ff21514d8981 679 */
AnnaBridge 156:ff21514d8981 680
AnnaBridge 156:ff21514d8981 681 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
AnnaBridge 156:ff21514d8981 682 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
AnnaBridge 156:ff21514d8981 683 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
AnnaBridge 156:ff21514d8981 684 ((MODE) == QSPI_INSTRUCTION_4_LINES))
AnnaBridge 156:ff21514d8981 685
AnnaBridge 156:ff21514d8981 686 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
AnnaBridge 156:ff21514d8981 687 ((MODE) == QSPI_ADDRESS_1_LINE) || \
AnnaBridge 156:ff21514d8981 688 ((MODE) == QSPI_ADDRESS_2_LINES) || \
AnnaBridge 156:ff21514d8981 689 ((MODE) == QSPI_ADDRESS_4_LINES))
AnnaBridge 156:ff21514d8981 690
AnnaBridge 156:ff21514d8981 691 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
AnnaBridge 156:ff21514d8981 692 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
AnnaBridge 156:ff21514d8981 693 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
AnnaBridge 156:ff21514d8981 694 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
AnnaBridge 156:ff21514d8981 695
AnnaBridge 156:ff21514d8981 696 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
AnnaBridge 156:ff21514d8981 697 ((MODE) == QSPI_DATA_1_LINE) || \
AnnaBridge 156:ff21514d8981 698 ((MODE) == QSPI_DATA_2_LINES) || \
AnnaBridge 156:ff21514d8981 699 ((MODE) == QSPI_DATA_4_LINES))
AnnaBridge 156:ff21514d8981 700
AnnaBridge 156:ff21514d8981 701 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
AnnaBridge 156:ff21514d8981 702 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
AnnaBridge 156:ff21514d8981 703
AnnaBridge 156:ff21514d8981 704 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
AnnaBridge 156:ff21514d8981 705 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
AnnaBridge 156:ff21514d8981 706
AnnaBridge 156:ff21514d8981 707 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
AnnaBridge 156:ff21514d8981 708 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
AnnaBridge 156:ff21514d8981 709
AnnaBridge 156:ff21514d8981 710 /** @defgroup QSPI_Interval QSPI Interval
AnnaBridge 156:ff21514d8981 711 * @{
AnnaBridge 156:ff21514d8981 712 */
AnnaBridge 156:ff21514d8981 713 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
AnnaBridge 156:ff21514d8981 714 /**
AnnaBridge 156:ff21514d8981 715 * @}
AnnaBridge 156:ff21514d8981 716 */
AnnaBridge 156:ff21514d8981 717
AnnaBridge 156:ff21514d8981 718 /** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
AnnaBridge 156:ff21514d8981 719 * @{
AnnaBridge 156:ff21514d8981 720 */
AnnaBridge 156:ff21514d8981 721 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
AnnaBridge 156:ff21514d8981 722 /**
AnnaBridge 156:ff21514d8981 723 * @}
AnnaBridge 156:ff21514d8981 724 */
AnnaBridge 156:ff21514d8981 725 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
AnnaBridge 156:ff21514d8981 726 ((MODE) == QSPI_MATCH_MODE_OR))
AnnaBridge 156:ff21514d8981 727
AnnaBridge 156:ff21514d8981 728 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
AnnaBridge 156:ff21514d8981 729 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
AnnaBridge 156:ff21514d8981 730
AnnaBridge 156:ff21514d8981 731 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
AnnaBridge 156:ff21514d8981 732 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
AnnaBridge 156:ff21514d8981 733
AnnaBridge 156:ff21514d8981 734 /** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
AnnaBridge 156:ff21514d8981 735 * @{
AnnaBridge 156:ff21514d8981 736 */
AnnaBridge 156:ff21514d8981 737 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
AnnaBridge 156:ff21514d8981 738 /**
AnnaBridge 156:ff21514d8981 739 * @}
AnnaBridge 156:ff21514d8981 740 */
AnnaBridge 156:ff21514d8981 741
AnnaBridge 156:ff21514d8981 742 #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
AnnaBridge 156:ff21514d8981 743 ((FLAG) == QSPI_FLAG_TO) || \
AnnaBridge 156:ff21514d8981 744 ((FLAG) == QSPI_FLAG_SM) || \
AnnaBridge 156:ff21514d8981 745 ((FLAG) == QSPI_FLAG_FT) || \
AnnaBridge 156:ff21514d8981 746 ((FLAG) == QSPI_FLAG_TC) || \
AnnaBridge 156:ff21514d8981 747 ((FLAG) == QSPI_FLAG_TE))
AnnaBridge 156:ff21514d8981 748
AnnaBridge 156:ff21514d8981 749 #define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
AnnaBridge 156:ff21514d8981 750 /**
AnnaBridge 156:ff21514d8981 751 * @}
AnnaBridge 156:ff21514d8981 752 */
AnnaBridge 156:ff21514d8981 753
AnnaBridge 156:ff21514d8981 754 /* Private functions ---------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 755 /** @defgroup QSPI_Private_Functions QSPI Private Functions
AnnaBridge 156:ff21514d8981 756 * @{
AnnaBridge 156:ff21514d8981 757 */
AnnaBridge 156:ff21514d8981 758
AnnaBridge 156:ff21514d8981 759 /**
AnnaBridge 156:ff21514d8981 760 * @}
AnnaBridge 156:ff21514d8981 761 */
AnnaBridge 156:ff21514d8981 762
AnnaBridge 156:ff21514d8981 763 /**
AnnaBridge 156:ff21514d8981 764 * @}
AnnaBridge 156:ff21514d8981 765 */
AnnaBridge 156:ff21514d8981 766
AnnaBridge 156:ff21514d8981 767 /**
AnnaBridge 156:ff21514d8981 768 * @}
AnnaBridge 156:ff21514d8981 769 */
AnnaBridge 156:ff21514d8981 770
AnnaBridge 156:ff21514d8981 771 /**
AnnaBridge 156:ff21514d8981 772 * @}
AnnaBridge 156:ff21514d8981 773 */
AnnaBridge 156:ff21514d8981 774 #endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||
AnnaBridge 156:ff21514d8981 775 STM32F413xx || STM32F423xx */
AnnaBridge 156:ff21514d8981 776
AnnaBridge 156:ff21514d8981 777 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 778 }
AnnaBridge 156:ff21514d8981 779 #endif
AnnaBridge 156:ff21514d8981 780
AnnaBridge 156:ff21514d8981 781 #endif /* __STM32F4xx_HAL_QSPI_H */
AnnaBridge 156:ff21514d8981 782
AnnaBridge 156:ff21514d8981 783 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/