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TARGET_NUCLEO_F401RE/core_cm0.h@128:9bcdf88f62b0, 2016-10-27 (annotated)
- Committer:
- <>
- Date:
- Thu Oct 27 16:45:56 2016 +0100
- Revision:
- 128:9bcdf88f62b0
- Parent:
- 110:165afa46840b
- Child:
- 131:faff56e089b2
Release 128 of the mbed library
Ports for Upcoming Targets
Fixes and Changes
2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966
3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068
3089: Kinetis HAL: Remove clock initialization code from serial and ticker https://github.com/ARMmbed/mbed-os/pull/3089
2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943
2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938
3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108
3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076
3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085
3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046
3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122
3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022
3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121
3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
emilmont | 77:869cf507173a | 1 | /**************************************************************************//** |
emilmont | 77:869cf507173a | 2 | * @file core_cm0.h |
emilmont | 77:869cf507173a | 3 | * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File |
Kojto | 110:165afa46840b | 4 | * @version V4.10 |
Kojto | 110:165afa46840b | 5 | * @date 18. March 2015 |
emilmont | 77:869cf507173a | 6 | * |
emilmont | 77:869cf507173a | 7 | * @note |
emilmont | 77:869cf507173a | 8 | * |
emilmont | 77:869cf507173a | 9 | ******************************************************************************/ |
Kojto | 110:165afa46840b | 10 | /* Copyright (c) 2009 - 2015 ARM LIMITED |
emilmont | 77:869cf507173a | 11 | |
emilmont | 77:869cf507173a | 12 | All rights reserved. |
emilmont | 77:869cf507173a | 13 | Redistribution and use in source and binary forms, with or without |
emilmont | 77:869cf507173a | 14 | modification, are permitted provided that the following conditions are met: |
emilmont | 77:869cf507173a | 15 | - Redistributions of source code must retain the above copyright |
emilmont | 77:869cf507173a | 16 | notice, this list of conditions and the following disclaimer. |
emilmont | 77:869cf507173a | 17 | - Redistributions in binary form must reproduce the above copyright |
emilmont | 77:869cf507173a | 18 | notice, this list of conditions and the following disclaimer in the |
emilmont | 77:869cf507173a | 19 | documentation and/or other materials provided with the distribution. |
emilmont | 77:869cf507173a | 20 | - Neither the name of ARM nor the names of its contributors may be used |
emilmont | 77:869cf507173a | 21 | to endorse or promote products derived from this software without |
emilmont | 77:869cf507173a | 22 | specific prior written permission. |
emilmont | 77:869cf507173a | 23 | * |
emilmont | 77:869cf507173a | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
emilmont | 77:869cf507173a | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
emilmont | 77:869cf507173a | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
emilmont | 77:869cf507173a | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
emilmont | 77:869cf507173a | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
emilmont | 77:869cf507173a | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
emilmont | 77:869cf507173a | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
emilmont | 77:869cf507173a | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
emilmont | 77:869cf507173a | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
emilmont | 77:869cf507173a | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
emilmont | 77:869cf507173a | 34 | POSSIBILITY OF SUCH DAMAGE. |
emilmont | 77:869cf507173a | 35 | ---------------------------------------------------------------------------*/ |
emilmont | 77:869cf507173a | 36 | |
emilmont | 77:869cf507173a | 37 | |
emilmont | 77:869cf507173a | 38 | #if defined ( __ICCARM__ ) |
emilmont | 77:869cf507173a | 39 | #pragma system_include /* treat file as system include file for MISRA check */ |
emilmont | 77:869cf507173a | 40 | #endif |
emilmont | 77:869cf507173a | 41 | |
Kojto | 110:165afa46840b | 42 | #ifndef __CORE_CM0_H_GENERIC |
Kojto | 110:165afa46840b | 43 | #define __CORE_CM0_H_GENERIC |
Kojto | 110:165afa46840b | 44 | |
emilmont | 77:869cf507173a | 45 | #ifdef __cplusplus |
emilmont | 77:869cf507173a | 46 | extern "C" { |
emilmont | 77:869cf507173a | 47 | #endif |
emilmont | 77:869cf507173a | 48 | |
emilmont | 77:869cf507173a | 49 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
emilmont | 77:869cf507173a | 50 | CMSIS violates the following MISRA-C:2004 rules: |
emilmont | 77:869cf507173a | 51 | |
emilmont | 77:869cf507173a | 52 | \li Required Rule 8.5, object/function definition in header file.<br> |
emilmont | 77:869cf507173a | 53 | Function definitions in header files are used to allow 'inlining'. |
emilmont | 77:869cf507173a | 54 | |
emilmont | 77:869cf507173a | 55 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
emilmont | 77:869cf507173a | 56 | Unions are used for effective representation of core registers. |
emilmont | 77:869cf507173a | 57 | |
emilmont | 77:869cf507173a | 58 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
emilmont | 77:869cf507173a | 59 | Function-like macros are used to allow more efficient code. |
emilmont | 77:869cf507173a | 60 | */ |
emilmont | 77:869cf507173a | 61 | |
emilmont | 77:869cf507173a | 62 | |
emilmont | 77:869cf507173a | 63 | /******************************************************************************* |
emilmont | 77:869cf507173a | 64 | * CMSIS definitions |
emilmont | 77:869cf507173a | 65 | ******************************************************************************/ |
emilmont | 77:869cf507173a | 66 | /** \ingroup Cortex_M0 |
emilmont | 77:869cf507173a | 67 | @{ |
emilmont | 77:869cf507173a | 68 | */ |
emilmont | 77:869cf507173a | 69 | |
emilmont | 77:869cf507173a | 70 | /* CMSIS CM0 definitions */ |
Kojto | 110:165afa46840b | 71 | #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ |
Kojto | 110:165afa46840b | 72 | #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ |
emilmont | 77:869cf507173a | 73 | #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ |
emilmont | 77:869cf507173a | 74 | __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
emilmont | 77:869cf507173a | 75 | |
emilmont | 77:869cf507173a | 76 | #define __CORTEX_M (0x00) /*!< Cortex-M Core */ |
emilmont | 77:869cf507173a | 77 | |
emilmont | 77:869cf507173a | 78 | |
emilmont | 77:869cf507173a | 79 | #if defined ( __CC_ARM ) |
emilmont | 77:869cf507173a | 80 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
emilmont | 77:869cf507173a | 81 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
emilmont | 77:869cf507173a | 82 | #define __STATIC_INLINE static __inline |
emilmont | 77:869cf507173a | 83 | |
Kojto | 110:165afa46840b | 84 | #elif defined ( __GNUC__ ) |
Kojto | 110:165afa46840b | 85 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
Kojto | 110:165afa46840b | 86 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
Kojto | 110:165afa46840b | 87 | #define __STATIC_INLINE static inline |
Kojto | 110:165afa46840b | 88 | |
emilmont | 77:869cf507173a | 89 | #elif defined ( __ICCARM__ ) |
emilmont | 77:869cf507173a | 90 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
emilmont | 77:869cf507173a | 91 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
emilmont | 77:869cf507173a | 92 | #define __STATIC_INLINE static inline |
emilmont | 77:869cf507173a | 93 | |
Kojto | 110:165afa46840b | 94 | #elif defined ( __TMS470__ ) |
Kojto | 110:165afa46840b | 95 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
emilmont | 77:869cf507173a | 96 | #define __STATIC_INLINE static inline |
emilmont | 77:869cf507173a | 97 | |
emilmont | 77:869cf507173a | 98 | #elif defined ( __TASKING__ ) |
emilmont | 77:869cf507173a | 99 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
emilmont | 77:869cf507173a | 100 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
emilmont | 77:869cf507173a | 101 | #define __STATIC_INLINE static inline |
emilmont | 77:869cf507173a | 102 | |
Kojto | 110:165afa46840b | 103 | #elif defined ( __CSMC__ ) |
Kojto | 110:165afa46840b | 104 | #define __packed |
Kojto | 110:165afa46840b | 105 | #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
Kojto | 110:165afa46840b | 106 | #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ |
Kojto | 110:165afa46840b | 107 | #define __STATIC_INLINE static inline |
Kojto | 110:165afa46840b | 108 | |
emilmont | 77:869cf507173a | 109 | #endif |
emilmont | 77:869cf507173a | 110 | |
Kojto | 110:165afa46840b | 111 | /** __FPU_USED indicates whether an FPU is used or not. |
Kojto | 110:165afa46840b | 112 | This core does not support an FPU at all |
emilmont | 77:869cf507173a | 113 | */ |
emilmont | 77:869cf507173a | 114 | #define __FPU_USED 0 |
emilmont | 77:869cf507173a | 115 | |
emilmont | 77:869cf507173a | 116 | #if defined ( __CC_ARM ) |
emilmont | 77:869cf507173a | 117 | #if defined __TARGET_FPU_VFP |
emilmont | 77:869cf507173a | 118 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emilmont | 77:869cf507173a | 119 | #endif |
emilmont | 77:869cf507173a | 120 | |
Kojto | 110:165afa46840b | 121 | #elif defined ( __GNUC__ ) |
Kojto | 110:165afa46840b | 122 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
Kojto | 110:165afa46840b | 123 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 110:165afa46840b | 124 | #endif |
Kojto | 110:165afa46840b | 125 | |
emilmont | 77:869cf507173a | 126 | #elif defined ( __ICCARM__ ) |
emilmont | 77:869cf507173a | 127 | #if defined __ARMVFP__ |
emilmont | 77:869cf507173a | 128 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emilmont | 77:869cf507173a | 129 | #endif |
emilmont | 77:869cf507173a | 130 | |
Kojto | 110:165afa46840b | 131 | #elif defined ( __TMS470__ ) |
Kojto | 110:165afa46840b | 132 | #if defined __TI__VFP_SUPPORT____ |
emilmont | 77:869cf507173a | 133 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emilmont | 77:869cf507173a | 134 | #endif |
emilmont | 77:869cf507173a | 135 | |
emilmont | 77:869cf507173a | 136 | #elif defined ( __TASKING__ ) |
emilmont | 77:869cf507173a | 137 | #if defined __FPU_VFP__ |
emilmont | 77:869cf507173a | 138 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emilmont | 77:869cf507173a | 139 | #endif |
Kojto | 110:165afa46840b | 140 | |
Kojto | 110:165afa46840b | 141 | #elif defined ( __CSMC__ ) /* Cosmic */ |
Kojto | 110:165afa46840b | 142 | #if ( __CSMC__ & 0x400) // FPU present for parser |
Kojto | 110:165afa46840b | 143 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 110:165afa46840b | 144 | #endif |
emilmont | 77:869cf507173a | 145 | #endif |
emilmont | 77:869cf507173a | 146 | |
emilmont | 77:869cf507173a | 147 | #include <stdint.h> /* standard types definitions */ |
emilmont | 77:869cf507173a | 148 | #include <core_cmInstr.h> /* Core Instruction Access */ |
emilmont | 77:869cf507173a | 149 | #include <core_cmFunc.h> /* Core Function Access */ |
emilmont | 77:869cf507173a | 150 | |
Kojto | 110:165afa46840b | 151 | #ifdef __cplusplus |
Kojto | 110:165afa46840b | 152 | } |
Kojto | 110:165afa46840b | 153 | #endif |
Kojto | 110:165afa46840b | 154 | |
emilmont | 77:869cf507173a | 155 | #endif /* __CORE_CM0_H_GENERIC */ |
emilmont | 77:869cf507173a | 156 | |
emilmont | 77:869cf507173a | 157 | #ifndef __CMSIS_GENERIC |
emilmont | 77:869cf507173a | 158 | |
emilmont | 77:869cf507173a | 159 | #ifndef __CORE_CM0_H_DEPENDANT |
emilmont | 77:869cf507173a | 160 | #define __CORE_CM0_H_DEPENDANT |
emilmont | 77:869cf507173a | 161 | |
Kojto | 110:165afa46840b | 162 | #ifdef __cplusplus |
Kojto | 110:165afa46840b | 163 | extern "C" { |
Kojto | 110:165afa46840b | 164 | #endif |
Kojto | 110:165afa46840b | 165 | |
emilmont | 77:869cf507173a | 166 | /* check device defines and use defaults */ |
emilmont | 77:869cf507173a | 167 | #if defined __CHECK_DEVICE_DEFINES |
emilmont | 77:869cf507173a | 168 | #ifndef __CM0_REV |
emilmont | 77:869cf507173a | 169 | #define __CM0_REV 0x0000 |
emilmont | 77:869cf507173a | 170 | #warning "__CM0_REV not defined in device header file; using default!" |
emilmont | 77:869cf507173a | 171 | #endif |
emilmont | 77:869cf507173a | 172 | |
emilmont | 77:869cf507173a | 173 | #ifndef __NVIC_PRIO_BITS |
emilmont | 77:869cf507173a | 174 | #define __NVIC_PRIO_BITS 2 |
emilmont | 77:869cf507173a | 175 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
emilmont | 77:869cf507173a | 176 | #endif |
emilmont | 77:869cf507173a | 177 | |
emilmont | 77:869cf507173a | 178 | #ifndef __Vendor_SysTickConfig |
emilmont | 77:869cf507173a | 179 | #define __Vendor_SysTickConfig 0 |
emilmont | 77:869cf507173a | 180 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
emilmont | 77:869cf507173a | 181 | #endif |
emilmont | 77:869cf507173a | 182 | #endif |
emilmont | 77:869cf507173a | 183 | |
emilmont | 77:869cf507173a | 184 | /* IO definitions (access restrictions to peripheral registers) */ |
emilmont | 77:869cf507173a | 185 | /** |
emilmont | 77:869cf507173a | 186 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
emilmont | 77:869cf507173a | 187 | |
emilmont | 77:869cf507173a | 188 | <strong>IO Type Qualifiers</strong> are used |
emilmont | 77:869cf507173a | 189 | \li to specify the access to peripheral variables. |
emilmont | 77:869cf507173a | 190 | \li for automatic generation of peripheral register debug information. |
emilmont | 77:869cf507173a | 191 | */ |
emilmont | 77:869cf507173a | 192 | #ifdef __cplusplus |
emilmont | 77:869cf507173a | 193 | #define __I volatile /*!< Defines 'read only' permissions */ |
emilmont | 77:869cf507173a | 194 | #else |
emilmont | 77:869cf507173a | 195 | #define __I volatile const /*!< Defines 'read only' permissions */ |
emilmont | 77:869cf507173a | 196 | #endif |
emilmont | 77:869cf507173a | 197 | #define __O volatile /*!< Defines 'write only' permissions */ |
emilmont | 77:869cf507173a | 198 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
emilmont | 77:869cf507173a | 199 | |
<> | 128:9bcdf88f62b0 | 200 | #ifdef __cplusplus |
<> | 128:9bcdf88f62b0 | 201 | #define __IM volatile /*!< Defines 'read only' permissions */ |
<> | 128:9bcdf88f62b0 | 202 | #else |
<> | 128:9bcdf88f62b0 | 203 | #define __IM volatile const /*!< Defines 'read only' permissions */ |
<> | 128:9bcdf88f62b0 | 204 | #endif |
<> | 128:9bcdf88f62b0 | 205 | #define __OM volatile /*!< Defines 'write only' permissions */ |
<> | 128:9bcdf88f62b0 | 206 | #define __IOM volatile /*!< Defines 'read / write' permissions */ |
<> | 128:9bcdf88f62b0 | 207 | |
emilmont | 77:869cf507173a | 208 | /*@} end of group Cortex_M0 */ |
emilmont | 77:869cf507173a | 209 | |
emilmont | 77:869cf507173a | 210 | |
emilmont | 77:869cf507173a | 211 | |
emilmont | 77:869cf507173a | 212 | /******************************************************************************* |
emilmont | 77:869cf507173a | 213 | * Register Abstraction |
emilmont | 77:869cf507173a | 214 | Core Register contain: |
emilmont | 77:869cf507173a | 215 | - Core Register |
emilmont | 77:869cf507173a | 216 | - Core NVIC Register |
emilmont | 77:869cf507173a | 217 | - Core SCB Register |
emilmont | 77:869cf507173a | 218 | - Core SysTick Register |
emilmont | 77:869cf507173a | 219 | ******************************************************************************/ |
emilmont | 77:869cf507173a | 220 | /** \defgroup CMSIS_core_register Defines and Type Definitions |
emilmont | 77:869cf507173a | 221 | \brief Type definitions and defines for Cortex-M processor based devices. |
emilmont | 77:869cf507173a | 222 | */ |
emilmont | 77:869cf507173a | 223 | |
emilmont | 77:869cf507173a | 224 | /** \ingroup CMSIS_core_register |
emilmont | 77:869cf507173a | 225 | \defgroup CMSIS_CORE Status and Control Registers |
emilmont | 77:869cf507173a | 226 | \brief Core Register type definitions. |
emilmont | 77:869cf507173a | 227 | @{ |
emilmont | 77:869cf507173a | 228 | */ |
emilmont | 77:869cf507173a | 229 | |
emilmont | 77:869cf507173a | 230 | /** \brief Union type to access the Application Program Status Register (APSR). |
emilmont | 77:869cf507173a | 231 | */ |
emilmont | 77:869cf507173a | 232 | typedef union |
emilmont | 77:869cf507173a | 233 | { |
emilmont | 77:869cf507173a | 234 | struct |
emilmont | 77:869cf507173a | 235 | { |
Kojto | 110:165afa46840b | 236 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
emilmont | 77:869cf507173a | 237 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
emilmont | 77:869cf507173a | 238 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
emilmont | 77:869cf507173a | 239 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
emilmont | 77:869cf507173a | 240 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
emilmont | 77:869cf507173a | 241 | } b; /*!< Structure used for bit access */ |
emilmont | 77:869cf507173a | 242 | uint32_t w; /*!< Type used for word access */ |
emilmont | 77:869cf507173a | 243 | } APSR_Type; |
emilmont | 77:869cf507173a | 244 | |
Kojto | 110:165afa46840b | 245 | /* APSR Register Definitions */ |
Kojto | 110:165afa46840b | 246 | #define APSR_N_Pos 31 /*!< APSR: N Position */ |
Kojto | 110:165afa46840b | 247 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
Kojto | 110:165afa46840b | 248 | |
Kojto | 110:165afa46840b | 249 | #define APSR_Z_Pos 30 /*!< APSR: Z Position */ |
Kojto | 110:165afa46840b | 250 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
Kojto | 110:165afa46840b | 251 | |
Kojto | 110:165afa46840b | 252 | #define APSR_C_Pos 29 /*!< APSR: C Position */ |
Kojto | 110:165afa46840b | 253 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
Kojto | 110:165afa46840b | 254 | |
Kojto | 110:165afa46840b | 255 | #define APSR_V_Pos 28 /*!< APSR: V Position */ |
Kojto | 110:165afa46840b | 256 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
Kojto | 110:165afa46840b | 257 | |
emilmont | 77:869cf507173a | 258 | |
emilmont | 77:869cf507173a | 259 | /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
emilmont | 77:869cf507173a | 260 | */ |
emilmont | 77:869cf507173a | 261 | typedef union |
emilmont | 77:869cf507173a | 262 | { |
emilmont | 77:869cf507173a | 263 | struct |
emilmont | 77:869cf507173a | 264 | { |
emilmont | 77:869cf507173a | 265 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
emilmont | 77:869cf507173a | 266 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
emilmont | 77:869cf507173a | 267 | } b; /*!< Structure used for bit access */ |
emilmont | 77:869cf507173a | 268 | uint32_t w; /*!< Type used for word access */ |
emilmont | 77:869cf507173a | 269 | } IPSR_Type; |
emilmont | 77:869cf507173a | 270 | |
Kojto | 110:165afa46840b | 271 | /* IPSR Register Definitions */ |
Kojto | 110:165afa46840b | 272 | #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ |
Kojto | 110:165afa46840b | 273 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
Kojto | 110:165afa46840b | 274 | |
emilmont | 77:869cf507173a | 275 | |
emilmont | 77:869cf507173a | 276 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
emilmont | 77:869cf507173a | 277 | */ |
emilmont | 77:869cf507173a | 278 | typedef union |
emilmont | 77:869cf507173a | 279 | { |
emilmont | 77:869cf507173a | 280 | struct |
emilmont | 77:869cf507173a | 281 | { |
emilmont | 77:869cf507173a | 282 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
emilmont | 77:869cf507173a | 283 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
emilmont | 77:869cf507173a | 284 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
Kojto | 110:165afa46840b | 285 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
emilmont | 77:869cf507173a | 286 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
emilmont | 77:869cf507173a | 287 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
emilmont | 77:869cf507173a | 288 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
emilmont | 77:869cf507173a | 289 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
emilmont | 77:869cf507173a | 290 | } b; /*!< Structure used for bit access */ |
emilmont | 77:869cf507173a | 291 | uint32_t w; /*!< Type used for word access */ |
emilmont | 77:869cf507173a | 292 | } xPSR_Type; |
emilmont | 77:869cf507173a | 293 | |
Kojto | 110:165afa46840b | 294 | /* xPSR Register Definitions */ |
Kojto | 110:165afa46840b | 295 | #define xPSR_N_Pos 31 /*!< xPSR: N Position */ |
Kojto | 110:165afa46840b | 296 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
Kojto | 110:165afa46840b | 297 | |
Kojto | 110:165afa46840b | 298 | #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ |
Kojto | 110:165afa46840b | 299 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
Kojto | 110:165afa46840b | 300 | |
Kojto | 110:165afa46840b | 301 | #define xPSR_C_Pos 29 /*!< xPSR: C Position */ |
Kojto | 110:165afa46840b | 302 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
Kojto | 110:165afa46840b | 303 | |
Kojto | 110:165afa46840b | 304 | #define xPSR_V_Pos 28 /*!< xPSR: V Position */ |
Kojto | 110:165afa46840b | 305 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
Kojto | 110:165afa46840b | 306 | |
Kojto | 110:165afa46840b | 307 | #define xPSR_T_Pos 24 /*!< xPSR: T Position */ |
Kojto | 110:165afa46840b | 308 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
Kojto | 110:165afa46840b | 309 | |
Kojto | 110:165afa46840b | 310 | #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ |
Kojto | 110:165afa46840b | 311 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
Kojto | 110:165afa46840b | 312 | |
emilmont | 77:869cf507173a | 313 | |
emilmont | 77:869cf507173a | 314 | /** \brief Union type to access the Control Registers (CONTROL). |
emilmont | 77:869cf507173a | 315 | */ |
emilmont | 77:869cf507173a | 316 | typedef union |
emilmont | 77:869cf507173a | 317 | { |
emilmont | 77:869cf507173a | 318 | struct |
emilmont | 77:869cf507173a | 319 | { |
Kojto | 110:165afa46840b | 320 | uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
emilmont | 77:869cf507173a | 321 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
Kojto | 110:165afa46840b | 322 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
emilmont | 77:869cf507173a | 323 | } b; /*!< Structure used for bit access */ |
emilmont | 77:869cf507173a | 324 | uint32_t w; /*!< Type used for word access */ |
emilmont | 77:869cf507173a | 325 | } CONTROL_Type; |
emilmont | 77:869cf507173a | 326 | |
Kojto | 110:165afa46840b | 327 | /* CONTROL Register Definitions */ |
Kojto | 110:165afa46840b | 328 | #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ |
Kojto | 110:165afa46840b | 329 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
Kojto | 110:165afa46840b | 330 | |
emilmont | 77:869cf507173a | 331 | /*@} end of group CMSIS_CORE */ |
emilmont | 77:869cf507173a | 332 | |
emilmont | 77:869cf507173a | 333 | |
emilmont | 77:869cf507173a | 334 | /** \ingroup CMSIS_core_register |
emilmont | 77:869cf507173a | 335 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
emilmont | 77:869cf507173a | 336 | \brief Type definitions for the NVIC Registers |
emilmont | 77:869cf507173a | 337 | @{ |
emilmont | 77:869cf507173a | 338 | */ |
emilmont | 77:869cf507173a | 339 | |
emilmont | 77:869cf507173a | 340 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
emilmont | 77:869cf507173a | 341 | */ |
emilmont | 77:869cf507173a | 342 | typedef struct |
emilmont | 77:869cf507173a | 343 | { |
emilmont | 77:869cf507173a | 344 | __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
emilmont | 77:869cf507173a | 345 | uint32_t RESERVED0[31]; |
emilmont | 77:869cf507173a | 346 | __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
emilmont | 77:869cf507173a | 347 | uint32_t RSERVED1[31]; |
emilmont | 77:869cf507173a | 348 | __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
emilmont | 77:869cf507173a | 349 | uint32_t RESERVED2[31]; |
emilmont | 77:869cf507173a | 350 | __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
emilmont | 77:869cf507173a | 351 | uint32_t RESERVED3[31]; |
emilmont | 77:869cf507173a | 352 | uint32_t RESERVED4[64]; |
emilmont | 77:869cf507173a | 353 | __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
emilmont | 77:869cf507173a | 354 | } NVIC_Type; |
emilmont | 77:869cf507173a | 355 | |
emilmont | 77:869cf507173a | 356 | /*@} end of group CMSIS_NVIC */ |
emilmont | 77:869cf507173a | 357 | |
emilmont | 77:869cf507173a | 358 | |
emilmont | 77:869cf507173a | 359 | /** \ingroup CMSIS_core_register |
emilmont | 77:869cf507173a | 360 | \defgroup CMSIS_SCB System Control Block (SCB) |
emilmont | 77:869cf507173a | 361 | \brief Type definitions for the System Control Block Registers |
emilmont | 77:869cf507173a | 362 | @{ |
emilmont | 77:869cf507173a | 363 | */ |
emilmont | 77:869cf507173a | 364 | |
emilmont | 77:869cf507173a | 365 | /** \brief Structure type to access the System Control Block (SCB). |
emilmont | 77:869cf507173a | 366 | */ |
emilmont | 77:869cf507173a | 367 | typedef struct |
emilmont | 77:869cf507173a | 368 | { |
emilmont | 77:869cf507173a | 369 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
emilmont | 77:869cf507173a | 370 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
emilmont | 77:869cf507173a | 371 | uint32_t RESERVED0; |
emilmont | 77:869cf507173a | 372 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
emilmont | 77:869cf507173a | 373 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
emilmont | 77:869cf507173a | 374 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
emilmont | 77:869cf507173a | 375 | uint32_t RESERVED1; |
emilmont | 77:869cf507173a | 376 | __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
emilmont | 77:869cf507173a | 377 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
emilmont | 77:869cf507173a | 378 | } SCB_Type; |
emilmont | 77:869cf507173a | 379 | |
emilmont | 77:869cf507173a | 380 | /* SCB CPUID Register Definitions */ |
emilmont | 77:869cf507173a | 381 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
emilmont | 77:869cf507173a | 382 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
emilmont | 77:869cf507173a | 383 | |
emilmont | 77:869cf507173a | 384 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
emilmont | 77:869cf507173a | 385 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
emilmont | 77:869cf507173a | 386 | |
emilmont | 77:869cf507173a | 387 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
emilmont | 77:869cf507173a | 388 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
emilmont | 77:869cf507173a | 389 | |
emilmont | 77:869cf507173a | 390 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
emilmont | 77:869cf507173a | 391 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
emilmont | 77:869cf507173a | 392 | |
emilmont | 77:869cf507173a | 393 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
Kojto | 110:165afa46840b | 394 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
emilmont | 77:869cf507173a | 395 | |
emilmont | 77:869cf507173a | 396 | /* SCB Interrupt Control State Register Definitions */ |
emilmont | 77:869cf507173a | 397 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
emilmont | 77:869cf507173a | 398 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
emilmont | 77:869cf507173a | 399 | |
emilmont | 77:869cf507173a | 400 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
emilmont | 77:869cf507173a | 401 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
emilmont | 77:869cf507173a | 402 | |
emilmont | 77:869cf507173a | 403 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
emilmont | 77:869cf507173a | 404 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
emilmont | 77:869cf507173a | 405 | |
emilmont | 77:869cf507173a | 406 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
emilmont | 77:869cf507173a | 407 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
emilmont | 77:869cf507173a | 408 | |
emilmont | 77:869cf507173a | 409 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
emilmont | 77:869cf507173a | 410 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
emilmont | 77:869cf507173a | 411 | |
emilmont | 77:869cf507173a | 412 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
emilmont | 77:869cf507173a | 413 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
emilmont | 77:869cf507173a | 414 | |
emilmont | 77:869cf507173a | 415 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
emilmont | 77:869cf507173a | 416 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
emilmont | 77:869cf507173a | 417 | |
emilmont | 77:869cf507173a | 418 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
emilmont | 77:869cf507173a | 419 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
emilmont | 77:869cf507173a | 420 | |
emilmont | 77:869cf507173a | 421 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
Kojto | 110:165afa46840b | 422 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
emilmont | 77:869cf507173a | 423 | |
emilmont | 77:869cf507173a | 424 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
emilmont | 77:869cf507173a | 425 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
emilmont | 77:869cf507173a | 426 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
emilmont | 77:869cf507173a | 427 | |
emilmont | 77:869cf507173a | 428 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
emilmont | 77:869cf507173a | 429 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
emilmont | 77:869cf507173a | 430 | |
emilmont | 77:869cf507173a | 431 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
emilmont | 77:869cf507173a | 432 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
emilmont | 77:869cf507173a | 433 | |
emilmont | 77:869cf507173a | 434 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
emilmont | 77:869cf507173a | 435 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
emilmont | 77:869cf507173a | 436 | |
emilmont | 77:869cf507173a | 437 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
emilmont | 77:869cf507173a | 438 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
emilmont | 77:869cf507173a | 439 | |
emilmont | 77:869cf507173a | 440 | /* SCB System Control Register Definitions */ |
emilmont | 77:869cf507173a | 441 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
emilmont | 77:869cf507173a | 442 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
emilmont | 77:869cf507173a | 443 | |
emilmont | 77:869cf507173a | 444 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
emilmont | 77:869cf507173a | 445 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
emilmont | 77:869cf507173a | 446 | |
emilmont | 77:869cf507173a | 447 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
emilmont | 77:869cf507173a | 448 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
emilmont | 77:869cf507173a | 449 | |
emilmont | 77:869cf507173a | 450 | /* SCB Configuration Control Register Definitions */ |
emilmont | 77:869cf507173a | 451 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
emilmont | 77:869cf507173a | 452 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
emilmont | 77:869cf507173a | 453 | |
emilmont | 77:869cf507173a | 454 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
emilmont | 77:869cf507173a | 455 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
emilmont | 77:869cf507173a | 456 | |
emilmont | 77:869cf507173a | 457 | /* SCB System Handler Control and State Register Definitions */ |
emilmont | 77:869cf507173a | 458 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
emilmont | 77:869cf507173a | 459 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
emilmont | 77:869cf507173a | 460 | |
emilmont | 77:869cf507173a | 461 | /*@} end of group CMSIS_SCB */ |
emilmont | 77:869cf507173a | 462 | |
emilmont | 77:869cf507173a | 463 | |
emilmont | 77:869cf507173a | 464 | /** \ingroup CMSIS_core_register |
emilmont | 77:869cf507173a | 465 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
emilmont | 77:869cf507173a | 466 | \brief Type definitions for the System Timer Registers. |
emilmont | 77:869cf507173a | 467 | @{ |
emilmont | 77:869cf507173a | 468 | */ |
emilmont | 77:869cf507173a | 469 | |
emilmont | 77:869cf507173a | 470 | /** \brief Structure type to access the System Timer (SysTick). |
emilmont | 77:869cf507173a | 471 | */ |
emilmont | 77:869cf507173a | 472 | typedef struct |
emilmont | 77:869cf507173a | 473 | { |
emilmont | 77:869cf507173a | 474 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
emilmont | 77:869cf507173a | 475 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
emilmont | 77:869cf507173a | 476 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
emilmont | 77:869cf507173a | 477 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
emilmont | 77:869cf507173a | 478 | } SysTick_Type; |
emilmont | 77:869cf507173a | 479 | |
emilmont | 77:869cf507173a | 480 | /* SysTick Control / Status Register Definitions */ |
emilmont | 77:869cf507173a | 481 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
emilmont | 77:869cf507173a | 482 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
emilmont | 77:869cf507173a | 483 | |
emilmont | 77:869cf507173a | 484 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
emilmont | 77:869cf507173a | 485 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
emilmont | 77:869cf507173a | 486 | |
emilmont | 77:869cf507173a | 487 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
emilmont | 77:869cf507173a | 488 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
emilmont | 77:869cf507173a | 489 | |
emilmont | 77:869cf507173a | 490 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
Kojto | 110:165afa46840b | 491 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
emilmont | 77:869cf507173a | 492 | |
emilmont | 77:869cf507173a | 493 | /* SysTick Reload Register Definitions */ |
emilmont | 77:869cf507173a | 494 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
Kojto | 110:165afa46840b | 495 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
emilmont | 77:869cf507173a | 496 | |
emilmont | 77:869cf507173a | 497 | /* SysTick Current Register Definitions */ |
emilmont | 77:869cf507173a | 498 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
Kojto | 110:165afa46840b | 499 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
emilmont | 77:869cf507173a | 500 | |
emilmont | 77:869cf507173a | 501 | /* SysTick Calibration Register Definitions */ |
emilmont | 77:869cf507173a | 502 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
emilmont | 77:869cf507173a | 503 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
emilmont | 77:869cf507173a | 504 | |
emilmont | 77:869cf507173a | 505 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
emilmont | 77:869cf507173a | 506 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
emilmont | 77:869cf507173a | 507 | |
emilmont | 77:869cf507173a | 508 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
Kojto | 110:165afa46840b | 509 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
emilmont | 77:869cf507173a | 510 | |
emilmont | 77:869cf507173a | 511 | /*@} end of group CMSIS_SysTick */ |
emilmont | 77:869cf507173a | 512 | |
emilmont | 77:869cf507173a | 513 | |
emilmont | 77:869cf507173a | 514 | /** \ingroup CMSIS_core_register |
emilmont | 77:869cf507173a | 515 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
emilmont | 77:869cf507173a | 516 | \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) |
emilmont | 77:869cf507173a | 517 | are only accessible over DAP and not via processor. Therefore |
emilmont | 77:869cf507173a | 518 | they are not covered by the Cortex-M0 header file. |
emilmont | 77:869cf507173a | 519 | @{ |
emilmont | 77:869cf507173a | 520 | */ |
emilmont | 77:869cf507173a | 521 | /*@} end of group CMSIS_CoreDebug */ |
emilmont | 77:869cf507173a | 522 | |
emilmont | 77:869cf507173a | 523 | |
emilmont | 77:869cf507173a | 524 | /** \ingroup CMSIS_core_register |
emilmont | 77:869cf507173a | 525 | \defgroup CMSIS_core_base Core Definitions |
emilmont | 77:869cf507173a | 526 | \brief Definitions for base addresses, unions, and structures. |
emilmont | 77:869cf507173a | 527 | @{ |
emilmont | 77:869cf507173a | 528 | */ |
emilmont | 77:869cf507173a | 529 | |
emilmont | 77:869cf507173a | 530 | /* Memory mapping of Cortex-M0 Hardware */ |
emilmont | 77:869cf507173a | 531 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
emilmont | 77:869cf507173a | 532 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
emilmont | 77:869cf507173a | 533 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
emilmont | 77:869cf507173a | 534 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
emilmont | 77:869cf507173a | 535 | |
emilmont | 77:869cf507173a | 536 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
emilmont | 77:869cf507173a | 537 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
emilmont | 77:869cf507173a | 538 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
emilmont | 77:869cf507173a | 539 | |
emilmont | 77:869cf507173a | 540 | |
emilmont | 77:869cf507173a | 541 | /*@} */ |
emilmont | 77:869cf507173a | 542 | |
emilmont | 77:869cf507173a | 543 | |
emilmont | 77:869cf507173a | 544 | |
emilmont | 77:869cf507173a | 545 | /******************************************************************************* |
emilmont | 77:869cf507173a | 546 | * Hardware Abstraction Layer |
emilmont | 77:869cf507173a | 547 | Core Function Interface contains: |
emilmont | 77:869cf507173a | 548 | - Core NVIC Functions |
emilmont | 77:869cf507173a | 549 | - Core SysTick Functions |
emilmont | 77:869cf507173a | 550 | - Core Register Access Functions |
emilmont | 77:869cf507173a | 551 | ******************************************************************************/ |
emilmont | 77:869cf507173a | 552 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
emilmont | 77:869cf507173a | 553 | */ |
emilmont | 77:869cf507173a | 554 | |
emilmont | 77:869cf507173a | 555 | |
emilmont | 77:869cf507173a | 556 | |
emilmont | 77:869cf507173a | 557 | /* ########################## NVIC functions #################################### */ |
emilmont | 77:869cf507173a | 558 | /** \ingroup CMSIS_Core_FunctionInterface |
emilmont | 77:869cf507173a | 559 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
emilmont | 77:869cf507173a | 560 | \brief Functions that manage interrupts and exceptions via the NVIC. |
emilmont | 77:869cf507173a | 561 | @{ |
emilmont | 77:869cf507173a | 562 | */ |
emilmont | 77:869cf507173a | 563 | |
emilmont | 77:869cf507173a | 564 | /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
emilmont | 77:869cf507173a | 565 | /* The following MACROS handle generation of the register offset and byte masks */ |
Kojto | 110:165afa46840b | 566 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
Kojto | 110:165afa46840b | 567 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
Kojto | 110:165afa46840b | 568 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
emilmont | 77:869cf507173a | 569 | |
emilmont | 77:869cf507173a | 570 | |
emilmont | 77:869cf507173a | 571 | /** \brief Enable External Interrupt |
emilmont | 77:869cf507173a | 572 | |
emilmont | 77:869cf507173a | 573 | The function enables a device-specific interrupt in the NVIC interrupt controller. |
emilmont | 77:869cf507173a | 574 | |
emilmont | 77:869cf507173a | 575 | \param [in] IRQn External interrupt number. Value cannot be negative. |
emilmont | 77:869cf507173a | 576 | */ |
emilmont | 77:869cf507173a | 577 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
emilmont | 77:869cf507173a | 578 | { |
Kojto | 110:165afa46840b | 579 | NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
emilmont | 77:869cf507173a | 580 | } |
emilmont | 77:869cf507173a | 581 | |
emilmont | 77:869cf507173a | 582 | |
emilmont | 77:869cf507173a | 583 | /** \brief Disable External Interrupt |
emilmont | 77:869cf507173a | 584 | |
emilmont | 77:869cf507173a | 585 | The function disables a device-specific interrupt in the NVIC interrupt controller. |
emilmont | 77:869cf507173a | 586 | |
emilmont | 77:869cf507173a | 587 | \param [in] IRQn External interrupt number. Value cannot be negative. |
emilmont | 77:869cf507173a | 588 | */ |
emilmont | 77:869cf507173a | 589 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
emilmont | 77:869cf507173a | 590 | { |
Kojto | 110:165afa46840b | 591 | NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
emilmont | 77:869cf507173a | 592 | } |
emilmont | 77:869cf507173a | 593 | |
emilmont | 77:869cf507173a | 594 | |
emilmont | 77:869cf507173a | 595 | /** \brief Get Pending Interrupt |
emilmont | 77:869cf507173a | 596 | |
emilmont | 77:869cf507173a | 597 | The function reads the pending register in the NVIC and returns the pending bit |
emilmont | 77:869cf507173a | 598 | for the specified interrupt. |
emilmont | 77:869cf507173a | 599 | |
emilmont | 77:869cf507173a | 600 | \param [in] IRQn Interrupt number. |
emilmont | 77:869cf507173a | 601 | |
emilmont | 77:869cf507173a | 602 | \return 0 Interrupt status is not pending. |
emilmont | 77:869cf507173a | 603 | \return 1 Interrupt status is pending. |
emilmont | 77:869cf507173a | 604 | */ |
emilmont | 77:869cf507173a | 605 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
emilmont | 77:869cf507173a | 606 | { |
Kojto | 110:165afa46840b | 607 | return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
emilmont | 77:869cf507173a | 608 | } |
emilmont | 77:869cf507173a | 609 | |
emilmont | 77:869cf507173a | 610 | |
emilmont | 77:869cf507173a | 611 | /** \brief Set Pending Interrupt |
emilmont | 77:869cf507173a | 612 | |
emilmont | 77:869cf507173a | 613 | The function sets the pending bit of an external interrupt. |
emilmont | 77:869cf507173a | 614 | |
emilmont | 77:869cf507173a | 615 | \param [in] IRQn Interrupt number. Value cannot be negative. |
emilmont | 77:869cf507173a | 616 | */ |
emilmont | 77:869cf507173a | 617 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
emilmont | 77:869cf507173a | 618 | { |
Kojto | 110:165afa46840b | 619 | NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
emilmont | 77:869cf507173a | 620 | } |
emilmont | 77:869cf507173a | 621 | |
emilmont | 77:869cf507173a | 622 | |
emilmont | 77:869cf507173a | 623 | /** \brief Clear Pending Interrupt |
emilmont | 77:869cf507173a | 624 | |
emilmont | 77:869cf507173a | 625 | The function clears the pending bit of an external interrupt. |
emilmont | 77:869cf507173a | 626 | |
emilmont | 77:869cf507173a | 627 | \param [in] IRQn External interrupt number. Value cannot be negative. |
emilmont | 77:869cf507173a | 628 | */ |
emilmont | 77:869cf507173a | 629 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
emilmont | 77:869cf507173a | 630 | { |
Kojto | 110:165afa46840b | 631 | NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
emilmont | 77:869cf507173a | 632 | } |
emilmont | 77:869cf507173a | 633 | |
emilmont | 77:869cf507173a | 634 | |
emilmont | 77:869cf507173a | 635 | /** \brief Set Interrupt Priority |
emilmont | 77:869cf507173a | 636 | |
emilmont | 77:869cf507173a | 637 | The function sets the priority of an interrupt. |
emilmont | 77:869cf507173a | 638 | |
emilmont | 77:869cf507173a | 639 | \note The priority cannot be set for every core interrupt. |
emilmont | 77:869cf507173a | 640 | |
emilmont | 77:869cf507173a | 641 | \param [in] IRQn Interrupt number. |
emilmont | 77:869cf507173a | 642 | \param [in] priority Priority to set. |
emilmont | 77:869cf507173a | 643 | */ |
emilmont | 77:869cf507173a | 644 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
emilmont | 77:869cf507173a | 645 | { |
Kojto | 110:165afa46840b | 646 | if((int32_t)(IRQn) < 0) { |
Kojto | 110:165afa46840b | 647 | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
Kojto | 110:165afa46840b | 648 | (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
Kojto | 110:165afa46840b | 649 | } |
emilmont | 77:869cf507173a | 650 | else { |
Kojto | 110:165afa46840b | 651 | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
Kojto | 110:165afa46840b | 652 | (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
Kojto | 110:165afa46840b | 653 | } |
emilmont | 77:869cf507173a | 654 | } |
emilmont | 77:869cf507173a | 655 | |
emilmont | 77:869cf507173a | 656 | |
emilmont | 77:869cf507173a | 657 | /** \brief Get Interrupt Priority |
emilmont | 77:869cf507173a | 658 | |
emilmont | 77:869cf507173a | 659 | The function reads the priority of an interrupt. The interrupt |
emilmont | 77:869cf507173a | 660 | number can be positive to specify an external (device specific) |
emilmont | 77:869cf507173a | 661 | interrupt, or negative to specify an internal (core) interrupt. |
emilmont | 77:869cf507173a | 662 | |
emilmont | 77:869cf507173a | 663 | |
emilmont | 77:869cf507173a | 664 | \param [in] IRQn Interrupt number. |
emilmont | 77:869cf507173a | 665 | \return Interrupt Priority. Value is aligned automatically to the implemented |
emilmont | 77:869cf507173a | 666 | priority bits of the microcontroller. |
emilmont | 77:869cf507173a | 667 | */ |
emilmont | 77:869cf507173a | 668 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
emilmont | 77:869cf507173a | 669 | { |
emilmont | 77:869cf507173a | 670 | |
Kojto | 110:165afa46840b | 671 | if((int32_t)(IRQn) < 0) { |
Kojto | 110:165afa46840b | 672 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); |
Kojto | 110:165afa46840b | 673 | } |
emilmont | 77:869cf507173a | 674 | else { |
Kojto | 110:165afa46840b | 675 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); |
Kojto | 110:165afa46840b | 676 | } |
emilmont | 77:869cf507173a | 677 | } |
emilmont | 77:869cf507173a | 678 | |
emilmont | 77:869cf507173a | 679 | |
emilmont | 77:869cf507173a | 680 | /** \brief System Reset |
emilmont | 77:869cf507173a | 681 | |
emilmont | 77:869cf507173a | 682 | The function initiates a system reset request to reset the MCU. |
emilmont | 77:869cf507173a | 683 | */ |
emilmont | 77:869cf507173a | 684 | __STATIC_INLINE void NVIC_SystemReset(void) |
emilmont | 77:869cf507173a | 685 | { |
emilmont | 77:869cf507173a | 686 | __DSB(); /* Ensure all outstanding memory accesses included |
emilmont | 77:869cf507173a | 687 | buffered write are completed before reset */ |
Kojto | 110:165afa46840b | 688 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
emilmont | 77:869cf507173a | 689 | SCB_AIRCR_SYSRESETREQ_Msk); |
emilmont | 77:869cf507173a | 690 | __DSB(); /* Ensure completion of memory access */ |
Kojto | 110:165afa46840b | 691 | while(1) { __NOP(); } /* wait until reset */ |
emilmont | 77:869cf507173a | 692 | } |
emilmont | 77:869cf507173a | 693 | |
emilmont | 77:869cf507173a | 694 | /*@} end of CMSIS_Core_NVICFunctions */ |
emilmont | 77:869cf507173a | 695 | |
emilmont | 77:869cf507173a | 696 | |
emilmont | 77:869cf507173a | 697 | |
emilmont | 77:869cf507173a | 698 | /* ################################## SysTick function ############################################ */ |
emilmont | 77:869cf507173a | 699 | /** \ingroup CMSIS_Core_FunctionInterface |
emilmont | 77:869cf507173a | 700 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
emilmont | 77:869cf507173a | 701 | \brief Functions that configure the System. |
emilmont | 77:869cf507173a | 702 | @{ |
emilmont | 77:869cf507173a | 703 | */ |
emilmont | 77:869cf507173a | 704 | |
emilmont | 77:869cf507173a | 705 | #if (__Vendor_SysTickConfig == 0) |
emilmont | 77:869cf507173a | 706 | |
emilmont | 77:869cf507173a | 707 | /** \brief System Tick Configuration |
emilmont | 77:869cf507173a | 708 | |
emilmont | 77:869cf507173a | 709 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer. |
emilmont | 77:869cf507173a | 710 | Counter is in free running mode to generate periodic interrupts. |
emilmont | 77:869cf507173a | 711 | |
emilmont | 77:869cf507173a | 712 | \param [in] ticks Number of ticks between two interrupts. |
emilmont | 77:869cf507173a | 713 | |
emilmont | 77:869cf507173a | 714 | \return 0 Function succeeded. |
emilmont | 77:869cf507173a | 715 | \return 1 Function failed. |
emilmont | 77:869cf507173a | 716 | |
emilmont | 77:869cf507173a | 717 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
emilmont | 77:869cf507173a | 718 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
emilmont | 77:869cf507173a | 719 | must contain a vendor-specific implementation of this function. |
emilmont | 77:869cf507173a | 720 | |
emilmont | 77:869cf507173a | 721 | */ |
emilmont | 77:869cf507173a | 722 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
emilmont | 77:869cf507173a | 723 | { |
Kojto | 110:165afa46840b | 724 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ |
emilmont | 77:869cf507173a | 725 | |
Kojto | 110:165afa46840b | 726 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
Kojto | 110:165afa46840b | 727 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
Kojto | 110:165afa46840b | 728 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
emilmont | 77:869cf507173a | 729 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
emilmont | 77:869cf507173a | 730 | SysTick_CTRL_TICKINT_Msk | |
Kojto | 110:165afa46840b | 731 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
Kojto | 110:165afa46840b | 732 | return (0UL); /* Function successful */ |
emilmont | 77:869cf507173a | 733 | } |
emilmont | 77:869cf507173a | 734 | |
emilmont | 77:869cf507173a | 735 | #endif |
emilmont | 77:869cf507173a | 736 | |
emilmont | 77:869cf507173a | 737 | /*@} end of CMSIS_Core_SysTickFunctions */ |
emilmont | 77:869cf507173a | 738 | |
emilmont | 77:869cf507173a | 739 | |
emilmont | 77:869cf507173a | 740 | |
emilmont | 77:869cf507173a | 741 | |
Kojto | 110:165afa46840b | 742 | #ifdef __cplusplus |
Kojto | 110:165afa46840b | 743 | } |
Kojto | 110:165afa46840b | 744 | #endif |
Kojto | 110:165afa46840b | 745 | |
emilmont | 77:869cf507173a | 746 | #endif /* __CORE_CM0_H_DEPENDANT */ |
emilmont | 77:869cf507173a | 747 | |
emilmont | 77:869cf507173a | 748 | #endif /* __CMSIS_GENERIC */ |