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TARGET_NUCLEO_L011K4/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.h@132:9baf128c2fab, 2016-12-20 (annotated)
- Committer:
- <>
- Date:
- Tue Dec 20 15:36:52 2016 +0000
- Revision:
- 132:9baf128c2fab
- Parent:
- 130:d75b3fe1f5cb
Release 132 of the mbed library
Ports for Upcoming Targets
3241: Add support for FRDM-KW41 https://github.com/ARMmbed/mbed-os/pull/3241
3291: Adding mbed enabled Maker board with NINA-B1 and EVA-M8Q https://github.com/ARMmbed/mbed-os/pull/3291
Fixes and Changes
3062: TARGET_STM :USB device FS https://github.com/ARMmbed/mbed-os/pull/3062
3213: STM32: Refactor us_ticker.c + hal_tick.c files https://github.com/ARMmbed/mbed-os/pull/3213
3288: Dev spi asynch l0l1 https://github.com/ARMmbed/mbed-os/pull/3288
3289: Bug fix of initial value of interrupt edge in "gpio_irq_init" function. https://github.com/ARMmbed/mbed-os/pull/3289
3302: STM32F4 AnalogIn - Clear VBATE and TSVREFE bits before configuring ADC channels https://github.com/ARMmbed/mbed-os/pull/3302
3320: STM32 - Add ADC_VREF label https://github.com/ARMmbed/mbed-os/pull/3320
3321: no HSE available by default for NUCLEO_L432KC https://github.com/ARMmbed/mbed-os/pull/3321
3352: ublox eva nina - fix line endings https://github.com/ARMmbed/mbed-os/pull/3352
3322: DISCO_L053C8 doesn't support LSE https://github.com/ARMmbed/mbed-os/pull/3322
3345: STM32 - Remove TIM_IT_UPDATE flag in HAL_Suspend/ResumeTick functions https://github.com/ARMmbed/mbed-os/pull/3345
3309: [NUC472/M453] Fix CI failed tests https://github.com/ARMmbed/mbed-os/pull/3309
3157: [Silicon Labs] Adding support for EFR32MG1 wireless SoC https://github.com/ARMmbed/mbed-os/pull/3157
3301: I2C - correct return values for write functions (docs) - part 1 https://github.com/ARMmbed/mbed-os/pull/3301
3303: Fix #2956 #2939 #2957 #2959 #2960: Add HAL_DeInit function in gpio_irq destructor https://github.com/ARMmbed/mbed-os/pull/3303
3304: STM32L476: no HSE is present in NUCLEO and DISCO boards https://github.com/ARMmbed/mbed-os/pull/3304
3318: Register map changes for RevG https://github.com/ARMmbed/mbed-os/pull/3318
3317: NUCLEO_F429ZI has integrated LSE https://github.com/ARMmbed/mbed-os/pull/3317
3312: K64F: SPI Asynch API implementation https://github.com/ARMmbed/mbed-os/pull/3312
3324: Dev i2c common code https://github.com/ARMmbed/mbed-os/pull/3324
3369: Add CAN2 missing pins for connector CN12 https://github.com/ARMmbed/mbed-os/pull/3369
3377: STM32 NUCLEO-L152RE Update system core clock to 32MHz https://github.com/ARMmbed/mbed-os/pull/3377
3378: K66F: Enable LWIP feature https://github.com/ARMmbed/mbed-os/pull/3378
3382: [MAX32620] Fixing serial readable function. https://github.com/ARMmbed/mbed-os/pull/3382
3399: NUCLEO_F103RB - Add SERIAL_FC feature https://github.com/ARMmbed/mbed-os/pull/3399
3409: STM32L1 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3409
3416: Renames i2c_api.c for STM32F1 targets to fix IAR exporter https://github.com/ARMmbed/mbed-os/pull/3416
3348: Fix frequency function of CAN driver. https://github.com/ARMmbed/mbed-os/pull/3348
3366: NUCLEO_F412ZG - Add new platform https://github.com/ARMmbed/mbed-os/pull/3366
3379: STM32F0 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3379
3393: ISR register never re-evaluated in HAL_DMA_PollForTransfer for STM32F4 https://github.com/ARMmbed/mbed-os/pull/3393
3408: STM32F7 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3408
3411: STM32L0 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3411
3424: STM32F4 - FIX to add the update of hdma->State variable https://github.com/ARMmbed/mbed-os/pull/3424
3427: Fix stm i2c slave https://github.com/ARMmbed/mbed-os/pull/3427
3429: Fix stm i2c fix init https://github.com/ARMmbed/mbed-os/pull/3429
3434: [NUC472/M453] Fix stuck in lp_ticker_init and other updates https://github.com/ARMmbed/mbed-os/pull/3434
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 84:0b3ab51c8877 | 1 | /** |
| bogdanm | 84:0b3ab51c8877 | 2 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 3 | * @file stm32l0xx_hal_dma.h |
| bogdanm | 84:0b3ab51c8877 | 4 | * @author MCD Application Team |
| <> | 132:9baf128c2fab | 5 | * @version $VERSION$ |
| <> | 132:9baf128c2fab | 6 | * @date $DATE$ |
| bogdanm | 84:0b3ab51c8877 | 7 | * @brief Header file of DMA HAL module. |
| bogdanm | 84:0b3ab51c8877 | 8 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 9 | * @attention |
| bogdanm | 84:0b3ab51c8877 | 10 | * |
| Kojto | 119:aae6fcc7d9bb | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| bogdanm | 84:0b3ab51c8877 | 12 | * |
| bogdanm | 84:0b3ab51c8877 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 84:0b3ab51c8877 | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 84:0b3ab51c8877 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 84:0b3ab51c8877 | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 84:0b3ab51c8877 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 84:0b3ab51c8877 | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 84:0b3ab51c8877 | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 84:0b3ab51c8877 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 84:0b3ab51c8877 | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 84:0b3ab51c8877 | 22 | * without specific prior written permission. |
| bogdanm | 84:0b3ab51c8877 | 23 | * |
| bogdanm | 84:0b3ab51c8877 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 84:0b3ab51c8877 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 84:0b3ab51c8877 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 84:0b3ab51c8877 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 84:0b3ab51c8877 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 84:0b3ab51c8877 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 84:0b3ab51c8877 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 84:0b3ab51c8877 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 84:0b3ab51c8877 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 84:0b3ab51c8877 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 84:0b3ab51c8877 | 34 | * |
| bogdanm | 84:0b3ab51c8877 | 35 | ****************************************************************************** |
| bogdanm | 84:0b3ab51c8877 | 36 | */ |
| bogdanm | 84:0b3ab51c8877 | 37 | |
| bogdanm | 84:0b3ab51c8877 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 39 | #ifndef __STM32L0xx_HAL_DMA_H |
| bogdanm | 84:0b3ab51c8877 | 40 | #define __STM32L0xx_HAL_DMA_H |
| bogdanm | 84:0b3ab51c8877 | 41 | |
| bogdanm | 84:0b3ab51c8877 | 42 | #ifdef __cplusplus |
| bogdanm | 84:0b3ab51c8877 | 43 | extern "C" { |
| bogdanm | 84:0b3ab51c8877 | 44 | #endif |
| bogdanm | 84:0b3ab51c8877 | 45 | |
| bogdanm | 84:0b3ab51c8877 | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 47 | #include "stm32l0xx_hal_def.h" |
| bogdanm | 84:0b3ab51c8877 | 48 | |
| bogdanm | 84:0b3ab51c8877 | 49 | /** @addtogroup STM32L0xx_HAL_Driver |
| bogdanm | 84:0b3ab51c8877 | 50 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 51 | */ |
| bogdanm | 84:0b3ab51c8877 | 52 | |
| Kojto | 96:487b796308b0 | 53 | /** @defgroup DMA DMA |
| bogdanm | 84:0b3ab51c8877 | 54 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 55 | */ |
| bogdanm | 84:0b3ab51c8877 | 56 | |
| Kojto | 119:aae6fcc7d9bb | 57 | /** @defgroup DMA_Exported_Types DMA Exported Types |
| Kojto | 119:aae6fcc7d9bb | 58 | * @{ |
| Kojto | 119:aae6fcc7d9bb | 59 | */ |
| bogdanm | 84:0b3ab51c8877 | 60 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 61 | |
| bogdanm | 84:0b3ab51c8877 | 62 | /** |
| bogdanm | 84:0b3ab51c8877 | 63 | * @brief DMA Configuration Structure definition |
| bogdanm | 84:0b3ab51c8877 | 64 | */ |
| bogdanm | 84:0b3ab51c8877 | 65 | typedef struct |
| bogdanm | 84:0b3ab51c8877 | 66 | { |
| bogdanm | 84:0b3ab51c8877 | 67 | uint32_t Request; /*!< Specifies the request selected for the specified channel. |
| bogdanm | 84:0b3ab51c8877 | 68 | This parameter can be a value of @ref DMA_request */ |
| bogdanm | 84:0b3ab51c8877 | 69 | |
| bogdanm | 84:0b3ab51c8877 | 70 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| bogdanm | 84:0b3ab51c8877 | 71 | from memory to memory or from peripheral to memory. |
| bogdanm | 92:4fc01daae5a5 | 72 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| bogdanm | 84:0b3ab51c8877 | 73 | |
| bogdanm | 84:0b3ab51c8877 | 74 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| Kojto | 96:487b796308b0 | 75 | When Memory to Memory transfer is used, this is the Source Increment mode |
| bogdanm | 92:4fc01daae5a5 | 76 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| bogdanm | 84:0b3ab51c8877 | 77 | |
| bogdanm | 84:0b3ab51c8877 | 78 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| Kojto | 96:487b796308b0 | 79 | When Memory to Memory transfer is used, this is the Destination Increment mode |
| bogdanm | 92:4fc01daae5a5 | 80 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| bogdanm | 84:0b3ab51c8877 | 81 | |
| bogdanm | 84:0b3ab51c8877 | 82 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| Kojto | 96:487b796308b0 | 83 | When Memory to Memory transfer is used, this is the Source Alignment format |
| bogdanm | 92:4fc01daae5a5 | 84 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| bogdanm | 84:0b3ab51c8877 | 85 | |
| bogdanm | 84:0b3ab51c8877 | 86 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| Kojto | 96:487b796308b0 | 87 | When Memory to Memory transfer is used, this is the Destination Alignment format |
| bogdanm | 92:4fc01daae5a5 | 88 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| bogdanm | 84:0b3ab51c8877 | 89 | |
| Kojto | 96:487b796308b0 | 90 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx (Normal or Circular). |
| bogdanm | 84:0b3ab51c8877 | 91 | This parameter can be a value of @ref DMA_mode |
| bogdanm | 84:0b3ab51c8877 | 92 | @note The circular buffer mode cannot be used if the memory-to-memory |
| bogdanm | 84:0b3ab51c8877 | 93 | data transfer is configured on the selected Channel */ |
| bogdanm | 84:0b3ab51c8877 | 94 | |
| bogdanm | 84:0b3ab51c8877 | 95 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. |
| bogdanm | 92:4fc01daae5a5 | 96 | This parameter can be a value of @ref DMA_Priority_level */ |
| bogdanm | 84:0b3ab51c8877 | 97 | } DMA_InitTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 98 | |
| bogdanm | 84:0b3ab51c8877 | 99 | /** |
| bogdanm | 84:0b3ab51c8877 | 100 | * @brief DMA Configuration enumeration values definition |
| bogdanm | 84:0b3ab51c8877 | 101 | */ |
| bogdanm | 84:0b3ab51c8877 | 102 | typedef enum |
| bogdanm | 84:0b3ab51c8877 | 103 | { |
| <> | 130:d75b3fe1f5cb | 104 | DMA_MODE = 0U, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ |
| <> | 130:d75b3fe1f5cb | 105 | DMA_PRIORITY = 1U, /*!< Control related priority level Parameter in DMA_InitTypeDef */ |
| bogdanm | 84:0b3ab51c8877 | 106 | |
| bogdanm | 84:0b3ab51c8877 | 107 | } DMA_ControlTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 108 | |
| bogdanm | 84:0b3ab51c8877 | 109 | /** |
| bogdanm | 84:0b3ab51c8877 | 110 | * @brief HAL DMA State structures definition |
| bogdanm | 84:0b3ab51c8877 | 111 | */ |
| bogdanm | 84:0b3ab51c8877 | 112 | typedef enum |
| bogdanm | 84:0b3ab51c8877 | 113 | { |
| <> | 130:d75b3fe1f5cb | 114 | HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ |
| <> | 130:d75b3fe1f5cb | 115 | HAL_DMA_STATE_READY = 0x01U, /*!< DMA process success and ready for use */ |
| <> | 130:d75b3fe1f5cb | 116 | HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ |
| <> | 130:d75b3fe1f5cb | 117 | HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ |
| <> | 130:d75b3fe1f5cb | 118 | HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ |
| <> | 130:d75b3fe1f5cb | 119 | HAL_DMA_STATE_READY_HALF = 0x05U, /*!< DMA Half process success */ |
| bogdanm | 84:0b3ab51c8877 | 120 | }HAL_DMA_StateTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 121 | |
| bogdanm | 84:0b3ab51c8877 | 122 | /** |
| bogdanm | 84:0b3ab51c8877 | 123 | * @brief HAL DMA Error Code structure definition |
| bogdanm | 84:0b3ab51c8877 | 124 | */ |
| bogdanm | 84:0b3ab51c8877 | 125 | typedef enum |
| bogdanm | 84:0b3ab51c8877 | 126 | { |
| <> | 130:d75b3fe1f5cb | 127 | HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ |
| <> | 130:d75b3fe1f5cb | 128 | HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ |
| bogdanm | 84:0b3ab51c8877 | 129 | |
| bogdanm | 84:0b3ab51c8877 | 130 | }HAL_DMA_LevelCompleteTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 131 | |
| bogdanm | 84:0b3ab51c8877 | 132 | |
| bogdanm | 84:0b3ab51c8877 | 133 | /** |
| bogdanm | 84:0b3ab51c8877 | 134 | * @brief DMA handle Structure definition |
| bogdanm | 84:0b3ab51c8877 | 135 | */ |
| bogdanm | 84:0b3ab51c8877 | 136 | typedef struct __DMA_HandleTypeDef |
| bogdanm | 84:0b3ab51c8877 | 137 | { |
| bogdanm | 84:0b3ab51c8877 | 138 | DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
| bogdanm | 84:0b3ab51c8877 | 139 | |
| bogdanm | 84:0b3ab51c8877 | 140 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| bogdanm | 84:0b3ab51c8877 | 141 | |
| <> | 132:9baf128c2fab | 142 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| bogdanm | 84:0b3ab51c8877 | 143 | |
| bogdanm | 84:0b3ab51c8877 | 144 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| bogdanm | 84:0b3ab51c8877 | 145 | |
| <> | 132:9baf128c2fab | 146 | void *Parent; /*!< Parent object state */ |
| bogdanm | 84:0b3ab51c8877 | 147 | |
| bogdanm | 84:0b3ab51c8877 | 148 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| bogdanm | 84:0b3ab51c8877 | 149 | |
| bogdanm | 84:0b3ab51c8877 | 150 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| bogdanm | 84:0b3ab51c8877 | 151 | |
| bogdanm | 84:0b3ab51c8877 | 152 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| <> | 132:9baf128c2fab | 153 | |
| <> | 132:9baf128c2fab | 154 | void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ |
| <> | 132:9baf128c2fab | 155 | |
| <> | 132:9baf128c2fab | 156 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| bogdanm | 84:0b3ab51c8877 | 157 | |
| bogdanm | 84:0b3ab51c8877 | 158 | } DMA_HandleTypeDef; |
| bogdanm | 84:0b3ab51c8877 | 159 | |
| Kojto | 119:aae6fcc7d9bb | 160 | /** |
| Kojto | 119:aae6fcc7d9bb | 161 | * @} |
| Kojto | 119:aae6fcc7d9bb | 162 | */ |
| Kojto | 119:aae6fcc7d9bb | 163 | |
| bogdanm | 84:0b3ab51c8877 | 164 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 165 | |
| Kojto | 96:487b796308b0 | 166 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
| bogdanm | 84:0b3ab51c8877 | 167 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 168 | */ |
| bogdanm | 84:0b3ab51c8877 | 169 | |
| Kojto | 96:487b796308b0 | 170 | /** @defgroup DMA_Error_Code DMA Error Codes |
| bogdanm | 84:0b3ab51c8877 | 171 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 172 | */ |
| <> | 130:d75b3fe1f5cb | 173 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
| <> | 130:d75b3fe1f5cb | 174 | #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ |
| <> | 132:9baf128c2fab | 175 | #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< no ongoing transfer */ |
| <> | 130:d75b3fe1f5cb | 176 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ |
| bogdanm | 84:0b3ab51c8877 | 177 | |
| Kojto | 119:aae6fcc7d9bb | 178 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| Kojto | 119:aae6fcc7d9bb | 179 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
| Kojto | 119:aae6fcc7d9bb | 180 | ((INSTANCE) == DMA1_Channel2) || \ |
| Kojto | 119:aae6fcc7d9bb | 181 | ((INSTANCE) == DMA1_Channel3) || \ |
| Kojto | 119:aae6fcc7d9bb | 182 | ((INSTANCE) == DMA1_Channel4) || \ |
| Kojto | 119:aae6fcc7d9bb | 183 | ((INSTANCE) == DMA1_Channel5)) |
| Kojto | 119:aae6fcc7d9bb | 184 | #else |
| Kojto | 119:aae6fcc7d9bb | 185 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
| Kojto | 119:aae6fcc7d9bb | 186 | ((INSTANCE) == DMA1_Channel2) || \ |
| Kojto | 119:aae6fcc7d9bb | 187 | ((INSTANCE) == DMA1_Channel3) || \ |
| Kojto | 119:aae6fcc7d9bb | 188 | ((INSTANCE) == DMA1_Channel4) || \ |
| Kojto | 119:aae6fcc7d9bb | 189 | ((INSTANCE) == DMA1_Channel5) || \ |
| Kojto | 119:aae6fcc7d9bb | 190 | ((INSTANCE) == DMA1_Channel6) || \ |
| Kojto | 119:aae6fcc7d9bb | 191 | ((INSTANCE) == DMA1_Channel7)) |
| bogdanm | 84:0b3ab51c8877 | 192 | |
| Kojto | 119:aae6fcc7d9bb | 193 | #endif |
| bogdanm | 84:0b3ab51c8877 | 194 | #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1)) |
| bogdanm | 84:0b3ab51c8877 | 195 | |
| bogdanm | 84:0b3ab51c8877 | 196 | /** |
| bogdanm | 84:0b3ab51c8877 | 197 | * @} |
| bogdanm | 84:0b3ab51c8877 | 198 | */ |
| bogdanm | 84:0b3ab51c8877 | 199 | |
| Kojto | 96:487b796308b0 | 200 | /** @defgroup DMA_request DMA request defintiions |
| bogdanm | 84:0b3ab51c8877 | 201 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 202 | */ |
| Kojto | 96:487b796308b0 | 203 | |
| Kojto | 96:487b796308b0 | 204 | #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
| Kojto | 96:487b796308b0 | 205 | |
| <> | 130:d75b3fe1f5cb | 206 | #define DMA_REQUEST_0 ((uint32_t)0x00000000U) |
| <> | 130:d75b3fe1f5cb | 207 | #define DMA_REQUEST_1 ((uint32_t)0x00000001U) |
| <> | 130:d75b3fe1f5cb | 208 | #define DMA_REQUEST_2 ((uint32_t)0x00000002U) |
| <> | 130:d75b3fe1f5cb | 209 | #define DMA_REQUEST_3 ((uint32_t)0x00000003U) |
| <> | 130:d75b3fe1f5cb | 210 | #define DMA_REQUEST_4 ((uint32_t)0x00000004U) |
| <> | 130:d75b3fe1f5cb | 211 | #define DMA_REQUEST_5 ((uint32_t)0x00000005U) |
| <> | 130:d75b3fe1f5cb | 212 | #define DMA_REQUEST_6 ((uint32_t)0x00000006U) |
| <> | 130:d75b3fe1f5cb | 213 | #define DMA_REQUEST_7 ((uint32_t)0x00000007U) |
| <> | 130:d75b3fe1f5cb | 214 | #define DMA_REQUEST_8 ((uint32_t)0x00000008U) |
| <> | 130:d75b3fe1f5cb | 215 | #define DMA_REQUEST_9 ((uint32_t)0x00000009U) |
| <> | 130:d75b3fe1f5cb | 216 | #define DMA_REQUEST_10 ((uint32_t)0x0000000AU) |
| <> | 130:d75b3fe1f5cb | 217 | #define DMA_REQUEST_11 ((uint32_t)0x0000000BU) |
| <> | 130:d75b3fe1f5cb | 218 | #define DMA_REQUEST_12 ((uint32_t)0x0000000CU) |
| <> | 130:d75b3fe1f5cb | 219 | #define DMA_REQUEST_13 ((uint32_t)0x0000000DU) |
| <> | 130:d75b3fe1f5cb | 220 | #define DMA_REQUEST_14 ((uint32_t)0x0000000EU) |
| <> | 130:d75b3fe1f5cb | 221 | #define DMA_REQUEST_15 ((uint32_t)0x0000000FU) |
| Kojto | 96:487b796308b0 | 222 | |
| Kojto | 96:487b796308b0 | 223 | #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ |
| Kojto | 96:487b796308b0 | 224 | ((REQUEST) == DMA_REQUEST_1) || \ |
| Kojto | 96:487b796308b0 | 225 | ((REQUEST) == DMA_REQUEST_2) || \ |
| Kojto | 96:487b796308b0 | 226 | ((REQUEST) == DMA_REQUEST_3) || \ |
| Kojto | 96:487b796308b0 | 227 | ((REQUEST) == DMA_REQUEST_4) || \ |
| Kojto | 96:487b796308b0 | 228 | ((REQUEST) == DMA_REQUEST_5) || \ |
| Kojto | 96:487b796308b0 | 229 | ((REQUEST) == DMA_REQUEST_6) || \ |
| Kojto | 96:487b796308b0 | 230 | ((REQUEST) == DMA_REQUEST_7) || \ |
| Kojto | 96:487b796308b0 | 231 | ((REQUEST) == DMA_REQUEST_8) || \ |
| Kojto | 96:487b796308b0 | 232 | ((REQUEST) == DMA_REQUEST_9) || \ |
| Kojto | 96:487b796308b0 | 233 | ((REQUEST) == DMA_REQUEST_10) || \ |
| Kojto | 96:487b796308b0 | 234 | ((REQUEST) == DMA_REQUEST_11) || \ |
| Kojto | 96:487b796308b0 | 235 | ((REQUEST) == DMA_REQUEST_12) || \ |
| Kojto | 96:487b796308b0 | 236 | ((REQUEST) == DMA_REQUEST_13) || \ |
| Kojto | 96:487b796308b0 | 237 | ((REQUEST) == DMA_REQUEST_14) || \ |
| Kojto | 96:487b796308b0 | 238 | ((REQUEST) == DMA_REQUEST_15)) |
| Kojto | 96:487b796308b0 | 239 | |
| Kojto | 96:487b796308b0 | 240 | #else /* #if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ |
| Kojto | 96:487b796308b0 | 241 | |
| <> | 130:d75b3fe1f5cb | 242 | #define DMA_REQUEST_0 ((uint32_t)0x00000000U) |
| <> | 130:d75b3fe1f5cb | 243 | #define DMA_REQUEST_1 ((uint32_t)0x00000001U) |
| <> | 130:d75b3fe1f5cb | 244 | #define DMA_REQUEST_2 ((uint32_t)0x00000002U) |
| <> | 130:d75b3fe1f5cb | 245 | #define DMA_REQUEST_3 ((uint32_t)0x00000003U) |
| <> | 130:d75b3fe1f5cb | 246 | #define DMA_REQUEST_4 ((uint32_t)0x00000004U) |
| <> | 130:d75b3fe1f5cb | 247 | #define DMA_REQUEST_5 ((uint32_t)0x00000005U) |
| <> | 130:d75b3fe1f5cb | 248 | #define DMA_REQUEST_6 ((uint32_t)0x00000006U) |
| <> | 130:d75b3fe1f5cb | 249 | #define DMA_REQUEST_7 ((uint32_t)0x00000007U) |
| <> | 130:d75b3fe1f5cb | 250 | #define DMA_REQUEST_8 ((uint32_t)0x00000008U) |
| <> | 130:d75b3fe1f5cb | 251 | #define DMA_REQUEST_9 ((uint32_t)0x00000009U) |
| <> | 130:d75b3fe1f5cb | 252 | #define DMA_REQUEST_11 ((uint32_t)0x0000000BU) |
| bogdanm | 84:0b3ab51c8877 | 253 | |
| bogdanm | 84:0b3ab51c8877 | 254 | #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ |
| bogdanm | 84:0b3ab51c8877 | 255 | ((REQUEST) == DMA_REQUEST_1) || \ |
| bogdanm | 84:0b3ab51c8877 | 256 | ((REQUEST) == DMA_REQUEST_2) || \ |
| bogdanm | 84:0b3ab51c8877 | 257 | ((REQUEST) == DMA_REQUEST_3) || \ |
| bogdanm | 84:0b3ab51c8877 | 258 | ((REQUEST) == DMA_REQUEST_4) || \ |
| bogdanm | 84:0b3ab51c8877 | 259 | ((REQUEST) == DMA_REQUEST_5) || \ |
| bogdanm | 84:0b3ab51c8877 | 260 | ((REQUEST) == DMA_REQUEST_6) || \ |
| bogdanm | 84:0b3ab51c8877 | 261 | ((REQUEST) == DMA_REQUEST_7) || \ |
| bogdanm | 84:0b3ab51c8877 | 262 | ((REQUEST) == DMA_REQUEST_8) || \ |
| bogdanm | 84:0b3ab51c8877 | 263 | ((REQUEST) == DMA_REQUEST_9) || \ |
| bogdanm | 84:0b3ab51c8877 | 264 | ((REQUEST) == DMA_REQUEST_11)) |
| Kojto | 96:487b796308b0 | 265 | #endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */ |
| Kojto | 96:487b796308b0 | 266 | |
| bogdanm | 84:0b3ab51c8877 | 267 | /** |
| bogdanm | 84:0b3ab51c8877 | 268 | * @} |
| bogdanm | 84:0b3ab51c8877 | 269 | */ |
| bogdanm | 84:0b3ab51c8877 | 270 | |
| Kojto | 96:487b796308b0 | 271 | /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions |
| bogdanm | 84:0b3ab51c8877 | 272 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 273 | */ |
| <> | 130:d75b3fe1f5cb | 274 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ |
| bogdanm | 84:0b3ab51c8877 | 275 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
| bogdanm | 84:0b3ab51c8877 | 276 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ |
| bogdanm | 84:0b3ab51c8877 | 277 | |
| bogdanm | 84:0b3ab51c8877 | 278 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| bogdanm | 84:0b3ab51c8877 | 279 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| bogdanm | 84:0b3ab51c8877 | 280 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| bogdanm | 84:0b3ab51c8877 | 281 | /** |
| bogdanm | 84:0b3ab51c8877 | 282 | * @} |
| bogdanm | 84:0b3ab51c8877 | 283 | */ |
| bogdanm | 84:0b3ab51c8877 | 284 | |
| Kojto | 119:aae6fcc7d9bb | 285 | /** @defgroup DMA_Data_buffer_size DMA Data Buffer Size Check |
| bogdanm | 84:0b3ab51c8877 | 286 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 287 | */ |
| bogdanm | 84:0b3ab51c8877 | 288 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| bogdanm | 84:0b3ab51c8877 | 289 | /** |
| bogdanm | 84:0b3ab51c8877 | 290 | * @} |
| bogdanm | 84:0b3ab51c8877 | 291 | */ |
| bogdanm | 84:0b3ab51c8877 | 292 | |
| Kojto | 119:aae6fcc7d9bb | 293 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral Incremented Mode |
| bogdanm | 84:0b3ab51c8877 | 294 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 295 | */ |
| bogdanm | 84:0b3ab51c8877 | 296 | #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
| <> | 130:d75b3fe1f5cb | 297 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */ |
| bogdanm | 84:0b3ab51c8877 | 298 | |
| bogdanm | 84:0b3ab51c8877 | 299 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 300 | ((STATE) == DMA_PINC_DISABLE)) |
| bogdanm | 84:0b3ab51c8877 | 301 | /** |
| bogdanm | 84:0b3ab51c8877 | 302 | * @} |
| bogdanm | 84:0b3ab51c8877 | 303 | */ |
| bogdanm | 84:0b3ab51c8877 | 304 | |
| Kojto | 119:aae6fcc7d9bb | 305 | /** @defgroup DMA_Memory_incremented_mode DMA Memory Incremented Mode |
| bogdanm | 84:0b3ab51c8877 | 306 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 307 | */ |
| bogdanm | 84:0b3ab51c8877 | 308 | #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
| <> | 130:d75b3fe1f5cb | 309 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */ |
| bogdanm | 84:0b3ab51c8877 | 310 | |
| bogdanm | 84:0b3ab51c8877 | 311 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| bogdanm | 84:0b3ab51c8877 | 312 | ((STATE) == DMA_MINC_DISABLE)) |
| bogdanm | 84:0b3ab51c8877 | 313 | /** |
| bogdanm | 84:0b3ab51c8877 | 314 | * @} |
| bogdanm | 84:0b3ab51c8877 | 315 | */ |
| bogdanm | 84:0b3ab51c8877 | 316 | |
| Kojto | 119:aae6fcc7d9bb | 317 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral Data Size Alignment |
| bogdanm | 84:0b3ab51c8877 | 318 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 319 | */ |
| <> | 130:d75b3fe1f5cb | 320 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */ |
| bogdanm | 84:0b3ab51c8877 | 321 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ |
| bogdanm | 84:0b3ab51c8877 | 322 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ |
| bogdanm | 84:0b3ab51c8877 | 323 | |
| bogdanm | 84:0b3ab51c8877 | 324 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| bogdanm | 84:0b3ab51c8877 | 325 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| bogdanm | 84:0b3ab51c8877 | 326 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| bogdanm | 84:0b3ab51c8877 | 327 | /** |
| bogdanm | 84:0b3ab51c8877 | 328 | * @} |
| bogdanm | 84:0b3ab51c8877 | 329 | */ |
| bogdanm | 84:0b3ab51c8877 | 330 | |
| bogdanm | 84:0b3ab51c8877 | 331 | |
| Kojto | 119:aae6fcc7d9bb | 332 | /** @defgroup DMA_Memory_data_size DMA Memory Data Size Alignment |
| bogdanm | 84:0b3ab51c8877 | 333 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 334 | */ |
| <> | 130:d75b3fe1f5cb | 335 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */ |
| bogdanm | 84:0b3ab51c8877 | 336 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ |
| bogdanm | 84:0b3ab51c8877 | 337 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ |
| bogdanm | 84:0b3ab51c8877 | 338 | |
| bogdanm | 84:0b3ab51c8877 | 339 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| bogdanm | 84:0b3ab51c8877 | 340 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| bogdanm | 84:0b3ab51c8877 | 341 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| bogdanm | 84:0b3ab51c8877 | 342 | /** |
| bogdanm | 84:0b3ab51c8877 | 343 | * @} |
| bogdanm | 84:0b3ab51c8877 | 344 | */ |
| bogdanm | 84:0b3ab51c8877 | 345 | |
| Kojto | 119:aae6fcc7d9bb | 346 | /** @defgroup DMA_mode DMA Mode |
| bogdanm | 84:0b3ab51c8877 | 347 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 348 | */ |
| <> | 130:d75b3fe1f5cb | 349 | #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */ |
| bogdanm | 84:0b3ab51c8877 | 350 | #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ |
| bogdanm | 84:0b3ab51c8877 | 351 | |
| bogdanm | 84:0b3ab51c8877 | 352 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| bogdanm | 84:0b3ab51c8877 | 353 | ((MODE) == DMA_CIRCULAR)) |
| bogdanm | 84:0b3ab51c8877 | 354 | /** |
| bogdanm | 84:0b3ab51c8877 | 355 | * @} |
| bogdanm | 84:0b3ab51c8877 | 356 | */ |
| bogdanm | 84:0b3ab51c8877 | 357 | |
| Kojto | 119:aae6fcc7d9bb | 358 | /** @defgroup DMA_Priority_level DMA Priority Level |
| bogdanm | 84:0b3ab51c8877 | 359 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 360 | */ |
| <> | 130:d75b3fe1f5cb | 361 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */ |
| bogdanm | 84:0b3ab51c8877 | 362 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
| bogdanm | 84:0b3ab51c8877 | 363 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
| bogdanm | 84:0b3ab51c8877 | 364 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
| bogdanm | 84:0b3ab51c8877 | 365 | |
| bogdanm | 84:0b3ab51c8877 | 366 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| bogdanm | 84:0b3ab51c8877 | 367 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| bogdanm | 84:0b3ab51c8877 | 368 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| bogdanm | 84:0b3ab51c8877 | 369 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| bogdanm | 84:0b3ab51c8877 | 370 | /** |
| bogdanm | 84:0b3ab51c8877 | 371 | * @} |
| bogdanm | 84:0b3ab51c8877 | 372 | */ |
| bogdanm | 84:0b3ab51c8877 | 373 | |
| bogdanm | 84:0b3ab51c8877 | 374 | |
| Kojto | 119:aae6fcc7d9bb | 375 | /** @defgroup DMA_interrupt_enable_definitions DMA Interrupt Definitions |
| bogdanm | 84:0b3ab51c8877 | 376 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 377 | */ |
| bogdanm | 84:0b3ab51c8877 | 378 | |
| bogdanm | 84:0b3ab51c8877 | 379 | #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
| bogdanm | 84:0b3ab51c8877 | 380 | #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
| bogdanm | 84:0b3ab51c8877 | 381 | #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
| bogdanm | 84:0b3ab51c8877 | 382 | |
| bogdanm | 84:0b3ab51c8877 | 383 | /** |
| bogdanm | 84:0b3ab51c8877 | 384 | * @} |
| bogdanm | 84:0b3ab51c8877 | 385 | */ |
| bogdanm | 84:0b3ab51c8877 | 386 | |
| Kojto | 119:aae6fcc7d9bb | 387 | /** @defgroup DMA_flag_definitions DMA Flag Definitions |
| bogdanm | 84:0b3ab51c8877 | 388 | * @{ |
| bogdanm | 84:0b3ab51c8877 | 389 | */ |
| bogdanm | 84:0b3ab51c8877 | 390 | |
| <> | 130:d75b3fe1f5cb | 391 | #define DMA_FLAG_GL1 ((uint32_t)0x00000001U) |
| <> | 130:d75b3fe1f5cb | 392 | #define DMA_FLAG_TC1 ((uint32_t)0x00000002U) |
| <> | 130:d75b3fe1f5cb | 393 | #define DMA_FLAG_HT1 ((uint32_t)0x00000004U) |
| <> | 130:d75b3fe1f5cb | 394 | #define DMA_FLAG_TE1 ((uint32_t)0x00000008U) |
| <> | 130:d75b3fe1f5cb | 395 | #define DMA_FLAG_GL2 ((uint32_t)0x00000010U) |
| <> | 130:d75b3fe1f5cb | 396 | #define DMA_FLAG_TC2 ((uint32_t)0x00000020U) |
| <> | 130:d75b3fe1f5cb | 397 | #define DMA_FLAG_HT2 ((uint32_t)0x00000040U) |
| <> | 130:d75b3fe1f5cb | 398 | #define DMA_FLAG_TE2 ((uint32_t)0x00000080U) |
| <> | 130:d75b3fe1f5cb | 399 | #define DMA_FLAG_GL3 ((uint32_t)0x00000100U) |
| <> | 130:d75b3fe1f5cb | 400 | #define DMA_FLAG_TC3 ((uint32_t)0x00000200U) |
| <> | 130:d75b3fe1f5cb | 401 | #define DMA_FLAG_HT3 ((uint32_t)0x00000400U) |
| <> | 130:d75b3fe1f5cb | 402 | #define DMA_FLAG_TE3 ((uint32_t)0x00000800U) |
| <> | 130:d75b3fe1f5cb | 403 | #define DMA_FLAG_GL4 ((uint32_t)0x00001000U) |
| <> | 130:d75b3fe1f5cb | 404 | #define DMA_FLAG_TC4 ((uint32_t)0x00002000U) |
| <> | 130:d75b3fe1f5cb | 405 | #define DMA_FLAG_HT4 ((uint32_t)0x00004000U) |
| <> | 130:d75b3fe1f5cb | 406 | #define DMA_FLAG_TE4 ((uint32_t)0x00008000U) |
| <> | 130:d75b3fe1f5cb | 407 | #define DMA_FLAG_GL5 ((uint32_t)0x00010000U) |
| <> | 130:d75b3fe1f5cb | 408 | #define DMA_FLAG_TC5 ((uint32_t)0x00020000U) |
| <> | 130:d75b3fe1f5cb | 409 | #define DMA_FLAG_HT5 ((uint32_t)0x00040000U) |
| <> | 130:d75b3fe1f5cb | 410 | #define DMA_FLAG_TE5 ((uint32_t)0x00080000U) |
| <> | 130:d75b3fe1f5cb | 411 | #define DMA_FLAG_GL6 ((uint32_t)0x00100000U) |
| <> | 130:d75b3fe1f5cb | 412 | #define DMA_FLAG_TC6 ((uint32_t)0x00200000U) |
| <> | 130:d75b3fe1f5cb | 413 | #define DMA_FLAG_HT6 ((uint32_t)0x00400000U) |
| <> | 130:d75b3fe1f5cb | 414 | #define DMA_FLAG_TE6 ((uint32_t)0x00800000U) |
| <> | 130:d75b3fe1f5cb | 415 | #define DMA_FLAG_GL7 ((uint32_t)0x01000000U) |
| <> | 130:d75b3fe1f5cb | 416 | #define DMA_FLAG_TC7 ((uint32_t)0x02000000U) |
| <> | 130:d75b3fe1f5cb | 417 | #define DMA_FLAG_HT7 ((uint32_t)0x04000000U) |
| <> | 130:d75b3fe1f5cb | 418 | #define DMA_FLAG_TE7 ((uint32_t)0x08000000U) |
| bogdanm | 84:0b3ab51c8877 | 419 | |
| bogdanm | 84:0b3ab51c8877 | 420 | |
| bogdanm | 84:0b3ab51c8877 | 421 | /** |
| bogdanm | 84:0b3ab51c8877 | 422 | * @} |
| bogdanm | 84:0b3ab51c8877 | 423 | */ |
| Kojto | 96:487b796308b0 | 424 | |
| Kojto | 96:487b796308b0 | 425 | /** |
| Kojto | 96:487b796308b0 | 426 | * @} |
| Kojto | 96:487b796308b0 | 427 | */ |
| Kojto | 96:487b796308b0 | 428 | |
| bogdanm | 84:0b3ab51c8877 | 429 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 84:0b3ab51c8877 | 430 | |
| Kojto | 96:487b796308b0 | 431 | /** @defgroup DMA_Exported_Macros DMA Exported Macros |
| Kojto | 96:487b796308b0 | 432 | * @{ |
| Kojto | 96:487b796308b0 | 433 | */ |
| Kojto | 96:487b796308b0 | 434 | |
| bogdanm | 84:0b3ab51c8877 | 435 | /** @brief Reset DMA handle state |
| bogdanm | 84:0b3ab51c8877 | 436 | * @param __HANDLE__: DMA handle |
| bogdanm | 84:0b3ab51c8877 | 437 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 438 | */ |
| bogdanm | 84:0b3ab51c8877 | 439 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| bogdanm | 84:0b3ab51c8877 | 440 | |
| bogdanm | 84:0b3ab51c8877 | 441 | /** |
| bogdanm | 84:0b3ab51c8877 | 442 | * @brief Enable the specified DMA Channel. |
| bogdanm | 84:0b3ab51c8877 | 443 | * @param __HANDLE__: DMA handle |
| bogdanm | 84:0b3ab51c8877 | 444 | * @retval None. |
| bogdanm | 84:0b3ab51c8877 | 445 | */ |
| bogdanm | 84:0b3ab51c8877 | 446 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) |
| bogdanm | 84:0b3ab51c8877 | 447 | |
| bogdanm | 84:0b3ab51c8877 | 448 | /** |
| bogdanm | 84:0b3ab51c8877 | 449 | * @brief Disable the specified DMA Channel. |
| bogdanm | 84:0b3ab51c8877 | 450 | * @param __HANDLE__: DMA handle |
| bogdanm | 84:0b3ab51c8877 | 451 | * @retval None. |
| bogdanm | 84:0b3ab51c8877 | 452 | */ |
| bogdanm | 84:0b3ab51c8877 | 453 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) |
| bogdanm | 84:0b3ab51c8877 | 454 | |
| bogdanm | 84:0b3ab51c8877 | 455 | |
| bogdanm | 84:0b3ab51c8877 | 456 | /* Interrupt & Flag management */ |
| bogdanm | 84:0b3ab51c8877 | 457 | |
| bogdanm | 84:0b3ab51c8877 | 458 | /** |
| bogdanm | 84:0b3ab51c8877 | 459 | * @brief Returns the current DMA Channel transfer complete flag. |
| bogdanm | 84:0b3ab51c8877 | 460 | * @param __HANDLE__: DMA handle |
| bogdanm | 84:0b3ab51c8877 | 461 | * @retval The specified transfer complete flag index. |
| bogdanm | 84:0b3ab51c8877 | 462 | */ |
| bogdanm | 84:0b3ab51c8877 | 463 | |
| Kojto | 119:aae6fcc7d9bb | 464 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| Kojto | 119:aae6fcc7d9bb | 465 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| Kojto | 119:aae6fcc7d9bb | 466 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| Kojto | 119:aae6fcc7d9bb | 467 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| Kojto | 119:aae6fcc7d9bb | 468 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| Kojto | 119:aae6fcc7d9bb | 469 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| Kojto | 119:aae6fcc7d9bb | 470 | DMA_FLAG_TC5) |
| Kojto | 119:aae6fcc7d9bb | 471 | #else |
| bogdanm | 84:0b3ab51c8877 | 472 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| bogdanm | 84:0b3ab51c8877 | 473 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| bogdanm | 84:0b3ab51c8877 | 474 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| bogdanm | 84:0b3ab51c8877 | 475 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| bogdanm | 84:0b3ab51c8877 | 476 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| bogdanm | 84:0b3ab51c8877 | 477 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
| bogdanm | 84:0b3ab51c8877 | 478 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
| Kojto | 119:aae6fcc7d9bb | 479 | DMA_FLAG_TC7) |
| Kojto | 119:aae6fcc7d9bb | 480 | #endif |
| bogdanm | 84:0b3ab51c8877 | 481 | /** |
| bogdanm | 84:0b3ab51c8877 | 482 | * @brief Returns the current DMA Channel half transfer complete flag. |
| bogdanm | 84:0b3ab51c8877 | 483 | * @param __HANDLE__: DMA handle |
| bogdanm | 84:0b3ab51c8877 | 484 | * @retval The specified half transfer complete flag index. |
| Kojto | 119:aae6fcc7d9bb | 485 | */ |
| Kojto | 119:aae6fcc7d9bb | 486 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| Kojto | 119:aae6fcc7d9bb | 487 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| Kojto | 119:aae6fcc7d9bb | 488 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| Kojto | 119:aae6fcc7d9bb | 489 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| Kojto | 119:aae6fcc7d9bb | 490 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| Kojto | 119:aae6fcc7d9bb | 491 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| Kojto | 119:aae6fcc7d9bb | 492 | DMA_FLAG_HT5) |
| Kojto | 119:aae6fcc7d9bb | 493 | #else |
| bogdanm | 84:0b3ab51c8877 | 494 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 84:0b3ab51c8877 | 495 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| bogdanm | 84:0b3ab51c8877 | 496 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| bogdanm | 84:0b3ab51c8877 | 497 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| bogdanm | 84:0b3ab51c8877 | 498 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| bogdanm | 84:0b3ab51c8877 | 499 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
| bogdanm | 84:0b3ab51c8877 | 500 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
| bogdanm | 84:0b3ab51c8877 | 501 | DMA_FLAG_HT7) |
| Kojto | 119:aae6fcc7d9bb | 502 | #endif |
| bogdanm | 84:0b3ab51c8877 | 503 | /** |
| bogdanm | 84:0b3ab51c8877 | 504 | * @brief Returns the current DMA Channel transfer error flag. |
| bogdanm | 84:0b3ab51c8877 | 505 | * @param __HANDLE__: DMA handle |
| bogdanm | 84:0b3ab51c8877 | 506 | * @retval The specified transfer error flag index. |
| bogdanm | 84:0b3ab51c8877 | 507 | */ |
| Kojto | 119:aae6fcc7d9bb | 508 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| Kojto | 119:aae6fcc7d9bb | 509 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| Kojto | 119:aae6fcc7d9bb | 510 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| Kojto | 119:aae6fcc7d9bb | 511 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| Kojto | 119:aae6fcc7d9bb | 512 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| Kojto | 119:aae6fcc7d9bb | 513 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| Kojto | 119:aae6fcc7d9bb | 514 | DMA_FLAG_TE5) |
| Kojto | 119:aae6fcc7d9bb | 515 | #else |
| bogdanm | 84:0b3ab51c8877 | 516 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 84:0b3ab51c8877 | 517 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| bogdanm | 84:0b3ab51c8877 | 518 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| bogdanm | 84:0b3ab51c8877 | 519 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| bogdanm | 84:0b3ab51c8877 | 520 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| bogdanm | 84:0b3ab51c8877 | 521 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
| bogdanm | 84:0b3ab51c8877 | 522 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
| bogdanm | 84:0b3ab51c8877 | 523 | DMA_FLAG_TE7) |
| Kojto | 119:aae6fcc7d9bb | 524 | #endif |
| bogdanm | 84:0b3ab51c8877 | 525 | /** |
| bogdanm | 84:0b3ab51c8877 | 526 | * @brief Returns the current DMA Channel Global interrupt flag. |
| bogdanm | 84:0b3ab51c8877 | 527 | * @param __HANDLE__: DMA handle |
| bogdanm | 84:0b3ab51c8877 | 528 | * @retval The specified transfer error flag index. |
| bogdanm | 84:0b3ab51c8877 | 529 | */ |
| Kojto | 119:aae6fcc7d9bb | 530 | #if defined (STM32L011xx) || defined (STM32L021xx) |
| Kojto | 119:aae6fcc7d9bb | 531 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
| Kojto | 119:aae6fcc7d9bb | 532 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ |
| Kojto | 119:aae6fcc7d9bb | 533 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ |
| Kojto | 119:aae6fcc7d9bb | 534 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ |
| Kojto | 119:aae6fcc7d9bb | 535 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ |
| Kojto | 119:aae6fcc7d9bb | 536 | DMA_ISR_GIF5) |
| Kojto | 119:aae6fcc7d9bb | 537 | #else |
| bogdanm | 84:0b3ab51c8877 | 538 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
| bogdanm | 84:0b3ab51c8877 | 539 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ |
| bogdanm | 84:0b3ab51c8877 | 540 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ |
| bogdanm | 84:0b3ab51c8877 | 541 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ |
| bogdanm | 84:0b3ab51c8877 | 542 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ |
| bogdanm | 84:0b3ab51c8877 | 543 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ |
| bogdanm | 84:0b3ab51c8877 | 544 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ |
| bogdanm | 84:0b3ab51c8877 | 545 | DMA_ISR_GIF7) |
| Kojto | 119:aae6fcc7d9bb | 546 | #endif |
| bogdanm | 84:0b3ab51c8877 | 547 | /** |
| bogdanm | 84:0b3ab51c8877 | 548 | * @brief Get the DMA Channel pending flags. |
| bogdanm | 84:0b3ab51c8877 | 549 | * @param __HANDLE__: DMA handle |
| bogdanm | 84:0b3ab51c8877 | 550 | * @param __FLAG__: Get the specified flag. |
| bogdanm | 84:0b3ab51c8877 | 551 | * This parameter can be any combination of the following values: |
| bogdanm | 84:0b3ab51c8877 | 552 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| bogdanm | 84:0b3ab51c8877 | 553 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| bogdanm | 84:0b3ab51c8877 | 554 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| bogdanm | 84:0b3ab51c8877 | 555 | * @arg DMA_ISR_GIFx: Global interrupt flag |
| bogdanm | 84:0b3ab51c8877 | 556 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
| bogdanm | 84:0b3ab51c8877 | 557 | * @retval The state of FLAG (SET or RESET). |
| bogdanm | 84:0b3ab51c8877 | 558 | */ |
| bogdanm | 84:0b3ab51c8877 | 559 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
| bogdanm | 84:0b3ab51c8877 | 560 | |
| bogdanm | 84:0b3ab51c8877 | 561 | /** |
| bogdanm | 84:0b3ab51c8877 | 562 | * @brief Clears the DMA Channel pending flags. |
| bogdanm | 84:0b3ab51c8877 | 563 | * @param __HANDLE__: DMA handle |
| bogdanm | 84:0b3ab51c8877 | 564 | * @param __FLAG__: specifies the flag to clear. |
| bogdanm | 84:0b3ab51c8877 | 565 | * This parameter can be any combination of the following values: |
| bogdanm | 84:0b3ab51c8877 | 566 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| bogdanm | 84:0b3ab51c8877 | 567 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| bogdanm | 84:0b3ab51c8877 | 568 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| bogdanm | 84:0b3ab51c8877 | 569 | * @arg DMA_ISR_GIFx: Global interrupt flag |
| bogdanm | 84:0b3ab51c8877 | 570 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
| bogdanm | 84:0b3ab51c8877 | 571 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 572 | */ |
| bogdanm | 92:4fc01daae5a5 | 573 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
| bogdanm | 84:0b3ab51c8877 | 574 | |
| bogdanm | 84:0b3ab51c8877 | 575 | /** |
| bogdanm | 84:0b3ab51c8877 | 576 | * @brief Enables the specified DMA Channel interrupts. |
| bogdanm | 84:0b3ab51c8877 | 577 | * @param __HANDLE__: DMA handle |
| bogdanm | 84:0b3ab51c8877 | 578 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| bogdanm | 84:0b3ab51c8877 | 579 | * This parameter can be any combination of the following values: |
| bogdanm | 84:0b3ab51c8877 | 580 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| bogdanm | 84:0b3ab51c8877 | 581 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| bogdanm | 84:0b3ab51c8877 | 582 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| bogdanm | 84:0b3ab51c8877 | 583 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 584 | */ |
| bogdanm | 84:0b3ab51c8877 | 585 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) |
| bogdanm | 84:0b3ab51c8877 | 586 | |
| bogdanm | 84:0b3ab51c8877 | 587 | /** |
| bogdanm | 84:0b3ab51c8877 | 588 | * @brief Disables the specified DMA Channel interrupts. |
| bogdanm | 84:0b3ab51c8877 | 589 | * @param __HANDLE__: DMA handle |
| bogdanm | 84:0b3ab51c8877 | 590 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| bogdanm | 84:0b3ab51c8877 | 591 | * This parameter can be any combination of the following values: |
| bogdanm | 84:0b3ab51c8877 | 592 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| bogdanm | 84:0b3ab51c8877 | 593 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| bogdanm | 84:0b3ab51c8877 | 594 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| bogdanm | 84:0b3ab51c8877 | 595 | * @retval None |
| bogdanm | 84:0b3ab51c8877 | 596 | */ |
| bogdanm | 84:0b3ab51c8877 | 597 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) |
| bogdanm | 84:0b3ab51c8877 | 598 | |
| bogdanm | 84:0b3ab51c8877 | 599 | /** |
| Kojto | 119:aae6fcc7d9bb | 600 | * @brief Checks whether the specified DMA Channel interrupt is enabled or not. |
| bogdanm | 84:0b3ab51c8877 | 601 | * @param __HANDLE__: DMA handle |
| bogdanm | 84:0b3ab51c8877 | 602 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| bogdanm | 84:0b3ab51c8877 | 603 | * This parameter can be one of the following values: |
| bogdanm | 84:0b3ab51c8877 | 604 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| bogdanm | 84:0b3ab51c8877 | 605 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| bogdanm | 84:0b3ab51c8877 | 606 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| bogdanm | 84:0b3ab51c8877 | 607 | * @retval The state of DMA_IT (SET or RESET). |
| bogdanm | 84:0b3ab51c8877 | 608 | */ |
| bogdanm | 84:0b3ab51c8877 | 609 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) |
| bogdanm | 84:0b3ab51c8877 | 610 | |
| Kojto | 96:487b796308b0 | 611 | /** |
| <> | 130:d75b3fe1f5cb | 612 | * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. |
| <> | 130:d75b3fe1f5cb | 613 | * @param __HANDLE__: DMA handle |
| <> | 130:d75b3fe1f5cb | 614 | * |
| <> | 130:d75b3fe1f5cb | 615 | * @retval The number of remaining data units in the current DMA Channel transfer. |
| <> | 130:d75b3fe1f5cb | 616 | */ |
| <> | 130:d75b3fe1f5cb | 617 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) |
| <> | 130:d75b3fe1f5cb | 618 | |
| <> | 130:d75b3fe1f5cb | 619 | /** |
| Kojto | 96:487b796308b0 | 620 | * @} |
| Kojto | 96:487b796308b0 | 621 | */ |
| bogdanm | 84:0b3ab51c8877 | 622 | |
| bogdanm | 84:0b3ab51c8877 | 623 | /* Exported functions --------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 624 | |
| Kojto | 96:487b796308b0 | 625 | /** @defgroup DMA_Exported_Functions DMA Exported Functions |
| Kojto | 96:487b796308b0 | 626 | * @{ |
| Kojto | 96:487b796308b0 | 627 | */ |
| Kojto | 96:487b796308b0 | 628 | |
| Kojto | 96:487b796308b0 | 629 | /** @defgroup DMA_Exported_Functions_Group1 Initialization/de-initialization functions |
| Kojto | 96:487b796308b0 | 630 | * @{ |
| Kojto | 96:487b796308b0 | 631 | */ |
| Kojto | 96:487b796308b0 | 632 | |
| bogdanm | 84:0b3ab51c8877 | 633 | /* Initialization and de-initialization functions *****************************/ |
| bogdanm | 84:0b3ab51c8877 | 634 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| bogdanm | 84:0b3ab51c8877 | 635 | HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
| bogdanm | 84:0b3ab51c8877 | 636 | |
| Kojto | 96:487b796308b0 | 637 | /** |
| Kojto | 96:487b796308b0 | 638 | * @} |
| Kojto | 96:487b796308b0 | 639 | */ |
| Kojto | 96:487b796308b0 | 640 | |
| Kojto | 96:487b796308b0 | 641 | /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions |
| Kojto | 96:487b796308b0 | 642 | * @{ |
| Kojto | 96:487b796308b0 | 643 | */ |
| Kojto | 96:487b796308b0 | 644 | |
| bogdanm | 84:0b3ab51c8877 | 645 | /* IO operation functions *****************************************************/ |
| bogdanm | 84:0b3ab51c8877 | 646 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| bogdanm | 84:0b3ab51c8877 | 647 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| bogdanm | 84:0b3ab51c8877 | 648 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| <> | 132:9baf128c2fab | 649 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); |
| bogdanm | 84:0b3ab51c8877 | 650 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
| bogdanm | 84:0b3ab51c8877 | 651 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| Kojto | 96:487b796308b0 | 652 | /** |
| Kojto | 96:487b796308b0 | 653 | * @} |
| Kojto | 96:487b796308b0 | 654 | */ |
| Kojto | 96:487b796308b0 | 655 | |
| Kojto | 96:487b796308b0 | 656 | /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions |
| Kojto | 96:487b796308b0 | 657 | * @{ |
| Kojto | 96:487b796308b0 | 658 | */ |
| bogdanm | 84:0b3ab51c8877 | 659 | |
| bogdanm | 84:0b3ab51c8877 | 660 | /* Peripheral State and Error functions ***************************************/ |
| bogdanm | 84:0b3ab51c8877 | 661 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| bogdanm | 84:0b3ab51c8877 | 662 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| bogdanm | 84:0b3ab51c8877 | 663 | |
| bogdanm | 84:0b3ab51c8877 | 664 | /** |
| bogdanm | 84:0b3ab51c8877 | 665 | * @} |
| bogdanm | 84:0b3ab51c8877 | 666 | */ |
| bogdanm | 84:0b3ab51c8877 | 667 | |
| bogdanm | 84:0b3ab51c8877 | 668 | /** |
| bogdanm | 84:0b3ab51c8877 | 669 | * @} |
| bogdanm | 84:0b3ab51c8877 | 670 | */ |
| Kojto | 119:aae6fcc7d9bb | 671 | /* Define the private group ***********************************/ |
| Kojto | 119:aae6fcc7d9bb | 672 | /**************************************************************/ |
| Kojto | 119:aae6fcc7d9bb | 673 | /** @defgroup DMA_Private DMA Private |
| Kojto | 119:aae6fcc7d9bb | 674 | * @{ |
| Kojto | 119:aae6fcc7d9bb | 675 | */ |
| Kojto | 119:aae6fcc7d9bb | 676 | /** |
| Kojto | 119:aae6fcc7d9bb | 677 | * @} |
| Kojto | 119:aae6fcc7d9bb | 678 | */ |
| Kojto | 119:aae6fcc7d9bb | 679 | /**************************************************************/ |
| Kojto | 96:487b796308b0 | 680 | |
| Kojto | 96:487b796308b0 | 681 | /** |
| Kojto | 96:487b796308b0 | 682 | * @} |
| Kojto | 96:487b796308b0 | 683 | */ |
| Kojto | 96:487b796308b0 | 684 | |
| Kojto | 96:487b796308b0 | 685 | /** |
| Kojto | 96:487b796308b0 | 686 | * @} |
| Kojto | 96:487b796308b0 | 687 | */ |
| bogdanm | 84:0b3ab51c8877 | 688 | |
| bogdanm | 84:0b3ab51c8877 | 689 | #ifdef __cplusplus |
| bogdanm | 84:0b3ab51c8877 | 690 | } |
| bogdanm | 84:0b3ab51c8877 | 691 | #endif |
| bogdanm | 84:0b3ab51c8877 | 692 | |
| bogdanm | 84:0b3ab51c8877 | 693 | #endif /* __STM32L0xx_HAL_DMA_H */ |
| bogdanm | 84:0b3ab51c8877 | 694 | |
| bogdanm | 84:0b3ab51c8877 | 695 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| Kojto | 96:487b796308b0 | 696 |
