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This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L053R8/stm32l0xx_hal_dma.h@119:aae6fcc7d9bb, 2016-04-27 (annotated)

Committer:
Kojto
Date:
Wed Apr 27 12:10:56 2016 -0500
Revision:
119:aae6fcc7d9bb
Parent:
96:487b796308b0 
Release 119 of the mbed library



Changes:

- new targets - EFM32PG_STK3401, NUCLEO_L031K6

- ST - hwflwctl support for NUCLEO_L476RG

     - Update STM32CUBE_L0 from v1.2 to v1.5

     - STM32F7 - bugfix - The weak function HAL_Delay is overwritten to use us ticker API.

- Maxim - Fixing the send break for the MAXWSNENV and MAX32600MBED

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l0xx_hal_dma.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
Kojto 119:aae6fcc7d9bb 5 * @version V1.5.0
Kojto 119:aae6fcc7d9bb 6 * @date 8-January-2016
bogdanm 84:0b3ab51c8877 7 * @brief Header file of DMA HAL module.
bogdanm 84:0b3ab51c8877 8 ******************************************************************************
bogdanm 84:0b3ab51c8877 9 * @attention
bogdanm 84:0b3ab51c8877 10 *
Kojto 119:aae6fcc7d9bb 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 12 *
bogdanm 84:0b3ab51c8877 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 14 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 16 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 19 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 21 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 22 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 34 *
bogdanm 84:0b3ab51c8877 35 ******************************************************************************
bogdanm 84:0b3ab51c8877 36 */
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 84:0b3ab51c8877 39 #ifndef __STM32L0xx_HAL_DMA_H
bogdanm 84:0b3ab51c8877 40 #define __STM32L0xx_HAL_DMA_H
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 43 extern "C" {
bogdanm 84:0b3ab51c8877 44 #endif
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /* Includes ------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 47 #include "stm32l0xx_hal_def.h"
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 84:0b3ab51c8877 50 * @{
bogdanm 84:0b3ab51c8877 51 */
bogdanm 84:0b3ab51c8877 52
Kojto 96:487b796308b0 53 /** @defgroup DMA DMA
bogdanm 84:0b3ab51c8877 54 * @{
bogdanm 84:0b3ab51c8877 55 */
bogdanm 84:0b3ab51c8877 56
Kojto 119:aae6fcc7d9bb 57 /** @defgroup DMA_Exported_Types DMA Exported Types
Kojto 119:aae6fcc7d9bb 58 * @{
Kojto 119:aae6fcc7d9bb 59 */
bogdanm 84:0b3ab51c8877 60 /* Exported types ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 61
bogdanm 84:0b3ab51c8877 62 /**
bogdanm 84:0b3ab51c8877 63 * @brief DMA Configuration Structure definition
bogdanm 84:0b3ab51c8877 64 */
bogdanm 84:0b3ab51c8877 65 typedef struct
bogdanm 84:0b3ab51c8877 66 {
bogdanm 84:0b3ab51c8877 67 uint32_t Request; /*!< Specifies the request selected for the specified channel.
bogdanm 84:0b3ab51c8877 68 This parameter can be a value of @ref DMA_request */
bogdanm 84:0b3ab51c8877 69
bogdanm 84:0b3ab51c8877 70 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 84:0b3ab51c8877 71 from memory to memory or from peripheral to memory.
bogdanm 92:4fc01daae5a5 72 This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm 84:0b3ab51c8877 73
bogdanm 84:0b3ab51c8877 74 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
Kojto 96:487b796308b0 75 When Memory to Memory transfer is used, this is the Source Increment mode
bogdanm 92:4fc01daae5a5 76 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 84:0b3ab51c8877 77
bogdanm 84:0b3ab51c8877 78 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
Kojto 96:487b796308b0 79 When Memory to Memory transfer is used, this is the Destination Increment mode
bogdanm 92:4fc01daae5a5 80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 84:0b3ab51c8877 81
bogdanm 84:0b3ab51c8877 82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
Kojto 96:487b796308b0 83 When Memory to Memory transfer is used, this is the Source Alignment format
bogdanm 92:4fc01daae5a5 84 This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm 84:0b3ab51c8877 85
bogdanm 84:0b3ab51c8877 86 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
Kojto 96:487b796308b0 87 When Memory to Memory transfer is used, this is the Destination Alignment format
bogdanm 92:4fc01daae5a5 88 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 84:0b3ab51c8877 89
Kojto 96:487b796308b0 90 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx (Normal or Circular).
bogdanm 84:0b3ab51c8877 91 This parameter can be a value of @ref DMA_mode
bogdanm 84:0b3ab51c8877 92 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 84:0b3ab51c8877 93 data transfer is configured on the selected Channel */
bogdanm 84:0b3ab51c8877 94
bogdanm 84:0b3ab51c8877 95 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
bogdanm 92:4fc01daae5a5 96 This parameter can be a value of @ref DMA_Priority_level */
bogdanm 84:0b3ab51c8877 97 } DMA_InitTypeDef;
bogdanm 84:0b3ab51c8877 98
bogdanm 84:0b3ab51c8877 99 /**
bogdanm 84:0b3ab51c8877 100 * @brief DMA Configuration enumeration values definition
bogdanm 84:0b3ab51c8877 101 */
bogdanm 84:0b3ab51c8877 102 typedef enum
bogdanm 84:0b3ab51c8877 103 {
bogdanm 84:0b3ab51c8877 104 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
bogdanm 84:0b3ab51c8877 105 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
bogdanm 84:0b3ab51c8877 106
bogdanm 84:0b3ab51c8877 107 } DMA_ControlTypeDef;
bogdanm 84:0b3ab51c8877 108
bogdanm 84:0b3ab51c8877 109 /**
bogdanm 84:0b3ab51c8877 110 * @brief HAL DMA State structures definition
bogdanm 84:0b3ab51c8877 111 */
bogdanm 84:0b3ab51c8877 112 typedef enum
bogdanm 84:0b3ab51c8877 113 {
bogdanm 84:0b3ab51c8877 114 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
bogdanm 84:0b3ab51c8877 115 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
bogdanm 84:0b3ab51c8877 116 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
bogdanm 84:0b3ab51c8877 117 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
bogdanm 84:0b3ab51c8877 118 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
bogdanm 84:0b3ab51c8877 119 HAL_DMA_STATE_READY_HALF = 0x05, /*!< DMA Half process success */
bogdanm 84:0b3ab51c8877 120 }HAL_DMA_StateTypeDef;
bogdanm 84:0b3ab51c8877 121
bogdanm 84:0b3ab51c8877 122 /**
bogdanm 84:0b3ab51c8877 123 * @brief HAL DMA Error Code structure definition
bogdanm 84:0b3ab51c8877 124 */
bogdanm 84:0b3ab51c8877 125 typedef enum
bogdanm 84:0b3ab51c8877 126 {
bogdanm 84:0b3ab51c8877 127 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
bogdanm 84:0b3ab51c8877 128 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
bogdanm 84:0b3ab51c8877 129
bogdanm 84:0b3ab51c8877 130 }HAL_DMA_LevelCompleteTypeDef;
bogdanm 84:0b3ab51c8877 131
bogdanm 84:0b3ab51c8877 132
bogdanm 84:0b3ab51c8877 133 /**
bogdanm 84:0b3ab51c8877 134 * @brief DMA handle Structure definition
bogdanm 84:0b3ab51c8877 135 */
bogdanm 84:0b3ab51c8877 136 typedef struct __DMA_HandleTypeDef
bogdanm 84:0b3ab51c8877 137 {
bogdanm 84:0b3ab51c8877 138 DMA_Channel_TypeDef *Instance; /*!< Register base address */
bogdanm 84:0b3ab51c8877 139
bogdanm 84:0b3ab51c8877 140 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 84:0b3ab51c8877 141
bogdanm 84:0b3ab51c8877 142 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 84:0b3ab51c8877 143
bogdanm 84:0b3ab51c8877 144 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 84:0b3ab51c8877 145
bogdanm 84:0b3ab51c8877 146 void *Parent; /*!< Parent object state */
bogdanm 84:0b3ab51c8877 147
bogdanm 84:0b3ab51c8877 148 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 84:0b3ab51c8877 149
bogdanm 84:0b3ab51c8877 150 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 84:0b3ab51c8877 151
bogdanm 84:0b3ab51c8877 152 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
bogdanm 84:0b3ab51c8877 153
bogdanm 84:0b3ab51c8877 154 __IO uint32_t ErrorCode; /*!< DMA Error code */
bogdanm 84:0b3ab51c8877 155
bogdanm 84:0b3ab51c8877 156 } DMA_HandleTypeDef;
bogdanm 84:0b3ab51c8877 157
Kojto 119:aae6fcc7d9bb 158 /**
Kojto 119:aae6fcc7d9bb 159 * @}
Kojto 119:aae6fcc7d9bb 160 */
Kojto 119:aae6fcc7d9bb 161
bogdanm 84:0b3ab51c8877 162 /* Exported constants --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 163
Kojto 96:487b796308b0 164 /** @defgroup DMA_Exported_Constants DMA Exported Constants
bogdanm 84:0b3ab51c8877 165 * @{
bogdanm 84:0b3ab51c8877 166 */
bogdanm 84:0b3ab51c8877 167
Kojto 96:487b796308b0 168 /** @defgroup DMA_Error_Code DMA Error Codes
bogdanm 84:0b3ab51c8877 169 * @{
bogdanm 84:0b3ab51c8877 170 */
bogdanm 84:0b3ab51c8877 171 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 84:0b3ab51c8877 172 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 84:0b3ab51c8877 173 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 84:0b3ab51c8877 174
Kojto 119:aae6fcc7d9bb 175 #if defined (STM32L011xx) || defined (STM32L021xx)
Kojto 119:aae6fcc7d9bb 176 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 119:aae6fcc7d9bb 177 ((INSTANCE) == DMA1_Channel2) || \
Kojto 119:aae6fcc7d9bb 178 ((INSTANCE) == DMA1_Channel3) || \
Kojto 119:aae6fcc7d9bb 179 ((INSTANCE) == DMA1_Channel4) || \
Kojto 119:aae6fcc7d9bb 180 ((INSTANCE) == DMA1_Channel5))
Kojto 119:aae6fcc7d9bb 181 #else
Kojto 119:aae6fcc7d9bb 182 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 119:aae6fcc7d9bb 183 ((INSTANCE) == DMA1_Channel2) || \
Kojto 119:aae6fcc7d9bb 184 ((INSTANCE) == DMA1_Channel3) || \
Kojto 119:aae6fcc7d9bb 185 ((INSTANCE) == DMA1_Channel4) || \
Kojto 119:aae6fcc7d9bb 186 ((INSTANCE) == DMA1_Channel5) || \
Kojto 119:aae6fcc7d9bb 187 ((INSTANCE) == DMA1_Channel6) || \
Kojto 119:aae6fcc7d9bb 188 ((INSTANCE) == DMA1_Channel7))
bogdanm 84:0b3ab51c8877 189
Kojto 119:aae6fcc7d9bb 190 #endif
bogdanm 84:0b3ab51c8877 191 #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1))
bogdanm 84:0b3ab51c8877 192
bogdanm 84:0b3ab51c8877 193 /**
bogdanm 84:0b3ab51c8877 194 * @}
bogdanm 84:0b3ab51c8877 195 */
bogdanm 84:0b3ab51c8877 196
Kojto 96:487b796308b0 197 /** @defgroup DMA_request DMA request defintiions
bogdanm 84:0b3ab51c8877 198 * @{
bogdanm 84:0b3ab51c8877 199 */
Kojto 96:487b796308b0 200
Kojto 96:487b796308b0 201 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
Kojto 96:487b796308b0 202
Kojto 96:487b796308b0 203 #define DMA_REQUEST_0 ((uint32_t)0x00000000)
Kojto 96:487b796308b0 204 #define DMA_REQUEST_1 ((uint32_t)0x00000001)
Kojto 96:487b796308b0 205 #define DMA_REQUEST_2 ((uint32_t)0x00000002)
Kojto 96:487b796308b0 206 #define DMA_REQUEST_3 ((uint32_t)0x00000003)
Kojto 96:487b796308b0 207 #define DMA_REQUEST_4 ((uint32_t)0x00000004)
Kojto 96:487b796308b0 208 #define DMA_REQUEST_5 ((uint32_t)0x00000005)
Kojto 96:487b796308b0 209 #define DMA_REQUEST_6 ((uint32_t)0x00000006)
Kojto 96:487b796308b0 210 #define DMA_REQUEST_7 ((uint32_t)0x00000007)
Kojto 96:487b796308b0 211 #define DMA_REQUEST_8 ((uint32_t)0x00000008)
Kojto 96:487b796308b0 212 #define DMA_REQUEST_9 ((uint32_t)0x00000009)
Kojto 96:487b796308b0 213 #define DMA_REQUEST_10 ((uint32_t)0x0000000A)
Kojto 96:487b796308b0 214 #define DMA_REQUEST_11 ((uint32_t)0x0000000B)
Kojto 96:487b796308b0 215 #define DMA_REQUEST_12 ((uint32_t)0x0000000C)
Kojto 96:487b796308b0 216 #define DMA_REQUEST_13 ((uint32_t)0x0000000D)
Kojto 96:487b796308b0 217 #define DMA_REQUEST_14 ((uint32_t)0x0000000E)
Kojto 96:487b796308b0 218 #define DMA_REQUEST_15 ((uint32_t)0x0000000F)
Kojto 96:487b796308b0 219
Kojto 96:487b796308b0 220 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
Kojto 96:487b796308b0 221 ((REQUEST) == DMA_REQUEST_1) || \
Kojto 96:487b796308b0 222 ((REQUEST) == DMA_REQUEST_2) || \
Kojto 96:487b796308b0 223 ((REQUEST) == DMA_REQUEST_3) || \
Kojto 96:487b796308b0 224 ((REQUEST) == DMA_REQUEST_4) || \
Kojto 96:487b796308b0 225 ((REQUEST) == DMA_REQUEST_5) || \
Kojto 96:487b796308b0 226 ((REQUEST) == DMA_REQUEST_6) || \
Kojto 96:487b796308b0 227 ((REQUEST) == DMA_REQUEST_7) || \
Kojto 96:487b796308b0 228 ((REQUEST) == DMA_REQUEST_8) || \
Kojto 96:487b796308b0 229 ((REQUEST) == DMA_REQUEST_9) || \
Kojto 96:487b796308b0 230 ((REQUEST) == DMA_REQUEST_10) || \
Kojto 96:487b796308b0 231 ((REQUEST) == DMA_REQUEST_11) || \
Kojto 96:487b796308b0 232 ((REQUEST) == DMA_REQUEST_12) || \
Kojto 96:487b796308b0 233 ((REQUEST) == DMA_REQUEST_13) || \
Kojto 96:487b796308b0 234 ((REQUEST) == DMA_REQUEST_14) || \
Kojto 96:487b796308b0 235 ((REQUEST) == DMA_REQUEST_15))
Kojto 96:487b796308b0 236
Kojto 96:487b796308b0 237 #else /* #if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
Kojto 96:487b796308b0 238
bogdanm 84:0b3ab51c8877 239 #define DMA_REQUEST_0 ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 240 #define DMA_REQUEST_1 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 241 #define DMA_REQUEST_2 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 242 #define DMA_REQUEST_3 ((uint32_t)0x00000003)
bogdanm 84:0b3ab51c8877 243 #define DMA_REQUEST_4 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 244 #define DMA_REQUEST_5 ((uint32_t)0x00000005)
bogdanm 84:0b3ab51c8877 245 #define DMA_REQUEST_6 ((uint32_t)0x00000006)
bogdanm 84:0b3ab51c8877 246 #define DMA_REQUEST_7 ((uint32_t)0x00000007)
bogdanm 84:0b3ab51c8877 247 #define DMA_REQUEST_8 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 248 #define DMA_REQUEST_9 ((uint32_t)0x00000009)
bogdanm 84:0b3ab51c8877 249 #define DMA_REQUEST_11 ((uint32_t)0x0000000B)
bogdanm 84:0b3ab51c8877 250
bogdanm 84:0b3ab51c8877 251 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
bogdanm 84:0b3ab51c8877 252 ((REQUEST) == DMA_REQUEST_1) || \
bogdanm 84:0b3ab51c8877 253 ((REQUEST) == DMA_REQUEST_2) || \
bogdanm 84:0b3ab51c8877 254 ((REQUEST) == DMA_REQUEST_3) || \
bogdanm 84:0b3ab51c8877 255 ((REQUEST) == DMA_REQUEST_4) || \
bogdanm 84:0b3ab51c8877 256 ((REQUEST) == DMA_REQUEST_5) || \
bogdanm 84:0b3ab51c8877 257 ((REQUEST) == DMA_REQUEST_6) || \
bogdanm 84:0b3ab51c8877 258 ((REQUEST) == DMA_REQUEST_7) || \
bogdanm 84:0b3ab51c8877 259 ((REQUEST) == DMA_REQUEST_8) || \
bogdanm 84:0b3ab51c8877 260 ((REQUEST) == DMA_REQUEST_9) || \
bogdanm 84:0b3ab51c8877 261 ((REQUEST) == DMA_REQUEST_11))
Kojto 96:487b796308b0 262 #endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */
Kojto 96:487b796308b0 263
bogdanm 84:0b3ab51c8877 264 /**
bogdanm 84:0b3ab51c8877 265 * @}
bogdanm 84:0b3ab51c8877 266 */
bogdanm 84:0b3ab51c8877 267
Kojto 96:487b796308b0 268 /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions
bogdanm 84:0b3ab51c8877 269 * @{
bogdanm 84:0b3ab51c8877 270 */
bogdanm 84:0b3ab51c8877 271 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
bogdanm 84:0b3ab51c8877 272 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
bogdanm 84:0b3ab51c8877 273 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
bogdanm 84:0b3ab51c8877 274
bogdanm 84:0b3ab51c8877 275 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
bogdanm 84:0b3ab51c8877 276 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
bogdanm 84:0b3ab51c8877 277 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
bogdanm 84:0b3ab51c8877 278 /**
bogdanm 84:0b3ab51c8877 279 * @}
bogdanm 84:0b3ab51c8877 280 */
bogdanm 84:0b3ab51c8877 281
Kojto 119:aae6fcc7d9bb 282 /** @defgroup DMA_Data_buffer_size DMA Data Buffer Size Check
bogdanm 84:0b3ab51c8877 283 * @{
bogdanm 84:0b3ab51c8877 284 */
bogdanm 84:0b3ab51c8877 285 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
bogdanm 84:0b3ab51c8877 286 /**
bogdanm 84:0b3ab51c8877 287 * @}
bogdanm 84:0b3ab51c8877 288 */
bogdanm 84:0b3ab51c8877 289
Kojto 119:aae6fcc7d9bb 290 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral Incremented Mode
bogdanm 84:0b3ab51c8877 291 * @{
bogdanm 84:0b3ab51c8877 292 */
bogdanm 84:0b3ab51c8877 293 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
bogdanm 84:0b3ab51c8877 294 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
bogdanm 84:0b3ab51c8877 295
bogdanm 84:0b3ab51c8877 296 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
bogdanm 84:0b3ab51c8877 297 ((STATE) == DMA_PINC_DISABLE))
bogdanm 84:0b3ab51c8877 298 /**
bogdanm 84:0b3ab51c8877 299 * @}
bogdanm 84:0b3ab51c8877 300 */
bogdanm 84:0b3ab51c8877 301
Kojto 119:aae6fcc7d9bb 302 /** @defgroup DMA_Memory_incremented_mode DMA Memory Incremented Mode
bogdanm 84:0b3ab51c8877 303 * @{
bogdanm 84:0b3ab51c8877 304 */
bogdanm 84:0b3ab51c8877 305 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
bogdanm 84:0b3ab51c8877 306 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
bogdanm 84:0b3ab51c8877 307
bogdanm 84:0b3ab51c8877 308 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
bogdanm 84:0b3ab51c8877 309 ((STATE) == DMA_MINC_DISABLE))
bogdanm 84:0b3ab51c8877 310 /**
bogdanm 84:0b3ab51c8877 311 * @}
bogdanm 84:0b3ab51c8877 312 */
bogdanm 84:0b3ab51c8877 313
Kojto 119:aae6fcc7d9bb 314 /** @defgroup DMA_Peripheral_data_size DMA Peripheral Data Size Alignment
bogdanm 84:0b3ab51c8877 315 * @{
bogdanm 84:0b3ab51c8877 316 */
bogdanm 84:0b3ab51c8877 317 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
bogdanm 84:0b3ab51c8877 318 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
bogdanm 84:0b3ab51c8877 319 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
bogdanm 84:0b3ab51c8877 320
bogdanm 84:0b3ab51c8877 321 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
bogdanm 84:0b3ab51c8877 322 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
bogdanm 84:0b3ab51c8877 323 ((SIZE) == DMA_PDATAALIGN_WORD))
bogdanm 84:0b3ab51c8877 324 /**
bogdanm 84:0b3ab51c8877 325 * @}
bogdanm 84:0b3ab51c8877 326 */
bogdanm 84:0b3ab51c8877 327
bogdanm 84:0b3ab51c8877 328
Kojto 119:aae6fcc7d9bb 329 /** @defgroup DMA_Memory_data_size DMA Memory Data Size Alignment
bogdanm 84:0b3ab51c8877 330 * @{
bogdanm 84:0b3ab51c8877 331 */
bogdanm 84:0b3ab51c8877 332 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
bogdanm 84:0b3ab51c8877 333 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
bogdanm 84:0b3ab51c8877 334 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
bogdanm 84:0b3ab51c8877 335
bogdanm 84:0b3ab51c8877 336 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
bogdanm 84:0b3ab51c8877 337 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
bogdanm 84:0b3ab51c8877 338 ((SIZE) == DMA_MDATAALIGN_WORD ))
bogdanm 84:0b3ab51c8877 339 /**
bogdanm 84:0b3ab51c8877 340 * @}
bogdanm 84:0b3ab51c8877 341 */
bogdanm 84:0b3ab51c8877 342
Kojto 119:aae6fcc7d9bb 343 /** @defgroup DMA_mode DMA Mode
bogdanm 84:0b3ab51c8877 344 * @{
bogdanm 84:0b3ab51c8877 345 */
bogdanm 84:0b3ab51c8877 346 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
bogdanm 84:0b3ab51c8877 347 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
bogdanm 84:0b3ab51c8877 348
bogdanm 84:0b3ab51c8877 349 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
bogdanm 84:0b3ab51c8877 350 ((MODE) == DMA_CIRCULAR))
bogdanm 84:0b3ab51c8877 351 /**
bogdanm 84:0b3ab51c8877 352 * @}
bogdanm 84:0b3ab51c8877 353 */
bogdanm 84:0b3ab51c8877 354
Kojto 119:aae6fcc7d9bb 355 /** @defgroup DMA_Priority_level DMA Priority Level
bogdanm 84:0b3ab51c8877 356 * @{
bogdanm 84:0b3ab51c8877 357 */
bogdanm 84:0b3ab51c8877 358 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
bogdanm 84:0b3ab51c8877 359 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
bogdanm 84:0b3ab51c8877 360 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
bogdanm 84:0b3ab51c8877 361 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
bogdanm 84:0b3ab51c8877 362
bogdanm 84:0b3ab51c8877 363 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
bogdanm 84:0b3ab51c8877 364 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
bogdanm 84:0b3ab51c8877 365 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
bogdanm 84:0b3ab51c8877 366 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
bogdanm 84:0b3ab51c8877 367 /**
bogdanm 84:0b3ab51c8877 368 * @}
bogdanm 84:0b3ab51c8877 369 */
bogdanm 84:0b3ab51c8877 370
bogdanm 84:0b3ab51c8877 371
Kojto 119:aae6fcc7d9bb 372 /** @defgroup DMA_interrupt_enable_definitions DMA Interrupt Definitions
bogdanm 84:0b3ab51c8877 373 * @{
bogdanm 84:0b3ab51c8877 374 */
bogdanm 84:0b3ab51c8877 375
bogdanm 84:0b3ab51c8877 376 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
bogdanm 84:0b3ab51c8877 377 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
bogdanm 84:0b3ab51c8877 378 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
bogdanm 84:0b3ab51c8877 379
bogdanm 84:0b3ab51c8877 380 /**
bogdanm 84:0b3ab51c8877 381 * @}
bogdanm 84:0b3ab51c8877 382 */
bogdanm 84:0b3ab51c8877 383
Kojto 119:aae6fcc7d9bb 384 /** @defgroup DMA_flag_definitions DMA Flag Definitions
bogdanm 84:0b3ab51c8877 385 * @{
bogdanm 84:0b3ab51c8877 386 */
bogdanm 84:0b3ab51c8877 387
bogdanm 84:0b3ab51c8877 388 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 389 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 390 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 391 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 392 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 393 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 394 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
bogdanm 84:0b3ab51c8877 395 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
bogdanm 84:0b3ab51c8877 396 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
bogdanm 84:0b3ab51c8877 397 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
bogdanm 84:0b3ab51c8877 398 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
bogdanm 84:0b3ab51c8877 399 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
bogdanm 84:0b3ab51c8877 400 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
bogdanm 84:0b3ab51c8877 401 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
bogdanm 84:0b3ab51c8877 402 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
bogdanm 84:0b3ab51c8877 403 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
bogdanm 84:0b3ab51c8877 404 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
bogdanm 84:0b3ab51c8877 405 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
bogdanm 84:0b3ab51c8877 406 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
bogdanm 84:0b3ab51c8877 407 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
bogdanm 84:0b3ab51c8877 408 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
bogdanm 84:0b3ab51c8877 409 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
bogdanm 84:0b3ab51c8877 410 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
bogdanm 84:0b3ab51c8877 411 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
bogdanm 84:0b3ab51c8877 412 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
bogdanm 84:0b3ab51c8877 413 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
bogdanm 84:0b3ab51c8877 414 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
bogdanm 84:0b3ab51c8877 415 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
bogdanm 84:0b3ab51c8877 416
bogdanm 84:0b3ab51c8877 417
bogdanm 84:0b3ab51c8877 418 /**
bogdanm 84:0b3ab51c8877 419 * @}
bogdanm 84:0b3ab51c8877 420 */
Kojto 96:487b796308b0 421
Kojto 96:487b796308b0 422 /**
Kojto 96:487b796308b0 423 * @}
Kojto 96:487b796308b0 424 */
Kojto 96:487b796308b0 425
bogdanm 84:0b3ab51c8877 426 /* Exported macro ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 427
Kojto 96:487b796308b0 428 /** @defgroup DMA_Exported_Macros DMA Exported Macros
Kojto 96:487b796308b0 429 * @{
Kojto 96:487b796308b0 430 */
Kojto 96:487b796308b0 431
bogdanm 84:0b3ab51c8877 432 /** @brief Reset DMA handle state
bogdanm 84:0b3ab51c8877 433 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 434 * @retval None
bogdanm 84:0b3ab51c8877 435 */
bogdanm 84:0b3ab51c8877 436 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 84:0b3ab51c8877 437
bogdanm 84:0b3ab51c8877 438 /**
bogdanm 84:0b3ab51c8877 439 * @brief Enable the specified DMA Channel.
bogdanm 84:0b3ab51c8877 440 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 441 * @retval None.
bogdanm 84:0b3ab51c8877 442 */
bogdanm 84:0b3ab51c8877 443 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
bogdanm 84:0b3ab51c8877 444
bogdanm 84:0b3ab51c8877 445 /**
bogdanm 84:0b3ab51c8877 446 * @brief Disable the specified DMA Channel.
bogdanm 84:0b3ab51c8877 447 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 448 * @retval None.
bogdanm 84:0b3ab51c8877 449 */
bogdanm 84:0b3ab51c8877 450 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
bogdanm 84:0b3ab51c8877 451
bogdanm 84:0b3ab51c8877 452
bogdanm 84:0b3ab51c8877 453 /* Interrupt & Flag management */
bogdanm 84:0b3ab51c8877 454
bogdanm 84:0b3ab51c8877 455 /**
bogdanm 84:0b3ab51c8877 456 * @brief Returns the current DMA Channel transfer complete flag.
bogdanm 84:0b3ab51c8877 457 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 458 * @retval The specified transfer complete flag index.
bogdanm 84:0b3ab51c8877 459 */
bogdanm 84:0b3ab51c8877 460
Kojto 119:aae6fcc7d9bb 461 #if defined (STM32L011xx) || defined (STM32L021xx)
Kojto 119:aae6fcc7d9bb 462 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
Kojto 119:aae6fcc7d9bb 463 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
Kojto 119:aae6fcc7d9bb 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
Kojto 119:aae6fcc7d9bb 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
Kojto 119:aae6fcc7d9bb 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
Kojto 119:aae6fcc7d9bb 467 DMA_FLAG_TC5)
Kojto 119:aae6fcc7d9bb 468 #else
bogdanm 84:0b3ab51c8877 469 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
bogdanm 84:0b3ab51c8877 470 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
bogdanm 84:0b3ab51c8877 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
bogdanm 84:0b3ab51c8877 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
bogdanm 84:0b3ab51c8877 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
bogdanm 84:0b3ab51c8877 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
bogdanm 84:0b3ab51c8877 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
Kojto 119:aae6fcc7d9bb 476 DMA_FLAG_TC7)
Kojto 119:aae6fcc7d9bb 477 #endif
bogdanm 84:0b3ab51c8877 478 /**
bogdanm 84:0b3ab51c8877 479 * @brief Returns the current DMA Channel half transfer complete flag.
bogdanm 84:0b3ab51c8877 480 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 481 * @retval The specified half transfer complete flag index.
Kojto 119:aae6fcc7d9bb 482 */
Kojto 119:aae6fcc7d9bb 483 #if defined (STM32L011xx) || defined (STM32L021xx)
Kojto 119:aae6fcc7d9bb 484 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
Kojto 119:aae6fcc7d9bb 485 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
Kojto 119:aae6fcc7d9bb 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
Kojto 119:aae6fcc7d9bb 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
Kojto 119:aae6fcc7d9bb 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
Kojto 119:aae6fcc7d9bb 489 DMA_FLAG_HT5)
Kojto 119:aae6fcc7d9bb 490 #else
bogdanm 84:0b3ab51c8877 491 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
bogdanm 84:0b3ab51c8877 492 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
bogdanm 84:0b3ab51c8877 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
bogdanm 84:0b3ab51c8877 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
bogdanm 84:0b3ab51c8877 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
bogdanm 84:0b3ab51c8877 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
bogdanm 84:0b3ab51c8877 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
bogdanm 84:0b3ab51c8877 498 DMA_FLAG_HT7)
Kojto 119:aae6fcc7d9bb 499 #endif
bogdanm 84:0b3ab51c8877 500 /**
bogdanm 84:0b3ab51c8877 501 * @brief Returns the current DMA Channel transfer error flag.
bogdanm 84:0b3ab51c8877 502 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 503 * @retval The specified transfer error flag index.
bogdanm 84:0b3ab51c8877 504 */
Kojto 119:aae6fcc7d9bb 505 #if defined (STM32L011xx) || defined (STM32L021xx)
Kojto 119:aae6fcc7d9bb 506 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
Kojto 119:aae6fcc7d9bb 507 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
Kojto 119:aae6fcc7d9bb 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
Kojto 119:aae6fcc7d9bb 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
Kojto 119:aae6fcc7d9bb 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
Kojto 119:aae6fcc7d9bb 511 DMA_FLAG_TE5)
Kojto 119:aae6fcc7d9bb 512 #else
bogdanm 84:0b3ab51c8877 513 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
bogdanm 84:0b3ab51c8877 514 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
bogdanm 84:0b3ab51c8877 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
bogdanm 84:0b3ab51c8877 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
bogdanm 84:0b3ab51c8877 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
bogdanm 84:0b3ab51c8877 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
bogdanm 84:0b3ab51c8877 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
bogdanm 84:0b3ab51c8877 520 DMA_FLAG_TE7)
Kojto 119:aae6fcc7d9bb 521 #endif
bogdanm 84:0b3ab51c8877 522 /**
bogdanm 84:0b3ab51c8877 523 * @brief Returns the current DMA Channel Global interrupt flag.
bogdanm 84:0b3ab51c8877 524 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 525 * @retval The specified transfer error flag index.
bogdanm 84:0b3ab51c8877 526 */
Kojto 119:aae6fcc7d9bb 527 #if defined (STM32L011xx) || defined (STM32L021xx)
Kojto 119:aae6fcc7d9bb 528 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
Kojto 119:aae6fcc7d9bb 529 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
Kojto 119:aae6fcc7d9bb 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
Kojto 119:aae6fcc7d9bb 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
Kojto 119:aae6fcc7d9bb 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
Kojto 119:aae6fcc7d9bb 533 DMA_ISR_GIF5)
Kojto 119:aae6fcc7d9bb 534 #else
bogdanm 84:0b3ab51c8877 535 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
bogdanm 84:0b3ab51c8877 536 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
bogdanm 84:0b3ab51c8877 537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
bogdanm 84:0b3ab51c8877 538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
bogdanm 84:0b3ab51c8877 539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
bogdanm 84:0b3ab51c8877 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
bogdanm 84:0b3ab51c8877 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
bogdanm 84:0b3ab51c8877 542 DMA_ISR_GIF7)
Kojto 119:aae6fcc7d9bb 543 #endif
bogdanm 84:0b3ab51c8877 544 /**
bogdanm 84:0b3ab51c8877 545 * @brief Get the DMA Channel pending flags.
bogdanm 84:0b3ab51c8877 546 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 547 * @param __FLAG__: Get the specified flag.
bogdanm 84:0b3ab51c8877 548 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 549 * @arg DMA_FLAG_TCIFx: Transfer complete flag
bogdanm 84:0b3ab51c8877 550 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
bogdanm 84:0b3ab51c8877 551 * @arg DMA_FLAG_TEIFx: Transfer error flag
bogdanm 84:0b3ab51c8877 552 * @arg DMA_ISR_GIFx: Global interrupt flag
bogdanm 84:0b3ab51c8877 553 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
bogdanm 84:0b3ab51c8877 554 * @retval The state of FLAG (SET or RESET).
bogdanm 84:0b3ab51c8877 555 */
bogdanm 84:0b3ab51c8877 556 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
bogdanm 84:0b3ab51c8877 557
bogdanm 84:0b3ab51c8877 558 /**
bogdanm 84:0b3ab51c8877 559 * @brief Clears the DMA Channel pending flags.
bogdanm 84:0b3ab51c8877 560 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 561 * @param __FLAG__: specifies the flag to clear.
bogdanm 84:0b3ab51c8877 562 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 563 * @arg DMA_FLAG_TCIFx: Transfer complete flag
bogdanm 84:0b3ab51c8877 564 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
bogdanm 84:0b3ab51c8877 565 * @arg DMA_FLAG_TEIFx: Transfer error flag
bogdanm 84:0b3ab51c8877 566 * @arg DMA_ISR_GIFx: Global interrupt flag
bogdanm 84:0b3ab51c8877 567 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
bogdanm 84:0b3ab51c8877 568 * @retval None
bogdanm 84:0b3ab51c8877 569 */
bogdanm 92:4fc01daae5a5 570 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
bogdanm 84:0b3ab51c8877 571
bogdanm 84:0b3ab51c8877 572 /**
bogdanm 84:0b3ab51c8877 573 * @brief Enables the specified DMA Channel interrupts.
bogdanm 84:0b3ab51c8877 574 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 575 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 84:0b3ab51c8877 576 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 577 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 84:0b3ab51c8877 578 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 84:0b3ab51c8877 579 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 84:0b3ab51c8877 580 * @retval None
bogdanm 84:0b3ab51c8877 581 */
bogdanm 84:0b3ab51c8877 582 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 583
bogdanm 84:0b3ab51c8877 584 /**
bogdanm 84:0b3ab51c8877 585 * @brief Disables the specified DMA Channel interrupts.
bogdanm 84:0b3ab51c8877 586 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 587 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 84:0b3ab51c8877 588 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 589 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 84:0b3ab51c8877 590 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 84:0b3ab51c8877 591 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 84:0b3ab51c8877 592 * @retval None
bogdanm 84:0b3ab51c8877 593 */
bogdanm 84:0b3ab51c8877 594 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
bogdanm 84:0b3ab51c8877 595
bogdanm 84:0b3ab51c8877 596 /**
Kojto 119:aae6fcc7d9bb 597 * @brief Checks whether the specified DMA Channel interrupt is enabled or not.
bogdanm 84:0b3ab51c8877 598 * @param __HANDLE__: DMA handle
bogdanm 84:0b3ab51c8877 599 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 84:0b3ab51c8877 600 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 601 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 84:0b3ab51c8877 602 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 84:0b3ab51c8877 603 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 84:0b3ab51c8877 604 * @retval The state of DMA_IT (SET or RESET).
bogdanm 84:0b3ab51c8877 605 */
bogdanm 84:0b3ab51c8877 606 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
bogdanm 84:0b3ab51c8877 607
Kojto 96:487b796308b0 608 /**
Kojto 96:487b796308b0 609 * @}
Kojto 96:487b796308b0 610 */
bogdanm 84:0b3ab51c8877 611
bogdanm 84:0b3ab51c8877 612 /* Exported functions --------------------------------------------------------*/
Kojto 96:487b796308b0 613
Kojto 96:487b796308b0 614 /** @defgroup DMA_Exported_Functions DMA Exported Functions
Kojto 96:487b796308b0 615 * @{
Kojto 96:487b796308b0 616 */
Kojto 96:487b796308b0 617
Kojto 96:487b796308b0 618 /** @defgroup DMA_Exported_Functions_Group1 Initialization/de-initialization functions
Kojto 96:487b796308b0 619 * @{
Kojto 96:487b796308b0 620 */
Kojto 96:487b796308b0 621
bogdanm 84:0b3ab51c8877 622 /* Initialization and de-initialization functions *****************************/
bogdanm 84:0b3ab51c8877 623 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 624 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 625
Kojto 96:487b796308b0 626 /**
Kojto 96:487b796308b0 627 * @}
Kojto 96:487b796308b0 628 */
Kojto 96:487b796308b0 629
Kojto 96:487b796308b0 630 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
Kojto 96:487b796308b0 631 * @{
Kojto 96:487b796308b0 632 */
Kojto 96:487b796308b0 633
bogdanm 84:0b3ab51c8877 634 /* IO operation functions *****************************************************/
bogdanm 84:0b3ab51c8877 635 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 84:0b3ab51c8877 636 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 84:0b3ab51c8877 637 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 638 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm 84:0b3ab51c8877 639 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto 96:487b796308b0 640 /**
Kojto 96:487b796308b0 641 * @}
Kojto 96:487b796308b0 642 */
Kojto 96:487b796308b0 643
Kojto 96:487b796308b0 644 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
Kojto 96:487b796308b0 645 * @{
Kojto 96:487b796308b0 646 */
bogdanm 84:0b3ab51c8877 647
bogdanm 84:0b3ab51c8877 648 /* Peripheral State and Error functions ***************************************/
bogdanm 84:0b3ab51c8877 649 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 650 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
bogdanm 84:0b3ab51c8877 651
bogdanm 84:0b3ab51c8877 652 /**
bogdanm 84:0b3ab51c8877 653 * @}
bogdanm 84:0b3ab51c8877 654 */
bogdanm 84:0b3ab51c8877 655
bogdanm 84:0b3ab51c8877 656 /**
bogdanm 84:0b3ab51c8877 657 * @}
bogdanm 84:0b3ab51c8877 658 */
Kojto 119:aae6fcc7d9bb 659 /* Define the private group ***********************************/
Kojto 119:aae6fcc7d9bb 660 /**************************************************************/
Kojto 119:aae6fcc7d9bb 661 /** @defgroup DMA_Private DMA Private
Kojto 119:aae6fcc7d9bb 662 * @{
Kojto 119:aae6fcc7d9bb 663 */
Kojto 119:aae6fcc7d9bb 664 /**
Kojto 119:aae6fcc7d9bb 665 * @}
Kojto 119:aae6fcc7d9bb 666 */
Kojto 119:aae6fcc7d9bb 667 /**************************************************************/
Kojto 96:487b796308b0 668
Kojto 96:487b796308b0 669 /**
Kojto 96:487b796308b0 670 * @}
Kojto 96:487b796308b0 671 */
Kojto 96:487b796308b0 672
Kojto 96:487b796308b0 673 /**
Kojto 96:487b796308b0 674 * @}
Kojto 96:487b796308b0 675 */
bogdanm 84:0b3ab51c8877 676
bogdanm 84:0b3ab51c8877 677 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 678 }
bogdanm 84:0b3ab51c8877 679 #endif
bogdanm 84:0b3ab51c8877 680
bogdanm 84:0b3ab51c8877 681 #endif /* __STM32L0xx_HAL_DMA_H */
bogdanm 84:0b3ab51c8877 682
bogdanm 84:0b3ab51c8877 683 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 96:487b796308b0 684