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TARGET_NUCLEO_F412ZG/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h@132:9baf128c2fab, 2016-12-20 (annotated)

Committer:: <>
Date:: Tue Dec 20 15:36:52 2016 +0000
Revision:: 132:9baf128c2fab
Child:: 145:64910690c574

Release 132 of the mbed library

Ports for Upcoming Targets

3241: Add support for FRDM-KW41 https://github.com/ARMmbed/mbed-os/pull/3241

3291: Adding mbed enabled Maker board with NINA-B1 and EVA-M8Q https://github.com/ARMmbed/mbed-os/pull/3291

Fixes and Changes

3062: TARGET_STM :USB device FS https://github.com/ARMmbed/mbed-os/pull/3062

3213: STM32: Refactor us_ticker.c + hal_tick.c files https://github.com/ARMmbed/mbed-os/pull/3213

3288: Dev spi asynch l0l1 https://github.com/ARMmbed/mbed-os/pull/3288

3289: Bug fix of initial value of interrupt edge in "gpio_irq_init" function. https://github.com/ARMmbed/mbed-os/pull/3289

3302: STM32F4 AnalogIn - Clear VBATE and TSVREFE bits before configuring ADC channels https://github.com/ARMmbed/mbed-os/pull/3302

3320: STM32 - Add ADC_VREF label https://github.com/ARMmbed/mbed-os/pull/3320

3321: no HSE available by default for NUCLEO_L432KC https://github.com/ARMmbed/mbed-os/pull/3321

3352: ublox eva nina - fix line endings https://github.com/ARMmbed/mbed-os/pull/3352

3322: DISCO_L053C8 doesn't support LSE https://github.com/ARMmbed/mbed-os/pull/3322

3345: STM32 - Remove TIM_IT_UPDATE flag in HAL_Suspend/ResumeTick functions https://github.com/ARMmbed/mbed-os/pull/3345

3309: [NUC472/M453] Fix CI failed tests https://github.com/ARMmbed/mbed-os/pull/3309

3157: [Silicon Labs] Adding support for EFR32MG1 wireless SoC https://github.com/ARMmbed/mbed-os/pull/3157

3301: I2C - correct return values for write functions (docs) - part 1 https://github.com/ARMmbed/mbed-os/pull/3301

3303: Fix #2956 #2939 #2957 #2959 #2960: Add HAL_DeInit function in gpio_irq destructor https://github.com/ARMmbed/mbed-os/pull/3303

3304: STM32L476: no HSE is present in NUCLEO and DISCO boards https://github.com/ARMmbed/mbed-os/pull/3304

3318: Register map changes for RevG https://github.com/ARMmbed/mbed-os/pull/3318

3317: NUCLEO_F429ZI has integrated LSE https://github.com/ARMmbed/mbed-os/pull/3317

3312: K64F: SPI Asynch API implementation https://github.com/ARMmbed/mbed-os/pull/3312

3324: Dev i2c common code https://github.com/ARMmbed/mbed-os/pull/3324

3369: Add CAN2 missing pins for connector CN12 https://github.com/ARMmbed/mbed-os/pull/3369

3377: STM32 NUCLEO-L152RE Update system core clock to 32MHz https://github.com/ARMmbed/mbed-os/pull/3377

3378: K66F: Enable LWIP feature https://github.com/ARMmbed/mbed-os/pull/3378

3382: [MAX32620] Fixing serial readable function. https://github.com/ARMmbed/mbed-os/pull/3382

3399: NUCLEO_F103RB - Add SERIAL_FC feature https://github.com/ARMmbed/mbed-os/pull/3399

3409: STM32L1 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3409

3416: Renames i2c_api.c for STM32F1 targets to fix IAR exporter https://github.com/ARMmbed/mbed-os/pull/3416

3348: Fix frequency function of CAN driver. https://github.com/ARMmbed/mbed-os/pull/3348

3366: NUCLEO_F412ZG - Add new platform https://github.com/ARMmbed/mbed-os/pull/3366

3379: STM32F0 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3379

3393: ISR register never re-evaluated in HAL_DMA_PollForTransfer for STM32F4 https://github.com/ARMmbed/mbed-os/pull/3393

3408: STM32F7 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3408

3411: STM32L0 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3411

3424: STM32F4 - FIX to add the update of hdma->State variable https://github.com/ARMmbed/mbed-os/pull/3424

3427: Fix stm i2c slave https://github.com/ARMmbed/mbed-os/pull/3427

3429: Fix stm i2c fix init https://github.com/ARMmbed/mbed-os/pull/3429

3434: [NUC472/M453] Fix stuck in lp_ticker_init and other updates https://github.com/ARMmbed/mbed-os/pull/3434

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	132:9baf128c2fab	1	/**
<>	132:9baf128c2fab	2	******************************************************************************
<>	132:9baf128c2fab	3	* @file stm32f4xx_hal_tim.h
<>	132:9baf128c2fab	4	* @author MCD Application Team
<>	132:9baf128c2fab	5	* @version V1.5.0
<>	132:9baf128c2fab	6	* @date 06-May-2016
<>	132:9baf128c2fab	7	* @brief Header file of TIM HAL module.
<>	132:9baf128c2fab	8	******************************************************************************
<>	132:9baf128c2fab	9	* @attention
<>	132:9baf128c2fab	10	*
<>	132:9baf128c2fab	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	132:9baf128c2fab	12	*
<>	132:9baf128c2fab	13	* Redistribution and use in source and binary forms, with or without modification,
<>	132:9baf128c2fab	14	* are permitted provided that the following conditions are met:
<>	132:9baf128c2fab	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	132:9baf128c2fab	16	* this list of conditions and the following disclaimer.
<>	132:9baf128c2fab	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	132:9baf128c2fab	18	* this list of conditions and the following disclaimer in the documentation
<>	132:9baf128c2fab	19	* and/or other materials provided with the distribution.
<>	132:9baf128c2fab	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	132:9baf128c2fab	21	* may be used to endorse or promote products derived from this software
<>	132:9baf128c2fab	22	* without specific prior written permission.
<>	132:9baf128c2fab	23	*
<>	132:9baf128c2fab	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	132:9baf128c2fab	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	132:9baf128c2fab	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	132:9baf128c2fab	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	132:9baf128c2fab	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	132:9baf128c2fab	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	132:9baf128c2fab	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	132:9baf128c2fab	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	132:9baf128c2fab	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	132:9baf128c2fab	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	132:9baf128c2fab	34	*
<>	132:9baf128c2fab	35	******************************************************************************
<>	132:9baf128c2fab	36	*/
<>	132:9baf128c2fab	37
<>	132:9baf128c2fab	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	132:9baf128c2fab	39	#ifndef __STM32F4xx_HAL_TIM_H
<>	132:9baf128c2fab	40	#define __STM32F4xx_HAL_TIM_H
<>	132:9baf128c2fab	41
<>	132:9baf128c2fab	42	#ifdef __cplusplus
<>	132:9baf128c2fab	43	extern "C" {
<>	132:9baf128c2fab	44	#endif
<>	132:9baf128c2fab	45
<>	132:9baf128c2fab	46	/* Includes ------------------------------------------------------------------*/
<>	132:9baf128c2fab	47	#include "stm32f4xx_hal_def.h"
<>	132:9baf128c2fab	48
<>	132:9baf128c2fab	49	/** @addtogroup STM32F4xx_HAL_Driver
<>	132:9baf128c2fab	50	* @{
<>	132:9baf128c2fab	51	*/
<>	132:9baf128c2fab	52
<>	132:9baf128c2fab	53	/** @addtogroup TIM
<>	132:9baf128c2fab	54	* @{
<>	132:9baf128c2fab	55	*/
<>	132:9baf128c2fab	56
<>	132:9baf128c2fab	57	/* Exported types ------------------------------------------------------------*/
<>	132:9baf128c2fab	58	/** @defgroup TIM_Exported_Types TIM Exported Types
<>	132:9baf128c2fab	59	* @{
<>	132:9baf128c2fab	60	*/
<>	132:9baf128c2fab	61
<>	132:9baf128c2fab	62	/**
<>	132:9baf128c2fab	63	* @brief TIM Time base Configuration Structure definition
<>	132:9baf128c2fab	64	*/
<>	132:9baf128c2fab	65	typedef struct
<>	132:9baf128c2fab	66	{
<>	132:9baf128c2fab	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<>	132:9baf128c2fab	68	This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
<>	132:9baf128c2fab	69
<>	132:9baf128c2fab	70	uint32_t CounterMode; /*!< Specifies the counter mode.
<>	132:9baf128c2fab	71	This parameter can be a value of @ref TIM_Counter_Mode */
<>	132:9baf128c2fab	72
<>	132:9baf128c2fab	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
<>	132:9baf128c2fab	74	Auto-Reload Register at the next update event.
<>	132:9baf128c2fab	75	This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF. */
<>	132:9baf128c2fab	76
<>	132:9baf128c2fab	77	uint32_t ClockDivision; /*!< Specifies the clock division.
<>	132:9baf128c2fab	78	This parameter can be a value of @ref TIM_ClockDivision */
<>	132:9baf128c2fab	79
<>	132:9baf128c2fab	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
<>	132:9baf128c2fab	81	reaches zero, an update event is generated and counting restarts
<>	132:9baf128c2fab	82	from the RCR value (N).
<>	132:9baf128c2fab	83	This means in PWM mode that (N+1) corresponds to:
<>	132:9baf128c2fab	84	- the number of PWM periods in edge-aligned mode
<>	132:9baf128c2fab	85	- the number of half PWM period in center-aligned mode
<>	132:9baf128c2fab	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
<>	132:9baf128c2fab	87	@note This parameter is valid only for TIM1 and TIM8. */
<>	132:9baf128c2fab	88	} TIM_Base_InitTypeDef;
<>	132:9baf128c2fab	89
<>	132:9baf128c2fab	90	/**
<>	132:9baf128c2fab	91	* @brief TIM Output Compare Configuration Structure definition
<>	132:9baf128c2fab	92	*/
<>	132:9baf128c2fab	93
<>	132:9baf128c2fab	94	typedef struct
<>	132:9baf128c2fab	95	{
<>	132:9baf128c2fab	96	uint32_t OCMode; /*!< Specifies the TIM mode.
<>	132:9baf128c2fab	97	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<>	132:9baf128c2fab	98
<>	132:9baf128c2fab	99	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<>	132:9baf128c2fab	100	This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
<>	132:9baf128c2fab	101
<>	132:9baf128c2fab	102	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	132:9baf128c2fab	103	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<>	132:9baf128c2fab	104
<>	132:9baf128c2fab	105	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<>	132:9baf128c2fab	106	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
<>	132:9baf128c2fab	107	@note This parameter is valid only for TIM1 and TIM8. */
<>	132:9baf128c2fab	108
<>	132:9baf128c2fab	109	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
<>	132:9baf128c2fab	110	This parameter can be a value of @ref TIM_Output_Fast_State
<>	132:9baf128c2fab	111	@note This parameter is valid only in PWM1 and PWM2 mode. */
<>	132:9baf128c2fab	112
<>	132:9baf128c2fab	113
<>	132:9baf128c2fab	114	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	132:9baf128c2fab	115	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
<>	132:9baf128c2fab	116	@note This parameter is valid only for TIM1 and TIM8. */
<>	132:9baf128c2fab	117
<>	132:9baf128c2fab	118	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	132:9baf128c2fab	119	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
<>	132:9baf128c2fab	120	@note This parameter is valid only for TIM1 and TIM8. */
<>	132:9baf128c2fab	121	} TIM_OC_InitTypeDef;
<>	132:9baf128c2fab	122
<>	132:9baf128c2fab	123	/**
<>	132:9baf128c2fab	124	* @brief TIM One Pulse Mode Configuration Structure definition
<>	132:9baf128c2fab	125	*/
<>	132:9baf128c2fab	126	typedef struct
<>	132:9baf128c2fab	127	{
<>	132:9baf128c2fab	128	uint32_t OCMode; /*!< Specifies the TIM mode.
<>	132:9baf128c2fab	129	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<>	132:9baf128c2fab	130
<>	132:9baf128c2fab	131	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<>	132:9baf128c2fab	132	This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
<>	132:9baf128c2fab	133
<>	132:9baf128c2fab	134	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	132:9baf128c2fab	135	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<>	132:9baf128c2fab	136
<>	132:9baf128c2fab	137	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<>	132:9baf128c2fab	138	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
<>	132:9baf128c2fab	139	@note This parameter is valid only for TIM1 and TIM8. */
<>	132:9baf128c2fab	140
<>	132:9baf128c2fab	141	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	132:9baf128c2fab	142	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
<>	132:9baf128c2fab	143	@note This parameter is valid only for TIM1 and TIM8. */
<>	132:9baf128c2fab	144
<>	132:9baf128c2fab	145	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	132:9baf128c2fab	146	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
<>	132:9baf128c2fab	147	@note This parameter is valid only for TIM1 and TIM8. */
<>	132:9baf128c2fab	148
<>	132:9baf128c2fab	149	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	132:9baf128c2fab	150	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	132:9baf128c2fab	151
<>	132:9baf128c2fab	152	uint32_t ICSelection; /*!< Specifies the input.
<>	132:9baf128c2fab	153	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	132:9baf128c2fab	154
<>	132:9baf128c2fab	155	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	132:9baf128c2fab	156	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	132:9baf128c2fab	157	} TIM_OnePulse_InitTypeDef;
<>	132:9baf128c2fab	158
<>	132:9baf128c2fab	159
<>	132:9baf128c2fab	160	/**
<>	132:9baf128c2fab	161	* @brief TIM Input Capture Configuration Structure definition
<>	132:9baf128c2fab	162	*/
<>	132:9baf128c2fab	163
<>	132:9baf128c2fab	164	typedef struct
<>	132:9baf128c2fab	165	{
<>	132:9baf128c2fab	166	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	132:9baf128c2fab	167	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	132:9baf128c2fab	168
<>	132:9baf128c2fab	169	uint32_t ICSelection; /*!< Specifies the input.
<>	132:9baf128c2fab	170	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	132:9baf128c2fab	171
<>	132:9baf128c2fab	172	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<>	132:9baf128c2fab	173	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<>	132:9baf128c2fab	174
<>	132:9baf128c2fab	175	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	132:9baf128c2fab	176	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	132:9baf128c2fab	177	} TIM_IC_InitTypeDef;
<>	132:9baf128c2fab	178
<>	132:9baf128c2fab	179	/**
<>	132:9baf128c2fab	180	* @brief TIM Encoder Configuration Structure definition
<>	132:9baf128c2fab	181	*/
<>	132:9baf128c2fab	182
<>	132:9baf128c2fab	183	typedef struct
<>	132:9baf128c2fab	184	{
<>	132:9baf128c2fab	185	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
<>	132:9baf128c2fab	186	This parameter can be a value of @ref TIM_Encoder_Mode */
<>	132:9baf128c2fab	187
<>	132:9baf128c2fab	188	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
<>	132:9baf128c2fab	189	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	132:9baf128c2fab	190
<>	132:9baf128c2fab	191	uint32_t IC1Selection; /*!< Specifies the input.
<>	132:9baf128c2fab	192	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	132:9baf128c2fab	193
<>	132:9baf128c2fab	194	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
<>	132:9baf128c2fab	195	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<>	132:9baf128c2fab	196
<>	132:9baf128c2fab	197	uint32_t IC1Filter; /*!< Specifies the input capture filter.
<>	132:9baf128c2fab	198	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	132:9baf128c2fab	199
<>	132:9baf128c2fab	200	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
<>	132:9baf128c2fab	201	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	132:9baf128c2fab	202
<>	132:9baf128c2fab	203	uint32_t IC2Selection; /*!< Specifies the input.
<>	132:9baf128c2fab	204	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	132:9baf128c2fab	205
<>	132:9baf128c2fab	206	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
<>	132:9baf128c2fab	207	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<>	132:9baf128c2fab	208
<>	132:9baf128c2fab	209	uint32_t IC2Filter; /*!< Specifies the input capture filter.
<>	132:9baf128c2fab	210	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	132:9baf128c2fab	211	} TIM_Encoder_InitTypeDef;
<>	132:9baf128c2fab	212
<>	132:9baf128c2fab	213	/**
<>	132:9baf128c2fab	214	* @brief Clock Configuration Handle Structure definition
<>	132:9baf128c2fab	215	*/
<>	132:9baf128c2fab	216	typedef struct
<>	132:9baf128c2fab	217	{
<>	132:9baf128c2fab	218	uint32_t ClockSource; /*!< TIM clock sources.
<>	132:9baf128c2fab	219	This parameter can be a value of @ref TIM_Clock_Source */
<>	132:9baf128c2fab	220	uint32_t ClockPolarity; /*!< TIM clock polarity.
<>	132:9baf128c2fab	221	This parameter can be a value of @ref TIM_Clock_Polarity */
<>	132:9baf128c2fab	222	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
<>	132:9baf128c2fab	223	This parameter can be a value of @ref TIM_Clock_Prescaler */
<>	132:9baf128c2fab	224	uint32_t ClockFilter; /*!< TIM clock filter.
<>	132:9baf128c2fab	225	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	132:9baf128c2fab	226	}TIM_ClockConfigTypeDef;
<>	132:9baf128c2fab	227
<>	132:9baf128c2fab	228	/**
<>	132:9baf128c2fab	229	* @brief Clear Input Configuration Handle Structure definition
<>	132:9baf128c2fab	230	*/
<>	132:9baf128c2fab	231	typedef struct
<>	132:9baf128c2fab	232	{
<>	132:9baf128c2fab	233	uint32_t ClearInputState; /*!< TIM clear Input state.
<>	132:9baf128c2fab	234	This parameter can be ENABLE or DISABLE */
<>	132:9baf128c2fab	235	uint32_t ClearInputSource; /*!< TIM clear Input sources.
<>	132:9baf128c2fab	236	This parameter can be a value of @ref TIM_ClearInput_Source */
<>	132:9baf128c2fab	237	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
<>	132:9baf128c2fab	238	This parameter can be a value of @ref TIM_ClearInput_Polarity */
<>	132:9baf128c2fab	239	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
<>	132:9baf128c2fab	240	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
<>	132:9baf128c2fab	241	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
<>	132:9baf128c2fab	242	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	132:9baf128c2fab	243	}TIM_ClearInputConfigTypeDef;
<>	132:9baf128c2fab	244
<>	132:9baf128c2fab	245	/**
<>	132:9baf128c2fab	246	* @brief TIM Slave configuration Structure definition
<>	132:9baf128c2fab	247	*/
<>	132:9baf128c2fab	248	typedef struct {
<>	132:9baf128c2fab	249	uint32_t SlaveMode; /*!< Slave mode selection
<>	132:9baf128c2fab	250	This parameter can be a value of @ref TIM_Slave_Mode */
<>	132:9baf128c2fab	251	uint32_t InputTrigger; /*!< Input Trigger source
<>	132:9baf128c2fab	252	This parameter can be a value of @ref TIM_Trigger_Selection */
<>	132:9baf128c2fab	253	uint32_t TriggerPolarity; /*!< Input Trigger polarity
<>	132:9baf128c2fab	254	This parameter can be a value of @ref TIM_Trigger_Polarity */
<>	132:9baf128c2fab	255	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
<>	132:9baf128c2fab	256	This parameter can be a value of @ref TIM_Trigger_Prescaler */
<>	132:9baf128c2fab	257	uint32_t TriggerFilter; /*!< Input trigger filter
<>	132:9baf128c2fab	258	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	132:9baf128c2fab	259
<>	132:9baf128c2fab	260	}TIM_SlaveConfigTypeDef;
<>	132:9baf128c2fab	261
<>	132:9baf128c2fab	262	/**
<>	132:9baf128c2fab	263	* @brief HAL State structures definition
<>	132:9baf128c2fab	264	*/
<>	132:9baf128c2fab	265	typedef enum
<>	132:9baf128c2fab	266	{
<>	132:9baf128c2fab	267	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
<>	132:9baf128c2fab	268	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
<>	132:9baf128c2fab	269	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
<>	132:9baf128c2fab	270	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
<>	132:9baf128c2fab	271	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
<>	132:9baf128c2fab	272	}HAL_TIM_StateTypeDef;
<>	132:9baf128c2fab	273
<>	132:9baf128c2fab	274	/**
<>	132:9baf128c2fab	275	* @brief HAL Active channel structures definition
<>	132:9baf128c2fab	276	*/
<>	132:9baf128c2fab	277	typedef enum
<>	132:9baf128c2fab	278	{
<>	132:9baf128c2fab	279	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
<>	132:9baf128c2fab	280	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
<>	132:9baf128c2fab	281	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
<>	132:9baf128c2fab	282	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
<>	132:9baf128c2fab	283	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
<>	132:9baf128c2fab	284	}HAL_TIM_ActiveChannel;
<>	132:9baf128c2fab	285
<>	132:9baf128c2fab	286	/**
<>	132:9baf128c2fab	287	* @brief TIM Time Base Handle Structure definition
<>	132:9baf128c2fab	288	*/
<>	132:9baf128c2fab	289	typedef struct
<>	132:9baf128c2fab	290	{
<>	132:9baf128c2fab	291	TIM_TypeDef Instance; /!< Register base address */
<>	132:9baf128c2fab	292	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
<>	132:9baf128c2fab	293	HAL_TIM_ActiveChannel Channel; /!< Active channel /
<>	132:9baf128c2fab	294	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
<>	132:9baf128c2fab	295	This array is accessed by a @ref DMA_Handle_index */
<>	132:9baf128c2fab	296	HAL_LockTypeDef Lock; /!< Locking object /
<>	132:9baf128c2fab	297	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
<>	132:9baf128c2fab	298	}TIM_HandleTypeDef;
<>	132:9baf128c2fab	299	/**
<>	132:9baf128c2fab	300	* @}
<>	132:9baf128c2fab	301	*/
<>	132:9baf128c2fab	302
<>	132:9baf128c2fab	303	/* Exported constants --------------------------------------------------------*/
<>	132:9baf128c2fab	304	/** @defgroup TIM_Exported_Constants TIM Exported Constants
<>	132:9baf128c2fab	305	* @{
<>	132:9baf128c2fab	306	*/
<>	132:9baf128c2fab	307
<>	132:9baf128c2fab	308	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
<>	132:9baf128c2fab	309	* @{
<>	132:9baf128c2fab	310	*/
<>	132:9baf128c2fab	311	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /!< Polarity for TIx source /
<>	132:9baf128c2fab	312	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
<>	132:9baf128c2fab	313	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
<>	132:9baf128c2fab	314	/**
<>	132:9baf128c2fab	315	* @}
<>	132:9baf128c2fab	316	*/
<>	132:9baf128c2fab	317
<>	132:9baf128c2fab	318	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
<>	132:9baf128c2fab	319	* @{
<>	132:9baf128c2fab	320	*/
<>	132:9baf128c2fab	321	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
<>	132:9baf128c2fab	322	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x00000000U) /!< Polarity for ETR source /
<>	132:9baf128c2fab	323	/**
<>	132:9baf128c2fab	324	* @}
<>	132:9baf128c2fab	325	*/
<>	132:9baf128c2fab	326
<>	132:9baf128c2fab	327	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
<>	132:9baf128c2fab	328	* @{
<>	132:9baf128c2fab	329	*/
<>	132:9baf128c2fab	330	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x00000000U) /!< No prescaler is used /
<>	132:9baf128c2fab	331	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
<>	132:9baf128c2fab	332	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
<>	132:9baf128c2fab	333	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
<>	132:9baf128c2fab	334	/**
<>	132:9baf128c2fab	335	* @}
<>	132:9baf128c2fab	336	*/
<>	132:9baf128c2fab	337
<>	132:9baf128c2fab	338	/** @defgroup TIM_Counter_Mode TIM Counter Mode
<>	132:9baf128c2fab	339	* @{
<>	132:9baf128c2fab	340	*/
<>	132:9baf128c2fab	341	#define TIM_COUNTERMODE_UP ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	342	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
<>	132:9baf128c2fab	343	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
<>	132:9baf128c2fab	344	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
<>	132:9baf128c2fab	345	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
<>	132:9baf128c2fab	346	/**
<>	132:9baf128c2fab	347	* @}
<>	132:9baf128c2fab	348	*/
<>	132:9baf128c2fab	349
<>	132:9baf128c2fab	350	/** @defgroup TIM_ClockDivision TIM Clock Division
<>	132:9baf128c2fab	351	* @{
<>	132:9baf128c2fab	352	*/
<>	132:9baf128c2fab	353	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	354	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
<>	132:9baf128c2fab	355	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
<>	132:9baf128c2fab	356	/**
<>	132:9baf128c2fab	357	* @}
<>	132:9baf128c2fab	358	*/
<>	132:9baf128c2fab	359
<>	132:9baf128c2fab	360	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
<>	132:9baf128c2fab	361	* @{
<>	132:9baf128c2fab	362	*/
<>	132:9baf128c2fab	363	#define TIM_OCMODE_TIMING ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	364	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
<>	132:9baf128c2fab	365	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
<>	132:9baf128c2fab	366	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
<>	132:9baf128c2fab	367	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
<>	132:9baf128c2fab	368	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
<>	132:9baf128c2fab	369	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
<>	132:9baf128c2fab	370	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
<>	132:9baf128c2fab	371
<>	132:9baf128c2fab	372	/**
<>	132:9baf128c2fab	373	* @}
<>	132:9baf128c2fab	374	*/
<>	132:9baf128c2fab	375
<>	132:9baf128c2fab	376	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
<>	132:9baf128c2fab	377	* @{
<>	132:9baf128c2fab	378	*/
<>	132:9baf128c2fab	379	#define TIM_OCFAST_DISABLE ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	380	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
<>	132:9baf128c2fab	381	/**
<>	132:9baf128c2fab	382	* @}
<>	132:9baf128c2fab	383	*/
<>	132:9baf128c2fab	384
<>	132:9baf128c2fab	385	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
<>	132:9baf128c2fab	386	* @{
<>	132:9baf128c2fab	387	*/
<>	132:9baf128c2fab	388	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	389	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
<>	132:9baf128c2fab	390	/**
<>	132:9baf128c2fab	391	* @}
<>	132:9baf128c2fab	392	*/
<>	132:9baf128c2fab	393
<>	132:9baf128c2fab	394	/** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
<>	132:9baf128c2fab	395	* @{
<>	132:9baf128c2fab	396	*/
<>	132:9baf128c2fab	397	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	398	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
<>	132:9baf128c2fab	399	/**
<>	132:9baf128c2fab	400	* @}
<>	132:9baf128c2fab	401	*/
<>	132:9baf128c2fab	402
<>	132:9baf128c2fab	403	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
<>	132:9baf128c2fab	404	* @{
<>	132:9baf128c2fab	405	*/
<>	132:9baf128c2fab	406	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
<>	132:9baf128c2fab	407	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	408	/**
<>	132:9baf128c2fab	409	* @}
<>	132:9baf128c2fab	410	*/
<>	132:9baf128c2fab	411
<>	132:9baf128c2fab	412	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
<>	132:9baf128c2fab	413	* @{
<>	132:9baf128c2fab	414	*/
<>	132:9baf128c2fab	415	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
<>	132:9baf128c2fab	416	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	417	/**
<>	132:9baf128c2fab	418	* @}
<>	132:9baf128c2fab	419	*/
<>	132:9baf128c2fab	420
<>	132:9baf128c2fab	421	/** @defgroup TIM_Channel TIM Channel
<>	132:9baf128c2fab	422	* @{
<>	132:9baf128c2fab	423	*/
<>	132:9baf128c2fab	424	#define TIM_CHANNEL_1 ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	425	#define TIM_CHANNEL_2 ((uint32_t)0x00000004U)
<>	132:9baf128c2fab	426	#define TIM_CHANNEL_3 ((uint32_t)0x00000008U)
<>	132:9baf128c2fab	427	#define TIM_CHANNEL_4 ((uint32_t)0x0000000CU)
<>	132:9baf128c2fab	428	#define TIM_CHANNEL_ALL ((uint32_t)0x00000018U)
<>	132:9baf128c2fab	429
<>	132:9baf128c2fab	430	/**
<>	132:9baf128c2fab	431	* @}
<>	132:9baf128c2fab	432	*/
<>	132:9baf128c2fab	433
<>	132:9baf128c2fab	434	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
<>	132:9baf128c2fab	435	* @{
<>	132:9baf128c2fab	436	*/
<>	132:9baf128c2fab	437	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
<>	132:9baf128c2fab	438	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
<>	132:9baf128c2fab	439	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
<>	132:9baf128c2fab	440	/**
<>	132:9baf128c2fab	441	* @}
<>	132:9baf128c2fab	442	*/
<>	132:9baf128c2fab	443
<>	132:9baf128c2fab	444	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
<>	132:9baf128c2fab	445	* @{
<>	132:9baf128c2fab	446	*/
<>	132:9baf128c2fab	447	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<>	132:9baf128c2fab	448	connected to IC1, IC2, IC3 or IC4, respectively */
<>	132:9baf128c2fab	449	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<>	132:9baf128c2fab	450	connected to IC2, IC1, IC4 or IC3, respectively */
<>	132:9baf128c2fab	451	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
<>	132:9baf128c2fab	452
<>	132:9baf128c2fab	453	/**
<>	132:9baf128c2fab	454	* @}
<>	132:9baf128c2fab	455	*/
<>	132:9baf128c2fab	456
<>	132:9baf128c2fab	457	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
<>	132:9baf128c2fab	458	* @{
<>	132:9baf128c2fab	459	*/
<>	132:9baf128c2fab	460	#define TIM_ICPSC_DIV1 ((uint32_t)0x00000000U) /!< Capture performed each time an edge is detected on the capture input /
<>	132:9baf128c2fab	461	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
<>	132:9baf128c2fab	462	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
<>	132:9baf128c2fab	463	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
<>	132:9baf128c2fab	464	/**
<>	132:9baf128c2fab	465	* @}
<>	132:9baf128c2fab	466	*/
<>	132:9baf128c2fab	467
<>	132:9baf128c2fab	468	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
<>	132:9baf128c2fab	469	* @{
<>	132:9baf128c2fab	470	*/
<>	132:9baf128c2fab	471	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
<>	132:9baf128c2fab	472	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	473	/**
<>	132:9baf128c2fab	474	* @}
<>	132:9baf128c2fab	475	*/
<>	132:9baf128c2fab	476
<>	132:9baf128c2fab	477	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
<>	132:9baf128c2fab	478	* @{
<>	132:9baf128c2fab	479	*/
<>	132:9baf128c2fab	480	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
<>	132:9baf128c2fab	481	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
<>	132:9baf128c2fab	482	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
<>	132:9baf128c2fab	483
<>	132:9baf128c2fab	484	/**
<>	132:9baf128c2fab	485	* @}
<>	132:9baf128c2fab	486	*/
<>	132:9baf128c2fab	487
<>	132:9baf128c2fab	488	/** @defgroup TIM_Interrupt_definition TIM Interrupt definition
<>	132:9baf128c2fab	489	* @{
<>	132:9baf128c2fab	490	*/
<>	132:9baf128c2fab	491	#define TIM_IT_UPDATE (TIM_DIER_UIE)
<>	132:9baf128c2fab	492	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
<>	132:9baf128c2fab	493	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
<>	132:9baf128c2fab	494	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
<>	132:9baf128c2fab	495	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
<>	132:9baf128c2fab	496	#define TIM_IT_COM (TIM_DIER_COMIE)
<>	132:9baf128c2fab	497	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
<>	132:9baf128c2fab	498	#define TIM_IT_BREAK (TIM_DIER_BIE)
<>	132:9baf128c2fab	499	/**
<>	132:9baf128c2fab	500	* @}
<>	132:9baf128c2fab	501	*/
<>	132:9baf128c2fab	502
<>	132:9baf128c2fab	503	/** @defgroup TIM_Commutation_Source TIM Commutation Source
<>	132:9baf128c2fab	504	* @{
<>	132:9baf128c2fab	505	*/
<>	132:9baf128c2fab	506	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
<>	132:9baf128c2fab	507	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	508	/**
<>	132:9baf128c2fab	509	* @}
<>	132:9baf128c2fab	510	*/
<>	132:9baf128c2fab	511
<>	132:9baf128c2fab	512	/** @defgroup TIM_DMA_sources TIM DMA sources
<>	132:9baf128c2fab	513	* @{
<>	132:9baf128c2fab	514	*/
<>	132:9baf128c2fab	515	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
<>	132:9baf128c2fab	516	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
<>	132:9baf128c2fab	517	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
<>	132:9baf128c2fab	518	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
<>	132:9baf128c2fab	519	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
<>	132:9baf128c2fab	520	#define TIM_DMA_COM (TIM_DIER_COMDE)
<>	132:9baf128c2fab	521	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
<>	132:9baf128c2fab	522	/**
<>	132:9baf128c2fab	523	* @}
<>	132:9baf128c2fab	524	*/
<>	132:9baf128c2fab	525
<>	132:9baf128c2fab	526	/** @defgroup TIM_Event_Source TIM Event Source
<>	132:9baf128c2fab	527	* @{
<>	132:9baf128c2fab	528	*/
<>	132:9baf128c2fab	529	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
<>	132:9baf128c2fab	530	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
<>	132:9baf128c2fab	531	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
<>	132:9baf128c2fab	532	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
<>	132:9baf128c2fab	533	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
<>	132:9baf128c2fab	534	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
<>	132:9baf128c2fab	535	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
<>	132:9baf128c2fab	536	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
<>	132:9baf128c2fab	537
<>	132:9baf128c2fab	538	/**
<>	132:9baf128c2fab	539	* @}
<>	132:9baf128c2fab	540	*/
<>	132:9baf128c2fab	541
<>	132:9baf128c2fab	542	/** @defgroup TIM_Flag_definition TIM Flag definition
<>	132:9baf128c2fab	543	* @{
<>	132:9baf128c2fab	544	*/
<>	132:9baf128c2fab	545	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
<>	132:9baf128c2fab	546	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
<>	132:9baf128c2fab	547	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
<>	132:9baf128c2fab	548	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
<>	132:9baf128c2fab	549	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
<>	132:9baf128c2fab	550	#define TIM_FLAG_COM (TIM_SR_COMIF)
<>	132:9baf128c2fab	551	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
<>	132:9baf128c2fab	552	#define TIM_FLAG_BREAK (TIM_SR_BIF)
<>	132:9baf128c2fab	553	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
<>	132:9baf128c2fab	554	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
<>	132:9baf128c2fab	555	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
<>	132:9baf128c2fab	556	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
<>	132:9baf128c2fab	557	/**
<>	132:9baf128c2fab	558	* @}
<>	132:9baf128c2fab	559	*/
<>	132:9baf128c2fab	560
<>	132:9baf128c2fab	561	/** @defgroup TIM_Clock_Source TIM Clock Source
<>	132:9baf128c2fab	562	* @{
<>	132:9baf128c2fab	563	*/
<>	132:9baf128c2fab	564	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
<>	132:9baf128c2fab	565	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
<>	132:9baf128c2fab	566	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	567	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
<>	132:9baf128c2fab	568	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
<>	132:9baf128c2fab	569	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
<>	132:9baf128c2fab	570	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
<>	132:9baf128c2fab	571	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
<>	132:9baf128c2fab	572	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
<>	132:9baf128c2fab	573	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
<>	132:9baf128c2fab	574	/**
<>	132:9baf128c2fab	575	* @}
<>	132:9baf128c2fab	576	*/
<>	132:9baf128c2fab	577
<>	132:9baf128c2fab	578	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
<>	132:9baf128c2fab	579	* @{
<>	132:9baf128c2fab	580	*/
<>	132:9baf128c2fab	581	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
<>	132:9baf128c2fab	582	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
<>	132:9baf128c2fab	583	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
<>	132:9baf128c2fab	584	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
<>	132:9baf128c2fab	585	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
<>	132:9baf128c2fab	586	/**
<>	132:9baf128c2fab	587	* @}
<>	132:9baf128c2fab	588	*/
<>	132:9baf128c2fab	589
<>	132:9baf128c2fab	590	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
<>	132:9baf128c2fab	591	* @{
<>	132:9baf128c2fab	592	*/
<>	132:9baf128c2fab	593	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
<>	132:9baf128c2fab	594	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
<>	132:9baf128c2fab	595	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
<>	132:9baf128c2fab	596	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
<>	132:9baf128c2fab	597	/**
<>	132:9baf128c2fab	598	* @}
<>	132:9baf128c2fab	599	*/
<>	132:9baf128c2fab	600
<>	132:9baf128c2fab	601	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
<>	132:9baf128c2fab	602	* @{
<>	132:9baf128c2fab	603	*/
<>	132:9baf128c2fab	604	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x00000001U)
<>	132:9baf128c2fab	605	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	606	/**
<>	132:9baf128c2fab	607	* @}
<>	132:9baf128c2fab	608	*/
<>	132:9baf128c2fab	609
<>	132:9baf128c2fab	610	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
<>	132:9baf128c2fab	611	* @{
<>	132:9baf128c2fab	612	*/
<>	132:9baf128c2fab	613	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
<>	132:9baf128c2fab	614	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
<>	132:9baf128c2fab	615	/**
<>	132:9baf128c2fab	616	* @}
<>	132:9baf128c2fab	617	*/
<>	132:9baf128c2fab	618
<>	132:9baf128c2fab	619	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
<>	132:9baf128c2fab	620	* @{
<>	132:9baf128c2fab	621	*/
<>	132:9baf128c2fab	622	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
<>	132:9baf128c2fab	623	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
<>	132:9baf128c2fab	624	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
<>	132:9baf128c2fab	625	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
<>	132:9baf128c2fab	626	/**
<>	132:9baf128c2fab	627	* @}
<>	132:9baf128c2fab	628	*/
<>	132:9baf128c2fab	629
<>	132:9baf128c2fab	630	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
<>	132:9baf128c2fab	631	* @{
<>	132:9baf128c2fab	632	*/
<>	132:9baf128c2fab	633	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
<>	132:9baf128c2fab	634	#define TIM_OSSR_DISABLE ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	635	/**
<>	132:9baf128c2fab	636	* @}
<>	132:9baf128c2fab	637	*/
<>	132:9baf128c2fab	638
<>	132:9baf128c2fab	639	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
<>	132:9baf128c2fab	640	* @{
<>	132:9baf128c2fab	641	*/
<>	132:9baf128c2fab	642	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
<>	132:9baf128c2fab	643	#define TIM_OSSI_DISABLE ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	644	/**
<>	132:9baf128c2fab	645	* @}
<>	132:9baf128c2fab	646	*/
<>	132:9baf128c2fab	647
<>	132:9baf128c2fab	648	/** @defgroup TIM_Lock_level TIM Lock level
<>	132:9baf128c2fab	649	* @{
<>	132:9baf128c2fab	650	*/
<>	132:9baf128c2fab	651	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	652	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
<>	132:9baf128c2fab	653	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
<>	132:9baf128c2fab	654	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
<>	132:9baf128c2fab	655	/**
<>	132:9baf128c2fab	656	* @}
<>	132:9baf128c2fab	657	*/
<>	132:9baf128c2fab	658	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
<>	132:9baf128c2fab	659	* @{
<>	132:9baf128c2fab	660	*/
<>	132:9baf128c2fab	661	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
<>	132:9baf128c2fab	662	#define TIM_BREAK_DISABLE ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	663	/**
<>	132:9baf128c2fab	664	* @}
<>	132:9baf128c2fab	665	*/
<>	132:9baf128c2fab	666
<>	132:9baf128c2fab	667	/** @defgroup TIM_Break_Polarity TIM Break Polarity
<>	132:9baf128c2fab	668	* @{
<>	132:9baf128c2fab	669	*/
<>	132:9baf128c2fab	670	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	671	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
<>	132:9baf128c2fab	672	/**
<>	132:9baf128c2fab	673	* @}
<>	132:9baf128c2fab	674	*/
<>	132:9baf128c2fab	675
<>	132:9baf128c2fab	676	/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
<>	132:9baf128c2fab	677	* @{
<>	132:9baf128c2fab	678	*/
<>	132:9baf128c2fab	679	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
<>	132:9baf128c2fab	680	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	681	/**
<>	132:9baf128c2fab	682	* @}
<>	132:9baf128c2fab	683	*/
<>	132:9baf128c2fab	684
<>	132:9baf128c2fab	685	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
<>	132:9baf128c2fab	686	* @{
<>	132:9baf128c2fab	687	*/
<>	132:9baf128c2fab	688	#define TIM_TRGO_RESET ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	689	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
<>	132:9baf128c2fab	690	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
<>	132:9baf128c2fab	691	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
<>	132:9baf128c2fab	692	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
<>	132:9baf128c2fab	693	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
<>	132:9baf128c2fab	694	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
<>	132:9baf128c2fab	695	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
<>	132:9baf128c2fab	696	/**
<>	132:9baf128c2fab	697	* @}
<>	132:9baf128c2fab	698	*/
<>	132:9baf128c2fab	699
<>	132:9baf128c2fab	700	/** @defgroup TIM_Slave_Mode TIM Slave Mode
<>	132:9baf128c2fab	701	* @{
<>	132:9baf128c2fab	702	*/
<>	132:9baf128c2fab	703	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	704	#define TIM_SLAVEMODE_RESET ((uint32_t)0x00000004U)
<>	132:9baf128c2fab	705	#define TIM_SLAVEMODE_GATED ((uint32_t)0x00000005U)
<>	132:9baf128c2fab	706	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x00000006U)
<>	132:9baf128c2fab	707	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x00000007U)
<>	132:9baf128c2fab	708	/**
<>	132:9baf128c2fab	709	* @}
<>	132:9baf128c2fab	710	*/
<>	132:9baf128c2fab	711
<>	132:9baf128c2fab	712	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
<>	132:9baf128c2fab	713	* @{
<>	132:9baf128c2fab	714	*/
<>	132:9baf128c2fab	715	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x00000080U)
<>	132:9baf128c2fab	716	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	717	/**
<>	132:9baf128c2fab	718	* @}
<>	132:9baf128c2fab	719	*/
<>	132:9baf128c2fab	720
<>	132:9baf128c2fab	721	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
<>	132:9baf128c2fab	722	* @{
<>	132:9baf128c2fab	723	*/
<>	132:9baf128c2fab	724	#define TIM_TS_ITR0 ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	725	#define TIM_TS_ITR1 ((uint32_t)0x00000010U)
<>	132:9baf128c2fab	726	#define TIM_TS_ITR2 ((uint32_t)0x00000020U)
<>	132:9baf128c2fab	727	#define TIM_TS_ITR3 ((uint32_t)0x00000030U)
<>	132:9baf128c2fab	728	#define TIM_TS_TI1F_ED ((uint32_t)0x00000040U)
<>	132:9baf128c2fab	729	#define TIM_TS_TI1FP1 ((uint32_t)0x00000050U)
<>	132:9baf128c2fab	730	#define TIM_TS_TI2FP2 ((uint32_t)0x00000060U)
<>	132:9baf128c2fab	731	#define TIM_TS_ETRF ((uint32_t)0x00000070U)
<>	132:9baf128c2fab	732	#define TIM_TS_NONE ((uint32_t)0x0000FFFFU)
<>	132:9baf128c2fab	733	/**
<>	132:9baf128c2fab	734	* @}
<>	132:9baf128c2fab	735	*/
<>	132:9baf128c2fab	736
<>	132:9baf128c2fab	737	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
<>	132:9baf128c2fab	738	* @{
<>	132:9baf128c2fab	739	*/
<>	132:9baf128c2fab	740	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
<>	132:9baf128c2fab	741	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
<>	132:9baf128c2fab	742	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
<>	132:9baf128c2fab	743	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
<>	132:9baf128c2fab	744	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
<>	132:9baf128c2fab	745	/**
<>	132:9baf128c2fab	746	* @}
<>	132:9baf128c2fab	747	*/
<>	132:9baf128c2fab	748
<>	132:9baf128c2fab	749	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
<>	132:9baf128c2fab	750	* @{
<>	132:9baf128c2fab	751	*/
<>	132:9baf128c2fab	752	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
<>	132:9baf128c2fab	753	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
<>	132:9baf128c2fab	754	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
<>	132:9baf128c2fab	755	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
<>	132:9baf128c2fab	756	/**
<>	132:9baf128c2fab	757	* @}
<>	132:9baf128c2fab	758	*/
<>	132:9baf128c2fab	759
<>	132:9baf128c2fab	760
<>	132:9baf128c2fab	761	/** @defgroup TIM_TI1_Selection TIM TI1 Selection
<>	132:9baf128c2fab	762	* @{
<>	132:9baf128c2fab	763	*/
<>	132:9baf128c2fab	764	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	765	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
<>	132:9baf128c2fab	766	/**
<>	132:9baf128c2fab	767	* @}
<>	132:9baf128c2fab	768	*/
<>	132:9baf128c2fab	769
<>	132:9baf128c2fab	770	/** @defgroup TIM_DMA_Base_address TIM DMA Base address
<>	132:9baf128c2fab	771	* @{
<>	132:9baf128c2fab	772	*/
<>	132:9baf128c2fab	773	#define TIM_DMABASE_CR1 (0x00000000U)
<>	132:9baf128c2fab	774	#define TIM_DMABASE_CR2 (0x00000001U)
<>	132:9baf128c2fab	775	#define TIM_DMABASE_SMCR (0x00000002U)
<>	132:9baf128c2fab	776	#define TIM_DMABASE_DIER (0x00000003U)
<>	132:9baf128c2fab	777	#define TIM_DMABASE_SR (0x00000004U)
<>	132:9baf128c2fab	778	#define TIM_DMABASE_EGR (0x00000005U)
<>	132:9baf128c2fab	779	#define TIM_DMABASE_CCMR1 (0x00000006U)
<>	132:9baf128c2fab	780	#define TIM_DMABASE_CCMR2 (0x00000007U)
<>	132:9baf128c2fab	781	#define TIM_DMABASE_CCER (0x00000008U)
<>	132:9baf128c2fab	782	#define TIM_DMABASE_CNT (0x00000009U)
<>	132:9baf128c2fab	783	#define TIM_DMABASE_PSC (0x0000000AU)
<>	132:9baf128c2fab	784	#define TIM_DMABASE_ARR (0x0000000BU)
<>	132:9baf128c2fab	785	#define TIM_DMABASE_RCR (0x0000000CU)
<>	132:9baf128c2fab	786	#define TIM_DMABASE_CCR1 (0x0000000DU)
<>	132:9baf128c2fab	787	#define TIM_DMABASE_CCR2 (0x0000000EU)
<>	132:9baf128c2fab	788	#define TIM_DMABASE_CCR3 (0x0000000FU)
<>	132:9baf128c2fab	789	#define TIM_DMABASE_CCR4 (0x00000010U)
<>	132:9baf128c2fab	790	#define TIM_DMABASE_BDTR (0x00000011U)
<>	132:9baf128c2fab	791	#define TIM_DMABASE_DCR (0x00000012U)
<>	132:9baf128c2fab	792	#define TIM_DMABASE_OR (0x00000013U)
<>	132:9baf128c2fab	793	/**
<>	132:9baf128c2fab	794	* @}
<>	132:9baf128c2fab	795	*/
<>	132:9baf128c2fab	796
<>	132:9baf128c2fab	797	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
<>	132:9baf128c2fab	798	* @{
<>	132:9baf128c2fab	799	*/
<>	132:9baf128c2fab	800	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
<>	132:9baf128c2fab	801	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
<>	132:9baf128c2fab	802	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
<>	132:9baf128c2fab	803	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
<>	132:9baf128c2fab	804	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
<>	132:9baf128c2fab	805	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
<>	132:9baf128c2fab	806	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
<>	132:9baf128c2fab	807	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
<>	132:9baf128c2fab	808	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
<>	132:9baf128c2fab	809	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
<>	132:9baf128c2fab	810	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
<>	132:9baf128c2fab	811	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
<>	132:9baf128c2fab	812	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
<>	132:9baf128c2fab	813	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
<>	132:9baf128c2fab	814	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
<>	132:9baf128c2fab	815	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
<>	132:9baf128c2fab	816	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
<>	132:9baf128c2fab	817	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
<>	132:9baf128c2fab	818	/**
<>	132:9baf128c2fab	819	* @}
<>	132:9baf128c2fab	820	*/
<>	132:9baf128c2fab	821
<>	132:9baf128c2fab	822	/** @defgroup DMA_Handle_index DMA Handle index
<>	132:9baf128c2fab	823	* @{
<>	132:9baf128c2fab	824	*/
<>	132:9baf128c2fab	825	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000U) /!< Index of the DMA handle used for Update DMA requests /
<>	132:9baf128c2fab	826	#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001U) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
<>	132:9baf128c2fab	827	#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002U) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
<>	132:9baf128c2fab	828	#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003U) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
<>	132:9baf128c2fab	829	#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004U) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
<>	132:9baf128c2fab	830	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005U) /!< Index of the DMA handle used for Commutation DMA requests /
<>	132:9baf128c2fab	831	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006U) /!< Index of the DMA handle used for Trigger DMA requests /
<>	132:9baf128c2fab	832	/**
<>	132:9baf128c2fab	833	* @}
<>	132:9baf128c2fab	834	*/
<>	132:9baf128c2fab	835
<>	132:9baf128c2fab	836	/** @defgroup Channel_CC_State Channel CC State
<>	132:9baf128c2fab	837	* @{
<>	132:9baf128c2fab	838	*/
<>	132:9baf128c2fab	839	#define TIM_CCx_ENABLE ((uint32_t)0x00000001U)
<>	132:9baf128c2fab	840	#define TIM_CCx_DISABLE ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	841	#define TIM_CCxN_ENABLE ((uint32_t)0x00000004U)
<>	132:9baf128c2fab	842	#define TIM_CCxN_DISABLE ((uint32_t)0x00000000U)
<>	132:9baf128c2fab	843	/**
<>	132:9baf128c2fab	844	* @}
<>	132:9baf128c2fab	845	*/
<>	132:9baf128c2fab	846
<>	132:9baf128c2fab	847	/**
<>	132:9baf128c2fab	848	* @}
<>	132:9baf128c2fab	849	*/
<>	132:9baf128c2fab	850
<>	132:9baf128c2fab	851	/* Exported macro ------------------------------------------------------------*/
<>	132:9baf128c2fab	852	/** @defgroup TIM_Exported_Macros TIM Exported Macros
<>	132:9baf128c2fab	853	* @{
<>	132:9baf128c2fab	854	*/
<>	132:9baf128c2fab	855	/** @brief Reset TIM handle state
<>	132:9baf128c2fab	856	* @param __HANDLE__: TIM handle
<>	132:9baf128c2fab	857	* @retval None
<>	132:9baf128c2fab	858	*/
<>	132:9baf128c2fab	859	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
<>	132:9baf128c2fab	860
<>	132:9baf128c2fab	861	/**
<>	132:9baf128c2fab	862	* @brief Enable the TIM peripheral.
<>	132:9baf128c2fab	863	* @param __HANDLE__: TIM handle
<>	132:9baf128c2fab	864	* @retval None
<>	132:9baf128c2fab	865	*/
<>	132:9baf128c2fab	866	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
<>	132:9baf128c2fab	867
<>	132:9baf128c2fab	868	/**
<>	132:9baf128c2fab	869	* @brief Enable the TIM main Output.
<>	132:9baf128c2fab	870	* @param __HANDLE__: TIM handle
<>	132:9baf128c2fab	871	* @retval None
<>	132:9baf128c2fab	872	*/
<>	132:9baf128c2fab	873	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
<>	132:9baf128c2fab	874
<>	132:9baf128c2fab	875
<>	132:9baf128c2fab	876	/**
<>	132:9baf128c2fab	877	* @brief Disable the TIM peripheral.
<>	132:9baf128c2fab	878	* @param __HANDLE__: TIM handle
<>	132:9baf128c2fab	879	* @retval None
<>	132:9baf128c2fab	880	*/
<>	132:9baf128c2fab	881	#define __HAL_TIM_DISABLE(__HANDLE__) \
<>	132:9baf128c2fab	882	do { \
<>	132:9baf128c2fab	883	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
<>	132:9baf128c2fab	884	{ \
<>	132:9baf128c2fab	885	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
<>	132:9baf128c2fab	886	{ \
<>	132:9baf128c2fab	887	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
<>	132:9baf128c2fab	888	} \
<>	132:9baf128c2fab	889	} \
<>	132:9baf128c2fab	890	} while(0)
<>	132:9baf128c2fab	891
<>	132:9baf128c2fab	892	/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
<>	132:9baf128c2fab	893	channels have been disabled */
<>	132:9baf128c2fab	894	/**
<>	132:9baf128c2fab	895	* @brief Disable the TIM main Output.
<>	132:9baf128c2fab	896	* @param __HANDLE__: TIM handle
<>	132:9baf128c2fab	897	* @retval None
<>	132:9baf128c2fab	898	*/
<>	132:9baf128c2fab	899	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
<>	132:9baf128c2fab	900	do { \
<>	132:9baf128c2fab	901	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
<>	132:9baf128c2fab	902	{ \
<>	132:9baf128c2fab	903	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
<>	132:9baf128c2fab	904	{ \
<>	132:9baf128c2fab	905	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
<>	132:9baf128c2fab	906	} \
<>	132:9baf128c2fab	907	} \
<>	132:9baf128c2fab	908	} while(0)
<>	132:9baf128c2fab	909
<>	132:9baf128c2fab	910	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
<>	132:9baf128c2fab	911	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
<>	132:9baf128c2fab	912	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
<>	132:9baf128c2fab	913	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
<>	132:9baf128c2fab	914	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
<>	132:9baf128c2fab	915	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
<>	132:9baf128c2fab	916
<>	132:9baf128c2fab	917	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<>	132:9baf128c2fab	918	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
<>	132:9baf128c2fab	919
<>	132:9baf128c2fab	920	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
<>	132:9baf128c2fab	921	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
<>	132:9baf128c2fab	922
<>	132:9baf128c2fab	923	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
<>	132:9baf128c2fab	924	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
<>	132:9baf128c2fab	925	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
<>	132:9baf128c2fab	926	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
<>	132:9baf128c2fab	927	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
<>	132:9baf128c2fab	928
<>	132:9baf128c2fab	929	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
<>	132:9baf128c2fab	930	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
<>	132:9baf128c2fab	931	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
<>	132:9baf128c2fab	932	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
<>	132:9baf128c2fab	933	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
<>	132:9baf128c2fab	934
<>	132:9baf128c2fab	935	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<>	132:9baf128c2fab	936	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
<>	132:9baf128c2fab	937	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
<>	132:9baf128c2fab	938	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
<>	132:9baf128c2fab	939	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
<>	132:9baf128c2fab	940
<>	132:9baf128c2fab	941	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
<>	132:9baf128c2fab	942	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
<>	132:9baf128c2fab	943	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
<>	132:9baf128c2fab	944	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
<>	132:9baf128c2fab	945	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
<>	132:9baf128c2fab	946
<>	132:9baf128c2fab	947	/**
<>	132:9baf128c2fab	948	* @brief Sets the TIM Capture Compare Register value on runtime without
<>	132:9baf128c2fab	949	* calling another time ConfigChannel function.
<>	132:9baf128c2fab	950	* @param __HANDLE__: TIM handle.
<>	132:9baf128c2fab	951	* @param __CHANNEL__ : TIM Channels to be configured.
<>	132:9baf128c2fab	952	* This parameter can be one of the following values:
<>	132:9baf128c2fab	953	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	132:9baf128c2fab	954	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	132:9baf128c2fab	955	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	132:9baf128c2fab	956	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	132:9baf128c2fab	957	* @param __COMPARE__: specifies the Capture Compare register new value.
<>	132:9baf128c2fab	958	* @retval None
<>	132:9baf128c2fab	959	*/
<>	132:9baf128c2fab	960	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
<>	132:9baf128c2fab	961	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
<>	132:9baf128c2fab	962
<>	132:9baf128c2fab	963	/**
<>	132:9baf128c2fab	964	* @brief Gets the TIM Capture Compare Register value on runtime
<>	132:9baf128c2fab	965	* @param __HANDLE__: TIM handle.
<>	132:9baf128c2fab	966	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
<>	132:9baf128c2fab	967	* This parameter can be one of the following values:
<>	132:9baf128c2fab	968	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
<>	132:9baf128c2fab	969	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
<>	132:9baf128c2fab	970	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
<>	132:9baf128c2fab	971	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
<>	132:9baf128c2fab	972	* @retval None
<>	132:9baf128c2fab	973	*/
<>	132:9baf128c2fab	974	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
<>	132:9baf128c2fab	975	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
<>	132:9baf128c2fab	976
<>	132:9baf128c2fab	977	/**
<>	132:9baf128c2fab	978	* @brief Sets the TIM Counter Register value on runtime.
<>	132:9baf128c2fab	979	* @param __HANDLE__: TIM handle.
<>	132:9baf128c2fab	980	* @param __COUNTER__: specifies the Counter register new value.
<>	132:9baf128c2fab	981	* @retval None
<>	132:9baf128c2fab	982	*/
<>	132:9baf128c2fab	983	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
<>	132:9baf128c2fab	984
<>	132:9baf128c2fab	985	/**
<>	132:9baf128c2fab	986	* @brief Gets the TIM Counter Register value on runtime.
<>	132:9baf128c2fab	987	* @param __HANDLE__: TIM handle.
<>	132:9baf128c2fab	988	* @retval None
<>	132:9baf128c2fab	989	*/
<>	132:9baf128c2fab	990	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
<>	132:9baf128c2fab	991
<>	132:9baf128c2fab	992	/**
<>	132:9baf128c2fab	993	* @brief Sets the TIM Autoreload Register value on runtime without calling
<>	132:9baf128c2fab	994	* another time any Init function.
<>	132:9baf128c2fab	995	* @param __HANDLE__: TIM handle.
<>	132:9baf128c2fab	996	* @param __AUTORELOAD__: specifies the Counter register new value.
<>	132:9baf128c2fab	997	* @retval None
<>	132:9baf128c2fab	998	*/
<>	132:9baf128c2fab	999	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
<>	132:9baf128c2fab	1000	do{ \
<>	132:9baf128c2fab	1001	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
<>	132:9baf128c2fab	1002	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
<>	132:9baf128c2fab	1003	} while(0)
<>	132:9baf128c2fab	1004	/**
<>	132:9baf128c2fab	1005	* @brief Gets the TIM Autoreload Register value on runtime
<>	132:9baf128c2fab	1006	* @param __HANDLE__: TIM handle.
<>	132:9baf128c2fab	1007	* @retval None
<>	132:9baf128c2fab	1008	*/
<>	132:9baf128c2fab	1009	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
<>	132:9baf128c2fab	1010
<>	132:9baf128c2fab	1011	/**
<>	132:9baf128c2fab	1012	* @brief Sets the TIM Clock Division value on runtime without calling
<>	132:9baf128c2fab	1013	* another time any Init function.
<>	132:9baf128c2fab	1014	* @param __HANDLE__: TIM handle.
<>	132:9baf128c2fab	1015	* @param __CKD__: specifies the clock division value.
<>	132:9baf128c2fab	1016	* This parameter can be one of the following value:
<>	132:9baf128c2fab	1017	* @arg TIM_CLOCKDIVISION_DIV1
<>	132:9baf128c2fab	1018	* @arg TIM_CLOCKDIVISION_DIV2
<>	132:9baf128c2fab	1019	* @arg TIM_CLOCKDIVISION_DIV4
<>	132:9baf128c2fab	1020	* @retval None
<>	132:9baf128c2fab	1021	*/
<>	132:9baf128c2fab	1022	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
<>	132:9baf128c2fab	1023	do{ \
<>	132:9baf128c2fab	1024	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
<>	132:9baf128c2fab	1025	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
<>	132:9baf128c2fab	1026	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
<>	132:9baf128c2fab	1027	} while(0)
<>	132:9baf128c2fab	1028	/**
<>	132:9baf128c2fab	1029	* @brief Gets the TIM Clock Division value on runtime
<>	132:9baf128c2fab	1030	* @param __HANDLE__: TIM handle.
<>	132:9baf128c2fab	1031	* @retval None
<>	132:9baf128c2fab	1032	*/
<>	132:9baf128c2fab	1033	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
<>	132:9baf128c2fab	1034
<>	132:9baf128c2fab	1035	/**
<>	132:9baf128c2fab	1036	* @brief Sets the TIM Input Capture prescaler on runtime without calling
<>	132:9baf128c2fab	1037	* another time HAL_TIM_IC_ConfigChannel() function.
<>	132:9baf128c2fab	1038	* @param __HANDLE__: TIM handle.
<>	132:9baf128c2fab	1039	* @param __CHANNEL__ : TIM Channels to be configured.
<>	132:9baf128c2fab	1040	* This parameter can be one of the following values:
<>	132:9baf128c2fab	1041	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	132:9baf128c2fab	1042	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	132:9baf128c2fab	1043	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	132:9baf128c2fab	1044	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	132:9baf128c2fab	1045	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
<>	132:9baf128c2fab	1046	* This parameter can be one of the following values:
<>	132:9baf128c2fab	1047	* @arg TIM_ICPSC_DIV1: no prescaler
<>	132:9baf128c2fab	1048	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
<>	132:9baf128c2fab	1049	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
<>	132:9baf128c2fab	1050	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
<>	132:9baf128c2fab	1051	* @retval None
<>	132:9baf128c2fab	1052	*/
<>	132:9baf128c2fab	1053	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
<>	132:9baf128c2fab	1054	do{ \
<>	132:9baf128c2fab	1055	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
<>	132:9baf128c2fab	1056	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
<>	132:9baf128c2fab	1057	} while(0)
<>	132:9baf128c2fab	1058
<>	132:9baf128c2fab	1059	/**
<>	132:9baf128c2fab	1060	* @brief Gets the TIM Input Capture prescaler on runtime
<>	132:9baf128c2fab	1061	* @param __HANDLE__: TIM handle.
<>	132:9baf128c2fab	1062	* @param __CHANNEL__ : TIM Channels to be configured.
<>	132:9baf128c2fab	1063	* This parameter can be one of the following values:
<>	132:9baf128c2fab	1064	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
<>	132:9baf128c2fab	1065	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
<>	132:9baf128c2fab	1066	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
<>	132:9baf128c2fab	1067	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
<>	132:9baf128c2fab	1068	* @retval None
<>	132:9baf128c2fab	1069	*/
<>	132:9baf128c2fab	1070	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
<>	132:9baf128c2fab	1071	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
<>	132:9baf128c2fab	1072	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
<>	132:9baf128c2fab	1073	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
<>	132:9baf128c2fab	1074	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
<>	132:9baf128c2fab	1075
<>	132:9baf128c2fab	1076	/**
<>	132:9baf128c2fab	1077	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
<>	132:9baf128c2fab	1078	* @param __HANDLE__: TIM handle.
<>	132:9baf128c2fab	1079	* @note When the USR bit of the TIMx_CR1 register is set, only counter
<>	132:9baf128c2fab	1080	* overflow/underflow generates an update interrupt or DMA request (if
<>	132:9baf128c2fab	1081	* enabled)
<>	132:9baf128c2fab	1082	* @retval None
<>	132:9baf128c2fab	1083	*/
<>	132:9baf128c2fab	1084	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
<>	132:9baf128c2fab	1085	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
<>	132:9baf128c2fab	1086
<>	132:9baf128c2fab	1087	/**
<>	132:9baf128c2fab	1088	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
<>	132:9baf128c2fab	1089	* @param __HANDLE__: TIM handle.
<>	132:9baf128c2fab	1090	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
<>	132:9baf128c2fab	1091	* following events generate an update interrupt or DMA request (if
<>	132:9baf128c2fab	1092	* enabled):
<>	132:9baf128c2fab	1093	* _ Counter overflow/underflow
<>	132:9baf128c2fab	1094	* _ Setting the UG bit
<>	132:9baf128c2fab	1095	* _ Update generation through the slave mode controller
<>	132:9baf128c2fab	1096	* @retval None
<>	132:9baf128c2fab	1097	*/
<>	132:9baf128c2fab	1098	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
<>	132:9baf128c2fab	1099	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
<>	132:9baf128c2fab	1100
<>	132:9baf128c2fab	1101	/**
<>	132:9baf128c2fab	1102	* @brief Sets the TIM Capture x input polarity on runtime.
<>	132:9baf128c2fab	1103	* @param __HANDLE__: TIM handle.
<>	132:9baf128c2fab	1104	* @param __CHANNEL__: TIM Channels to be configured.
<>	132:9baf128c2fab	1105	* This parameter can be one of the following values:
<>	132:9baf128c2fab	1106	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	132:9baf128c2fab	1107	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	132:9baf128c2fab	1108	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	132:9baf128c2fab	1109	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	132:9baf128c2fab	1110	* @param __POLARITY__: Polarity for TIx source
<>	132:9baf128c2fab	1111	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
<>	132:9baf128c2fab	1112	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
<>	132:9baf128c2fab	1113	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
<>	132:9baf128c2fab	1114	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
<>	132:9baf128c2fab	1115	* @retval None
<>	132:9baf128c2fab	1116	*/
<>	132:9baf128c2fab	1117	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<>	132:9baf128c2fab	1118	do{ \
<>	132:9baf128c2fab	1119	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
<>	132:9baf128c2fab	1120	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
<>	132:9baf128c2fab	1121	}while(0)
<>	132:9baf128c2fab	1122	/**
<>	132:9baf128c2fab	1123	* @}
<>	132:9baf128c2fab	1124	*/
<>	132:9baf128c2fab	1125
<>	132:9baf128c2fab	1126	/* Include TIM HAL Extension module */
<>	132:9baf128c2fab	1127	#include "stm32f4xx_hal_tim_ex.h"
<>	132:9baf128c2fab	1128
<>	132:9baf128c2fab	1129	/* Exported functions --------------------------------------------------------*/
<>	132:9baf128c2fab	1130	/** @addtogroup TIM_Exported_Functions
<>	132:9baf128c2fab	1131	* @{
<>	132:9baf128c2fab	1132	*/
<>	132:9baf128c2fab	1133
<>	132:9baf128c2fab	1134	/** @addtogroup TIM_Exported_Functions_Group1
<>	132:9baf128c2fab	1135	* @{
<>	132:9baf128c2fab	1136	*/
<>	132:9baf128c2fab	1137
<>	132:9baf128c2fab	1138	/* Time Base functions ********************************************************/
<>	132:9baf128c2fab	1139	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1140	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1141	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1142	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1143	/* Blocking mode: Polling */
<>	132:9baf128c2fab	1144	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1145	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1146	/* Non-Blocking mode: Interrupt */
<>	132:9baf128c2fab	1147	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1148	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1149	/* Non-Blocking mode: DMA */
<>	132:9baf128c2fab	1150	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
<>	132:9baf128c2fab	1151	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1152	/**
<>	132:9baf128c2fab	1153	* @}
<>	132:9baf128c2fab	1154	*/
<>	132:9baf128c2fab	1155
<>	132:9baf128c2fab	1156	/** @addtogroup TIM_Exported_Functions_Group2
<>	132:9baf128c2fab	1157	* @{
<>	132:9baf128c2fab	1158	*/
<>	132:9baf128c2fab	1159	/* Timer Output Compare functions **********************************************/
<>	132:9baf128c2fab	1160	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1161	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1162	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1163	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1164	/* Blocking mode: Polling */
<>	132:9baf128c2fab	1165	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1166	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1167	/* Non-Blocking mode: Interrupt */
<>	132:9baf128c2fab	1168	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1169	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1170	/* Non-Blocking mode: DMA */
<>	132:9baf128c2fab	1171	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	132:9baf128c2fab	1172	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1173
<>	132:9baf128c2fab	1174	/**
<>	132:9baf128c2fab	1175	* @}
<>	132:9baf128c2fab	1176	*/
<>	132:9baf128c2fab	1177
<>	132:9baf128c2fab	1178	/** @addtogroup TIM_Exported_Functions_Group3
<>	132:9baf128c2fab	1179	* @{
<>	132:9baf128c2fab	1180	*/
<>	132:9baf128c2fab	1181	/* Timer PWM functions *********************************************************/
<>	132:9baf128c2fab	1182	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1183	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1184	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1185	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1186	/* Blocking mode: Polling */
<>	132:9baf128c2fab	1187	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1188	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1189	/* Non-Blocking mode: Interrupt */
<>	132:9baf128c2fab	1190	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1191	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1192	/* Non-Blocking mode: DMA */
<>	132:9baf128c2fab	1193	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	132:9baf128c2fab	1194	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1195
<>	132:9baf128c2fab	1196	/**
<>	132:9baf128c2fab	1197	* @}
<>	132:9baf128c2fab	1198	*/
<>	132:9baf128c2fab	1199
<>	132:9baf128c2fab	1200	/** @addtogroup TIM_Exported_Functions_Group4
<>	132:9baf128c2fab	1201	* @{
<>	132:9baf128c2fab	1202	*/
<>	132:9baf128c2fab	1203	/* Timer Input Capture functions ***********************************************/
<>	132:9baf128c2fab	1204	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1205	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1206	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1207	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1208	/* Blocking mode: Polling */
<>	132:9baf128c2fab	1209	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1210	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1211	/* Non-Blocking mode: Interrupt */
<>	132:9baf128c2fab	1212	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1213	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1214	/* Non-Blocking mode: DMA */
<>	132:9baf128c2fab	1215	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	132:9baf128c2fab	1216	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1217
<>	132:9baf128c2fab	1218	/**
<>	132:9baf128c2fab	1219	* @}
<>	132:9baf128c2fab	1220	*/
<>	132:9baf128c2fab	1221
<>	132:9baf128c2fab	1222	/** @addtogroup TIM_Exported_Functions_Group5
<>	132:9baf128c2fab	1223	* @{
<>	132:9baf128c2fab	1224	*/
<>	132:9baf128c2fab	1225	/* Timer One Pulse functions ***************************************************/
<>	132:9baf128c2fab	1226	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
<>	132:9baf128c2fab	1227	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1228	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1229	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1230	/* Blocking mode: Polling */
<>	132:9baf128c2fab	1231	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	132:9baf128c2fab	1232	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	132:9baf128c2fab	1233
<>	132:9baf128c2fab	1234	/* Non-Blocking mode: Interrupt */
<>	132:9baf128c2fab	1235	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	132:9baf128c2fab	1236	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	132:9baf128c2fab	1237
<>	132:9baf128c2fab	1238	/**
<>	132:9baf128c2fab	1239	* @}
<>	132:9baf128c2fab	1240	*/
<>	132:9baf128c2fab	1241
<>	132:9baf128c2fab	1242	/** @addtogroup TIM_Exported_Functions_Group6
<>	132:9baf128c2fab	1243	* @{
<>	132:9baf128c2fab	1244	*/
<>	132:9baf128c2fab	1245	/* Timer Encoder functions *****************************************************/
<>	132:9baf128c2fab	1246	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
<>	132:9baf128c2fab	1247	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1248	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1249	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1250	/* Blocking mode: Polling */
<>	132:9baf128c2fab	1251	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1252	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1253	/* Non-Blocking mode: Interrupt */
<>	132:9baf128c2fab	1254	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1255	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1256	/* Non-Blocking mode: DMA */
<>	132:9baf128c2fab	1257	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
<>	132:9baf128c2fab	1258	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1259
<>	132:9baf128c2fab	1260	/**
<>	132:9baf128c2fab	1261	* @}
<>	132:9baf128c2fab	1262	*/
<>	132:9baf128c2fab	1263
<>	132:9baf128c2fab	1264	/** @addtogroup TIM_Exported_Functions_Group7
<>	132:9baf128c2fab	1265	* @{
<>	132:9baf128c2fab	1266	*/
<>	132:9baf128c2fab	1267	/* Interrupt Handler functions **********************************************/
<>	132:9baf128c2fab	1268	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1269
<>	132:9baf128c2fab	1270	/**
<>	132:9baf128c2fab	1271	* @}
<>	132:9baf128c2fab	1272	*/
<>	132:9baf128c2fab	1273
<>	132:9baf128c2fab	1274	/** @addtogroup TIM_Exported_Functions_Group8
<>	132:9baf128c2fab	1275	* @{
<>	132:9baf128c2fab	1276	*/
<>	132:9baf128c2fab	1277	/* Control functions *********************************************************/
<>	132:9baf128c2fab	1278	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
<>	132:9baf128c2fab	1279	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
<>	132:9baf128c2fab	1280	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
<>	132:9baf128c2fab	1281	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
<>	132:9baf128c2fab	1282	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
<>	132:9baf128c2fab	1283	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
<>	132:9baf128c2fab	1284	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
<>	132:9baf128c2fab	1285	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
<>	132:9baf128c2fab	1286	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
<>	132:9baf128c2fab	1287	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<>	132:9baf128c2fab	1288	uint32_t *BurstBuffer, uint32_t BurstLength);
<>	132:9baf128c2fab	1289	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<>	132:9baf128c2fab	1290	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<>	132:9baf128c2fab	1291	uint32_t *BurstBuffer, uint32_t BurstLength);
<>	132:9baf128c2fab	1292	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<>	132:9baf128c2fab	1293	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
<>	132:9baf128c2fab	1294	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	132:9baf128c2fab	1295
<>	132:9baf128c2fab	1296	/**
<>	132:9baf128c2fab	1297	* @}
<>	132:9baf128c2fab	1298	*/
<>	132:9baf128c2fab	1299
<>	132:9baf128c2fab	1300	/** @addtogroup TIM_Exported_Functions_Group9
<>	132:9baf128c2fab	1301	* @{
<>	132:9baf128c2fab	1302	*/
<>	132:9baf128c2fab	1303	/* Callback in non blocking modes (Interrupt and DMA) *************************/
<>	132:9baf128c2fab	1304	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1305	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1306	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1307	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1308	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1309	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1310
<>	132:9baf128c2fab	1311	/**
<>	132:9baf128c2fab	1312	* @}
<>	132:9baf128c2fab	1313	*/
<>	132:9baf128c2fab	1314
<>	132:9baf128c2fab	1315	/** @addtogroup TIM_Exported_Functions_Group10
<>	132:9baf128c2fab	1316	* @{
<>	132:9baf128c2fab	1317	*/
<>	132:9baf128c2fab	1318	/* Peripheral State functions **************************************************/
<>	132:9baf128c2fab	1319	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1320	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1321	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1322	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1323	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1324	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
<>	132:9baf128c2fab	1325
<>	132:9baf128c2fab	1326	/**
<>	132:9baf128c2fab	1327	* @}
<>	132:9baf128c2fab	1328	*/
<>	132:9baf128c2fab	1329
<>	132:9baf128c2fab	1330	/**
<>	132:9baf128c2fab	1331	* @}
<>	132:9baf128c2fab	1332	*/
<>	132:9baf128c2fab	1333
<>	132:9baf128c2fab	1334	/* Private macros ------------------------------------------------------------*/
<>	132:9baf128c2fab	1335	/** @defgroup TIM_Private_Macros TIM Private Macros
<>	132:9baf128c2fab	1336	* @{
<>	132:9baf128c2fab	1337	*/
<>	132:9baf128c2fab	1338
<>	132:9baf128c2fab	1339	/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
<>	132:9baf128c2fab	1340	* @{
<>	132:9baf128c2fab	1341	*/
<>	132:9baf128c2fab	1342	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
<>	132:9baf128c2fab	1343	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
<>	132:9baf128c2fab	1344	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
<>	132:9baf128c2fab	1345	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
<>	132:9baf128c2fab	1346	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
<>	132:9baf128c2fab	1347
<>	132:9baf128c2fab	1348	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
<>	132:9baf128c2fab	1349	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
<>	132:9baf128c2fab	1350	((DIV) == TIM_CLOCKDIVISION_DIV4))
<>	132:9baf128c2fab	1351
<>	132:9baf128c2fab	1352	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
<>	132:9baf128c2fab	1353	((MODE) == TIM_OCMODE_PWM2))
<>	132:9baf128c2fab	1354
<>	132:9baf128c2fab	1355	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
<>	132:9baf128c2fab	1356	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
<>	132:9baf128c2fab	1357	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
<>	132:9baf128c2fab	1358	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
<>	132:9baf128c2fab	1359	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
<>	132:9baf128c2fab	1360	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
<>	132:9baf128c2fab	1361
<>	132:9baf128c2fab	1362	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
<>	132:9baf128c2fab	1363	((STATE) == TIM_OCFAST_ENABLE))
<>	132:9baf128c2fab	1364
<>	132:9baf128c2fab	1365	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
<>	132:9baf128c2fab	1366	((POLARITY) == TIM_OCPOLARITY_LOW))
<>	132:9baf128c2fab	1367
<>	132:9baf128c2fab	1368	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
<>	132:9baf128c2fab	1369	((POLARITY) == TIM_OCNPOLARITY_LOW))
<>	132:9baf128c2fab	1370
<>	132:9baf128c2fab	1371	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
<>	132:9baf128c2fab	1372	((STATE) == TIM_OCIDLESTATE_RESET))
<>	132:9baf128c2fab	1373
<>	132:9baf128c2fab	1374	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
<>	132:9baf128c2fab	1375	((STATE) == TIM_OCNIDLESTATE_RESET))
<>	132:9baf128c2fab	1376
<>	132:9baf128c2fab	1377	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	132:9baf128c2fab	1378	((CHANNEL) == TIM_CHANNEL_2) \|\| \
<>	132:9baf128c2fab	1379	((CHANNEL) == TIM_CHANNEL_3) \|\| \
<>	132:9baf128c2fab	1380	((CHANNEL) == TIM_CHANNEL_4) \|\| \
<>	132:9baf128c2fab	1381	((CHANNEL) == TIM_CHANNEL_ALL))
<>	132:9baf128c2fab	1382
<>	132:9baf128c2fab	1383	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	132:9baf128c2fab	1384	((CHANNEL) == TIM_CHANNEL_2))
<>	132:9baf128c2fab	1385
<>	132:9baf128c2fab	1386	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	132:9baf128c2fab	1387	((CHANNEL) == TIM_CHANNEL_2) \|\| \
<>	132:9baf128c2fab	1388	((CHANNEL) == TIM_CHANNEL_3))
<>	132:9baf128c2fab	1389
<>	132:9baf128c2fab	1390	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
<>	132:9baf128c2fab	1391	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
<>	132:9baf128c2fab	1392	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
<>	132:9baf128c2fab	1393
<>	132:9baf128c2fab	1394	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
<>	132:9baf128c2fab	1395	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
<>	132:9baf128c2fab	1396	((SELECTION) == TIM_ICSELECTION_TRC))
<>	132:9baf128c2fab	1397
<>	132:9baf128c2fab	1398	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
<>	132:9baf128c2fab	1399	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
<>	132:9baf128c2fab	1400	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
<>	132:9baf128c2fab	1401	((PRESCALER) == TIM_ICPSC_DIV8))
<>	132:9baf128c2fab	1402
<>	132:9baf128c2fab	1403	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
<>	132:9baf128c2fab	1404	((MODE) == TIM_OPMODE_REPETITIVE))
<>	132:9baf128c2fab	1405
<>	132:9baf128c2fab	1406	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
<>	132:9baf128c2fab	1407
<>	132:9baf128c2fab	1408	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
<>	132:9baf128c2fab	1409	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
<>	132:9baf128c2fab	1410	((MODE) == TIM_ENCODERMODE_TI12))
<>	132:9baf128c2fab	1411
<>	132:9baf128c2fab	1412	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
<>	132:9baf128c2fab	1413
<>	132:9baf128c2fab	1414	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
<>	132:9baf128c2fab	1415	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
<>	132:9baf128c2fab	1416	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
<>	132:9baf128c2fab	1417	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
<>	132:9baf128c2fab	1418	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
<>	132:9baf128c2fab	1419	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
<>	132:9baf128c2fab	1420	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
<>	132:9baf128c2fab	1421	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
<>	132:9baf128c2fab	1422	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
<>	132:9baf128c2fab	1423	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
<>	132:9baf128c2fab	1424
<>	132:9baf128c2fab	1425	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
<>	132:9baf128c2fab	1426	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
<>	132:9baf128c2fab	1427	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
<>	132:9baf128c2fab	1428	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
<>	132:9baf128c2fab	1429	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
<>	132:9baf128c2fab	1430
<>	132:9baf128c2fab	1431	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
<>	132:9baf128c2fab	1432	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
<>	132:9baf128c2fab	1433	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
<>	132:9baf128c2fab	1434	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
<>	132:9baf128c2fab	1435
<>	132:9baf128c2fab	1436	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
<>	132:9baf128c2fab	1437
<>	132:9baf128c2fab	1438	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
<>	132:9baf128c2fab	1439	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
<>	132:9baf128c2fab	1440
<>	132:9baf128c2fab	1441	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
<>	132:9baf128c2fab	1442	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
<>	132:9baf128c2fab	1443
<>	132:9baf128c2fab	1444	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
<>	132:9baf128c2fab	1445	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
<>	132:9baf128c2fab	1446	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
<>	132:9baf128c2fab	1447	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
<>	132:9baf128c2fab	1448
<>	132:9baf128c2fab	1449	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
<>	132:9baf128c2fab	1450
<>	132:9baf128c2fab	1451	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
<>	132:9baf128c2fab	1452	((STATE) == TIM_OSSR_DISABLE))
<>	132:9baf128c2fab	1453
<>	132:9baf128c2fab	1454	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
<>	132:9baf128c2fab	1455	((STATE) == TIM_OSSI_DISABLE))
<>	132:9baf128c2fab	1456
<>	132:9baf128c2fab	1457	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
<>	132:9baf128c2fab	1458	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
<>	132:9baf128c2fab	1459	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
<>	132:9baf128c2fab	1460	((LEVEL) == TIM_LOCKLEVEL_3))
<>	132:9baf128c2fab	1461
<>	132:9baf128c2fab	1462	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
<>	132:9baf128c2fab	1463	((STATE) == TIM_BREAK_DISABLE))
<>	132:9baf128c2fab	1464
<>	132:9baf128c2fab	1465	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
<>	132:9baf128c2fab	1466	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
<>	132:9baf128c2fab	1467
<>	132:9baf128c2fab	1468	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
<>	132:9baf128c2fab	1469	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
<>	132:9baf128c2fab	1470
<>	132:9baf128c2fab	1471	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
<>	132:9baf128c2fab	1472	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
<>	132:9baf128c2fab	1473	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
<>	132:9baf128c2fab	1474	((SOURCE) == TIM_TRGO_OC1) \|\| \
<>	132:9baf128c2fab	1475	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
<>	132:9baf128c2fab	1476	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
<>	132:9baf128c2fab	1477	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
<>	132:9baf128c2fab	1478	((SOURCE) == TIM_TRGO_OC4REF))
<>	132:9baf128c2fab	1479
<>	132:9baf128c2fab	1480	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
<>	132:9baf128c2fab	1481	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
<>	132:9baf128c2fab	1482	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
<>	132:9baf128c2fab	1483	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
<>	132:9baf128c2fab	1484	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
<>	132:9baf128c2fab	1485
<>	132:9baf128c2fab	1486	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
<>	132:9baf128c2fab	1487	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
<>	132:9baf128c2fab	1488
<>	132:9baf128c2fab	1489	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
<>	132:9baf128c2fab	1490	((SELECTION) == TIM_TS_ITR1) \|\| \
<>	132:9baf128c2fab	1491	((SELECTION) == TIM_TS_ITR2) \|\| \
<>	132:9baf128c2fab	1492	((SELECTION) == TIM_TS_ITR3) \|\| \
<>	132:9baf128c2fab	1493	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
<>	132:9baf128c2fab	1494	((SELECTION) == TIM_TS_TI1FP1) \|\| \
<>	132:9baf128c2fab	1495	((SELECTION) == TIM_TS_TI2FP2) \|\| \
<>	132:9baf128c2fab	1496	((SELECTION) == TIM_TS_ETRF))
<>	132:9baf128c2fab	1497
<>	132:9baf128c2fab	1498	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
<>	132:9baf128c2fab	1499	((SELECTION) == TIM_TS_ITR1) \|\| \
<>	132:9baf128c2fab	1500	((SELECTION) == TIM_TS_ITR2) \|\| \
<>	132:9baf128c2fab	1501	((SELECTION) == TIM_TS_ITR3) \|\| \
<>	132:9baf128c2fab	1502	((SELECTION) == TIM_TS_NONE))
<>	132:9baf128c2fab	1503
<>	132:9baf128c2fab	1504	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
<>	132:9baf128c2fab	1505	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
<>	132:9baf128c2fab	1506	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
<>	132:9baf128c2fab	1507	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
<>	132:9baf128c2fab	1508	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
<>	132:9baf128c2fab	1509
<>	132:9baf128c2fab	1510	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
<>	132:9baf128c2fab	1511	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
<>	132:9baf128c2fab	1512	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
<>	132:9baf128c2fab	1513	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
<>	132:9baf128c2fab	1514
<>	132:9baf128c2fab	1515	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
<>	132:9baf128c2fab	1516
<>	132:9baf128c2fab	1517	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
<>	132:9baf128c2fab	1518	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
<>	132:9baf128c2fab	1519
<>	132:9baf128c2fab	1520	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
<>	132:9baf128c2fab	1521	((BASE) == TIM_DMABASE_CR2) \|\| \
<>	132:9baf128c2fab	1522	((BASE) == TIM_DMABASE_SMCR) \|\| \
<>	132:9baf128c2fab	1523	((BASE) == TIM_DMABASE_DIER) \|\| \
<>	132:9baf128c2fab	1524	((BASE) == TIM_DMABASE_SR) \|\| \
<>	132:9baf128c2fab	1525	((BASE) == TIM_DMABASE_EGR) \|\| \
<>	132:9baf128c2fab	1526	((BASE) == TIM_DMABASE_CCMR1) \|\| \
<>	132:9baf128c2fab	1527	((BASE) == TIM_DMABASE_CCMR2) \|\| \
<>	132:9baf128c2fab	1528	((BASE) == TIM_DMABASE_CCER) \|\| \
<>	132:9baf128c2fab	1529	((BASE) == TIM_DMABASE_CNT) \|\| \
<>	132:9baf128c2fab	1530	((BASE) == TIM_DMABASE_PSC) \|\| \
<>	132:9baf128c2fab	1531	((BASE) == TIM_DMABASE_ARR) \|\| \
<>	132:9baf128c2fab	1532	((BASE) == TIM_DMABASE_RCR) \|\| \
<>	132:9baf128c2fab	1533	((BASE) == TIM_DMABASE_CCR1) \|\| \
<>	132:9baf128c2fab	1534	((BASE) == TIM_DMABASE_CCR2) \|\| \
<>	132:9baf128c2fab	1535	((BASE) == TIM_DMABASE_CCR3) \|\| \
<>	132:9baf128c2fab	1536	((BASE) == TIM_DMABASE_CCR4) \|\| \
<>	132:9baf128c2fab	1537	((BASE) == TIM_DMABASE_BDTR) \|\| \
<>	132:9baf128c2fab	1538	((BASE) == TIM_DMABASE_DCR) \|\| \
<>	132:9baf128c2fab	1539	((BASE) == TIM_DMABASE_OR))
<>	132:9baf128c2fab	1540
<>	132:9baf128c2fab	1541	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
<>	132:9baf128c2fab	1542	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
<>	132:9baf128c2fab	1543	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
<>	132:9baf128c2fab	1544	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
<>	132:9baf128c2fab	1545	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
<>	132:9baf128c2fab	1546	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
<>	132:9baf128c2fab	1547	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
<>	132:9baf128c2fab	1548	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
<>	132:9baf128c2fab	1549	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
<>	132:9baf128c2fab	1550	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
<>	132:9baf128c2fab	1551	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
<>	132:9baf128c2fab	1552	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
<>	132:9baf128c2fab	1553	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
<>	132:9baf128c2fab	1554	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
<>	132:9baf128c2fab	1555	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
<>	132:9baf128c2fab	1556	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
<>	132:9baf128c2fab	1557	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
<>	132:9baf128c2fab	1558	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
<>	132:9baf128c2fab	1559
<>	132:9baf128c2fab	1560	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0F)
<>	132:9baf128c2fab	1561	/**
<>	132:9baf128c2fab	1562	* @}
<>	132:9baf128c2fab	1563	*/
<>	132:9baf128c2fab	1564
<>	132:9baf128c2fab	1565	/** @defgroup TIM_Mask_Definitions TIM Mask Definition
<>	132:9baf128c2fab	1566	* @{
<>	132:9baf128c2fab	1567	*/
<>	132:9baf128c2fab	1568	/* The counter of a timer instance is disabled only if all the CCx and CCxN
<>	132:9baf128c2fab	1569	channels have been disabled */
<>	132:9baf128c2fab	1570	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
<>	132:9baf128c2fab	1571	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
<>	132:9baf128c2fab	1572	/**
<>	132:9baf128c2fab	1573	* @}
<>	132:9baf128c2fab	1574	*/
<>	132:9baf128c2fab	1575
<>	132:9baf128c2fab	1576	/**
<>	132:9baf128c2fab	1577	* @}
<>	132:9baf128c2fab	1578	*/
<>	132:9baf128c2fab	1579
<>	132:9baf128c2fab	1580	/* Private functions ---------------------------------------------------------*/
<>	132:9baf128c2fab	1581	/** @defgroup TIM_Private_Functions TIM Private Functions
<>	132:9baf128c2fab	1582	* @{
<>	132:9baf128c2fab	1583	*/
<>	132:9baf128c2fab	1584	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
<>	132:9baf128c2fab	1585	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<>	132:9baf128c2fab	1586	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	132:9baf128c2fab	1587	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
<>	132:9baf128c2fab	1588	void TIM_DMAError(DMA_HandleTypeDef *hdma);
<>	132:9baf128c2fab	1589	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
<>	132:9baf128c2fab	1590	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
<>	132:9baf128c2fab	1591	/**
<>	132:9baf128c2fab	1592	* @}
<>	132:9baf128c2fab	1593	*/
<>	132:9baf128c2fab	1594
<>	132:9baf128c2fab	1595	/**
<>	132:9baf128c2fab	1596	* @}
<>	132:9baf128c2fab	1597	*/
<>	132:9baf128c2fab	1598
<>	132:9baf128c2fab	1599	/**
<>	132:9baf128c2fab	1600	* @}
<>	132:9baf128c2fab	1601	*/
<>	132:9baf128c2fab	1602
<>	132:9baf128c2fab	1603	#ifdef __cplusplus
<>	132:9baf128c2fab	1604	}
<>	132:9baf128c2fab	1605	#endif
<>	132:9baf128c2fab	1606
<>	132:9baf128c2fab	1607	#endif /* __STM32F4xx_HAL_TIM_H */
<>	132:9baf128c2fab	1608
<>	132:9baf128c2fab	1609	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/