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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F411RE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h@132:9baf128c2fab, 2016-12-20 (annotated)

Committer:
<>
Date:
Tue Dec 20 15:36:52 2016 +0000
Revision:
132:9baf128c2fab
Parent:
128:9bcdf88f62b0
Child:
143:86740a56073b
Release 132 of the mbed library



Ports for Upcoming Targets



3241: Add support for FRDM-KW41 https://github.com/ARMmbed/mbed-os/pull/3241

3291: Adding mbed enabled Maker board with NINA-B1 and EVA-M8Q https://github.com/ARMmbed/mbed-os/pull/3291



Fixes and Changes



3062: TARGET_STM :USB device FS  https://github.com/ARMmbed/mbed-os/pull/3062

3213: STM32: Refactor us_ticker.c + hal_tick.c files https://github.com/ARMmbed/mbed-os/pull/3213

3288: Dev spi asynch l0l1 https://github.com/ARMmbed/mbed-os/pull/3288

3289: Bug fix of initial value of interrupt edge in "gpio_irq_init" function. https://github.com/ARMmbed/mbed-os/pull/3289

3302: STM32F4 AnalogIn - Clear VBATE and TSVREFE bits before configuring ADC channels https://github.com/ARMmbed/mbed-os/pull/3302

3320: STM32 - Add ADC_VREF label https://github.com/ARMmbed/mbed-os/pull/3320

3321: no HSE available by default for NUCLEO_L432KC https://github.com/ARMmbed/mbed-os/pull/3321

3352: ublox eva nina - fix line endings https://github.com/ARMmbed/mbed-os/pull/3352

3322: DISCO_L053C8 doesn't support LSE https://github.com/ARMmbed/mbed-os/pull/3322

3345: STM32 - Remove TIM_IT_UPDATE flag in HAL_Suspend/ResumeTick functions https://github.com/ARMmbed/mbed-os/pull/3345

3309: [NUC472/M453] Fix CI failed tests https://github.com/ARMmbed/mbed-os/pull/3309

3157: [Silicon Labs] Adding support for EFR32MG1 wireless SoC https://github.com/ARMmbed/mbed-os/pull/3157

3301: I2C - correct return values for write functions (docs) - part 1 https://github.com/ARMmbed/mbed-os/pull/3301

3303: Fix #2956 #2939 #2957 #2959 #2960: Add HAL_DeInit function in gpio_irq destructor https://github.com/ARMmbed/mbed-os/pull/3303

3304: STM32L476: no HSE is present in NUCLEO and DISCO boards https://github.com/ARMmbed/mbed-os/pull/3304

3318: Register map changes for RevG https://github.com/ARMmbed/mbed-os/pull/3318

3317: NUCLEO_F429ZI has integrated LSE https://github.com/ARMmbed/mbed-os/pull/3317

3312: K64F: SPI Asynch API implementation https://github.com/ARMmbed/mbed-os/pull/3312

3324: Dev i2c common code https://github.com/ARMmbed/mbed-os/pull/3324

3369: Add CAN2 missing pins for connector CN12 https://github.com/ARMmbed/mbed-os/pull/3369

3377: STM32 NUCLEO-L152RE Update system core clock to 32MHz https://github.com/ARMmbed/mbed-os/pull/3377

3378: K66F: Enable LWIP feature https://github.com/ARMmbed/mbed-os/pull/3378

3382: [MAX32620] Fixing serial readable function. https://github.com/ARMmbed/mbed-os/pull/3382

3399: NUCLEO_F103RB - Add SERIAL_FC feature https://github.com/ARMmbed/mbed-os/pull/3399

3409: STM32L1 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3409

3416: Renames i2c_api.c for STM32F1 targets to fix IAR exporter https://github.com/ARMmbed/mbed-os/pull/3416

3348: Fix frequency function of CAN driver. https://github.com/ARMmbed/mbed-os/pull/3348

3366: NUCLEO_F412ZG - Add new platform https://github.com/ARMmbed/mbed-os/pull/3366

3379: STM32F0 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3379

3393: ISR register never re-evaluated in HAL_DMA_PollForTransfer for STM32F4 https://github.com/ARMmbed/mbed-os/pull/3393

3408: STM32F7 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3408

3411: STM32L0 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3411

3424: STM32F4 - FIX to add the update of hdma->State variable https://github.com/ARMmbed/mbed-os/pull/3424

3427: Fix stm i2c slave https://github.com/ARMmbed/mbed-os/pull/3427

3429: Fix stm i2c fix init https://github.com/ARMmbed/mbed-os/pull/3429

3434: [NUC472/M453] Fix stuck in lp_ticker_init and other updates https://github.com/ARMmbed/mbed-os/pull/3434

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**
Kojto 122:f9eeca106725 2 ******************************************************************************
Kojto 122:f9eeca106725 3 * @file stm32f4xx_hal_dma.h
Kojto 122:f9eeca106725 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.0
Kojto 122:f9eeca106725 6 * @date 06-May-2016
Kojto 122:f9eeca106725 7 * @brief Header file of DMA HAL module.
Kojto 122:f9eeca106725 8 ******************************************************************************
Kojto 122:f9eeca106725 9 * @attention
Kojto 122:f9eeca106725 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 122:f9eeca106725 12 *
Kojto 122:f9eeca106725 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 14 * are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 122:f9eeca106725 16 * this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 122:f9eeca106725 18 * this list of conditions and the following disclaimer in the documentation
Kojto 122:f9eeca106725 19 * and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 122:f9eeca106725 21 * may be used to endorse or promote products derived from this software
Kojto 122:f9eeca106725 22 * without specific prior written permission.
Kojto 122:f9eeca106725 23 *
Kojto 122:f9eeca106725 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 122:f9eeca106725 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 122:f9eeca106725 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 122:f9eeca106725 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 122:f9eeca106725 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 122:f9eeca106725 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 122:f9eeca106725 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 34 *
Kojto 122:f9eeca106725 35 ******************************************************************************
Kojto 122:f9eeca106725 36 */
Kojto 122:f9eeca106725 37
Kojto 122:f9eeca106725 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 122:f9eeca106725 39 #ifndef __STM32F4xx_HAL_DMA_H
Kojto 122:f9eeca106725 40 #define __STM32F4xx_HAL_DMA_H
Kojto 122:f9eeca106725 41
Kojto 122:f9eeca106725 42 #ifdef __cplusplus
Kojto 122:f9eeca106725 43 extern "C" {
Kojto 122:f9eeca106725 44 #endif
Kojto 122:f9eeca106725 45
Kojto 122:f9eeca106725 46 /* Includes ------------------------------------------------------------------*/
Kojto 122:f9eeca106725 47 #include "stm32f4xx_hal_def.h"
Kojto 122:f9eeca106725 48
Kojto 122:f9eeca106725 49 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 122:f9eeca106725 50 * @{
Kojto 122:f9eeca106725 51 */
Kojto 122:f9eeca106725 52
Kojto 122:f9eeca106725 53 /** @addtogroup DMA
Kojto 122:f9eeca106725 54 * @{
Kojto 122:f9eeca106725 55 */
Kojto 122:f9eeca106725 56
Kojto 122:f9eeca106725 57 /* Exported types ------------------------------------------------------------*/
Kojto 122:f9eeca106725 58
Kojto 122:f9eeca106725 59 /** @defgroup DMA_Exported_Types DMA Exported Types
Kojto 122:f9eeca106725 60 * @brief DMA Exported Types
Kojto 122:f9eeca106725 61 * @{
Kojto 122:f9eeca106725 62 */
Kojto 122:f9eeca106725 63
Kojto 122:f9eeca106725 64 /**
Kojto 122:f9eeca106725 65 * @brief DMA Configuration Structure definition
Kojto 122:f9eeca106725 66 */
Kojto 122:f9eeca106725 67 typedef struct
Kojto 122:f9eeca106725 68 {
Kojto 122:f9eeca106725 69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
Kojto 122:f9eeca106725 70 This parameter can be a value of @ref DMA_Channel_selection */
Kojto 122:f9eeca106725 71
Kojto 122:f9eeca106725 72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
Kojto 122:f9eeca106725 73 from memory to memory or from peripheral to memory.
Kojto 122:f9eeca106725 74 This parameter can be a value of @ref DMA_Data_transfer_direction */
Kojto 122:f9eeca106725 75
Kojto 122:f9eeca106725 76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
Kojto 122:f9eeca106725 77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
Kojto 122:f9eeca106725 78
Kojto 122:f9eeca106725 79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
Kojto 122:f9eeca106725 80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
Kojto 122:f9eeca106725 81
Kojto 122:f9eeca106725 82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
Kojto 122:f9eeca106725 83 This parameter can be a value of @ref DMA_Peripheral_data_size */
Kojto 122:f9eeca106725 84
Kojto 122:f9eeca106725 85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
Kojto 122:f9eeca106725 86 This parameter can be a value of @ref DMA_Memory_data_size */
Kojto 122:f9eeca106725 87
Kojto 122:f9eeca106725 88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
Kojto 122:f9eeca106725 89 This parameter can be a value of @ref DMA_mode
Kojto 122:f9eeca106725 90 @note The circular buffer mode cannot be used if the memory-to-memory
Kojto 122:f9eeca106725 91 data transfer is configured on the selected Stream */
Kojto 122:f9eeca106725 92
Kojto 122:f9eeca106725 93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
Kojto 122:f9eeca106725 94 This parameter can be a value of @ref DMA_Priority_level */
Kojto 122:f9eeca106725 95
Kojto 122:f9eeca106725 96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
Kojto 122:f9eeca106725 97 This parameter can be a value of @ref DMA_FIFO_direct_mode
Kojto 122:f9eeca106725 98 @note The Direct mode (FIFO mode disabled) cannot be used if the
Kojto 122:f9eeca106725 99 memory-to-memory data transfer is configured on the selected stream */
Kojto 122:f9eeca106725 100
Kojto 122:f9eeca106725 101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
Kojto 122:f9eeca106725 102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
Kojto 122:f9eeca106725 103
Kojto 122:f9eeca106725 104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
Kojto 122:f9eeca106725 105 It specifies the amount of data to be transferred in a single non interruptible
Kojto 122:f9eeca106725 106 transaction.
Kojto 122:f9eeca106725 107 This parameter can be a value of @ref DMA_Memory_burst
Kojto 122:f9eeca106725 108 @note The burst mode is possible only if the address Increment mode is enabled. */
Kojto 122:f9eeca106725 109
Kojto 122:f9eeca106725 110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
Kojto 122:f9eeca106725 111 It specifies the amount of data to be transferred in a single non interruptible
Kojto 122:f9eeca106725 112 transaction.
Kojto 122:f9eeca106725 113 This parameter can be a value of @ref DMA_Peripheral_burst
Kojto 122:f9eeca106725 114 @note The burst mode is possible only if the address Increment mode is enabled. */
Kojto 122:f9eeca106725 115 }DMA_InitTypeDef;
Kojto 122:f9eeca106725 116
Kojto 122:f9eeca106725 117
Kojto 122:f9eeca106725 118 /**
Kojto 122:f9eeca106725 119 * @brief HAL DMA State structures definition
Kojto 122:f9eeca106725 120 */
Kojto 122:f9eeca106725 121 typedef enum
Kojto 122:f9eeca106725 122 {
Kojto 122:f9eeca106725 123 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
Kojto 122:f9eeca106725 124 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
<> 132:9baf128c2fab 125 HAL_DMA_STATE_READY_MEM0 = 0x11U, /*!< DMA Mem0 process success */ // FIX
<> 132:9baf128c2fab 126 HAL_DMA_STATE_READY_MEM1 = 0x21U, /*!< DMA Mem1 process success */ // FIX
<> 132:9baf128c2fab 127 HAL_DMA_STATE_READY_HALF_MEM0 = 0x31U, /*!< DMA Mem0 Half process success */ // FIX
<> 132:9baf128c2fab 128 HAL_DMA_STATE_READY_HALF_MEM1 = 0x41U, /*!< DMA Mem1 Half process success */ // FIX
Kojto 122:f9eeca106725 129 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
<> 132:9baf128c2fab 130 HAL_DMA_STATE_BUSY_MEM0 = 0x12U, /*!< DMA Mem0 process is ongoing */ // FIX
<> 132:9baf128c2fab 131 HAL_DMA_STATE_BUSY_MEM1 = 0x22U, /*!< DMA Mem1 process is ongoing */ // FIX
Kojto 122:f9eeca106725 132 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
Kojto 122:f9eeca106725 133 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
Kojto 122:f9eeca106725 134 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
Kojto 122:f9eeca106725 135 }HAL_DMA_StateTypeDef;
Kojto 122:f9eeca106725 136
Kojto 122:f9eeca106725 137 /**
Kojto 122:f9eeca106725 138 * @brief HAL DMA Error Code structure definition
Kojto 122:f9eeca106725 139 */
Kojto 122:f9eeca106725 140 typedef enum
Kojto 122:f9eeca106725 141 {
Kojto 122:f9eeca106725 142 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
Kojto 122:f9eeca106725 143 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
Kojto 122:f9eeca106725 144 }HAL_DMA_LevelCompleteTypeDef;
Kojto 122:f9eeca106725 145
Kojto 122:f9eeca106725 146 /**
Kojto 122:f9eeca106725 147 * @brief HAL DMA Error Code structure definition
Kojto 122:f9eeca106725 148 */
Kojto 122:f9eeca106725 149 typedef enum
Kojto 122:f9eeca106725 150 {
Kojto 122:f9eeca106725 151 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
Kojto 122:f9eeca106725 152 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
Kojto 122:f9eeca106725 153 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
Kojto 122:f9eeca106725 154 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
Kojto 122:f9eeca106725 155 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
Kojto 122:f9eeca106725 156 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
Kojto 122:f9eeca106725 157 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
Kojto 122:f9eeca106725 158 }HAL_DMA_CallbackIDTypeDef;
Kojto 122:f9eeca106725 159
Kojto 122:f9eeca106725 160 /**
Kojto 122:f9eeca106725 161 * @brief DMA handle Structure definition
Kojto 122:f9eeca106725 162 */
Kojto 122:f9eeca106725 163 typedef struct __DMA_HandleTypeDef
Kojto 122:f9eeca106725 164 {
Kojto 122:f9eeca106725 165 DMA_Stream_TypeDef *Instance; /*!< Register base address */
Kojto 122:f9eeca106725 166
Kojto 122:f9eeca106725 167 DMA_InitTypeDef Init; /*!< DMA communication parameters */
Kojto 122:f9eeca106725 168
Kojto 122:f9eeca106725 169 HAL_LockTypeDef Lock; /*!< DMA locking object */
Kojto 122:f9eeca106725 170
Kojto 122:f9eeca106725 171 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
Kojto 122:f9eeca106725 172
Kojto 122:f9eeca106725 173 void *Parent; /*!< Parent object state */
Kojto 122:f9eeca106725 174
Kojto 122:f9eeca106725 175 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
Kojto 122:f9eeca106725 176
Kojto 122:f9eeca106725 177 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
Kojto 122:f9eeca106725 178
Kojto 122:f9eeca106725 179 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
Kojto 122:f9eeca106725 180
Kojto 122:f9eeca106725 181 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
Kojto 122:f9eeca106725 182
Kojto 122:f9eeca106725 183 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
Kojto 122:f9eeca106725 184
Kojto 122:f9eeca106725 185 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
Kojto 122:f9eeca106725 186
Kojto 122:f9eeca106725 187 __IO uint32_t ErrorCode; /*!< DMA Error code */
Kojto 122:f9eeca106725 188
Kojto 122:f9eeca106725 189 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
Kojto 122:f9eeca106725 190
Kojto 122:f9eeca106725 191 uint32_t StreamIndex; /*!< DMA Stream Index */
Kojto 122:f9eeca106725 192
Kojto 122:f9eeca106725 193 }DMA_HandleTypeDef;
Kojto 122:f9eeca106725 194
Kojto 122:f9eeca106725 195 /**
Kojto 122:f9eeca106725 196 * @}
Kojto 122:f9eeca106725 197 */
Kojto 122:f9eeca106725 198
Kojto 122:f9eeca106725 199 /* Exported constants --------------------------------------------------------*/
Kojto 122:f9eeca106725 200
Kojto 122:f9eeca106725 201 /** @defgroup DMA_Exported_Constants DMA Exported Constants
Kojto 122:f9eeca106725 202 * @brief DMA Exported constants
Kojto 122:f9eeca106725 203 * @{
Kojto 122:f9eeca106725 204 */
Kojto 122:f9eeca106725 205
Kojto 122:f9eeca106725 206 /** @defgroup DMA_Error_Code DMA Error Code
Kojto 122:f9eeca106725 207 * @brief DMA Error Code
Kojto 122:f9eeca106725 208 * @{
Kojto 122:f9eeca106725 209 */
Kojto 122:f9eeca106725 210 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
Kojto 122:f9eeca106725 211 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
Kojto 122:f9eeca106725 212 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */
Kojto 122:f9eeca106725 213 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */
Kojto 122:f9eeca106725 214 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
Kojto 122:f9eeca106725 215 #define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */
Kojto 122:f9eeca106725 216 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */
Kojto 122:f9eeca106725 217 #define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */
Kojto 122:f9eeca106725 218 /**
Kojto 122:f9eeca106725 219 * @}
Kojto 122:f9eeca106725 220 */
Kojto 122:f9eeca106725 221
Kojto 122:f9eeca106725 222 /** @defgroup DMA_Channel_selection DMA Channel selection
Kojto 122:f9eeca106725 223 * @brief DMA channel selection
Kojto 122:f9eeca106725 224 * @{
Kojto 122:f9eeca106725 225 */
Kojto 122:f9eeca106725 226 #define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */
Kojto 122:f9eeca106725 227 #define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */
Kojto 122:f9eeca106725 228 #define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */
Kojto 122:f9eeca106725 229 #define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */
Kojto 122:f9eeca106725 230 #define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */
Kojto 122:f9eeca106725 231 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */
Kojto 122:f9eeca106725 232 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */
Kojto 122:f9eeca106725 233 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */
Kojto 122:f9eeca106725 234 /**
Kojto 122:f9eeca106725 235 * @}
Kojto 122:f9eeca106725 236 */
Kojto 122:f9eeca106725 237
Kojto 122:f9eeca106725 238 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
Kojto 122:f9eeca106725 239 * @brief DMA data transfer direction
Kojto 122:f9eeca106725 240 * @{
Kojto 122:f9eeca106725 241 */
Kojto 122:f9eeca106725 242 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
Kojto 122:f9eeca106725 243 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
Kojto 122:f9eeca106725 244 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
Kojto 122:f9eeca106725 245 /**
Kojto 122:f9eeca106725 246 * @}
Kojto 122:f9eeca106725 247 */
Kojto 122:f9eeca106725 248
Kojto 122:f9eeca106725 249 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
Kojto 122:f9eeca106725 250 * @brief DMA peripheral incremented mode
Kojto 122:f9eeca106725 251 * @{
Kojto 122:f9eeca106725 252 */
Kojto 122:f9eeca106725 253 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
Kojto 122:f9eeca106725 254 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
Kojto 122:f9eeca106725 255 /**
Kojto 122:f9eeca106725 256 * @}
Kojto 122:f9eeca106725 257 */
Kojto 122:f9eeca106725 258
Kojto 122:f9eeca106725 259 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
Kojto 122:f9eeca106725 260 * @brief DMA memory incremented mode
Kojto 122:f9eeca106725 261 * @{
Kojto 122:f9eeca106725 262 */
Kojto 122:f9eeca106725 263 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
Kojto 122:f9eeca106725 264 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
Kojto 122:f9eeca106725 265 /**
Kojto 122:f9eeca106725 266 * @}
Kojto 122:f9eeca106725 267 */
Kojto 122:f9eeca106725 268
Kojto 122:f9eeca106725 269 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
Kojto 122:f9eeca106725 270 * @brief DMA peripheral data size
Kojto 122:f9eeca106725 271 * @{
Kojto 122:f9eeca106725 272 */
Kojto 122:f9eeca106725 273 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
Kojto 122:f9eeca106725 274 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
Kojto 122:f9eeca106725 275 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
Kojto 122:f9eeca106725 276 /**
Kojto 122:f9eeca106725 277 * @}
Kojto 122:f9eeca106725 278 */
Kojto 122:f9eeca106725 279
Kojto 122:f9eeca106725 280 /** @defgroup DMA_Memory_data_size DMA Memory data size
Kojto 122:f9eeca106725 281 * @brief DMA memory data size
Kojto 122:f9eeca106725 282 * @{
Kojto 122:f9eeca106725 283 */
Kojto 122:f9eeca106725 284 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
Kojto 122:f9eeca106725 285 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
Kojto 122:f9eeca106725 286 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
Kojto 122:f9eeca106725 287 /**
Kojto 122:f9eeca106725 288 * @}
Kojto 122:f9eeca106725 289 */
Kojto 122:f9eeca106725 290
Kojto 122:f9eeca106725 291 /** @defgroup DMA_mode DMA mode
Kojto 122:f9eeca106725 292 * @brief DMA mode
Kojto 122:f9eeca106725 293 * @{
Kojto 122:f9eeca106725 294 */
Kojto 122:f9eeca106725 295 #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
Kojto 122:f9eeca106725 296 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
Kojto 122:f9eeca106725 297 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
Kojto 122:f9eeca106725 298 /**
Kojto 122:f9eeca106725 299 * @}
Kojto 122:f9eeca106725 300 */
Kojto 122:f9eeca106725 301
Kojto 122:f9eeca106725 302 /** @defgroup DMA_Priority_level DMA Priority level
Kojto 122:f9eeca106725 303 * @brief DMA priority levels
Kojto 122:f9eeca106725 304 * @{
Kojto 122:f9eeca106725 305 */
Kojto 122:f9eeca106725 306 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
Kojto 122:f9eeca106725 307 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
Kojto 122:f9eeca106725 308 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
Kojto 122:f9eeca106725 309 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
Kojto 122:f9eeca106725 310 /**
Kojto 122:f9eeca106725 311 * @}
Kojto 122:f9eeca106725 312 */
Kojto 122:f9eeca106725 313
Kojto 122:f9eeca106725 314 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
Kojto 122:f9eeca106725 315 * @brief DMA FIFO direct mode
Kojto 122:f9eeca106725 316 * @{
Kojto 122:f9eeca106725 317 */
Kojto 122:f9eeca106725 318 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
Kojto 122:f9eeca106725 319 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
Kojto 122:f9eeca106725 320 /**
Kojto 122:f9eeca106725 321 * @}
Kojto 122:f9eeca106725 322 */
Kojto 122:f9eeca106725 323
Kojto 122:f9eeca106725 324 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
Kojto 122:f9eeca106725 325 * @brief DMA FIFO level
Kojto 122:f9eeca106725 326 * @{
Kojto 122:f9eeca106725 327 */
Kojto 122:f9eeca106725 328 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
Kojto 122:f9eeca106725 329 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
Kojto 122:f9eeca106725 330 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
Kojto 122:f9eeca106725 331 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
Kojto 122:f9eeca106725 332 /**
Kojto 122:f9eeca106725 333 * @}
Kojto 122:f9eeca106725 334 */
Kojto 122:f9eeca106725 335
Kojto 122:f9eeca106725 336 /** @defgroup DMA_Memory_burst DMA Memory burst
Kojto 122:f9eeca106725 337 * @brief DMA memory burst
Kojto 122:f9eeca106725 338 * @{
Kojto 122:f9eeca106725 339 */
Kojto 122:f9eeca106725 340 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 341 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
Kojto 122:f9eeca106725 342 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
Kojto 122:f9eeca106725 343 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
Kojto 122:f9eeca106725 344 /**
Kojto 122:f9eeca106725 345 * @}
Kojto 122:f9eeca106725 346 */
Kojto 122:f9eeca106725 347
Kojto 122:f9eeca106725 348 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
Kojto 122:f9eeca106725 349 * @brief DMA peripheral burst
Kojto 122:f9eeca106725 350 * @{
Kojto 122:f9eeca106725 351 */
Kojto 122:f9eeca106725 352 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 353 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
Kojto 122:f9eeca106725 354 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
Kojto 122:f9eeca106725 355 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
Kojto 122:f9eeca106725 356 /**
Kojto 122:f9eeca106725 357 * @}
Kojto 122:f9eeca106725 358 */
Kojto 122:f9eeca106725 359
Kojto 122:f9eeca106725 360 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
Kojto 122:f9eeca106725 361 * @brief DMA interrupts definition
Kojto 122:f9eeca106725 362 * @{
Kojto 122:f9eeca106725 363 */
Kojto 122:f9eeca106725 364 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
Kojto 122:f9eeca106725 365 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
Kojto 122:f9eeca106725 366 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
Kojto 122:f9eeca106725 367 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
Kojto 122:f9eeca106725 368 #define DMA_IT_FE ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 369 /**
Kojto 122:f9eeca106725 370 * @}
Kojto 122:f9eeca106725 371 */
Kojto 122:f9eeca106725 372
Kojto 122:f9eeca106725 373 /** @defgroup DMA_flag_definitions DMA flag definitions
Kojto 122:f9eeca106725 374 * @brief DMA flag definitions
Kojto 122:f9eeca106725 375 * @{
Kojto 122:f9eeca106725 376 */
Kojto 122:f9eeca106725 377 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
Kojto 122:f9eeca106725 378 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
Kojto 122:f9eeca106725 379 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 380 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 381 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 382 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 383 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 384 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 385 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 386 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 387 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 388 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 389 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 390 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 391 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 392 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 393 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
Kojto 122:f9eeca106725 394 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 395 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
Kojto 122:f9eeca106725 396 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
Kojto 122:f9eeca106725 397 /**
Kojto 122:f9eeca106725 398 * @}
Kojto 122:f9eeca106725 399 */
Kojto 122:f9eeca106725 400
Kojto 122:f9eeca106725 401 /**
Kojto 122:f9eeca106725 402 * @}
Kojto 122:f9eeca106725 403 */
Kojto 122:f9eeca106725 404
Kojto 122:f9eeca106725 405 /* Exported macro ------------------------------------------------------------*/
Kojto 122:f9eeca106725 406
Kojto 122:f9eeca106725 407 /** @brief Reset DMA handle state
Kojto 122:f9eeca106725 408 * @param __HANDLE__: specifies the DMA handle.
Kojto 122:f9eeca106725 409 * @retval None
Kojto 122:f9eeca106725 410 */
Kojto 122:f9eeca106725 411 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Kojto 122:f9eeca106725 412
Kojto 122:f9eeca106725 413 /**
Kojto 122:f9eeca106725 414 * @brief Return the current DMA Stream FIFO filled level.
Kojto 122:f9eeca106725 415 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 416 * @retval The FIFO filling state.
Kojto 122:f9eeca106725 417 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
Kojto 122:f9eeca106725 418 * and not empty.
Kojto 122:f9eeca106725 419 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
Kojto 122:f9eeca106725 420 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
Kojto 122:f9eeca106725 421 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
Kojto 122:f9eeca106725 422 * - DMA_FIFOStatus_Empty: when FIFO is empty
Kojto 122:f9eeca106725 423 * - DMA_FIFOStatus_Full: when FIFO is full
Kojto 122:f9eeca106725 424 */
Kojto 122:f9eeca106725 425 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
Kojto 122:f9eeca106725 426
Kojto 122:f9eeca106725 427 /**
Kojto 122:f9eeca106725 428 * @brief Enable the specified DMA Stream.
Kojto 122:f9eeca106725 429 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 430 * @retval None
Kojto 122:f9eeca106725 431 */
Kojto 122:f9eeca106725 432 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
Kojto 122:f9eeca106725 433
Kojto 122:f9eeca106725 434 /**
Kojto 122:f9eeca106725 435 * @brief Disable the specified DMA Stream.
Kojto 122:f9eeca106725 436 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 437 * @retval None
Kojto 122:f9eeca106725 438 */
Kojto 122:f9eeca106725 439 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
Kojto 122:f9eeca106725 440
Kojto 122:f9eeca106725 441 /* Interrupt & Flag management */
Kojto 122:f9eeca106725 442
Kojto 122:f9eeca106725 443 /**
Kojto 122:f9eeca106725 444 * @brief Return the current DMA Stream transfer complete flag.
Kojto 122:f9eeca106725 445 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 446 * @retval The specified transfer complete flag index.
Kojto 122:f9eeca106725 447 */
Kojto 122:f9eeca106725 448 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
Kojto 122:f9eeca106725 449 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
Kojto 122:f9eeca106725 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
Kojto 122:f9eeca106725 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
Kojto 122:f9eeca106725 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
Kojto 122:f9eeca106725 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
Kojto 122:f9eeca106725 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
Kojto 122:f9eeca106725 455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
Kojto 122:f9eeca106725 456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
Kojto 122:f9eeca106725 457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
Kojto 122:f9eeca106725 458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
Kojto 122:f9eeca106725 459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
Kojto 122:f9eeca106725 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
Kojto 122:f9eeca106725 461 DMA_FLAG_TCIF3_7)
Kojto 122:f9eeca106725 462
Kojto 122:f9eeca106725 463 /**
Kojto 122:f9eeca106725 464 * @brief Return the current DMA Stream half transfer complete flag.
Kojto 122:f9eeca106725 465 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 466 * @retval The specified half transfer complete flag index.
Kojto 122:f9eeca106725 467 */
Kojto 122:f9eeca106725 468 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
Kojto 122:f9eeca106725 469 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
Kojto 122:f9eeca106725 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
Kojto 122:f9eeca106725 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
Kojto 122:f9eeca106725 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
Kojto 122:f9eeca106725 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
Kojto 122:f9eeca106725 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
Kojto 122:f9eeca106725 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
Kojto 122:f9eeca106725 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
Kojto 122:f9eeca106725 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
Kojto 122:f9eeca106725 478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
Kojto 122:f9eeca106725 479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
Kojto 122:f9eeca106725 480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
Kojto 122:f9eeca106725 481 DMA_FLAG_HTIF3_7)
Kojto 122:f9eeca106725 482
Kojto 122:f9eeca106725 483 /**
Kojto 122:f9eeca106725 484 * @brief Return the current DMA Stream transfer error flag.
Kojto 122:f9eeca106725 485 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 486 * @retval The specified transfer error flag index.
Kojto 122:f9eeca106725 487 */
Kojto 122:f9eeca106725 488 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
Kojto 122:f9eeca106725 489 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
Kojto 122:f9eeca106725 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
Kojto 122:f9eeca106725 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
Kojto 122:f9eeca106725 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
Kojto 122:f9eeca106725 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
Kojto 122:f9eeca106725 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
Kojto 122:f9eeca106725 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
Kojto 122:f9eeca106725 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
Kojto 122:f9eeca106725 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
Kojto 122:f9eeca106725 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
Kojto 122:f9eeca106725 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
Kojto 122:f9eeca106725 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
Kojto 122:f9eeca106725 501 DMA_FLAG_TEIF3_7)
Kojto 122:f9eeca106725 502
Kojto 122:f9eeca106725 503 /**
Kojto 122:f9eeca106725 504 * @brief Return the current DMA Stream FIFO error flag.
Kojto 122:f9eeca106725 505 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 506 * @retval The specified FIFO error flag index.
Kojto 122:f9eeca106725 507 */
Kojto 122:f9eeca106725 508 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
Kojto 122:f9eeca106725 509 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
Kojto 122:f9eeca106725 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
Kojto 122:f9eeca106725 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
Kojto 122:f9eeca106725 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
Kojto 122:f9eeca106725 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
Kojto 122:f9eeca106725 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
Kojto 122:f9eeca106725 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
Kojto 122:f9eeca106725 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
Kojto 122:f9eeca106725 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
Kojto 122:f9eeca106725 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
Kojto 122:f9eeca106725 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
Kojto 122:f9eeca106725 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
Kojto 122:f9eeca106725 521 DMA_FLAG_FEIF3_7)
Kojto 122:f9eeca106725 522
Kojto 122:f9eeca106725 523 /**
Kojto 122:f9eeca106725 524 * @brief Return the current DMA Stream direct mode error flag.
Kojto 122:f9eeca106725 525 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 526 * @retval The specified direct mode error flag index.
Kojto 122:f9eeca106725 527 */
Kojto 122:f9eeca106725 528 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
Kojto 122:f9eeca106725 529 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
Kojto 122:f9eeca106725 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
Kojto 122:f9eeca106725 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
Kojto 122:f9eeca106725 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
Kojto 122:f9eeca106725 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
Kojto 122:f9eeca106725 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
Kojto 122:f9eeca106725 535 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
Kojto 122:f9eeca106725 536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
Kojto 122:f9eeca106725 537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
Kojto 122:f9eeca106725 538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
Kojto 122:f9eeca106725 539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
Kojto 122:f9eeca106725 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
Kojto 122:f9eeca106725 541 DMA_FLAG_DMEIF3_7)
Kojto 122:f9eeca106725 542
Kojto 122:f9eeca106725 543 /**
Kojto 122:f9eeca106725 544 * @brief Get the DMA Stream pending flags.
Kojto 122:f9eeca106725 545 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 546 * @param __FLAG__: Get the specified flag.
Kojto 122:f9eeca106725 547 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 548 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
Kojto 122:f9eeca106725 549 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
Kojto 122:f9eeca106725 550 * @arg DMA_FLAG_TEIFx: Transfer error flag.
Kojto 122:f9eeca106725 551 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
Kojto 122:f9eeca106725 552 * @arg DMA_FLAG_FEIFx: FIFO error flag.
Kojto 122:f9eeca106725 553 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Kojto 122:f9eeca106725 554 * @retval The state of FLAG (SET or RESET).
Kojto 122:f9eeca106725 555 */
Kojto 122:f9eeca106725 556 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
Kojto 122:f9eeca106725 557 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
Kojto 122:f9eeca106725 558 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
Kojto 122:f9eeca106725 559 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
Kojto 122:f9eeca106725 560
Kojto 122:f9eeca106725 561 /**
Kojto 122:f9eeca106725 562 * @brief Clear the DMA Stream pending flags.
Kojto 122:f9eeca106725 563 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 564 * @param __FLAG__: specifies the flag to clear.
Kojto 122:f9eeca106725 565 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 566 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
Kojto 122:f9eeca106725 567 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
Kojto 122:f9eeca106725 568 * @arg DMA_FLAG_TEIFx: Transfer error flag.
Kojto 122:f9eeca106725 569 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
Kojto 122:f9eeca106725 570 * @arg DMA_FLAG_FEIFx: FIFO error flag.
Kojto 122:f9eeca106725 571 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Kojto 122:f9eeca106725 572 * @retval None
Kojto 122:f9eeca106725 573 */
Kojto 122:f9eeca106725 574 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
Kojto 122:f9eeca106725 575 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
Kojto 122:f9eeca106725 576 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
Kojto 122:f9eeca106725 577 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
Kojto 122:f9eeca106725 578
Kojto 122:f9eeca106725 579 /**
Kojto 122:f9eeca106725 580 * @brief Enable the specified DMA Stream interrupts.
Kojto 122:f9eeca106725 581 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 582 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 122:f9eeca106725 583 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 584 * @arg DMA_IT_TC: Transfer complete interrupt mask.
Kojto 122:f9eeca106725 585 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
Kojto 122:f9eeca106725 586 * @arg DMA_IT_TE: Transfer error interrupt mask.
Kojto 122:f9eeca106725 587 * @arg DMA_IT_FE: FIFO error interrupt mask.
Kojto 122:f9eeca106725 588 * @arg DMA_IT_DME: Direct mode error interrupt.
Kojto 122:f9eeca106725 589 * @retval None
Kojto 122:f9eeca106725 590 */
Kojto 122:f9eeca106725 591 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
Kojto 122:f9eeca106725 592 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
Kojto 122:f9eeca106725 593
Kojto 122:f9eeca106725 594 /**
Kojto 122:f9eeca106725 595 * @brief Disable the specified DMA Stream interrupts.
Kojto 122:f9eeca106725 596 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 597 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 122:f9eeca106725 598 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 599 * @arg DMA_IT_TC: Transfer complete interrupt mask.
Kojto 122:f9eeca106725 600 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
Kojto 122:f9eeca106725 601 * @arg DMA_IT_TE: Transfer error interrupt mask.
Kojto 122:f9eeca106725 602 * @arg DMA_IT_FE: FIFO error interrupt mask.
Kojto 122:f9eeca106725 603 * @arg DMA_IT_DME: Direct mode error interrupt.
Kojto 122:f9eeca106725 604 * @retval None
Kojto 122:f9eeca106725 605 */
Kojto 122:f9eeca106725 606 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
Kojto 122:f9eeca106725 607 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
Kojto 122:f9eeca106725 608
Kojto 122:f9eeca106725 609 /**
Kojto 122:f9eeca106725 610 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
Kojto 122:f9eeca106725 611 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 612 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
Kojto 122:f9eeca106725 613 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 614 * @arg DMA_IT_TC: Transfer complete interrupt mask.
Kojto 122:f9eeca106725 615 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
Kojto 122:f9eeca106725 616 * @arg DMA_IT_TE: Transfer error interrupt mask.
Kojto 122:f9eeca106725 617 * @arg DMA_IT_FE: FIFO error interrupt mask.
Kojto 122:f9eeca106725 618 * @arg DMA_IT_DME: Direct mode error interrupt.
Kojto 122:f9eeca106725 619 * @retval The state of DMA_IT.
Kojto 122:f9eeca106725 620 */
Kojto 122:f9eeca106725 621 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
Kojto 122:f9eeca106725 622 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
Kojto 122:f9eeca106725 623 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
Kojto 122:f9eeca106725 624
Kojto 122:f9eeca106725 625 /**
Kojto 122:f9eeca106725 626 * @brief Writes the number of data units to be transferred on the DMA Stream.
Kojto 122:f9eeca106725 627 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 628 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
Kojto 122:f9eeca106725 629 * Number of data items depends only on the Peripheral data format.
Kojto 122:f9eeca106725 630 *
Kojto 122:f9eeca106725 631 * @note If Peripheral data format is Bytes: number of data units is equal
Kojto 122:f9eeca106725 632 * to total number of bytes to be transferred.
Kojto 122:f9eeca106725 633 *
Kojto 122:f9eeca106725 634 * @note If Peripheral data format is Half-Word: number of data units is
Kojto 122:f9eeca106725 635 * equal to total number of bytes to be transferred / 2.
Kojto 122:f9eeca106725 636 *
Kojto 122:f9eeca106725 637 * @note If Peripheral data format is Word: number of data units is equal
Kojto 122:f9eeca106725 638 * to total number of bytes to be transferred / 4.
Kojto 122:f9eeca106725 639 *
Kojto 122:f9eeca106725 640 * @retval The number of remaining data units in the current DMAy Streamx transfer.
Kojto 122:f9eeca106725 641 */
Kojto 122:f9eeca106725 642 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
Kojto 122:f9eeca106725 643
Kojto 122:f9eeca106725 644 /**
Kojto 122:f9eeca106725 645 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
Kojto 122:f9eeca106725 646 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 647 *
Kojto 122:f9eeca106725 648 * @retval The number of remaining data units in the current DMA Stream transfer.
Kojto 122:f9eeca106725 649 */
Kojto 122:f9eeca106725 650 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
Kojto 122:f9eeca106725 651
Kojto 122:f9eeca106725 652
Kojto 122:f9eeca106725 653 /* Include DMA HAL Extension module */
Kojto 122:f9eeca106725 654 #include "stm32f4xx_hal_dma_ex.h"
Kojto 122:f9eeca106725 655
Kojto 122:f9eeca106725 656 /* Exported functions --------------------------------------------------------*/
Kojto 122:f9eeca106725 657
Kojto 122:f9eeca106725 658 /** @defgroup DMA_Exported_Functions DMA Exported Functions
Kojto 122:f9eeca106725 659 * @brief DMA Exported functions
Kojto 122:f9eeca106725 660 * @{
Kojto 122:f9eeca106725 661 */
Kojto 122:f9eeca106725 662
Kojto 122:f9eeca106725 663 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 122:f9eeca106725 664 * @brief Initialization and de-initialization functions
Kojto 122:f9eeca106725 665 * @{
Kojto 122:f9eeca106725 666 */
Kojto 122:f9eeca106725 667 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 668 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 669 /**
Kojto 122:f9eeca106725 670 * @}
Kojto 122:f9eeca106725 671 */
Kojto 122:f9eeca106725 672
Kojto 122:f9eeca106725 673 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
Kojto 122:f9eeca106725 674 * @brief I/O operation functions
Kojto 122:f9eeca106725 675 * @{
Kojto 122:f9eeca106725 676 */
Kojto 122:f9eeca106725 677 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 122:f9eeca106725 678 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 122:f9eeca106725 679 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 680 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 681 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
Kojto 122:f9eeca106725 682 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 683 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 684 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
Kojto 122:f9eeca106725 685 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
Kojto 122:f9eeca106725 686
Kojto 122:f9eeca106725 687 /**
Kojto 122:f9eeca106725 688 * @}
Kojto 122:f9eeca106725 689 */
Kojto 122:f9eeca106725 690
Kojto 122:f9eeca106725 691 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
Kojto 122:f9eeca106725 692 * @brief Peripheral State functions
Kojto 122:f9eeca106725 693 * @{
Kojto 122:f9eeca106725 694 */
Kojto 122:f9eeca106725 695 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 696 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 697 /**
Kojto 122:f9eeca106725 698 * @}
Kojto 122:f9eeca106725 699 */
Kojto 122:f9eeca106725 700 /**
Kojto 122:f9eeca106725 701 * @}
Kojto 122:f9eeca106725 702 */
Kojto 122:f9eeca106725 703 /* Private Constants -------------------------------------------------------------*/
Kojto 122:f9eeca106725 704 /** @defgroup DMA_Private_Constants DMA Private Constants
Kojto 122:f9eeca106725 705 * @brief DMA private defines and constants
Kojto 122:f9eeca106725 706 * @{
Kojto 122:f9eeca106725 707 */
Kojto 122:f9eeca106725 708 /**
Kojto 122:f9eeca106725 709 * @}
Kojto 122:f9eeca106725 710 */
Kojto 122:f9eeca106725 711
Kojto 122:f9eeca106725 712 /* Private macros ------------------------------------------------------------*/
Kojto 122:f9eeca106725 713 /** @defgroup DMA_Private_Macros DMA Private Macros
Kojto 122:f9eeca106725 714 * @brief DMA private macros
Kojto 122:f9eeca106725 715 * @{
Kojto 122:f9eeca106725 716 */
Kojto 122:f9eeca106725 717 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
Kojto 122:f9eeca106725 718 ((CHANNEL) == DMA_CHANNEL_1) || \
Kojto 122:f9eeca106725 719 ((CHANNEL) == DMA_CHANNEL_2) || \
Kojto 122:f9eeca106725 720 ((CHANNEL) == DMA_CHANNEL_3) || \
Kojto 122:f9eeca106725 721 ((CHANNEL) == DMA_CHANNEL_4) || \
Kojto 122:f9eeca106725 722 ((CHANNEL) == DMA_CHANNEL_5) || \
Kojto 122:f9eeca106725 723 ((CHANNEL) == DMA_CHANNEL_6) || \
Kojto 122:f9eeca106725 724 ((CHANNEL) == DMA_CHANNEL_7))
Kojto 122:f9eeca106725 725
Kojto 122:f9eeca106725 726 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
Kojto 122:f9eeca106725 727 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
Kojto 122:f9eeca106725 728 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto 122:f9eeca106725 729
Kojto 122:f9eeca106725 730 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
Kojto 122:f9eeca106725 731
Kojto 122:f9eeca106725 732 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
Kojto 122:f9eeca106725 733 ((STATE) == DMA_PINC_DISABLE))
Kojto 122:f9eeca106725 734
Kojto 122:f9eeca106725 735 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
Kojto 122:f9eeca106725 736 ((STATE) == DMA_MINC_DISABLE))
Kojto 122:f9eeca106725 737
Kojto 122:f9eeca106725 738 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
Kojto 122:f9eeca106725 739 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
Kojto 122:f9eeca106725 740 ((SIZE) == DMA_PDATAALIGN_WORD))
Kojto 122:f9eeca106725 741
Kojto 122:f9eeca106725 742 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
Kojto 122:f9eeca106725 743 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
Kojto 122:f9eeca106725 744 ((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto 122:f9eeca106725 745
Kojto 122:f9eeca106725 746 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
Kojto 122:f9eeca106725 747 ((MODE) == DMA_CIRCULAR) || \
Kojto 122:f9eeca106725 748 ((MODE) == DMA_PFCTRL))
Kojto 122:f9eeca106725 749
Kojto 122:f9eeca106725 750 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
Kojto 122:f9eeca106725 751 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
Kojto 122:f9eeca106725 752 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
Kojto 122:f9eeca106725 753 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto 122:f9eeca106725 754
Kojto 122:f9eeca106725 755 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
Kojto 122:f9eeca106725 756 ((STATE) == DMA_FIFOMODE_ENABLE))
Kojto 122:f9eeca106725 757
Kojto 122:f9eeca106725 758 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
Kojto 122:f9eeca106725 759 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
Kojto 122:f9eeca106725 760 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
Kojto 122:f9eeca106725 761 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
Kojto 122:f9eeca106725 762
Kojto 122:f9eeca106725 763 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
Kojto 122:f9eeca106725 764 ((BURST) == DMA_MBURST_INC4) || \
Kojto 122:f9eeca106725 765 ((BURST) == DMA_MBURST_INC8) || \
Kojto 122:f9eeca106725 766 ((BURST) == DMA_MBURST_INC16))
Kojto 122:f9eeca106725 767
Kojto 122:f9eeca106725 768 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
Kojto 122:f9eeca106725 769 ((BURST) == DMA_PBURST_INC4) || \
Kojto 122:f9eeca106725 770 ((BURST) == DMA_PBURST_INC8) || \
Kojto 122:f9eeca106725 771 ((BURST) == DMA_PBURST_INC16))
Kojto 122:f9eeca106725 772 /**
Kojto 122:f9eeca106725 773 * @}
Kojto 122:f9eeca106725 774 */
Kojto 122:f9eeca106725 775
Kojto 122:f9eeca106725 776 /* Private functions ---------------------------------------------------------*/
Kojto 122:f9eeca106725 777 /** @defgroup DMA_Private_Functions DMA Private Functions
Kojto 122:f9eeca106725 778 * @brief DMA private functions
Kojto 122:f9eeca106725 779 * @{
Kojto 122:f9eeca106725 780 */
Kojto 122:f9eeca106725 781 /**
Kojto 122:f9eeca106725 782 * @}
Kojto 122:f9eeca106725 783 */
Kojto 122:f9eeca106725 784
Kojto 122:f9eeca106725 785 /**
Kojto 122:f9eeca106725 786 * @}
Kojto 122:f9eeca106725 787 */
Kojto 122:f9eeca106725 788
Kojto 122:f9eeca106725 789 /**
Kojto 122:f9eeca106725 790 * @}
Kojto 122:f9eeca106725 791 */
Kojto 122:f9eeca106725 792
Kojto 122:f9eeca106725 793 #ifdef __cplusplus
Kojto 122:f9eeca106725 794 }
Kojto 122:f9eeca106725 795 #endif
Kojto 122:f9eeca106725 796
Kojto 122:f9eeca106725 797 #endif /* __STM32F4xx_HAL_DMA_H */
Kojto 122:f9eeca106725 798
Kojto 122:f9eeca106725 799 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/