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TARGET_NUCLEO_F411RE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Parent:: 132:9baf128c2fab
Child:: 145:64910690c574

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/**
Kojto	122:f9eeca106725	2	******************************************************************************
Kojto	122:f9eeca106725	3	* @file stm32f4xx_hal_dma.h
Kojto	122:f9eeca106725	4	* @author MCD Application Team
Kojto	122:f9eeca106725	5	* @version V1.5.0
Kojto	122:f9eeca106725	6	* @date 06-May-2016
Kojto	122:f9eeca106725	7	* @brief Header file of DMA HAL module.
Kojto	122:f9eeca106725	8	******************************************************************************
Kojto	122:f9eeca106725	9	* @attention
Kojto	122:f9eeca106725	10	*
Kojto	122:f9eeca106725	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto	122:f9eeca106725	12	*
Kojto	122:f9eeca106725	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	122:f9eeca106725	14	* are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	122:f9eeca106725	16	* this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	122:f9eeca106725	18	* this list of conditions and the following disclaimer in the documentation
Kojto	122:f9eeca106725	19	* and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	122:f9eeca106725	21	* may be used to endorse or promote products derived from this software
Kojto	122:f9eeca106725	22	* without specific prior written permission.
Kojto	122:f9eeca106725	23	*
Kojto	122:f9eeca106725	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	122:f9eeca106725	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	122:f9eeca106725	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	122:f9eeca106725	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	122:f9eeca106725	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	122:f9eeca106725	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	122:f9eeca106725	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	122:f9eeca106725	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	34	*
Kojto	122:f9eeca106725	35	******************************************************************************
Kojto	122:f9eeca106725	36	*/
Kojto	122:f9eeca106725	37
Kojto	122:f9eeca106725	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	122:f9eeca106725	39	#ifndef __STM32F4xx_HAL_DMA_H
Kojto	122:f9eeca106725	40	#define __STM32F4xx_HAL_DMA_H
Kojto	122:f9eeca106725	41
Kojto	122:f9eeca106725	42	#ifdef __cplusplus
Kojto	122:f9eeca106725	43	extern "C" {
Kojto	122:f9eeca106725	44	#endif
Kojto	122:f9eeca106725	45
Kojto	122:f9eeca106725	46	/* Includes ------------------------------------------------------------------*/
Kojto	122:f9eeca106725	47	#include "stm32f4xx_hal_def.h"
Kojto	122:f9eeca106725	48
Kojto	122:f9eeca106725	49	/** @addtogroup STM32F4xx_HAL_Driver
Kojto	122:f9eeca106725	50	* @{
Kojto	122:f9eeca106725	51	*/
Kojto	122:f9eeca106725	52
Kojto	122:f9eeca106725	53	/** @addtogroup DMA
Kojto	122:f9eeca106725	54	* @{
Kojto	122:f9eeca106725	55	*/
Kojto	122:f9eeca106725	56
Kojto	122:f9eeca106725	57	/* Exported types ------------------------------------------------------------*/
Kojto	122:f9eeca106725	58
Kojto	122:f9eeca106725	59	/** @defgroup DMA_Exported_Types DMA Exported Types
Kojto	122:f9eeca106725	60	* @brief DMA Exported Types
Kojto	122:f9eeca106725	61	* @{
Kojto	122:f9eeca106725	62	*/
Kojto	122:f9eeca106725	63
Kojto	122:f9eeca106725	64	/**
Kojto	122:f9eeca106725	65	* @brief DMA Configuration Structure definition
Kojto	122:f9eeca106725	66	*/
Kojto	122:f9eeca106725	67	typedef struct
Kojto	122:f9eeca106725	68	{
Kojto	122:f9eeca106725	69	uint32_t Channel; /*!< Specifies the channel used for the specified stream.
Kojto	122:f9eeca106725	70	This parameter can be a value of @ref DMA_Channel_selection */
Kojto	122:f9eeca106725	71
Kojto	122:f9eeca106725	72	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
Kojto	122:f9eeca106725	73	from memory to memory or from peripheral to memory.
Kojto	122:f9eeca106725	74	This parameter can be a value of @ref DMA_Data_transfer_direction */
Kojto	122:f9eeca106725	75
Kojto	122:f9eeca106725	76	uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
Kojto	122:f9eeca106725	77	This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
Kojto	122:f9eeca106725	78
Kojto	122:f9eeca106725	79	uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
Kojto	122:f9eeca106725	80	This parameter can be a value of @ref DMA_Memory_incremented_mode */
Kojto	122:f9eeca106725	81
Kojto	122:f9eeca106725	82	uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
Kojto	122:f9eeca106725	83	This parameter can be a value of @ref DMA_Peripheral_data_size */
Kojto	122:f9eeca106725	84
Kojto	122:f9eeca106725	85	uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
Kojto	122:f9eeca106725	86	This parameter can be a value of @ref DMA_Memory_data_size */
Kojto	122:f9eeca106725	87
Kojto	122:f9eeca106725	88	uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
Kojto	122:f9eeca106725	89	This parameter can be a value of @ref DMA_mode
Kojto	122:f9eeca106725	90	@note The circular buffer mode cannot be used if the memory-to-memory
Kojto	122:f9eeca106725	91	data transfer is configured on the selected Stream */
Kojto	122:f9eeca106725	92
Kojto	122:f9eeca106725	93	uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
Kojto	122:f9eeca106725	94	This parameter can be a value of @ref DMA_Priority_level */
Kojto	122:f9eeca106725	95
Kojto	122:f9eeca106725	96	uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
Kojto	122:f9eeca106725	97	This parameter can be a value of @ref DMA_FIFO_direct_mode
Kojto	122:f9eeca106725	98	@note The Direct mode (FIFO mode disabled) cannot be used if the
Kojto	122:f9eeca106725	99	memory-to-memory data transfer is configured on the selected stream */
Kojto	122:f9eeca106725	100
Kojto	122:f9eeca106725	101	uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
Kojto	122:f9eeca106725	102	This parameter can be a value of @ref DMA_FIFO_threshold_level */
Kojto	122:f9eeca106725	103
Kojto	122:f9eeca106725	104	uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
Kojto	122:f9eeca106725	105	It specifies the amount of data to be transferred in a single non interruptible
Kojto	122:f9eeca106725	106	transaction.
Kojto	122:f9eeca106725	107	This parameter can be a value of @ref DMA_Memory_burst
Kojto	122:f9eeca106725	108	@note The burst mode is possible only if the address Increment mode is enabled. */
Kojto	122:f9eeca106725	109
Kojto	122:f9eeca106725	110	uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
Kojto	122:f9eeca106725	111	It specifies the amount of data to be transferred in a single non interruptible
Kojto	122:f9eeca106725	112	transaction.
Kojto	122:f9eeca106725	113	This parameter can be a value of @ref DMA_Peripheral_burst
Kojto	122:f9eeca106725	114	@note The burst mode is possible only if the address Increment mode is enabled. */
Kojto	122:f9eeca106725	115	}DMA_InitTypeDef;
Kojto	122:f9eeca106725	116
Kojto	122:f9eeca106725	117
Kojto	122:f9eeca106725	118	/**
Kojto	122:f9eeca106725	119	* @brief HAL DMA State structures definition
Kojto	122:f9eeca106725	120	*/
Kojto	122:f9eeca106725	121	typedef enum
Kojto	122:f9eeca106725	122	{
Kojto	122:f9eeca106725	123	HAL_DMA_STATE_RESET = 0x00U, /!< DMA not yet initialized or disabled /
Kojto	122:f9eeca106725	124	HAL_DMA_STATE_READY = 0x01U, /!< DMA initialized and ready for use /
Kojto	122:f9eeca106725	125	HAL_DMA_STATE_BUSY = 0x02U, /!< DMA process is ongoing /
Kojto	122:f9eeca106725	126	HAL_DMA_STATE_TIMEOUT = 0x03U, /!< DMA timeout state /
Kojto	122:f9eeca106725	127	HAL_DMA_STATE_ERROR = 0x04U, /!< DMA error state /
Kojto	122:f9eeca106725	128	HAL_DMA_STATE_ABORT = 0x05U, /!< DMA Abort state /
Kojto	122:f9eeca106725	129	}HAL_DMA_StateTypeDef;
Kojto	122:f9eeca106725	130
Kojto	122:f9eeca106725	131	/**
Kojto	122:f9eeca106725	132	* @brief HAL DMA Error Code structure definition
Kojto	122:f9eeca106725	133	*/
Kojto	122:f9eeca106725	134	typedef enum
Kojto	122:f9eeca106725	135	{
Kojto	122:f9eeca106725	136	HAL_DMA_FULL_TRANSFER = 0x00U, /!< Full transfer /
Kojto	122:f9eeca106725	137	HAL_DMA_HALF_TRANSFER = 0x01U /!< Half Transfer /
Kojto	122:f9eeca106725	138	}HAL_DMA_LevelCompleteTypeDef;
Kojto	122:f9eeca106725	139
Kojto	122:f9eeca106725	140	/**
Kojto	122:f9eeca106725	141	* @brief HAL DMA Error Code structure definition
Kojto	122:f9eeca106725	142	*/
Kojto	122:f9eeca106725	143	typedef enum
Kojto	122:f9eeca106725	144	{
Kojto	122:f9eeca106725	145	HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /!< Full transfer /
Kojto	122:f9eeca106725	146	HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /!< Half Transfer /
Kojto	122:f9eeca106725	147	HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /!< M1 Full Transfer /
Kojto	122:f9eeca106725	148	HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /!< M1 Half Transfer /
Kojto	122:f9eeca106725	149	HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /!< Error /
Kojto	122:f9eeca106725	150	HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /!< Abort /
Kojto	122:f9eeca106725	151	HAL_DMA_XFER_ALL_CB_ID = 0x06U /!< All /
Kojto	122:f9eeca106725	152	}HAL_DMA_CallbackIDTypeDef;
Kojto	122:f9eeca106725	153
Kojto	122:f9eeca106725	154	/**
Kojto	122:f9eeca106725	155	* @brief DMA handle Structure definition
Kojto	122:f9eeca106725	156	*/
Kojto	122:f9eeca106725	157	typedef struct __DMA_HandleTypeDef
Kojto	122:f9eeca106725	158	{
Kojto	122:f9eeca106725	159	DMA_Stream_TypeDef Instance; /!< Register base address */
Kojto	122:f9eeca106725	160
Kojto	122:f9eeca106725	161	DMA_InitTypeDef Init; /!< DMA communication parameters /
Kojto	122:f9eeca106725	162
Kojto	122:f9eeca106725	163	HAL_LockTypeDef Lock; /!< DMA locking object /
Kojto	122:f9eeca106725	164
Kojto	122:f9eeca106725	165	__IO HAL_DMA_StateTypeDef State; /!< DMA transfer state /
Kojto	122:f9eeca106725	166
Kojto	122:f9eeca106725	167	void Parent; /!< Parent object state */
Kojto	122:f9eeca106725	168
Kojto	122:f9eeca106725	169	void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer complete callback /
Kojto	122:f9eeca106725	170
Kojto	122:f9eeca106725	171	void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA Half transfer complete callback /
Kojto	122:f9eeca106725	172
Kojto	122:f9eeca106725	173	void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer complete Memory1 callback /
Kojto	122:f9eeca106725	174
Kojto	122:f9eeca106725	175	void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer Half complete Memory1 callback /
Kojto	122:f9eeca106725	176
Kojto	122:f9eeca106725	177	void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer error callback /
Kojto	122:f9eeca106725	178
Kojto	122:f9eeca106725	179	void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer Abort callback /
Kojto	122:f9eeca106725	180
Kojto	122:f9eeca106725	181	__IO uint32_t ErrorCode; /!< DMA Error code /
Kojto	122:f9eeca106725	182
Kojto	122:f9eeca106725	183	uint32_t StreamBaseAddress; /!< DMA Stream Base Address /
Kojto	122:f9eeca106725	184
Kojto	122:f9eeca106725	185	uint32_t StreamIndex; /!< DMA Stream Index /
Kojto	122:f9eeca106725	186
Kojto	122:f9eeca106725	187	}DMA_HandleTypeDef;
Kojto	122:f9eeca106725	188
Kojto	122:f9eeca106725	189	/**
Kojto	122:f9eeca106725	190	* @}
Kojto	122:f9eeca106725	191	*/
Kojto	122:f9eeca106725	192
Kojto	122:f9eeca106725	193	/* Exported constants --------------------------------------------------------*/
Kojto	122:f9eeca106725	194
Kojto	122:f9eeca106725	195	/** @defgroup DMA_Exported_Constants DMA Exported Constants
Kojto	122:f9eeca106725	196	* @brief DMA Exported constants
Kojto	122:f9eeca106725	197	* @{
Kojto	122:f9eeca106725	198	*/
Kojto	122:f9eeca106725	199
Kojto	122:f9eeca106725	200	/** @defgroup DMA_Error_Code DMA Error Code
Kojto	122:f9eeca106725	201	* @brief DMA Error Code
Kojto	122:f9eeca106725	202	* @{
Kojto	122:f9eeca106725	203	*/
Kojto	122:f9eeca106725	204	#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /!< No error /
Kojto	122:f9eeca106725	205	#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /!< Transfer error /
Kojto	122:f9eeca106725	206	#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /!< FIFO error /
Kojto	122:f9eeca106725	207	#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /!< Direct Mode error /
Kojto	122:f9eeca106725	208	#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /!< Timeout error /
Kojto	122:f9eeca106725	209	#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /!< Parameter error /
Kojto	122:f9eeca106725	210	#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /!< Abort requested with no Xfer ongoing /
Kojto	122:f9eeca106725	211	#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /!< Not supported mode /
Kojto	122:f9eeca106725	212	/**
Kojto	122:f9eeca106725	213	* @}
Kojto	122:f9eeca106725	214	*/
Kojto	122:f9eeca106725	215
Kojto	122:f9eeca106725	216	/** @defgroup DMA_Channel_selection DMA Channel selection
Kojto	122:f9eeca106725	217	* @brief DMA channel selection
Kojto	122:f9eeca106725	218	* @{
Kojto	122:f9eeca106725	219	*/
Kojto	122:f9eeca106725	220	#define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /!< DMA Channel 0 /
Kojto	122:f9eeca106725	221	#define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /!< DMA Channel 1 /
Kojto	122:f9eeca106725	222	#define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /!< DMA Channel 2 /
Kojto	122:f9eeca106725	223	#define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /!< DMA Channel 3 /
Kojto	122:f9eeca106725	224	#define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /!< DMA Channel 4 /
Kojto	122:f9eeca106725	225	#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /!< DMA Channel 5 /
Kojto	122:f9eeca106725	226	#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /!< DMA Channel 6 /
Kojto	122:f9eeca106725	227	#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /!< DMA Channel 7 /
Kojto	122:f9eeca106725	228	/**
Kojto	122:f9eeca106725	229	* @}
Kojto	122:f9eeca106725	230	*/
Kojto	122:f9eeca106725	231
Kojto	122:f9eeca106725	232	/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
Kojto	122:f9eeca106725	233	* @brief DMA data transfer direction
Kojto	122:f9eeca106725	234	* @{
Kojto	122:f9eeca106725	235	*/
Kojto	122:f9eeca106725	236	#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /!< Peripheral to memory direction /
Kojto	122:f9eeca106725	237	#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /!< Memory to peripheral direction /
Kojto	122:f9eeca106725	238	#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /!< Memory to memory direction /
Kojto	122:f9eeca106725	239	/**
Kojto	122:f9eeca106725	240	* @}
Kojto	122:f9eeca106725	241	*/
Kojto	122:f9eeca106725	242
Kojto	122:f9eeca106725	243	/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
Kojto	122:f9eeca106725	244	* @brief DMA peripheral incremented mode
Kojto	122:f9eeca106725	245	* @{
Kojto	122:f9eeca106725	246	*/
Kojto	122:f9eeca106725	247	#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /!< Peripheral increment mode enable /
Kojto	122:f9eeca106725	248	#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /!< Peripheral increment mode disable /
Kojto	122:f9eeca106725	249	/**
Kojto	122:f9eeca106725	250	* @}
Kojto	122:f9eeca106725	251	*/
Kojto	122:f9eeca106725	252
Kojto	122:f9eeca106725	253	/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
Kojto	122:f9eeca106725	254	* @brief DMA memory incremented mode
Kojto	122:f9eeca106725	255	* @{
Kojto	122:f9eeca106725	256	*/
Kojto	122:f9eeca106725	257	#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /!< Memory increment mode enable /
Kojto	122:f9eeca106725	258	#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /!< Memory increment mode disable /
Kojto	122:f9eeca106725	259	/**
Kojto	122:f9eeca106725	260	* @}
Kojto	122:f9eeca106725	261	*/
Kojto	122:f9eeca106725	262
Kojto	122:f9eeca106725	263	/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
Kojto	122:f9eeca106725	264	* @brief DMA peripheral data size
Kojto	122:f9eeca106725	265	* @{
Kojto	122:f9eeca106725	266	*/
Kojto	122:f9eeca106725	267	#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Peripheral data alignment: Byte /
Kojto	122:f9eeca106725	268	#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /!< Peripheral data alignment: HalfWord /
Kojto	122:f9eeca106725	269	#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /!< Peripheral data alignment: Word /
Kojto	122:f9eeca106725	270	/**
Kojto	122:f9eeca106725	271	* @}
Kojto	122:f9eeca106725	272	*/
Kojto	122:f9eeca106725	273
Kojto	122:f9eeca106725	274	/** @defgroup DMA_Memory_data_size DMA Memory data size
Kojto	122:f9eeca106725	275	* @brief DMA memory data size
Kojto	122:f9eeca106725	276	* @{
Kojto	122:f9eeca106725	277	*/
Kojto	122:f9eeca106725	278	#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Memory data alignment: Byte /
Kojto	122:f9eeca106725	279	#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /!< Memory data alignment: HalfWord /
Kojto	122:f9eeca106725	280	#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /!< Memory data alignment: Word /
Kojto	122:f9eeca106725	281	/**
Kojto	122:f9eeca106725	282	* @}
Kojto	122:f9eeca106725	283	*/
Kojto	122:f9eeca106725	284
Kojto	122:f9eeca106725	285	/** @defgroup DMA_mode DMA mode
Kojto	122:f9eeca106725	286	* @brief DMA mode
Kojto	122:f9eeca106725	287	* @{
Kojto	122:f9eeca106725	288	*/
Kojto	122:f9eeca106725	289	#define DMA_NORMAL ((uint32_t)0x00000000U) /!< Normal mode /
Kojto	122:f9eeca106725	290	#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /!< Circular mode /
Kojto	122:f9eeca106725	291	#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /!< Peripheral flow control mode /
Kojto	122:f9eeca106725	292	/**
Kojto	122:f9eeca106725	293	* @}
Kojto	122:f9eeca106725	294	*/
Kojto	122:f9eeca106725	295
Kojto	122:f9eeca106725	296	/** @defgroup DMA_Priority_level DMA Priority level
Kojto	122:f9eeca106725	297	* @brief DMA priority levels
Kojto	122:f9eeca106725	298	* @{
Kojto	122:f9eeca106725	299	*/
Kojto	122:f9eeca106725	300	#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /!< Priority level: Low /
Kojto	122:f9eeca106725	301	#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /!< Priority level: Medium /
Kojto	122:f9eeca106725	302	#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /!< Priority level: High /
Kojto	122:f9eeca106725	303	#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /!< Priority level: Very High /
Kojto	122:f9eeca106725	304	/**
Kojto	122:f9eeca106725	305	* @}
Kojto	122:f9eeca106725	306	*/
Kojto	122:f9eeca106725	307
Kojto	122:f9eeca106725	308	/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
Kojto	122:f9eeca106725	309	* @brief DMA FIFO direct mode
Kojto	122:f9eeca106725	310	* @{
Kojto	122:f9eeca106725	311	*/
Kojto	122:f9eeca106725	312	#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /!< FIFO mode disable /
Kojto	122:f9eeca106725	313	#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /!< FIFO mode enable /
Kojto	122:f9eeca106725	314	/**
Kojto	122:f9eeca106725	315	* @}
Kojto	122:f9eeca106725	316	*/
Kojto	122:f9eeca106725	317
Kojto	122:f9eeca106725	318	/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
Kojto	122:f9eeca106725	319	* @brief DMA FIFO level
Kojto	122:f9eeca106725	320	* @{
Kojto	122:f9eeca106725	321	*/
Kojto	122:f9eeca106725	322	#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /!< FIFO threshold 1 quart full configuration /
Kojto	122:f9eeca106725	323	#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /!< FIFO threshold half full configuration /
Kojto	122:f9eeca106725	324	#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /!< FIFO threshold 3 quarts full configuration /
Kojto	122:f9eeca106725	325	#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /!< FIFO threshold full configuration /
Kojto	122:f9eeca106725	326	/**
Kojto	122:f9eeca106725	327	* @}
Kojto	122:f9eeca106725	328	*/
Kojto	122:f9eeca106725	329
Kojto	122:f9eeca106725	330	/** @defgroup DMA_Memory_burst DMA Memory burst
Kojto	122:f9eeca106725	331	* @brief DMA memory burst
Kojto	122:f9eeca106725	332	* @{
Kojto	122:f9eeca106725	333	*/
Kojto	122:f9eeca106725	334	#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	335	#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
Kojto	122:f9eeca106725	336	#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
Kojto	122:f9eeca106725	337	#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
Kojto	122:f9eeca106725	338	/**
Kojto	122:f9eeca106725	339	* @}
Kojto	122:f9eeca106725	340	*/
Kojto	122:f9eeca106725	341
Kojto	122:f9eeca106725	342	/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
Kojto	122:f9eeca106725	343	* @brief DMA peripheral burst
Kojto	122:f9eeca106725	344	* @{
Kojto	122:f9eeca106725	345	*/
Kojto	122:f9eeca106725	346	#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	347	#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
Kojto	122:f9eeca106725	348	#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
Kojto	122:f9eeca106725	349	#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
Kojto	122:f9eeca106725	350	/**
Kojto	122:f9eeca106725	351	* @}
Kojto	122:f9eeca106725	352	*/
Kojto	122:f9eeca106725	353
Kojto	122:f9eeca106725	354	/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
Kojto	122:f9eeca106725	355	* @brief DMA interrupts definition
Kojto	122:f9eeca106725	356	* @{
Kojto	122:f9eeca106725	357	*/
Kojto	122:f9eeca106725	358	#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
Kojto	122:f9eeca106725	359	#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
Kojto	122:f9eeca106725	360	#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
Kojto	122:f9eeca106725	361	#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
Kojto	122:f9eeca106725	362	#define DMA_IT_FE ((uint32_t)0x00000080U)
Kojto	122:f9eeca106725	363	/**
Kojto	122:f9eeca106725	364	* @}
Kojto	122:f9eeca106725	365	*/
Kojto	122:f9eeca106725	366
Kojto	122:f9eeca106725	367	/** @defgroup DMA_flag_definitions DMA flag definitions
Kojto	122:f9eeca106725	368	* @brief DMA flag definitions
Kojto	122:f9eeca106725	369	* @{
Kojto	122:f9eeca106725	370	*/
Kojto	122:f9eeca106725	371	#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
Kojto	122:f9eeca106725	372	#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
Kojto	122:f9eeca106725	373	#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
Kojto	122:f9eeca106725	374	#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	375	#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
Kojto	122:f9eeca106725	376	#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
Kojto	122:f9eeca106725	377	#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
Kojto	122:f9eeca106725	378	#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
Kojto	122:f9eeca106725	379	#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
Kojto	122:f9eeca106725	380	#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
Kojto	122:f9eeca106725	381	#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
Kojto	122:f9eeca106725	382	#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
Kojto	122:f9eeca106725	383	#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
Kojto	122:f9eeca106725	384	#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
Kojto	122:f9eeca106725	385	#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
Kojto	122:f9eeca106725	386	#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
Kojto	122:f9eeca106725	387	#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
Kojto	122:f9eeca106725	388	#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
Kojto	122:f9eeca106725	389	#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
Kojto	122:f9eeca106725	390	#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
Kojto	122:f9eeca106725	391	/**
Kojto	122:f9eeca106725	392	* @}
Kojto	122:f9eeca106725	393	*/
Kojto	122:f9eeca106725	394
Kojto	122:f9eeca106725	395	/**
Kojto	122:f9eeca106725	396	* @}
Kojto	122:f9eeca106725	397	*/
Kojto	122:f9eeca106725	398
Kojto	122:f9eeca106725	399	/* Exported macro ------------------------------------------------------------*/
Kojto	122:f9eeca106725	400
Kojto	122:f9eeca106725	401	/** @brief Reset DMA handle state
Kojto	122:f9eeca106725	402	* @param __HANDLE__: specifies the DMA handle.
Kojto	122:f9eeca106725	403	* @retval None
Kojto	122:f9eeca106725	404	*/
Kojto	122:f9eeca106725	405	#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Kojto	122:f9eeca106725	406
Kojto	122:f9eeca106725	407	/**
Kojto	122:f9eeca106725	408	* @brief Return the current DMA Stream FIFO filled level.
Kojto	122:f9eeca106725	409	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	410	* @retval The FIFO filling state.
Kojto	122:f9eeca106725	411	* - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
Kojto	122:f9eeca106725	412	* and not empty.
Kojto	122:f9eeca106725	413	* - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
Kojto	122:f9eeca106725	414	* - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
Kojto	122:f9eeca106725	415	* - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
Kojto	122:f9eeca106725	416	* - DMA_FIFOStatus_Empty: when FIFO is empty
Kojto	122:f9eeca106725	417	* - DMA_FIFOStatus_Full: when FIFO is full
Kojto	122:f9eeca106725	418	*/
Kojto	122:f9eeca106725	419	#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
Kojto	122:f9eeca106725	420
Kojto	122:f9eeca106725	421	/**
Kojto	122:f9eeca106725	422	* @brief Enable the specified DMA Stream.
Kojto	122:f9eeca106725	423	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	424	* @retval None
Kojto	122:f9eeca106725	425	*/
Kojto	122:f9eeca106725	426	#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= DMA_SxCR_EN)
Kojto	122:f9eeca106725	427
Kojto	122:f9eeca106725	428	/**
Kojto	122:f9eeca106725	429	* @brief Disable the specified DMA Stream.
Kojto	122:f9eeca106725	430	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	431	* @retval None
Kojto	122:f9eeca106725	432	*/
Kojto	122:f9eeca106725	433	#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
Kojto	122:f9eeca106725	434
Kojto	122:f9eeca106725	435	/* Interrupt & Flag management */
Kojto	122:f9eeca106725	436
Kojto	122:f9eeca106725	437	/**
Kojto	122:f9eeca106725	438	* @brief Return the current DMA Stream transfer complete flag.
Kojto	122:f9eeca106725	439	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	440	* @retval The specified transfer complete flag index.
Kojto	122:f9eeca106725	441	*/
Kojto	122:f9eeca106725	442	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
Kojto	122:f9eeca106725	443	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
Kojto	122:f9eeca106725	444	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
Kojto	122:f9eeca106725	445	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
Kojto	122:f9eeca106725	446	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
Kojto	122:f9eeca106725	447	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
Kojto	122:f9eeca106725	448	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
Kojto	122:f9eeca106725	449	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
Kojto	122:f9eeca106725	450	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
Kojto	122:f9eeca106725	451	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
Kojto	122:f9eeca106725	452	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
Kojto	122:f9eeca106725	453	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
Kojto	122:f9eeca106725	454	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
Kojto	122:f9eeca106725	455	DMA_FLAG_TCIF3_7)
Kojto	122:f9eeca106725	456
Kojto	122:f9eeca106725	457	/**
Kojto	122:f9eeca106725	458	* @brief Return the current DMA Stream half transfer complete flag.
Kojto	122:f9eeca106725	459	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	460	* @retval The specified half transfer complete flag index.
Kojto	122:f9eeca106725	461	*/
Kojto	122:f9eeca106725	462	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
Kojto	122:f9eeca106725	463	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
Kojto	122:f9eeca106725	464	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
Kojto	122:f9eeca106725	465	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
Kojto	122:f9eeca106725	466	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
Kojto	122:f9eeca106725	467	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
Kojto	122:f9eeca106725	468	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
Kojto	122:f9eeca106725	469	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
Kojto	122:f9eeca106725	470	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
Kojto	122:f9eeca106725	471	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
Kojto	122:f9eeca106725	472	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
Kojto	122:f9eeca106725	473	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
Kojto	122:f9eeca106725	474	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
Kojto	122:f9eeca106725	475	DMA_FLAG_HTIF3_7)
Kojto	122:f9eeca106725	476
Kojto	122:f9eeca106725	477	/**
Kojto	122:f9eeca106725	478	* @brief Return the current DMA Stream transfer error flag.
Kojto	122:f9eeca106725	479	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	480	* @retval The specified transfer error flag index.
Kojto	122:f9eeca106725	481	*/
Kojto	122:f9eeca106725	482	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
Kojto	122:f9eeca106725	483	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
Kojto	122:f9eeca106725	484	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
Kojto	122:f9eeca106725	485	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
Kojto	122:f9eeca106725	486	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
Kojto	122:f9eeca106725	487	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
Kojto	122:f9eeca106725	488	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
Kojto	122:f9eeca106725	489	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
Kojto	122:f9eeca106725	490	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
Kojto	122:f9eeca106725	491	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
Kojto	122:f9eeca106725	492	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
Kojto	122:f9eeca106725	493	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
Kojto	122:f9eeca106725	494	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
Kojto	122:f9eeca106725	495	DMA_FLAG_TEIF3_7)
Kojto	122:f9eeca106725	496
Kojto	122:f9eeca106725	497	/**
Kojto	122:f9eeca106725	498	* @brief Return the current DMA Stream FIFO error flag.
Kojto	122:f9eeca106725	499	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	500	* @retval The specified FIFO error flag index.
Kojto	122:f9eeca106725	501	*/
Kojto	122:f9eeca106725	502	#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
Kojto	122:f9eeca106725	503	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
Kojto	122:f9eeca106725	504	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
Kojto	122:f9eeca106725	505	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
Kojto	122:f9eeca106725	506	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
Kojto	122:f9eeca106725	507	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
Kojto	122:f9eeca106725	508	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
Kojto	122:f9eeca106725	509	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
Kojto	122:f9eeca106725	510	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
Kojto	122:f9eeca106725	511	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
Kojto	122:f9eeca106725	512	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
Kojto	122:f9eeca106725	513	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
Kojto	122:f9eeca106725	514	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
Kojto	122:f9eeca106725	515	DMA_FLAG_FEIF3_7)
Kojto	122:f9eeca106725	516
Kojto	122:f9eeca106725	517	/**
Kojto	122:f9eeca106725	518	* @brief Return the current DMA Stream direct mode error flag.
Kojto	122:f9eeca106725	519	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	520	* @retval The specified direct mode error flag index.
Kojto	122:f9eeca106725	521	*/
Kojto	122:f9eeca106725	522	#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
Kojto	122:f9eeca106725	523	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
Kojto	122:f9eeca106725	524	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
Kojto	122:f9eeca106725	525	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
Kojto	122:f9eeca106725	526	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
Kojto	122:f9eeca106725	527	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
Kojto	122:f9eeca106725	528	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
Kojto	122:f9eeca106725	529	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
Kojto	122:f9eeca106725	530	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
Kojto	122:f9eeca106725	531	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
Kojto	122:f9eeca106725	532	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
Kojto	122:f9eeca106725	533	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
Kojto	122:f9eeca106725	534	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
Kojto	122:f9eeca106725	535	DMA_FLAG_DMEIF3_7)
Kojto	122:f9eeca106725	536
Kojto	122:f9eeca106725	537	/**
Kojto	122:f9eeca106725	538	* @brief Get the DMA Stream pending flags.
Kojto	122:f9eeca106725	539	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	540	* @param __FLAG__: Get the specified flag.
Kojto	122:f9eeca106725	541	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	542	* @arg DMA_FLAG_TCIFx: Transfer complete flag.
Kojto	122:f9eeca106725	543	* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
Kojto	122:f9eeca106725	544	* @arg DMA_FLAG_TEIFx: Transfer error flag.
Kojto	122:f9eeca106725	545	* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
Kojto	122:f9eeca106725	546	* @arg DMA_FLAG_FEIFx: FIFO error flag.
Kojto	122:f9eeca106725	547	* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Kojto	122:f9eeca106725	548	* @retval The state of FLAG (SET or RESET).
Kojto	122:f9eeca106725	549	*/
Kojto	122:f9eeca106725	550	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
Kojto	122:f9eeca106725	551	(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
Kojto	122:f9eeca106725	552	((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
Kojto	122:f9eeca106725	553	((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
Kojto	122:f9eeca106725	554
Kojto	122:f9eeca106725	555	/**
Kojto	122:f9eeca106725	556	* @brief Clear the DMA Stream pending flags.
Kojto	122:f9eeca106725	557	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	558	* @param __FLAG__: specifies the flag to clear.
Kojto	122:f9eeca106725	559	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	560	* @arg DMA_FLAG_TCIFx: Transfer complete flag.
Kojto	122:f9eeca106725	561	* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
Kojto	122:f9eeca106725	562	* @arg DMA_FLAG_TEIFx: Transfer error flag.
Kojto	122:f9eeca106725	563	* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
Kojto	122:f9eeca106725	564	* @arg DMA_FLAG_FEIFx: FIFO error flag.
Kojto	122:f9eeca106725	565	* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Kojto	122:f9eeca106725	566	* @retval None
Kojto	122:f9eeca106725	567	*/
Kojto	122:f9eeca106725	568	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
Kojto	122:f9eeca106725	569	(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
Kojto	122:f9eeca106725	570	((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
Kojto	122:f9eeca106725	571	((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
Kojto	122:f9eeca106725	572
Kojto	122:f9eeca106725	573	/**
Kojto	122:f9eeca106725	574	* @brief Enable the specified DMA Stream interrupts.
Kojto	122:f9eeca106725	575	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	576	* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto	122:f9eeca106725	577	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	578	* @arg DMA_IT_TC: Transfer complete interrupt mask.
Kojto	122:f9eeca106725	579	* @arg DMA_IT_HT: Half transfer complete interrupt mask.
Kojto	122:f9eeca106725	580	* @arg DMA_IT_TE: Transfer error interrupt mask.
Kojto	122:f9eeca106725	581	* @arg DMA_IT_FE: FIFO error interrupt mask.
Kojto	122:f9eeca106725	582	* @arg DMA_IT_DME: Direct mode error interrupt.
Kojto	122:f9eeca106725	583	* @retval None
Kojto	122:f9eeca106725	584	*/
Kojto	122:f9eeca106725	585	#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
Kojto	122:f9eeca106725	586	((__HANDLE__)->Instance->CR \|= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR \|= (__INTERRUPT__)))
Kojto	122:f9eeca106725	587
Kojto	122:f9eeca106725	588	/**
Kojto	122:f9eeca106725	589	* @brief Disable the specified DMA Stream interrupts.
Kojto	122:f9eeca106725	590	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	591	* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto	122:f9eeca106725	592	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	593	* @arg DMA_IT_TC: Transfer complete interrupt mask.
Kojto	122:f9eeca106725	594	* @arg DMA_IT_HT: Half transfer complete interrupt mask.
Kojto	122:f9eeca106725	595	* @arg DMA_IT_TE: Transfer error interrupt mask.
Kojto	122:f9eeca106725	596	* @arg DMA_IT_FE: FIFO error interrupt mask.
Kojto	122:f9eeca106725	597	* @arg DMA_IT_DME: Direct mode error interrupt.
Kojto	122:f9eeca106725	598	* @retval None
Kojto	122:f9eeca106725	599	*/
Kojto	122:f9eeca106725	600	#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
Kojto	122:f9eeca106725	601	((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
Kojto	122:f9eeca106725	602
Kojto	122:f9eeca106725	603	/**
Kojto	122:f9eeca106725	604	* @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
Kojto	122:f9eeca106725	605	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	606	* @param __INTERRUPT__: specifies the DMA interrupt source to check.
Kojto	122:f9eeca106725	607	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	608	* @arg DMA_IT_TC: Transfer complete interrupt mask.
Kojto	122:f9eeca106725	609	* @arg DMA_IT_HT: Half transfer complete interrupt mask.
Kojto	122:f9eeca106725	610	* @arg DMA_IT_TE: Transfer error interrupt mask.
Kojto	122:f9eeca106725	611	* @arg DMA_IT_FE: FIFO error interrupt mask.
Kojto	122:f9eeca106725	612	* @arg DMA_IT_DME: Direct mode error interrupt.
Kojto	122:f9eeca106725	613	* @retval The state of DMA_IT.
Kojto	122:f9eeca106725	614	*/
Kojto	122:f9eeca106725	615	#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
Kojto	122:f9eeca106725	616	((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
Kojto	122:f9eeca106725	617	((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
Kojto	122:f9eeca106725	618
Kojto	122:f9eeca106725	619	/**
Kojto	122:f9eeca106725	620	* @brief Writes the number of data units to be transferred on the DMA Stream.
Kojto	122:f9eeca106725	621	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	622	* @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
Kojto	122:f9eeca106725	623	* Number of data items depends only on the Peripheral data format.
Kojto	122:f9eeca106725	624	*
Kojto	122:f9eeca106725	625	* @note If Peripheral data format is Bytes: number of data units is equal
Kojto	122:f9eeca106725	626	* to total number of bytes to be transferred.
Kojto	122:f9eeca106725	627	*
Kojto	122:f9eeca106725	628	* @note If Peripheral data format is Half-Word: number of data units is
Kojto	122:f9eeca106725	629	* equal to total number of bytes to be transferred / 2.
Kojto	122:f9eeca106725	630	*
Kojto	122:f9eeca106725	631	* @note If Peripheral data format is Word: number of data units is equal
Kojto	122:f9eeca106725	632	* to total number of bytes to be transferred / 4.
Kojto	122:f9eeca106725	633	*
Kojto	122:f9eeca106725	634	* @retval The number of remaining data units in the current DMAy Streamx transfer.
Kojto	122:f9eeca106725	635	*/
Kojto	122:f9eeca106725	636	#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
Kojto	122:f9eeca106725	637
Kojto	122:f9eeca106725	638	/**
Kojto	122:f9eeca106725	639	* @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
Kojto	122:f9eeca106725	640	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	641	*
Kojto	122:f9eeca106725	642	* @retval The number of remaining data units in the current DMA Stream transfer.
Kojto	122:f9eeca106725	643	*/
Kojto	122:f9eeca106725	644	#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
Kojto	122:f9eeca106725	645
Kojto	122:f9eeca106725	646
Kojto	122:f9eeca106725	647	/* Include DMA HAL Extension module */
Kojto	122:f9eeca106725	648	#include "stm32f4xx_hal_dma_ex.h"
Kojto	122:f9eeca106725	649
Kojto	122:f9eeca106725	650	/* Exported functions --------------------------------------------------------*/
Kojto	122:f9eeca106725	651
Kojto	122:f9eeca106725	652	/** @defgroup DMA_Exported_Functions DMA Exported Functions
Kojto	122:f9eeca106725	653	* @brief DMA Exported functions
Kojto	122:f9eeca106725	654	* @{
Kojto	122:f9eeca106725	655	*/
Kojto	122:f9eeca106725	656
Kojto	122:f9eeca106725	657	/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto	122:f9eeca106725	658	* @brief Initialization and de-initialization functions
Kojto	122:f9eeca106725	659	* @{
Kojto	122:f9eeca106725	660	*/
Kojto	122:f9eeca106725	661	HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
Kojto	122:f9eeca106725	662	HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
Kojto	122:f9eeca106725	663	/**
Kojto	122:f9eeca106725	664	* @}
Kojto	122:f9eeca106725	665	*/
Kojto	122:f9eeca106725	666
Kojto	122:f9eeca106725	667	/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
Kojto	122:f9eeca106725	668	* @brief I/O operation functions
Kojto	122:f9eeca106725	669	* @{
Kojto	122:f9eeca106725	670	*/
Kojto	122:f9eeca106725	671	HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto	122:f9eeca106725	672	HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto	122:f9eeca106725	673	HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
Kojto	122:f9eeca106725	674	HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
Kojto	122:f9eeca106725	675	HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
Kojto	122:f9eeca106725	676	void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto	122:f9eeca106725	677	HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
Kojto	122:f9eeca106725	678	HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void ( pCallback)(DMA_HandleTypeDef *_hdma));
Kojto	122:f9eeca106725	679	HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
Kojto	122:f9eeca106725	680
Kojto	122:f9eeca106725	681	/**
Kojto	122:f9eeca106725	682	* @}
Kojto	122:f9eeca106725	683	*/
Kojto	122:f9eeca106725	684
Kojto	122:f9eeca106725	685	/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
Kojto	122:f9eeca106725	686	* @brief Peripheral State functions
Kojto	122:f9eeca106725	687	* @{
Kojto	122:f9eeca106725	688	*/
Kojto	122:f9eeca106725	689	HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
Kojto	122:f9eeca106725	690	uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
Kojto	122:f9eeca106725	691	/**
Kojto	122:f9eeca106725	692	* @}
Kojto	122:f9eeca106725	693	*/
Kojto	122:f9eeca106725	694	/**
Kojto	122:f9eeca106725	695	* @}
Kojto	122:f9eeca106725	696	*/
Kojto	122:f9eeca106725	697	/* Private Constants -------------------------------------------------------------*/
Kojto	122:f9eeca106725	698	/** @defgroup DMA_Private_Constants DMA Private Constants
Kojto	122:f9eeca106725	699	* @brief DMA private defines and constants
Kojto	122:f9eeca106725	700	* @{
Kojto	122:f9eeca106725	701	*/
Kojto	122:f9eeca106725	702	/**
Kojto	122:f9eeca106725	703	* @}
Kojto	122:f9eeca106725	704	*/
Kojto	122:f9eeca106725	705
Kojto	122:f9eeca106725	706	/* Private macros ------------------------------------------------------------*/
Kojto	122:f9eeca106725	707	/** @defgroup DMA_Private_Macros DMA Private Macros
Kojto	122:f9eeca106725	708	* @brief DMA private macros
Kojto	122:f9eeca106725	709	* @{
Kojto	122:f9eeca106725	710	*/
Kojto	122:f9eeca106725	711	#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) \|\| \
Kojto	122:f9eeca106725	712	((CHANNEL) == DMA_CHANNEL_1) \|\| \
Kojto	122:f9eeca106725	713	((CHANNEL) == DMA_CHANNEL_2) \|\| \
Kojto	122:f9eeca106725	714	((CHANNEL) == DMA_CHANNEL_3) \|\| \
Kojto	122:f9eeca106725	715	((CHANNEL) == DMA_CHANNEL_4) \|\| \
Kojto	122:f9eeca106725	716	((CHANNEL) == DMA_CHANNEL_5) \|\| \
Kojto	122:f9eeca106725	717	((CHANNEL) == DMA_CHANNEL_6) \|\| \
Kojto	122:f9eeca106725	718	((CHANNEL) == DMA_CHANNEL_7))
Kojto	122:f9eeca106725	719
Kojto	122:f9eeca106725	720	#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) \|\| \
Kojto	122:f9eeca106725	721	((DIRECTION) == DMA_MEMORY_TO_PERIPH) \|\| \
Kojto	122:f9eeca106725	722	((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto	122:f9eeca106725	723
Kojto	122:f9eeca106725	724	#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
Kojto	122:f9eeca106725	725
Kojto	122:f9eeca106725	726	#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) \|\| \
Kojto	122:f9eeca106725	727	((STATE) == DMA_PINC_DISABLE))
Kojto	122:f9eeca106725	728
Kojto	122:f9eeca106725	729	#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) \|\| \
Kojto	122:f9eeca106725	730	((STATE) == DMA_MINC_DISABLE))
Kojto	122:f9eeca106725	731
Kojto	122:f9eeca106725	732	#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) \|\| \
Kojto	122:f9eeca106725	733	((SIZE) == DMA_PDATAALIGN_HALFWORD) \|\| \
Kojto	122:f9eeca106725	734	((SIZE) == DMA_PDATAALIGN_WORD))
Kojto	122:f9eeca106725	735
Kojto	122:f9eeca106725	736	#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) \|\| \
Kojto	122:f9eeca106725	737	((SIZE) == DMA_MDATAALIGN_HALFWORD) \|\| \
Kojto	122:f9eeca106725	738	((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto	122:f9eeca106725	739
Kojto	122:f9eeca106725	740	#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) \|\| \
Kojto	122:f9eeca106725	741	((MODE) == DMA_CIRCULAR) \|\| \
Kojto	122:f9eeca106725	742	((MODE) == DMA_PFCTRL))
Kojto	122:f9eeca106725	743
Kojto	122:f9eeca106725	744	#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) \|\| \
Kojto	122:f9eeca106725	745	((PRIORITY) == DMA_PRIORITY_MEDIUM) \|\| \
Kojto	122:f9eeca106725	746	((PRIORITY) == DMA_PRIORITY_HIGH) \|\| \
Kojto	122:f9eeca106725	747	((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto	122:f9eeca106725	748
Kojto	122:f9eeca106725	749	#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) \|\| \
Kojto	122:f9eeca106725	750	((STATE) == DMA_FIFOMODE_ENABLE))
Kojto	122:f9eeca106725	751
Kojto	122:f9eeca106725	752	#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) \|\| \
Kojto	122:f9eeca106725	753	((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) \|\| \
Kojto	122:f9eeca106725	754	((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) \|\| \
Kojto	122:f9eeca106725	755	((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
Kojto	122:f9eeca106725	756
Kojto	122:f9eeca106725	757	#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) \|\| \
Kojto	122:f9eeca106725	758	((BURST) == DMA_MBURST_INC4) \|\| \
Kojto	122:f9eeca106725	759	((BURST) == DMA_MBURST_INC8) \|\| \
Kojto	122:f9eeca106725	760	((BURST) == DMA_MBURST_INC16))
Kojto	122:f9eeca106725	761
Kojto	122:f9eeca106725	762	#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) \|\| \
Kojto	122:f9eeca106725	763	((BURST) == DMA_PBURST_INC4) \|\| \
Kojto	122:f9eeca106725	764	((BURST) == DMA_PBURST_INC8) \|\| \
Kojto	122:f9eeca106725	765	((BURST) == DMA_PBURST_INC16))
Kojto	122:f9eeca106725	766	/**
Kojto	122:f9eeca106725	767	* @}
Kojto	122:f9eeca106725	768	*/
Kojto	122:f9eeca106725	769
Kojto	122:f9eeca106725	770	/* Private functions ---------------------------------------------------------*/
Kojto	122:f9eeca106725	771	/** @defgroup DMA_Private_Functions DMA Private Functions
Kojto	122:f9eeca106725	772	* @brief DMA private functions
Kojto	122:f9eeca106725	773	* @{
Kojto	122:f9eeca106725	774	*/
Kojto	122:f9eeca106725	775	/**
Kojto	122:f9eeca106725	776	* @}
Kojto	122:f9eeca106725	777	*/
Kojto	122:f9eeca106725	778
Kojto	122:f9eeca106725	779	/**
Kojto	122:f9eeca106725	780	* @}
Kojto	122:f9eeca106725	781	*/
Kojto	122:f9eeca106725	782
Kojto	122:f9eeca106725	783	/**
Kojto	122:f9eeca106725	784	* @}
Kojto	122:f9eeca106725	785	*/
Kojto	122:f9eeca106725	786
Kojto	122:f9eeca106725	787	#ifdef __cplusplus
Kojto	122:f9eeca106725	788	}
Kojto	122:f9eeca106725	789	#endif
Kojto	122:f9eeca106725	790
Kojto	122:f9eeca106725	791	#endif /* __STM32F4xx_HAL_DMA_H */
Kojto	122:f9eeca106725	792
Kojto	122:f9eeca106725	793	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/