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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:: <>
Date:: Wed Apr 12 16:07:08 2017 +0100
Revision:: 140:97feb9bacc10
Parent:: 128:9bcdf88f62b0
Child:: 145:64910690c574

Release 140 of the mbed library

Ports for Upcoming Targets

3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992

Fixes and Changes

3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/**
Kojto	122:f9eeca106725	2	******************************************************************************
Kojto	122:f9eeca106725	3	* @file stm32l4xx_ll_rcc.h
Kojto	122:f9eeca106725	4	* @author MCD Application Team
Kojto	122:f9eeca106725	5	* @version V1.5.1
Kojto	122:f9eeca106725	6	* @date 31-May-2016
Kojto	122:f9eeca106725	7	* @brief Header file of RCC LL module.
Kojto	122:f9eeca106725	8	******************************************************************************
Kojto	122:f9eeca106725	9	* @attention
Kojto	122:f9eeca106725	10	*
Kojto	122:f9eeca106725	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto	122:f9eeca106725	12	*
Kojto	122:f9eeca106725	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	122:f9eeca106725	14	* are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	122:f9eeca106725	16	* this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	122:f9eeca106725	18	* this list of conditions and the following disclaimer in the documentation
Kojto	122:f9eeca106725	19	* and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	122:f9eeca106725	21	* may be used to endorse or promote products derived from this software
Kojto	122:f9eeca106725	22	* without specific prior written permission.
Kojto	122:f9eeca106725	23	*
Kojto	122:f9eeca106725	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	122:f9eeca106725	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	122:f9eeca106725	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	122:f9eeca106725	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	122:f9eeca106725	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	122:f9eeca106725	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	122:f9eeca106725	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	122:f9eeca106725	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	34	*
Kojto	122:f9eeca106725	35	******************************************************************************
Kojto	122:f9eeca106725	36	*/
Kojto	122:f9eeca106725	37
Kojto	122:f9eeca106725	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	122:f9eeca106725	39	#ifndef __STM32L4xx_LL_RCC_H
Kojto	122:f9eeca106725	40	#define __STM32L4xx_LL_RCC_H
Kojto	122:f9eeca106725	41
Kojto	122:f9eeca106725	42	#ifdef __cplusplus
Kojto	122:f9eeca106725	43	extern "C" {
Kojto	122:f9eeca106725	44	#endif
Kojto	122:f9eeca106725	45
Kojto	122:f9eeca106725	46	/* Includes ------------------------------------------------------------------*/
Kojto	122:f9eeca106725	47	#include "stm32l4xx.h"
Kojto	122:f9eeca106725	48
Kojto	122:f9eeca106725	49	/** @addtogroup STM32L4xx_LL_Driver
Kojto	122:f9eeca106725	50	* @{
Kojto	122:f9eeca106725	51	*/
Kojto	122:f9eeca106725	52
Kojto	122:f9eeca106725	53	#if defined(RCC)
Kojto	122:f9eeca106725	54
Kojto	122:f9eeca106725	55	/** @defgroup RCC_LL RCC
Kojto	122:f9eeca106725	56	* @{
Kojto	122:f9eeca106725	57	*/
Kojto	122:f9eeca106725	58
Kojto	122:f9eeca106725	59	/* Private types -------------------------------------------------------------*/
Kojto	122:f9eeca106725	60	/* Private variables ---------------------------------------------------------*/
Kojto	122:f9eeca106725	61	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
Kojto	122:f9eeca106725	62	* @{
Kojto	122:f9eeca106725	63	*/
Kojto	122:f9eeca106725	64
Kojto	122:f9eeca106725	65	static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
Kojto	122:f9eeca106725	66
Kojto	122:f9eeca106725	67	/**
Kojto	122:f9eeca106725	68	* @}
Kojto	122:f9eeca106725	69	*/
Kojto	122:f9eeca106725	70
Kojto	122:f9eeca106725	71	/* Private constants ---------------------------------------------------------*/
Kojto	122:f9eeca106725	72	/** @defgroup RCC_LL_Private_Constants RCC Private Constants
Kojto	122:f9eeca106725	73	* @{
Kojto	122:f9eeca106725	74	*/
Kojto	122:f9eeca106725	75	/* Defines used for the bit position in the register and perform offsets*/
Kojto	122:f9eeca106725	76	#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)
Kojto	122:f9eeca106725	77	#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)
Kojto	122:f9eeca106725	78	#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)
Kojto	122:f9eeca106725	79	#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_HSICAL)
Kojto	122:f9eeca106725	80	#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_HSITRIM)
Kojto	122:f9eeca106725	81	#define RCC_POSITION_MSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL)
Kojto	122:f9eeca106725	82	#define RCC_POSITION_MSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM)
Kojto	122:f9eeca106725	83	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	84	#define RCC_POSITION_HSI48CAL (uint32_t)POSITION_VAL(RCC_CRRCR_HSI48CAL)
Kojto	122:f9eeca106725	85	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	86	#define RCC_POSITION_PLLN (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLN)
Kojto	122:f9eeca106725	87	#define RCC_POSITION_PLLM (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLM)
Kojto	122:f9eeca106725	88	#define RCC_POSITION_PLLR (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLR)
Kojto	122:f9eeca106725	89	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	90	#define RCC_POSITION_PLLP (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLPDIV)
Kojto	122:f9eeca106725	91	#else
Kojto	122:f9eeca106725	92	#define RCC_POSITION_PLLP (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLP)
Kojto	122:f9eeca106725	93	#endif /* RCC_PLLP_DIV_2_31_SUPPOR T*/
Kojto	122:f9eeca106725	94	#define RCC_POSITION_PLLQ (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLQ)
Kojto	122:f9eeca106725	95	#define RCC_POSITION_PLLSAI1N (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)
Kojto	122:f9eeca106725	96	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	97	#define RCC_POSITION_PLLSAI1P (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)
Kojto	122:f9eeca106725	98	#else
Kojto	122:f9eeca106725	99	#define RCC_POSITION_PLLSAI1P (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)
Kojto	122:f9eeca106725	100	#endif /RCC_PLLSAI1P_DIV_2_31_SUPPORT/
Kojto	122:f9eeca106725	101	#define RCC_POSITION_PLLSAI1Q (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)
Kojto	122:f9eeca106725	102	#define RCC_POSITION_PLLSAI1R (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)
Kojto	122:f9eeca106725	103	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	104	#define RCC_POSITION_PLLSAI2N (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)
Kojto	122:f9eeca106725	105	#define RCC_POSITION_PLLSAI2P (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)
Kojto	122:f9eeca106725	106	#define RCC_POSITION_PLLSAI2R (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)
Kojto	122:f9eeca106725	107	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	108
Kojto	122:f9eeca106725	109	/**
Kojto	122:f9eeca106725	110	* @}
Kojto	122:f9eeca106725	111	*/
Kojto	122:f9eeca106725	112
Kojto	122:f9eeca106725	113	/* Private macros ------------------------------------------------------------*/
Kojto	122:f9eeca106725	114	#if defined(USE_FULL_LL_DRIVER)
Kojto	122:f9eeca106725	115	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
Kojto	122:f9eeca106725	116	* @{
Kojto	122:f9eeca106725	117	*/
Kojto	122:f9eeca106725	118	/**
Kojto	122:f9eeca106725	119	* @}
Kojto	122:f9eeca106725	120	*/
Kojto	122:f9eeca106725	121	#endif /USE_FULL_LL_DRIVER/
Kojto	122:f9eeca106725	122	/* Exported types ------------------------------------------------------------*/
Kojto	122:f9eeca106725	123	#if defined(USE_FULL_LL_DRIVER)
Kojto	122:f9eeca106725	124	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
Kojto	122:f9eeca106725	125	* @{
Kojto	122:f9eeca106725	126	*/
Kojto	122:f9eeca106725	127
Kojto	122:f9eeca106725	128	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
Kojto	122:f9eeca106725	129	* @{
Kojto	122:f9eeca106725	130	*/
Kojto	122:f9eeca106725	131
Kojto	122:f9eeca106725	132	/**
Kojto	122:f9eeca106725	133	* @brief RCC Clocks Frequency Structure
Kojto	122:f9eeca106725	134	*/
Kojto	122:f9eeca106725	135	typedef struct
Kojto	122:f9eeca106725	136	{
Kojto	122:f9eeca106725	137	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
Kojto	122:f9eeca106725	138	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
Kojto	122:f9eeca106725	139	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
Kojto	122:f9eeca106725	140	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
Kojto	122:f9eeca106725	141	} LL_RCC_ClocksTypeDef;
Kojto	122:f9eeca106725	142
Kojto	122:f9eeca106725	143	/**
Kojto	122:f9eeca106725	144	* @}
Kojto	122:f9eeca106725	145	*/
Kojto	122:f9eeca106725	146
Kojto	122:f9eeca106725	147	/**
Kojto	122:f9eeca106725	148	* @}
Kojto	122:f9eeca106725	149	*/
Kojto	122:f9eeca106725	150	#endif /* USE_FULL_LL_DRIVER */
Kojto	122:f9eeca106725	151
Kojto	122:f9eeca106725	152	/* Exported constants --------------------------------------------------------*/
Kojto	122:f9eeca106725	153	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
Kojto	122:f9eeca106725	154	* @{
Kojto	122:f9eeca106725	155	*/
Kojto	122:f9eeca106725	156
Kojto	122:f9eeca106725	157	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
Kojto	122:f9eeca106725	158	* @brief Defines used to adapt values of different oscillators
Kojto	122:f9eeca106725	159	* @note These values could be modified in the user environment according to
Kojto	122:f9eeca106725	160	* HW set-up.
Kojto	122:f9eeca106725	161	* @{
Kojto	122:f9eeca106725	162	*/
Kojto	122:f9eeca106725	163	#if !defined (HSE_VALUE)
Kojto	122:f9eeca106725	164	#define HSE_VALUE ((uint32_t)8000000) /!< Value of the HSE oscillator in Hz /
Kojto	122:f9eeca106725	165	#endif /* HSE_VALUE */
Kojto	122:f9eeca106725	166
Kojto	122:f9eeca106725	167	#if !defined (HSI_VALUE)
Kojto	122:f9eeca106725	168	#define HSI_VALUE ((uint32_t)16000000) /!< Value of the HSI oscillator in Hz /
Kojto	122:f9eeca106725	169	#endif /* HSI_VALUE */
Kojto	122:f9eeca106725	170
Kojto	122:f9eeca106725	171	#if !defined (LSE_VALUE)
Kojto	122:f9eeca106725	172	#define LSE_VALUE ((uint32_t)32768) /!< Value of the LSE oscillator in Hz /
Kojto	122:f9eeca106725	173	#endif /* LSE_VALUE */
Kojto	122:f9eeca106725	174
Kojto	122:f9eeca106725	175	#if !defined (LSI_VALUE)
Kojto	122:f9eeca106725	176	#define LSI_VALUE ((uint32_t)32000) /!< Value of the LSI oscillator in Hz /
Kojto	122:f9eeca106725	177	#endif /* LSI_VALUE */
Kojto	122:f9eeca106725	178	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	179
Kojto	122:f9eeca106725	180	#if !defined (HSI48_VALUE)
Kojto	122:f9eeca106725	181	#define HSI48_VALUE ((uint32_t)48000000) /!< Value of the HSI48 oscillator in Hz /
Kojto	122:f9eeca106725	182	#endif /* HSI48_VALUE */
Kojto	122:f9eeca106725	183	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	184	/**
Kojto	122:f9eeca106725	185	* @}
Kojto	122:f9eeca106725	186	*/
Kojto	122:f9eeca106725	187
Kojto	122:f9eeca106725	188	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
Kojto	122:f9eeca106725	189	* @brief Flags defines which can be used with LL_RCC_WriteReg function
Kojto	122:f9eeca106725	190	* @{
Kojto	122:f9eeca106725	191	*/
Kojto	122:f9eeca106725	192	#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /!< LSI Ready Interrupt Clear /
Kojto	122:f9eeca106725	193	#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /!< LSE Ready Interrupt Clear /
Kojto	122:f9eeca106725	194	#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /!< MSI Ready Interrupt Clear /
Kojto	122:f9eeca106725	195	#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /!< HSI Ready Interrupt Clear /
Kojto	122:f9eeca106725	196	#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /!< HSE Ready Interrupt Clear /
Kojto	122:f9eeca106725	197	#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /!< PLL Ready Interrupt Clear /
Kojto	122:f9eeca106725	198	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	199	#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /!< HSI48 Ready Interrupt Clear /
Kojto	122:f9eeca106725	200	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	201	#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /!< PLLSAI1 Ready Interrupt Clear /
Kojto	122:f9eeca106725	202	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	203	#define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /!< PLLSAI2 Ready Interrupt Clear /
Kojto	122:f9eeca106725	204	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	205	#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /!< LSE Clock Security System Interrupt Clear /
Kojto	122:f9eeca106725	206	#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /!< Clock Security System Interrupt Clear /
Kojto	122:f9eeca106725	207	/**
Kojto	122:f9eeca106725	208	* @}
Kojto	122:f9eeca106725	209	*/
Kojto	122:f9eeca106725	210
Kojto	122:f9eeca106725	211	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
Kojto	122:f9eeca106725	212	* @brief Flags defines which can be used with LL_RCC_ReadReg function
Kojto	122:f9eeca106725	213	* @{
Kojto	122:f9eeca106725	214	*/
Kojto	122:f9eeca106725	215	#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /!< LSI Ready Interrupt flag /
Kojto	122:f9eeca106725	216	#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /!< LSE Ready Interrupt flag /
Kojto	122:f9eeca106725	217	#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /!< MSI Ready Interrupt flag /
Kojto	122:f9eeca106725	218	#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /!< HSI Ready Interrupt flag /
Kojto	122:f9eeca106725	219	#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /!< HSE Ready Interrupt flag /
Kojto	122:f9eeca106725	220	#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /!< PLL Ready Interrupt flag /
Kojto	122:f9eeca106725	221	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	222	#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
Kojto	122:f9eeca106725	223	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	224	#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /!< PLLSAI1 Ready Interrupt flag /
Kojto	122:f9eeca106725	225	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	226	#define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /!< PLLSAI2 Ready Interrupt flag /
Kojto	122:f9eeca106725	227	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	228	#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /!< LSE Clock Security System Interrupt flag /
Kojto	122:f9eeca106725	229	#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /!< Clock Security System Interrupt flag /
Kojto	122:f9eeca106725	230	#define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /!< Firewall reset flag /
Kojto	122:f9eeca106725	231	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
Kojto	122:f9eeca106725	232	#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /!< OBL reset flag /
Kojto	122:f9eeca106725	233	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
Kojto	122:f9eeca106725	234	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
Kojto	122:f9eeca106725	235	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
Kojto	122:f9eeca106725	236	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
Kojto	122:f9eeca106725	237	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /!< BOR reset flag /
Kojto	122:f9eeca106725	238	/**
Kojto	122:f9eeca106725	239	* @}
Kojto	122:f9eeca106725	240	*/
Kojto	122:f9eeca106725	241
Kojto	122:f9eeca106725	242	/** @defgroup RCC_LL_EC_IT IT Defines
Kojto	122:f9eeca106725	243	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
Kojto	122:f9eeca106725	244	* @{
Kojto	122:f9eeca106725	245	*/
Kojto	122:f9eeca106725	246	#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /!< LSI Ready Interrupt Enable /
Kojto	122:f9eeca106725	247	#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /!< LSE Ready Interrupt Enable /
Kojto	122:f9eeca106725	248	#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /!< MSI Ready Interrupt Enable /
Kojto	122:f9eeca106725	249	#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /!< HSI Ready Interrupt Enable /
Kojto	122:f9eeca106725	250	#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /!< HSE Ready Interrupt Enable /
Kojto	122:f9eeca106725	251	#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /!< PLL Ready Interrupt Enable /
Kojto	122:f9eeca106725	252	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	253	#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /!< HSI48 Ready Interrupt Enable /
Kojto	122:f9eeca106725	254	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	255	#define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /!< PLLSAI1 Ready Interrupt Enable /
Kojto	122:f9eeca106725	256	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	257	#define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /!< PLLSAI2 Ready Interrupt Enable /
Kojto	122:f9eeca106725	258	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	259	#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /!< LSE CSS Interrupt Enable /
Kojto	122:f9eeca106725	260	/**
Kojto	122:f9eeca106725	261	* @}
Kojto	122:f9eeca106725	262	*/
Kojto	122:f9eeca106725	263
Kojto	122:f9eeca106725	264	/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
Kojto	122:f9eeca106725	265	* @{
Kojto	122:f9eeca106725	266	*/
Kojto	122:f9eeca106725	267	#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) /!< Xtal mode lower driving capability /
Kojto	122:f9eeca106725	268	#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /!< Xtal mode medium low driving capability /
Kojto	122:f9eeca106725	269	#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /!< Xtal mode medium high driving capability /
Kojto	122:f9eeca106725	270	#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
Kojto	122:f9eeca106725	271	/**
Kojto	122:f9eeca106725	272	* @}
Kojto	122:f9eeca106725	273	*/
Kojto	122:f9eeca106725	274
Kojto	122:f9eeca106725	275	/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
Kojto	122:f9eeca106725	276	* @{
Kojto	122:f9eeca106725	277	*/
Kojto	122:f9eeca106725	278	#define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /!< MSI = 100 KHz /
Kojto	122:f9eeca106725	279	#define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /!< MSI = 200 KHz /
Kojto	122:f9eeca106725	280	#define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /!< MSI = 400 KHz /
Kojto	122:f9eeca106725	281	#define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /!< MSI = 800 KHz /
Kojto	122:f9eeca106725	282	#define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /!< MSI = 1 MHz /
Kojto	122:f9eeca106725	283	#define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /!< MSI = 2 MHz /
Kojto	122:f9eeca106725	284	#define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /!< MSI = 4 MHz /
Kojto	122:f9eeca106725	285	#define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /!< MSI = 8 MHz /
Kojto	122:f9eeca106725	286	#define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /!< MSI = 16 MHz /
Kojto	122:f9eeca106725	287	#define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /!< MSI = 24 MHz /
Kojto	122:f9eeca106725	288	#define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /!< MSI = 32 MHz /
Kojto	122:f9eeca106725	289	#define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /!< MSI = 48 MHz /
Kojto	122:f9eeca106725	290	/**
Kojto	122:f9eeca106725	291	* @}
Kojto	122:f9eeca106725	292	*/
Kojto	122:f9eeca106725	293
Kojto	122:f9eeca106725	294	/** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
Kojto	122:f9eeca106725	295	* @{
Kojto	122:f9eeca106725	296	*/
Kojto	122:f9eeca106725	297	#define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /!< MSI = 1 MHz /
Kojto	122:f9eeca106725	298	#define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /!< MSI = 2 MHz /
Kojto	122:f9eeca106725	299	#define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /!< MSI = 4 MHz /
Kojto	122:f9eeca106725	300	#define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /!< MSI = 8 MHz /
Kojto	122:f9eeca106725	301	/**
Kojto	122:f9eeca106725	302	* @}
Kojto	122:f9eeca106725	303	*/
Kojto	122:f9eeca106725	304
Kojto	122:f9eeca106725	305	/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
Kojto	122:f9eeca106725	306	* @{
Kojto	122:f9eeca106725	307	*/
Kojto	122:f9eeca106725	308	#define LL_RCC_LSCO_CLKSOURCE_LSI (uint32_t)0x00000000 /!< LSI selection for low speed clock /
Kojto	122:f9eeca106725	309	#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /!< LSE selection for low speed clock /
Kojto	122:f9eeca106725	310	/**
Kojto	122:f9eeca106725	311	* @}
Kojto	122:f9eeca106725	312	*/
Kojto	122:f9eeca106725	313
Kojto	122:f9eeca106725	314	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
Kojto	122:f9eeca106725	315	* @{
Kojto	122:f9eeca106725	316	*/
Kojto	122:f9eeca106725	317	#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
Kojto	122:f9eeca106725	318	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
Kojto	122:f9eeca106725	319	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
Kojto	122:f9eeca106725	320	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
Kojto	122:f9eeca106725	321	/**
Kojto	122:f9eeca106725	322	* @}
Kojto	122:f9eeca106725	323	*/
Kojto	122:f9eeca106725	324
Kojto	122:f9eeca106725	325	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
Kojto	122:f9eeca106725	326	* @{
Kojto	122:f9eeca106725	327	*/
Kojto	122:f9eeca106725	328	#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
Kojto	122:f9eeca106725	329	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
Kojto	122:f9eeca106725	330	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
Kojto	122:f9eeca106725	331	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
Kojto	122:f9eeca106725	332	/**
Kojto	122:f9eeca106725	333	* @}
Kojto	122:f9eeca106725	334	*/
Kojto	122:f9eeca106725	335
Kojto	122:f9eeca106725	336	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
Kojto	122:f9eeca106725	337	* @{
Kojto	122:f9eeca106725	338	*/
Kojto	122:f9eeca106725	339	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
Kojto	122:f9eeca106725	340	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
Kojto	122:f9eeca106725	341	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
Kojto	122:f9eeca106725	342	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
Kojto	122:f9eeca106725	343	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
Kojto	122:f9eeca106725	344	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
Kojto	122:f9eeca106725	345	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
Kojto	122:f9eeca106725	346	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
Kojto	122:f9eeca106725	347	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
Kojto	122:f9eeca106725	348	/**
Kojto	122:f9eeca106725	349	* @}
Kojto	122:f9eeca106725	350	*/
Kojto	122:f9eeca106725	351
Kojto	122:f9eeca106725	352	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
Kojto	122:f9eeca106725	353	* @{
Kojto	122:f9eeca106725	354	*/
Kojto	122:f9eeca106725	355	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
Kojto	122:f9eeca106725	356	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
Kojto	122:f9eeca106725	357	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
Kojto	122:f9eeca106725	358	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
Kojto	122:f9eeca106725	359	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
Kojto	122:f9eeca106725	360	/**
Kojto	122:f9eeca106725	361	* @}
Kojto	122:f9eeca106725	362	*/
Kojto	122:f9eeca106725	363	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
Kojto	122:f9eeca106725	364	* @{
Kojto	122:f9eeca106725	365	*/
Kojto	122:f9eeca106725	366	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
Kojto	122:f9eeca106725	367	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
Kojto	122:f9eeca106725	368	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
Kojto	122:f9eeca106725	369	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
Kojto	122:f9eeca106725	370	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
Kojto	122:f9eeca106725	371	/**
Kojto	122:f9eeca106725	372	* @}
Kojto	122:f9eeca106725	373	*/
Kojto	122:f9eeca106725	374	/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
Kojto	122:f9eeca106725	375	* @{
Kojto	122:f9eeca106725	376	*/
Kojto	122:f9eeca106725	377	#define LL_RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000) /!< MSI selection after wake-up from STOP /
Kojto	122:f9eeca106725	378	#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
Kojto	122:f9eeca106725	379	/**
Kojto	122:f9eeca106725	380	* @}
Kojto	122:f9eeca106725	381	*/
Kojto	122:f9eeca106725	382
Kojto	122:f9eeca106725	383	/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
Kojto	122:f9eeca106725	384	* @{
Kojto	122:f9eeca106725	385	*/
Kojto	122:f9eeca106725	386	#define LL_RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000) /!< MCO output disabled, no clock on MCO /
Kojto	122:f9eeca106725	387	#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /!< SYSCLK selection as MCO1 source /
Kojto	122:f9eeca106725	388	#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /!< MSI selection as MCO1 source /
Kojto	122:f9eeca106725	389	#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1) /!< HSI16 selection as MCO1 source /
Kojto	122:f9eeca106725	390	#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /!< HSE selection as MCO1 source /
Kojto	122:f9eeca106725	391	#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2) /!< Main PLL selection as MCO1 source /
Kojto	122:f9eeca106725	392	#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSI selection as MCO1 source /
Kojto	122:f9eeca106725	393	#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSE selection as MCO1 source /
Kojto	122:f9eeca106725	394	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	395	#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /!< HSI48 selection as MCO1 source /
Kojto	122:f9eeca106725	396	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	397	/**
Kojto	122:f9eeca106725	398	* @}
Kojto	122:f9eeca106725	399	*/
Kojto	122:f9eeca106725	400
Kojto	122:f9eeca106725	401	/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
Kojto	122:f9eeca106725	402	* @{
Kojto	122:f9eeca106725	403	*/
Kojto	122:f9eeca106725	404	#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /!< MCO not divided /
Kojto	122:f9eeca106725	405	#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO divided by 2 /
Kojto	122:f9eeca106725	406	#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO divided by 4 /
Kojto	122:f9eeca106725	407	#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO divided by 8 /
Kojto	122:f9eeca106725	408	#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO divided by 16 /
Kojto	122:f9eeca106725	409	/**
Kojto	122:f9eeca106725	410	* @}
Kojto	122:f9eeca106725	411	*/
Kojto	122:f9eeca106725	412
Kojto	122:f9eeca106725	413	#if defined(USE_FULL_LL_DRIVER)
Kojto	122:f9eeca106725	414	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
Kojto	122:f9eeca106725	415	* @{
Kojto	122:f9eeca106725	416	*/
Kojto	122:f9eeca106725	417	#define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000 /!< No clock enabled for the peripheral /
Kojto	122:f9eeca106725	418	#define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
Kojto	122:f9eeca106725	419	/**
Kojto	122:f9eeca106725	420	* @}
Kojto	122:f9eeca106725	421	*/
Kojto	122:f9eeca106725	422	#endif /* USE_FULL_LL_DRIVER */
Kojto	122:f9eeca106725	423
Kojto	122:f9eeca106725	424	/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
Kojto	122:f9eeca106725	425	* @{
Kojto	122:f9eeca106725	426	*/
Kojto	122:f9eeca106725	427	#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_CCIPR_USART1SEL << 16) \| 0x00000000) /!< PCLK2 clock used as USART1 clock source /
Kojto	122:f9eeca106725	428	#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART1SEL << 16) \| RCC_CCIPR_USART1SEL_0) /!< SYSCLK clock used as USART1 clock source /
Kojto	122:f9eeca106725	429	#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART1SEL << 16) \| RCC_CCIPR_USART1SEL_1) /!< HSI clock used as USART1 clock source /
Kojto	122:f9eeca106725	430	#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART1SEL << 16) \| RCC_CCIPR_USART1SEL) /!< LSE clock used as USART1 clock source /
Kojto	122:f9eeca106725	431	#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART2SEL << 16) \| 0x00000000) /!< PCLK1 clock used as USART2 clock source /
Kojto	122:f9eeca106725	432	#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART2SEL << 16) \| RCC_CCIPR_USART2SEL_0) /!< SYSCLK clock used as USART2 clock source /
Kojto	122:f9eeca106725	433	#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART2SEL << 16) \| RCC_CCIPR_USART2SEL_1) /!< HSI clock used as USART2 clock source /
Kojto	122:f9eeca106725	434	#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART2SEL << 16) \| RCC_CCIPR_USART2SEL) /!< LSE clock used as USART2 clock source /
Kojto	122:f9eeca106725	435	#if defined(RCC_CCIPR_USART3SEL)
Kojto	122:f9eeca106725	436	#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART3SEL << 16) \| 0x00000000) /!< PCLK1 clock used as USART3 clock source /
Kojto	122:f9eeca106725	437	#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART3SEL << 16) \| RCC_CCIPR_USART3SEL_0) /!< SYSCLK clock used as USART3 clock source /
Kojto	122:f9eeca106725	438	#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART3SEL << 16) \| RCC_CCIPR_USART3SEL_1) /!< HSI clock used as USART3 clock source /
Kojto	122:f9eeca106725	439	#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART3SEL << 16) \| RCC_CCIPR_USART3SEL) /!< LSE clock used as USART3 clock source /
Kojto	122:f9eeca106725	440	#endif /* RCC_CCIPR_USART3SEL */
Kojto	122:f9eeca106725	441	/**
Kojto	122:f9eeca106725	442	* @}
Kojto	122:f9eeca106725	443	*/
Kojto	122:f9eeca106725	444
Kojto	122:f9eeca106725	445	#if defined(RCC_CCIPR_UART4SEL) \|\| defined(RCC_CCIPR_UART5SEL)
Kojto	122:f9eeca106725	446	/** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
Kojto	122:f9eeca106725	447	* @{
Kojto	122:f9eeca106725	448	*/
Kojto	122:f9eeca106725	449	#if defined(RCC_CCIPR_UART4SEL)
Kojto	122:f9eeca106725	450	#define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART4SEL << 16) \| 0x00000000) /!< PCLK1 clock used as UART4 clock source /
Kojto	122:f9eeca106725	451	#define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART4SEL << 16) \| RCC_CCIPR_UART4SEL_0) /!< SYSCLK clock used as UART4 clock source /
Kojto	122:f9eeca106725	452	#define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART4SEL << 16) \| RCC_CCIPR_UART4SEL_1) /!< HSI clock used as UART4 clock source /
Kojto	122:f9eeca106725	453	#define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART4SEL << 16) \| RCC_CCIPR_UART4SEL) /!< LSE clock used as UART4 clock source /
Kojto	122:f9eeca106725	454	#endif /* RCC_CCIPR_UART4SEL */
Kojto	122:f9eeca106725	455	#if defined(RCC_CCIPR_UART5SEL)
Kojto	122:f9eeca106725	456	#define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART5SEL << 16) \| 0x00000000) /!< PCLK1 clock used as UART5 clock source /
Kojto	122:f9eeca106725	457	#define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART5SEL << 16) \| RCC_CCIPR_UART5SEL_0) /!< SYSCLK clock used as UART5 clock source /
Kojto	122:f9eeca106725	458	#define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART5SEL << 16) \| RCC_CCIPR_UART5SEL_1) /!< HSI clock used as UART5 clock source /
Kojto	122:f9eeca106725	459	#define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART5SEL << 16) \| RCC_CCIPR_UART5SEL) /!< LSE clock used as UART5 clock source /
Kojto	122:f9eeca106725	460	#endif /* RCC_CCIPR_UART5SEL */
Kojto	122:f9eeca106725	461	/**
Kojto	122:f9eeca106725	462	* @}
Kojto	122:f9eeca106725	463	*/
Kojto	122:f9eeca106725	464	#endif /* RCC_CCIPR_UART4SEL \|\| RCC_CCIPR_UART5SEL */
Kojto	122:f9eeca106725	465
Kojto	122:f9eeca106725	466	/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
Kojto	122:f9eeca106725	467	* @{
Kojto	122:f9eeca106725	468	*/
Kojto	122:f9eeca106725	469	#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 (uint32_t)0x00000000 /!< PCLK1 clock used as LPUART1 clock source /
Kojto	122:f9eeca106725	470	#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /!< SYSCLK clock used as LPUART1 clock source /
Kojto	122:f9eeca106725	471	#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /!< HSI clock used as LPUART1 clock source /
Kojto	122:f9eeca106725	472	#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /!< LSE clock used as LPUART1 clock source /
Kojto	122:f9eeca106725	473	/**
Kojto	122:f9eeca106725	474	* @}
Kojto	122:f9eeca106725	475	*/
Kojto	122:f9eeca106725	476
Kojto	122:f9eeca106725	477	/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
Kojto	122:f9eeca106725	478	* @{
Kojto	122:f9eeca106725	479	*/
Kojto	122:f9eeca106725	480	#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) \| (0x00000000 >> 4)) /!< PCLK1 clock used as I2C1 clock source /
Kojto	122:f9eeca106725	481	#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) \| (RCC_CCIPR_I2C1SEL_0 >> 4)) /!< SYSCLK clock used as I2C1 clock source /
Kojto	122:f9eeca106725	482	#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) \| (RCC_CCIPR_I2C1SEL_1 >> 4)) /!< HSI clock used as I2C1 clock source /
Kojto	122:f9eeca106725	483	#if defined(RCC_CCIPR_I2C2SEL)
Kojto	122:f9eeca106725	484	#define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C2SEL << 4) \| (0x00000000 >> 4)) /!< PCLK1 clock used as I2C2 clock source /
Kojto	122:f9eeca106725	485	#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C2SEL << 4) \| (RCC_CCIPR_I2C2SEL_0 >> 4)) /!< SYSCLK clock used as I2C2 clock source /
Kojto	122:f9eeca106725	486	#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C2SEL << 4) \| (RCC_CCIPR_I2C2SEL_1 >> 4)) /!< HSI clock used as I2C2 clock source /
Kojto	122:f9eeca106725	487	#endif /* RCC_CCIPR_I2C2SEL */
Kojto	122:f9eeca106725	488	#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) \| (0x00000000 >> 4)) /!< PCLK1 clock used as I2C3 clock source /
Kojto	122:f9eeca106725	489	#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) \| (RCC_CCIPR_I2C3SEL_0 >> 4)) /!< SYSCLK clock used as I2C3 clock source /
Kojto	122:f9eeca106725	490	#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) \| (RCC_CCIPR_I2C3SEL_1 >> 4)) /!< HSI clock used as I2C3 clock source /
Kojto	122:f9eeca106725	491	/**
Kojto	122:f9eeca106725	492	* @}
Kojto	122:f9eeca106725	493	*/
Kojto	122:f9eeca106725	494
Kojto	122:f9eeca106725	495	/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
Kojto	122:f9eeca106725	496	* @{
Kojto	122:f9eeca106725	497	*/
Kojto	122:f9eeca106725	498	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL \| (0x00000000 >> 16)) /!< PCLK1 clock used as LPTIM1 clock source /
Kojto	122:f9eeca106725	499	#define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /!< LSI clock used as LPTIM1 clock source /
Kojto	122:f9eeca106725	500	#define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /!< HSI clock used as LPTIM1 clock source /
Kojto	122:f9eeca106725	501	#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL >> 16)) /!< LSE clock used as LPTIM1 clock source /
Kojto	122:f9eeca106725	502	#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL \| (0x00000000 >> 16)) /!< PCLK1 clock used as LPTIM2 clock source /
Kojto	122:f9eeca106725	503	#define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /!< LSI clock used as LPTIM2 clock source /
Kojto	122:f9eeca106725	504	#define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /!< HSI clock used as LPTIM2 clock source /
Kojto	122:f9eeca106725	505	#define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL >> 16)) /!< LSE clock used as LPTIM2 clock source /
Kojto	122:f9eeca106725	506	/**
Kojto	122:f9eeca106725	507	* @}
Kojto	122:f9eeca106725	508	*/
Kojto	122:f9eeca106725	509
Kojto	122:f9eeca106725	510	/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
Kojto	122:f9eeca106725	511	* @{
Kojto	122:f9eeca106725	512	*/
Kojto	122:f9eeca106725	513	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI1SEL \| (0x00000000 >> 16)) /!< PLLSAI1 clock used as SAI1 clock source /
Kojto	122:f9eeca106725	514	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	515	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL_0 >> 16)) /!< PLLSAI2 clock used as SAI1 clock source /
Kojto	122:f9eeca106725	516	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	517	#define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL_1 >> 16)) /!< PLL clock used as SAI1 clock source /
Kojto	122:f9eeca106725	518	#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL >> 16)) /!< External input clock used as SAI1 clock source /
Kojto	122:f9eeca106725	519	#if defined(RCC_CCIPR_SAI2SEL)
Kojto	122:f9eeca106725	520	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI2SEL \| (0x00000000 >> 16)) /!< PLLSAI1 clock used as SAI2 clock source /
Kojto	122:f9eeca106725	521	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	522	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL_0 >> 16)) /!< PLLSAI2 clock used as SAI2 clock source /
Kojto	122:f9eeca106725	523	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	524	#define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL_1 >> 16)) /!< PLL clock used as SAI2 clock source /
Kojto	122:f9eeca106725	525	#define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL >> 16)) /!< External input clock used as SAI2 clock source /
Kojto	122:f9eeca106725	526	#endif /* RCC_CCIPR_SAI2SEL */
Kojto	122:f9eeca106725	527	/**
Kojto	122:f9eeca106725	528	* @}
Kojto	122:f9eeca106725	529	*/
Kojto	122:f9eeca106725	530
Kojto	122:f9eeca106725	531	/** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
Kojto	122:f9eeca106725	532	* @{
Kojto	122:f9eeca106725	533	*/
Kojto	122:f9eeca106725	534	#define LL_RCC_SDMMC1_CLKSOURCE_NONE (uint32_t)(0x00000000) /!< No clock used as SDMMC1 clock source /
Kojto	122:f9eeca106725	535	#define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0) /!< PLLSAI1 clock used as SDMMC1 clock source /
Kojto	122:f9eeca106725	536	#define LL_RCC_SDMMC1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1) /!< PLL clock used as SDMMC1 clock source /
Kojto	122:f9eeca106725	537	#define LL_RCC_SDMMC1_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL) /!< MSI clock used as SDMMC1 clock source /
Kojto	122:f9eeca106725	538	/**
Kojto	122:f9eeca106725	539	* @}
Kojto	122:f9eeca106725	540	*/
Kojto	122:f9eeca106725	541
Kojto	122:f9eeca106725	542	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
Kojto	122:f9eeca106725	543	* @{
Kojto	122:f9eeca106725	544	*/
Kojto	122:f9eeca106725	545	#define LL_RCC_RNG_CLKSOURCE_NONE (uint32_t)(0x00000000) /!< No clock used as RNG clock source /
Kojto	122:f9eeca106725	546	#define LL_RCC_RNG_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0) /!< PLLSAI1 clock used as RNG clock source /
Kojto	122:f9eeca106725	547	#define LL_RCC_RNG_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1) /!< PLL clock used as RNG clock source /
Kojto	122:f9eeca106725	548	#define LL_RCC_RNG_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL) /!< MSI clock used as RNG clock source /
Kojto	122:f9eeca106725	549	/**
Kojto	122:f9eeca106725	550	* @}
Kojto	122:f9eeca106725	551	*/
Kojto	122:f9eeca106725	552
Kojto	122:f9eeca106725	553	#if defined(USB_OTG_FS) \|\| defined(USB)
Kojto	122:f9eeca106725	554	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
Kojto	122:f9eeca106725	555	* @{
Kojto	122:f9eeca106725	556	*/
Kojto	122:f9eeca106725	557	#define LL_RCC_USB_CLKSOURCE_NONE (uint32_t)(0x00000000) /!< No clock used as USB clock source /
Kojto	122:f9eeca106725	558	#define LL_RCC_USB_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0) /!< PLLSAI1 clock used as USB clock source /
Kojto	122:f9eeca106725	559	#define LL_RCC_USB_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1) /!< PLL clock used as USB clock source /
Kojto	122:f9eeca106725	560	#define LL_RCC_USB_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL) /!< MSI clock used as USB clock source /
Kojto	122:f9eeca106725	561	/**
Kojto	122:f9eeca106725	562	* @}
Kojto	122:f9eeca106725	563	*/
Kojto	122:f9eeca106725	564
Kojto	122:f9eeca106725	565	#endif /* USB_OTG_FS \|\| USB */
Kojto	122:f9eeca106725	566
Kojto	122:f9eeca106725	567	/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
Kojto	122:f9eeca106725	568	* @{
Kojto	122:f9eeca106725	569	*/
Kojto	122:f9eeca106725	570	#define LL_RCC_ADC_CLKSOURCE_NONE (uint32_t)(0x00000000) /!< No clock used as ADC clock source /
Kojto	122:f9eeca106725	571	#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_ADCSEL_0) /!< PLLSAI1 clock used as ADC clock source /
Kojto	122:f9eeca106725	572	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	573	#define LL_RCC_ADC_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_ADCSEL_1) /!< PLLSAI2 clock used as ADC clock source /
Kojto	122:f9eeca106725	574	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	575	#define LL_RCC_ADC_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_ADCSEL) /!< SYSCLK clock used as ADC clock source /
Kojto	122:f9eeca106725	576	/**
Kojto	122:f9eeca106725	577	* @}
Kojto	122:f9eeca106725	578	*/
Kojto	122:f9eeca106725	579
Kojto	122:f9eeca106725	580	/** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI clock source selection
Kojto	122:f9eeca106725	581	* @{
Kojto	122:f9eeca106725	582	*/
Kojto	122:f9eeca106725	583	#define LL_RCC_SWPMI1_CLKSOURCE_PCLK (uint32_t)(0x00000000) /!< PCLK used as SWPMI1 clock source /
Kojto	122:f9eeca106725	584	#define LL_RCC_SWPMI1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_SWPMI1SEL) /!< HSI used as SWPMI1 clock source /
Kojto	122:f9eeca106725	585	/**
Kojto	122:f9eeca106725	586	* @}
Kojto	122:f9eeca106725	587	*/
Kojto	122:f9eeca106725	588
Kojto	122:f9eeca106725	589	#if defined(DFSDM1_Channel0)
Kojto	122:f9eeca106725	590	/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM clock source selection
Kojto	122:f9eeca106725	591	* @{
Kojto	122:f9eeca106725	592	*/
Kojto	122:f9eeca106725	593	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK (uint32_t)(0x00000000) /!< PCLK used as DFSDM1 clock source /
Kojto	122:f9eeca106725	594	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_DFSDM1SEL) /!< SYSCLK used as DFSDM1 clock source /
Kojto	122:f9eeca106725	595	/**
Kojto	122:f9eeca106725	596	* @}
Kojto	122:f9eeca106725	597	*/
Kojto	122:f9eeca106725	598	#endif /* DFSDM1_Channel0 */
Kojto	122:f9eeca106725	599
Kojto	122:f9eeca106725	600	/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
Kojto	122:f9eeca106725	601	* @{
Kojto	122:f9eeca106725	602	*/
Kojto	122:f9eeca106725	603	#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /!< USART1 Clock source selection /
Kojto	122:f9eeca106725	604	#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /!< USART2 Clock source selection /
Kojto	122:f9eeca106725	605	#if defined(RCC_CCIPR_USART3SEL)
Kojto	122:f9eeca106725	606	#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /!< USART3 Clock source selection /
Kojto	122:f9eeca106725	607	#endif /* RCC_CCIPR_USART3SEL */
Kojto	122:f9eeca106725	608	/**
Kojto	122:f9eeca106725	609	* @}
Kojto	122:f9eeca106725	610	*/
Kojto	122:f9eeca106725	611
Kojto	122:f9eeca106725	612	#if defined(RCC_CCIPR_UART4SEL) \|\| defined(RCC_CCIPR_UART5SEL)
Kojto	122:f9eeca106725	613	/** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source
Kojto	122:f9eeca106725	614	* @{
Kojto	122:f9eeca106725	615	*/
Kojto	122:f9eeca106725	616	#if defined(RCC_CCIPR_UART4SEL)
Kojto	122:f9eeca106725	617	#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /!< UART4 Clock source selection /
Kojto	122:f9eeca106725	618	#endif /* RCC_CCIPR_UART4SEL */
Kojto	122:f9eeca106725	619	#if defined(RCC_CCIPR_UART5SEL)
Kojto	122:f9eeca106725	620	#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /!< UART5 Clock source selection /
Kojto	122:f9eeca106725	621	#endif /* RCC_CCIPR_UART5SEL */
Kojto	122:f9eeca106725	622	/**
Kojto	122:f9eeca106725	623	* @}
Kojto	122:f9eeca106725	624	*/
Kojto	122:f9eeca106725	625	#endif /* RCC_CCIPR_UART4SEL \|\| RCC_CCIPR_UART5SEL */
Kojto	122:f9eeca106725	626
Kojto	122:f9eeca106725	627	/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
Kojto	122:f9eeca106725	628	* @{
Kojto	122:f9eeca106725	629	*/
Kojto	122:f9eeca106725	630	#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /!< LPUART1 Clock source selection /
Kojto	122:f9eeca106725	631	/**
Kojto	122:f9eeca106725	632	* @}
Kojto	122:f9eeca106725	633	*/
Kojto	122:f9eeca106725	634
Kojto	122:f9eeca106725	635	/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
Kojto	122:f9eeca106725	636	* @{
Kojto	122:f9eeca106725	637	*/
Kojto	122:f9eeca106725	638	#define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /!< I2C1 Clock source selection /
Kojto	122:f9eeca106725	639	#if defined(RCC_CCIPR_I2C2SEL)
Kojto	122:f9eeca106725	640	#define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL /!< I2C2 Clock source selection /
Kojto	122:f9eeca106725	641	#endif /* RCC_CCIPR_I2C2SEL */
Kojto	122:f9eeca106725	642	#define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /!< I2C3 Clock source selection /
Kojto	122:f9eeca106725	643	/**
Kojto	122:f9eeca106725	644	* @}
Kojto	122:f9eeca106725	645	*/
Kojto	122:f9eeca106725	646
Kojto	122:f9eeca106725	647	/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
Kojto	122:f9eeca106725	648	* @{
Kojto	122:f9eeca106725	649	*/
Kojto	122:f9eeca106725	650	#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /!< LPTIM1 Clock source selection /
Kojto	122:f9eeca106725	651	#define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /!< LPTIM2 Clock source selection /
Kojto	122:f9eeca106725	652	/**
Kojto	122:f9eeca106725	653	* @}
Kojto	122:f9eeca106725	654	*/
Kojto	122:f9eeca106725	655
Kojto	122:f9eeca106725	656	/** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
Kojto	122:f9eeca106725	657	* @{
Kojto	122:f9eeca106725	658	*/
Kojto	122:f9eeca106725	659	#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /!< SAI1 Clock source selection /
Kojto	122:f9eeca106725	660	#if defined(RCC_CCIPR_SAI2SEL)
Kojto	122:f9eeca106725	661	#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /!< SAI2 Clock source selection /
Kojto	122:f9eeca106725	662	#endif /* RCC_CCIPR_SAI2SEL */
Kojto	122:f9eeca106725	663	/**
Kojto	122:f9eeca106725	664	* @}
Kojto	122:f9eeca106725	665	*/
Kojto	122:f9eeca106725	666
Kojto	122:f9eeca106725	667	/** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source
Kojto	122:f9eeca106725	668	* @{
Kojto	122:f9eeca106725	669	*/
Kojto	122:f9eeca106725	670	#define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /!< SDMMC1 Clock source selection /
Kojto	122:f9eeca106725	671	/**
Kojto	122:f9eeca106725	672	* @}
Kojto	122:f9eeca106725	673	*/
Kojto	122:f9eeca106725	674
Kojto	122:f9eeca106725	675	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
Kojto	122:f9eeca106725	676	* @{
Kojto	122:f9eeca106725	677	*/
Kojto	122:f9eeca106725	678	#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /!< RNG Clock source selection /
Kojto	122:f9eeca106725	679	/**
Kojto	122:f9eeca106725	680	* @}
Kojto	122:f9eeca106725	681	*/
Kojto	122:f9eeca106725	682
Kojto	122:f9eeca106725	683	#if defined(USB_OTG_FS) \|\| defined(USB)
Kojto	122:f9eeca106725	684	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
Kojto	122:f9eeca106725	685	* @{
Kojto	122:f9eeca106725	686	*/
Kojto	122:f9eeca106725	687	#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /!< USB Clock source selection /
Kojto	122:f9eeca106725	688	/**
Kojto	122:f9eeca106725	689	* @}
Kojto	122:f9eeca106725	690	*/
Kojto	122:f9eeca106725	691
Kojto	122:f9eeca106725	692	#endif /* USB_OTG_FS \|\| USB */
Kojto	122:f9eeca106725	693
Kojto	122:f9eeca106725	694	/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
Kojto	122:f9eeca106725	695	* @{
Kojto	122:f9eeca106725	696	*/
Kojto	122:f9eeca106725	697	#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /!< ADC Clock source selection /
Kojto	122:f9eeca106725	698	/**
Kojto	122:f9eeca106725	699	* @}
Kojto	122:f9eeca106725	700	*/
Kojto	122:f9eeca106725	701
Kojto	122:f9eeca106725	702	/** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI get clock source
Kojto	122:f9eeca106725	703	* @{
Kojto	122:f9eeca106725	704	*/
Kojto	122:f9eeca106725	705	#define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL /!< SWPMI1 Clock source selection /
Kojto	122:f9eeca106725	706	/**
Kojto	122:f9eeca106725	707	* @}
Kojto	122:f9eeca106725	708	*/
Kojto	122:f9eeca106725	709
Kojto	122:f9eeca106725	710	#if defined(DFSDM1_Channel0)
Kojto	122:f9eeca106725	711	/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
Kojto	122:f9eeca106725	712	* @{
Kojto	122:f9eeca106725	713	*/
Kojto	122:f9eeca106725	714	#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /!< DFSDM1 Clock source selection /
Kojto	122:f9eeca106725	715	/**
Kojto	122:f9eeca106725	716	* @}
Kojto	122:f9eeca106725	717	*/
Kojto	122:f9eeca106725	718	#endif /* DFSDM1_Channel0 */
Kojto	122:f9eeca106725	719
Kojto	122:f9eeca106725	720	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
Kojto	122:f9eeca106725	721	* @{
Kojto	122:f9eeca106725	722	*/
Kojto	122:f9eeca106725	723	#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000) /!< No clock used as RTC clock /
Kojto	122:f9eeca106725	724	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
Kojto	122:f9eeca106725	725	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
Kojto	122:f9eeca106725	726	#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
Kojto	122:f9eeca106725	727	/**
Kojto	122:f9eeca106725	728	* @}
Kojto	122:f9eeca106725	729	*/
Kojto	122:f9eeca106725	730
Kojto	122:f9eeca106725	731	/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source
Kojto	122:f9eeca106725	732	* @{
Kojto	122:f9eeca106725	733	*/
Kojto	122:f9eeca106725	734	#define LL_RCC_PLLSOURCE_NONE (uint32_t)0x00000000 /!< No clock /
Kojto	122:f9eeca106725	735	#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /!< MSI clock selected as PLL entry clock source /
Kojto	122:f9eeca106725	736	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI16 clock selected as PLL entry clock source /
Kojto	122:f9eeca106725	737	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
Kojto	122:f9eeca106725	738	/**
Kojto	122:f9eeca106725	739	* @}
Kojto	122:f9eeca106725	740	*/
Kojto	122:f9eeca106725	741
Kojto	122:f9eeca106725	742	/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLSAI1 and PLLSAI2 division factor
Kojto	122:f9eeca106725	743	* @{
Kojto	122:f9eeca106725	744	*/
Kojto	122:f9eeca106725	745	#define LL_RCC_PLLM_DIV_1 ((uint32_t)0x00000000) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 1 /
Kojto	122:f9eeca106725	746	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 2 /
Kojto	122:f9eeca106725	747	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 3 /
Kojto	122:f9eeca106725	748	#define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0)) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 4 /
Kojto	122:f9eeca106725	749	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 5 /
Kojto	122:f9eeca106725	750	#define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0)) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 6 /
Kojto	122:f9eeca106725	751	#define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1)) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 7 /
Kojto	122:f9eeca106725	752	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 8 /
Kojto	122:f9eeca106725	753	/**
Kojto	122:f9eeca106725	754	* @}
Kojto	122:f9eeca106725	755	*/
Kojto	122:f9eeca106725	756
Kojto	122:f9eeca106725	757	/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
Kojto	122:f9eeca106725	758	* @{
Kojto	122:f9eeca106725	759	*/
Kojto	122:f9eeca106725	760	#define LL_RCC_PLLR_DIV_2 ((uint32_t)0x00000000) /!< Main PLL division factor for PLLCLK (system clock) by 2 /
Kojto	122:f9eeca106725	761	#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 4 /
Kojto	122:f9eeca106725	762	#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 6 /
Kojto	122:f9eeca106725	763	#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /!< Main PLL division factor for PLLCLK (system clock) by 8 /
Kojto	122:f9eeca106725	764	/**
Kojto	122:f9eeca106725	765	* @}
Kojto	122:f9eeca106725	766	*/
Kojto	122:f9eeca106725	767
Kojto	122:f9eeca106725	768	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
Kojto	122:f9eeca106725	769	* @{
Kojto	122:f9eeca106725	770	*/
Kojto	122:f9eeca106725	771	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	772	#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 2 /
Kojto	122:f9eeca106725	773	#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 3 /
Kojto	122:f9eeca106725	774	#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 4 /
Kojto	122:f9eeca106725	775	#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 5 /
Kojto	122:f9eeca106725	776	#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 6 /
Kojto	122:f9eeca106725	777	#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 7 /
Kojto	122:f9eeca106725	778	#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 8 /
Kojto	122:f9eeca106725	779	#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 9 /
Kojto	122:f9eeca106725	780	#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 10 /
Kojto	122:f9eeca106725	781	#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_3)) /!< Main PLL division factor for PLLP output by 11 /
Kojto	122:f9eeca106725	782	#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 12 /
Kojto	122:f9eeca106725	783	#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 13 /
Kojto	122:f9eeca106725	784	#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 14 /
Kojto	122:f9eeca106725	785	#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 15 /
Kojto	122:f9eeca106725	786	#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 16 /
Kojto	122:f9eeca106725	787	#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 17 /
Kojto	122:f9eeca106725	788	#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 18 /
Kojto	122:f9eeca106725	789	#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_4)) /!< Main PLL division factor for PLLP output by 19 /
Kojto	122:f9eeca106725	790	#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 20 /
Kojto	122:f9eeca106725	791	#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 21 /
Kojto	122:f9eeca106725	792	#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 22 /
Kojto	122:f9eeca106725	793	#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 23 /
Kojto	122:f9eeca106725	794	#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 24 /
Kojto	122:f9eeca106725	795	#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 25 /
Kojto	122:f9eeca106725	796	#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 26 /
Kojto	122:f9eeca106725	797	#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 27 /
Kojto	122:f9eeca106725	798	#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 28 /
Kojto	122:f9eeca106725	799	#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 29 /
Kojto	122:f9eeca106725	800	#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 30 /
Kojto	122:f9eeca106725	801	#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 31 /
Kojto	122:f9eeca106725	802	#else
Kojto	122:f9eeca106725	803	#define LL_RCC_PLLP_DIV_7 ((uint32_t)0x00000000) /!< Main PLL division factor for PLLP output by 7 /
Kojto	122:f9eeca106725	804	#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /!< Main PLL division factor for PLLP output by 17 /
Kojto	122:f9eeca106725	805	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	806	/**
Kojto	122:f9eeca106725	807	* @}
Kojto	122:f9eeca106725	808	*/
Kojto	122:f9eeca106725	809
Kojto	122:f9eeca106725	810	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
Kojto	122:f9eeca106725	811	* @{
Kojto	122:f9eeca106725	812	*/
Kojto	122:f9eeca106725	813	#define LL_RCC_PLLQ_DIV_2 ((uint32_t)0x00000000) /!< Main PLL division factor for PLLQ output by 2 /
Kojto	122:f9eeca106725	814	#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 4 /
Kojto	122:f9eeca106725	815	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 6 /
Kojto	122:f9eeca106725	816	#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /!< Main PLL division factor for PLLQ output by 8 /
Kojto	122:f9eeca106725	817	/**
Kojto	122:f9eeca106725	818	* @}
Kojto	122:f9eeca106725	819	*/
Kojto	122:f9eeca106725	820
Kojto	122:f9eeca106725	821	/** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q)
Kojto	122:f9eeca106725	822	* @{
Kojto	122:f9eeca106725	823	*/
Kojto	122:f9eeca106725	824	#define LL_RCC_PLLSAI1Q_DIV_2 ((uint32_t)0x00000000) /!< PLLSAI1 division factor for PLLSAI1Q output by 2 /
Kojto	122:f9eeca106725	825	#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /!< PLLSAI1 division factor for PLLSAI1Q output by 4 /
Kojto	122:f9eeca106725	826	#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /!< PLLSAI1 division factor for PLLSAI1Q output by 6 /
Kojto	122:f9eeca106725	827	#define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /!< PLLSAI1 division factor for PLLSAI1Q output by 8 /
Kojto	122:f9eeca106725	828	/**
Kojto	122:f9eeca106725	829	* @}
Kojto	122:f9eeca106725	830	*/
Kojto	122:f9eeca106725	831
Kojto	122:f9eeca106725	832	/** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P)
Kojto	122:f9eeca106725	833	* @{
Kojto	122:f9eeca106725	834	*/
Kojto	122:f9eeca106725	835	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	836	#define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 2 /
Kojto	122:f9eeca106725	837	#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 3 /
Kojto	122:f9eeca106725	838	#define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 4 /
Kojto	122:f9eeca106725	839	#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 5 /
Kojto	122:f9eeca106725	840	#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 6 /
Kojto	122:f9eeca106725	841	#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 7 /
Kojto	122:f9eeca106725	842	#define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 8 /
Kojto	122:f9eeca106725	843	#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 9 /
Kojto	122:f9eeca106725	844	#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 10 /
Kojto	122:f9eeca106725	845	#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)) /!< PLLSAI1 division factor for PLLSAI1P output by 1 /
Kojto	122:f9eeca106725	846	#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 12 /
Kojto	122:f9eeca106725	847	#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 13 /
Kojto	122:f9eeca106725	848	#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 14 /
Kojto	122:f9eeca106725	849	#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 15 /
Kojto	122:f9eeca106725	850	#define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 16 /
Kojto	122:f9eeca106725	851	#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 17 /
Kojto	122:f9eeca106725	852	#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 18 /
Kojto	122:f9eeca106725	853	#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)) /!< PLLSAI1 division factor for PLLSAI1P output by 19 /
Kojto	122:f9eeca106725	854	#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 20 /
Kojto	122:f9eeca106725	855	#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division fctor for PLLSAI1P output by 21 /
Kojto	122:f9eeca106725	856	#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 22 /
Kojto	122:f9eeca106725	857	#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 23 /
Kojto	122:f9eeca106725	858	#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 24 /
Kojto	122:f9eeca106725	859	#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 25 /
Kojto	122:f9eeca106725	860	#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 26 /
Kojto	122:f9eeca106725	861	#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 27 /
Kojto	122:f9eeca106725	862	#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 28 /
Kojto	122:f9eeca106725	863	#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 29 /
Kojto	122:f9eeca106725	864	#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 30 /
Kojto	122:f9eeca106725	865	#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 31 /
Kojto	122:f9eeca106725	866	#else
Kojto	122:f9eeca106725	867	#define LL_RCC_PLLSAI1P_DIV_7 ((uint32_t)0x00000000) /!< PLLSAI1 division factor for PLLSAI1P output by 7 /
Kojto	122:f9eeca106725	868	#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /!< PLLSAI1 division factor for PLLSAI1P output by 17 /
Kojto	122:f9eeca106725	869	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	870	/**
Kojto	122:f9eeca106725	871	* @}
Kojto	122:f9eeca106725	872	*/
Kojto	122:f9eeca106725	873
Kojto	122:f9eeca106725	874	/** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R)
Kojto	122:f9eeca106725	875	* @{
Kojto	122:f9eeca106725	876	*/
Kojto	122:f9eeca106725	877	#define LL_RCC_PLLSAI1R_DIV_2 ((uint32_t)0x00000000) /!< PLLSAI1 division factor for PLLSAI1R output by 2 /
Kojto	122:f9eeca106725	878	#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /!< PLLSAI1 division factor for PLLSAI1R output by 4 /
Kojto	122:f9eeca106725	879	#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /!< PLLSAI1 division factor for PLLSAI1R output by 6 /
Kojto	122:f9eeca106725	880	#define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /!< PLLSAI1 division factor for PLLSAI1R output by 8 /
Kojto	122:f9eeca106725	881	/**
Kojto	122:f9eeca106725	882	* @}
Kojto	122:f9eeca106725	883	*/
Kojto	122:f9eeca106725	884
Kojto	122:f9eeca106725	885	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	886	/** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P)
Kojto	122:f9eeca106725	887	* @{
Kojto	122:f9eeca106725	888	*/
Kojto	122:f9eeca106725	889	#define LL_RCC_PLLSAI2P_DIV_7 ((uint32_t)0x00000000) /!< PLLSAI2 division factor for PLLSAI2P output by 7 /
Kojto	122:f9eeca106725	890	#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /!< PLLSAI2 division factor for PLLSAI2P output by 17 /
Kojto	122:f9eeca106725	891	/**
Kojto	122:f9eeca106725	892	* @}
Kojto	122:f9eeca106725	893	*/
Kojto	122:f9eeca106725	894
Kojto	122:f9eeca106725	895	/** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R)
Kojto	122:f9eeca106725	896	* @{
Kojto	122:f9eeca106725	897	*/
Kojto	122:f9eeca106725	898	#define LL_RCC_PLLSAI2R_DIV_2 ((uint32_t)0x00000000) /!< PLLSAI2 division factor for PLLSAI2R output by 2 /
Kojto	122:f9eeca106725	899	#define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0) /!< PLLSAI2 division factor for PLLSAI2R output by 4 /
Kojto	122:f9eeca106725	900	#define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1) /!< PLLSAI2 division factor for PLLSAI2R output by 6 /
Kojto	122:f9eeca106725	901	#define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R) /!< PLLSAI2 division factor for PLLSAI2R output by 8 /
Kojto	122:f9eeca106725	902	/**
Kojto	122:f9eeca106725	903	* @}
Kojto	122:f9eeca106725	904	*/
Kojto	122:f9eeca106725	905	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	906
Kojto	122:f9eeca106725	907	/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
Kojto	122:f9eeca106725	908	* @{
Kojto	122:f9eeca106725	909	*/
Kojto	122:f9eeca106725	910	#define LL_RCC_MSIRANGESEL_STANDBY (uint32_t)0 /!< MSI Range is provided by MSISRANGE /
Kojto	122:f9eeca106725	911	#define LL_RCC_MSIRANGESEL_RUN (uint32_t)1 /!< MSI Range is provided by MSIRANGE /
Kojto	122:f9eeca106725	912	/**
Kojto	122:f9eeca106725	913	* @}
Kojto	122:f9eeca106725	914	*/
Kojto	122:f9eeca106725	915
Kojto	122:f9eeca106725	916	/** Legacy definitions for compatibility purpose
Kojto	122:f9eeca106725	917	@cond 0
Kojto	122:f9eeca106725	918	*/
Kojto	122:f9eeca106725	919	#if defined(DFSDM1_Channel0)
Kojto	122:f9eeca106725	920	#define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK
Kojto	122:f9eeca106725	921	#define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	922	#define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE
Kojto	122:f9eeca106725	923	#endif /* DFSDM1_Channel0 */
Kojto	122:f9eeca106725	924	/**
Kojto	122:f9eeca106725	925	@endcond
Kojto	122:f9eeca106725	926	*/
Kojto	122:f9eeca106725	927
Kojto	122:f9eeca106725	928	/**
Kojto	122:f9eeca106725	929	* @}
Kojto	122:f9eeca106725	930	*/
Kojto	122:f9eeca106725	931
Kojto	122:f9eeca106725	932	/* Exported macro ------------------------------------------------------------*/
Kojto	122:f9eeca106725	933	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
Kojto	122:f9eeca106725	934	* @{
Kojto	122:f9eeca106725	935	*/
Kojto	122:f9eeca106725	936
Kojto	122:f9eeca106725	937	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
Kojto	122:f9eeca106725	938	* @{
Kojto	122:f9eeca106725	939	*/
Kojto	122:f9eeca106725	940
Kojto	122:f9eeca106725	941	/**
Kojto	122:f9eeca106725	942	* @brief Write a value in RCC register
Kojto	122:f9eeca106725	943	* @param __REG__ Register to be written
Kojto	122:f9eeca106725	944	* @param __VALUE__ Value to be written in the register
Kojto	122:f9eeca106725	945	* @retval None
Kojto	122:f9eeca106725	946	*/
Kojto	122:f9eeca106725	947	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
Kojto	122:f9eeca106725	948
Kojto	122:f9eeca106725	949	/**
Kojto	122:f9eeca106725	950	* @brief Read a value in RCC register
Kojto	122:f9eeca106725	951	* @param __REG__ Register to be read
Kojto	122:f9eeca106725	952	* @retval Register value
Kojto	122:f9eeca106725	953	*/
Kojto	122:f9eeca106725	954	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Kojto	122:f9eeca106725	955	/**
Kojto	122:f9eeca106725	956	* @}
Kojto	122:f9eeca106725	957	*/
Kojto	122:f9eeca106725	958
Kojto	122:f9eeca106725	959	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
Kojto	122:f9eeca106725	960	* @{
Kojto	122:f9eeca106725	961	*/
Kojto	122:f9eeca106725	962
Kojto	122:f9eeca106725	963	/**
Kojto	122:f9eeca106725	964	* @brief Helper macro to calculate the PLLCLK frequency on system domain
Kojto	122:f9eeca106725	965	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	966	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
Kojto	122:f9eeca106725	967	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	968	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	969	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	970	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	971	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	972	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	973	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	974	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	975	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	976	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	977	* @param __PLLN__ Between 8 and 86
Kojto	122:f9eeca106725	978	* @param __PLLR__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	979	* @arg @ref LL_RCC_PLLR_DIV_2
Kojto	122:f9eeca106725	980	* @arg @ref LL_RCC_PLLR_DIV_4
Kojto	122:f9eeca106725	981	* @arg @ref LL_RCC_PLLR_DIV_6
Kojto	122:f9eeca106725	982	* @arg @ref LL_RCC_PLLR_DIV_8
Kojto	122:f9eeca106725	983	* @retval PLL clock frequency (in Hz)
Kojto	122:f9eeca106725	984	*/
Kojto	122:f9eeca106725	985	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
Kojto	122:f9eeca106725	986	((((__PLLR__) >> RCC_POSITION_PLLR ) + 1 ) * 2))
Kojto	122:f9eeca106725	987
Kojto	122:f9eeca106725	988	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	989	/**
Kojto	122:f9eeca106725	990	* @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
Kojto	122:f9eeca106725	991	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	992	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
Kojto	122:f9eeca106725	993	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	994	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	995	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	996	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	997	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	998	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	999	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1000	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1001	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1002	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1003	* @param __PLLN__ Between 8 and 86
Kojto	122:f9eeca106725	1004	* @param __PLLP__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1005	* @arg @ref LL_RCC_PLLP_DIV_2
Kojto	122:f9eeca106725	1006	* @arg @ref LL_RCC_PLLP_DIV_3
Kojto	122:f9eeca106725	1007	* @arg @ref LL_RCC_PLLP_DIV_4
Kojto	122:f9eeca106725	1008	* @arg @ref LL_RCC_PLLP_DIV_5
Kojto	122:f9eeca106725	1009	* @arg @ref LL_RCC_PLLP_DIV_6
Kojto	122:f9eeca106725	1010	* @arg @ref LL_RCC_PLLP_DIV_7
Kojto	122:f9eeca106725	1011	* @arg @ref LL_RCC_PLLP_DIV_8
Kojto	122:f9eeca106725	1012	* @arg @ref LL_RCC_PLLP_DIV_9
Kojto	122:f9eeca106725	1013	* @arg @ref LL_RCC_PLLP_DIV_10
Kojto	122:f9eeca106725	1014	* @arg @ref LL_RCC_PLLP_DIV_11
Kojto	122:f9eeca106725	1015	* @arg @ref LL_RCC_PLLP_DIV_12
Kojto	122:f9eeca106725	1016	* @arg @ref LL_RCC_PLLP_DIV_13
Kojto	122:f9eeca106725	1017	* @arg @ref LL_RCC_PLLP_DIV_14
Kojto	122:f9eeca106725	1018	* @arg @ref LL_RCC_PLLP_DIV_15
Kojto	122:f9eeca106725	1019	* @arg @ref LL_RCC_PLLP_DIV_16
Kojto	122:f9eeca106725	1020	* @arg @ref LL_RCC_PLLP_DIV_17
Kojto	122:f9eeca106725	1021	* @arg @ref LL_RCC_PLLP_DIV_18
Kojto	122:f9eeca106725	1022	* @arg @ref LL_RCC_PLLP_DIV_19
Kojto	122:f9eeca106725	1023	* @arg @ref LL_RCC_PLLP_DIV_20
Kojto	122:f9eeca106725	1024	* @arg @ref LL_RCC_PLLP_DIV_21
Kojto	122:f9eeca106725	1025	* @arg @ref LL_RCC_PLLP_DIV_22
Kojto	122:f9eeca106725	1026	* @arg @ref LL_RCC_PLLP_DIV_23
Kojto	122:f9eeca106725	1027	* @arg @ref LL_RCC_PLLP_DIV_24
Kojto	122:f9eeca106725	1028	* @arg @ref LL_RCC_PLLP_DIV_25
Kojto	122:f9eeca106725	1029	* @arg @ref LL_RCC_PLLP_DIV_26
Kojto	122:f9eeca106725	1030	* @arg @ref LL_RCC_PLLP_DIV_27
Kojto	122:f9eeca106725	1031	* @arg @ref LL_RCC_PLLP_DIV_28
Kojto	122:f9eeca106725	1032	* @arg @ref LL_RCC_PLLP_DIV_29
Kojto	122:f9eeca106725	1033	* @arg @ref LL_RCC_PLLP_DIV_30
Kojto	122:f9eeca106725	1034	* @arg @ref LL_RCC_PLLP_DIV_31
Kojto	122:f9eeca106725	1035	* @retval PLL clock frequency (in Hz)
Kojto	122:f9eeca106725	1036	*/
Kojto	122:f9eeca106725	1037	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
Kojto	122:f9eeca106725	1038	((__PLLP__) >> RCC_POSITION_PLLP))
Kojto	122:f9eeca106725	1039
Kojto	122:f9eeca106725	1040	#else
Kojto	122:f9eeca106725	1041	/**
Kojto	122:f9eeca106725	1042	* @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
Kojto	122:f9eeca106725	1043	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1044	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
Kojto	122:f9eeca106725	1045	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1046	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1047	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1048	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1049	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1050	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1051	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1052	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1053	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1054	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1055	* @param __PLLN__ Between 8 and 86
Kojto	122:f9eeca106725	1056	* @param __PLLP__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1057	* @arg @ref LL_RCC_PLLP_DIV_7
Kojto	122:f9eeca106725	1058	* @arg @ref LL_RCC_PLLP_DIV_17
Kojto	122:f9eeca106725	1059	* @retval PLL clock frequency (in Hz)
Kojto	122:f9eeca106725	1060	*/
Kojto	122:f9eeca106725	1061	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
Kojto	122:f9eeca106725	1062	(((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7 : 17))
Kojto	122:f9eeca106725	1063
Kojto	122:f9eeca106725	1064	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	1065	/**
Kojto	122:f9eeca106725	1066	* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
Kojto	122:f9eeca106725	1067	* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1068	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
Kojto	122:f9eeca106725	1069	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1070	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1071	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1072	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1073	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1074	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1075	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1076	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1077	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1078	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1079	* @param __PLLN__ Between 8 and 86
Kojto	122:f9eeca106725	1080	* @param __PLLQ__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1081	* @arg @ref LL_RCC_PLLQ_DIV_2
Kojto	122:f9eeca106725	1082	* @arg @ref LL_RCC_PLLQ_DIV_4
Kojto	122:f9eeca106725	1083	* @arg @ref LL_RCC_PLLQ_DIV_6
Kojto	122:f9eeca106725	1084	* @arg @ref LL_RCC_PLLQ_DIV_8
Kojto	122:f9eeca106725	1085	* @retval PLL clock frequency (in Hz)
Kojto	122:f9eeca106725	1086	*/
Kojto	122:f9eeca106725	1087	#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
Kojto	122:f9eeca106725	1088	((((__PLLQ__) >> RCC_POSITION_PLLQ) + 1) << 1))
Kojto	122:f9eeca106725	1089
Kojto	122:f9eeca106725	1090	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	1091	/**
Kojto	122:f9eeca106725	1092	* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
Kojto	122:f9eeca106725	1093	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1094	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
Kojto	122:f9eeca106725	1095	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1096	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1097	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1098	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1099	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1100	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1101	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1102	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1103	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1104	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1105	* @param __PLLSAI1N__ Between 8 and 86
Kojto	122:f9eeca106725	1106	* @param __PLLSAI1P__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1107	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
Kojto	122:f9eeca106725	1108	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
Kojto	122:f9eeca106725	1109	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
Kojto	122:f9eeca106725	1110	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
Kojto	122:f9eeca106725	1111	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
Kojto	122:f9eeca106725	1112	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
Kojto	122:f9eeca106725	1113	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
Kojto	122:f9eeca106725	1114	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
Kojto	122:f9eeca106725	1115	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
Kojto	122:f9eeca106725	1116	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
Kojto	122:f9eeca106725	1117	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
Kojto	122:f9eeca106725	1118	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
Kojto	122:f9eeca106725	1119	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
Kojto	122:f9eeca106725	1120	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
Kojto	122:f9eeca106725	1121	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
Kojto	122:f9eeca106725	1122	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
Kojto	122:f9eeca106725	1123	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
Kojto	122:f9eeca106725	1124	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
Kojto	122:f9eeca106725	1125	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
Kojto	122:f9eeca106725	1126	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
Kojto	122:f9eeca106725	1127	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
Kojto	122:f9eeca106725	1128	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
Kojto	122:f9eeca106725	1129	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
Kojto	122:f9eeca106725	1130	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
Kojto	122:f9eeca106725	1131	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
Kojto	122:f9eeca106725	1132	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
Kojto	122:f9eeca106725	1133	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
Kojto	122:f9eeca106725	1134	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
Kojto	122:f9eeca106725	1135	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
Kojto	122:f9eeca106725	1136	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
Kojto	122:f9eeca106725	1137	* @retval PLLSAI1 clock frequency (in Hz)
Kojto	122:f9eeca106725	1138	*/
Kojto	122:f9eeca106725	1139	#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
Kojto	122:f9eeca106725	1140	((__PLLSAI1P__) >> RCC_POSITION_PLLSAI1P))
Kojto	122:f9eeca106725	1141	#else
Kojto	122:f9eeca106725	1142	/**
Kojto	122:f9eeca106725	1143	* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
Kojto	122:f9eeca106725	1144	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1145	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
Kojto	122:f9eeca106725	1146	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1147	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1148	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1149	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1150	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1151	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1152	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1153	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1154	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1155	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1156	* @param __PLLSAI1N__ Between 8 and 86
Kojto	122:f9eeca106725	1157	* @param __PLLSAI1P__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1158	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
Kojto	122:f9eeca106725	1159	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
Kojto	122:f9eeca106725	1160	* @retval PLLSAI1 clock frequency (in Hz)
Kojto	122:f9eeca106725	1161	*/
Kojto	122:f9eeca106725	1162	#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
Kojto	122:f9eeca106725	1163	(((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7 : 17))
Kojto	122:f9eeca106725	1164	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	1165
Kojto	122:f9eeca106725	1166	/**
Kojto	122:f9eeca106725	1167	* @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
Kojto	122:f9eeca106725	1168	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1169	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
Kojto	122:f9eeca106725	1170	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1171	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1172	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1173	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1174	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1175	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1176	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1177	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1178	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1179	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1180	* @param __PLLSAI1N__ Between 8 and 86
Kojto	122:f9eeca106725	1181	* @param __PLLSAI1Q__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1182	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
Kojto	122:f9eeca106725	1183	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
Kojto	122:f9eeca106725	1184	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
Kojto	122:f9eeca106725	1185	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
Kojto	122:f9eeca106725	1186	* @retval PLLSAI1 clock frequency (in Hz)
Kojto	122:f9eeca106725	1187	*/
Kojto	122:f9eeca106725	1188	#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
Kojto	122:f9eeca106725	1189	((((__PLLSAI1Q__) >> RCC_POSITION_PLLSAI1Q) + 1) << 1))
Kojto	122:f9eeca106725	1190
Kojto	122:f9eeca106725	1191	/**
Kojto	122:f9eeca106725	1192	* @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
Kojto	122:f9eeca106725	1193	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1194	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
Kojto	122:f9eeca106725	1195	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1196	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1197	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1198	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1199	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1200	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1201	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1202	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1203	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1204	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1205	* @param __PLLSAI1N__ Between 8 and 86
Kojto	122:f9eeca106725	1206	* @param __PLLSAI1R__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1207	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
Kojto	122:f9eeca106725	1208	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
Kojto	122:f9eeca106725	1209	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
Kojto	122:f9eeca106725	1210	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
Kojto	122:f9eeca106725	1211	* @retval PLLSAI1 clock frequency (in Hz)
Kojto	122:f9eeca106725	1212	*/
Kojto	122:f9eeca106725	1213	#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
Kojto	122:f9eeca106725	1214	((((__PLLSAI1R__) >> RCC_POSITION_PLLSAI1R ) + 1 ) * 2))
Kojto	122:f9eeca106725	1215
Kojto	122:f9eeca106725	1216	/**
Kojto	122:f9eeca106725	1217	* @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
Kojto	122:f9eeca106725	1218	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1219	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
Kojto	122:f9eeca106725	1220	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1221	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1222	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1223	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1224	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1225	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1226	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1227	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1228	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1229	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1230	* @param __PLLSAI2N__ Between 8 and 86
Kojto	122:f9eeca106725	1231	* @param __PLLSAI2P__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1232	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
Kojto	122:f9eeca106725	1233	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
Kojto	122:f9eeca106725	1234	* @retval PLLSAI2 clock frequency (in Hz)
Kojto	122:f9eeca106725	1235	*/
Kojto	122:f9eeca106725	1236	#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI2N__) / \
Kojto	122:f9eeca106725	1237	(((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7 : 17))
Kojto	122:f9eeca106725	1238
Kojto	122:f9eeca106725	1239	/**
Kojto	122:f9eeca106725	1240	* @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain
Kojto	122:f9eeca106725	1241	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1242	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ());
Kojto	122:f9eeca106725	1243	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1244	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1245	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1246	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1247	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1248	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1249	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1250	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1251	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1252	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1253	* @param __PLLSAI2N__ Between 8 and 86
Kojto	122:f9eeca106725	1254	* @param __PLLSAI2R__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1255	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
Kojto	122:f9eeca106725	1256	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
Kojto	122:f9eeca106725	1257	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
Kojto	122:f9eeca106725	1258	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
Kojto	122:f9eeca106725	1259	* @retval PLLSAI2 clock frequency (in Hz)
Kojto	122:f9eeca106725	1260	*/
Kojto	122:f9eeca106725	1261	#define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI2N__) / \
Kojto	122:f9eeca106725	1262	((((__PLLSAI2R__) >> RCC_POSITION_PLLSAI2R ) + 1 ) * 2))
Kojto	122:f9eeca106725	1263
Kojto	122:f9eeca106725	1264	/**
Kojto	122:f9eeca106725	1265	* @brief Helper macro to calculate the HCLK frequency
Kojto	122:f9eeca106725	1266	* @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
Kojto	122:f9eeca106725	1267	* @param __AHBPRESCALER__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1268	* @arg @ref LL_RCC_SYSCLK_DIV_1
Kojto	122:f9eeca106725	1269	* @arg @ref LL_RCC_SYSCLK_DIV_2
Kojto	122:f9eeca106725	1270	* @arg @ref LL_RCC_SYSCLK_DIV_4
Kojto	122:f9eeca106725	1271	* @arg @ref LL_RCC_SYSCLK_DIV_8
Kojto	122:f9eeca106725	1272	* @arg @ref LL_RCC_SYSCLK_DIV_16
Kojto	122:f9eeca106725	1273	* @arg @ref LL_RCC_SYSCLK_DIV_64
Kojto	122:f9eeca106725	1274	* @arg @ref LL_RCC_SYSCLK_DIV_128
Kojto	122:f9eeca106725	1275	* @arg @ref LL_RCC_SYSCLK_DIV_256
Kojto	122:f9eeca106725	1276	* @arg @ref LL_RCC_SYSCLK_DIV_512
Kojto	122:f9eeca106725	1277	* @retval HCLK clock frequency (in Hz)
Kojto	122:f9eeca106725	1278	*/
Kojto	122:f9eeca106725	1279	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE])
Kojto	122:f9eeca106725	1280
Kojto	122:f9eeca106725	1281	/**
Kojto	122:f9eeca106725	1282	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
Kojto	122:f9eeca106725	1283	* @param __HCLKFREQ__ HCLK frequency
Kojto	122:f9eeca106725	1284	* @param __APB1PRESCALER__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1285	* @arg @ref LL_RCC_APB1_DIV_1
Kojto	122:f9eeca106725	1286	* @arg @ref LL_RCC_APB1_DIV_2
Kojto	122:f9eeca106725	1287	* @arg @ref LL_RCC_APB1_DIV_4
Kojto	122:f9eeca106725	1288	* @arg @ref LL_RCC_APB1_DIV_8
Kojto	122:f9eeca106725	1289	* @arg @ref LL_RCC_APB1_DIV_16
Kojto	122:f9eeca106725	1290	* @retval PCLK1 clock frequency (in Hz)
Kojto	122:f9eeca106725	1291	*/
Kojto	122:f9eeca106725	1292	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1])
Kojto	122:f9eeca106725	1293
Kojto	122:f9eeca106725	1294	/**
Kojto	122:f9eeca106725	1295	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
Kojto	122:f9eeca106725	1296	* @param __HCLKFREQ__ HCLK frequency
Kojto	122:f9eeca106725	1297	* @param __APB2PRESCALER__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1298	* @arg @ref LL_RCC_APB2_DIV_1
Kojto	122:f9eeca106725	1299	* @arg @ref LL_RCC_APB2_DIV_2
Kojto	122:f9eeca106725	1300	* @arg @ref LL_RCC_APB2_DIV_4
Kojto	122:f9eeca106725	1301	* @arg @ref LL_RCC_APB2_DIV_8
Kojto	122:f9eeca106725	1302	* @arg @ref LL_RCC_APB2_DIV_16
Kojto	122:f9eeca106725	1303	* @retval PCLK2 clock frequency (in Hz)
Kojto	122:f9eeca106725	1304	*/
Kojto	122:f9eeca106725	1305	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2])
Kojto	122:f9eeca106725	1306
Kojto	122:f9eeca106725	1307	/**
Kojto	122:f9eeca106725	1308	* @brief Helper macro to calculate the MSI frequency (in Hz)
Kojto	122:f9eeca106725	1309	* @note: __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect
Kojto	122:f9eeca106725	1310	* @note: if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
Kojto	122:f9eeca106725	1311	* __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby
Kojto	122:f9eeca106725	1312	* else by LL_RCC_MSI_GetRange
Kojto	122:f9eeca106725	1313	* ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
Kojto	122:f9eeca106725	1314	* (LL_RCC_MSI_IsEnabledRangeSelect()?
Kojto	122:f9eeca106725	1315	* LL_RCC_MSI_GetRange():
Kojto	122:f9eeca106725	1316	* LL_RCC_MSI_GetRangeAfterStandby()))
Kojto	122:f9eeca106725	1317	* @param __MSISEL__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1318	* @arg @ref LL_RCC_MSIRANGESEL_STANDBY
Kojto	122:f9eeca106725	1319	* @arg @ref LL_RCC_MSIRANGESEL_RUN
Kojto	122:f9eeca106725	1320	* @param __MSIRANGE__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1321	* @arg @ref LL_RCC_MSIRANGE_0
Kojto	122:f9eeca106725	1322	* @arg @ref LL_RCC_MSIRANGE_1
Kojto	122:f9eeca106725	1323	* @arg @ref LL_RCC_MSIRANGE_2
Kojto	122:f9eeca106725	1324	* @arg @ref LL_RCC_MSIRANGE_3
Kojto	122:f9eeca106725	1325	* @arg @ref LL_RCC_MSIRANGE_4
Kojto	122:f9eeca106725	1326	* @arg @ref LL_RCC_MSIRANGE_5
Kojto	122:f9eeca106725	1327	* @arg @ref LL_RCC_MSIRANGE_6
Kojto	122:f9eeca106725	1328	* @arg @ref LL_RCC_MSIRANGE_7
Kojto	122:f9eeca106725	1329	* @arg @ref LL_RCC_MSIRANGE_8
Kojto	122:f9eeca106725	1330	* @arg @ref LL_RCC_MSIRANGE_9
Kojto	122:f9eeca106725	1331	* @arg @ref LL_RCC_MSIRANGE_10
Kojto	122:f9eeca106725	1332	* @arg @ref LL_RCC_MSIRANGE_11
Kojto	122:f9eeca106725	1333	* @arg @ref LL_RCC_MSISRANGE_4
Kojto	122:f9eeca106725	1334	* @arg @ref LL_RCC_MSISRANGE_5
Kojto	122:f9eeca106725	1335	* @arg @ref LL_RCC_MSISRANGE_6
Kojto	122:f9eeca106725	1336	* @arg @ref LL_RCC_MSISRANGE_7
Kojto	122:f9eeca106725	1337	* @retval MSI clock frequency (in Hz)
Kojto	122:f9eeca106725	1338	*/
Kojto	122:f9eeca106725	1339	#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
Kojto	122:f9eeca106725	1340	(MSIRangeTable[(__MSIRANGE__) >> 8]) : \
Kojto	122:f9eeca106725	1341	(MSIRangeTable[(__MSIRANGE__) >> 4]))
Kojto	122:f9eeca106725	1342
Kojto	122:f9eeca106725	1343	/**
Kojto	122:f9eeca106725	1344	* @}
Kojto	122:f9eeca106725	1345	*/
Kojto	122:f9eeca106725	1346
Kojto	122:f9eeca106725	1347	/**
Kojto	122:f9eeca106725	1348	* @}
Kojto	122:f9eeca106725	1349	*/
Kojto	122:f9eeca106725	1350
Kojto	122:f9eeca106725	1351	/* Exported functions --------------------------------------------------------*/
Kojto	122:f9eeca106725	1352	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
Kojto	122:f9eeca106725	1353	* @{
Kojto	122:f9eeca106725	1354	*/
Kojto	122:f9eeca106725	1355
Kojto	122:f9eeca106725	1356	/** @defgroup RCC_LL_EF_HSE HSE
Kojto	122:f9eeca106725	1357	* @{
Kojto	122:f9eeca106725	1358	*/
Kojto	122:f9eeca106725	1359
Kojto	122:f9eeca106725	1360	/**
Kojto	122:f9eeca106725	1361	* @brief Enable the Clock Security System.
Kojto	122:f9eeca106725	1362	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
Kojto	122:f9eeca106725	1363	* @retval None
Kojto	122:f9eeca106725	1364	*/
Kojto	122:f9eeca106725	1365	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
Kojto	122:f9eeca106725	1366	{
Kojto	122:f9eeca106725	1367	SET_BIT(RCC->CR, RCC_CR_CSSON);
Kojto	122:f9eeca106725	1368	}
Kojto	122:f9eeca106725	1369
Kojto	122:f9eeca106725	1370	/**
Kojto	122:f9eeca106725	1371	* @brief Enable HSE external oscillator (HSE Bypass)
Kojto	122:f9eeca106725	1372	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
Kojto	122:f9eeca106725	1373	* @retval None
Kojto	122:f9eeca106725	1374	*/
Kojto	122:f9eeca106725	1375	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
Kojto	122:f9eeca106725	1376	{
Kojto	122:f9eeca106725	1377	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
Kojto	122:f9eeca106725	1378	}
Kojto	122:f9eeca106725	1379
Kojto	122:f9eeca106725	1380	/**
Kojto	122:f9eeca106725	1381	* @brief Disable HSE external oscillator (HSE Bypass)
Kojto	122:f9eeca106725	1382	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
Kojto	122:f9eeca106725	1383	* @retval None
Kojto	122:f9eeca106725	1384	*/
Kojto	122:f9eeca106725	1385	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
Kojto	122:f9eeca106725	1386	{
Kojto	122:f9eeca106725	1387	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
Kojto	122:f9eeca106725	1388	}
Kojto	122:f9eeca106725	1389
Kojto	122:f9eeca106725	1390	/**
Kojto	122:f9eeca106725	1391	* @brief Enable HSE crystal oscillator (HSE ON)
Kojto	122:f9eeca106725	1392	* @rmtoll CR HSEON LL_RCC_HSE_Enable
Kojto	122:f9eeca106725	1393	* @retval None
Kojto	122:f9eeca106725	1394	*/
Kojto	122:f9eeca106725	1395	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
Kojto	122:f9eeca106725	1396	{
Kojto	122:f9eeca106725	1397	SET_BIT(RCC->CR, RCC_CR_HSEON);
Kojto	122:f9eeca106725	1398	}
Kojto	122:f9eeca106725	1399
Kojto	122:f9eeca106725	1400	/**
Kojto	122:f9eeca106725	1401	* @brief Disable HSE crystal oscillator (HSE ON)
Kojto	122:f9eeca106725	1402	* @rmtoll CR HSEON LL_RCC_HSE_Disable
Kojto	122:f9eeca106725	1403	* @retval None
Kojto	122:f9eeca106725	1404	*/
Kojto	122:f9eeca106725	1405	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
Kojto	122:f9eeca106725	1406	{
Kojto	122:f9eeca106725	1407	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
Kojto	122:f9eeca106725	1408	}
Kojto	122:f9eeca106725	1409
Kojto	122:f9eeca106725	1410	/**
Kojto	122:f9eeca106725	1411	* @brief Check if HSE oscillator Ready
Kojto	122:f9eeca106725	1412	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
Kojto	122:f9eeca106725	1413	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1414	*/
Kojto	122:f9eeca106725	1415	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
Kojto	122:f9eeca106725	1416	{
Kojto	122:f9eeca106725	1417	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
Kojto	122:f9eeca106725	1418	}
Kojto	122:f9eeca106725	1419
Kojto	122:f9eeca106725	1420	/**
Kojto	122:f9eeca106725	1421	* @}
Kojto	122:f9eeca106725	1422	*/
Kojto	122:f9eeca106725	1423
Kojto	122:f9eeca106725	1424	/** @defgroup RCC_LL_EF_HSI HSI
Kojto	122:f9eeca106725	1425	* @{
Kojto	122:f9eeca106725	1426	*/
Kojto	122:f9eeca106725	1427
Kojto	122:f9eeca106725	1428	/**
Kojto	122:f9eeca106725	1429	* @brief Enable HSI even in stop mode
Kojto	122:f9eeca106725	1430	* @note HSI oscillator is forced ON even in Stop mode
Kojto	122:f9eeca106725	1431	* @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
Kojto	122:f9eeca106725	1432	* @retval None
Kojto	122:f9eeca106725	1433	*/
Kojto	122:f9eeca106725	1434	__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
Kojto	122:f9eeca106725	1435	{
Kojto	122:f9eeca106725	1436	SET_BIT(RCC->CR, RCC_CR_HSIKERON);
Kojto	122:f9eeca106725	1437	}
Kojto	122:f9eeca106725	1438
Kojto	122:f9eeca106725	1439	/**
Kojto	122:f9eeca106725	1440	* @brief Disable HSI in stop mode
Kojto	122:f9eeca106725	1441	* @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
Kojto	122:f9eeca106725	1442	* @retval None
Kojto	122:f9eeca106725	1443	*/
Kojto	122:f9eeca106725	1444	__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
Kojto	122:f9eeca106725	1445	{
Kojto	122:f9eeca106725	1446	CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
Kojto	122:f9eeca106725	1447	}
Kojto	122:f9eeca106725	1448
Kojto	122:f9eeca106725	1449	/**
Kojto	122:f9eeca106725	1450	* @brief Enable HSI oscillator
Kojto	122:f9eeca106725	1451	* @rmtoll CR HSION LL_RCC_HSI_Enable
Kojto	122:f9eeca106725	1452	* @retval None
Kojto	122:f9eeca106725	1453	*/
Kojto	122:f9eeca106725	1454	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
Kojto	122:f9eeca106725	1455	{
Kojto	122:f9eeca106725	1456	SET_BIT(RCC->CR, RCC_CR_HSION);
Kojto	122:f9eeca106725	1457	}
Kojto	122:f9eeca106725	1458
Kojto	122:f9eeca106725	1459	/**
Kojto	122:f9eeca106725	1460	* @brief Disable HSI oscillator
Kojto	122:f9eeca106725	1461	* @rmtoll CR HSION LL_RCC_HSI_Disable
Kojto	122:f9eeca106725	1462	* @retval None
Kojto	122:f9eeca106725	1463	*/
Kojto	122:f9eeca106725	1464	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
Kojto	122:f9eeca106725	1465	{
Kojto	122:f9eeca106725	1466	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
Kojto	122:f9eeca106725	1467	}
Kojto	122:f9eeca106725	1468
Kojto	122:f9eeca106725	1469	/**
Kojto	122:f9eeca106725	1470	* @brief Check if HSI clock is ready
Kojto	122:f9eeca106725	1471	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
Kojto	122:f9eeca106725	1472	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1473	*/
Kojto	122:f9eeca106725	1474	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
Kojto	122:f9eeca106725	1475	{
Kojto	122:f9eeca106725	1476	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
Kojto	122:f9eeca106725	1477	}
Kojto	122:f9eeca106725	1478
Kojto	122:f9eeca106725	1479	/**
Kojto	122:f9eeca106725	1480	* @brief Enable HSI Automatic from stop mode
Kojto	122:f9eeca106725	1481	* @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
Kojto	122:f9eeca106725	1482	* @retval None
Kojto	122:f9eeca106725	1483	*/
Kojto	122:f9eeca106725	1484	__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
Kojto	122:f9eeca106725	1485	{
Kojto	122:f9eeca106725	1486	SET_BIT(RCC->CR, RCC_CR_HSIASFS);
Kojto	122:f9eeca106725	1487	}
Kojto	122:f9eeca106725	1488
Kojto	122:f9eeca106725	1489	/**
Kojto	122:f9eeca106725	1490	* @brief Disable HSI Automatic from stop mode
Kojto	122:f9eeca106725	1491	* @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
Kojto	122:f9eeca106725	1492	* @retval None
Kojto	122:f9eeca106725	1493	*/
Kojto	122:f9eeca106725	1494	__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
Kojto	122:f9eeca106725	1495	{
Kojto	122:f9eeca106725	1496	CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
Kojto	122:f9eeca106725	1497	}
Kojto	122:f9eeca106725	1498	/**
Kojto	122:f9eeca106725	1499	* @brief Get HSI Calibration value
Kojto	122:f9eeca106725	1500	* @note When HSITRIM is written, HSICAL is updated with the sum of
Kojto	122:f9eeca106725	1501	* HSITRIM and the factory trim value
Kojto	122:f9eeca106725	1502	* @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
Kojto	122:f9eeca106725	1503	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
Kojto	122:f9eeca106725	1504	*/
Kojto	122:f9eeca106725	1505	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
Kojto	122:f9eeca106725	1506	{
Kojto	122:f9eeca106725	1507	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL);
Kojto	122:f9eeca106725	1508	}
Kojto	122:f9eeca106725	1509
Kojto	122:f9eeca106725	1510	/**
Kojto	122:f9eeca106725	1511	* @brief Set HSI Calibration trimming
Kojto	122:f9eeca106725	1512	* @note user-programmable trimming value that is added to the HSICAL
Kojto	122:f9eeca106725	1513	* @note Default value is 16, which, when added to the HSICAL value,
Kojto	122:f9eeca106725	1514	* should trim the HSI to 16 MHz +/- 1 %
Kojto	122:f9eeca106725	1515	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
Kojto	122:f9eeca106725	1516	* @param Value Between Min_Data = 0 and Max_Data = 31
Kojto	122:f9eeca106725	1517	* @retval None
Kojto	122:f9eeca106725	1518	*/
Kojto	122:f9eeca106725	1519	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
Kojto	122:f9eeca106725	1520	{
Kojto	122:f9eeca106725	1521	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM);
Kojto	122:f9eeca106725	1522	}
Kojto	122:f9eeca106725	1523
Kojto	122:f9eeca106725	1524	/**
Kojto	122:f9eeca106725	1525	* @brief Get HSI Calibration trimming
Kojto	122:f9eeca106725	1526	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
Kojto	122:f9eeca106725	1527	* @retval Between Min_Data = 0 and Max_Data = 31
Kojto	122:f9eeca106725	1528	*/
Kojto	122:f9eeca106725	1529	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
Kojto	122:f9eeca106725	1530	{
Kojto	122:f9eeca106725	1531	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM);
Kojto	122:f9eeca106725	1532	}
Kojto	122:f9eeca106725	1533
Kojto	122:f9eeca106725	1534	/**
Kojto	122:f9eeca106725	1535	* @}
Kojto	122:f9eeca106725	1536	*/
Kojto	122:f9eeca106725	1537
Kojto	122:f9eeca106725	1538	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	1539	/** @defgroup RCC_LL_EF_HSI48 HSI48
Kojto	122:f9eeca106725	1540	* @{
Kojto	122:f9eeca106725	1541	*/
Kojto	122:f9eeca106725	1542
Kojto	122:f9eeca106725	1543	/**
Kojto	122:f9eeca106725	1544	* @brief Enable HSI48
Kojto	122:f9eeca106725	1545	* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
Kojto	122:f9eeca106725	1546	* @retval None
Kojto	122:f9eeca106725	1547	*/
Kojto	122:f9eeca106725	1548	__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
Kojto	122:f9eeca106725	1549	{
Kojto	122:f9eeca106725	1550	SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
Kojto	122:f9eeca106725	1551	}
Kojto	122:f9eeca106725	1552
Kojto	122:f9eeca106725	1553	/**
Kojto	122:f9eeca106725	1554	* @brief Disable HSI48
Kojto	122:f9eeca106725	1555	* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
Kojto	122:f9eeca106725	1556	* @retval None
Kojto	122:f9eeca106725	1557	*/
Kojto	122:f9eeca106725	1558	__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
Kojto	122:f9eeca106725	1559	{
Kojto	122:f9eeca106725	1560	CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
Kojto	122:f9eeca106725	1561	}
Kojto	122:f9eeca106725	1562
Kojto	122:f9eeca106725	1563	/**
Kojto	122:f9eeca106725	1564	* @brief Check if HSI48 oscillator Ready
Kojto	122:f9eeca106725	1565	* @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
Kojto	122:f9eeca106725	1566	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1567	*/
Kojto	122:f9eeca106725	1568	__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
Kojto	122:f9eeca106725	1569	{
Kojto	122:f9eeca106725	1570	return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY));
Kojto	122:f9eeca106725	1571	}
Kojto	122:f9eeca106725	1572
Kojto	122:f9eeca106725	1573	/**
Kojto	122:f9eeca106725	1574	* @brief Get HSI48 Calibration value
Kojto	122:f9eeca106725	1575	* @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
Kojto	122:f9eeca106725	1576	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
Kojto	122:f9eeca106725	1577	*/
Kojto	122:f9eeca106725	1578	__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
Kojto	122:f9eeca106725	1579	{
Kojto	122:f9eeca106725	1580	return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_POSITION_HSI48CAL);
Kojto	122:f9eeca106725	1581	}
Kojto	122:f9eeca106725	1582
Kojto	122:f9eeca106725	1583	/**
Kojto	122:f9eeca106725	1584	* @}
Kojto	122:f9eeca106725	1585	*/
Kojto	122:f9eeca106725	1586	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	1587
Kojto	122:f9eeca106725	1588	/** @defgroup RCC_LL_EF_LSE LSE
Kojto	122:f9eeca106725	1589	* @{
Kojto	122:f9eeca106725	1590	*/
Kojto	122:f9eeca106725	1591
Kojto	122:f9eeca106725	1592	/**
Kojto	122:f9eeca106725	1593	* @brief Enable Low Speed External (LSE) crystal.
Kojto	122:f9eeca106725	1594	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
Kojto	122:f9eeca106725	1595	* @retval None
Kojto	122:f9eeca106725	1596	*/
Kojto	122:f9eeca106725	1597	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
Kojto	122:f9eeca106725	1598	{
Kojto	122:f9eeca106725	1599	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
Kojto	122:f9eeca106725	1600	}
Kojto	122:f9eeca106725	1601
Kojto	122:f9eeca106725	1602	/**
Kojto	122:f9eeca106725	1603	* @brief Disable Low Speed External (LSE) crystal.
Kojto	122:f9eeca106725	1604	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
Kojto	122:f9eeca106725	1605	* @retval None
Kojto	122:f9eeca106725	1606	*/
Kojto	122:f9eeca106725	1607	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
Kojto	122:f9eeca106725	1608	{
Kojto	122:f9eeca106725	1609	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
Kojto	122:f9eeca106725	1610	}
Kojto	122:f9eeca106725	1611
Kojto	122:f9eeca106725	1612	/**
Kojto	122:f9eeca106725	1613	* @brief Enable external clock source (LSE bypass).
Kojto	122:f9eeca106725	1614	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
Kojto	122:f9eeca106725	1615	* @retval None
Kojto	122:f9eeca106725	1616	*/
Kojto	122:f9eeca106725	1617	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
Kojto	122:f9eeca106725	1618	{
Kojto	122:f9eeca106725	1619	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
Kojto	122:f9eeca106725	1620	}
Kojto	122:f9eeca106725	1621
Kojto	122:f9eeca106725	1622	/**
Kojto	122:f9eeca106725	1623	* @brief Disable external clock source (LSE bypass).
Kojto	122:f9eeca106725	1624	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
Kojto	122:f9eeca106725	1625	* @retval None
Kojto	122:f9eeca106725	1626	*/
Kojto	122:f9eeca106725	1627	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
Kojto	122:f9eeca106725	1628	{
Kojto	122:f9eeca106725	1629	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
Kojto	122:f9eeca106725	1630	}
Kojto	122:f9eeca106725	1631
Kojto	122:f9eeca106725	1632	/**
Kojto	122:f9eeca106725	1633	* @brief Set LSE oscillator drive capability
Kojto	122:f9eeca106725	1634	* @note The oscillator is in Xtal mode when it is not in bypass mode.
Kojto	122:f9eeca106725	1635	* @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
Kojto	122:f9eeca106725	1636	* @param LSEDrive This parameter can be one of the following values:
Kojto	122:f9eeca106725	1637	* @arg @ref LL_RCC_LSEDRIVE_LOW
Kojto	122:f9eeca106725	1638	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
Kojto	122:f9eeca106725	1639	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
Kojto	122:f9eeca106725	1640	* @arg @ref LL_RCC_LSEDRIVE_HIGH
Kojto	122:f9eeca106725	1641	* @retval None
Kojto	122:f9eeca106725	1642	*/
Kojto	122:f9eeca106725	1643	__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
Kojto	122:f9eeca106725	1644	{
Kojto	122:f9eeca106725	1645	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
Kojto	122:f9eeca106725	1646	}
Kojto	122:f9eeca106725	1647
Kojto	122:f9eeca106725	1648	/**
Kojto	122:f9eeca106725	1649	* @brief Get LSE oscillator drive capability
Kojto	122:f9eeca106725	1650	* @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
Kojto	122:f9eeca106725	1651	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	1652	* @arg @ref LL_RCC_LSEDRIVE_LOW
Kojto	122:f9eeca106725	1653	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
Kojto	122:f9eeca106725	1654	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
Kojto	122:f9eeca106725	1655	* @arg @ref LL_RCC_LSEDRIVE_HIGH
Kojto	122:f9eeca106725	1656	*/
Kojto	122:f9eeca106725	1657	__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
Kojto	122:f9eeca106725	1658	{
Kojto	122:f9eeca106725	1659	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
Kojto	122:f9eeca106725	1660	}
Kojto	122:f9eeca106725	1661
Kojto	122:f9eeca106725	1662	/**
Kojto	122:f9eeca106725	1663	* @brief Enable Clock security system on LSE.
Kojto	122:f9eeca106725	1664	* @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
Kojto	122:f9eeca106725	1665	* @retval None
Kojto	122:f9eeca106725	1666	*/
Kojto	122:f9eeca106725	1667	__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
Kojto	122:f9eeca106725	1668	{
Kojto	122:f9eeca106725	1669	SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
Kojto	122:f9eeca106725	1670	}
Kojto	122:f9eeca106725	1671
Kojto	122:f9eeca106725	1672	/**
Kojto	122:f9eeca106725	1673	* @brief Disable Clock security system on LSE.
Kojto	122:f9eeca106725	1674	* @note Clock security system can be disabled only after a LSE
Kojto	122:f9eeca106725	1675	* failure detection. In that case it MUST be disabled by software.
Kojto	122:f9eeca106725	1676	* @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
Kojto	122:f9eeca106725	1677	* @retval None
Kojto	122:f9eeca106725	1678	*/
Kojto	122:f9eeca106725	1679	__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
Kojto	122:f9eeca106725	1680	{
Kojto	122:f9eeca106725	1681	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
Kojto	122:f9eeca106725	1682	}
Kojto	122:f9eeca106725	1683
Kojto	122:f9eeca106725	1684	/**
Kojto	122:f9eeca106725	1685	* @brief Check if LSE oscillator Ready
Kojto	122:f9eeca106725	1686	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
Kojto	122:f9eeca106725	1687	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1688	*/
Kojto	122:f9eeca106725	1689	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
Kojto	122:f9eeca106725	1690	{
Kojto	122:f9eeca106725	1691	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
Kojto	122:f9eeca106725	1692	}
Kojto	122:f9eeca106725	1693
Kojto	122:f9eeca106725	1694	/**
Kojto	122:f9eeca106725	1695	* @brief Check if CSS on LSE failure Detection
Kojto	122:f9eeca106725	1696	* @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
Kojto	122:f9eeca106725	1697	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1698	*/
Kojto	122:f9eeca106725	1699	__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
Kojto	122:f9eeca106725	1700	{
Kojto	122:f9eeca106725	1701	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD));
Kojto	122:f9eeca106725	1702	}
Kojto	122:f9eeca106725	1703
Kojto	122:f9eeca106725	1704	/**
Kojto	122:f9eeca106725	1705	* @}
Kojto	122:f9eeca106725	1706	*/
Kojto	122:f9eeca106725	1707
Kojto	122:f9eeca106725	1708	/** @defgroup RCC_LL_EF_LSI LSI
Kojto	122:f9eeca106725	1709	* @{
Kojto	122:f9eeca106725	1710	*/
Kojto	122:f9eeca106725	1711
Kojto	122:f9eeca106725	1712	/**
Kojto	122:f9eeca106725	1713	* @brief Enable LSI Oscillator
Kojto	122:f9eeca106725	1714	* @rmtoll CSR LSION LL_RCC_LSI_Enable
Kojto	122:f9eeca106725	1715	* @retval None
Kojto	122:f9eeca106725	1716	*/
Kojto	122:f9eeca106725	1717	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
Kojto	122:f9eeca106725	1718	{
Kojto	122:f9eeca106725	1719	SET_BIT(RCC->CSR, RCC_CSR_LSION);
Kojto	122:f9eeca106725	1720	}
Kojto	122:f9eeca106725	1721
Kojto	122:f9eeca106725	1722	/**
Kojto	122:f9eeca106725	1723	* @brief Disable LSI Oscillator
Kojto	122:f9eeca106725	1724	* @rmtoll CSR LSION LL_RCC_LSI_Disable
Kojto	122:f9eeca106725	1725	* @retval None
Kojto	122:f9eeca106725	1726	*/
Kojto	122:f9eeca106725	1727	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
Kojto	122:f9eeca106725	1728	{
Kojto	122:f9eeca106725	1729	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
Kojto	122:f9eeca106725	1730	}
Kojto	122:f9eeca106725	1731
Kojto	122:f9eeca106725	1732	/**
Kojto	122:f9eeca106725	1733	* @brief Check if LSI is Ready
Kojto	122:f9eeca106725	1734	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
Kojto	122:f9eeca106725	1735	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1736	*/
Kojto	122:f9eeca106725	1737	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
Kojto	122:f9eeca106725	1738	{
Kojto	122:f9eeca106725	1739	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
Kojto	122:f9eeca106725	1740	}
Kojto	122:f9eeca106725	1741
Kojto	122:f9eeca106725	1742	/**
Kojto	122:f9eeca106725	1743	* @}
Kojto	122:f9eeca106725	1744	*/
Kojto	122:f9eeca106725	1745
Kojto	122:f9eeca106725	1746	/** @defgroup RCC_LL_EF_MSI MSI
Kojto	122:f9eeca106725	1747	* @{
Kojto	122:f9eeca106725	1748	*/
Kojto	122:f9eeca106725	1749
Kojto	122:f9eeca106725	1750	/**
Kojto	122:f9eeca106725	1751	* @brief Enable MSI oscillator
Kojto	122:f9eeca106725	1752	* @rmtoll CR MSION LL_RCC_MSI_Enable
Kojto	122:f9eeca106725	1753	* @retval None
Kojto	122:f9eeca106725	1754	*/
Kojto	122:f9eeca106725	1755	__STATIC_INLINE void LL_RCC_MSI_Enable(void)
Kojto	122:f9eeca106725	1756	{
Kojto	122:f9eeca106725	1757	SET_BIT(RCC->CR, RCC_CR_MSION);
Kojto	122:f9eeca106725	1758	}
Kojto	122:f9eeca106725	1759
Kojto	122:f9eeca106725	1760	/**
Kojto	122:f9eeca106725	1761	* @brief Disable MSI oscillator
Kojto	122:f9eeca106725	1762	* @rmtoll CR MSION LL_RCC_MSI_Disable
Kojto	122:f9eeca106725	1763	* @retval None
Kojto	122:f9eeca106725	1764	*/
Kojto	122:f9eeca106725	1765	__STATIC_INLINE void LL_RCC_MSI_Disable(void)
Kojto	122:f9eeca106725	1766	{
Kojto	122:f9eeca106725	1767	CLEAR_BIT(RCC->CR, RCC_CR_MSION);
Kojto	122:f9eeca106725	1768	}
Kojto	122:f9eeca106725	1769
Kojto	122:f9eeca106725	1770	/**
Kojto	122:f9eeca106725	1771	* @brief Check if MSI oscillator Ready
Kojto	122:f9eeca106725	1772	* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
Kojto	122:f9eeca106725	1773	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1774	*/
Kojto	122:f9eeca106725	1775	__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
Kojto	122:f9eeca106725	1776	{
Kojto	122:f9eeca106725	1777	return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
Kojto	122:f9eeca106725	1778	}
Kojto	122:f9eeca106725	1779
Kojto	122:f9eeca106725	1780	/**
Kojto	122:f9eeca106725	1781	* @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
Kojto	122:f9eeca106725	1782	* @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
Kojto	122:f9eeca106725	1783	* and ready (LSERDY set by hardware)
Kojto	122:f9eeca106725	1784	* @note hardware protection to avoid enabling MSIPLLEN if LSE is not
Kojto	122:f9eeca106725	1785	* ready
Kojto	122:f9eeca106725	1786	* @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
Kojto	122:f9eeca106725	1787	* @retval None
Kojto	122:f9eeca106725	1788	*/
Kojto	122:f9eeca106725	1789	__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
Kojto	122:f9eeca106725	1790	{
Kojto	122:f9eeca106725	1791	SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
Kojto	122:f9eeca106725	1792	}
Kojto	122:f9eeca106725	1793
Kojto	122:f9eeca106725	1794	/**
Kojto	122:f9eeca106725	1795	* @brief Disable MSI-PLL mode
Kojto	122:f9eeca106725	1796	* @note cleared by hardware when LSE is disabled (LSEON = 0) or when
Kojto	122:f9eeca106725	1797	* the Clock Security System on LSE detects a LSE failure
Kojto	122:f9eeca106725	1798	* @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
Kojto	122:f9eeca106725	1799	* @retval None
Kojto	122:f9eeca106725	1800	*/
Kojto	122:f9eeca106725	1801	__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
Kojto	122:f9eeca106725	1802	{
Kojto	122:f9eeca106725	1803	CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
Kojto	122:f9eeca106725	1804	}
Kojto	122:f9eeca106725	1805
Kojto	122:f9eeca106725	1806	/**
Kojto	122:f9eeca106725	1807	* @brief Enable MSI clock range selection with MSIRANGE register
Kojto	122:f9eeca106725	1808	* @note Write 0 has no effect. After a standby or a reset
Kojto	122:f9eeca106725	1809	* MSIRGSEL is at 0 and the MSI range value is provided by
Kojto	122:f9eeca106725	1810	* MSISRANGE
Kojto	122:f9eeca106725	1811	* @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
Kojto	122:f9eeca106725	1812	* @retval None
Kojto	122:f9eeca106725	1813	*/
Kojto	122:f9eeca106725	1814	__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
Kojto	122:f9eeca106725	1815	{
Kojto	122:f9eeca106725	1816	SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
Kojto	122:f9eeca106725	1817	}
Kojto	122:f9eeca106725	1818
Kojto	122:f9eeca106725	1819	/**
Kojto	122:f9eeca106725	1820	* @brief Check if MSI clock range is selected with MSIRANGE register
Kojto	122:f9eeca106725	1821	* @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
Kojto	122:f9eeca106725	1822	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1823	*/
Kojto	122:f9eeca106725	1824	__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
Kojto	122:f9eeca106725	1825	{
Kojto	122:f9eeca106725	1826	return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL));
Kojto	122:f9eeca106725	1827	}
Kojto	122:f9eeca106725	1828
Kojto	122:f9eeca106725	1829	/**
Kojto	122:f9eeca106725	1830	* @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
Kojto	122:f9eeca106725	1831	* @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
Kojto	122:f9eeca106725	1832	* @param Range This parameter can be one of the following values:
Kojto	122:f9eeca106725	1833	* @arg @ref LL_RCC_MSIRANGE_0
Kojto	122:f9eeca106725	1834	* @arg @ref LL_RCC_MSIRANGE_1
Kojto	122:f9eeca106725	1835	* @arg @ref LL_RCC_MSIRANGE_2
Kojto	122:f9eeca106725	1836	* @arg @ref LL_RCC_MSIRANGE_3
Kojto	122:f9eeca106725	1837	* @arg @ref LL_RCC_MSIRANGE_4
Kojto	122:f9eeca106725	1838	* @arg @ref LL_RCC_MSIRANGE_5
Kojto	122:f9eeca106725	1839	* @arg @ref LL_RCC_MSIRANGE_6
Kojto	122:f9eeca106725	1840	* @arg @ref LL_RCC_MSIRANGE_7
Kojto	122:f9eeca106725	1841	* @arg @ref LL_RCC_MSIRANGE_8
Kojto	122:f9eeca106725	1842	* @arg @ref LL_RCC_MSIRANGE_9
Kojto	122:f9eeca106725	1843	* @arg @ref LL_RCC_MSIRANGE_10
Kojto	122:f9eeca106725	1844	* @arg @ref LL_RCC_MSIRANGE_11
Kojto	122:f9eeca106725	1845	* @retval None
Kojto	122:f9eeca106725	1846	*/
Kojto	122:f9eeca106725	1847	__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
Kojto	122:f9eeca106725	1848	{
Kojto	122:f9eeca106725	1849	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
Kojto	122:f9eeca106725	1850	}
Kojto	122:f9eeca106725	1851
Kojto	122:f9eeca106725	1852	/**
Kojto	122:f9eeca106725	1853	* @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
Kojto	122:f9eeca106725	1854	* @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
Kojto	122:f9eeca106725	1855	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	1856	* @arg @ref LL_RCC_MSIRANGE_0
Kojto	122:f9eeca106725	1857	* @arg @ref LL_RCC_MSIRANGE_1
Kojto	122:f9eeca106725	1858	* @arg @ref LL_RCC_MSIRANGE_2
Kojto	122:f9eeca106725	1859	* @arg @ref LL_RCC_MSIRANGE_3
Kojto	122:f9eeca106725	1860	* @arg @ref LL_RCC_MSIRANGE_4
Kojto	122:f9eeca106725	1861	* @arg @ref LL_RCC_MSIRANGE_5
Kojto	122:f9eeca106725	1862	* @arg @ref LL_RCC_MSIRANGE_6
Kojto	122:f9eeca106725	1863	* @arg @ref LL_RCC_MSIRANGE_7
Kojto	122:f9eeca106725	1864	* @arg @ref LL_RCC_MSIRANGE_8
Kojto	122:f9eeca106725	1865	* @arg @ref LL_RCC_MSIRANGE_9
Kojto	122:f9eeca106725	1866	* @arg @ref LL_RCC_MSIRANGE_10
Kojto	122:f9eeca106725	1867	* @arg @ref LL_RCC_MSIRANGE_11
Kojto	122:f9eeca106725	1868	*/
Kojto	122:f9eeca106725	1869	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
Kojto	122:f9eeca106725	1870	{
Kojto	122:f9eeca106725	1871	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
Kojto	122:f9eeca106725	1872	}
Kojto	122:f9eeca106725	1873
Kojto	122:f9eeca106725	1874	/**
Kojto	122:f9eeca106725	1875	* @brief Configure MSI range used after standby
Kojto	122:f9eeca106725	1876	* @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby
Kojto	122:f9eeca106725	1877	* @param Range This parameter can be one of the following values:
Kojto	122:f9eeca106725	1878	* @arg @ref LL_RCC_MSISRANGE_4
Kojto	122:f9eeca106725	1879	* @arg @ref LL_RCC_MSISRANGE_5
Kojto	122:f9eeca106725	1880	* @arg @ref LL_RCC_MSISRANGE_6
Kojto	122:f9eeca106725	1881	* @arg @ref LL_RCC_MSISRANGE_7
Kojto	122:f9eeca106725	1882	* @retval None
Kojto	122:f9eeca106725	1883	*/
Kojto	122:f9eeca106725	1884	__STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
Kojto	122:f9eeca106725	1885	{
Kojto	122:f9eeca106725	1886	MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
Kojto	122:f9eeca106725	1887	}
Kojto	122:f9eeca106725	1888
Kojto	122:f9eeca106725	1889	/**
Kojto	122:f9eeca106725	1890	* @brief Get MSI range used after standby
Kojto	122:f9eeca106725	1891	* @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby
Kojto	122:f9eeca106725	1892	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	1893	* @arg @ref LL_RCC_MSISRANGE_4
Kojto	122:f9eeca106725	1894	* @arg @ref LL_RCC_MSISRANGE_5
Kojto	122:f9eeca106725	1895	* @arg @ref LL_RCC_MSISRANGE_6
Kojto	122:f9eeca106725	1896	* @arg @ref LL_RCC_MSISRANGE_7
Kojto	122:f9eeca106725	1897	*/
Kojto	122:f9eeca106725	1898	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
Kojto	122:f9eeca106725	1899	{
Kojto	122:f9eeca106725	1900	return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
Kojto	122:f9eeca106725	1901	}
Kojto	122:f9eeca106725	1902
Kojto	122:f9eeca106725	1903	/**
Kojto	122:f9eeca106725	1904	* @brief Get MSI Calibration value
Kojto	122:f9eeca106725	1905	* @note When MSITRIM is written, MSICAL is updated with the sum of
Kojto	122:f9eeca106725	1906	* MSITRIM and the factory trim value
Kojto	122:f9eeca106725	1907	* @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
Kojto	122:f9eeca106725	1908	* @retval Between Min_Data = 0 and Max_Data = 255
Kojto	122:f9eeca106725	1909	*/
Kojto	122:f9eeca106725	1910	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
Kojto	122:f9eeca106725	1911	{
Kojto	122:f9eeca106725	1912	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL);
Kojto	122:f9eeca106725	1913	}
Kojto	122:f9eeca106725	1914
Kojto	122:f9eeca106725	1915	/**
Kojto	122:f9eeca106725	1916	* @brief Set MSI Calibration trimming
Kojto	122:f9eeca106725	1917	* @note user-programmable trimming value that is added to the MSICAL
Kojto	122:f9eeca106725	1918	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
Kojto	122:f9eeca106725	1919	* @param Value Between Min_Data = 0 and Max_Data = 255
Kojto	122:f9eeca106725	1920	* @retval None
Kojto	122:f9eeca106725	1921	*/
Kojto	122:f9eeca106725	1922	__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
Kojto	122:f9eeca106725	1923	{
Kojto	122:f9eeca106725	1924	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM);
Kojto	122:f9eeca106725	1925	}
Kojto	122:f9eeca106725	1926
Kojto	122:f9eeca106725	1927	/**
Kojto	122:f9eeca106725	1928	* @brief Get MSI Calibration trimming
Kojto	122:f9eeca106725	1929	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
Kojto	122:f9eeca106725	1930	* @retval Between 0 and 255
Kojto	122:f9eeca106725	1931	*/
Kojto	122:f9eeca106725	1932	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
Kojto	122:f9eeca106725	1933	{
Kojto	122:f9eeca106725	1934	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM);
Kojto	122:f9eeca106725	1935	}
Kojto	122:f9eeca106725	1936
Kojto	122:f9eeca106725	1937	/**
Kojto	122:f9eeca106725	1938	* @}
Kojto	122:f9eeca106725	1939	*/
Kojto	122:f9eeca106725	1940
Kojto	122:f9eeca106725	1941	/** @defgroup RCC_LL_EF_LSCO LSCO
Kojto	122:f9eeca106725	1942	* @{
Kojto	122:f9eeca106725	1943	*/
Kojto	122:f9eeca106725	1944
Kojto	122:f9eeca106725	1945	/**
Kojto	122:f9eeca106725	1946	* @brief Enable Low speed clock
Kojto	122:f9eeca106725	1947	* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
Kojto	122:f9eeca106725	1948	* @retval None
Kojto	122:f9eeca106725	1949	*/
Kojto	122:f9eeca106725	1950	__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
Kojto	122:f9eeca106725	1951	{
Kojto	122:f9eeca106725	1952	SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
Kojto	122:f9eeca106725	1953	}
Kojto	122:f9eeca106725	1954
Kojto	122:f9eeca106725	1955	/**
Kojto	122:f9eeca106725	1956	* @brief Disable Low speed clock
Kojto	122:f9eeca106725	1957	* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
Kojto	122:f9eeca106725	1958	* @retval None
Kojto	122:f9eeca106725	1959	*/
Kojto	122:f9eeca106725	1960	__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
Kojto	122:f9eeca106725	1961	{
Kojto	122:f9eeca106725	1962	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
Kojto	122:f9eeca106725	1963	}
Kojto	122:f9eeca106725	1964
Kojto	122:f9eeca106725	1965	/**
Kojto	122:f9eeca106725	1966	* @brief Configure Low speed clock selection
Kojto	122:f9eeca106725	1967	* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
Kojto	122:f9eeca106725	1968	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	1969	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
Kojto	122:f9eeca106725	1970	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
Kojto	122:f9eeca106725	1971	* @retval None
Kojto	122:f9eeca106725	1972	*/
Kojto	122:f9eeca106725	1973	__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
Kojto	122:f9eeca106725	1974	{
Kojto	122:f9eeca106725	1975	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
Kojto	122:f9eeca106725	1976	}
Kojto	122:f9eeca106725	1977
Kojto	122:f9eeca106725	1978	/**
Kojto	122:f9eeca106725	1979	* @brief Get Low speed clock selection
Kojto	122:f9eeca106725	1980	* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
Kojto	122:f9eeca106725	1981	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	1982	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
Kojto	122:f9eeca106725	1983	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
Kojto	122:f9eeca106725	1984	*/
Kojto	122:f9eeca106725	1985	__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
Kojto	122:f9eeca106725	1986	{
Kojto	122:f9eeca106725	1987	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
Kojto	122:f9eeca106725	1988	}
Kojto	122:f9eeca106725	1989
Kojto	122:f9eeca106725	1990	/**
Kojto	122:f9eeca106725	1991	* @}
Kojto	122:f9eeca106725	1992	*/
Kojto	122:f9eeca106725	1993
Kojto	122:f9eeca106725	1994	/** @defgroup RCC_LL_EF_System System
Kojto	122:f9eeca106725	1995	* @{
Kojto	122:f9eeca106725	1996	*/
Kojto	122:f9eeca106725	1997
Kojto	122:f9eeca106725	1998	/**
Kojto	122:f9eeca106725	1999	* @brief Configure the system clock source
Kojto	122:f9eeca106725	2000	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
Kojto	122:f9eeca106725	2001	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	2002	* @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
Kojto	122:f9eeca106725	2003	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2004	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
Kojto	122:f9eeca106725	2005	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2006	* @retval None
Kojto	122:f9eeca106725	2007	*/
Kojto	122:f9eeca106725	2008	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
Kojto	122:f9eeca106725	2009	{
Kojto	122:f9eeca106725	2010	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
Kojto	122:f9eeca106725	2011	}
Kojto	122:f9eeca106725	2012
Kojto	122:f9eeca106725	2013	/**
Kojto	122:f9eeca106725	2014	* @brief Get the system clock source
Kojto	122:f9eeca106725	2015	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
Kojto	122:f9eeca106725	2016	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2017	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
Kojto	122:f9eeca106725	2018	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
Kojto	122:f9eeca106725	2019	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
Kojto	122:f9eeca106725	2020	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
Kojto	122:f9eeca106725	2021	*/
Kojto	122:f9eeca106725	2022	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
Kojto	122:f9eeca106725	2023	{
Kojto	122:f9eeca106725	2024	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
Kojto	122:f9eeca106725	2025	}
Kojto	122:f9eeca106725	2026
Kojto	122:f9eeca106725	2027	/**
Kojto	122:f9eeca106725	2028	* @brief Set AHB prescaler
Kojto	122:f9eeca106725	2029	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
Kojto	122:f9eeca106725	2030	* @param Prescaler This parameter can be one of the following values:
Kojto	122:f9eeca106725	2031	* @arg @ref LL_RCC_SYSCLK_DIV_1
Kojto	122:f9eeca106725	2032	* @arg @ref LL_RCC_SYSCLK_DIV_2
Kojto	122:f9eeca106725	2033	* @arg @ref LL_RCC_SYSCLK_DIV_4
Kojto	122:f9eeca106725	2034	* @arg @ref LL_RCC_SYSCLK_DIV_8
Kojto	122:f9eeca106725	2035	* @arg @ref LL_RCC_SYSCLK_DIV_16
Kojto	122:f9eeca106725	2036	* @arg @ref LL_RCC_SYSCLK_DIV_64
Kojto	122:f9eeca106725	2037	* @arg @ref LL_RCC_SYSCLK_DIV_128
Kojto	122:f9eeca106725	2038	* @arg @ref LL_RCC_SYSCLK_DIV_256
Kojto	122:f9eeca106725	2039	* @arg @ref LL_RCC_SYSCLK_DIV_512
Kojto	122:f9eeca106725	2040	* @retval None
Kojto	122:f9eeca106725	2041	*/
Kojto	122:f9eeca106725	2042	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
Kojto	122:f9eeca106725	2043	{
Kojto	122:f9eeca106725	2044	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
Kojto	122:f9eeca106725	2045	}
Kojto	122:f9eeca106725	2046
Kojto	122:f9eeca106725	2047	/**
Kojto	122:f9eeca106725	2048	* @brief Set APB1 prescaler
Kojto	122:f9eeca106725	2049	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
Kojto	122:f9eeca106725	2050	* @param Prescaler This parameter can be one of the following values:
Kojto	122:f9eeca106725	2051	* @arg @ref LL_RCC_APB1_DIV_1
Kojto	122:f9eeca106725	2052	* @arg @ref LL_RCC_APB1_DIV_2
Kojto	122:f9eeca106725	2053	* @arg @ref LL_RCC_APB1_DIV_4
Kojto	122:f9eeca106725	2054	* @arg @ref LL_RCC_APB1_DIV_8
Kojto	122:f9eeca106725	2055	* @arg @ref LL_RCC_APB1_DIV_16
Kojto	122:f9eeca106725	2056	* @retval None
Kojto	122:f9eeca106725	2057	*/
Kojto	122:f9eeca106725	2058	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
Kojto	122:f9eeca106725	2059	{
Kojto	122:f9eeca106725	2060	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
Kojto	122:f9eeca106725	2061	}
Kojto	122:f9eeca106725	2062
Kojto	122:f9eeca106725	2063	/**
Kojto	122:f9eeca106725	2064	* @brief Set APB2 prescaler
Kojto	122:f9eeca106725	2065	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
Kojto	122:f9eeca106725	2066	* @param Prescaler This parameter can be one of the following values:
Kojto	122:f9eeca106725	2067	* @arg @ref LL_RCC_APB2_DIV_1
Kojto	122:f9eeca106725	2068	* @arg @ref LL_RCC_APB2_DIV_2
Kojto	122:f9eeca106725	2069	* @arg @ref LL_RCC_APB2_DIV_4
Kojto	122:f9eeca106725	2070	* @arg @ref LL_RCC_APB2_DIV_8
Kojto	122:f9eeca106725	2071	* @arg @ref LL_RCC_APB2_DIV_16
Kojto	122:f9eeca106725	2072	* @retval None
Kojto	122:f9eeca106725	2073	*/
Kojto	122:f9eeca106725	2074	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
Kojto	122:f9eeca106725	2075	{
Kojto	122:f9eeca106725	2076	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
Kojto	122:f9eeca106725	2077	}
Kojto	122:f9eeca106725	2078
Kojto	122:f9eeca106725	2079	/**
Kojto	122:f9eeca106725	2080	* @brief Get AHB prescaler
Kojto	122:f9eeca106725	2081	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
Kojto	122:f9eeca106725	2082	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2083	* @arg @ref LL_RCC_SYSCLK_DIV_1
Kojto	122:f9eeca106725	2084	* @arg @ref LL_RCC_SYSCLK_DIV_2
Kojto	122:f9eeca106725	2085	* @arg @ref LL_RCC_SYSCLK_DIV_4
Kojto	122:f9eeca106725	2086	* @arg @ref LL_RCC_SYSCLK_DIV_8
Kojto	122:f9eeca106725	2087	* @arg @ref LL_RCC_SYSCLK_DIV_16
Kojto	122:f9eeca106725	2088	* @arg @ref LL_RCC_SYSCLK_DIV_64
Kojto	122:f9eeca106725	2089	* @arg @ref LL_RCC_SYSCLK_DIV_128
Kojto	122:f9eeca106725	2090	* @arg @ref LL_RCC_SYSCLK_DIV_256
Kojto	122:f9eeca106725	2091	* @arg @ref LL_RCC_SYSCLK_DIV_512
Kojto	122:f9eeca106725	2092	*/
Kojto	122:f9eeca106725	2093	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
Kojto	122:f9eeca106725	2094	{
Kojto	122:f9eeca106725	2095	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
Kojto	122:f9eeca106725	2096	}
Kojto	122:f9eeca106725	2097
Kojto	122:f9eeca106725	2098	/**
Kojto	122:f9eeca106725	2099	* @brief Get APB1 prescaler
Kojto	122:f9eeca106725	2100	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
Kojto	122:f9eeca106725	2101	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2102	* @arg @ref LL_RCC_APB1_DIV_1
Kojto	122:f9eeca106725	2103	* @arg @ref LL_RCC_APB1_DIV_2
Kojto	122:f9eeca106725	2104	* @arg @ref LL_RCC_APB1_DIV_4
Kojto	122:f9eeca106725	2105	* @arg @ref LL_RCC_APB1_DIV_8
Kojto	122:f9eeca106725	2106	* @arg @ref LL_RCC_APB1_DIV_16
Kojto	122:f9eeca106725	2107	*/
Kojto	122:f9eeca106725	2108	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
Kojto	122:f9eeca106725	2109	{
Kojto	122:f9eeca106725	2110	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
Kojto	122:f9eeca106725	2111	}
Kojto	122:f9eeca106725	2112
Kojto	122:f9eeca106725	2113	/**
Kojto	122:f9eeca106725	2114	* @brief Get APB2 prescaler
Kojto	122:f9eeca106725	2115	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
Kojto	122:f9eeca106725	2116	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2117	* @arg @ref LL_RCC_APB2_DIV_1
Kojto	122:f9eeca106725	2118	* @arg @ref LL_RCC_APB2_DIV_2
Kojto	122:f9eeca106725	2119	* @arg @ref LL_RCC_APB2_DIV_4
Kojto	122:f9eeca106725	2120	* @arg @ref LL_RCC_APB2_DIV_8
Kojto	122:f9eeca106725	2121	* @arg @ref LL_RCC_APB2_DIV_16
Kojto	122:f9eeca106725	2122	*/
Kojto	122:f9eeca106725	2123	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
Kojto	122:f9eeca106725	2124	{
Kojto	122:f9eeca106725	2125	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
Kojto	122:f9eeca106725	2126	}
Kojto	122:f9eeca106725	2127
Kojto	122:f9eeca106725	2128
Kojto	122:f9eeca106725	2129	/**
Kojto	122:f9eeca106725	2130	* @brief Set Clock After Wake-Up From Stop mode
Kojto	122:f9eeca106725	2131	* @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
Kojto	122:f9eeca106725	2132	* @param Clock This parameter can be one of the following values:
Kojto	122:f9eeca106725	2133	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
Kojto	122:f9eeca106725	2134	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
Kojto	122:f9eeca106725	2135	* @retval None
Kojto	122:f9eeca106725	2136	*/
Kojto	122:f9eeca106725	2137	__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
Kojto	122:f9eeca106725	2138	{
Kojto	122:f9eeca106725	2139	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
Kojto	122:f9eeca106725	2140	}
Kojto	122:f9eeca106725	2141
Kojto	122:f9eeca106725	2142	/**
Kojto	122:f9eeca106725	2143	* @brief Get Clock After Wake-Up From Stop mode
Kojto	122:f9eeca106725	2144	* @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
Kojto	122:f9eeca106725	2145	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2146	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
Kojto	122:f9eeca106725	2147	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
Kojto	122:f9eeca106725	2148	*/
Kojto	122:f9eeca106725	2149	__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
Kojto	122:f9eeca106725	2150	{
Kojto	122:f9eeca106725	2151	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
Kojto	122:f9eeca106725	2152	}
Kojto	122:f9eeca106725	2153
Kojto	122:f9eeca106725	2154	/**
Kojto	122:f9eeca106725	2155	* @}
Kojto	122:f9eeca106725	2156	*/
Kojto	122:f9eeca106725	2157
Kojto	122:f9eeca106725	2158	/** @defgroup RCC_LL_EF_MCO MCO
Kojto	122:f9eeca106725	2159	* @{
Kojto	122:f9eeca106725	2160	*/
Kojto	122:f9eeca106725	2161
Kojto	122:f9eeca106725	2162	/**
Kojto	122:f9eeca106725	2163	* @brief Configure MCOx
Kojto	122:f9eeca106725	2164	* @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
Kojto	122:f9eeca106725	2165	* CFGR MCOPRE LL_RCC_ConfigMCO
Kojto	122:f9eeca106725	2166	* @param MCOxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2167	* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
Kojto	122:f9eeca106725	2168	* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
Kojto	122:f9eeca106725	2169	* @arg @ref LL_RCC_MCO1SOURCE_MSI
Kojto	122:f9eeca106725	2170	* @arg @ref LL_RCC_MCO1SOURCE_HSI
Kojto	122:f9eeca106725	2171	* @arg @ref LL_RCC_MCO1SOURCE_HSE
Kojto	122:f9eeca106725	2172	* @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
Kojto	122:f9eeca106725	2173	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
Kojto	122:f9eeca106725	2174	* @arg @ref LL_RCC_MCO1SOURCE_LSI
Kojto	122:f9eeca106725	2175	* @arg @ref LL_RCC_MCO1SOURCE_LSE
Kojto	122:f9eeca106725	2176	*
Kojto	122:f9eeca106725	2177	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2178	* @param MCOxPrescaler This parameter can be one of the following values:
Kojto	122:f9eeca106725	2179	* @arg @ref LL_RCC_MCO1_DIV_1
Kojto	122:f9eeca106725	2180	* @arg @ref LL_RCC_MCO1_DIV_2
Kojto	122:f9eeca106725	2181	* @arg @ref LL_RCC_MCO1_DIV_4
Kojto	122:f9eeca106725	2182	* @arg @ref LL_RCC_MCO1_DIV_8
Kojto	122:f9eeca106725	2183	* @arg @ref LL_RCC_MCO1_DIV_16
Kojto	122:f9eeca106725	2184	* @retval None
Kojto	122:f9eeca106725	2185	*/
Kojto	122:f9eeca106725	2186	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
Kojto	122:f9eeca106725	2187	{
Kojto	122:f9eeca106725	2188	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE, MCOxSource \| MCOxPrescaler);
Kojto	122:f9eeca106725	2189	}
Kojto	122:f9eeca106725	2190
Kojto	122:f9eeca106725	2191	/**
Kojto	122:f9eeca106725	2192	* @}
Kojto	122:f9eeca106725	2193	*/
Kojto	122:f9eeca106725	2194
Kojto	122:f9eeca106725	2195	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
Kojto	122:f9eeca106725	2196	* @{
Kojto	122:f9eeca106725	2197	*/
Kojto	122:f9eeca106725	2198
Kojto	122:f9eeca106725	2199	/**
Kojto	122:f9eeca106725	2200	* @brief Configure USARTx clock source
Kojto	122:f9eeca106725	2201	* @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
Kojto	122:f9eeca106725	2202	* @param USARTxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2203	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
Kojto	122:f9eeca106725	2204	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2205	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2206	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2207	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2208	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2209	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2210	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2211	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
Kojto	122:f9eeca106725	2212	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
Kojto	122:f9eeca106725	2213	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
Kojto	122:f9eeca106725	2214	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
Kojto	122:f9eeca106725	2215	*
Kojto	122:f9eeca106725	2216	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2217	* @retval None
Kojto	122:f9eeca106725	2218	*/
Kojto	122:f9eeca106725	2219	__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
Kojto	122:f9eeca106725	2220	{
Kojto	122:f9eeca106725	2221	MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF));
Kojto	122:f9eeca106725	2222	}
Kojto	122:f9eeca106725	2223
Kojto	122:f9eeca106725	2224	#if defined(UART4) \|\| defined(UART5)
Kojto	122:f9eeca106725	2225	/**
Kojto	122:f9eeca106725	2226	* @brief Configure UARTx clock source
Kojto	122:f9eeca106725	2227	* @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
Kojto	122:f9eeca106725	2228	* @param UARTxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2229	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2230	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2231	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2232	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2233	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2234	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2235	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2236	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2237	* @retval None
Kojto	122:f9eeca106725	2238	*/
Kojto	122:f9eeca106725	2239	__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
Kojto	122:f9eeca106725	2240	{
Kojto	122:f9eeca106725	2241	MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF));
Kojto	122:f9eeca106725	2242	}
Kojto	122:f9eeca106725	2243	#endif /* UART4 \|\| UART5 */
Kojto	122:f9eeca106725	2244
Kojto	122:f9eeca106725	2245	/**
Kojto	122:f9eeca106725	2246	* @brief Configure LPUART1x clock source
Kojto	122:f9eeca106725	2247	* @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
Kojto	122:f9eeca106725	2248	* @param LPUARTxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2249	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2250	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2251	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2252	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2253	* @retval None
Kojto	122:f9eeca106725	2254	*/
Kojto	122:f9eeca106725	2255	__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
Kojto	122:f9eeca106725	2256	{
Kojto	122:f9eeca106725	2257	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
Kojto	122:f9eeca106725	2258	}
Kojto	122:f9eeca106725	2259
Kojto	122:f9eeca106725	2260	/**
Kojto	122:f9eeca106725	2261	* @brief Configure I2Cx clock source
Kojto	122:f9eeca106725	2262	* @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
Kojto	122:f9eeca106725	2263	* @param I2CxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2264	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2265	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2266	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2267	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
Kojto	122:f9eeca106725	2268	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
Kojto	122:f9eeca106725	2269	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
Kojto	122:f9eeca106725	2270	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2271	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2272	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2273	*
Kojto	122:f9eeca106725	2274	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2275	* @retval None
Kojto	122:f9eeca106725	2276	*/
Kojto	122:f9eeca106725	2277	__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
Kojto	122:f9eeca106725	2278	{
Kojto	122:f9eeca106725	2279	MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000), ((I2CxSource << 4) & 0x000FF000));
Kojto	122:f9eeca106725	2280	}
Kojto	122:f9eeca106725	2281
Kojto	122:f9eeca106725	2282	/**
Kojto	122:f9eeca106725	2283	* @brief Configure LPTIMx clock source
Kojto	122:f9eeca106725	2284	* @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
Kojto	122:f9eeca106725	2285	* @param LPTIMxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2286	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2287	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
Kojto	122:f9eeca106725	2288	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2289	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2290	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2291	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
Kojto	122:f9eeca106725	2292	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2293	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2294	* @retval None
Kojto	122:f9eeca106725	2295	*/
Kojto	122:f9eeca106725	2296	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
Kojto	122:f9eeca106725	2297	{
Kojto	122:f9eeca106725	2298	MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16));
Kojto	122:f9eeca106725	2299	}
Kojto	122:f9eeca106725	2300
Kojto	122:f9eeca106725	2301	/**
Kojto	122:f9eeca106725	2302	* @brief Configure SAIx clock source
Kojto	122:f9eeca106725	2303	* @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource
Kojto	122:f9eeca106725	2304	* @param SAIxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2305	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2306	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
Kojto	122:f9eeca106725	2307	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2308	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
Kojto	122:f9eeca106725	2309	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
Kojto	122:f9eeca106725	2310	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
Kojto	122:f9eeca106725	2311	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
Kojto	122:f9eeca106725	2312	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
Kojto	122:f9eeca106725	2313	*
Kojto	122:f9eeca106725	2314	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2315	* @retval None
Kojto	122:f9eeca106725	2316	*/
Kojto	122:f9eeca106725	2317	__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
Kojto	122:f9eeca106725	2318	{
Kojto	122:f9eeca106725	2319	MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16));
Kojto	122:f9eeca106725	2320	}
Kojto	122:f9eeca106725	2321
Kojto	122:f9eeca106725	2322	/**
Kojto	122:f9eeca106725	2323	* @brief Configure SDMMC1 clock source
Kojto	122:f9eeca106725	2324	* @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource
Kojto	122:f9eeca106725	2325	* @param SDMMCxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2326	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2327	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2328	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2329	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
Kojto	122:f9eeca106725	2330	* @retval None
Kojto	122:f9eeca106725	2331	*/
Kojto	122:f9eeca106725	2332	__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
Kojto	122:f9eeca106725	2333	{
Kojto	122:f9eeca106725	2334	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
Kojto	122:f9eeca106725	2335	}
Kojto	122:f9eeca106725	2336
Kojto	122:f9eeca106725	2337	/**
Kojto	122:f9eeca106725	2338	* @brief Configure RNG clock source
Kojto	122:f9eeca106725	2339	* @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
Kojto	122:f9eeca106725	2340	* @param RNGxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2341	* @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2342	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2343	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2344	* @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
Kojto	122:f9eeca106725	2345	* @retval None
Kojto	122:f9eeca106725	2346	*/
Kojto	122:f9eeca106725	2347	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
Kojto	122:f9eeca106725	2348	{
Kojto	122:f9eeca106725	2349	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
Kojto	122:f9eeca106725	2350	}
Kojto	122:f9eeca106725	2351
Kojto	122:f9eeca106725	2352	#if defined(USB_OTG_FS) \|\| defined(USB)
Kojto	122:f9eeca106725	2353	/**
Kojto	122:f9eeca106725	2354	* @brief Configure USB clock source
Kojto	122:f9eeca106725	2355	* @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
Kojto	122:f9eeca106725	2356	* @param USBxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2357	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2358	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2359	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2360	* @arg @ref LL_RCC_USB_CLKSOURCE_MSI
Kojto	122:f9eeca106725	2361	* @retval None
Kojto	122:f9eeca106725	2362	*/
Kojto	122:f9eeca106725	2363	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
Kojto	122:f9eeca106725	2364	{
Kojto	122:f9eeca106725	2365	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
Kojto	122:f9eeca106725	2366	}
Kojto	122:f9eeca106725	2367	#endif /* USB_OTG_FS \|\| USB */
Kojto	122:f9eeca106725	2368
Kojto	122:f9eeca106725	2369	/**
Kojto	122:f9eeca106725	2370	* @brief Configure ADC clock source
Kojto	122:f9eeca106725	2371	* @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
Kojto	122:f9eeca106725	2372	* @param ADCxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2373	* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2374	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2375	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
Kojto	122:f9eeca106725	2376	* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2377	*
Kojto	122:f9eeca106725	2378	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2379	* @retval None
Kojto	122:f9eeca106725	2380	*/
Kojto	122:f9eeca106725	2381	__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
Kojto	122:f9eeca106725	2382	{
Kojto	122:f9eeca106725	2383	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
Kojto	122:f9eeca106725	2384	}
Kojto	122:f9eeca106725	2385
Kojto	122:f9eeca106725	2386	/**
Kojto	122:f9eeca106725	2387	* @brief Configure SWPMI clock source
Kojto	122:f9eeca106725	2388	* @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource
Kojto	122:f9eeca106725	2389	* @param SWPMIxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2390	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK
Kojto	122:f9eeca106725	2391	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2392	* @retval None
Kojto	122:f9eeca106725	2393	*/
Kojto	122:f9eeca106725	2394	__STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
Kojto	122:f9eeca106725	2395	{
Kojto	122:f9eeca106725	2396	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
Kojto	122:f9eeca106725	2397	}
Kojto	122:f9eeca106725	2398
Kojto	122:f9eeca106725	2399	#if defined(DFSDM1_Channel0)
Kojto	122:f9eeca106725	2400	/**
Kojto	122:f9eeca106725	2401	* @brief Configure DFSDM clock source
Kojto	122:f9eeca106725	2402	* @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource
Kojto	122:f9eeca106725	2403	* @param DFSDMxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2404	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK
Kojto	122:f9eeca106725	2405	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2406	* @retval None
Kojto	122:f9eeca106725	2407	*/
Kojto	122:f9eeca106725	2408	__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
Kojto	122:f9eeca106725	2409	{
Kojto	122:f9eeca106725	2410	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);
Kojto	122:f9eeca106725	2411	}
Kojto	122:f9eeca106725	2412	#endif /* DFSDM1_Channel0 */
Kojto	122:f9eeca106725	2413
Kojto	122:f9eeca106725	2414	/**
Kojto	122:f9eeca106725	2415	* @brief Get USARTx clock source
Kojto	122:f9eeca106725	2416	* @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
Kojto	122:f9eeca106725	2417	* @param USARTx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2418	* @arg @ref LL_RCC_USART1_CLKSOURCE
Kojto	122:f9eeca106725	2419	* @arg @ref LL_RCC_USART2_CLKSOURCE
Kojto	122:f9eeca106725	2420	* @arg @ref LL_RCC_USART3_CLKSOURCE (*)
Kojto	122:f9eeca106725	2421	*
Kojto	122:f9eeca106725	2422	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2423	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2424	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
Kojto	122:f9eeca106725	2425	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2426	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2427	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2428	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2429	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2430	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2431	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2432	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
Kojto	122:f9eeca106725	2433	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
Kojto	122:f9eeca106725	2434	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
Kojto	122:f9eeca106725	2435	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
Kojto	122:f9eeca106725	2436	*
Kojto	122:f9eeca106725	2437	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2438	*/
Kojto	122:f9eeca106725	2439	__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
Kojto	122:f9eeca106725	2440	{
Kojto	122:f9eeca106725	2441	return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) \| (USARTx << 16));
Kojto	122:f9eeca106725	2442	}
Kojto	122:f9eeca106725	2443
Kojto	122:f9eeca106725	2444	#if defined(UART4) \|\| defined(UART5)
Kojto	122:f9eeca106725	2445	/**
Kojto	122:f9eeca106725	2446	* @brief Get UARTx clock source
Kojto	122:f9eeca106725	2447	* @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
Kojto	122:f9eeca106725	2448	* @param UARTx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2449	* @arg @ref LL_RCC_UART4_CLKSOURCE
Kojto	122:f9eeca106725	2450	* @arg @ref LL_RCC_UART5_CLKSOURCE
Kojto	122:f9eeca106725	2451	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2452	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2453	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2454	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2455	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2456	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2457	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2458	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2459	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2460	*/
Kojto	122:f9eeca106725	2461	__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
Kojto	122:f9eeca106725	2462	{
Kojto	122:f9eeca106725	2463	return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) \| (UARTx << 16));
Kojto	122:f9eeca106725	2464	}
Kojto	122:f9eeca106725	2465	#endif /* UART4 \|\| UART5 */
Kojto	122:f9eeca106725	2466
Kojto	122:f9eeca106725	2467	/**
Kojto	122:f9eeca106725	2468	* @brief Get LPUARTx clock source
Kojto	122:f9eeca106725	2469	* @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
Kojto	122:f9eeca106725	2470	* @param LPUARTx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2471	* @arg @ref LL_RCC_LPUART1_CLKSOURCE
Kojto	122:f9eeca106725	2472	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2473	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2474	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2475	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2476	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2477	*/
Kojto	122:f9eeca106725	2478	__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
Kojto	122:f9eeca106725	2479	{
Kojto	122:f9eeca106725	2480	return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
Kojto	122:f9eeca106725	2481	}
Kojto	122:f9eeca106725	2482
Kojto	122:f9eeca106725	2483	/**
Kojto	122:f9eeca106725	2484	* @brief Get I2Cx clock source
Kojto	122:f9eeca106725	2485	* @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
Kojto	122:f9eeca106725	2486	* @param I2Cx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2487	* @arg @ref LL_RCC_I2C1_CLKSOURCE
Kojto	122:f9eeca106725	2488	* @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
Kojto	122:f9eeca106725	2489	* @arg @ref LL_RCC_I2C3_CLKSOURCE
Kojto	122:f9eeca106725	2490	*
Kojto	122:f9eeca106725	2491	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2492	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2493	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2494	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2495	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2496	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
Kojto	122:f9eeca106725	2497	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
Kojto	122:f9eeca106725	2498	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
Kojto	122:f9eeca106725	2499	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2500	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2501	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2502	*
Kojto	122:f9eeca106725	2503	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2504	*/
Kojto	122:f9eeca106725	2505	__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
Kojto	122:f9eeca106725	2506	{
Kojto	122:f9eeca106725	2507	return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4) \| (I2Cx << 4));
Kojto	122:f9eeca106725	2508	}
Kojto	122:f9eeca106725	2509
Kojto	122:f9eeca106725	2510	/**
Kojto	122:f9eeca106725	2511	* @brief Get LPTIMx clock source
Kojto	122:f9eeca106725	2512	* @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
Kojto	122:f9eeca106725	2513	* @param LPTIMx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2514	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
Kojto	122:f9eeca106725	2515	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE
Kojto	122:f9eeca106725	2516	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2517	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2518	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
Kojto	122:f9eeca106725	2519	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2520	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2521	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2522	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
Kojto	122:f9eeca106725	2523	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2524	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2525	*/
Kojto	122:f9eeca106725	2526	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
Kojto	122:f9eeca106725	2527	{
Kojto	122:f9eeca106725	2528	return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16 \| LPTIMx);
Kojto	122:f9eeca106725	2529	}
Kojto	122:f9eeca106725	2530
Kojto	122:f9eeca106725	2531	/**
Kojto	122:f9eeca106725	2532	* @brief Get SAIx clock source
Kojto	122:f9eeca106725	2533	* @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource
Kojto	122:f9eeca106725	2534	* @param SAIx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2535	* @arg @ref LL_RCC_SAI1_CLKSOURCE
Kojto	122:f9eeca106725	2536	* @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
Kojto	122:f9eeca106725	2537	*
Kojto	122:f9eeca106725	2538	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2539	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2540	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2541	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
Kojto	122:f9eeca106725	2542	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2543	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
Kojto	122:f9eeca106725	2544	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
Kojto	122:f9eeca106725	2545	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
Kojto	122:f9eeca106725	2546	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
Kojto	122:f9eeca106725	2547	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
Kojto	122:f9eeca106725	2548	*
Kojto	122:f9eeca106725	2549	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2550	*/
Kojto	122:f9eeca106725	2551	__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
Kojto	122:f9eeca106725	2552	{
Kojto	122:f9eeca106725	2553	return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16 \| SAIx);
Kojto	122:f9eeca106725	2554	}
Kojto	122:f9eeca106725	2555
Kojto	122:f9eeca106725	2556	/**
Kojto	122:f9eeca106725	2557	* @brief Get SDMMCx clock source
Kojto	122:f9eeca106725	2558	* @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource
Kojto	122:f9eeca106725	2559	* @param SDMMCx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2560	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE
Kojto	122:f9eeca106725	2561	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2562	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2563	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2564	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2565	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
Kojto	122:f9eeca106725	2566	*/
Kojto	122:f9eeca106725	2567	__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
Kojto	122:f9eeca106725	2568	{
Kojto	122:f9eeca106725	2569	return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
Kojto	122:f9eeca106725	2570	}
Kojto	122:f9eeca106725	2571
Kojto	122:f9eeca106725	2572	/**
Kojto	122:f9eeca106725	2573	* @brief Get RNGx clock source
Kojto	122:f9eeca106725	2574	* @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
Kojto	122:f9eeca106725	2575	* @param RNGx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2576	* @arg @ref LL_RCC_RNG_CLKSOURCE
Kojto	122:f9eeca106725	2577	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2578	* @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2579	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2580	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2581	* @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
Kojto	122:f9eeca106725	2582	*/
Kojto	122:f9eeca106725	2583	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
Kojto	122:f9eeca106725	2584	{
Kojto	122:f9eeca106725	2585	return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
Kojto	122:f9eeca106725	2586	}
Kojto	122:f9eeca106725	2587
Kojto	122:f9eeca106725	2588	#if defined(USB_OTG_FS) \|\| defined(USB)
Kojto	122:f9eeca106725	2589	/**
Kojto	122:f9eeca106725	2590	* @brief Get USBx clock source
Kojto	122:f9eeca106725	2591	* @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
Kojto	122:f9eeca106725	2592	* @param USBx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2593	* @arg @ref LL_RCC_USB_CLKSOURCE
Kojto	122:f9eeca106725	2594	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2595	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2596	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2597	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2598	* @arg @ref LL_RCC_USB_CLKSOURCE_MSI
Kojto	122:f9eeca106725	2599	*/
Kojto	122:f9eeca106725	2600	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
Kojto	122:f9eeca106725	2601	{
Kojto	122:f9eeca106725	2602	return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
Kojto	122:f9eeca106725	2603	}
Kojto	122:f9eeca106725	2604	#endif /* USB_OTG_FS \|\| USB */
Kojto	122:f9eeca106725	2605
Kojto	122:f9eeca106725	2606	/**
Kojto	122:f9eeca106725	2607	* @brief Get ADCx clock source
Kojto	122:f9eeca106725	2608	* @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
Kojto	122:f9eeca106725	2609	* @param ADCx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2610	* @arg @ref LL_RCC_ADC_CLKSOURCE
Kojto	122:f9eeca106725	2611	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2612	* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2613	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2614	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
Kojto	122:f9eeca106725	2615	* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2616	*
Kojto	122:f9eeca106725	2617	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2618	*/
Kojto	122:f9eeca106725	2619	__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
Kojto	122:f9eeca106725	2620	{
Kojto	122:f9eeca106725	2621	return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
Kojto	122:f9eeca106725	2622	}
Kojto	122:f9eeca106725	2623
Kojto	122:f9eeca106725	2624	/**
Kojto	122:f9eeca106725	2625	* @brief Get SWPMIx clock source
Kojto	122:f9eeca106725	2626	* @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource
Kojto	122:f9eeca106725	2627	* @param SPWMIx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2628	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE
Kojto	122:f9eeca106725	2629	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2630	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK
Kojto	122:f9eeca106725	2631	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2632	*/
Kojto	122:f9eeca106725	2633	__STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
Kojto	122:f9eeca106725	2634	{
Kojto	122:f9eeca106725	2635	return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
Kojto	122:f9eeca106725	2636	}
Kojto	122:f9eeca106725	2637
Kojto	122:f9eeca106725	2638	#if defined(DFSDM1_Channel0)
Kojto	122:f9eeca106725	2639	/**
Kojto	122:f9eeca106725	2640	* @brief Get DFSDMx clock source
Kojto	122:f9eeca106725	2641	* @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource
Kojto	122:f9eeca106725	2642	* @param DFSDMx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2643	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
Kojto	122:f9eeca106725	2644	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2645	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK
Kojto	122:f9eeca106725	2646	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2647	*/
Kojto	122:f9eeca106725	2648	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
Kojto	122:f9eeca106725	2649	{
Kojto	122:f9eeca106725	2650	return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
Kojto	122:f9eeca106725	2651	}
Kojto	122:f9eeca106725	2652	#endif /* DFSDM1_Channel0 */
Kojto	122:f9eeca106725	2653
Kojto	122:f9eeca106725	2654	/**
Kojto	122:f9eeca106725	2655	* @}
Kojto	122:f9eeca106725	2656	*/
Kojto	122:f9eeca106725	2657
Kojto	122:f9eeca106725	2658	/** @defgroup RCC_LL_EF_RTC RTC
Kojto	122:f9eeca106725	2659	* @{
Kojto	122:f9eeca106725	2660	*/
Kojto	122:f9eeca106725	2661
Kojto	122:f9eeca106725	2662	/**
Kojto	122:f9eeca106725	2663	* @brief Set RTC Clock Source
Kojto	122:f9eeca106725	2664	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
Kojto	122:f9eeca106725	2665	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
Kojto	122:f9eeca106725	2666	* set). The BDRST bit can be used to reset them.
Kojto	122:f9eeca106725	2667	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
Kojto	122:f9eeca106725	2668	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	2669	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2670	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2671	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
Kojto	122:f9eeca106725	2672	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
Kojto	122:f9eeca106725	2673	* @retval None
Kojto	122:f9eeca106725	2674	*/
Kojto	122:f9eeca106725	2675	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
Kojto	122:f9eeca106725	2676	{
Kojto	122:f9eeca106725	2677	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
Kojto	122:f9eeca106725	2678	}
Kojto	122:f9eeca106725	2679
Kojto	122:f9eeca106725	2680	/**
Kojto	122:f9eeca106725	2681	* @brief Get RTC Clock Source
Kojto	122:f9eeca106725	2682	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
Kojto	122:f9eeca106725	2683	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2684	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2685	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2686	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
Kojto	122:f9eeca106725	2687	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
Kojto	122:f9eeca106725	2688	*/
Kojto	122:f9eeca106725	2689	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
Kojto	122:f9eeca106725	2690	{
Kojto	122:f9eeca106725	2691	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
Kojto	122:f9eeca106725	2692	}
Kojto	122:f9eeca106725	2693
Kojto	122:f9eeca106725	2694	/**
Kojto	122:f9eeca106725	2695	* @brief Enable RTC
Kojto	122:f9eeca106725	2696	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
Kojto	122:f9eeca106725	2697	* @retval None
Kojto	122:f9eeca106725	2698	*/
Kojto	122:f9eeca106725	2699	__STATIC_INLINE void LL_RCC_EnableRTC(void)
Kojto	122:f9eeca106725	2700	{
Kojto	122:f9eeca106725	2701	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
Kojto	122:f9eeca106725	2702	}
Kojto	122:f9eeca106725	2703
Kojto	122:f9eeca106725	2704	/**
Kojto	122:f9eeca106725	2705	* @brief Disable RTC
Kojto	122:f9eeca106725	2706	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
Kojto	122:f9eeca106725	2707	* @retval None
Kojto	122:f9eeca106725	2708	*/
Kojto	122:f9eeca106725	2709	__STATIC_INLINE void LL_RCC_DisableRTC(void)
Kojto	122:f9eeca106725	2710	{
Kojto	122:f9eeca106725	2711	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
Kojto	122:f9eeca106725	2712	}
Kojto	122:f9eeca106725	2713
Kojto	122:f9eeca106725	2714	/**
Kojto	122:f9eeca106725	2715	* @brief Check if RTC has been enabled or not
Kojto	122:f9eeca106725	2716	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
Kojto	122:f9eeca106725	2717	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	2718	*/
Kojto	122:f9eeca106725	2719	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
Kojto	122:f9eeca106725	2720	{
Kojto	122:f9eeca106725	2721	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
Kojto	122:f9eeca106725	2722	}
Kojto	122:f9eeca106725	2723
Kojto	122:f9eeca106725	2724	/**
Kojto	122:f9eeca106725	2725	* @brief Force the Backup domain reset
Kojto	122:f9eeca106725	2726	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
Kojto	122:f9eeca106725	2727	* @retval None
Kojto	122:f9eeca106725	2728	*/
Kojto	122:f9eeca106725	2729	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
Kojto	122:f9eeca106725	2730	{
Kojto	122:f9eeca106725	2731	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
Kojto	122:f9eeca106725	2732	}
Kojto	122:f9eeca106725	2733
Kojto	122:f9eeca106725	2734	/**
Kojto	122:f9eeca106725	2735	* @brief Release the Backup domain reset
Kojto	122:f9eeca106725	2736	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
Kojto	122:f9eeca106725	2737	* @retval None
Kojto	122:f9eeca106725	2738	*/
Kojto	122:f9eeca106725	2739	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
Kojto	122:f9eeca106725	2740	{
Kojto	122:f9eeca106725	2741	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
Kojto	122:f9eeca106725	2742	}
Kojto	122:f9eeca106725	2743
Kojto	122:f9eeca106725	2744	/**
Kojto	122:f9eeca106725	2745	* @}
Kojto	122:f9eeca106725	2746	*/
Kojto	122:f9eeca106725	2747
Kojto	122:f9eeca106725	2748	/** @defgroup RCC_LL_EF_PLL PLL
Kojto	122:f9eeca106725	2749	* @{
Kojto	122:f9eeca106725	2750	*/
Kojto	122:f9eeca106725	2751
Kojto	122:f9eeca106725	2752	/**
Kojto	122:f9eeca106725	2753	* @brief Enable PLL
Kojto	122:f9eeca106725	2754	* @rmtoll CR PLLON LL_RCC_PLL_Enable
Kojto	122:f9eeca106725	2755	* @retval None
Kojto	122:f9eeca106725	2756	*/
Kojto	122:f9eeca106725	2757	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
Kojto	122:f9eeca106725	2758	{
Kojto	122:f9eeca106725	2759	SET_BIT(RCC->CR, RCC_CR_PLLON);
Kojto	122:f9eeca106725	2760	}
Kojto	122:f9eeca106725	2761
Kojto	122:f9eeca106725	2762	/**
Kojto	122:f9eeca106725	2763	* @brief Disable PLL
Kojto	122:f9eeca106725	2764	* @note Cannot be disabled if the PLL clock is used as the system clock
Kojto	122:f9eeca106725	2765	* @rmtoll CR PLLON LL_RCC_PLL_Disable
Kojto	122:f9eeca106725	2766	* @retval None
Kojto	122:f9eeca106725	2767	*/
Kojto	122:f9eeca106725	2768	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
Kojto	122:f9eeca106725	2769	{
Kojto	122:f9eeca106725	2770	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
Kojto	122:f9eeca106725	2771	}
Kojto	122:f9eeca106725	2772
Kojto	122:f9eeca106725	2773	/**
Kojto	122:f9eeca106725	2774	* @brief Check if PLL Ready
Kojto	122:f9eeca106725	2775	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
Kojto	122:f9eeca106725	2776	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	2777	*/
Kojto	122:f9eeca106725	2778	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
Kojto	122:f9eeca106725	2779	{
Kojto	122:f9eeca106725	2780	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
Kojto	122:f9eeca106725	2781	}
Kojto	122:f9eeca106725	2782
Kojto	122:f9eeca106725	2783	/**
Kojto	122:f9eeca106725	2784	* @brief Configure PLL used for SYSCLK Domain
Kojto	122:f9eeca106725	2785	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	2786	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	2787	* @note PLLN/PLLR can be written only when PLL is disabled
Kojto	122:f9eeca106725	2788	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
Kojto	122:f9eeca106725	2789	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
Kojto	122:f9eeca106725	2790	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
Kojto	122:f9eeca106725	2791	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
Kojto	122:f9eeca106725	2792	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	2793	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	2794	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	2795	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	2796	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	2797	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	2798	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	2799	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	2800	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	2801	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	2802	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	2803	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	2804	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	2805	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	2806	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	2807	* @param PLLR This parameter can be one of the following values:
Kojto	122:f9eeca106725	2808	* @arg @ref LL_RCC_PLLR_DIV_2
Kojto	122:f9eeca106725	2809	* @arg @ref LL_RCC_PLLR_DIV_4
Kojto	122:f9eeca106725	2810	* @arg @ref LL_RCC_PLLR_DIV_6
Kojto	122:f9eeca106725	2811	* @arg @ref LL_RCC_PLLR_DIV_8
Kojto	122:f9eeca106725	2812	* @retval None
Kojto	122:f9eeca106725	2813	*/
Kojto	122:f9eeca106725	2814	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Kojto	122:f9eeca106725	2815	{
Kojto	122:f9eeca106725	2816	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
Kojto	122:f9eeca106725	2817	Source \| PLLM \| PLLN << RCC_POSITION_PLLN \| PLLR);
Kojto	122:f9eeca106725	2818	}
Kojto	122:f9eeca106725	2819
Kojto	122:f9eeca106725	2820	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	2821	/**
Kojto	122:f9eeca106725	2822	* @brief Configure PLL used for SAI domain clock
Kojto	122:f9eeca106725	2823	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	2824	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	2825	* @note PLLN/PLLP can be written only when PLL is disabled
Kojto	122:f9eeca106725	2826	* @note This can be selected for SAI1 or SAI2 (*)
Kojto	122:f9eeca106725	2827	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	2828	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	2829	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	2830	* PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI
Kojto	122:f9eeca106725	2831	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	2832	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	2833	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	2834	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	2835	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	2836	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	2837	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	2838	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	2839	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	2840	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	2841	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	2842	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	2843	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	2844	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	2845	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	2846	* @param PLLP This parameter can be one of the following values:
Kojto	122:f9eeca106725	2847	* @arg @ref LL_RCC_PLLP_DIV_2
Kojto	122:f9eeca106725	2848	* @arg @ref LL_RCC_PLLP_DIV_3
Kojto	122:f9eeca106725	2849	* @arg @ref LL_RCC_PLLP_DIV_4
Kojto	122:f9eeca106725	2850	* @arg @ref LL_RCC_PLLP_DIV_5
Kojto	122:f9eeca106725	2851	* @arg @ref LL_RCC_PLLP_DIV_6
Kojto	122:f9eeca106725	2852	* @arg @ref LL_RCC_PLLP_DIV_7
Kojto	122:f9eeca106725	2853	* @arg @ref LL_RCC_PLLP_DIV_8
Kojto	122:f9eeca106725	2854	* @arg @ref LL_RCC_PLLP_DIV_9
Kojto	122:f9eeca106725	2855	* @arg @ref LL_RCC_PLLP_DIV_10
Kojto	122:f9eeca106725	2856	* @arg @ref LL_RCC_PLLP_DIV_11
Kojto	122:f9eeca106725	2857	* @arg @ref LL_RCC_PLLP_DIV_12
Kojto	122:f9eeca106725	2858	* @arg @ref LL_RCC_PLLP_DIV_13
Kojto	122:f9eeca106725	2859	* @arg @ref LL_RCC_PLLP_DIV_14
Kojto	122:f9eeca106725	2860	* @arg @ref LL_RCC_PLLP_DIV_15
Kojto	122:f9eeca106725	2861	* @arg @ref LL_RCC_PLLP_DIV_16
Kojto	122:f9eeca106725	2862	* @arg @ref LL_RCC_PLLP_DIV_17
Kojto	122:f9eeca106725	2863	* @arg @ref LL_RCC_PLLP_DIV_18
Kojto	122:f9eeca106725	2864	* @arg @ref LL_RCC_PLLP_DIV_19
Kojto	122:f9eeca106725	2865	* @arg @ref LL_RCC_PLLP_DIV_20
Kojto	122:f9eeca106725	2866	* @arg @ref LL_RCC_PLLP_DIV_21
Kojto	122:f9eeca106725	2867	* @arg @ref LL_RCC_PLLP_DIV_22
Kojto	122:f9eeca106725	2868	* @arg @ref LL_RCC_PLLP_DIV_23
Kojto	122:f9eeca106725	2869	* @arg @ref LL_RCC_PLLP_DIV_24
Kojto	122:f9eeca106725	2870	* @arg @ref LL_RCC_PLLP_DIV_25
Kojto	122:f9eeca106725	2871	* @arg @ref LL_RCC_PLLP_DIV_26
Kojto	122:f9eeca106725	2872	* @arg @ref LL_RCC_PLLP_DIV_27
Kojto	122:f9eeca106725	2873	* @arg @ref LL_RCC_PLLP_DIV_28
Kojto	122:f9eeca106725	2874	* @arg @ref LL_RCC_PLLP_DIV_29
Kojto	122:f9eeca106725	2875	* @arg @ref LL_RCC_PLLP_DIV_30
Kojto	122:f9eeca106725	2876	* @arg @ref LL_RCC_PLLP_DIV_31
Kojto	122:f9eeca106725	2877	* @retval None
Kojto	122:f9eeca106725	2878	*/
Kojto	122:f9eeca106725	2879	#else
Kojto	122:f9eeca106725	2880	/**
Kojto	122:f9eeca106725	2881	* @brief Configure PLL used for SAI domain clock
Kojto	122:f9eeca106725	2882	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	2883	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	2884	* @note PLLN/PLLP can be written only when PLL is disabled
Kojto	122:f9eeca106725	2885	* @note This can be selected for SAI1 or SAI2 (*)
Kojto	122:f9eeca106725	2886	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	2887	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	2888	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	2889	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
Kojto	122:f9eeca106725	2890	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	2891	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	2892	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	2893	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	2894	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	2895	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	2896	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	2897	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	2898	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	2899	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	2900	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	2901	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	2902	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	2903	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	2904	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	2905	* @param PLLP This parameter can be one of the following values:
Kojto	122:f9eeca106725	2906	* @arg @ref LL_RCC_PLLP_DIV_7
Kojto	122:f9eeca106725	2907	* @arg @ref LL_RCC_PLLP_DIV_17
Kojto	122:f9eeca106725	2908	* @retval None
Kojto	122:f9eeca106725	2909	*/
Kojto	122:f9eeca106725	2910	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	2911	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Kojto	122:f9eeca106725	2912	{
Kojto	122:f9eeca106725	2913	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	2914	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLPDIV,
Kojto	122:f9eeca106725	2915	Source \| PLLM \| PLLN << RCC_POSITION_PLLN \| PLLP);
Kojto	122:f9eeca106725	2916	#else
Kojto	122:f9eeca106725	2917	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLP,
Kojto	122:f9eeca106725	2918	Source \| PLLM \| PLLN << RCC_POSITION_PLLN \| PLLP);
Kojto	122:f9eeca106725	2919	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	2920	}
Kojto	122:f9eeca106725	2921
Kojto	122:f9eeca106725	2922	/**
Kojto	122:f9eeca106725	2923	* @brief Configure PLL used for 48Mhz domain clock
Kojto	122:f9eeca106725	2924	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	2925	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	2926	* @note PLLN/PLLQ can be written only when PLL is disabled
Kojto	122:f9eeca106725	2927	* @note This can be selected for USB, RNG, SDMMC
Kojto	122:f9eeca106725	2928	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
Kojto	122:f9eeca106725	2929	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
Kojto	122:f9eeca106725	2930	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
Kojto	122:f9eeca106725	2931	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
Kojto	122:f9eeca106725	2932	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	2933	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	2934	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	2935	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	2936	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	2937	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	2938	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	2939	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	2940	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	2941	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	2942	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	2943	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	2944	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	2945	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	2946	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	2947	* @param PLLQ This parameter can be one of the following values:
Kojto	122:f9eeca106725	2948	* @arg @ref LL_RCC_PLLQ_DIV_2
Kojto	122:f9eeca106725	2949	* @arg @ref LL_RCC_PLLQ_DIV_4
Kojto	122:f9eeca106725	2950	* @arg @ref LL_RCC_PLLQ_DIV_6
Kojto	122:f9eeca106725	2951	* @arg @ref LL_RCC_PLLQ_DIV_8
Kojto	122:f9eeca106725	2952	* @retval None
Kojto	122:f9eeca106725	2953	*/
Kojto	122:f9eeca106725	2954	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Kojto	122:f9eeca106725	2955	{
Kojto	122:f9eeca106725	2956	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
Kojto	122:f9eeca106725	2957	Source \| PLLM \| PLLN << RCC_POSITION_PLLN \| PLLQ);
Kojto	122:f9eeca106725	2958	}
Kojto	122:f9eeca106725	2959
Kojto	122:f9eeca106725	2960	/**
Kojto	122:f9eeca106725	2961	* @brief Get Main PLL multiplication factor for VCO
Kojto	122:f9eeca106725	2962	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
Kojto	122:f9eeca106725	2963	* @retval Between 8 and 86
Kojto	122:f9eeca106725	2964	*/
Kojto	122:f9eeca106725	2965	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
Kojto	122:f9eeca106725	2966	{
Kojto	122:f9eeca106725	2967	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_POSITION_PLLN);
Kojto	122:f9eeca106725	2968	}
Kojto	122:f9eeca106725	2969
Kojto	122:f9eeca106725	2970	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	2971	/**
Kojto	122:f9eeca106725	2972	* @brief Get Main PLL division factor for PLLP
Kojto	122:f9eeca106725	2973	* @note used for PLLSAI3CLK (SAI1 and SAI2 clock)
Kojto	122:f9eeca106725	2974	* @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP
Kojto	122:f9eeca106725	2975	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2976	* @arg @ref LL_RCC_PLLP_DIV_2
Kojto	122:f9eeca106725	2977	* @arg @ref LL_RCC_PLLP_DIV_3
Kojto	122:f9eeca106725	2978	* @arg @ref LL_RCC_PLLP_DIV_4
Kojto	122:f9eeca106725	2979	* @arg @ref LL_RCC_PLLP_DIV_5
Kojto	122:f9eeca106725	2980	* @arg @ref LL_RCC_PLLP_DIV_6
Kojto	122:f9eeca106725	2981	* @arg @ref LL_RCC_PLLP_DIV_7
Kojto	122:f9eeca106725	2982	* @arg @ref LL_RCC_PLLP_DIV_8
Kojto	122:f9eeca106725	2983	* @arg @ref LL_RCC_PLLP_DIV_9
Kojto	122:f9eeca106725	2984	* @arg @ref LL_RCC_PLLP_DIV_10
Kojto	122:f9eeca106725	2985	* @arg @ref LL_RCC_PLLP_DIV_11
Kojto	122:f9eeca106725	2986	* @arg @ref LL_RCC_PLLP_DIV_12
Kojto	122:f9eeca106725	2987	* @arg @ref LL_RCC_PLLP_DIV_13
Kojto	122:f9eeca106725	2988	* @arg @ref LL_RCC_PLLP_DIV_14
Kojto	122:f9eeca106725	2989	* @arg @ref LL_RCC_PLLP_DIV_15
Kojto	122:f9eeca106725	2990	* @arg @ref LL_RCC_PLLP_DIV_16
Kojto	122:f9eeca106725	2991	* @arg @ref LL_RCC_PLLP_DIV_17
Kojto	122:f9eeca106725	2992	* @arg @ref LL_RCC_PLLP_DIV_18
Kojto	122:f9eeca106725	2993	* @arg @ref LL_RCC_PLLP_DIV_19
Kojto	122:f9eeca106725	2994	* @arg @ref LL_RCC_PLLP_DIV_20
Kojto	122:f9eeca106725	2995	* @arg @ref LL_RCC_PLLP_DIV_21
Kojto	122:f9eeca106725	2996	* @arg @ref LL_RCC_PLLP_DIV_22
Kojto	122:f9eeca106725	2997	* @arg @ref LL_RCC_PLLP_DIV_23
Kojto	122:f9eeca106725	2998	* @arg @ref LL_RCC_PLLP_DIV_24
Kojto	122:f9eeca106725	2999	* @arg @ref LL_RCC_PLLP_DIV_25
Kojto	122:f9eeca106725	3000	* @arg @ref LL_RCC_PLLP_DIV_26
Kojto	122:f9eeca106725	3001	* @arg @ref LL_RCC_PLLP_DIV_27
Kojto	122:f9eeca106725	3002	* @arg @ref LL_RCC_PLLP_DIV_28
Kojto	122:f9eeca106725	3003	* @arg @ref LL_RCC_PLLP_DIV_29
Kojto	122:f9eeca106725	3004	* @arg @ref LL_RCC_PLLP_DIV_30
Kojto	122:f9eeca106725	3005	* @arg @ref LL_RCC_PLLP_DIV_31
Kojto	122:f9eeca106725	3006	*/
Kojto	122:f9eeca106725	3007	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
Kojto	122:f9eeca106725	3008	{
Kojto	122:f9eeca106725	3009	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
Kojto	122:f9eeca106725	3010	}
Kojto	122:f9eeca106725	3011	#else
Kojto	122:f9eeca106725	3012	/**
Kojto	122:f9eeca106725	3013	* @brief Get Main PLL division factor for PLLP
Kojto	122:f9eeca106725	3014	* @note used for PLLSAI3CLK (SAI1 and SAI2 clock)
Kojto	122:f9eeca106725	3015	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
Kojto	122:f9eeca106725	3016	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3017	* @arg @ref LL_RCC_PLLP_DIV_7
Kojto	122:f9eeca106725	3018	* @arg @ref LL_RCC_PLLP_DIV_17
Kojto	122:f9eeca106725	3019	*/
Kojto	122:f9eeca106725	3020	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
Kojto	122:f9eeca106725	3021	{
Kojto	122:f9eeca106725	3022	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
Kojto	122:f9eeca106725	3023	}
Kojto	122:f9eeca106725	3024	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	3025
Kojto	122:f9eeca106725	3026	/**
Kojto	122:f9eeca106725	3027	* @brief Get Main PLL division factor for PLLQ
Kojto	122:f9eeca106725	3028	* @note used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
Kojto	122:f9eeca106725	3029	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
Kojto	122:f9eeca106725	3030	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3031	* @arg @ref LL_RCC_PLLQ_DIV_2
Kojto	122:f9eeca106725	3032	* @arg @ref LL_RCC_PLLQ_DIV_4
Kojto	122:f9eeca106725	3033	* @arg @ref LL_RCC_PLLQ_DIV_6
Kojto	122:f9eeca106725	3034	* @arg @ref LL_RCC_PLLQ_DIV_8
Kojto	122:f9eeca106725	3035	*/
Kojto	122:f9eeca106725	3036	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
Kojto	122:f9eeca106725	3037	{
Kojto	122:f9eeca106725	3038	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
Kojto	122:f9eeca106725	3039	}
Kojto	122:f9eeca106725	3040
Kojto	122:f9eeca106725	3041	/**
Kojto	122:f9eeca106725	3042	* @brief Get Main PLL division factor for PLLR
Kojto	122:f9eeca106725	3043	* @note used for PLLCLK (system clock)
Kojto	122:f9eeca106725	3044	* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
Kojto	122:f9eeca106725	3045	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3046	* @arg @ref LL_RCC_PLLR_DIV_2
Kojto	122:f9eeca106725	3047	* @arg @ref LL_RCC_PLLR_DIV_4
Kojto	122:f9eeca106725	3048	* @arg @ref LL_RCC_PLLR_DIV_6
Kojto	122:f9eeca106725	3049	* @arg @ref LL_RCC_PLLR_DIV_8
Kojto	122:f9eeca106725	3050	*/
Kojto	122:f9eeca106725	3051	__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
Kojto	122:f9eeca106725	3052	{
Kojto	122:f9eeca106725	3053	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
Kojto	122:f9eeca106725	3054	}
Kojto	122:f9eeca106725	3055
Kojto	122:f9eeca106725	3056	/**
Kojto	122:f9eeca106725	3057	* @brief Get the oscillator used as PLL clock source.
Kojto	122:f9eeca106725	3058	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
Kojto	122:f9eeca106725	3059	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3060	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3061	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3062	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3063	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3064	*/
Kojto	122:f9eeca106725	3065	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
Kojto	122:f9eeca106725	3066	{
Kojto	122:f9eeca106725	3067	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
Kojto	122:f9eeca106725	3068	}
Kojto	122:f9eeca106725	3069
Kojto	122:f9eeca106725	3070	/**
Kojto	122:f9eeca106725	3071	* @brief Get Division factor for the main PLL and other PLL
Kojto	122:f9eeca106725	3072	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
Kojto	122:f9eeca106725	3073	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3074	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3075	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3076	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3077	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3078	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3079	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3080	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3081	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3082	*/
Kojto	122:f9eeca106725	3083	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
Kojto	122:f9eeca106725	3084	{
Kojto	122:f9eeca106725	3085	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
Kojto	122:f9eeca106725	3086	}
Kojto	122:f9eeca106725	3087
Kojto	122:f9eeca106725	3088	/**
Kojto	122:f9eeca106725	3089	* @brief Enable PLL output mapped on SAI domain clock
Kojto	122:f9eeca106725	3090	* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
Kojto	122:f9eeca106725	3091	* @retval None
Kojto	122:f9eeca106725	3092	*/
Kojto	122:f9eeca106725	3093	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
Kojto	122:f9eeca106725	3094	{
Kojto	122:f9eeca106725	3095	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
Kojto	122:f9eeca106725	3096	}
Kojto	122:f9eeca106725	3097
Kojto	122:f9eeca106725	3098	/**
Kojto	122:f9eeca106725	3099	* @brief Disable PLL output mapped on SAI domain clock
Kojto	122:f9eeca106725	3100	* @note Cannot be disabled if the PLL clock is used as the system
Kojto	122:f9eeca106725	3101	* clock
Kojto	122:f9eeca106725	3102	* @note In order to save power, when the PLLCLK of the PLL is
Kojto	122:f9eeca106725	3103	* not used, should be 0
Kojto	122:f9eeca106725	3104	* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
Kojto	122:f9eeca106725	3105	* @retval None
Kojto	122:f9eeca106725	3106	*/
Kojto	122:f9eeca106725	3107	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
Kojto	122:f9eeca106725	3108	{
Kojto	122:f9eeca106725	3109	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
Kojto	122:f9eeca106725	3110	}
Kojto	122:f9eeca106725	3111
Kojto	122:f9eeca106725	3112	/**
Kojto	122:f9eeca106725	3113	* @brief Enable PLL output mapped on 48MHz domain clock
Kojto	122:f9eeca106725	3114	* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
Kojto	122:f9eeca106725	3115	* @retval None
Kojto	122:f9eeca106725	3116	*/
Kojto	122:f9eeca106725	3117	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
Kojto	122:f9eeca106725	3118	{
Kojto	122:f9eeca106725	3119	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
Kojto	122:f9eeca106725	3120	}
Kojto	122:f9eeca106725	3121
Kojto	122:f9eeca106725	3122	/**
Kojto	122:f9eeca106725	3123	* @brief Disable PLL output mapped on 48MHz domain clock
Kojto	122:f9eeca106725	3124	* @note Cannot be disabled if the PLL clock is used as the system
Kojto	122:f9eeca106725	3125	* clock
Kojto	122:f9eeca106725	3126	* @note In order to save power, when the PLLCLK of the PLL is
Kojto	122:f9eeca106725	3127	* not used, should be 0
Kojto	122:f9eeca106725	3128	* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
Kojto	122:f9eeca106725	3129	* @retval None
Kojto	122:f9eeca106725	3130	*/
Kojto	122:f9eeca106725	3131	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
Kojto	122:f9eeca106725	3132	{
Kojto	122:f9eeca106725	3133	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
Kojto	122:f9eeca106725	3134	}
Kojto	122:f9eeca106725	3135
Kojto	122:f9eeca106725	3136	/**
Kojto	122:f9eeca106725	3137	* @brief Enable PLL output mapped on SYSCLK domain
Kojto	122:f9eeca106725	3138	* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
Kojto	122:f9eeca106725	3139	* @retval None
Kojto	122:f9eeca106725	3140	*/
Kojto	122:f9eeca106725	3141	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
Kojto	122:f9eeca106725	3142	{
Kojto	122:f9eeca106725	3143	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
Kojto	122:f9eeca106725	3144	}
Kojto	122:f9eeca106725	3145
Kojto	122:f9eeca106725	3146	/**
Kojto	122:f9eeca106725	3147	* @brief Disable PLL output mapped on SYSCLK domain
Kojto	122:f9eeca106725	3148	* @note Cannot be disabled if the PLL clock is used as the system
Kojto	122:f9eeca106725	3149	* clock
Kojto	122:f9eeca106725	3150	* @note In order to save power, when the PLLCLK of the PLL is
Kojto	122:f9eeca106725	3151	* not used, Main PLL should be 0
Kojto	122:f9eeca106725	3152	* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
Kojto	122:f9eeca106725	3153	* @retval None
Kojto	122:f9eeca106725	3154	*/
Kojto	122:f9eeca106725	3155	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
Kojto	122:f9eeca106725	3156	{
Kojto	122:f9eeca106725	3157	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
Kojto	122:f9eeca106725	3158	}
Kojto	122:f9eeca106725	3159
Kojto	122:f9eeca106725	3160	/**
Kojto	122:f9eeca106725	3161	* @}
Kojto	122:f9eeca106725	3162	*/
Kojto	122:f9eeca106725	3163
Kojto	122:f9eeca106725	3164	/** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
Kojto	122:f9eeca106725	3165	* @{
Kojto	122:f9eeca106725	3166	*/
Kojto	122:f9eeca106725	3167
Kojto	122:f9eeca106725	3168	/**
Kojto	122:f9eeca106725	3169	* @brief Enable PLLSAI1
Kojto	122:f9eeca106725	3170	* @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
Kojto	122:f9eeca106725	3171	* @retval None
Kojto	122:f9eeca106725	3172	*/
Kojto	122:f9eeca106725	3173	__STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
Kojto	122:f9eeca106725	3174	{
Kojto	122:f9eeca106725	3175	SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
Kojto	122:f9eeca106725	3176	}
Kojto	122:f9eeca106725	3177
Kojto	122:f9eeca106725	3178	/**
Kojto	122:f9eeca106725	3179	* @brief Disable PLLSAI1
Kojto	122:f9eeca106725	3180	* @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
Kojto	122:f9eeca106725	3181	* @retval None
Kojto	122:f9eeca106725	3182	*/
Kojto	122:f9eeca106725	3183	__STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
Kojto	122:f9eeca106725	3184	{
Kojto	122:f9eeca106725	3185	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
Kojto	122:f9eeca106725	3186	}
Kojto	122:f9eeca106725	3187
Kojto	122:f9eeca106725	3188	/**
Kojto	122:f9eeca106725	3189	* @brief Check if PLLSAI1 Ready
Kojto	122:f9eeca106725	3190	* @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
Kojto	122:f9eeca106725	3191	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3192	*/
Kojto	122:f9eeca106725	3193	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
Kojto	122:f9eeca106725	3194	{
Kojto	122:f9eeca106725	3195	return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY));
Kojto	122:f9eeca106725	3196	}
Kojto	122:f9eeca106725	3197
Kojto	122:f9eeca106725	3198	/**
Kojto	122:f9eeca106725	3199	* @brief Configure PLLSAI1 used for 48Mhz domain clock
Kojto	122:f9eeca106725	3200	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	3201	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	3202	* @note PLLN/PLLQ can be written only when PLLSAI1 is disabled
Kojto	122:f9eeca106725	3203	* @note This can be selected for USB, RNG, SDMMC
Kojto	122:f9eeca106725	3204	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
Kojto	122:f9eeca106725	3205	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
Kojto	122:f9eeca106725	3206	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
Kojto	122:f9eeca106725	3207	* PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
Kojto	122:f9eeca106725	3208	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	3209	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3210	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3211	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3212	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3213	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	3214	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3215	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3216	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3217	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3218	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3219	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3220	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3221	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3222	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	3223	* @param PLLQ This parameter can be one of the following values:
Kojto	122:f9eeca106725	3224	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
Kojto	122:f9eeca106725	3225	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
Kojto	122:f9eeca106725	3226	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
Kojto	122:f9eeca106725	3227	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
Kojto	122:f9eeca106725	3228	* @retval None
Kojto	122:f9eeca106725	3229	*/
Kojto	122:f9eeca106725	3230	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Kojto	122:f9eeca106725	3231	{
Kojto	122:f9eeca106725	3232	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
Kojto	122:f9eeca106725	3233	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_POSITION_PLLSAI1N \| PLLQ);
Kojto	122:f9eeca106725	3234	}
Kojto	122:f9eeca106725	3235
Kojto	122:f9eeca106725	3236	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	3237	/**
Kojto	122:f9eeca106725	3238	* @brief Configure PLLSAI1 used for SAI domain clock
Kojto	122:f9eeca106725	3239	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	3240	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	3241	* @note PLLN/PLLP can be written only when PLLSAI1 is disabled
Kojto	122:f9eeca106725	3242	* @note This can be selected for SAI1 or SAI2 (*)
Kojto	122:f9eeca106725	3243	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3244	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3245	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3246	* PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
Kojto	122:f9eeca106725	3247	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	3248	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3249	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3250	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3251	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3252	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	3253	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3254	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3255	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3256	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3257	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3258	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3259	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3260	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3261	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	3262	* @param PLLP This parameter can be one of the following values:
Kojto	122:f9eeca106725	3263	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
Kojto	122:f9eeca106725	3264	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
Kojto	122:f9eeca106725	3265	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
Kojto	122:f9eeca106725	3266	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
Kojto	122:f9eeca106725	3267	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
Kojto	122:f9eeca106725	3268	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
Kojto	122:f9eeca106725	3269	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
Kojto	122:f9eeca106725	3270	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
Kojto	122:f9eeca106725	3271	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
Kojto	122:f9eeca106725	3272	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
Kojto	122:f9eeca106725	3273	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
Kojto	122:f9eeca106725	3274	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
Kojto	122:f9eeca106725	3275	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
Kojto	122:f9eeca106725	3276	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
Kojto	122:f9eeca106725	3277	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
Kojto	122:f9eeca106725	3278	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
Kojto	122:f9eeca106725	3279	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
Kojto	122:f9eeca106725	3280	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
Kojto	122:f9eeca106725	3281	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
Kojto	122:f9eeca106725	3282	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
Kojto	122:f9eeca106725	3283	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
Kojto	122:f9eeca106725	3284	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
Kojto	122:f9eeca106725	3285	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
Kojto	122:f9eeca106725	3286	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
Kojto	122:f9eeca106725	3287	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
Kojto	122:f9eeca106725	3288	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
Kojto	122:f9eeca106725	3289	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
Kojto	122:f9eeca106725	3290	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
Kojto	122:f9eeca106725	3291	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
Kojto	122:f9eeca106725	3292	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
Kojto	122:f9eeca106725	3293	* @retval None
Kojto	122:f9eeca106725	3294	*/
Kojto	122:f9eeca106725	3295	#else
Kojto	122:f9eeca106725	3296	/**
Kojto	122:f9eeca106725	3297	* @brief Configure PLLSAI1 used for SAI domain clock
Kojto	122:f9eeca106725	3298	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	3299	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	3300	* @note PLLN/PLLP can be written only when PLLSAI1 is disabled
Kojto	122:f9eeca106725	3301	* @note This can be selected for SAI1 or SAI2 (*)
Kojto	122:f9eeca106725	3302	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3303	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3304	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3305	* PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI
Kojto	122:f9eeca106725	3306	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	3307	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3308	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3309	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3310	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3311	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	3312	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3313	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3314	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3315	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3316	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3317	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3318	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3319	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3320	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	3321	* @param PLLP This parameter can be one of the following values:
Kojto	122:f9eeca106725	3322	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
Kojto	122:f9eeca106725	3323	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
Kojto	122:f9eeca106725	3324	* @retval None
Kojto	122:f9eeca106725	3325	*/
Kojto	122:f9eeca106725	3326	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	3327	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Kojto	122:f9eeca106725	3328	{
Kojto	122:f9eeca106725	3329	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
Kojto	122:f9eeca106725	3330	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	3331	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1PDIV,
Kojto	122:f9eeca106725	3332	PLLN << RCC_POSITION_PLLSAI1N \| PLLP);
Kojto	122:f9eeca106725	3333	#else
Kojto	122:f9eeca106725	3334	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_POSITION_PLLSAI1N \| PLLP);
Kojto	122:f9eeca106725	3335	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	3336	}
Kojto	122:f9eeca106725	3337
Kojto	122:f9eeca106725	3338	/**
Kojto	122:f9eeca106725	3339	* @brief Configure PLLSAI1 used for ADC domain clock
Kojto	122:f9eeca106725	3340	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	3341	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	3342	* @note PLLN/PLLR can be written only when PLLSAI1 is disabled
Kojto	122:f9eeca106725	3343	* @note This can be selected for ADC
Kojto	122:f9eeca106725	3344	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
Kojto	122:f9eeca106725	3345	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
Kojto	122:f9eeca106725	3346	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
Kojto	122:f9eeca106725	3347	* PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
Kojto	122:f9eeca106725	3348	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	3349	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3350	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3351	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3352	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3353	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	3354	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3355	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3356	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3357	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3358	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3359	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3360	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3361	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3362	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	3363	* @param PLLR This parameter can be one of the following values:
Kojto	122:f9eeca106725	3364	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
Kojto	122:f9eeca106725	3365	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
Kojto	122:f9eeca106725	3366	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
Kojto	122:f9eeca106725	3367	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
Kojto	122:f9eeca106725	3368	* @retval None
Kojto	122:f9eeca106725	3369	*/
Kojto	122:f9eeca106725	3370	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Kojto	122:f9eeca106725	3371	{
Kojto	122:f9eeca106725	3372	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
Kojto	122:f9eeca106725	3373	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_POSITION_PLLSAI1N \| PLLR);
Kojto	122:f9eeca106725	3374	}
Kojto	122:f9eeca106725	3375
Kojto	122:f9eeca106725	3376	/**
Kojto	122:f9eeca106725	3377	* @brief Get SAI1PLL multiplication factor for VCO
Kojto	122:f9eeca106725	3378	* @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN
Kojto	122:f9eeca106725	3379	* @retval Between 8 and 86
Kojto	122:f9eeca106725	3380	*/
Kojto	122:f9eeca106725	3381	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
Kojto	122:f9eeca106725	3382	{
Kojto	122:f9eeca106725	3383	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_POSITION_PLLSAI1N);
Kojto	122:f9eeca106725	3384	}
Kojto	122:f9eeca106725	3385
Kojto	122:f9eeca106725	3386	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	3387	/**
Kojto	122:f9eeca106725	3388	* @brief Get SAI1PLL division factor for PLLSAI1P
Kojto	122:f9eeca106725	3389	* @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
Kojto	122:f9eeca106725	3390	* @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP
Kojto	122:f9eeca106725	3391	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3392	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
Kojto	122:f9eeca106725	3393	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
Kojto	122:f9eeca106725	3394	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
Kojto	122:f9eeca106725	3395	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
Kojto	122:f9eeca106725	3396	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
Kojto	122:f9eeca106725	3397	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
Kojto	122:f9eeca106725	3398	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
Kojto	122:f9eeca106725	3399	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
Kojto	122:f9eeca106725	3400	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
Kojto	122:f9eeca106725	3401	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
Kojto	122:f9eeca106725	3402	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
Kojto	122:f9eeca106725	3403	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
Kojto	122:f9eeca106725	3404	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
Kojto	122:f9eeca106725	3405	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
Kojto	122:f9eeca106725	3406	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
Kojto	122:f9eeca106725	3407	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
Kojto	122:f9eeca106725	3408	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
Kojto	122:f9eeca106725	3409	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
Kojto	122:f9eeca106725	3410	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
Kojto	122:f9eeca106725	3411	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
Kojto	122:f9eeca106725	3412	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
Kojto	122:f9eeca106725	3413	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
Kojto	122:f9eeca106725	3414	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
Kojto	122:f9eeca106725	3415	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
Kojto	122:f9eeca106725	3416	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
Kojto	122:f9eeca106725	3417	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
Kojto	122:f9eeca106725	3418	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
Kojto	122:f9eeca106725	3419	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
Kojto	122:f9eeca106725	3420	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
Kojto	122:f9eeca106725	3421	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
Kojto	122:f9eeca106725	3422	*/
Kojto	122:f9eeca106725	3423	#else
Kojto	122:f9eeca106725	3424	/**
Kojto	122:f9eeca106725	3425	* @brief Get SAI1PLL division factor for PLLSAI1P
Kojto	122:f9eeca106725	3426	* @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
Kojto	122:f9eeca106725	3427	* @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP
Kojto	122:f9eeca106725	3428	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3429	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
Kojto	122:f9eeca106725	3430	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
Kojto	122:f9eeca106725	3431	*/
Kojto	122:f9eeca106725	3432	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	3433	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
Kojto	122:f9eeca106725	3434	{
Kojto	122:f9eeca106725	3435	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	3436	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
Kojto	122:f9eeca106725	3437	#else
Kojto	122:f9eeca106725	3438	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
Kojto	122:f9eeca106725	3439	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	3440	}
Kojto	122:f9eeca106725	3441
Kojto	122:f9eeca106725	3442	/**
Kojto	122:f9eeca106725	3443	* @brief Get SAI1PLL division factor for PLLSAI1Q
Kojto	122:f9eeca106725	3444	* @note used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
Kojto	122:f9eeca106725	3445	* @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
Kojto	122:f9eeca106725	3446	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3447	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
Kojto	122:f9eeca106725	3448	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
Kojto	122:f9eeca106725	3449	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
Kojto	122:f9eeca106725	3450	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
Kojto	122:f9eeca106725	3451	*/
Kojto	122:f9eeca106725	3452	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
Kojto	122:f9eeca106725	3453	{
Kojto	122:f9eeca106725	3454	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
Kojto	122:f9eeca106725	3455	}
Kojto	122:f9eeca106725	3456
Kojto	122:f9eeca106725	3457	/**
Kojto	122:f9eeca106725	3458	* @brief Get PLLSAI1 division factor for PLLSAIR
Kojto	122:f9eeca106725	3459	* @note used for PLLADC1CLK (ADC clock)
Kojto	122:f9eeca106725	3460	* @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
Kojto	122:f9eeca106725	3461	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3462	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
Kojto	122:f9eeca106725	3463	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
Kojto	122:f9eeca106725	3464	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
Kojto	122:f9eeca106725	3465	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
Kojto	122:f9eeca106725	3466	*/
Kojto	122:f9eeca106725	3467	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
Kojto	122:f9eeca106725	3468	{
Kojto	122:f9eeca106725	3469	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
Kojto	122:f9eeca106725	3470	}
Kojto	122:f9eeca106725	3471
Kojto	122:f9eeca106725	3472	/**
Kojto	122:f9eeca106725	3473	* @brief Enable PLLSAI1 output mapped on SAI domain clock
Kojto	122:f9eeca106725	3474	* @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI
Kojto	122:f9eeca106725	3475	* @retval None
Kojto	122:f9eeca106725	3476	*/
Kojto	122:f9eeca106725	3477	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
Kojto	122:f9eeca106725	3478	{
Kojto	122:f9eeca106725	3479	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
Kojto	122:f9eeca106725	3480	}
Kojto	122:f9eeca106725	3481
Kojto	122:f9eeca106725	3482	/**
Kojto	122:f9eeca106725	3483	* @brief Disable PLLSAI1 output mapped on SAI domain clock
Kojto	122:f9eeca106725	3484	* @note In order to save power, when of the PLLSAI1 is
Kojto	122:f9eeca106725	3485	* not used, should be 0
Kojto	122:f9eeca106725	3486	* @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI
Kojto	122:f9eeca106725	3487	* @retval None
Kojto	122:f9eeca106725	3488	*/
Kojto	122:f9eeca106725	3489	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
Kojto	122:f9eeca106725	3490	{
Kojto	122:f9eeca106725	3491	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
Kojto	122:f9eeca106725	3492	}
Kojto	122:f9eeca106725	3493
Kojto	122:f9eeca106725	3494	/**
Kojto	122:f9eeca106725	3495	* @brief Enable PLLSAI1 output mapped on 48MHz domain clock
Kojto	122:f9eeca106725	3496	* @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M
Kojto	122:f9eeca106725	3497	* @retval None
Kojto	122:f9eeca106725	3498	*/
Kojto	122:f9eeca106725	3499	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
Kojto	122:f9eeca106725	3500	{
Kojto	122:f9eeca106725	3501	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
Kojto	122:f9eeca106725	3502	}
Kojto	122:f9eeca106725	3503
Kojto	122:f9eeca106725	3504	/**
Kojto	122:f9eeca106725	3505	* @brief Disable PLLSAI1 output mapped on 48MHz domain clock
Kojto	122:f9eeca106725	3506	* @note In order to save power, when of the PLLSAI1 is
Kojto	122:f9eeca106725	3507	* not used, should be 0
Kojto	122:f9eeca106725	3508	* @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M
Kojto	122:f9eeca106725	3509	* @retval None
Kojto	122:f9eeca106725	3510	*/
Kojto	122:f9eeca106725	3511	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
Kojto	122:f9eeca106725	3512	{
Kojto	122:f9eeca106725	3513	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
Kojto	122:f9eeca106725	3514	}
Kojto	122:f9eeca106725	3515
Kojto	122:f9eeca106725	3516	/**
Kojto	122:f9eeca106725	3517	* @brief Enable PLLSAI1 output mapped on ADC domain clock
Kojto	122:f9eeca106725	3518	* @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC
Kojto	122:f9eeca106725	3519	* @retval None
Kojto	122:f9eeca106725	3520	*/
Kojto	122:f9eeca106725	3521	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
Kojto	122:f9eeca106725	3522	{
Kojto	122:f9eeca106725	3523	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
Kojto	122:f9eeca106725	3524	}
Kojto	122:f9eeca106725	3525
Kojto	122:f9eeca106725	3526	/**
Kojto	122:f9eeca106725	3527	* @brief Disable PLLSAI1 output mapped on ADC domain clock
Kojto	122:f9eeca106725	3528	* @note In order to save power, when of the PLLSAI1 is
Kojto	122:f9eeca106725	3529	* not used, Main PLLSAI1 should be 0
Kojto	122:f9eeca106725	3530	* @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC
Kojto	122:f9eeca106725	3531	* @retval None
Kojto	122:f9eeca106725	3532	*/
Kojto	122:f9eeca106725	3533	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
Kojto	122:f9eeca106725	3534	{
Kojto	122:f9eeca106725	3535	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
Kojto	122:f9eeca106725	3536	}
Kojto	122:f9eeca106725	3537
Kojto	122:f9eeca106725	3538	/**
Kojto	122:f9eeca106725	3539	* @}
Kojto	122:f9eeca106725	3540	*/
Kojto	122:f9eeca106725	3541
Kojto	122:f9eeca106725	3542	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	3543	/** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
Kojto	122:f9eeca106725	3544	* @{
Kojto	122:f9eeca106725	3545	*/
Kojto	122:f9eeca106725	3546
Kojto	122:f9eeca106725	3547	/**
Kojto	122:f9eeca106725	3548	* @brief Enable PLLSAI2
Kojto	122:f9eeca106725	3549	* @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable
Kojto	122:f9eeca106725	3550	* @retval None
Kojto	122:f9eeca106725	3551	*/
Kojto	122:f9eeca106725	3552	__STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
Kojto	122:f9eeca106725	3553	{
Kojto	122:f9eeca106725	3554	SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
Kojto	122:f9eeca106725	3555	}
Kojto	122:f9eeca106725	3556
Kojto	122:f9eeca106725	3557	/**
Kojto	122:f9eeca106725	3558	* @brief Disable PLLSAI2
Kojto	122:f9eeca106725	3559	* @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable
Kojto	122:f9eeca106725	3560	* @retval None
Kojto	122:f9eeca106725	3561	*/
Kojto	122:f9eeca106725	3562	__STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
Kojto	122:f9eeca106725	3563	{
Kojto	122:f9eeca106725	3564	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
Kojto	122:f9eeca106725	3565	}
Kojto	122:f9eeca106725	3566
Kojto	122:f9eeca106725	3567	/**
Kojto	122:f9eeca106725	3568	* @brief Check if PLLSAI2 Ready
Kojto	122:f9eeca106725	3569	* @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady
Kojto	122:f9eeca106725	3570	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3571	*/
Kojto	122:f9eeca106725	3572	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
Kojto	122:f9eeca106725	3573	{
Kojto	122:f9eeca106725	3574	return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY));
Kojto	122:f9eeca106725	3575	}
Kojto	122:f9eeca106725	3576
Kojto	122:f9eeca106725	3577	/**
Kojto	122:f9eeca106725	3578	* @brief Configure PLLSAI2 used for SAI domain clock
Kojto	122:f9eeca106725	3579	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	3580	* PLLSAI2 and PLLSAI2 are disabled
Kojto	122:f9eeca106725	3581	* @note PLLN/PLLP can be written only when PLLSAI2 is disabled
Kojto	122:f9eeca106725	3582	* @note This can be selected for SAI1 or SAI2
Kojto	122:f9eeca106725	3583	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3584	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3585	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3586	* PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI
Kojto	122:f9eeca106725	3587	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	3588	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3589	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3590	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3591	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3592	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	3593	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3594	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3595	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3596	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3597	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3598	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3599	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3600	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3601	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	3602	* @param PLLP This parameter can be one of the following values:
Kojto	122:f9eeca106725	3603	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
Kojto	122:f9eeca106725	3604	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
Kojto	122:f9eeca106725	3605	* @retval None
Kojto	122:f9eeca106725	3606	*/
Kojto	122:f9eeca106725	3607	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Kojto	122:f9eeca106725	3608	{
Kojto	122:f9eeca106725	3609	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
Kojto	122:f9eeca106725	3610	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_POSITION_PLLSAI2N \| PLLP);
Kojto	122:f9eeca106725	3611	}
Kojto	122:f9eeca106725	3612
Kojto	122:f9eeca106725	3613	/**
Kojto	122:f9eeca106725	3614	* @brief Configure PLLSAI2 used for ADC domain clock
Kojto	122:f9eeca106725	3615	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	3616	* PLLSAI2 and PLLSAI2 are disabled
Kojto	122:f9eeca106725	3617	* @note PLLN/PLLR can be written only when PLLSAI2 is disabled
Kojto	122:f9eeca106725	3618	* @note This can be selected for ADC
Kojto	122:f9eeca106725	3619	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n
Kojto	122:f9eeca106725	3620	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n
Kojto	122:f9eeca106725	3621	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n
Kojto	122:f9eeca106725	3622	* PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC
Kojto	122:f9eeca106725	3623	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	3624	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3625	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3626	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3627	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3628	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	3629	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3630	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3631	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3632	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3633	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3634	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3635	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3636	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3637	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	3638	* @param PLLR This parameter can be one of the following values:
Kojto	122:f9eeca106725	3639	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
Kojto	122:f9eeca106725	3640	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
Kojto	122:f9eeca106725	3641	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
Kojto	122:f9eeca106725	3642	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
Kojto	122:f9eeca106725	3643	* @retval None
Kojto	122:f9eeca106725	3644	*/
Kojto	122:f9eeca106725	3645	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Kojto	122:f9eeca106725	3646	{
Kojto	122:f9eeca106725	3647	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
Kojto	122:f9eeca106725	3648	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_POSITION_PLLSAI2N \| PLLR);
Kojto	122:f9eeca106725	3649	}
Kojto	122:f9eeca106725	3650
Kojto	122:f9eeca106725	3651	/**
Kojto	122:f9eeca106725	3652	* @brief Get SAI2PLL multiplication factor for VCO
Kojto	122:f9eeca106725	3653	* @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN
Kojto	122:f9eeca106725	3654	* @retval Between 8 and 86
Kojto	122:f9eeca106725	3655	*/
Kojto	122:f9eeca106725	3656	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
Kojto	122:f9eeca106725	3657	{
Kojto	122:f9eeca106725	3658	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_POSITION_PLLSAI2N);
Kojto	122:f9eeca106725	3659	}
Kojto	122:f9eeca106725	3660
Kojto	122:f9eeca106725	3661	/**
Kojto	122:f9eeca106725	3662	* @brief Get SAI2PLL division factor for PLLSAI2P
Kojto	122:f9eeca106725	3663	* @note used for PLLSAI2CLK (SAI1 or SAI2 clock).
Kojto	122:f9eeca106725	3664	* @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP
Kojto	122:f9eeca106725	3665	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3666	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
Kojto	122:f9eeca106725	3667	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
Kojto	122:f9eeca106725	3668	*/
Kojto	122:f9eeca106725	3669	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
Kojto	122:f9eeca106725	3670	{
Kojto	122:f9eeca106725	3671	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
Kojto	122:f9eeca106725	3672	}
Kojto	122:f9eeca106725	3673
Kojto	122:f9eeca106725	3674	/**
Kojto	122:f9eeca106725	3675	* @brief Get SAI2PLL division factor for PLLSAI2R
Kojto	122:f9eeca106725	3676	* @note used for PLLADC2CLK (ADC clock)
Kojto	122:f9eeca106725	3677	* @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR
Kojto	122:f9eeca106725	3678	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3679	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
Kojto	122:f9eeca106725	3680	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
Kojto	122:f9eeca106725	3681	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
Kojto	122:f9eeca106725	3682	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
Kojto	122:f9eeca106725	3683	*/
Kojto	122:f9eeca106725	3684	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
Kojto	122:f9eeca106725	3685	{
Kojto	122:f9eeca106725	3686	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
Kojto	122:f9eeca106725	3687	}
Kojto	122:f9eeca106725	3688
Kojto	122:f9eeca106725	3689	/**
Kojto	122:f9eeca106725	3690	* @brief Enable PLLSAI2 output mapped on SAI domain clock
Kojto	122:f9eeca106725	3691	* @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI
Kojto	122:f9eeca106725	3692	* @retval None
Kojto	122:f9eeca106725	3693	*/
Kojto	122:f9eeca106725	3694	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
Kojto	122:f9eeca106725	3695	{
Kojto	122:f9eeca106725	3696	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
Kojto	122:f9eeca106725	3697	}
Kojto	122:f9eeca106725	3698
Kojto	122:f9eeca106725	3699	/**
Kojto	122:f9eeca106725	3700	* @brief Disable PLLSAI2 output mapped on SAI domain clock
Kojto	122:f9eeca106725	3701	* @note In order to save power, when of the PLLSAI2 is
Kojto	122:f9eeca106725	3702	* not used, should be 0
Kojto	122:f9eeca106725	3703	* @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI
Kojto	122:f9eeca106725	3704	* @retval None
Kojto	122:f9eeca106725	3705	*/
Kojto	122:f9eeca106725	3706	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
Kojto	122:f9eeca106725	3707	{
Kojto	122:f9eeca106725	3708	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
Kojto	122:f9eeca106725	3709	}
Kojto	122:f9eeca106725	3710
Kojto	122:f9eeca106725	3711	/**
Kojto	122:f9eeca106725	3712	* @brief Enable PLLSAI2 output mapped on ADC domain clock
Kojto	122:f9eeca106725	3713	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC
Kojto	122:f9eeca106725	3714	* @retval None
Kojto	122:f9eeca106725	3715	*/
Kojto	122:f9eeca106725	3716	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
Kojto	122:f9eeca106725	3717	{
Kojto	122:f9eeca106725	3718	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
Kojto	122:f9eeca106725	3719	}
Kojto	122:f9eeca106725	3720
Kojto	122:f9eeca106725	3721	/**
Kojto	122:f9eeca106725	3722	* @brief Disable PLLSAI2 output mapped on ADC domain clock
Kojto	122:f9eeca106725	3723	* @note In order to save power, when of the PLLSAI2 is
Kojto	122:f9eeca106725	3724	* not used, Main PLLSAI2 should be 0
Kojto	122:f9eeca106725	3725	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC
Kojto	122:f9eeca106725	3726	* @retval None
Kojto	122:f9eeca106725	3727	*/
Kojto	122:f9eeca106725	3728	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
Kojto	122:f9eeca106725	3729	{
Kojto	122:f9eeca106725	3730	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
Kojto	122:f9eeca106725	3731	}
Kojto	122:f9eeca106725	3732
Kojto	122:f9eeca106725	3733	/**
Kojto	122:f9eeca106725	3734	* @}
Kojto	122:f9eeca106725	3735	*/
Kojto	122:f9eeca106725	3736
Kojto	122:f9eeca106725	3737	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	3738	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
Kojto	122:f9eeca106725	3739	* @{
Kojto	122:f9eeca106725	3740	*/
Kojto	122:f9eeca106725	3741
Kojto	122:f9eeca106725	3742	/**
Kojto	122:f9eeca106725	3743	* @brief Clear LSI ready interrupt flag
Kojto	122:f9eeca106725	3744	* @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
Kojto	122:f9eeca106725	3745	* @retval None
Kojto	122:f9eeca106725	3746	*/
Kojto	122:f9eeca106725	3747	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
Kojto	122:f9eeca106725	3748	{
Kojto	122:f9eeca106725	3749	SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
Kojto	122:f9eeca106725	3750	}
Kojto	122:f9eeca106725	3751
Kojto	122:f9eeca106725	3752	/**
Kojto	122:f9eeca106725	3753	* @brief Clear LSE ready interrupt flag
Kojto	122:f9eeca106725	3754	* @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
Kojto	122:f9eeca106725	3755	* @retval None
Kojto	122:f9eeca106725	3756	*/
Kojto	122:f9eeca106725	3757	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
Kojto	122:f9eeca106725	3758	{
Kojto	122:f9eeca106725	3759	SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
Kojto	122:f9eeca106725	3760	}
Kojto	122:f9eeca106725	3761
Kojto	122:f9eeca106725	3762	/**
Kojto	122:f9eeca106725	3763	* @brief Clear MSI ready interrupt flag
Kojto	122:f9eeca106725	3764	* @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
Kojto	122:f9eeca106725	3765	* @retval None
Kojto	122:f9eeca106725	3766	*/
Kojto	122:f9eeca106725	3767	__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
Kojto	122:f9eeca106725	3768	{
Kojto	122:f9eeca106725	3769	SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
Kojto	122:f9eeca106725	3770	}
Kojto	122:f9eeca106725	3771
Kojto	122:f9eeca106725	3772	/**
Kojto	122:f9eeca106725	3773	* @brief Clear HSI ready interrupt flag
Kojto	122:f9eeca106725	3774	* @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
Kojto	122:f9eeca106725	3775	* @retval None
Kojto	122:f9eeca106725	3776	*/
Kojto	122:f9eeca106725	3777	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
Kojto	122:f9eeca106725	3778	{
Kojto	122:f9eeca106725	3779	SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
Kojto	122:f9eeca106725	3780	}
Kojto	122:f9eeca106725	3781
Kojto	122:f9eeca106725	3782	/**
Kojto	122:f9eeca106725	3783	* @brief Clear HSE ready interrupt flag
Kojto	122:f9eeca106725	3784	* @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
Kojto	122:f9eeca106725	3785	* @retval None
Kojto	122:f9eeca106725	3786	*/
Kojto	122:f9eeca106725	3787	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
Kojto	122:f9eeca106725	3788	{
Kojto	122:f9eeca106725	3789	SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
Kojto	122:f9eeca106725	3790	}
Kojto	122:f9eeca106725	3791
Kojto	122:f9eeca106725	3792	/**
Kojto	122:f9eeca106725	3793	* @brief Clear PLL ready interrupt flag
Kojto	122:f9eeca106725	3794	* @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
Kojto	122:f9eeca106725	3795	* @retval None
Kojto	122:f9eeca106725	3796	*/
Kojto	122:f9eeca106725	3797	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
Kojto	122:f9eeca106725	3798	{
Kojto	122:f9eeca106725	3799	SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
Kojto	122:f9eeca106725	3800	}
Kojto	122:f9eeca106725	3801
Kojto	122:f9eeca106725	3802	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	3803	/**
Kojto	122:f9eeca106725	3804	* @brief Clear HSI48 ready interrupt flag
Kojto	122:f9eeca106725	3805	* @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
Kojto	122:f9eeca106725	3806	* @retval None
Kojto	122:f9eeca106725	3807	*/
Kojto	122:f9eeca106725	3808	__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
Kojto	122:f9eeca106725	3809	{
Kojto	122:f9eeca106725	3810	SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
Kojto	122:f9eeca106725	3811	}
Kojto	122:f9eeca106725	3812	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	3813
Kojto	122:f9eeca106725	3814	/**
Kojto	122:f9eeca106725	3815	* @brief Clear PLLSAI1 ready interrupt flag
Kojto	122:f9eeca106725	3816	* @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
Kojto	122:f9eeca106725	3817	* @retval None
Kojto	122:f9eeca106725	3818	*/
Kojto	122:f9eeca106725	3819	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
Kojto	122:f9eeca106725	3820	{
Kojto	122:f9eeca106725	3821	SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
Kojto	122:f9eeca106725	3822	}
Kojto	122:f9eeca106725	3823
Kojto	122:f9eeca106725	3824	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	3825	/**
Kojto	122:f9eeca106725	3826	* @brief Clear PLLSAI1 ready interrupt flag
Kojto	122:f9eeca106725	3827	* @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY
Kojto	122:f9eeca106725	3828	* @retval None
Kojto	122:f9eeca106725	3829	*/
Kojto	122:f9eeca106725	3830	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
Kojto	122:f9eeca106725	3831	{
Kojto	122:f9eeca106725	3832	SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
Kojto	122:f9eeca106725	3833	}
Kojto	122:f9eeca106725	3834
Kojto	122:f9eeca106725	3835	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	3836	/**
Kojto	122:f9eeca106725	3837	* @brief Clear Clock security system interrupt flag
Kojto	122:f9eeca106725	3838	* @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
Kojto	122:f9eeca106725	3839	* @retval None
Kojto	122:f9eeca106725	3840	*/
Kojto	122:f9eeca106725	3841	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
Kojto	122:f9eeca106725	3842	{
Kojto	122:f9eeca106725	3843	SET_BIT(RCC->CICR, RCC_CICR_CSSC);
Kojto	122:f9eeca106725	3844	}
Kojto	122:f9eeca106725	3845
Kojto	122:f9eeca106725	3846	/**
Kojto	122:f9eeca106725	3847	* @brief Clear LSE Clock security system interrupt flag
Kojto	122:f9eeca106725	3848	* @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
Kojto	122:f9eeca106725	3849	* @retval None
Kojto	122:f9eeca106725	3850	*/
Kojto	122:f9eeca106725	3851	__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
Kojto	122:f9eeca106725	3852	{
Kojto	122:f9eeca106725	3853	SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
Kojto	122:f9eeca106725	3854	}
Kojto	122:f9eeca106725	3855
Kojto	122:f9eeca106725	3856	/**
Kojto	122:f9eeca106725	3857	* @brief Check if LSI ready interrupt occurred or not
Kojto	122:f9eeca106725	3858	* @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
Kojto	122:f9eeca106725	3859	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3860	*/
Kojto	122:f9eeca106725	3861	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
Kojto	122:f9eeca106725	3862	{
Kojto	122:f9eeca106725	3863	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF));
Kojto	122:f9eeca106725	3864	}
Kojto	122:f9eeca106725	3865
Kojto	122:f9eeca106725	3866	/**
Kojto	122:f9eeca106725	3867	* @brief Check if LSE ready interrupt occurred or not
Kojto	122:f9eeca106725	3868	* @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
Kojto	122:f9eeca106725	3869	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3870	*/
Kojto	122:f9eeca106725	3871	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
Kojto	122:f9eeca106725	3872	{
Kojto	122:f9eeca106725	3873	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF));
Kojto	122:f9eeca106725	3874	}
Kojto	122:f9eeca106725	3875
Kojto	122:f9eeca106725	3876	/**
Kojto	122:f9eeca106725	3877	* @brief Check if MSI ready interrupt occurred or not
Kojto	122:f9eeca106725	3878	* @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
Kojto	122:f9eeca106725	3879	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3880	*/
Kojto	122:f9eeca106725	3881	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
Kojto	122:f9eeca106725	3882	{
Kojto	122:f9eeca106725	3883	return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF));
Kojto	122:f9eeca106725	3884	}
Kojto	122:f9eeca106725	3885
Kojto	122:f9eeca106725	3886	/**
Kojto	122:f9eeca106725	3887	* @brief Check if HSI ready interrupt occurred or not
Kojto	122:f9eeca106725	3888	* @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
Kojto	122:f9eeca106725	3889	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3890	*/
Kojto	122:f9eeca106725	3891	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
Kojto	122:f9eeca106725	3892	{
Kojto	122:f9eeca106725	3893	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF));
Kojto	122:f9eeca106725	3894	}
Kojto	122:f9eeca106725	3895
Kojto	122:f9eeca106725	3896	/**
Kojto	122:f9eeca106725	3897	* @brief Check if HSE ready interrupt occurred or not
Kojto	122:f9eeca106725	3898	* @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
Kojto	122:f9eeca106725	3899	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3900	*/
Kojto	122:f9eeca106725	3901	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
Kojto	122:f9eeca106725	3902	{
Kojto	122:f9eeca106725	3903	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF));
Kojto	122:f9eeca106725	3904	}
Kojto	122:f9eeca106725	3905
Kojto	122:f9eeca106725	3906	/**
Kojto	122:f9eeca106725	3907	* @brief Check if PLL ready interrupt occurred or not
Kojto	122:f9eeca106725	3908	* @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
Kojto	122:f9eeca106725	3909	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3910	*/
Kojto	122:f9eeca106725	3911	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
Kojto	122:f9eeca106725	3912	{
Kojto	122:f9eeca106725	3913	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF));
Kojto	122:f9eeca106725	3914	}
Kojto	122:f9eeca106725	3915
Kojto	122:f9eeca106725	3916	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	3917	/**
Kojto	122:f9eeca106725	3918	* @brief Check if HSI48 ready interrupt occurred or not
Kojto	122:f9eeca106725	3919	* @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
Kojto	122:f9eeca106725	3920	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3921	*/
Kojto	122:f9eeca106725	3922	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
Kojto	122:f9eeca106725	3923	{
Kojto	122:f9eeca106725	3924	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF));
Kojto	122:f9eeca106725	3925	}
Kojto	122:f9eeca106725	3926	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	3927
Kojto	122:f9eeca106725	3928	/**
Kojto	122:f9eeca106725	3929	* @brief Check if PLLSAI1 ready interrupt occurred or not
Kojto	122:f9eeca106725	3930	* @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
Kojto	122:f9eeca106725	3931	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3932	*/
Kojto	122:f9eeca106725	3933	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
Kojto	122:f9eeca106725	3934	{
Kojto	122:f9eeca106725	3935	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF));
Kojto	122:f9eeca106725	3936	}
Kojto	122:f9eeca106725	3937
Kojto	122:f9eeca106725	3938	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	3939	/**
Kojto	122:f9eeca106725	3940	* @brief Check if PLLSAI1 ready interrupt occurred or not
Kojto	122:f9eeca106725	3941	* @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY
Kojto	122:f9eeca106725	3942	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3943	*/
Kojto	122:f9eeca106725	3944	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
Kojto	122:f9eeca106725	3945	{
Kojto	122:f9eeca106725	3946	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF));
Kojto	122:f9eeca106725	3947	}
Kojto	122:f9eeca106725	3948
Kojto	122:f9eeca106725	3949	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	3950	/**
Kojto	122:f9eeca106725	3951	* @brief Check if Clock security system interrupt occurred or not
Kojto	122:f9eeca106725	3952	* @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
Kojto	122:f9eeca106725	3953	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3954	*/
Kojto	122:f9eeca106725	3955	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
Kojto	122:f9eeca106725	3956	{
Kojto	122:f9eeca106725	3957	return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF));
Kojto	122:f9eeca106725	3958	}
Kojto	122:f9eeca106725	3959
Kojto	122:f9eeca106725	3960	/**
Kojto	122:f9eeca106725	3961	* @brief Check if LSE Clock security system interrupt occurred or not
Kojto	122:f9eeca106725	3962	* @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
Kojto	122:f9eeca106725	3963	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3964	*/
Kojto	122:f9eeca106725	3965	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
Kojto	122:f9eeca106725	3966	{
Kojto	122:f9eeca106725	3967	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF));
Kojto	122:f9eeca106725	3968	}
Kojto	122:f9eeca106725	3969
Kojto	122:f9eeca106725	3970
Kojto	122:f9eeca106725	3971	/**
Kojto	122:f9eeca106725	3972	* @brief Check if RCC flag FW reset is set or not.
Kojto	122:f9eeca106725	3973	* @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST
Kojto	122:f9eeca106725	3974	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3975	*/
Kojto	122:f9eeca106725	3976	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
Kojto	122:f9eeca106725	3977	{
Kojto	122:f9eeca106725	3978	return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF));
Kojto	122:f9eeca106725	3979	}
Kojto	122:f9eeca106725	3980
Kojto	122:f9eeca106725	3981	/**
Kojto	122:f9eeca106725	3982	* @brief Check if RCC flag Independent Watchdog reset is set or not.
Kojto	122:f9eeca106725	3983	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
Kojto	122:f9eeca106725	3984	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3985	*/
Kojto	122:f9eeca106725	3986	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
Kojto	122:f9eeca106725	3987	{
Kojto	122:f9eeca106725	3988	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
Kojto	122:f9eeca106725	3989	}
Kojto	122:f9eeca106725	3990
Kojto	122:f9eeca106725	3991	/**
Kojto	122:f9eeca106725	3992	* @brief Check if RCC flag Low Power reset is set or not.
Kojto	122:f9eeca106725	3993	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
Kojto	122:f9eeca106725	3994	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3995	*/
Kojto	122:f9eeca106725	3996	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
Kojto	122:f9eeca106725	3997	{
Kojto	122:f9eeca106725	3998	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
Kojto	122:f9eeca106725	3999	}
Kojto	122:f9eeca106725	4000
Kojto	122:f9eeca106725	4001	/**
Kojto	122:f9eeca106725	4002	* @brief Check if RCC flag is set or not.
Kojto	122:f9eeca106725	4003	* @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
Kojto	122:f9eeca106725	4004	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4005	*/
Kojto	122:f9eeca106725	4006	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
Kojto	122:f9eeca106725	4007	{
Kojto	122:f9eeca106725	4008	return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
Kojto	122:f9eeca106725	4009	}
Kojto	122:f9eeca106725	4010
Kojto	122:f9eeca106725	4011	/**
Kojto	122:f9eeca106725	4012	* @brief Check if RCC flag Pin reset is set or not.
Kojto	122:f9eeca106725	4013	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
Kojto	122:f9eeca106725	4014	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4015	*/
Kojto	122:f9eeca106725	4016	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
Kojto	122:f9eeca106725	4017	{
Kojto	122:f9eeca106725	4018	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
Kojto	122:f9eeca106725	4019	}
Kojto	122:f9eeca106725	4020
Kojto	122:f9eeca106725	4021	/**
Kojto	122:f9eeca106725	4022	* @brief Check if RCC flag Software reset is set or not.
Kojto	122:f9eeca106725	4023	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
Kojto	122:f9eeca106725	4024	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4025	*/
Kojto	122:f9eeca106725	4026	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
Kojto	122:f9eeca106725	4027	{
Kojto	122:f9eeca106725	4028	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
Kojto	122:f9eeca106725	4029	}
Kojto	122:f9eeca106725	4030
Kojto	122:f9eeca106725	4031	/**
Kojto	122:f9eeca106725	4032	* @brief Check if RCC flag Window Watchdog reset is set or not.
Kojto	122:f9eeca106725	4033	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
Kojto	122:f9eeca106725	4034	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4035	*/
Kojto	122:f9eeca106725	4036	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
Kojto	122:f9eeca106725	4037	{
Kojto	122:f9eeca106725	4038	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
Kojto	122:f9eeca106725	4039	}
Kojto	122:f9eeca106725	4040
Kojto	122:f9eeca106725	4041	/**
Kojto	122:f9eeca106725	4042	* @brief Check if RCC flag BOR reset is set or not.
Kojto	122:f9eeca106725	4043	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
Kojto	122:f9eeca106725	4044	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4045	*/
Kojto	122:f9eeca106725	4046	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
Kojto	122:f9eeca106725	4047	{
Kojto	122:f9eeca106725	4048	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
Kojto	122:f9eeca106725	4049	}
Kojto	122:f9eeca106725	4050
Kojto	122:f9eeca106725	4051	/**
Kojto	122:f9eeca106725	4052	* @brief Set RMVF bit to clear the reset flags.
Kojto	122:f9eeca106725	4053	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
Kojto	122:f9eeca106725	4054	* @retval None
Kojto	122:f9eeca106725	4055	*/
Kojto	122:f9eeca106725	4056	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
Kojto	122:f9eeca106725	4057	{
Kojto	122:f9eeca106725	4058	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
Kojto	122:f9eeca106725	4059	}
Kojto	122:f9eeca106725	4060
Kojto	122:f9eeca106725	4061	/**
Kojto	122:f9eeca106725	4062	* @}
Kojto	122:f9eeca106725	4063	*/
Kojto	122:f9eeca106725	4064
Kojto	122:f9eeca106725	4065	/** @defgroup RCC_LL_EF_IT_Management IT Management
Kojto	122:f9eeca106725	4066	* @{
Kojto	122:f9eeca106725	4067	*/
Kojto	122:f9eeca106725	4068
Kojto	122:f9eeca106725	4069	/**
Kojto	122:f9eeca106725	4070	* @brief Enable LSI ready interrupt
Kojto	122:f9eeca106725	4071	* @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
Kojto	122:f9eeca106725	4072	* @retval None
Kojto	122:f9eeca106725	4073	*/
Kojto	122:f9eeca106725	4074	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
Kojto	122:f9eeca106725	4075	{
Kojto	122:f9eeca106725	4076	SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
Kojto	122:f9eeca106725	4077	}
Kojto	122:f9eeca106725	4078
Kojto	122:f9eeca106725	4079	/**
Kojto	122:f9eeca106725	4080	* @brief Enable LSE ready interrupt
Kojto	122:f9eeca106725	4081	* @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
Kojto	122:f9eeca106725	4082	* @retval None
Kojto	122:f9eeca106725	4083	*/
Kojto	122:f9eeca106725	4084	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
Kojto	122:f9eeca106725	4085	{
Kojto	122:f9eeca106725	4086	SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
Kojto	122:f9eeca106725	4087	}
Kojto	122:f9eeca106725	4088
Kojto	122:f9eeca106725	4089	/**
Kojto	122:f9eeca106725	4090	* @brief Enable MSI ready interrupt
Kojto	122:f9eeca106725	4091	* @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
Kojto	122:f9eeca106725	4092	* @retval None
Kojto	122:f9eeca106725	4093	*/
Kojto	122:f9eeca106725	4094	__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
Kojto	122:f9eeca106725	4095	{
Kojto	122:f9eeca106725	4096	SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
Kojto	122:f9eeca106725	4097	}
Kojto	122:f9eeca106725	4098
Kojto	122:f9eeca106725	4099	/**
Kojto	122:f9eeca106725	4100	* @brief Enable HSI ready interrupt
Kojto	122:f9eeca106725	4101	* @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
Kojto	122:f9eeca106725	4102	* @retval None
Kojto	122:f9eeca106725	4103	*/
Kojto	122:f9eeca106725	4104	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
Kojto	122:f9eeca106725	4105	{
Kojto	122:f9eeca106725	4106	SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
Kojto	122:f9eeca106725	4107	}
Kojto	122:f9eeca106725	4108
Kojto	122:f9eeca106725	4109	/**
Kojto	122:f9eeca106725	4110	* @brief Enable HSE ready interrupt
Kojto	122:f9eeca106725	4111	* @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
Kojto	122:f9eeca106725	4112	* @retval None
Kojto	122:f9eeca106725	4113	*/
Kojto	122:f9eeca106725	4114	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
Kojto	122:f9eeca106725	4115	{
Kojto	122:f9eeca106725	4116	SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
Kojto	122:f9eeca106725	4117	}
Kojto	122:f9eeca106725	4118
Kojto	122:f9eeca106725	4119	/**
Kojto	122:f9eeca106725	4120	* @brief Enable PLL ready interrupt
Kojto	122:f9eeca106725	4121	* @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
Kojto	122:f9eeca106725	4122	* @retval None
Kojto	122:f9eeca106725	4123	*/
Kojto	122:f9eeca106725	4124	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
Kojto	122:f9eeca106725	4125	{
Kojto	122:f9eeca106725	4126	SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
Kojto	122:f9eeca106725	4127	}
Kojto	122:f9eeca106725	4128
Kojto	122:f9eeca106725	4129	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	4130	/**
Kojto	122:f9eeca106725	4131	* @brief Enable HSI48 ready interrupt
Kojto	122:f9eeca106725	4132	* @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
Kojto	122:f9eeca106725	4133	* @retval None
Kojto	122:f9eeca106725	4134	*/
Kojto	122:f9eeca106725	4135	__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
Kojto	122:f9eeca106725	4136	{
Kojto	122:f9eeca106725	4137	SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
Kojto	122:f9eeca106725	4138	}
Kojto	122:f9eeca106725	4139	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	4140
Kojto	122:f9eeca106725	4141	/**
Kojto	122:f9eeca106725	4142	* @brief Enable PLLSAI1 ready interrupt
Kojto	122:f9eeca106725	4143	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
Kojto	122:f9eeca106725	4144	* @retval None
Kojto	122:f9eeca106725	4145	*/
Kojto	122:f9eeca106725	4146	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
Kojto	122:f9eeca106725	4147	{
Kojto	122:f9eeca106725	4148	SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
Kojto	122:f9eeca106725	4149	}
Kojto	122:f9eeca106725	4150
Kojto	122:f9eeca106725	4151	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	4152	/**
Kojto	122:f9eeca106725	4153	* @brief Enable PLLSAI2 ready interrupt
Kojto	122:f9eeca106725	4154	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY
Kojto	122:f9eeca106725	4155	* @retval None
Kojto	122:f9eeca106725	4156	*/
Kojto	122:f9eeca106725	4157	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
Kojto	122:f9eeca106725	4158	{
Kojto	122:f9eeca106725	4159	SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
Kojto	122:f9eeca106725	4160	}
Kojto	122:f9eeca106725	4161
Kojto	122:f9eeca106725	4162	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	4163	/**
Kojto	122:f9eeca106725	4164	* @brief Enable LSE clock security system interrupt
Kojto	122:f9eeca106725	4165	* @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
Kojto	122:f9eeca106725	4166	* @retval None
Kojto	122:f9eeca106725	4167	*/
Kojto	122:f9eeca106725	4168	__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
Kojto	122:f9eeca106725	4169	{
Kojto	122:f9eeca106725	4170	SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
Kojto	122:f9eeca106725	4171	}
Kojto	122:f9eeca106725	4172
Kojto	122:f9eeca106725	4173	/**
Kojto	122:f9eeca106725	4174	* @brief Disable LSI ready interrupt
Kojto	122:f9eeca106725	4175	* @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
Kojto	122:f9eeca106725	4176	* @retval None
Kojto	122:f9eeca106725	4177	*/
Kojto	122:f9eeca106725	4178	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
Kojto	122:f9eeca106725	4179	{
Kojto	122:f9eeca106725	4180	CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
Kojto	122:f9eeca106725	4181	}
Kojto	122:f9eeca106725	4182
Kojto	122:f9eeca106725	4183	/**
Kojto	122:f9eeca106725	4184	* @brief Disable LSE ready interrupt
Kojto	122:f9eeca106725	4185	* @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
Kojto	122:f9eeca106725	4186	* @retval None
Kojto	122:f9eeca106725	4187	*/
Kojto	122:f9eeca106725	4188	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
Kojto	122:f9eeca106725	4189	{
Kojto	122:f9eeca106725	4190	CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
Kojto	122:f9eeca106725	4191	}
Kojto	122:f9eeca106725	4192
Kojto	122:f9eeca106725	4193	/**
Kojto	122:f9eeca106725	4194	* @brief Disable MSI ready interrupt
Kojto	122:f9eeca106725	4195	* @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
Kojto	122:f9eeca106725	4196	* @retval None
Kojto	122:f9eeca106725	4197	*/
Kojto	122:f9eeca106725	4198	__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
Kojto	122:f9eeca106725	4199	{
Kojto	122:f9eeca106725	4200	CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
Kojto	122:f9eeca106725	4201	}
Kojto	122:f9eeca106725	4202
Kojto	122:f9eeca106725	4203	/**
Kojto	122:f9eeca106725	4204	* @brief Disable HSI ready interrupt
Kojto	122:f9eeca106725	4205	* @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
Kojto	122:f9eeca106725	4206	* @retval None
Kojto	122:f9eeca106725	4207	*/
Kojto	122:f9eeca106725	4208	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
Kojto	122:f9eeca106725	4209	{
Kojto	122:f9eeca106725	4210	CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
Kojto	122:f9eeca106725	4211	}
Kojto	122:f9eeca106725	4212
Kojto	122:f9eeca106725	4213	/**
Kojto	122:f9eeca106725	4214	* @brief Disable HSE ready interrupt
Kojto	122:f9eeca106725	4215	* @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
Kojto	122:f9eeca106725	4216	* @retval None
Kojto	122:f9eeca106725	4217	*/
Kojto	122:f9eeca106725	4218	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
Kojto	122:f9eeca106725	4219	{
Kojto	122:f9eeca106725	4220	CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
Kojto	122:f9eeca106725	4221	}
Kojto	122:f9eeca106725	4222
Kojto	122:f9eeca106725	4223	/**
Kojto	122:f9eeca106725	4224	* @brief Disable PLL ready interrupt
Kojto	122:f9eeca106725	4225	* @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
Kojto	122:f9eeca106725	4226	* @retval None
Kojto	122:f9eeca106725	4227	*/
Kojto	122:f9eeca106725	4228	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
Kojto	122:f9eeca106725	4229	{
Kojto	122:f9eeca106725	4230	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
Kojto	122:f9eeca106725	4231	}
Kojto	122:f9eeca106725	4232
Kojto	122:f9eeca106725	4233	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	4234	/**
Kojto	122:f9eeca106725	4235	* @brief Disable HSI48 ready interrupt
Kojto	122:f9eeca106725	4236	* @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
Kojto	122:f9eeca106725	4237	* @retval None
Kojto	122:f9eeca106725	4238	*/
Kojto	122:f9eeca106725	4239	__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
Kojto	122:f9eeca106725	4240	{
Kojto	122:f9eeca106725	4241	CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
Kojto	122:f9eeca106725	4242	}
Kojto	122:f9eeca106725	4243	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	4244
Kojto	122:f9eeca106725	4245	/**
Kojto	122:f9eeca106725	4246	* @brief Disable PLLSAI1 ready interrupt
Kojto	122:f9eeca106725	4247	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
Kojto	122:f9eeca106725	4248	* @retval None
Kojto	122:f9eeca106725	4249	*/
Kojto	122:f9eeca106725	4250	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
Kojto	122:f9eeca106725	4251	{
Kojto	122:f9eeca106725	4252	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
Kojto	122:f9eeca106725	4253	}
Kojto	122:f9eeca106725	4254
Kojto	122:f9eeca106725	4255	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	4256	/**
Kojto	122:f9eeca106725	4257	* @brief Disable PLLSAI2 ready interrupt
Kojto	122:f9eeca106725	4258	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY
Kojto	122:f9eeca106725	4259	* @retval None
Kojto	122:f9eeca106725	4260	*/
Kojto	122:f9eeca106725	4261	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
Kojto	122:f9eeca106725	4262	{
Kojto	122:f9eeca106725	4263	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
Kojto	122:f9eeca106725	4264	}
Kojto	122:f9eeca106725	4265
Kojto	122:f9eeca106725	4266	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	4267	/**
Kojto	122:f9eeca106725	4268	* @brief Disable LSE clock security system interrupt
Kojto	122:f9eeca106725	4269	* @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
Kojto	122:f9eeca106725	4270	* @retval None
Kojto	122:f9eeca106725	4271	*/
Kojto	122:f9eeca106725	4272	__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
Kojto	122:f9eeca106725	4273	{
Kojto	122:f9eeca106725	4274	CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
Kojto	122:f9eeca106725	4275	}
Kojto	122:f9eeca106725	4276
Kojto	122:f9eeca106725	4277	/**
Kojto	122:f9eeca106725	4278	* @brief Checks if LSI ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4279	* @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
Kojto	122:f9eeca106725	4280	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4281	*/
Kojto	122:f9eeca106725	4282	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
Kojto	122:f9eeca106725	4283	{
Kojto	122:f9eeca106725	4284	return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE));
Kojto	122:f9eeca106725	4285	}
Kojto	122:f9eeca106725	4286
Kojto	122:f9eeca106725	4287	/**
Kojto	122:f9eeca106725	4288	* @brief Checks if LSE ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4289	* @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
Kojto	122:f9eeca106725	4290	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4291	*/
Kojto	122:f9eeca106725	4292	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
Kojto	122:f9eeca106725	4293	{
Kojto	122:f9eeca106725	4294	return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE));
Kojto	122:f9eeca106725	4295	}
Kojto	122:f9eeca106725	4296
Kojto	122:f9eeca106725	4297	/**
Kojto	122:f9eeca106725	4298	* @brief Checks if MSI ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4299	* @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
Kojto	122:f9eeca106725	4300	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4301	*/
Kojto	122:f9eeca106725	4302	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
Kojto	122:f9eeca106725	4303	{
Kojto	122:f9eeca106725	4304	return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE));
Kojto	122:f9eeca106725	4305	}
Kojto	122:f9eeca106725	4306
Kojto	122:f9eeca106725	4307	/**
Kojto	122:f9eeca106725	4308	* @brief Checks if HSI ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4309	* @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
Kojto	122:f9eeca106725	4310	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4311	*/
Kojto	122:f9eeca106725	4312	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
Kojto	122:f9eeca106725	4313	{
Kojto	122:f9eeca106725	4314	return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE));
Kojto	122:f9eeca106725	4315	}
Kojto	122:f9eeca106725	4316
Kojto	122:f9eeca106725	4317	/**
Kojto	122:f9eeca106725	4318	* @brief Checks if HSE ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4319	* @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
Kojto	122:f9eeca106725	4320	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4321	*/
Kojto	122:f9eeca106725	4322	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
Kojto	122:f9eeca106725	4323	{
Kojto	122:f9eeca106725	4324	return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE));
Kojto	122:f9eeca106725	4325	}
Kojto	122:f9eeca106725	4326
Kojto	122:f9eeca106725	4327	/**
Kojto	122:f9eeca106725	4328	* @brief Checks if PLL ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4329	* @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
Kojto	122:f9eeca106725	4330	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4331	*/
Kojto	122:f9eeca106725	4332	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
Kojto	122:f9eeca106725	4333	{
Kojto	122:f9eeca106725	4334	return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE));
Kojto	122:f9eeca106725	4335	}
Kojto	122:f9eeca106725	4336
Kojto	122:f9eeca106725	4337	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	4338	/**
Kojto	122:f9eeca106725	4339	* @brief Checks if HSI48 ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4340	* @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
Kojto	122:f9eeca106725	4341	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4342	*/
Kojto	122:f9eeca106725	4343	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
Kojto	122:f9eeca106725	4344	{
Kojto	122:f9eeca106725	4345	return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE));
Kojto	122:f9eeca106725	4346	}
Kojto	122:f9eeca106725	4347	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	4348
Kojto	122:f9eeca106725	4349	/**
Kojto	122:f9eeca106725	4350	* @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4351	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
Kojto	122:f9eeca106725	4352	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4353	*/
Kojto	122:f9eeca106725	4354	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
Kojto	122:f9eeca106725	4355	{
Kojto	122:f9eeca106725	4356	return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE));
Kojto	122:f9eeca106725	4357	}
Kojto	122:f9eeca106725	4358
Kojto	122:f9eeca106725	4359	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	4360	/**
Kojto	122:f9eeca106725	4361	* @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4362	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY
Kojto	122:f9eeca106725	4363	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4364	*/
Kojto	122:f9eeca106725	4365	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
Kojto	122:f9eeca106725	4366	{
Kojto	122:f9eeca106725	4367	return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE));
Kojto	122:f9eeca106725	4368	}
Kojto	122:f9eeca106725	4369
Kojto	122:f9eeca106725	4370	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	4371	/**
Kojto	122:f9eeca106725	4372	* @brief Checks if LSECSS interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4373	* @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
Kojto	122:f9eeca106725	4374	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4375	*/
Kojto	122:f9eeca106725	4376	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
Kojto	122:f9eeca106725	4377	{
Kojto	122:f9eeca106725	4378	return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE));
Kojto	122:f9eeca106725	4379	}
Kojto	122:f9eeca106725	4380
Kojto	122:f9eeca106725	4381	/**
Kojto	122:f9eeca106725	4382	* @}
Kojto	122:f9eeca106725	4383	*/
Kojto	122:f9eeca106725	4384
Kojto	122:f9eeca106725	4385	#if defined(USE_FULL_LL_DRIVER)
Kojto	122:f9eeca106725	4386	/** @defgroup RCC_LL_EF_Init De-initialization function
Kojto	122:f9eeca106725	4387	* @{
Kojto	122:f9eeca106725	4388	*/
Kojto	122:f9eeca106725	4389	ErrorStatus LL_RCC_DeInit(void);
Kojto	122:f9eeca106725	4390	/**
Kojto	122:f9eeca106725	4391	* @}
Kojto	122:f9eeca106725	4392	*/
Kojto	122:f9eeca106725	4393
Kojto	122:f9eeca106725	4394	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
Kojto	122:f9eeca106725	4395	* @{
Kojto	122:f9eeca106725	4396	*/
Kojto	122:f9eeca106725	4397	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
Kojto	122:f9eeca106725	4398	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
Kojto	122:f9eeca106725	4399	#if defined(UART4) \|\| defined(UART5)
Kojto	122:f9eeca106725	4400	uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
Kojto	122:f9eeca106725	4401	#endif /* UART4 \|\| UART5 */
Kojto	122:f9eeca106725	4402	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
Kojto	122:f9eeca106725	4403	uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
Kojto	122:f9eeca106725	4404	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
Kojto	122:f9eeca106725	4405	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
Kojto	122:f9eeca106725	4406	uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
Kojto	122:f9eeca106725	4407	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
Kojto	122:f9eeca106725	4408	#if defined(USB_OTG_FS) \|\| defined(USB)
Kojto	122:f9eeca106725	4409	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
Kojto	122:f9eeca106725	4410	#endif /* USB_OTG_FS \|\| USB */
Kojto	122:f9eeca106725	4411	uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
Kojto	122:f9eeca106725	4412	uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource);
Kojto	122:f9eeca106725	4413	#if defined(DFSDM1_Channel0)
Kojto	122:f9eeca106725	4414	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
Kojto	122:f9eeca106725	4415	#endif /* DFSDM1_Channel0 */
Kojto	122:f9eeca106725	4416	/**
Kojto	122:f9eeca106725	4417	* @}
Kojto	122:f9eeca106725	4418	*/
Kojto	122:f9eeca106725	4419	#endif /* USE_FULL_LL_DRIVER */
Kojto	122:f9eeca106725	4420
Kojto	122:f9eeca106725	4421	/**
Kojto	122:f9eeca106725	4422	* @}
Kojto	122:f9eeca106725	4423	*/
Kojto	122:f9eeca106725	4424
Kojto	122:f9eeca106725	4425	/**
Kojto	122:f9eeca106725	4426	* @}
Kojto	122:f9eeca106725	4427	*/
Kojto	122:f9eeca106725	4428
Kojto	122:f9eeca106725	4429	#endif /* defined(RCC) */
Kojto	122:f9eeca106725	4430
Kojto	122:f9eeca106725	4431	/**
Kojto	122:f9eeca106725	4432	* @}
Kojto	122:f9eeca106725	4433	*/
Kojto	122:f9eeca106725	4434
Kojto	122:f9eeca106725	4435	#ifdef __cplusplus
Kojto	122:f9eeca106725	4436	}
Kojto	122:f9eeca106725	4437	#endif
Kojto	122:f9eeca106725	4438
Kojto	122:f9eeca106725	4439	#endif /* __STM32L4xx_LL_RCC_H */
Kojto	122:f9eeca106725	4440
Kojto	122:f9eeca106725	4441	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/