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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h@145:64910690c574, 2017-06-21 (annotated)

Committer:: AnnaBridge
Date:: Wed Jun 21 17:31:38 2017 +0100
Revision:: 145:64910690c574
Parent:: 128:9bcdf88f62b0

Release 145 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/**
Kojto	122:f9eeca106725	2	******************************************************************************
Kojto	122:f9eeca106725	3	* @file stm32l4xx_ll_rcc.h
Kojto	122:f9eeca106725	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @version V1.7.1
AnnaBridge	145:64910690c574	6	* @date 21-April-2017
Kojto	122:f9eeca106725	7	* @brief Header file of RCC LL module.
Kojto	122:f9eeca106725	8	******************************************************************************
Kojto	122:f9eeca106725	9	* @attention
Kojto	122:f9eeca106725	10	*
AnnaBridge	145:64910690c574	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
Kojto	122:f9eeca106725	12	*
Kojto	122:f9eeca106725	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	122:f9eeca106725	14	* are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	122:f9eeca106725	16	* this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	122:f9eeca106725	18	* this list of conditions and the following disclaimer in the documentation
Kojto	122:f9eeca106725	19	* and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	122:f9eeca106725	21	* may be used to endorse or promote products derived from this software
Kojto	122:f9eeca106725	22	* without specific prior written permission.
Kojto	122:f9eeca106725	23	*
Kojto	122:f9eeca106725	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	122:f9eeca106725	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	122:f9eeca106725	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	122:f9eeca106725	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	122:f9eeca106725	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	122:f9eeca106725	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	122:f9eeca106725	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	122:f9eeca106725	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	34	*
Kojto	122:f9eeca106725	35	******************************************************************************
Kojto	122:f9eeca106725	36	*/
Kojto	122:f9eeca106725	37
Kojto	122:f9eeca106725	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	122:f9eeca106725	39	#ifndef __STM32L4xx_LL_RCC_H
Kojto	122:f9eeca106725	40	#define __STM32L4xx_LL_RCC_H
Kojto	122:f9eeca106725	41
Kojto	122:f9eeca106725	42	#ifdef __cplusplus
Kojto	122:f9eeca106725	43	extern "C" {
Kojto	122:f9eeca106725	44	#endif
Kojto	122:f9eeca106725	45
Kojto	122:f9eeca106725	46	/* Includes ------------------------------------------------------------------*/
Kojto	122:f9eeca106725	47	#include "stm32l4xx.h"
Kojto	122:f9eeca106725	48
Kojto	122:f9eeca106725	49	/** @addtogroup STM32L4xx_LL_Driver
Kojto	122:f9eeca106725	50	* @{
Kojto	122:f9eeca106725	51	*/
Kojto	122:f9eeca106725	52
Kojto	122:f9eeca106725	53	#if defined(RCC)
Kojto	122:f9eeca106725	54
Kojto	122:f9eeca106725	55	/** @defgroup RCC_LL RCC
Kojto	122:f9eeca106725	56	* @{
Kojto	122:f9eeca106725	57	*/
Kojto	122:f9eeca106725	58
Kojto	122:f9eeca106725	59	/* Private types -------------------------------------------------------------*/
Kojto	122:f9eeca106725	60	/* Private variables ---------------------------------------------------------*/
Kojto	122:f9eeca106725	61	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
Kojto	122:f9eeca106725	62	* @{
Kojto	122:f9eeca106725	63	*/
Kojto	122:f9eeca106725	64
Kojto	122:f9eeca106725	65	static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
Kojto	122:f9eeca106725	66
Kojto	122:f9eeca106725	67	/**
Kojto	122:f9eeca106725	68	* @}
Kojto	122:f9eeca106725	69	*/
Kojto	122:f9eeca106725	70
Kojto	122:f9eeca106725	71	/* Private constants ---------------------------------------------------------*/
Kojto	122:f9eeca106725	72	/** @defgroup RCC_LL_Private_Constants RCC Private Constants
Kojto	122:f9eeca106725	73	* @{
Kojto	122:f9eeca106725	74	*/
AnnaBridge	145:64910690c574	75	/* Defines used to perform offsets*/
AnnaBridge	145:64910690c574	76	/* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
AnnaBridge	145:64910690c574	77	#define RCC_OFFSET_CCIPR 0U
AnnaBridge	145:64910690c574	78	#define RCC_OFFSET_CCIPR2 0x14U
Kojto	122:f9eeca106725	79
Kojto	122:f9eeca106725	80	/**
Kojto	122:f9eeca106725	81	* @}
Kojto	122:f9eeca106725	82	*/
Kojto	122:f9eeca106725	83
Kojto	122:f9eeca106725	84	/* Private macros ------------------------------------------------------------*/
Kojto	122:f9eeca106725	85	#if defined(USE_FULL_LL_DRIVER)
Kojto	122:f9eeca106725	86	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
Kojto	122:f9eeca106725	87	* @{
Kojto	122:f9eeca106725	88	*/
Kojto	122:f9eeca106725	89	/**
Kojto	122:f9eeca106725	90	* @}
Kojto	122:f9eeca106725	91	*/
Kojto	122:f9eeca106725	92	#endif /USE_FULL_LL_DRIVER/
Kojto	122:f9eeca106725	93	/* Exported types ------------------------------------------------------------*/
Kojto	122:f9eeca106725	94	#if defined(USE_FULL_LL_DRIVER)
Kojto	122:f9eeca106725	95	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
Kojto	122:f9eeca106725	96	* @{
Kojto	122:f9eeca106725	97	*/
Kojto	122:f9eeca106725	98
Kojto	122:f9eeca106725	99	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
Kojto	122:f9eeca106725	100	* @{
Kojto	122:f9eeca106725	101	*/
Kojto	122:f9eeca106725	102
Kojto	122:f9eeca106725	103	/**
Kojto	122:f9eeca106725	104	* @brief RCC Clocks Frequency Structure
Kojto	122:f9eeca106725	105	*/
Kojto	122:f9eeca106725	106	typedef struct
Kojto	122:f9eeca106725	107	{
Kojto	122:f9eeca106725	108	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
Kojto	122:f9eeca106725	109	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
Kojto	122:f9eeca106725	110	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
Kojto	122:f9eeca106725	111	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
Kojto	122:f9eeca106725	112	} LL_RCC_ClocksTypeDef;
Kojto	122:f9eeca106725	113
Kojto	122:f9eeca106725	114	/**
Kojto	122:f9eeca106725	115	* @}
Kojto	122:f9eeca106725	116	*/
Kojto	122:f9eeca106725	117
Kojto	122:f9eeca106725	118	/**
Kojto	122:f9eeca106725	119	* @}
Kojto	122:f9eeca106725	120	*/
Kojto	122:f9eeca106725	121	#endif /* USE_FULL_LL_DRIVER */
Kojto	122:f9eeca106725	122
Kojto	122:f9eeca106725	123	/* Exported constants --------------------------------------------------------*/
Kojto	122:f9eeca106725	124	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
Kojto	122:f9eeca106725	125	* @{
Kojto	122:f9eeca106725	126	*/
Kojto	122:f9eeca106725	127
Kojto	122:f9eeca106725	128	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
Kojto	122:f9eeca106725	129	* @brief Defines used to adapt values of different oscillators
Kojto	122:f9eeca106725	130	* @note These values could be modified in the user environment according to
Kojto	122:f9eeca106725	131	* HW set-up.
Kojto	122:f9eeca106725	132	* @{
Kojto	122:f9eeca106725	133	*/
Kojto	122:f9eeca106725	134	#if !defined (HSE_VALUE)
AnnaBridge	145:64910690c574	135	#define HSE_VALUE 8000000U /!< Value of the HSE oscillator in Hz /
Kojto	122:f9eeca106725	136	#endif /* HSE_VALUE */
Kojto	122:f9eeca106725	137
Kojto	122:f9eeca106725	138	#if !defined (HSI_VALUE)
AnnaBridge	145:64910690c574	139	#define HSI_VALUE 16000000U /!< Value of the HSI oscillator in Hz /
Kojto	122:f9eeca106725	140	#endif /* HSI_VALUE */
Kojto	122:f9eeca106725	141
Kojto	122:f9eeca106725	142	#if !defined (LSE_VALUE)
AnnaBridge	145:64910690c574	143	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
Kojto	122:f9eeca106725	144	#endif /* LSE_VALUE */
Kojto	122:f9eeca106725	145
Kojto	122:f9eeca106725	146	#if !defined (LSI_VALUE)
AnnaBridge	145:64910690c574	147	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
Kojto	122:f9eeca106725	148	#endif /* LSI_VALUE */
AnnaBridge	145:64910690c574	149
Kojto	122:f9eeca106725	150	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	151	#if !defined (HSI48_VALUE)
AnnaBridge	145:64910690c574	152	#define HSI48_VALUE 48000000U /!< Value of the HSI48 oscillator in Hz /
Kojto	122:f9eeca106725	153	#endif /* HSI48_VALUE */
Kojto	122:f9eeca106725	154	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	155	/**
Kojto	122:f9eeca106725	156	* @}
Kojto	122:f9eeca106725	157	*/
Kojto	122:f9eeca106725	158
Kojto	122:f9eeca106725	159	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
Kojto	122:f9eeca106725	160	* @brief Flags defines which can be used with LL_RCC_WriteReg function
Kojto	122:f9eeca106725	161	* @{
Kojto	122:f9eeca106725	162	*/
Kojto	122:f9eeca106725	163	#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /!< LSI Ready Interrupt Clear /
Kojto	122:f9eeca106725	164	#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /!< LSE Ready Interrupt Clear /
Kojto	122:f9eeca106725	165	#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /!< MSI Ready Interrupt Clear /
Kojto	122:f9eeca106725	166	#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /!< HSI Ready Interrupt Clear /
Kojto	122:f9eeca106725	167	#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /!< HSE Ready Interrupt Clear /
Kojto	122:f9eeca106725	168	#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /!< PLL Ready Interrupt Clear /
Kojto	122:f9eeca106725	169	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	170	#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /!< HSI48 Ready Interrupt Clear /
Kojto	122:f9eeca106725	171	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	172	#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /!< PLLSAI1 Ready Interrupt Clear /
Kojto	122:f9eeca106725	173	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	174	#define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /!< PLLSAI2 Ready Interrupt Clear /
Kojto	122:f9eeca106725	175	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	176	#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /!< LSE Clock Security System Interrupt Clear /
Kojto	122:f9eeca106725	177	#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /!< Clock Security System Interrupt Clear /
Kojto	122:f9eeca106725	178	/**
Kojto	122:f9eeca106725	179	* @}
Kojto	122:f9eeca106725	180	*/
Kojto	122:f9eeca106725	181
Kojto	122:f9eeca106725	182	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
Kojto	122:f9eeca106725	183	* @brief Flags defines which can be used with LL_RCC_ReadReg function
Kojto	122:f9eeca106725	184	* @{
Kojto	122:f9eeca106725	185	*/
Kojto	122:f9eeca106725	186	#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /!< LSI Ready Interrupt flag /
Kojto	122:f9eeca106725	187	#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /!< LSE Ready Interrupt flag /
Kojto	122:f9eeca106725	188	#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /!< MSI Ready Interrupt flag /
Kojto	122:f9eeca106725	189	#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /!< HSI Ready Interrupt flag /
Kojto	122:f9eeca106725	190	#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /!< HSE Ready Interrupt flag /
Kojto	122:f9eeca106725	191	#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /!< PLL Ready Interrupt flag /
Kojto	122:f9eeca106725	192	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	193	#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
Kojto	122:f9eeca106725	194	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	195	#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /!< PLLSAI1 Ready Interrupt flag /
Kojto	122:f9eeca106725	196	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	197	#define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /!< PLLSAI2 Ready Interrupt flag /
Kojto	122:f9eeca106725	198	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	199	#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /!< LSE Clock Security System Interrupt flag /
Kojto	122:f9eeca106725	200	#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /!< Clock Security System Interrupt flag /
Kojto	122:f9eeca106725	201	#define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /!< Firewall reset flag /
Kojto	122:f9eeca106725	202	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
Kojto	122:f9eeca106725	203	#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /!< OBL reset flag /
Kojto	122:f9eeca106725	204	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
Kojto	122:f9eeca106725	205	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
Kojto	122:f9eeca106725	206	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
Kojto	122:f9eeca106725	207	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
Kojto	122:f9eeca106725	208	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /!< BOR reset flag /
Kojto	122:f9eeca106725	209	/**
Kojto	122:f9eeca106725	210	* @}
Kojto	122:f9eeca106725	211	*/
Kojto	122:f9eeca106725	212
Kojto	122:f9eeca106725	213	/** @defgroup RCC_LL_EC_IT IT Defines
Kojto	122:f9eeca106725	214	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
Kojto	122:f9eeca106725	215	* @{
Kojto	122:f9eeca106725	216	*/
Kojto	122:f9eeca106725	217	#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /!< LSI Ready Interrupt Enable /
Kojto	122:f9eeca106725	218	#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /!< LSE Ready Interrupt Enable /
Kojto	122:f9eeca106725	219	#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /!< MSI Ready Interrupt Enable /
Kojto	122:f9eeca106725	220	#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /!< HSI Ready Interrupt Enable /
Kojto	122:f9eeca106725	221	#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /!< HSE Ready Interrupt Enable /
Kojto	122:f9eeca106725	222	#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /!< PLL Ready Interrupt Enable /
Kojto	122:f9eeca106725	223	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	224	#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /!< HSI48 Ready Interrupt Enable /
Kojto	122:f9eeca106725	225	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	226	#define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /!< PLLSAI1 Ready Interrupt Enable /
Kojto	122:f9eeca106725	227	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	228	#define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /!< PLLSAI2 Ready Interrupt Enable /
Kojto	122:f9eeca106725	229	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	230	#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /!< LSE CSS Interrupt Enable /
Kojto	122:f9eeca106725	231	/**
Kojto	122:f9eeca106725	232	* @}
Kojto	122:f9eeca106725	233	*/
Kojto	122:f9eeca106725	234
Kojto	122:f9eeca106725	235	/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
Kojto	122:f9eeca106725	236	* @{
Kojto	122:f9eeca106725	237	*/
AnnaBridge	145:64910690c574	238	#define LL_RCC_LSEDRIVE_LOW 0x00000000U /!< Xtal mode lower driving capability /
Kojto	122:f9eeca106725	239	#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /!< Xtal mode medium low driving capability /
Kojto	122:f9eeca106725	240	#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /!< Xtal mode medium high driving capability /
Kojto	122:f9eeca106725	241	#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
Kojto	122:f9eeca106725	242	/**
Kojto	122:f9eeca106725	243	* @}
Kojto	122:f9eeca106725	244	*/
Kojto	122:f9eeca106725	245
Kojto	122:f9eeca106725	246	/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
Kojto	122:f9eeca106725	247	* @{
Kojto	122:f9eeca106725	248	*/
Kojto	122:f9eeca106725	249	#define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /!< MSI = 100 KHz /
Kojto	122:f9eeca106725	250	#define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /!< MSI = 200 KHz /
Kojto	122:f9eeca106725	251	#define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /!< MSI = 400 KHz /
Kojto	122:f9eeca106725	252	#define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /!< MSI = 800 KHz /
Kojto	122:f9eeca106725	253	#define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /!< MSI = 1 MHz /
Kojto	122:f9eeca106725	254	#define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /!< MSI = 2 MHz /
Kojto	122:f9eeca106725	255	#define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /!< MSI = 4 MHz /
Kojto	122:f9eeca106725	256	#define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /!< MSI = 8 MHz /
Kojto	122:f9eeca106725	257	#define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /!< MSI = 16 MHz /
Kojto	122:f9eeca106725	258	#define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /!< MSI = 24 MHz /
Kojto	122:f9eeca106725	259	#define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /!< MSI = 32 MHz /
Kojto	122:f9eeca106725	260	#define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /!< MSI = 48 MHz /
Kojto	122:f9eeca106725	261	/**
Kojto	122:f9eeca106725	262	* @}
Kojto	122:f9eeca106725	263	*/
Kojto	122:f9eeca106725	264
Kojto	122:f9eeca106725	265	/** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
Kojto	122:f9eeca106725	266	* @{
Kojto	122:f9eeca106725	267	*/
Kojto	122:f9eeca106725	268	#define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /!< MSI = 1 MHz /
Kojto	122:f9eeca106725	269	#define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /!< MSI = 2 MHz /
Kojto	122:f9eeca106725	270	#define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /!< MSI = 4 MHz /
Kojto	122:f9eeca106725	271	#define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /!< MSI = 8 MHz /
Kojto	122:f9eeca106725	272	/**
Kojto	122:f9eeca106725	273	* @}
Kojto	122:f9eeca106725	274	*/
Kojto	122:f9eeca106725	275
Kojto	122:f9eeca106725	276	/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
Kojto	122:f9eeca106725	277	* @{
Kojto	122:f9eeca106725	278	*/
AnnaBridge	145:64910690c574	279	#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /!< LSI selection for low speed clock /
Kojto	122:f9eeca106725	280	#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /!< LSE selection for low speed clock /
Kojto	122:f9eeca106725	281	/**
Kojto	122:f9eeca106725	282	* @}
Kojto	122:f9eeca106725	283	*/
Kojto	122:f9eeca106725	284
Kojto	122:f9eeca106725	285	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
Kojto	122:f9eeca106725	286	* @{
Kojto	122:f9eeca106725	287	*/
Kojto	122:f9eeca106725	288	#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
Kojto	122:f9eeca106725	289	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
Kojto	122:f9eeca106725	290	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
Kojto	122:f9eeca106725	291	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
Kojto	122:f9eeca106725	292	/**
Kojto	122:f9eeca106725	293	* @}
Kojto	122:f9eeca106725	294	*/
Kojto	122:f9eeca106725	295
Kojto	122:f9eeca106725	296	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
Kojto	122:f9eeca106725	297	* @{
Kojto	122:f9eeca106725	298	*/
Kojto	122:f9eeca106725	299	#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
Kojto	122:f9eeca106725	300	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
Kojto	122:f9eeca106725	301	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
Kojto	122:f9eeca106725	302	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
Kojto	122:f9eeca106725	303	/**
Kojto	122:f9eeca106725	304	* @}
Kojto	122:f9eeca106725	305	*/
Kojto	122:f9eeca106725	306
Kojto	122:f9eeca106725	307	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
Kojto	122:f9eeca106725	308	* @{
Kojto	122:f9eeca106725	309	*/
Kojto	122:f9eeca106725	310	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
Kojto	122:f9eeca106725	311	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
Kojto	122:f9eeca106725	312	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
Kojto	122:f9eeca106725	313	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
Kojto	122:f9eeca106725	314	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
Kojto	122:f9eeca106725	315	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
Kojto	122:f9eeca106725	316	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
Kojto	122:f9eeca106725	317	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
Kojto	122:f9eeca106725	318	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
Kojto	122:f9eeca106725	319	/**
Kojto	122:f9eeca106725	320	* @}
Kojto	122:f9eeca106725	321	*/
Kojto	122:f9eeca106725	322
Kojto	122:f9eeca106725	323	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
Kojto	122:f9eeca106725	324	* @{
Kojto	122:f9eeca106725	325	*/
Kojto	122:f9eeca106725	326	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
Kojto	122:f9eeca106725	327	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
Kojto	122:f9eeca106725	328	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
Kojto	122:f9eeca106725	329	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
Kojto	122:f9eeca106725	330	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
Kojto	122:f9eeca106725	331	/**
Kojto	122:f9eeca106725	332	* @}
Kojto	122:f9eeca106725	333	*/
AnnaBridge	145:64910690c574	334
Kojto	122:f9eeca106725	335	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
Kojto	122:f9eeca106725	336	* @{
Kojto	122:f9eeca106725	337	*/
Kojto	122:f9eeca106725	338	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
Kojto	122:f9eeca106725	339	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
Kojto	122:f9eeca106725	340	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
Kojto	122:f9eeca106725	341	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
Kojto	122:f9eeca106725	342	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
Kojto	122:f9eeca106725	343	/**
Kojto	122:f9eeca106725	344	* @}
Kojto	122:f9eeca106725	345	*/
AnnaBridge	145:64910690c574	346
Kojto	122:f9eeca106725	347	/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
Kojto	122:f9eeca106725	348	* @{
Kojto	122:f9eeca106725	349	*/
AnnaBridge	145:64910690c574	350	#define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /!< MSI selection after wake-up from STOP /
Kojto	122:f9eeca106725	351	#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
Kojto	122:f9eeca106725	352	/**
Kojto	122:f9eeca106725	353	* @}
Kojto	122:f9eeca106725	354	*/
Kojto	122:f9eeca106725	355
Kojto	122:f9eeca106725	356	/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
Kojto	122:f9eeca106725	357	* @{
Kojto	122:f9eeca106725	358	*/
AnnaBridge	145:64910690c574	359	#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /!< MCO output disabled, no clock on MCO /
Kojto	122:f9eeca106725	360	#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /!< SYSCLK selection as MCO1 source /
Kojto	122:f9eeca106725	361	#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /!< MSI selection as MCO1 source /
Kojto	122:f9eeca106725	362	#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1) /!< HSI16 selection as MCO1 source /
Kojto	122:f9eeca106725	363	#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /!< HSE selection as MCO1 source /
Kojto	122:f9eeca106725	364	#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2) /!< Main PLL selection as MCO1 source /
Kojto	122:f9eeca106725	365	#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSI selection as MCO1 source /
Kojto	122:f9eeca106725	366	#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSE selection as MCO1 source /
Kojto	122:f9eeca106725	367	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	368	#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /!< HSI48 selection as MCO1 source /
Kojto	122:f9eeca106725	369	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	370	/**
Kojto	122:f9eeca106725	371	* @}
Kojto	122:f9eeca106725	372	*/
Kojto	122:f9eeca106725	373
Kojto	122:f9eeca106725	374	/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
Kojto	122:f9eeca106725	375	* @{
Kojto	122:f9eeca106725	376	*/
Kojto	122:f9eeca106725	377	#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /!< MCO not divided /
Kojto	122:f9eeca106725	378	#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO divided by 2 /
Kojto	122:f9eeca106725	379	#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO divided by 4 /
Kojto	122:f9eeca106725	380	#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO divided by 8 /
Kojto	122:f9eeca106725	381	#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO divided by 16 /
Kojto	122:f9eeca106725	382	/**
Kojto	122:f9eeca106725	383	* @}
Kojto	122:f9eeca106725	384	*/
Kojto	122:f9eeca106725	385
Kojto	122:f9eeca106725	386	#if defined(USE_FULL_LL_DRIVER)
Kojto	122:f9eeca106725	387	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
Kojto	122:f9eeca106725	388	* @{
Kojto	122:f9eeca106725	389	*/
AnnaBridge	145:64910690c574	390	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
AnnaBridge	145:64910690c574	391	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
Kojto	122:f9eeca106725	392	/**
Kojto	122:f9eeca106725	393	* @}
Kojto	122:f9eeca106725	394	*/
Kojto	122:f9eeca106725	395	#endif /* USE_FULL_LL_DRIVER */
Kojto	122:f9eeca106725	396
Kojto	122:f9eeca106725	397	/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
Kojto	122:f9eeca106725	398	* @{
Kojto	122:f9eeca106725	399	*/
AnnaBridge	145:64910690c574	400	#define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /!< PCLK2 clock used as USART1 clock source /
AnnaBridge	145:64910690c574	401	#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL_0) /!< SYSCLK clock used as USART1 clock source /
AnnaBridge	145:64910690c574	402	#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL_1) /!< HSI clock used as USART1 clock source /
AnnaBridge	145:64910690c574	403	#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL) /!< LSE clock used as USART1 clock source /
AnnaBridge	145:64910690c574	404	#define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /!< PCLK1 clock used as USART2 clock source /
AnnaBridge	145:64910690c574	405	#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL_0) /!< SYSCLK clock used as USART2 clock source /
AnnaBridge	145:64910690c574	406	#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL_1) /!< HSI clock used as USART2 clock source /
AnnaBridge	145:64910690c574	407	#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL) /!< LSE clock used as USART2 clock source /
Kojto	122:f9eeca106725	408	#if defined(RCC_CCIPR_USART3SEL)
AnnaBridge	145:64910690c574	409	#define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /!< PCLK1 clock used as USART3 clock source /
AnnaBridge	145:64910690c574	410	#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL_0) /!< SYSCLK clock used as USART3 clock source /
AnnaBridge	145:64910690c574	411	#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL_1) /!< HSI clock used as USART3 clock source /
AnnaBridge	145:64910690c574	412	#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL) /!< LSE clock used as USART3 clock source /
Kojto	122:f9eeca106725	413	#endif /* RCC_CCIPR_USART3SEL */
Kojto	122:f9eeca106725	414	/**
Kojto	122:f9eeca106725	415	* @}
Kojto	122:f9eeca106725	416	*/
Kojto	122:f9eeca106725	417
Kojto	122:f9eeca106725	418	#if defined(RCC_CCIPR_UART4SEL) \|\| defined(RCC_CCIPR_UART5SEL)
Kojto	122:f9eeca106725	419	/** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
Kojto	122:f9eeca106725	420	* @{
Kojto	122:f9eeca106725	421	*/
Kojto	122:f9eeca106725	422	#if defined(RCC_CCIPR_UART4SEL)
AnnaBridge	145:64910690c574	423	#define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /!< PCLK1 clock used as UART4 clock source /
AnnaBridge	145:64910690c574	424	#define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) \| RCC_CCIPR_UART4SEL_0) /!< SYSCLK clock used as UART4 clock source /
AnnaBridge	145:64910690c574	425	#define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) \| RCC_CCIPR_UART4SEL_1) /!< HSI clock used as UART4 clock source /
AnnaBridge	145:64910690c574	426	#define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) \| RCC_CCIPR_UART4SEL) /!< LSE clock used as UART4 clock source /
Kojto	122:f9eeca106725	427	#endif /* RCC_CCIPR_UART4SEL */
Kojto	122:f9eeca106725	428	#if defined(RCC_CCIPR_UART5SEL)
AnnaBridge	145:64910690c574	429	#define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /!< PCLK1 clock used as UART5 clock source /
AnnaBridge	145:64910690c574	430	#define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) \| RCC_CCIPR_UART5SEL_0) /!< SYSCLK clock used as UART5 clock source /
AnnaBridge	145:64910690c574	431	#define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) \| RCC_CCIPR_UART5SEL_1) /!< HSI clock used as UART5 clock source /
AnnaBridge	145:64910690c574	432	#define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) \| RCC_CCIPR_UART5SEL) /!< LSE clock used as UART5 clock source /
Kojto	122:f9eeca106725	433	#endif /* RCC_CCIPR_UART5SEL */
Kojto	122:f9eeca106725	434	/**
Kojto	122:f9eeca106725	435	* @}
Kojto	122:f9eeca106725	436	*/
Kojto	122:f9eeca106725	437	#endif /* RCC_CCIPR_UART4SEL \|\| RCC_CCIPR_UART5SEL */
Kojto	122:f9eeca106725	438
Kojto	122:f9eeca106725	439	/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
Kojto	122:f9eeca106725	440	* @{
Kojto	122:f9eeca106725	441	*/
AnnaBridge	145:64910690c574	442	#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as LPUART1 clock source /
Kojto	122:f9eeca106725	443	#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /!< SYSCLK clock used as LPUART1 clock source /
Kojto	122:f9eeca106725	444	#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /!< HSI clock used as LPUART1 clock source /
Kojto	122:f9eeca106725	445	#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /!< LSE clock used as LPUART1 clock source /
Kojto	122:f9eeca106725	446	/**
Kojto	122:f9eeca106725	447	* @}
Kojto	122:f9eeca106725	448	*/
Kojto	122:f9eeca106725	449
Kojto	122:f9eeca106725	450	/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
Kojto	122:f9eeca106725	451	* @{
Kojto	122:f9eeca106725	452	*/
AnnaBridge	145:64910690c574	453	#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U)) /!< PCLK1 clock used as I2C1 clock source /
AnnaBridge	145:64910690c574	454	#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /!< SYSCLK clock used as I2C1 clock source /
AnnaBridge	145:64910690c574	455	#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /!< HSI clock used as I2C1 clock source /
Kojto	122:f9eeca106725	456	#if defined(RCC_CCIPR_I2C2SEL)
AnnaBridge	145:64910690c574	457	#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U)) /!< PCLK1 clock used as I2C2 clock source /
AnnaBridge	145:64910690c574	458	#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /!< SYSCLK clock used as I2C2 clock source /
AnnaBridge	145:64910690c574	459	#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /!< HSI clock used as I2C2 clock source /
Kojto	122:f9eeca106725	460	#endif /* RCC_CCIPR_I2C2SEL */
AnnaBridge	145:64910690c574	461	#define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U)) /!< PCLK1 clock used as I2C3 clock source /
AnnaBridge	145:64910690c574	462	#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /!< SYSCLK clock used as I2C3 clock source /
AnnaBridge	145:64910690c574	463	#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /!< HSI clock used as I2C3 clock source /
AnnaBridge	145:64910690c574	464	#if defined(RCC_CCIPR2_I2C4SEL)
AnnaBridge	145:64910690c574	465	#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /!< PCLK1 clock used as I2C4 clock source /
AnnaBridge	145:64910690c574	466	#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U) \| (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /!< SYSCLK clock used as I2C4 clock source /
AnnaBridge	145:64910690c574	467	#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U) \| (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /!< HSI clock used as I2C4 clock source /
AnnaBridge	145:64910690c574	468	#endif /* RCC_CCIPR2_I2C4SEL */
Kojto	122:f9eeca106725	469	/**
Kojto	122:f9eeca106725	470	* @}
Kojto	122:f9eeca106725	471	*/
Kojto	122:f9eeca106725	472
Kojto	122:f9eeca106725	473	/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
Kojto	122:f9eeca106725	474	* @{
Kojto	122:f9eeca106725	475	*/
AnnaBridge	145:64910690c574	476	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM1SEL /!< PCLK1 clock used as LPTIM1 clock source /
AnnaBridge	145:64910690c574	477	#define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /!< LSI clock used as LPTIM1 clock source /
AnnaBridge	145:64910690c574	478	#define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /!< HSI clock used as LPTIM1 clock source /
AnnaBridge	145:64910690c574	479	#define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL >> 16U)) /!< LSE clock used as LPTIM1 clock source /
AnnaBridge	145:64910690c574	480	#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM2SEL /!< PCLK1 clock used as LPTIM2 clock source /
AnnaBridge	145:64910690c574	481	#define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /!< LSI clock used as LPTIM2 clock source /
AnnaBridge	145:64910690c574	482	#define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /!< HSI clock used as LPTIM2 clock source /
AnnaBridge	145:64910690c574	483	#define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL >> 16U)) /!< LSE clock used as LPTIM2 clock source /
Kojto	122:f9eeca106725	484	/**
Kojto	122:f9eeca106725	485	* @}
Kojto	122:f9eeca106725	486	*/
Kojto	122:f9eeca106725	487
Kojto	122:f9eeca106725	488	/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
Kojto	122:f9eeca106725	489	* @{
Kojto	122:f9eeca106725	490	*/
AnnaBridge	145:64910690c574	491	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /!< PLLSAI1 clock used as SAI1 clock source /
Kojto	122:f9eeca106725	492	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	145:64910690c574	493	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL_0 >> 16U)) /!< PLLSAI2 clock used as SAI1 clock source /
Kojto	122:f9eeca106725	494	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	145:64910690c574	495	#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL_1 >> 16U)) /!< PLL clock used as SAI1 clock source /
AnnaBridge	145:64910690c574	496	#define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL >> 16U)) /!< External input clock used as SAI1 clock source /
AnnaBridge	145:64910690c574	497
Kojto	122:f9eeca106725	498	#if defined(RCC_CCIPR_SAI2SEL)
AnnaBridge	145:64910690c574	499	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /!< PLLSAI1 clock used as SAI2 clock source /
Kojto	122:f9eeca106725	500	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	145:64910690c574	501	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL_0 >> 16U)) /!< PLLSAI2 clock used as SAI2 clock source /
Kojto	122:f9eeca106725	502	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	145:64910690c574	503	#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL_1 >> 16U)) /!< PLL clock used as SAI2 clock source /
AnnaBridge	145:64910690c574	504	#define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL >> 16U)) /!< External input clock used as SAI2 clock source /
AnnaBridge	145:64910690c574	505	#endif /* RCC_CCIPR_SAI2SEL //*
Kojto	122:f9eeca106725	506	* @}
Kojto	122:f9eeca106725	507	*/
Kojto	122:f9eeca106725	508
Kojto	122:f9eeca106725	509	/** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
Kojto	122:f9eeca106725	510	* @{
Kojto	122:f9eeca106725	511	*/
AnnaBridge	145:64910690c574	512	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	145:64910690c574	513	#define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U /!< HSI48 clock used as SDMMC1 clock source /
AnnaBridge	145:64910690c574	514	#else
AnnaBridge	145:64910690c574	515	#define LL_RCC_SDMMC1_CLKSOURCE_NONE 0x00000000U /!< No clock used as SDMMC1 clock source /
AnnaBridge	145:64910690c574	516	#endif
AnnaBridge	145:64910690c574	517	#define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /!< PLLSAI1 clock used as SDMMC1 clock source /
AnnaBridge	145:64910690c574	518	#define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /!< PLL clock used as SDMMC1 clock source /
AnnaBridge	145:64910690c574	519	#define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /!< MSI clock used as SDMMC1 clock source /
Kojto	122:f9eeca106725	520	/**
Kojto	122:f9eeca106725	521	* @}
Kojto	122:f9eeca106725	522	*/
Kojto	122:f9eeca106725	523
Kojto	122:f9eeca106725	524	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
Kojto	122:f9eeca106725	525	* @{
Kojto	122:f9eeca106725	526	*/
AnnaBridge	145:64910690c574	527	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	145:64910690c574	528	#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /!< HSI48 clock used as RNG clock source /
AnnaBridge	145:64910690c574	529	#else
AnnaBridge	145:64910690c574	530	#define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /!< No clock used as RNG clock source /
AnnaBridge	145:64910690c574	531	#endif
AnnaBridge	145:64910690c574	532	#define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /!< PLLSAI1 clock used as RNG clock source /
AnnaBridge	145:64910690c574	533	#define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /!< PLL clock used as RNG clock source /
AnnaBridge	145:64910690c574	534	#define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /!< MSI clock used as RNG clock source /
Kojto	122:f9eeca106725	535	/**
Kojto	122:f9eeca106725	536	* @}
Kojto	122:f9eeca106725	537	*/
Kojto	122:f9eeca106725	538
Kojto	122:f9eeca106725	539	#if defined(USB_OTG_FS) \|\| defined(USB)
Kojto	122:f9eeca106725	540	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
Kojto	122:f9eeca106725	541	* @{
Kojto	122:f9eeca106725	542	*/
AnnaBridge	145:64910690c574	543	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	145:64910690c574	544	#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /!< HSI48 clock used as USB clock source /
AnnaBridge	145:64910690c574	545	#else
AnnaBridge	145:64910690c574	546	#define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /!< No clock used as USB clock source /
AnnaBridge	145:64910690c574	547	#endif
AnnaBridge	145:64910690c574	548	#define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /!< PLLSAI1 clock used as USB clock source /
AnnaBridge	145:64910690c574	549	#define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /!< PLL clock used as USB clock source /
AnnaBridge	145:64910690c574	550	#define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /!< MSI clock used as USB clock source /
Kojto	122:f9eeca106725	551	/**
Kojto	122:f9eeca106725	552	* @}
Kojto	122:f9eeca106725	553	*/
Kojto	122:f9eeca106725	554
Kojto	122:f9eeca106725	555	#endif /* USB_OTG_FS \|\| USB */
Kojto	122:f9eeca106725	556
Kojto	122:f9eeca106725	557	/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
Kojto	122:f9eeca106725	558	* @{
Kojto	122:f9eeca106725	559	*/
AnnaBridge	145:64910690c574	560	#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /!< No clock used as ADC clock source /
AnnaBridge	145:64910690c574	561	#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /!< PLLSAI1 clock used as ADC clock source /
Kojto	122:f9eeca106725	562	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	145:64910690c574	563	#define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /!< PLLSAI2 clock used as ADC clock source /
Kojto	122:f9eeca106725	564	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	145:64910690c574	565	#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /!< SYSCLK clock used as ADC clock source /
Kojto	122:f9eeca106725	566	/**
Kojto	122:f9eeca106725	567	* @}
Kojto	122:f9eeca106725	568	*/
Kojto	122:f9eeca106725	569
AnnaBridge	145:64910690c574	570	#if defined(SWPMI1)
AnnaBridge	145:64910690c574	571	/** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI1 clock source selection
Kojto	122:f9eeca106725	572	* @{
Kojto	122:f9eeca106725	573	*/
AnnaBridge	145:64910690c574	574	#define LL_RCC_SWPMI1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 used as SWPMI1 clock source /
AnnaBridge	145:64910690c574	575	#define LL_RCC_SWPMI1_CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL /!< HSI used as SWPMI1 clock source /
Kojto	122:f9eeca106725	576	/**
Kojto	122:f9eeca106725	577	* @}
Kojto	122:f9eeca106725	578	*/
AnnaBridge	145:64910690c574	579	#endif /* SWPMI1 */
Kojto	122:f9eeca106725	580
Kojto	122:f9eeca106725	581	#if defined(DFSDM1_Channel0)
AnnaBridge	145:64910690c574	582	/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection
Kojto	122:f9eeca106725	583	* @{
Kojto	122:f9eeca106725	584	*/
AnnaBridge	145:64910690c574	585	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 used as DFSDM1 clock source /
AnnaBridge	145:64910690c574	586	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL /!< SYSCLK used as DFSDM1 clock source /
Kojto	122:f9eeca106725	587	/**
Kojto	122:f9eeca106725	588	* @}
Kojto	122:f9eeca106725	589	*/
Kojto	122:f9eeca106725	590	#endif /* DFSDM1_Channel0 */
Kojto	122:f9eeca106725	591
Kojto	122:f9eeca106725	592	/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
Kojto	122:f9eeca106725	593	* @{
Kojto	122:f9eeca106725	594	*/
Kojto	122:f9eeca106725	595	#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /!< USART1 Clock source selection /
Kojto	122:f9eeca106725	596	#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /!< USART2 Clock source selection /
Kojto	122:f9eeca106725	597	#if defined(RCC_CCIPR_USART3SEL)
Kojto	122:f9eeca106725	598	#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /!< USART3 Clock source selection /
Kojto	122:f9eeca106725	599	#endif /* RCC_CCIPR_USART3SEL */
Kojto	122:f9eeca106725	600	/**
Kojto	122:f9eeca106725	601	* @}
Kojto	122:f9eeca106725	602	*/
Kojto	122:f9eeca106725	603
Kojto	122:f9eeca106725	604	#if defined(RCC_CCIPR_UART4SEL) \|\| defined(RCC_CCIPR_UART5SEL)
Kojto	122:f9eeca106725	605	/** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source
Kojto	122:f9eeca106725	606	* @{
Kojto	122:f9eeca106725	607	*/
Kojto	122:f9eeca106725	608	#if defined(RCC_CCIPR_UART4SEL)
Kojto	122:f9eeca106725	609	#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /!< UART4 Clock source selection /
Kojto	122:f9eeca106725	610	#endif /* RCC_CCIPR_UART4SEL */
Kojto	122:f9eeca106725	611	#if defined(RCC_CCIPR_UART5SEL)
Kojto	122:f9eeca106725	612	#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /!< UART5 Clock source selection /
Kojto	122:f9eeca106725	613	#endif /* RCC_CCIPR_UART5SEL */
Kojto	122:f9eeca106725	614	/**
Kojto	122:f9eeca106725	615	* @}
Kojto	122:f9eeca106725	616	*/
Kojto	122:f9eeca106725	617	#endif /* RCC_CCIPR_UART4SEL \|\| RCC_CCIPR_UART5SEL */
Kojto	122:f9eeca106725	618
Kojto	122:f9eeca106725	619	/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
Kojto	122:f9eeca106725	620	* @{
Kojto	122:f9eeca106725	621	*/
Kojto	122:f9eeca106725	622	#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /!< LPUART1 Clock source selection /
Kojto	122:f9eeca106725	623	/**
Kojto	122:f9eeca106725	624	* @}
Kojto	122:f9eeca106725	625	*/
Kojto	122:f9eeca106725	626
Kojto	122:f9eeca106725	627	/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
Kojto	122:f9eeca106725	628	* @{
Kojto	122:f9eeca106725	629	*/
AnnaBridge	145:64910690c574	630	#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /!< I2C1 Clock source selection /
Kojto	122:f9eeca106725	631	#if defined(RCC_CCIPR_I2C2SEL)
AnnaBridge	145:64910690c574	632	#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /!< I2C2 Clock source selection /
Kojto	122:f9eeca106725	633	#endif /* RCC_CCIPR_I2C2SEL */
AnnaBridge	145:64910690c574	634	#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /!< I2C3 Clock source selection /
AnnaBridge	145:64910690c574	635	#if defined(RCC_CCIPR2_I2C4SEL)
AnnaBridge	145:64910690c574	636	#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U) \| (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /!< I2C4 Clock source selection /
AnnaBridge	145:64910690c574	637	#endif /* RCC_CCIPR2_I2C4SEL */
Kojto	122:f9eeca106725	638	/**
Kojto	122:f9eeca106725	639	* @}
Kojto	122:f9eeca106725	640	*/
Kojto	122:f9eeca106725	641
Kojto	122:f9eeca106725	642	/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
Kojto	122:f9eeca106725	643	* @{
Kojto	122:f9eeca106725	644	*/
Kojto	122:f9eeca106725	645	#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /!< LPTIM1 Clock source selection /
Kojto	122:f9eeca106725	646	#define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /!< LPTIM2 Clock source selection /
Kojto	122:f9eeca106725	647	/**
Kojto	122:f9eeca106725	648	* @}
Kojto	122:f9eeca106725	649	*/
Kojto	122:f9eeca106725	650
Kojto	122:f9eeca106725	651	/** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
Kojto	122:f9eeca106725	652	* @{
Kojto	122:f9eeca106725	653	*/
Kojto	122:f9eeca106725	654	#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /!< SAI1 Clock source selection /
Kojto	122:f9eeca106725	655	#if defined(RCC_CCIPR_SAI2SEL)
Kojto	122:f9eeca106725	656	#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /!< SAI2 Clock source selection /
Kojto	122:f9eeca106725	657	#endif /* RCC_CCIPR_SAI2SEL */
Kojto	122:f9eeca106725	658	/**
Kojto	122:f9eeca106725	659	* @}
Kojto	122:f9eeca106725	660	*/
Kojto	122:f9eeca106725	661
Kojto	122:f9eeca106725	662	/** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source
Kojto	122:f9eeca106725	663	* @{
Kojto	122:f9eeca106725	664	*/
Kojto	122:f9eeca106725	665	#define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /!< SDMMC1 Clock source selection /
Kojto	122:f9eeca106725	666	/**
Kojto	122:f9eeca106725	667	* @}
Kojto	122:f9eeca106725	668	*/
Kojto	122:f9eeca106725	669
Kojto	122:f9eeca106725	670	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
Kojto	122:f9eeca106725	671	* @{
Kojto	122:f9eeca106725	672	*/
Kojto	122:f9eeca106725	673	#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /!< RNG Clock source selection /
Kojto	122:f9eeca106725	674	/**
Kojto	122:f9eeca106725	675	* @}
Kojto	122:f9eeca106725	676	*/
Kojto	122:f9eeca106725	677
Kojto	122:f9eeca106725	678	#if defined(USB_OTG_FS) \|\| defined(USB)
Kojto	122:f9eeca106725	679	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
Kojto	122:f9eeca106725	680	* @{
Kojto	122:f9eeca106725	681	*/
Kojto	122:f9eeca106725	682	#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /!< USB Clock source selection /
Kojto	122:f9eeca106725	683	/**
Kojto	122:f9eeca106725	684	* @}
Kojto	122:f9eeca106725	685	*/
Kojto	122:f9eeca106725	686	#endif /* USB_OTG_FS \|\| USB */
Kojto	122:f9eeca106725	687
Kojto	122:f9eeca106725	688	/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
Kojto	122:f9eeca106725	689	* @{
Kojto	122:f9eeca106725	690	*/
Kojto	122:f9eeca106725	691	#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /!< ADC Clock source selection /
Kojto	122:f9eeca106725	692	/**
Kojto	122:f9eeca106725	693	* @}
Kojto	122:f9eeca106725	694	*/
Kojto	122:f9eeca106725	695
AnnaBridge	145:64910690c574	696	#if defined(SWPMI1)
AnnaBridge	145:64910690c574	697	/** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI1 get clock source
Kojto	122:f9eeca106725	698	* @{
Kojto	122:f9eeca106725	699	*/
Kojto	122:f9eeca106725	700	#define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL /!< SWPMI1 Clock source selection /
Kojto	122:f9eeca106725	701	/**
Kojto	122:f9eeca106725	702	* @}
Kojto	122:f9eeca106725	703	*/
AnnaBridge	145:64910690c574	704	#endif /* SWPMI1 */
Kojto	122:f9eeca106725	705
Kojto	122:f9eeca106725	706	#if defined(DFSDM1_Channel0)
AnnaBridge	145:64910690c574	707	/** @defgroup RCC_LL_EC_DFSDM1 Peripheral DFSDM1 get clock source
Kojto	122:f9eeca106725	708	* @{
Kojto	122:f9eeca106725	709	*/
Kojto	122:f9eeca106725	710	#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /!< DFSDM1 Clock source selection /
Kojto	122:f9eeca106725	711	/**
Kojto	122:f9eeca106725	712	* @}
Kojto	122:f9eeca106725	713	*/
Kojto	122:f9eeca106725	714	#endif /* DFSDM1_Channel0 */
Kojto	122:f9eeca106725	715
Kojto	122:f9eeca106725	716	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
Kojto	122:f9eeca106725	717	* @{
Kojto	122:f9eeca106725	718	*/
AnnaBridge	145:64910690c574	719	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
Kojto	122:f9eeca106725	720	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
Kojto	122:f9eeca106725	721	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
Kojto	122:f9eeca106725	722	#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
Kojto	122:f9eeca106725	723	/**
Kojto	122:f9eeca106725	724	* @}
Kojto	122:f9eeca106725	725	*/
Kojto	122:f9eeca106725	726
Kojto	122:f9eeca106725	727	/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source
Kojto	122:f9eeca106725	728	* @{
Kojto	122:f9eeca106725	729	*/
AnnaBridge	145:64910690c574	730	#define LL_RCC_PLLSOURCE_NONE 0x00000000U /!< No clock /
Kojto	122:f9eeca106725	731	#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /!< MSI clock selected as PLL entry clock source /
Kojto	122:f9eeca106725	732	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI16 clock selected as PLL entry clock source /
Kojto	122:f9eeca106725	733	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
Kojto	122:f9eeca106725	734	/**
Kojto	122:f9eeca106725	735	* @}
Kojto	122:f9eeca106725	736	*/
Kojto	122:f9eeca106725	737
Kojto	122:f9eeca106725	738	/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLSAI1 and PLLSAI2 division factor
Kojto	122:f9eeca106725	739	* @{
Kojto	122:f9eeca106725	740	*/
AnnaBridge	145:64910690c574	741	#define LL_RCC_PLLM_DIV_1 0x00000000U /!< PLL, PLLSAI1 and PLLSAI2 division factor by 1 /
Kojto	122:f9eeca106725	742	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 2 /
Kojto	122:f9eeca106725	743	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 3 /
Kojto	122:f9eeca106725	744	#define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0)) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 4 /
Kojto	122:f9eeca106725	745	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 5 /
Kojto	122:f9eeca106725	746	#define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0)) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 6 /
Kojto	122:f9eeca106725	747	#define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1)) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 7 /
Kojto	122:f9eeca106725	748	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /!< PLL, PLLSAI1 and PLLSAI2 division factor by 8 /
Kojto	122:f9eeca106725	749	/**
Kojto	122:f9eeca106725	750	* @}
Kojto	122:f9eeca106725	751	*/
Kojto	122:f9eeca106725	752
Kojto	122:f9eeca106725	753	/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
Kojto	122:f9eeca106725	754	* @{
Kojto	122:f9eeca106725	755	*/
AnnaBridge	145:64910690c574	756	#define LL_RCC_PLLR_DIV_2 0x00000000U /!< Main PLL division factor for PLLCLK (system clock) by 2 /
Kojto	122:f9eeca106725	757	#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 4 /
Kojto	122:f9eeca106725	758	#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 6 /
Kojto	122:f9eeca106725	759	#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /!< Main PLL division factor for PLLCLK (system clock) by 8 /
Kojto	122:f9eeca106725	760	/**
Kojto	122:f9eeca106725	761	* @}
Kojto	122:f9eeca106725	762	*/
Kojto	122:f9eeca106725	763
Kojto	122:f9eeca106725	764	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
Kojto	122:f9eeca106725	765	* @{
Kojto	122:f9eeca106725	766	*/
Kojto	122:f9eeca106725	767	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	768	#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 2 /
Kojto	122:f9eeca106725	769	#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 3 /
Kojto	122:f9eeca106725	770	#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 4 /
Kojto	122:f9eeca106725	771	#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 5 /
Kojto	122:f9eeca106725	772	#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 6 /
Kojto	122:f9eeca106725	773	#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 7 /
Kojto	122:f9eeca106725	774	#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 8 /
Kojto	122:f9eeca106725	775	#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 9 /
Kojto	122:f9eeca106725	776	#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 10 /
Kojto	122:f9eeca106725	777	#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_3)) /!< Main PLL division factor for PLLP output by 11 /
Kojto	122:f9eeca106725	778	#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 12 /
Kojto	122:f9eeca106725	779	#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 13 /
Kojto	122:f9eeca106725	780	#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 14 /
Kojto	122:f9eeca106725	781	#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 15 /
Kojto	122:f9eeca106725	782	#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 16 /
Kojto	122:f9eeca106725	783	#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 17 /
Kojto	122:f9eeca106725	784	#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 18 /
Kojto	122:f9eeca106725	785	#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_4)) /!< Main PLL division factor for PLLP output by 19 /
Kojto	122:f9eeca106725	786	#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 20 /
Kojto	122:f9eeca106725	787	#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 21 /
Kojto	122:f9eeca106725	788	#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 22 /
Kojto	122:f9eeca106725	789	#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 23 /
Kojto	122:f9eeca106725	790	#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 24 /
Kojto	122:f9eeca106725	791	#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 25 /
Kojto	122:f9eeca106725	792	#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 26 /
Kojto	122:f9eeca106725	793	#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 27 /
Kojto	122:f9eeca106725	794	#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 28 /
Kojto	122:f9eeca106725	795	#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 29 /
Kojto	122:f9eeca106725	796	#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 30 /
Kojto	122:f9eeca106725	797	#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_0\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 31 /
Kojto	122:f9eeca106725	798	#else
AnnaBridge	145:64910690c574	799	#define LL_RCC_PLLP_DIV_7 0x00000000U /!< Main PLL division factor for PLLP output by 7 /
Kojto	122:f9eeca106725	800	#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /!< Main PLL division factor for PLLP output by 17 /
Kojto	122:f9eeca106725	801	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	802	/**
Kojto	122:f9eeca106725	803	* @}
Kojto	122:f9eeca106725	804	*/
Kojto	122:f9eeca106725	805
Kojto	122:f9eeca106725	806	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
Kojto	122:f9eeca106725	807	* @{
Kojto	122:f9eeca106725	808	*/
AnnaBridge	145:64910690c574	809	#define LL_RCC_PLLQ_DIV_2 0x00000000U /!< Main PLL division factor for PLLQ output by 2 /
Kojto	122:f9eeca106725	810	#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 4 /
Kojto	122:f9eeca106725	811	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 6 /
Kojto	122:f9eeca106725	812	#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /!< Main PLL division factor for PLLQ output by 8 /
Kojto	122:f9eeca106725	813	/**
Kojto	122:f9eeca106725	814	* @}
Kojto	122:f9eeca106725	815	*/
Kojto	122:f9eeca106725	816
Kojto	122:f9eeca106725	817	/** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q)
Kojto	122:f9eeca106725	818	* @{
Kojto	122:f9eeca106725	819	*/
AnnaBridge	145:64910690c574	820	#define LL_RCC_PLLSAI1Q_DIV_2 0x00000000U /!< PLLSAI1 division factor for PLLSAI1Q output by 2 /
Kojto	122:f9eeca106725	821	#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /!< PLLSAI1 division factor for PLLSAI1Q output by 4 /
Kojto	122:f9eeca106725	822	#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /!< PLLSAI1 division factor for PLLSAI1Q output by 6 /
Kojto	122:f9eeca106725	823	#define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /!< PLLSAI1 division factor for PLLSAI1Q output by 8 /
Kojto	122:f9eeca106725	824	/**
Kojto	122:f9eeca106725	825	* @}
Kojto	122:f9eeca106725	826	*/
Kojto	122:f9eeca106725	827
Kojto	122:f9eeca106725	828	/** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P)
Kojto	122:f9eeca106725	829	* @{
Kojto	122:f9eeca106725	830	*/
Kojto	122:f9eeca106725	831	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	832	#define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 2 /
Kojto	122:f9eeca106725	833	#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 3 /
Kojto	122:f9eeca106725	834	#define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 4 /
Kojto	122:f9eeca106725	835	#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 5 /
Kojto	122:f9eeca106725	836	#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 6 /
Kojto	122:f9eeca106725	837	#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 7 /
Kojto	122:f9eeca106725	838	#define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 8 /
Kojto	122:f9eeca106725	839	#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 9 /
Kojto	122:f9eeca106725	840	#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 10 /
Kojto	122:f9eeca106725	841	#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)) /!< PLLSAI1 division factor for PLLSAI1P output by 1 /
Kojto	122:f9eeca106725	842	#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 12 /
Kojto	122:f9eeca106725	843	#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 13 /
Kojto	122:f9eeca106725	844	#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 14 /
Kojto	122:f9eeca106725	845	#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 15 /
Kojto	122:f9eeca106725	846	#define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 16 /
Kojto	122:f9eeca106725	847	#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 17 /
Kojto	122:f9eeca106725	848	#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 18 /
Kojto	122:f9eeca106725	849	#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)) /!< PLLSAI1 division factor for PLLSAI1P output by 19 /
Kojto	122:f9eeca106725	850	#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 20 /
Kojto	122:f9eeca106725	851	#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division fctor for PLLSAI1P output by 21 /
Kojto	122:f9eeca106725	852	#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 22 /
Kojto	122:f9eeca106725	853	#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 23 /
Kojto	122:f9eeca106725	854	#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 24 /
Kojto	122:f9eeca106725	855	#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 25 /
Kojto	122:f9eeca106725	856	#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 26 /
Kojto	122:f9eeca106725	857	#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 27 /
Kojto	122:f9eeca106725	858	#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 28 /
Kojto	122:f9eeca106725	859	#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 29 /
Kojto	122:f9eeca106725	860	#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 30 /
Kojto	122:f9eeca106725	861	#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 31 /
Kojto	122:f9eeca106725	862	#else
AnnaBridge	145:64910690c574	863	#define LL_RCC_PLLSAI1P_DIV_7 0x00000000U /!< PLLSAI1 division factor for PLLSAI1P output by 7 /
Kojto	122:f9eeca106725	864	#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /!< PLLSAI1 division factor for PLLSAI1P output by 17 /
Kojto	122:f9eeca106725	865	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	866	/**
Kojto	122:f9eeca106725	867	* @}
Kojto	122:f9eeca106725	868	*/
Kojto	122:f9eeca106725	869
Kojto	122:f9eeca106725	870	/** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R)
Kojto	122:f9eeca106725	871	* @{
Kojto	122:f9eeca106725	872	*/
AnnaBridge	145:64910690c574	873	#define LL_RCC_PLLSAI1R_DIV_2 0x00000000U /!< PLLSAI1 division factor for PLLSAI1R output by 2 /
Kojto	122:f9eeca106725	874	#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /!< PLLSAI1 division factor for PLLSAI1R output by 4 /
Kojto	122:f9eeca106725	875	#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /!< PLLSAI1 division factor for PLLSAI1R output by 6 /
Kojto	122:f9eeca106725	876	#define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /!< PLLSAI1 division factor for PLLSAI1R output by 8 /
Kojto	122:f9eeca106725	877	/**
Kojto	122:f9eeca106725	878	* @}
Kojto	122:f9eeca106725	879	*/
Kojto	122:f9eeca106725	880
Kojto	122:f9eeca106725	881	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	882	/** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P)
Kojto	122:f9eeca106725	883	* @{
Kojto	122:f9eeca106725	884	*/
AnnaBridge	145:64910690c574	885	#define LL_RCC_PLLSAI2P_DIV_7 0x00000000U /!< PLLSAI2 division factor for PLLSAI2P output by 7 /
Kojto	122:f9eeca106725	886	#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /!< PLLSAI2 division factor for PLLSAI2P output by 17 /
Kojto	122:f9eeca106725	887	/**
Kojto	122:f9eeca106725	888	* @}
Kojto	122:f9eeca106725	889	*/
Kojto	122:f9eeca106725	890
Kojto	122:f9eeca106725	891	/** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R)
Kojto	122:f9eeca106725	892	* @{
Kojto	122:f9eeca106725	893	*/
AnnaBridge	145:64910690c574	894	#define LL_RCC_PLLSAI2R_DIV_2 0x00000000U /!< PLLSAI2 division factor for PLLSAI2R output by 2 /
Kojto	122:f9eeca106725	895	#define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0) /!< PLLSAI2 division factor for PLLSAI2R output by 4 /
Kojto	122:f9eeca106725	896	#define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1) /!< PLLSAI2 division factor for PLLSAI2R output by 6 /
Kojto	122:f9eeca106725	897	#define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R) /!< PLLSAI2 division factor for PLLSAI2R output by 8 /
Kojto	122:f9eeca106725	898	/**
Kojto	122:f9eeca106725	899	* @}
Kojto	122:f9eeca106725	900	*/
Kojto	122:f9eeca106725	901	#endif /* RCC_PLLSAI2_SUPPORT */
Kojto	122:f9eeca106725	902
Kojto	122:f9eeca106725	903	/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
Kojto	122:f9eeca106725	904	* @{
Kojto	122:f9eeca106725	905	*/
AnnaBridge	145:64910690c574	906	#define LL_RCC_MSIRANGESEL_STANDBY 0U /!< MSI Range is provided by MSISRANGE /
AnnaBridge	145:64910690c574	907	#define LL_RCC_MSIRANGESEL_RUN 1U /!< MSI Range is provided by MSIRANGE /
Kojto	122:f9eeca106725	908	/**
Kojto	122:f9eeca106725	909	* @}
Kojto	122:f9eeca106725	910	*/
Kojto	122:f9eeca106725	911
Kojto	122:f9eeca106725	912	/** Legacy definitions for compatibility purpose
Kojto	122:f9eeca106725	913	@cond 0
Kojto	122:f9eeca106725	914	*/
Kojto	122:f9eeca106725	915	#if defined(DFSDM1_Channel0)
AnnaBridge	145:64910690c574	916	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	145:64910690c574	917	#define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
Kojto	122:f9eeca106725	918	#define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	919	#define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE
Kojto	122:f9eeca106725	920	#endif /* DFSDM1_Channel0 */
AnnaBridge	145:64910690c574	921	#if defined(SWPMI1)
AnnaBridge	145:64910690c574	922	#define LL_RCC_SWPMI1_CLKSOURCE_PCLK LL_RCC_SWPMI1_CLKSOURCE_PCLK1
AnnaBridge	145:64910690c574	923	#endif /* SWPMI1 */
Kojto	122:f9eeca106725	924	/**
Kojto	122:f9eeca106725	925	@endcond
Kojto	122:f9eeca106725	926	*/
Kojto	122:f9eeca106725	927
Kojto	122:f9eeca106725	928	/**
Kojto	122:f9eeca106725	929	* @}
Kojto	122:f9eeca106725	930	*/
Kojto	122:f9eeca106725	931
Kojto	122:f9eeca106725	932	/* Exported macro ------------------------------------------------------------*/
Kojto	122:f9eeca106725	933	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
Kojto	122:f9eeca106725	934	* @{
Kojto	122:f9eeca106725	935	*/
Kojto	122:f9eeca106725	936
Kojto	122:f9eeca106725	937	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
Kojto	122:f9eeca106725	938	* @{
Kojto	122:f9eeca106725	939	*/
Kojto	122:f9eeca106725	940
Kojto	122:f9eeca106725	941	/**
Kojto	122:f9eeca106725	942	* @brief Write a value in RCC register
Kojto	122:f9eeca106725	943	* @param __REG__ Register to be written
Kojto	122:f9eeca106725	944	* @param __VALUE__ Value to be written in the register
Kojto	122:f9eeca106725	945	* @retval None
Kojto	122:f9eeca106725	946	*/
Kojto	122:f9eeca106725	947	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
Kojto	122:f9eeca106725	948
Kojto	122:f9eeca106725	949	/**
Kojto	122:f9eeca106725	950	* @brief Read a value in RCC register
Kojto	122:f9eeca106725	951	* @param __REG__ Register to be read
Kojto	122:f9eeca106725	952	* @retval Register value
Kojto	122:f9eeca106725	953	*/
Kojto	122:f9eeca106725	954	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Kojto	122:f9eeca106725	955	/**
Kojto	122:f9eeca106725	956	* @}
Kojto	122:f9eeca106725	957	*/
Kojto	122:f9eeca106725	958
Kojto	122:f9eeca106725	959	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
Kojto	122:f9eeca106725	960	* @{
Kojto	122:f9eeca106725	961	*/
Kojto	122:f9eeca106725	962
Kojto	122:f9eeca106725	963	/**
Kojto	122:f9eeca106725	964	* @brief Helper macro to calculate the PLLCLK frequency on system domain
Kojto	122:f9eeca106725	965	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	966	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
Kojto	122:f9eeca106725	967	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	968	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	969	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	970	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	971	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	972	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	973	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	974	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	975	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	976	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	977	* @param __PLLN__ Between 8 and 86
Kojto	122:f9eeca106725	978	* @param __PLLR__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	979	* @arg @ref LL_RCC_PLLR_DIV_2
Kojto	122:f9eeca106725	980	* @arg @ref LL_RCC_PLLR_DIV_4
Kojto	122:f9eeca106725	981	* @arg @ref LL_RCC_PLLR_DIV_6
Kojto	122:f9eeca106725	982	* @arg @ref LL_RCC_PLLR_DIV_8
Kojto	122:f9eeca106725	983	* @retval PLL clock frequency (in Hz)
Kojto	122:f9eeca106725	984	*/
AnnaBridge	145:64910690c574	985	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	145:64910690c574	986	((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
Kojto	122:f9eeca106725	987
Kojto	122:f9eeca106725	988	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	989	/**
Kojto	122:f9eeca106725	990	* @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
Kojto	122:f9eeca106725	991	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	992	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
Kojto	122:f9eeca106725	993	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	994	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	995	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	996	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	997	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	998	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	999	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1000	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1001	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1002	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1003	* @param __PLLN__ Between 8 and 86
Kojto	122:f9eeca106725	1004	* @param __PLLP__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1005	* @arg @ref LL_RCC_PLLP_DIV_2
Kojto	122:f9eeca106725	1006	* @arg @ref LL_RCC_PLLP_DIV_3
Kojto	122:f9eeca106725	1007	* @arg @ref LL_RCC_PLLP_DIV_4
Kojto	122:f9eeca106725	1008	* @arg @ref LL_RCC_PLLP_DIV_5
Kojto	122:f9eeca106725	1009	* @arg @ref LL_RCC_PLLP_DIV_6
Kojto	122:f9eeca106725	1010	* @arg @ref LL_RCC_PLLP_DIV_7
Kojto	122:f9eeca106725	1011	* @arg @ref LL_RCC_PLLP_DIV_8
Kojto	122:f9eeca106725	1012	* @arg @ref LL_RCC_PLLP_DIV_9
Kojto	122:f9eeca106725	1013	* @arg @ref LL_RCC_PLLP_DIV_10
Kojto	122:f9eeca106725	1014	* @arg @ref LL_RCC_PLLP_DIV_11
Kojto	122:f9eeca106725	1015	* @arg @ref LL_RCC_PLLP_DIV_12
Kojto	122:f9eeca106725	1016	* @arg @ref LL_RCC_PLLP_DIV_13
Kojto	122:f9eeca106725	1017	* @arg @ref LL_RCC_PLLP_DIV_14
Kojto	122:f9eeca106725	1018	* @arg @ref LL_RCC_PLLP_DIV_15
Kojto	122:f9eeca106725	1019	* @arg @ref LL_RCC_PLLP_DIV_16
Kojto	122:f9eeca106725	1020	* @arg @ref LL_RCC_PLLP_DIV_17
Kojto	122:f9eeca106725	1021	* @arg @ref LL_RCC_PLLP_DIV_18
Kojto	122:f9eeca106725	1022	* @arg @ref LL_RCC_PLLP_DIV_19
Kojto	122:f9eeca106725	1023	* @arg @ref LL_RCC_PLLP_DIV_20
Kojto	122:f9eeca106725	1024	* @arg @ref LL_RCC_PLLP_DIV_21
Kojto	122:f9eeca106725	1025	* @arg @ref LL_RCC_PLLP_DIV_22
Kojto	122:f9eeca106725	1026	* @arg @ref LL_RCC_PLLP_DIV_23
Kojto	122:f9eeca106725	1027	* @arg @ref LL_RCC_PLLP_DIV_24
Kojto	122:f9eeca106725	1028	* @arg @ref LL_RCC_PLLP_DIV_25
Kojto	122:f9eeca106725	1029	* @arg @ref LL_RCC_PLLP_DIV_26
Kojto	122:f9eeca106725	1030	* @arg @ref LL_RCC_PLLP_DIV_27
Kojto	122:f9eeca106725	1031	* @arg @ref LL_RCC_PLLP_DIV_28
Kojto	122:f9eeca106725	1032	* @arg @ref LL_RCC_PLLP_DIV_29
Kojto	122:f9eeca106725	1033	* @arg @ref LL_RCC_PLLP_DIV_30
Kojto	122:f9eeca106725	1034	* @arg @ref LL_RCC_PLLP_DIV_31
Kojto	122:f9eeca106725	1035	* @retval PLL clock frequency (in Hz)
Kojto	122:f9eeca106725	1036	*/
AnnaBridge	145:64910690c574	1037	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	145:64910690c574	1038	((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos))
Kojto	122:f9eeca106725	1039
Kojto	122:f9eeca106725	1040	#else
Kojto	122:f9eeca106725	1041	/**
Kojto	122:f9eeca106725	1042	* @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
Kojto	122:f9eeca106725	1043	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1044	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
Kojto	122:f9eeca106725	1045	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1046	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1047	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1048	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1049	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1050	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1051	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1052	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1053	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1054	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1055	* @param __PLLN__ Between 8 and 86
Kojto	122:f9eeca106725	1056	* @param __PLLP__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1057	* @arg @ref LL_RCC_PLLP_DIV_7
Kojto	122:f9eeca106725	1058	* @arg @ref LL_RCC_PLLP_DIV_17
Kojto	122:f9eeca106725	1059	* @retval PLL clock frequency (in Hz)
Kojto	122:f9eeca106725	1060	*/
AnnaBridge	145:64910690c574	1061	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	145:64910690c574	1062	(((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U))
Kojto	122:f9eeca106725	1063
Kojto	122:f9eeca106725	1064	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	1065	/**
Kojto	122:f9eeca106725	1066	* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
Kojto	122:f9eeca106725	1067	* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1068	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
Kojto	122:f9eeca106725	1069	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1070	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1071	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1072	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1073	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1074	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1075	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1076	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1077	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1078	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1079	* @param __PLLN__ Between 8 and 86
Kojto	122:f9eeca106725	1080	* @param __PLLQ__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1081	* @arg @ref LL_RCC_PLLQ_DIV_2
Kojto	122:f9eeca106725	1082	* @arg @ref LL_RCC_PLLQ_DIV_4
Kojto	122:f9eeca106725	1083	* @arg @ref LL_RCC_PLLQ_DIV_6
Kojto	122:f9eeca106725	1084	* @arg @ref LL_RCC_PLLQ_DIV_8
Kojto	122:f9eeca106725	1085	* @retval PLL clock frequency (in Hz)
Kojto	122:f9eeca106725	1086	*/
AnnaBridge	145:64910690c574	1087	#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	145:64910690c574	1088	((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
Kojto	122:f9eeca106725	1089
Kojto	122:f9eeca106725	1090	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	1091	/**
Kojto	122:f9eeca106725	1092	* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
Kojto	122:f9eeca106725	1093	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1094	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
Kojto	122:f9eeca106725	1095	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1096	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1097	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1098	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1099	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1100	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1101	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1102	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1103	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1104	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1105	* @param __PLLSAI1N__ Between 8 and 86
Kojto	122:f9eeca106725	1106	* @param __PLLSAI1P__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1107	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
Kojto	122:f9eeca106725	1108	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
Kojto	122:f9eeca106725	1109	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
Kojto	122:f9eeca106725	1110	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
Kojto	122:f9eeca106725	1111	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
Kojto	122:f9eeca106725	1112	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
Kojto	122:f9eeca106725	1113	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
Kojto	122:f9eeca106725	1114	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
Kojto	122:f9eeca106725	1115	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
Kojto	122:f9eeca106725	1116	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
Kojto	122:f9eeca106725	1117	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
Kojto	122:f9eeca106725	1118	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
Kojto	122:f9eeca106725	1119	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
Kojto	122:f9eeca106725	1120	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
Kojto	122:f9eeca106725	1121	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
Kojto	122:f9eeca106725	1122	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
Kojto	122:f9eeca106725	1123	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
Kojto	122:f9eeca106725	1124	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
Kojto	122:f9eeca106725	1125	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
Kojto	122:f9eeca106725	1126	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
Kojto	122:f9eeca106725	1127	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
Kojto	122:f9eeca106725	1128	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
Kojto	122:f9eeca106725	1129	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
Kojto	122:f9eeca106725	1130	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
Kojto	122:f9eeca106725	1131	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
Kojto	122:f9eeca106725	1132	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
Kojto	122:f9eeca106725	1133	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
Kojto	122:f9eeca106725	1134	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
Kojto	122:f9eeca106725	1135	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
Kojto	122:f9eeca106725	1136	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
Kojto	122:f9eeca106725	1137	* @retval PLLSAI1 clock frequency (in Hz)
Kojto	122:f9eeca106725	1138	*/
AnnaBridge	145:64910690c574	1139	#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
AnnaBridge	145:64910690c574	1140	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	145:64910690c574	1141	((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos))
Kojto	122:f9eeca106725	1142	#else
Kojto	122:f9eeca106725	1143	/**
Kojto	122:f9eeca106725	1144	* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
Kojto	122:f9eeca106725	1145	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1146	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
Kojto	122:f9eeca106725	1147	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1148	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1149	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1150	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1151	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1152	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1153	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1154	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1155	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1156	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1157	* @param __PLLSAI1N__ Between 8 and 86
Kojto	122:f9eeca106725	1158	* @param __PLLSAI1P__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1159	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
Kojto	122:f9eeca106725	1160	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
Kojto	122:f9eeca106725	1161	* @retval PLLSAI1 clock frequency (in Hz)
Kojto	122:f9eeca106725	1162	*/
AnnaBridge	145:64910690c574	1163	#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
AnnaBridge	145:64910690c574	1164	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	145:64910690c574	1165	(((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U))
Kojto	122:f9eeca106725	1166	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	1167
Kojto	122:f9eeca106725	1168	/**
Kojto	122:f9eeca106725	1169	* @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
Kojto	122:f9eeca106725	1170	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1171	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
Kojto	122:f9eeca106725	1172	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1173	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1174	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1175	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1176	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1177	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1178	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1179	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1180	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1181	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1182	* @param __PLLSAI1N__ Between 8 and 86
Kojto	122:f9eeca106725	1183	* @param __PLLSAI1Q__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1184	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
Kojto	122:f9eeca106725	1185	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
Kojto	122:f9eeca106725	1186	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
Kojto	122:f9eeca106725	1187	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
Kojto	122:f9eeca106725	1188	* @retval PLLSAI1 clock frequency (in Hz)
Kojto	122:f9eeca106725	1189	*/
AnnaBridge	145:64910690c574	1190	#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \
AnnaBridge	145:64910690c574	1191	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	145:64910690c574	1192	((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
Kojto	122:f9eeca106725	1193
Kojto	122:f9eeca106725	1194	/**
Kojto	122:f9eeca106725	1195	* @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
Kojto	122:f9eeca106725	1196	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1197	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
Kojto	122:f9eeca106725	1198	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1199	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1200	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1201	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1202	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1203	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1204	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1205	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1206	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1207	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1208	* @param __PLLSAI1N__ Between 8 and 86
Kojto	122:f9eeca106725	1209	* @param __PLLSAI1R__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1210	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
Kojto	122:f9eeca106725	1211	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
Kojto	122:f9eeca106725	1212	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
Kojto	122:f9eeca106725	1213	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
Kojto	122:f9eeca106725	1214	* @retval PLLSAI1 clock frequency (in Hz)
Kojto	122:f9eeca106725	1215	*/
AnnaBridge	145:64910690c574	1216	#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \
AnnaBridge	145:64910690c574	1217	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	145:64910690c574	1218	((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
Kojto	122:f9eeca106725	1219
Kojto	122:f9eeca106725	1220	/**
Kojto	122:f9eeca106725	1221	* @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
Kojto	122:f9eeca106725	1222	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1223	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
Kojto	122:f9eeca106725	1224	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1225	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1226	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1227	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1228	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1229	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1230	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1231	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1232	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1233	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1234	* @param __PLLSAI2N__ Between 8 and 86
Kojto	122:f9eeca106725	1235	* @param __PLLSAI2P__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1236	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
Kojto	122:f9eeca106725	1237	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
Kojto	122:f9eeca106725	1238	* @retval PLLSAI2 clock frequency (in Hz)
Kojto	122:f9eeca106725	1239	*/
AnnaBridge	145:64910690c574	1240	#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
AnnaBridge	145:64910690c574	1241	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \
AnnaBridge	145:64910690c574	1242	(((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U))
Kojto	122:f9eeca106725	1243	/**
Kojto	122:f9eeca106725	1244	* @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain
Kojto	122:f9eeca106725	1245	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
Kojto	122:f9eeca106725	1246	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ());
Kojto	122:f9eeca106725	1247	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
Kojto	122:f9eeca106725	1248	* @param __PLLM__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1249	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	1250	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	1251	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	1252	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	1253	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	1254	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	1255	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	1256	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	1257	* @param __PLLSAI2N__ Between 8 and 86
Kojto	122:f9eeca106725	1258	* @param __PLLSAI2R__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1259	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
Kojto	122:f9eeca106725	1260	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
Kojto	122:f9eeca106725	1261	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
Kojto	122:f9eeca106725	1262	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
Kojto	122:f9eeca106725	1263	* @retval PLLSAI2 clock frequency (in Hz)
Kojto	122:f9eeca106725	1264	*/
AnnaBridge	145:64910690c574	1265	#define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) \
AnnaBridge	145:64910690c574	1266	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	145:64910690c574	1267	((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U))
AnnaBridge	145:64910690c574	1268
Kojto	122:f9eeca106725	1269
Kojto	122:f9eeca106725	1270	/**
Kojto	122:f9eeca106725	1271	* @brief Helper macro to calculate the HCLK frequency
Kojto	122:f9eeca106725	1272	* @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
Kojto	122:f9eeca106725	1273	* @param __AHBPRESCALER__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1274	* @arg @ref LL_RCC_SYSCLK_DIV_1
Kojto	122:f9eeca106725	1275	* @arg @ref LL_RCC_SYSCLK_DIV_2
Kojto	122:f9eeca106725	1276	* @arg @ref LL_RCC_SYSCLK_DIV_4
Kojto	122:f9eeca106725	1277	* @arg @ref LL_RCC_SYSCLK_DIV_8
Kojto	122:f9eeca106725	1278	* @arg @ref LL_RCC_SYSCLK_DIV_16
Kojto	122:f9eeca106725	1279	* @arg @ref LL_RCC_SYSCLK_DIV_64
Kojto	122:f9eeca106725	1280	* @arg @ref LL_RCC_SYSCLK_DIV_128
Kojto	122:f9eeca106725	1281	* @arg @ref LL_RCC_SYSCLK_DIV_256
Kojto	122:f9eeca106725	1282	* @arg @ref LL_RCC_SYSCLK_DIV_512
Kojto	122:f9eeca106725	1283	* @retval HCLK clock frequency (in Hz)
Kojto	122:f9eeca106725	1284	*/
AnnaBridge	145:64910690c574	1285	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
Kojto	122:f9eeca106725	1286
Kojto	122:f9eeca106725	1287	/**
Kojto	122:f9eeca106725	1288	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
Kojto	122:f9eeca106725	1289	* @param __HCLKFREQ__ HCLK frequency
Kojto	122:f9eeca106725	1290	* @param __APB1PRESCALER__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1291	* @arg @ref LL_RCC_APB1_DIV_1
Kojto	122:f9eeca106725	1292	* @arg @ref LL_RCC_APB1_DIV_2
Kojto	122:f9eeca106725	1293	* @arg @ref LL_RCC_APB1_DIV_4
Kojto	122:f9eeca106725	1294	* @arg @ref LL_RCC_APB1_DIV_8
Kojto	122:f9eeca106725	1295	* @arg @ref LL_RCC_APB1_DIV_16
Kojto	122:f9eeca106725	1296	* @retval PCLK1 clock frequency (in Hz)
Kojto	122:f9eeca106725	1297	*/
AnnaBridge	145:64910690c574	1298	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
Kojto	122:f9eeca106725	1299
Kojto	122:f9eeca106725	1300	/**
Kojto	122:f9eeca106725	1301	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
Kojto	122:f9eeca106725	1302	* @param __HCLKFREQ__ HCLK frequency
Kojto	122:f9eeca106725	1303	* @param __APB2PRESCALER__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1304	* @arg @ref LL_RCC_APB2_DIV_1
Kojto	122:f9eeca106725	1305	* @arg @ref LL_RCC_APB2_DIV_2
Kojto	122:f9eeca106725	1306	* @arg @ref LL_RCC_APB2_DIV_4
Kojto	122:f9eeca106725	1307	* @arg @ref LL_RCC_APB2_DIV_8
Kojto	122:f9eeca106725	1308	* @arg @ref LL_RCC_APB2_DIV_16
Kojto	122:f9eeca106725	1309	* @retval PCLK2 clock frequency (in Hz)
Kojto	122:f9eeca106725	1310	*/
AnnaBridge	145:64910690c574	1311	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
Kojto	122:f9eeca106725	1312
Kojto	122:f9eeca106725	1313	/**
Kojto	122:f9eeca106725	1314	* @brief Helper macro to calculate the MSI frequency (in Hz)
AnnaBridge	145:64910690c574	1315	* @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
AnnaBridge	145:64910690c574	1316	* @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
AnnaBridge	145:64910690c574	1317	* __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()
AnnaBridge	145:64910690c574	1318	* else by LL_RCC_MSI_GetRange()
Kojto	122:f9eeca106725	1319	* ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
Kojto	122:f9eeca106725	1320	* (LL_RCC_MSI_IsEnabledRangeSelect()?
Kojto	122:f9eeca106725	1321	* LL_RCC_MSI_GetRange():
Kojto	122:f9eeca106725	1322	* LL_RCC_MSI_GetRangeAfterStandby()))
Kojto	122:f9eeca106725	1323	* @param __MSISEL__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1324	* @arg @ref LL_RCC_MSIRANGESEL_STANDBY
Kojto	122:f9eeca106725	1325	* @arg @ref LL_RCC_MSIRANGESEL_RUN
Kojto	122:f9eeca106725	1326	* @param __MSIRANGE__ This parameter can be one of the following values:
Kojto	122:f9eeca106725	1327	* @arg @ref LL_RCC_MSIRANGE_0
Kojto	122:f9eeca106725	1328	* @arg @ref LL_RCC_MSIRANGE_1
Kojto	122:f9eeca106725	1329	* @arg @ref LL_RCC_MSIRANGE_2
Kojto	122:f9eeca106725	1330	* @arg @ref LL_RCC_MSIRANGE_3
Kojto	122:f9eeca106725	1331	* @arg @ref LL_RCC_MSIRANGE_4
Kojto	122:f9eeca106725	1332	* @arg @ref LL_RCC_MSIRANGE_5
Kojto	122:f9eeca106725	1333	* @arg @ref LL_RCC_MSIRANGE_6
Kojto	122:f9eeca106725	1334	* @arg @ref LL_RCC_MSIRANGE_7
Kojto	122:f9eeca106725	1335	* @arg @ref LL_RCC_MSIRANGE_8
Kojto	122:f9eeca106725	1336	* @arg @ref LL_RCC_MSIRANGE_9
Kojto	122:f9eeca106725	1337	* @arg @ref LL_RCC_MSIRANGE_10
Kojto	122:f9eeca106725	1338	* @arg @ref LL_RCC_MSIRANGE_11
Kojto	122:f9eeca106725	1339	* @arg @ref LL_RCC_MSISRANGE_4
Kojto	122:f9eeca106725	1340	* @arg @ref LL_RCC_MSISRANGE_5
Kojto	122:f9eeca106725	1341	* @arg @ref LL_RCC_MSISRANGE_6
Kojto	122:f9eeca106725	1342	* @arg @ref LL_RCC_MSISRANGE_7
Kojto	122:f9eeca106725	1343	* @retval MSI clock frequency (in Hz)
Kojto	122:f9eeca106725	1344	*/
Kojto	122:f9eeca106725	1345	#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
AnnaBridge	145:64910690c574	1346	(MSIRangeTable[(__MSIRANGE__) >> 8U]) : \
AnnaBridge	145:64910690c574	1347	(MSIRangeTable[(__MSIRANGE__) >> 4U]))
Kojto	122:f9eeca106725	1348
Kojto	122:f9eeca106725	1349	/**
Kojto	122:f9eeca106725	1350	* @}
Kojto	122:f9eeca106725	1351	*/
Kojto	122:f9eeca106725	1352
Kojto	122:f9eeca106725	1353	/**
Kojto	122:f9eeca106725	1354	* @}
Kojto	122:f9eeca106725	1355	*/
Kojto	122:f9eeca106725	1356
Kojto	122:f9eeca106725	1357	/* Exported functions --------------------------------------------------------*/
Kojto	122:f9eeca106725	1358	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
Kojto	122:f9eeca106725	1359	* @{
Kojto	122:f9eeca106725	1360	*/
Kojto	122:f9eeca106725	1361
Kojto	122:f9eeca106725	1362	/** @defgroup RCC_LL_EF_HSE HSE
Kojto	122:f9eeca106725	1363	* @{
Kojto	122:f9eeca106725	1364	*/
Kojto	122:f9eeca106725	1365
Kojto	122:f9eeca106725	1366	/**
Kojto	122:f9eeca106725	1367	* @brief Enable the Clock Security System.
Kojto	122:f9eeca106725	1368	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
Kojto	122:f9eeca106725	1369	* @retval None
Kojto	122:f9eeca106725	1370	*/
Kojto	122:f9eeca106725	1371	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
Kojto	122:f9eeca106725	1372	{
Kojto	122:f9eeca106725	1373	SET_BIT(RCC->CR, RCC_CR_CSSON);
Kojto	122:f9eeca106725	1374	}
Kojto	122:f9eeca106725	1375
Kojto	122:f9eeca106725	1376	/**
Kojto	122:f9eeca106725	1377	* @brief Enable HSE external oscillator (HSE Bypass)
Kojto	122:f9eeca106725	1378	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
Kojto	122:f9eeca106725	1379	* @retval None
Kojto	122:f9eeca106725	1380	*/
Kojto	122:f9eeca106725	1381	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
Kojto	122:f9eeca106725	1382	{
Kojto	122:f9eeca106725	1383	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
Kojto	122:f9eeca106725	1384	}
Kojto	122:f9eeca106725	1385
Kojto	122:f9eeca106725	1386	/**
Kojto	122:f9eeca106725	1387	* @brief Disable HSE external oscillator (HSE Bypass)
Kojto	122:f9eeca106725	1388	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
Kojto	122:f9eeca106725	1389	* @retval None
Kojto	122:f9eeca106725	1390	*/
Kojto	122:f9eeca106725	1391	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
Kojto	122:f9eeca106725	1392	{
Kojto	122:f9eeca106725	1393	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
Kojto	122:f9eeca106725	1394	}
Kojto	122:f9eeca106725	1395
Kojto	122:f9eeca106725	1396	/**
Kojto	122:f9eeca106725	1397	* @brief Enable HSE crystal oscillator (HSE ON)
Kojto	122:f9eeca106725	1398	* @rmtoll CR HSEON LL_RCC_HSE_Enable
Kojto	122:f9eeca106725	1399	* @retval None
Kojto	122:f9eeca106725	1400	*/
Kojto	122:f9eeca106725	1401	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
Kojto	122:f9eeca106725	1402	{
Kojto	122:f9eeca106725	1403	SET_BIT(RCC->CR, RCC_CR_HSEON);
Kojto	122:f9eeca106725	1404	}
Kojto	122:f9eeca106725	1405
Kojto	122:f9eeca106725	1406	/**
Kojto	122:f9eeca106725	1407	* @brief Disable HSE crystal oscillator (HSE ON)
Kojto	122:f9eeca106725	1408	* @rmtoll CR HSEON LL_RCC_HSE_Disable
Kojto	122:f9eeca106725	1409	* @retval None
Kojto	122:f9eeca106725	1410	*/
Kojto	122:f9eeca106725	1411	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
Kojto	122:f9eeca106725	1412	{
Kojto	122:f9eeca106725	1413	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
Kojto	122:f9eeca106725	1414	}
Kojto	122:f9eeca106725	1415
Kojto	122:f9eeca106725	1416	/**
Kojto	122:f9eeca106725	1417	* @brief Check if HSE oscillator Ready
Kojto	122:f9eeca106725	1418	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
Kojto	122:f9eeca106725	1419	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1420	*/
Kojto	122:f9eeca106725	1421	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
Kojto	122:f9eeca106725	1422	{
Kojto	122:f9eeca106725	1423	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
Kojto	122:f9eeca106725	1424	}
Kojto	122:f9eeca106725	1425
Kojto	122:f9eeca106725	1426	/**
Kojto	122:f9eeca106725	1427	* @}
Kojto	122:f9eeca106725	1428	*/
Kojto	122:f9eeca106725	1429
Kojto	122:f9eeca106725	1430	/** @defgroup RCC_LL_EF_HSI HSI
Kojto	122:f9eeca106725	1431	* @{
Kojto	122:f9eeca106725	1432	*/
Kojto	122:f9eeca106725	1433
Kojto	122:f9eeca106725	1434	/**
Kojto	122:f9eeca106725	1435	* @brief Enable HSI even in stop mode
Kojto	122:f9eeca106725	1436	* @note HSI oscillator is forced ON even in Stop mode
Kojto	122:f9eeca106725	1437	* @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
Kojto	122:f9eeca106725	1438	* @retval None
Kojto	122:f9eeca106725	1439	*/
Kojto	122:f9eeca106725	1440	__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
Kojto	122:f9eeca106725	1441	{
Kojto	122:f9eeca106725	1442	SET_BIT(RCC->CR, RCC_CR_HSIKERON);
Kojto	122:f9eeca106725	1443	}
Kojto	122:f9eeca106725	1444
Kojto	122:f9eeca106725	1445	/**
Kojto	122:f9eeca106725	1446	* @brief Disable HSI in stop mode
Kojto	122:f9eeca106725	1447	* @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
Kojto	122:f9eeca106725	1448	* @retval None
Kojto	122:f9eeca106725	1449	*/
Kojto	122:f9eeca106725	1450	__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
Kojto	122:f9eeca106725	1451	{
Kojto	122:f9eeca106725	1452	CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
Kojto	122:f9eeca106725	1453	}
Kojto	122:f9eeca106725	1454
Kojto	122:f9eeca106725	1455	/**
Kojto	122:f9eeca106725	1456	* @brief Enable HSI oscillator
Kojto	122:f9eeca106725	1457	* @rmtoll CR HSION LL_RCC_HSI_Enable
Kojto	122:f9eeca106725	1458	* @retval None
Kojto	122:f9eeca106725	1459	*/
Kojto	122:f9eeca106725	1460	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
Kojto	122:f9eeca106725	1461	{
Kojto	122:f9eeca106725	1462	SET_BIT(RCC->CR, RCC_CR_HSION);
Kojto	122:f9eeca106725	1463	}
Kojto	122:f9eeca106725	1464
Kojto	122:f9eeca106725	1465	/**
Kojto	122:f9eeca106725	1466	* @brief Disable HSI oscillator
Kojto	122:f9eeca106725	1467	* @rmtoll CR HSION LL_RCC_HSI_Disable
Kojto	122:f9eeca106725	1468	* @retval None
Kojto	122:f9eeca106725	1469	*/
Kojto	122:f9eeca106725	1470	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
Kojto	122:f9eeca106725	1471	{
Kojto	122:f9eeca106725	1472	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
Kojto	122:f9eeca106725	1473	}
Kojto	122:f9eeca106725	1474
Kojto	122:f9eeca106725	1475	/**
Kojto	122:f9eeca106725	1476	* @brief Check if HSI clock is ready
Kojto	122:f9eeca106725	1477	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
Kojto	122:f9eeca106725	1478	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1479	*/
Kojto	122:f9eeca106725	1480	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
Kojto	122:f9eeca106725	1481	{
Kojto	122:f9eeca106725	1482	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
Kojto	122:f9eeca106725	1483	}
Kojto	122:f9eeca106725	1484
Kojto	122:f9eeca106725	1485	/**
Kojto	122:f9eeca106725	1486	* @brief Enable HSI Automatic from stop mode
Kojto	122:f9eeca106725	1487	* @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
Kojto	122:f9eeca106725	1488	* @retval None
Kojto	122:f9eeca106725	1489	*/
Kojto	122:f9eeca106725	1490	__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
Kojto	122:f9eeca106725	1491	{
Kojto	122:f9eeca106725	1492	SET_BIT(RCC->CR, RCC_CR_HSIASFS);
Kojto	122:f9eeca106725	1493	}
Kojto	122:f9eeca106725	1494
Kojto	122:f9eeca106725	1495	/**
Kojto	122:f9eeca106725	1496	* @brief Disable HSI Automatic from stop mode
Kojto	122:f9eeca106725	1497	* @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
Kojto	122:f9eeca106725	1498	* @retval None
Kojto	122:f9eeca106725	1499	*/
Kojto	122:f9eeca106725	1500	__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
Kojto	122:f9eeca106725	1501	{
Kojto	122:f9eeca106725	1502	CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
Kojto	122:f9eeca106725	1503	}
Kojto	122:f9eeca106725	1504	/**
Kojto	122:f9eeca106725	1505	* @brief Get HSI Calibration value
Kojto	122:f9eeca106725	1506	* @note When HSITRIM is written, HSICAL is updated with the sum of
Kojto	122:f9eeca106725	1507	* HSITRIM and the factory trim value
Kojto	122:f9eeca106725	1508	* @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
Kojto	122:f9eeca106725	1509	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
Kojto	122:f9eeca106725	1510	*/
Kojto	122:f9eeca106725	1511	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
Kojto	122:f9eeca106725	1512	{
AnnaBridge	145:64910690c574	1513	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
Kojto	122:f9eeca106725	1514	}
Kojto	122:f9eeca106725	1515
Kojto	122:f9eeca106725	1516	/**
Kojto	122:f9eeca106725	1517	* @brief Set HSI Calibration trimming
Kojto	122:f9eeca106725	1518	* @note user-programmable trimming value that is added to the HSICAL
Kojto	122:f9eeca106725	1519	* @note Default value is 16, which, when added to the HSICAL value,
Kojto	122:f9eeca106725	1520	* should trim the HSI to 16 MHz +/- 1 %
Kojto	122:f9eeca106725	1521	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
Kojto	122:f9eeca106725	1522	* @param Value Between Min_Data = 0 and Max_Data = 31
Kojto	122:f9eeca106725	1523	* @retval None
Kojto	122:f9eeca106725	1524	*/
Kojto	122:f9eeca106725	1525	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
Kojto	122:f9eeca106725	1526	{
AnnaBridge	145:64910690c574	1527	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
Kojto	122:f9eeca106725	1528	}
Kojto	122:f9eeca106725	1529
Kojto	122:f9eeca106725	1530	/**
Kojto	122:f9eeca106725	1531	* @brief Get HSI Calibration trimming
Kojto	122:f9eeca106725	1532	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
Kojto	122:f9eeca106725	1533	* @retval Between Min_Data = 0 and Max_Data = 31
Kojto	122:f9eeca106725	1534	*/
Kojto	122:f9eeca106725	1535	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
Kojto	122:f9eeca106725	1536	{
AnnaBridge	145:64910690c574	1537	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
Kojto	122:f9eeca106725	1538	}
Kojto	122:f9eeca106725	1539
Kojto	122:f9eeca106725	1540	/**
Kojto	122:f9eeca106725	1541	* @}
Kojto	122:f9eeca106725	1542	*/
Kojto	122:f9eeca106725	1543
Kojto	122:f9eeca106725	1544	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	1545	/** @defgroup RCC_LL_EF_HSI48 HSI48
Kojto	122:f9eeca106725	1546	* @{
Kojto	122:f9eeca106725	1547	*/
Kojto	122:f9eeca106725	1548
Kojto	122:f9eeca106725	1549	/**
Kojto	122:f9eeca106725	1550	* @brief Enable HSI48
Kojto	122:f9eeca106725	1551	* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
Kojto	122:f9eeca106725	1552	* @retval None
Kojto	122:f9eeca106725	1553	*/
Kojto	122:f9eeca106725	1554	__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
Kojto	122:f9eeca106725	1555	{
Kojto	122:f9eeca106725	1556	SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
Kojto	122:f9eeca106725	1557	}
Kojto	122:f9eeca106725	1558
Kojto	122:f9eeca106725	1559	/**
Kojto	122:f9eeca106725	1560	* @brief Disable HSI48
Kojto	122:f9eeca106725	1561	* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
Kojto	122:f9eeca106725	1562	* @retval None
Kojto	122:f9eeca106725	1563	*/
Kojto	122:f9eeca106725	1564	__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
Kojto	122:f9eeca106725	1565	{
Kojto	122:f9eeca106725	1566	CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
Kojto	122:f9eeca106725	1567	}
Kojto	122:f9eeca106725	1568
Kojto	122:f9eeca106725	1569	/**
Kojto	122:f9eeca106725	1570	* @brief Check if HSI48 oscillator Ready
Kojto	122:f9eeca106725	1571	* @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
Kojto	122:f9eeca106725	1572	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1573	*/
Kojto	122:f9eeca106725	1574	__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
Kojto	122:f9eeca106725	1575	{
Kojto	122:f9eeca106725	1576	return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY));
Kojto	122:f9eeca106725	1577	}
Kojto	122:f9eeca106725	1578
Kojto	122:f9eeca106725	1579	/**
Kojto	122:f9eeca106725	1580	* @brief Get HSI48 Calibration value
Kojto	122:f9eeca106725	1581	* @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
Kojto	122:f9eeca106725	1582	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
Kojto	122:f9eeca106725	1583	*/
Kojto	122:f9eeca106725	1584	__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
Kojto	122:f9eeca106725	1585	{
AnnaBridge	145:64910690c574	1586	return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
Kojto	122:f9eeca106725	1587	}
Kojto	122:f9eeca106725	1588
Kojto	122:f9eeca106725	1589	/**
Kojto	122:f9eeca106725	1590	* @}
Kojto	122:f9eeca106725	1591	*/
Kojto	122:f9eeca106725	1592	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	1593
Kojto	122:f9eeca106725	1594	/** @defgroup RCC_LL_EF_LSE LSE
Kojto	122:f9eeca106725	1595	* @{
Kojto	122:f9eeca106725	1596	*/
Kojto	122:f9eeca106725	1597
Kojto	122:f9eeca106725	1598	/**
Kojto	122:f9eeca106725	1599	* @brief Enable Low Speed External (LSE) crystal.
Kojto	122:f9eeca106725	1600	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
Kojto	122:f9eeca106725	1601	* @retval None
Kojto	122:f9eeca106725	1602	*/
Kojto	122:f9eeca106725	1603	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
Kojto	122:f9eeca106725	1604	{
Kojto	122:f9eeca106725	1605	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
Kojto	122:f9eeca106725	1606	}
Kojto	122:f9eeca106725	1607
Kojto	122:f9eeca106725	1608	/**
Kojto	122:f9eeca106725	1609	* @brief Disable Low Speed External (LSE) crystal.
Kojto	122:f9eeca106725	1610	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
Kojto	122:f9eeca106725	1611	* @retval None
Kojto	122:f9eeca106725	1612	*/
Kojto	122:f9eeca106725	1613	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
Kojto	122:f9eeca106725	1614	{
Kojto	122:f9eeca106725	1615	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
Kojto	122:f9eeca106725	1616	}
Kojto	122:f9eeca106725	1617
Kojto	122:f9eeca106725	1618	/**
Kojto	122:f9eeca106725	1619	* @brief Enable external clock source (LSE bypass).
Kojto	122:f9eeca106725	1620	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
Kojto	122:f9eeca106725	1621	* @retval None
Kojto	122:f9eeca106725	1622	*/
Kojto	122:f9eeca106725	1623	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
Kojto	122:f9eeca106725	1624	{
Kojto	122:f9eeca106725	1625	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
Kojto	122:f9eeca106725	1626	}
Kojto	122:f9eeca106725	1627
Kojto	122:f9eeca106725	1628	/**
Kojto	122:f9eeca106725	1629	* @brief Disable external clock source (LSE bypass).
Kojto	122:f9eeca106725	1630	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
Kojto	122:f9eeca106725	1631	* @retval None
Kojto	122:f9eeca106725	1632	*/
Kojto	122:f9eeca106725	1633	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
Kojto	122:f9eeca106725	1634	{
Kojto	122:f9eeca106725	1635	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
Kojto	122:f9eeca106725	1636	}
Kojto	122:f9eeca106725	1637
Kojto	122:f9eeca106725	1638	/**
Kojto	122:f9eeca106725	1639	* @brief Set LSE oscillator drive capability
Kojto	122:f9eeca106725	1640	* @note The oscillator is in Xtal mode when it is not in bypass mode.
Kojto	122:f9eeca106725	1641	* @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
Kojto	122:f9eeca106725	1642	* @param LSEDrive This parameter can be one of the following values:
Kojto	122:f9eeca106725	1643	* @arg @ref LL_RCC_LSEDRIVE_LOW
Kojto	122:f9eeca106725	1644	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
Kojto	122:f9eeca106725	1645	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
Kojto	122:f9eeca106725	1646	* @arg @ref LL_RCC_LSEDRIVE_HIGH
Kojto	122:f9eeca106725	1647	* @retval None
Kojto	122:f9eeca106725	1648	*/
Kojto	122:f9eeca106725	1649	__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
Kojto	122:f9eeca106725	1650	{
Kojto	122:f9eeca106725	1651	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
Kojto	122:f9eeca106725	1652	}
Kojto	122:f9eeca106725	1653
Kojto	122:f9eeca106725	1654	/**
Kojto	122:f9eeca106725	1655	* @brief Get LSE oscillator drive capability
Kojto	122:f9eeca106725	1656	* @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
Kojto	122:f9eeca106725	1657	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	1658	* @arg @ref LL_RCC_LSEDRIVE_LOW
Kojto	122:f9eeca106725	1659	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
Kojto	122:f9eeca106725	1660	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
Kojto	122:f9eeca106725	1661	* @arg @ref LL_RCC_LSEDRIVE_HIGH
Kojto	122:f9eeca106725	1662	*/
Kojto	122:f9eeca106725	1663	__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
Kojto	122:f9eeca106725	1664	{
Kojto	122:f9eeca106725	1665	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
Kojto	122:f9eeca106725	1666	}
Kojto	122:f9eeca106725	1667
Kojto	122:f9eeca106725	1668	/**
Kojto	122:f9eeca106725	1669	* @brief Enable Clock security system on LSE.
Kojto	122:f9eeca106725	1670	* @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
Kojto	122:f9eeca106725	1671	* @retval None
Kojto	122:f9eeca106725	1672	*/
Kojto	122:f9eeca106725	1673	__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
Kojto	122:f9eeca106725	1674	{
Kojto	122:f9eeca106725	1675	SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
Kojto	122:f9eeca106725	1676	}
Kojto	122:f9eeca106725	1677
Kojto	122:f9eeca106725	1678	/**
Kojto	122:f9eeca106725	1679	* @brief Disable Clock security system on LSE.
Kojto	122:f9eeca106725	1680	* @note Clock security system can be disabled only after a LSE
Kojto	122:f9eeca106725	1681	* failure detection. In that case it MUST be disabled by software.
Kojto	122:f9eeca106725	1682	* @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
Kojto	122:f9eeca106725	1683	* @retval None
Kojto	122:f9eeca106725	1684	*/
Kojto	122:f9eeca106725	1685	__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
Kojto	122:f9eeca106725	1686	{
Kojto	122:f9eeca106725	1687	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
Kojto	122:f9eeca106725	1688	}
Kojto	122:f9eeca106725	1689
Kojto	122:f9eeca106725	1690	/**
Kojto	122:f9eeca106725	1691	* @brief Check if LSE oscillator Ready
Kojto	122:f9eeca106725	1692	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
Kojto	122:f9eeca106725	1693	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1694	*/
Kojto	122:f9eeca106725	1695	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
Kojto	122:f9eeca106725	1696	{
Kojto	122:f9eeca106725	1697	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
Kojto	122:f9eeca106725	1698	}
Kojto	122:f9eeca106725	1699
Kojto	122:f9eeca106725	1700	/**
Kojto	122:f9eeca106725	1701	* @brief Check if CSS on LSE failure Detection
Kojto	122:f9eeca106725	1702	* @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
Kojto	122:f9eeca106725	1703	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1704	*/
Kojto	122:f9eeca106725	1705	__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
Kojto	122:f9eeca106725	1706	{
Kojto	122:f9eeca106725	1707	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD));
Kojto	122:f9eeca106725	1708	}
Kojto	122:f9eeca106725	1709
Kojto	122:f9eeca106725	1710	/**
Kojto	122:f9eeca106725	1711	* @}
Kojto	122:f9eeca106725	1712	*/
Kojto	122:f9eeca106725	1713
Kojto	122:f9eeca106725	1714	/** @defgroup RCC_LL_EF_LSI LSI
Kojto	122:f9eeca106725	1715	* @{
Kojto	122:f9eeca106725	1716	*/
Kojto	122:f9eeca106725	1717
Kojto	122:f9eeca106725	1718	/**
Kojto	122:f9eeca106725	1719	* @brief Enable LSI Oscillator
Kojto	122:f9eeca106725	1720	* @rmtoll CSR LSION LL_RCC_LSI_Enable
Kojto	122:f9eeca106725	1721	* @retval None
Kojto	122:f9eeca106725	1722	*/
Kojto	122:f9eeca106725	1723	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
Kojto	122:f9eeca106725	1724	{
Kojto	122:f9eeca106725	1725	SET_BIT(RCC->CSR, RCC_CSR_LSION);
Kojto	122:f9eeca106725	1726	}
Kojto	122:f9eeca106725	1727
Kojto	122:f9eeca106725	1728	/**
Kojto	122:f9eeca106725	1729	* @brief Disable LSI Oscillator
Kojto	122:f9eeca106725	1730	* @rmtoll CSR LSION LL_RCC_LSI_Disable
Kojto	122:f9eeca106725	1731	* @retval None
Kojto	122:f9eeca106725	1732	*/
Kojto	122:f9eeca106725	1733	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
Kojto	122:f9eeca106725	1734	{
Kojto	122:f9eeca106725	1735	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
Kojto	122:f9eeca106725	1736	}
Kojto	122:f9eeca106725	1737
Kojto	122:f9eeca106725	1738	/**
Kojto	122:f9eeca106725	1739	* @brief Check if LSI is Ready
Kojto	122:f9eeca106725	1740	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
Kojto	122:f9eeca106725	1741	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1742	*/
Kojto	122:f9eeca106725	1743	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
Kojto	122:f9eeca106725	1744	{
Kojto	122:f9eeca106725	1745	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
Kojto	122:f9eeca106725	1746	}
Kojto	122:f9eeca106725	1747
Kojto	122:f9eeca106725	1748	/**
Kojto	122:f9eeca106725	1749	* @}
Kojto	122:f9eeca106725	1750	*/
Kojto	122:f9eeca106725	1751
Kojto	122:f9eeca106725	1752	/** @defgroup RCC_LL_EF_MSI MSI
Kojto	122:f9eeca106725	1753	* @{
Kojto	122:f9eeca106725	1754	*/
Kojto	122:f9eeca106725	1755
Kojto	122:f9eeca106725	1756	/**
Kojto	122:f9eeca106725	1757	* @brief Enable MSI oscillator
Kojto	122:f9eeca106725	1758	* @rmtoll CR MSION LL_RCC_MSI_Enable
Kojto	122:f9eeca106725	1759	* @retval None
Kojto	122:f9eeca106725	1760	*/
Kojto	122:f9eeca106725	1761	__STATIC_INLINE void LL_RCC_MSI_Enable(void)
Kojto	122:f9eeca106725	1762	{
Kojto	122:f9eeca106725	1763	SET_BIT(RCC->CR, RCC_CR_MSION);
Kojto	122:f9eeca106725	1764	}
Kojto	122:f9eeca106725	1765
Kojto	122:f9eeca106725	1766	/**
Kojto	122:f9eeca106725	1767	* @brief Disable MSI oscillator
Kojto	122:f9eeca106725	1768	* @rmtoll CR MSION LL_RCC_MSI_Disable
Kojto	122:f9eeca106725	1769	* @retval None
Kojto	122:f9eeca106725	1770	*/
Kojto	122:f9eeca106725	1771	__STATIC_INLINE void LL_RCC_MSI_Disable(void)
Kojto	122:f9eeca106725	1772	{
Kojto	122:f9eeca106725	1773	CLEAR_BIT(RCC->CR, RCC_CR_MSION);
Kojto	122:f9eeca106725	1774	}
Kojto	122:f9eeca106725	1775
Kojto	122:f9eeca106725	1776	/**
Kojto	122:f9eeca106725	1777	* @brief Check if MSI oscillator Ready
Kojto	122:f9eeca106725	1778	* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
Kojto	122:f9eeca106725	1779	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1780	*/
Kojto	122:f9eeca106725	1781	__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
Kojto	122:f9eeca106725	1782	{
Kojto	122:f9eeca106725	1783	return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
Kojto	122:f9eeca106725	1784	}
Kojto	122:f9eeca106725	1785
Kojto	122:f9eeca106725	1786	/**
Kojto	122:f9eeca106725	1787	* @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
Kojto	122:f9eeca106725	1788	* @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
Kojto	122:f9eeca106725	1789	* and ready (LSERDY set by hardware)
Kojto	122:f9eeca106725	1790	* @note hardware protection to avoid enabling MSIPLLEN if LSE is not
Kojto	122:f9eeca106725	1791	* ready
Kojto	122:f9eeca106725	1792	* @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
Kojto	122:f9eeca106725	1793	* @retval None
Kojto	122:f9eeca106725	1794	*/
Kojto	122:f9eeca106725	1795	__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
Kojto	122:f9eeca106725	1796	{
Kojto	122:f9eeca106725	1797	SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
Kojto	122:f9eeca106725	1798	}
Kojto	122:f9eeca106725	1799
Kojto	122:f9eeca106725	1800	/**
Kojto	122:f9eeca106725	1801	* @brief Disable MSI-PLL mode
Kojto	122:f9eeca106725	1802	* @note cleared by hardware when LSE is disabled (LSEON = 0) or when
Kojto	122:f9eeca106725	1803	* the Clock Security System on LSE detects a LSE failure
Kojto	122:f9eeca106725	1804	* @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
Kojto	122:f9eeca106725	1805	* @retval None
Kojto	122:f9eeca106725	1806	*/
Kojto	122:f9eeca106725	1807	__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
Kojto	122:f9eeca106725	1808	{
Kojto	122:f9eeca106725	1809	CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
Kojto	122:f9eeca106725	1810	}
Kojto	122:f9eeca106725	1811
Kojto	122:f9eeca106725	1812	/**
Kojto	122:f9eeca106725	1813	* @brief Enable MSI clock range selection with MSIRANGE register
Kojto	122:f9eeca106725	1814	* @note Write 0 has no effect. After a standby or a reset
Kojto	122:f9eeca106725	1815	* MSIRGSEL is at 0 and the MSI range value is provided by
Kojto	122:f9eeca106725	1816	* MSISRANGE
Kojto	122:f9eeca106725	1817	* @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
Kojto	122:f9eeca106725	1818	* @retval None
Kojto	122:f9eeca106725	1819	*/
Kojto	122:f9eeca106725	1820	__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
Kojto	122:f9eeca106725	1821	{
Kojto	122:f9eeca106725	1822	SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
Kojto	122:f9eeca106725	1823	}
Kojto	122:f9eeca106725	1824
Kojto	122:f9eeca106725	1825	/**
Kojto	122:f9eeca106725	1826	* @brief Check if MSI clock range is selected with MSIRANGE register
Kojto	122:f9eeca106725	1827	* @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
Kojto	122:f9eeca106725	1828	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1829	*/
Kojto	122:f9eeca106725	1830	__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
Kojto	122:f9eeca106725	1831	{
Kojto	122:f9eeca106725	1832	return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL));
Kojto	122:f9eeca106725	1833	}
Kojto	122:f9eeca106725	1834
Kojto	122:f9eeca106725	1835	/**
Kojto	122:f9eeca106725	1836	* @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
Kojto	122:f9eeca106725	1837	* @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
Kojto	122:f9eeca106725	1838	* @param Range This parameter can be one of the following values:
Kojto	122:f9eeca106725	1839	* @arg @ref LL_RCC_MSIRANGE_0
Kojto	122:f9eeca106725	1840	* @arg @ref LL_RCC_MSIRANGE_1
Kojto	122:f9eeca106725	1841	* @arg @ref LL_RCC_MSIRANGE_2
Kojto	122:f9eeca106725	1842	* @arg @ref LL_RCC_MSIRANGE_3
Kojto	122:f9eeca106725	1843	* @arg @ref LL_RCC_MSIRANGE_4
Kojto	122:f9eeca106725	1844	* @arg @ref LL_RCC_MSIRANGE_5
Kojto	122:f9eeca106725	1845	* @arg @ref LL_RCC_MSIRANGE_6
Kojto	122:f9eeca106725	1846	* @arg @ref LL_RCC_MSIRANGE_7
Kojto	122:f9eeca106725	1847	* @arg @ref LL_RCC_MSIRANGE_8
Kojto	122:f9eeca106725	1848	* @arg @ref LL_RCC_MSIRANGE_9
Kojto	122:f9eeca106725	1849	* @arg @ref LL_RCC_MSIRANGE_10
Kojto	122:f9eeca106725	1850	* @arg @ref LL_RCC_MSIRANGE_11
Kojto	122:f9eeca106725	1851	* @retval None
Kojto	122:f9eeca106725	1852	*/
Kojto	122:f9eeca106725	1853	__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
Kojto	122:f9eeca106725	1854	{
Kojto	122:f9eeca106725	1855	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
Kojto	122:f9eeca106725	1856	}
Kojto	122:f9eeca106725	1857
Kojto	122:f9eeca106725	1858	/**
Kojto	122:f9eeca106725	1859	* @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
Kojto	122:f9eeca106725	1860	* @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
Kojto	122:f9eeca106725	1861	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	1862	* @arg @ref LL_RCC_MSIRANGE_0
Kojto	122:f9eeca106725	1863	* @arg @ref LL_RCC_MSIRANGE_1
Kojto	122:f9eeca106725	1864	* @arg @ref LL_RCC_MSIRANGE_2
Kojto	122:f9eeca106725	1865	* @arg @ref LL_RCC_MSIRANGE_3
Kojto	122:f9eeca106725	1866	* @arg @ref LL_RCC_MSIRANGE_4
Kojto	122:f9eeca106725	1867	* @arg @ref LL_RCC_MSIRANGE_5
Kojto	122:f9eeca106725	1868	* @arg @ref LL_RCC_MSIRANGE_6
Kojto	122:f9eeca106725	1869	* @arg @ref LL_RCC_MSIRANGE_7
Kojto	122:f9eeca106725	1870	* @arg @ref LL_RCC_MSIRANGE_8
Kojto	122:f9eeca106725	1871	* @arg @ref LL_RCC_MSIRANGE_9
Kojto	122:f9eeca106725	1872	* @arg @ref LL_RCC_MSIRANGE_10
Kojto	122:f9eeca106725	1873	* @arg @ref LL_RCC_MSIRANGE_11
Kojto	122:f9eeca106725	1874	*/
Kojto	122:f9eeca106725	1875	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
Kojto	122:f9eeca106725	1876	{
Kojto	122:f9eeca106725	1877	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
Kojto	122:f9eeca106725	1878	}
Kojto	122:f9eeca106725	1879
Kojto	122:f9eeca106725	1880	/**
Kojto	122:f9eeca106725	1881	* @brief Configure MSI range used after standby
Kojto	122:f9eeca106725	1882	* @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby
Kojto	122:f9eeca106725	1883	* @param Range This parameter can be one of the following values:
Kojto	122:f9eeca106725	1884	* @arg @ref LL_RCC_MSISRANGE_4
Kojto	122:f9eeca106725	1885	* @arg @ref LL_RCC_MSISRANGE_5
Kojto	122:f9eeca106725	1886	* @arg @ref LL_RCC_MSISRANGE_6
Kojto	122:f9eeca106725	1887	* @arg @ref LL_RCC_MSISRANGE_7
Kojto	122:f9eeca106725	1888	* @retval None
Kojto	122:f9eeca106725	1889	*/
Kojto	122:f9eeca106725	1890	__STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
Kojto	122:f9eeca106725	1891	{
Kojto	122:f9eeca106725	1892	MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
Kojto	122:f9eeca106725	1893	}
Kojto	122:f9eeca106725	1894
Kojto	122:f9eeca106725	1895	/**
Kojto	122:f9eeca106725	1896	* @brief Get MSI range used after standby
Kojto	122:f9eeca106725	1897	* @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby
Kojto	122:f9eeca106725	1898	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	1899	* @arg @ref LL_RCC_MSISRANGE_4
Kojto	122:f9eeca106725	1900	* @arg @ref LL_RCC_MSISRANGE_5
Kojto	122:f9eeca106725	1901	* @arg @ref LL_RCC_MSISRANGE_6
Kojto	122:f9eeca106725	1902	* @arg @ref LL_RCC_MSISRANGE_7
Kojto	122:f9eeca106725	1903	*/
Kojto	122:f9eeca106725	1904	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
Kojto	122:f9eeca106725	1905	{
Kojto	122:f9eeca106725	1906	return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
Kojto	122:f9eeca106725	1907	}
Kojto	122:f9eeca106725	1908
Kojto	122:f9eeca106725	1909	/**
Kojto	122:f9eeca106725	1910	* @brief Get MSI Calibration value
Kojto	122:f9eeca106725	1911	* @note When MSITRIM is written, MSICAL is updated with the sum of
Kojto	122:f9eeca106725	1912	* MSITRIM and the factory trim value
Kojto	122:f9eeca106725	1913	* @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
Kojto	122:f9eeca106725	1914	* @retval Between Min_Data = 0 and Max_Data = 255
Kojto	122:f9eeca106725	1915	*/
Kojto	122:f9eeca106725	1916	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
Kojto	122:f9eeca106725	1917	{
AnnaBridge	145:64910690c574	1918	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
Kojto	122:f9eeca106725	1919	}
Kojto	122:f9eeca106725	1920
Kojto	122:f9eeca106725	1921	/**
Kojto	122:f9eeca106725	1922	* @brief Set MSI Calibration trimming
Kojto	122:f9eeca106725	1923	* @note user-programmable trimming value that is added to the MSICAL
Kojto	122:f9eeca106725	1924	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
Kojto	122:f9eeca106725	1925	* @param Value Between Min_Data = 0 and Max_Data = 255
Kojto	122:f9eeca106725	1926	* @retval None
Kojto	122:f9eeca106725	1927	*/
Kojto	122:f9eeca106725	1928	__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
Kojto	122:f9eeca106725	1929	{
AnnaBridge	145:64910690c574	1930	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
Kojto	122:f9eeca106725	1931	}
Kojto	122:f9eeca106725	1932
Kojto	122:f9eeca106725	1933	/**
Kojto	122:f9eeca106725	1934	* @brief Get MSI Calibration trimming
Kojto	122:f9eeca106725	1935	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
Kojto	122:f9eeca106725	1936	* @retval Between 0 and 255
Kojto	122:f9eeca106725	1937	*/
Kojto	122:f9eeca106725	1938	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
Kojto	122:f9eeca106725	1939	{
AnnaBridge	145:64910690c574	1940	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
Kojto	122:f9eeca106725	1941	}
Kojto	122:f9eeca106725	1942
Kojto	122:f9eeca106725	1943	/**
Kojto	122:f9eeca106725	1944	* @}
Kojto	122:f9eeca106725	1945	*/
Kojto	122:f9eeca106725	1946
Kojto	122:f9eeca106725	1947	/** @defgroup RCC_LL_EF_LSCO LSCO
Kojto	122:f9eeca106725	1948	* @{
Kojto	122:f9eeca106725	1949	*/
Kojto	122:f9eeca106725	1950
Kojto	122:f9eeca106725	1951	/**
Kojto	122:f9eeca106725	1952	* @brief Enable Low speed clock
Kojto	122:f9eeca106725	1953	* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
Kojto	122:f9eeca106725	1954	* @retval None
Kojto	122:f9eeca106725	1955	*/
Kojto	122:f9eeca106725	1956	__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
Kojto	122:f9eeca106725	1957	{
Kojto	122:f9eeca106725	1958	SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
Kojto	122:f9eeca106725	1959	}
Kojto	122:f9eeca106725	1960
Kojto	122:f9eeca106725	1961	/**
Kojto	122:f9eeca106725	1962	* @brief Disable Low speed clock
Kojto	122:f9eeca106725	1963	* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
Kojto	122:f9eeca106725	1964	* @retval None
Kojto	122:f9eeca106725	1965	*/
Kojto	122:f9eeca106725	1966	__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
Kojto	122:f9eeca106725	1967	{
Kojto	122:f9eeca106725	1968	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
Kojto	122:f9eeca106725	1969	}
Kojto	122:f9eeca106725	1970
Kojto	122:f9eeca106725	1971	/**
Kojto	122:f9eeca106725	1972	* @brief Configure Low speed clock selection
Kojto	122:f9eeca106725	1973	* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
Kojto	122:f9eeca106725	1974	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	1975	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
Kojto	122:f9eeca106725	1976	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
Kojto	122:f9eeca106725	1977	* @retval None
Kojto	122:f9eeca106725	1978	*/
Kojto	122:f9eeca106725	1979	__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
Kojto	122:f9eeca106725	1980	{
Kojto	122:f9eeca106725	1981	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
Kojto	122:f9eeca106725	1982	}
Kojto	122:f9eeca106725	1983
Kojto	122:f9eeca106725	1984	/**
Kojto	122:f9eeca106725	1985	* @brief Get Low speed clock selection
Kojto	122:f9eeca106725	1986	* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
Kojto	122:f9eeca106725	1987	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	1988	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
Kojto	122:f9eeca106725	1989	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
Kojto	122:f9eeca106725	1990	*/
Kojto	122:f9eeca106725	1991	__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
Kojto	122:f9eeca106725	1992	{
Kojto	122:f9eeca106725	1993	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
Kojto	122:f9eeca106725	1994	}
Kojto	122:f9eeca106725	1995
Kojto	122:f9eeca106725	1996	/**
Kojto	122:f9eeca106725	1997	* @}
Kojto	122:f9eeca106725	1998	*/
Kojto	122:f9eeca106725	1999
Kojto	122:f9eeca106725	2000	/** @defgroup RCC_LL_EF_System System
Kojto	122:f9eeca106725	2001	* @{
Kojto	122:f9eeca106725	2002	*/
Kojto	122:f9eeca106725	2003
Kojto	122:f9eeca106725	2004	/**
Kojto	122:f9eeca106725	2005	* @brief Configure the system clock source
Kojto	122:f9eeca106725	2006	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
Kojto	122:f9eeca106725	2007	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	2008	* @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
Kojto	122:f9eeca106725	2009	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2010	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
Kojto	122:f9eeca106725	2011	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2012	* @retval None
Kojto	122:f9eeca106725	2013	*/
Kojto	122:f9eeca106725	2014	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
Kojto	122:f9eeca106725	2015	{
Kojto	122:f9eeca106725	2016	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
Kojto	122:f9eeca106725	2017	}
Kojto	122:f9eeca106725	2018
Kojto	122:f9eeca106725	2019	/**
Kojto	122:f9eeca106725	2020	* @brief Get the system clock source
Kojto	122:f9eeca106725	2021	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
Kojto	122:f9eeca106725	2022	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2023	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
Kojto	122:f9eeca106725	2024	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
Kojto	122:f9eeca106725	2025	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
Kojto	122:f9eeca106725	2026	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
Kojto	122:f9eeca106725	2027	*/
Kojto	122:f9eeca106725	2028	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
Kojto	122:f9eeca106725	2029	{
Kojto	122:f9eeca106725	2030	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
Kojto	122:f9eeca106725	2031	}
Kojto	122:f9eeca106725	2032
Kojto	122:f9eeca106725	2033	/**
Kojto	122:f9eeca106725	2034	* @brief Set AHB prescaler
Kojto	122:f9eeca106725	2035	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
Kojto	122:f9eeca106725	2036	* @param Prescaler This parameter can be one of the following values:
Kojto	122:f9eeca106725	2037	* @arg @ref LL_RCC_SYSCLK_DIV_1
Kojto	122:f9eeca106725	2038	* @arg @ref LL_RCC_SYSCLK_DIV_2
Kojto	122:f9eeca106725	2039	* @arg @ref LL_RCC_SYSCLK_DIV_4
Kojto	122:f9eeca106725	2040	* @arg @ref LL_RCC_SYSCLK_DIV_8
Kojto	122:f9eeca106725	2041	* @arg @ref LL_RCC_SYSCLK_DIV_16
Kojto	122:f9eeca106725	2042	* @arg @ref LL_RCC_SYSCLK_DIV_64
Kojto	122:f9eeca106725	2043	* @arg @ref LL_RCC_SYSCLK_DIV_128
Kojto	122:f9eeca106725	2044	* @arg @ref LL_RCC_SYSCLK_DIV_256
Kojto	122:f9eeca106725	2045	* @arg @ref LL_RCC_SYSCLK_DIV_512
Kojto	122:f9eeca106725	2046	* @retval None
Kojto	122:f9eeca106725	2047	*/
Kojto	122:f9eeca106725	2048	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
Kojto	122:f9eeca106725	2049	{
Kojto	122:f9eeca106725	2050	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
Kojto	122:f9eeca106725	2051	}
Kojto	122:f9eeca106725	2052
Kojto	122:f9eeca106725	2053	/**
Kojto	122:f9eeca106725	2054	* @brief Set APB1 prescaler
Kojto	122:f9eeca106725	2055	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
Kojto	122:f9eeca106725	2056	* @param Prescaler This parameter can be one of the following values:
Kojto	122:f9eeca106725	2057	* @arg @ref LL_RCC_APB1_DIV_1
Kojto	122:f9eeca106725	2058	* @arg @ref LL_RCC_APB1_DIV_2
Kojto	122:f9eeca106725	2059	* @arg @ref LL_RCC_APB1_DIV_4
Kojto	122:f9eeca106725	2060	* @arg @ref LL_RCC_APB1_DIV_8
Kojto	122:f9eeca106725	2061	* @arg @ref LL_RCC_APB1_DIV_16
Kojto	122:f9eeca106725	2062	* @retval None
Kojto	122:f9eeca106725	2063	*/
Kojto	122:f9eeca106725	2064	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
Kojto	122:f9eeca106725	2065	{
Kojto	122:f9eeca106725	2066	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
Kojto	122:f9eeca106725	2067	}
Kojto	122:f9eeca106725	2068
Kojto	122:f9eeca106725	2069	/**
Kojto	122:f9eeca106725	2070	* @brief Set APB2 prescaler
Kojto	122:f9eeca106725	2071	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
Kojto	122:f9eeca106725	2072	* @param Prescaler This parameter can be one of the following values:
Kojto	122:f9eeca106725	2073	* @arg @ref LL_RCC_APB2_DIV_1
Kojto	122:f9eeca106725	2074	* @arg @ref LL_RCC_APB2_DIV_2
Kojto	122:f9eeca106725	2075	* @arg @ref LL_RCC_APB2_DIV_4
Kojto	122:f9eeca106725	2076	* @arg @ref LL_RCC_APB2_DIV_8
Kojto	122:f9eeca106725	2077	* @arg @ref LL_RCC_APB2_DIV_16
Kojto	122:f9eeca106725	2078	* @retval None
Kojto	122:f9eeca106725	2079	*/
Kojto	122:f9eeca106725	2080	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
Kojto	122:f9eeca106725	2081	{
Kojto	122:f9eeca106725	2082	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
Kojto	122:f9eeca106725	2083	}
Kojto	122:f9eeca106725	2084
Kojto	122:f9eeca106725	2085	/**
Kojto	122:f9eeca106725	2086	* @brief Get AHB prescaler
Kojto	122:f9eeca106725	2087	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
Kojto	122:f9eeca106725	2088	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2089	* @arg @ref LL_RCC_SYSCLK_DIV_1
Kojto	122:f9eeca106725	2090	* @arg @ref LL_RCC_SYSCLK_DIV_2
Kojto	122:f9eeca106725	2091	* @arg @ref LL_RCC_SYSCLK_DIV_4
Kojto	122:f9eeca106725	2092	* @arg @ref LL_RCC_SYSCLK_DIV_8
Kojto	122:f9eeca106725	2093	* @arg @ref LL_RCC_SYSCLK_DIV_16
Kojto	122:f9eeca106725	2094	* @arg @ref LL_RCC_SYSCLK_DIV_64
Kojto	122:f9eeca106725	2095	* @arg @ref LL_RCC_SYSCLK_DIV_128
Kojto	122:f9eeca106725	2096	* @arg @ref LL_RCC_SYSCLK_DIV_256
Kojto	122:f9eeca106725	2097	* @arg @ref LL_RCC_SYSCLK_DIV_512
Kojto	122:f9eeca106725	2098	*/
Kojto	122:f9eeca106725	2099	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
Kojto	122:f9eeca106725	2100	{
Kojto	122:f9eeca106725	2101	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
Kojto	122:f9eeca106725	2102	}
Kojto	122:f9eeca106725	2103
Kojto	122:f9eeca106725	2104	/**
Kojto	122:f9eeca106725	2105	* @brief Get APB1 prescaler
Kojto	122:f9eeca106725	2106	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
Kojto	122:f9eeca106725	2107	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2108	* @arg @ref LL_RCC_APB1_DIV_1
Kojto	122:f9eeca106725	2109	* @arg @ref LL_RCC_APB1_DIV_2
Kojto	122:f9eeca106725	2110	* @arg @ref LL_RCC_APB1_DIV_4
Kojto	122:f9eeca106725	2111	* @arg @ref LL_RCC_APB1_DIV_8
Kojto	122:f9eeca106725	2112	* @arg @ref LL_RCC_APB1_DIV_16
Kojto	122:f9eeca106725	2113	*/
Kojto	122:f9eeca106725	2114	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
Kojto	122:f9eeca106725	2115	{
Kojto	122:f9eeca106725	2116	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
Kojto	122:f9eeca106725	2117	}
Kojto	122:f9eeca106725	2118
Kojto	122:f9eeca106725	2119	/**
Kojto	122:f9eeca106725	2120	* @brief Get APB2 prescaler
Kojto	122:f9eeca106725	2121	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
Kojto	122:f9eeca106725	2122	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2123	* @arg @ref LL_RCC_APB2_DIV_1
Kojto	122:f9eeca106725	2124	* @arg @ref LL_RCC_APB2_DIV_2
Kojto	122:f9eeca106725	2125	* @arg @ref LL_RCC_APB2_DIV_4
Kojto	122:f9eeca106725	2126	* @arg @ref LL_RCC_APB2_DIV_8
Kojto	122:f9eeca106725	2127	* @arg @ref LL_RCC_APB2_DIV_16
Kojto	122:f9eeca106725	2128	*/
Kojto	122:f9eeca106725	2129	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
Kojto	122:f9eeca106725	2130	{
Kojto	122:f9eeca106725	2131	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
Kojto	122:f9eeca106725	2132	}
Kojto	122:f9eeca106725	2133
Kojto	122:f9eeca106725	2134	/**
Kojto	122:f9eeca106725	2135	* @brief Set Clock After Wake-Up From Stop mode
Kojto	122:f9eeca106725	2136	* @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
Kojto	122:f9eeca106725	2137	* @param Clock This parameter can be one of the following values:
Kojto	122:f9eeca106725	2138	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
Kojto	122:f9eeca106725	2139	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
Kojto	122:f9eeca106725	2140	* @retval None
Kojto	122:f9eeca106725	2141	*/
Kojto	122:f9eeca106725	2142	__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
Kojto	122:f9eeca106725	2143	{
Kojto	122:f9eeca106725	2144	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
Kojto	122:f9eeca106725	2145	}
Kojto	122:f9eeca106725	2146
Kojto	122:f9eeca106725	2147	/**
Kojto	122:f9eeca106725	2148	* @brief Get Clock After Wake-Up From Stop mode
Kojto	122:f9eeca106725	2149	* @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
Kojto	122:f9eeca106725	2150	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2151	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
Kojto	122:f9eeca106725	2152	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
Kojto	122:f9eeca106725	2153	*/
Kojto	122:f9eeca106725	2154	__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
Kojto	122:f9eeca106725	2155	{
Kojto	122:f9eeca106725	2156	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
Kojto	122:f9eeca106725	2157	}
Kojto	122:f9eeca106725	2158
Kojto	122:f9eeca106725	2159	/**
Kojto	122:f9eeca106725	2160	* @}
Kojto	122:f9eeca106725	2161	*/
Kojto	122:f9eeca106725	2162
Kojto	122:f9eeca106725	2163	/** @defgroup RCC_LL_EF_MCO MCO
Kojto	122:f9eeca106725	2164	* @{
Kojto	122:f9eeca106725	2165	*/
Kojto	122:f9eeca106725	2166
Kojto	122:f9eeca106725	2167	/**
Kojto	122:f9eeca106725	2168	* @brief Configure MCOx
Kojto	122:f9eeca106725	2169	* @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
Kojto	122:f9eeca106725	2170	* CFGR MCOPRE LL_RCC_ConfigMCO
Kojto	122:f9eeca106725	2171	* @param MCOxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2172	* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
Kojto	122:f9eeca106725	2173	* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
Kojto	122:f9eeca106725	2174	* @arg @ref LL_RCC_MCO1SOURCE_MSI
Kojto	122:f9eeca106725	2175	* @arg @ref LL_RCC_MCO1SOURCE_HSI
Kojto	122:f9eeca106725	2176	* @arg @ref LL_RCC_MCO1SOURCE_HSE
Kojto	122:f9eeca106725	2177	* @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
Kojto	122:f9eeca106725	2178	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
Kojto	122:f9eeca106725	2179	* @arg @ref LL_RCC_MCO1SOURCE_LSI
Kojto	122:f9eeca106725	2180	* @arg @ref LL_RCC_MCO1SOURCE_LSE
Kojto	122:f9eeca106725	2181	*
Kojto	122:f9eeca106725	2182	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2183	* @param MCOxPrescaler This parameter can be one of the following values:
Kojto	122:f9eeca106725	2184	* @arg @ref LL_RCC_MCO1_DIV_1
Kojto	122:f9eeca106725	2185	* @arg @ref LL_RCC_MCO1_DIV_2
Kojto	122:f9eeca106725	2186	* @arg @ref LL_RCC_MCO1_DIV_4
Kojto	122:f9eeca106725	2187	* @arg @ref LL_RCC_MCO1_DIV_8
Kojto	122:f9eeca106725	2188	* @arg @ref LL_RCC_MCO1_DIV_16
Kojto	122:f9eeca106725	2189	* @retval None
Kojto	122:f9eeca106725	2190	*/
Kojto	122:f9eeca106725	2191	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
Kojto	122:f9eeca106725	2192	{
Kojto	122:f9eeca106725	2193	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE, MCOxSource \| MCOxPrescaler);
Kojto	122:f9eeca106725	2194	}
Kojto	122:f9eeca106725	2195
Kojto	122:f9eeca106725	2196	/**
Kojto	122:f9eeca106725	2197	* @}
Kojto	122:f9eeca106725	2198	*/
Kojto	122:f9eeca106725	2199
Kojto	122:f9eeca106725	2200	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
Kojto	122:f9eeca106725	2201	* @{
Kojto	122:f9eeca106725	2202	*/
Kojto	122:f9eeca106725	2203
Kojto	122:f9eeca106725	2204	/**
Kojto	122:f9eeca106725	2205	* @brief Configure USARTx clock source
Kojto	122:f9eeca106725	2206	* @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
Kojto	122:f9eeca106725	2207	* @param USARTxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2208	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
Kojto	122:f9eeca106725	2209	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2210	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2211	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2212	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2213	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2214	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2215	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2216	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
Kojto	122:f9eeca106725	2217	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
Kojto	122:f9eeca106725	2218	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
Kojto	122:f9eeca106725	2219	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
Kojto	122:f9eeca106725	2220	*
Kojto	122:f9eeca106725	2221	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2222	* @retval None
Kojto	122:f9eeca106725	2223	*/
Kojto	122:f9eeca106725	2224	__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
Kojto	122:f9eeca106725	2225	{
Kojto	122:f9eeca106725	2226	MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF));
Kojto	122:f9eeca106725	2227	}
Kojto	122:f9eeca106725	2228
Kojto	122:f9eeca106725	2229	#if defined(UART4) \|\| defined(UART5)
Kojto	122:f9eeca106725	2230	/**
Kojto	122:f9eeca106725	2231	* @brief Configure UARTx clock source
Kojto	122:f9eeca106725	2232	* @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
Kojto	122:f9eeca106725	2233	* @param UARTxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2234	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2235	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2236	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2237	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2238	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2239	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2240	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2241	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2242	* @retval None
Kojto	122:f9eeca106725	2243	*/
Kojto	122:f9eeca106725	2244	__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
Kojto	122:f9eeca106725	2245	{
Kojto	122:f9eeca106725	2246	MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF));
Kojto	122:f9eeca106725	2247	}
Kojto	122:f9eeca106725	2248	#endif /* UART4 \|\| UART5 */
Kojto	122:f9eeca106725	2249
Kojto	122:f9eeca106725	2250	/**
Kojto	122:f9eeca106725	2251	* @brief Configure LPUART1x clock source
Kojto	122:f9eeca106725	2252	* @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
Kojto	122:f9eeca106725	2253	* @param LPUARTxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2254	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2255	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2256	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2257	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2258	* @retval None
Kojto	122:f9eeca106725	2259	*/
Kojto	122:f9eeca106725	2260	__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
Kojto	122:f9eeca106725	2261	{
Kojto	122:f9eeca106725	2262	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
Kojto	122:f9eeca106725	2263	}
Kojto	122:f9eeca106725	2264
Kojto	122:f9eeca106725	2265	/**
Kojto	122:f9eeca106725	2266	* @brief Configure I2Cx clock source
Kojto	122:f9eeca106725	2267	* @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
Kojto	122:f9eeca106725	2268	* @param I2CxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2269	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2270	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2271	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2272	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
Kojto	122:f9eeca106725	2273	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
Kojto	122:f9eeca106725	2274	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
Kojto	122:f9eeca106725	2275	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2276	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2277	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
AnnaBridge	145:64910690c574	2278	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
AnnaBridge	145:64910690c574	2279	* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
AnnaBridge	145:64910690c574	2280	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
Kojto	122:f9eeca106725	2281	*
Kojto	122:f9eeca106725	2282	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2283	* @retval None
Kojto	122:f9eeca106725	2284	*/
Kojto	122:f9eeca106725	2285	__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
Kojto	122:f9eeca106725	2286	{
AnnaBridge	145:64910690c574	2287	__IO uint32_t reg = (__IO uint32_t )(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
AnnaBridge	145:64910690c574	2288	MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U)));
Kojto	122:f9eeca106725	2289	}
Kojto	122:f9eeca106725	2290
Kojto	122:f9eeca106725	2291	/**
Kojto	122:f9eeca106725	2292	* @brief Configure LPTIMx clock source
Kojto	122:f9eeca106725	2293	* @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
Kojto	122:f9eeca106725	2294	* @param LPTIMxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2295	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2296	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
Kojto	122:f9eeca106725	2297	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2298	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2299	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2300	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
Kojto	122:f9eeca106725	2301	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2302	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2303	* @retval None
Kojto	122:f9eeca106725	2304	*/
Kojto	122:f9eeca106725	2305	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
Kojto	122:f9eeca106725	2306	{
AnnaBridge	145:64910690c574	2307	MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
Kojto	122:f9eeca106725	2308	}
Kojto	122:f9eeca106725	2309
Kojto	122:f9eeca106725	2310	/**
Kojto	122:f9eeca106725	2311	* @brief Configure SAIx clock source
Kojto	122:f9eeca106725	2312	* @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource
Kojto	122:f9eeca106725	2313	* @param SAIxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2314	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2315	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
Kojto	122:f9eeca106725	2316	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2317	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
Kojto	122:f9eeca106725	2318	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
Kojto	122:f9eeca106725	2319	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
Kojto	122:f9eeca106725	2320	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
Kojto	122:f9eeca106725	2321	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
Kojto	122:f9eeca106725	2322	*
Kojto	122:f9eeca106725	2323	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2324	* @retval None
Kojto	122:f9eeca106725	2325	*/
Kojto	122:f9eeca106725	2326	__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
Kojto	122:f9eeca106725	2327	{
AnnaBridge	145:64910690c574	2328	MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
Kojto	122:f9eeca106725	2329	}
Kojto	122:f9eeca106725	2330
Kojto	122:f9eeca106725	2331	/**
Kojto	122:f9eeca106725	2332	* @brief Configure SDMMC1 clock source
Kojto	122:f9eeca106725	2333	* @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource
Kojto	122:f9eeca106725	2334	* @param SDMMCxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2335	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
AnnaBridge	145:64910690c574	2336	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
AnnaBridge	145:64910690c574	2337	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
Kojto	122:f9eeca106725	2338	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2339	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
AnnaBridge	145:64910690c574	2340	*
AnnaBridge	145:64910690c574	2341	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2342	* @retval None
Kojto	122:f9eeca106725	2343	*/
Kojto	122:f9eeca106725	2344	__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
Kojto	122:f9eeca106725	2345	{
Kojto	122:f9eeca106725	2346	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
Kojto	122:f9eeca106725	2347	}
Kojto	122:f9eeca106725	2348
Kojto	122:f9eeca106725	2349	/**
Kojto	122:f9eeca106725	2350	* @brief Configure RNG clock source
Kojto	122:f9eeca106725	2351	* @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
Kojto	122:f9eeca106725	2352	* @param RNGxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2353	* @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
AnnaBridge	145:64910690c574	2354	* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
Kojto	122:f9eeca106725	2355	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2356	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2357	* @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
AnnaBridge	145:64910690c574	2358	*
AnnaBridge	145:64910690c574	2359	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2360	* @retval None
Kojto	122:f9eeca106725	2361	*/
Kojto	122:f9eeca106725	2362	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
Kojto	122:f9eeca106725	2363	{
Kojto	122:f9eeca106725	2364	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
Kojto	122:f9eeca106725	2365	}
Kojto	122:f9eeca106725	2366
Kojto	122:f9eeca106725	2367	#if defined(USB_OTG_FS) \|\| defined(USB)
Kojto	122:f9eeca106725	2368	/**
Kojto	122:f9eeca106725	2369	* @brief Configure USB clock source
Kojto	122:f9eeca106725	2370	* @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
Kojto	122:f9eeca106725	2371	* @param USBxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2372	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
AnnaBridge	145:64910690c574	2373	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
Kojto	122:f9eeca106725	2374	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2375	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2376	* @arg @ref LL_RCC_USB_CLKSOURCE_MSI
AnnaBridge	145:64910690c574	2377	*
AnnaBridge	145:64910690c574	2378	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2379	* @retval None
Kojto	122:f9eeca106725	2380	*/
Kojto	122:f9eeca106725	2381	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
Kojto	122:f9eeca106725	2382	{
Kojto	122:f9eeca106725	2383	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
Kojto	122:f9eeca106725	2384	}
Kojto	122:f9eeca106725	2385	#endif /* USB_OTG_FS \|\| USB */
Kojto	122:f9eeca106725	2386
Kojto	122:f9eeca106725	2387	/**
Kojto	122:f9eeca106725	2388	* @brief Configure ADC clock source
Kojto	122:f9eeca106725	2389	* @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
Kojto	122:f9eeca106725	2390	* @param ADCxSource This parameter can be one of the following values:
Kojto	122:f9eeca106725	2391	* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2392	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2393	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
Kojto	122:f9eeca106725	2394	* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2395	*
Kojto	122:f9eeca106725	2396	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2397	* @retval None
Kojto	122:f9eeca106725	2398	*/
Kojto	122:f9eeca106725	2399	__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
Kojto	122:f9eeca106725	2400	{
Kojto	122:f9eeca106725	2401	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
Kojto	122:f9eeca106725	2402	}
Kojto	122:f9eeca106725	2403
AnnaBridge	145:64910690c574	2404	#if defined(SWPMI1)
Kojto	122:f9eeca106725	2405	/**
Kojto	122:f9eeca106725	2406	* @brief Configure SWPMI clock source
Kojto	122:f9eeca106725	2407	* @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource
Kojto	122:f9eeca106725	2408	* @param SWPMIxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2409	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2410	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2411	* @retval None
Kojto	122:f9eeca106725	2412	*/
Kojto	122:f9eeca106725	2413	__STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
Kojto	122:f9eeca106725	2414	{
Kojto	122:f9eeca106725	2415	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
Kojto	122:f9eeca106725	2416	}
AnnaBridge	145:64910690c574	2417	#endif /* SWPMI1 */
Kojto	122:f9eeca106725	2418
Kojto	122:f9eeca106725	2419	#if defined(DFSDM1_Channel0)
Kojto	122:f9eeca106725	2420	/**
AnnaBridge	145:64910690c574	2421	* @brief Configure DFSDM Kernel clock source
Kojto	122:f9eeca106725	2422	* @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource
Kojto	122:f9eeca106725	2423	* @param DFSDMxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2424	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
Kojto	122:f9eeca106725	2425	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2426	* @retval None
Kojto	122:f9eeca106725	2427	*/
Kojto	122:f9eeca106725	2428	__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
Kojto	122:f9eeca106725	2429	{
Kojto	122:f9eeca106725	2430	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);
Kojto	122:f9eeca106725	2431	}
Kojto	122:f9eeca106725	2432	#endif /* DFSDM1_Channel0 */
Kojto	122:f9eeca106725	2433
Kojto	122:f9eeca106725	2434	/**
Kojto	122:f9eeca106725	2435	* @brief Get USARTx clock source
Kojto	122:f9eeca106725	2436	* @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
Kojto	122:f9eeca106725	2437	* @param USARTx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2438	* @arg @ref LL_RCC_USART1_CLKSOURCE
Kojto	122:f9eeca106725	2439	* @arg @ref LL_RCC_USART2_CLKSOURCE
Kojto	122:f9eeca106725	2440	* @arg @ref LL_RCC_USART3_CLKSOURCE (*)
Kojto	122:f9eeca106725	2441	*
Kojto	122:f9eeca106725	2442	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2443	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2444	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
Kojto	122:f9eeca106725	2445	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2446	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2447	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2448	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2449	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2450	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2451	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2452	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
Kojto	122:f9eeca106725	2453	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
Kojto	122:f9eeca106725	2454	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
Kojto	122:f9eeca106725	2455	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
Kojto	122:f9eeca106725	2456	*
Kojto	122:f9eeca106725	2457	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2458	*/
Kojto	122:f9eeca106725	2459	__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
Kojto	122:f9eeca106725	2460	{
AnnaBridge	145:64910690c574	2461	return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) \| (USARTx << 16U));
Kojto	122:f9eeca106725	2462	}
Kojto	122:f9eeca106725	2463
Kojto	122:f9eeca106725	2464	#if defined(UART4) \|\| defined(UART5)
Kojto	122:f9eeca106725	2465	/**
Kojto	122:f9eeca106725	2466	* @brief Get UARTx clock source
Kojto	122:f9eeca106725	2467	* @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
Kojto	122:f9eeca106725	2468	* @param UARTx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2469	* @arg @ref LL_RCC_UART4_CLKSOURCE
Kojto	122:f9eeca106725	2470	* @arg @ref LL_RCC_UART5_CLKSOURCE
Kojto	122:f9eeca106725	2471	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2472	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2473	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2474	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2475	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2476	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2477	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2478	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2479	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2480	*/
Kojto	122:f9eeca106725	2481	__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
Kojto	122:f9eeca106725	2482	{
AnnaBridge	145:64910690c574	2483	return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) \| (UARTx << 16U));
Kojto	122:f9eeca106725	2484	}
Kojto	122:f9eeca106725	2485	#endif /* UART4 \|\| UART5 */
Kojto	122:f9eeca106725	2486
Kojto	122:f9eeca106725	2487	/**
Kojto	122:f9eeca106725	2488	* @brief Get LPUARTx clock source
Kojto	122:f9eeca106725	2489	* @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
Kojto	122:f9eeca106725	2490	* @param LPUARTx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2491	* @arg @ref LL_RCC_LPUART1_CLKSOURCE
Kojto	122:f9eeca106725	2492	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2493	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2494	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2495	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2496	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2497	*/
Kojto	122:f9eeca106725	2498	__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
Kojto	122:f9eeca106725	2499	{
Kojto	122:f9eeca106725	2500	return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
Kojto	122:f9eeca106725	2501	}
Kojto	122:f9eeca106725	2502
Kojto	122:f9eeca106725	2503	/**
Kojto	122:f9eeca106725	2504	* @brief Get I2Cx clock source
Kojto	122:f9eeca106725	2505	* @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
Kojto	122:f9eeca106725	2506	* @param I2Cx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2507	* @arg @ref LL_RCC_I2C1_CLKSOURCE
Kojto	122:f9eeca106725	2508	* @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
Kojto	122:f9eeca106725	2509	* @arg @ref LL_RCC_I2C3_CLKSOURCE
AnnaBridge	145:64910690c574	2510	* @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
Kojto	122:f9eeca106725	2511	*
Kojto	122:f9eeca106725	2512	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2513	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2514	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2515	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2516	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2517	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
Kojto	122:f9eeca106725	2518	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
Kojto	122:f9eeca106725	2519	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
Kojto	122:f9eeca106725	2520	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2521	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2522	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
AnnaBridge	145:64910690c574	2523	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
AnnaBridge	145:64910690c574	2524	* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
AnnaBridge	145:64910690c574	2525	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
Kojto	122:f9eeca106725	2526	*
Kojto	122:f9eeca106725	2527	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2528	*/
Kojto	122:f9eeca106725	2529	__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
Kojto	122:f9eeca106725	2530	{
AnnaBridge	145:64910690c574	2531	__IO uint32_t reg = (__IO uint32_t )(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
AnnaBridge	145:64910690c574	2532	return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x0000FF0000U) >> 16U)) >> ((I2Cx & 0x0000FF0000U) >> 16U)) \| (I2Cx & 0xFFFF0000U));
Kojto	122:f9eeca106725	2533	}
Kojto	122:f9eeca106725	2534
Kojto	122:f9eeca106725	2535	/**
Kojto	122:f9eeca106725	2536	* @brief Get LPTIMx clock source
Kojto	122:f9eeca106725	2537	* @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
Kojto	122:f9eeca106725	2538	* @param LPTIMx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2539	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
Kojto	122:f9eeca106725	2540	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE
Kojto	122:f9eeca106725	2541	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2542	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2543	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
Kojto	122:f9eeca106725	2544	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2545	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2546	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2547	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
Kojto	122:f9eeca106725	2548	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2549	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2550	*/
Kojto	122:f9eeca106725	2551	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
Kojto	122:f9eeca106725	2552	{
AnnaBridge	145:64910690c574	2553	return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16U \| LPTIMx);
Kojto	122:f9eeca106725	2554	}
Kojto	122:f9eeca106725	2555
Kojto	122:f9eeca106725	2556	/**
Kojto	122:f9eeca106725	2557	* @brief Get SAIx clock source
Kojto	122:f9eeca106725	2558	* @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource
Kojto	122:f9eeca106725	2559	* @param SAIx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2560	* @arg @ref LL_RCC_SAI1_CLKSOURCE
Kojto	122:f9eeca106725	2561	* @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
Kojto	122:f9eeca106725	2562	*
Kojto	122:f9eeca106725	2563	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2564	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2565	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2566	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
Kojto	122:f9eeca106725	2567	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2568	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
Kojto	122:f9eeca106725	2569	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
Kojto	122:f9eeca106725	2570	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
Kojto	122:f9eeca106725	2571	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
Kojto	122:f9eeca106725	2572	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
Kojto	122:f9eeca106725	2573	*
Kojto	122:f9eeca106725	2574	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2575	*/
Kojto	122:f9eeca106725	2576	__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
Kojto	122:f9eeca106725	2577	{
AnnaBridge	145:64910690c574	2578	return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U \| SAIx);
Kojto	122:f9eeca106725	2579	}
Kojto	122:f9eeca106725	2580
Kojto	122:f9eeca106725	2581	/**
Kojto	122:f9eeca106725	2582	* @brief Get SDMMCx clock source
Kojto	122:f9eeca106725	2583	* @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource
Kojto	122:f9eeca106725	2584	* @param SDMMCx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2585	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE
Kojto	122:f9eeca106725	2586	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	2587	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
AnnaBridge	145:64910690c574	2588	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
Kojto	122:f9eeca106725	2589	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2590	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2591	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
AnnaBridge	145:64910690c574	2592	*
AnnaBridge	145:64910690c574	2593	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2594	*/
Kojto	122:f9eeca106725	2595	__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
Kojto	122:f9eeca106725	2596	{
Kojto	122:f9eeca106725	2597	return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
Kojto	122:f9eeca106725	2598	}
Kojto	122:f9eeca106725	2599
Kojto	122:f9eeca106725	2600	/**
Kojto	122:f9eeca106725	2601	* @brief Get RNGx clock source
Kojto	122:f9eeca106725	2602	* @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
Kojto	122:f9eeca106725	2603	* @param RNGx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2604	* @arg @ref LL_RCC_RNG_CLKSOURCE
Kojto	122:f9eeca106725	2605	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	2606	* @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
AnnaBridge	145:64910690c574	2607	* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
Kojto	122:f9eeca106725	2608	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2609	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2610	* @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
AnnaBridge	145:64910690c574	2611	*
AnnaBridge	145:64910690c574	2612	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2613	*/
Kojto	122:f9eeca106725	2614	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
Kojto	122:f9eeca106725	2615	{
Kojto	122:f9eeca106725	2616	return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
Kojto	122:f9eeca106725	2617	}
Kojto	122:f9eeca106725	2618
Kojto	122:f9eeca106725	2619	#if defined(USB_OTG_FS) \|\| defined(USB)
Kojto	122:f9eeca106725	2620	/**
Kojto	122:f9eeca106725	2621	* @brief Get USBx clock source
Kojto	122:f9eeca106725	2622	* @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
Kojto	122:f9eeca106725	2623	* @param USBx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2624	* @arg @ref LL_RCC_USB_CLKSOURCE
Kojto	122:f9eeca106725	2625	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	2626	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
AnnaBridge	145:64910690c574	2627	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
Kojto	122:f9eeca106725	2628	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2629	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
Kojto	122:f9eeca106725	2630	* @arg @ref LL_RCC_USB_CLKSOURCE_MSI
AnnaBridge	145:64910690c574	2631	*
AnnaBridge	145:64910690c574	2632	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2633	*/
Kojto	122:f9eeca106725	2634	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
Kojto	122:f9eeca106725	2635	{
Kojto	122:f9eeca106725	2636	return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
Kojto	122:f9eeca106725	2637	}
Kojto	122:f9eeca106725	2638	#endif /* USB_OTG_FS \|\| USB */
Kojto	122:f9eeca106725	2639
Kojto	122:f9eeca106725	2640	/**
Kojto	122:f9eeca106725	2641	* @brief Get ADCx clock source
Kojto	122:f9eeca106725	2642	* @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
Kojto	122:f9eeca106725	2643	* @param ADCx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2644	* @arg @ref LL_RCC_ADC_CLKSOURCE
Kojto	122:f9eeca106725	2645	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2646	* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2647	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
Kojto	122:f9eeca106725	2648	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
Kojto	122:f9eeca106725	2649	* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2650	*
Kojto	122:f9eeca106725	2651	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	2652	*/
Kojto	122:f9eeca106725	2653	__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
Kojto	122:f9eeca106725	2654	{
Kojto	122:f9eeca106725	2655	return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
Kojto	122:f9eeca106725	2656	}
Kojto	122:f9eeca106725	2657
AnnaBridge	145:64910690c574	2658	#if defined(SWPMI1)
Kojto	122:f9eeca106725	2659	/**
Kojto	122:f9eeca106725	2660	* @brief Get SWPMIx clock source
Kojto	122:f9eeca106725	2661	* @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource
Kojto	122:f9eeca106725	2662	* @param SPWMIx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2663	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE
Kojto	122:f9eeca106725	2664	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	2665	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
Kojto	122:f9eeca106725	2666	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
Kojto	122:f9eeca106725	2667	*/
Kojto	122:f9eeca106725	2668	__STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
Kojto	122:f9eeca106725	2669	{
Kojto	122:f9eeca106725	2670	return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
Kojto	122:f9eeca106725	2671	}
AnnaBridge	145:64910690c574	2672	#endif /* SWPMI1 */
Kojto	122:f9eeca106725	2673
Kojto	122:f9eeca106725	2674	#if defined(DFSDM1_Channel0)
Kojto	122:f9eeca106725	2675	/**
AnnaBridge	145:64910690c574	2676	* @brief Get DFSDMx Kernel clock source
Kojto	122:f9eeca106725	2677	* @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource
Kojto	122:f9eeca106725	2678	* @param DFSDMx This parameter can be one of the following values:
Kojto	122:f9eeca106725	2679	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
Kojto	122:f9eeca106725	2680	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	2681	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
Kojto	122:f9eeca106725	2682	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
Kojto	122:f9eeca106725	2683	*/
Kojto	122:f9eeca106725	2684	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
Kojto	122:f9eeca106725	2685	{
Kojto	122:f9eeca106725	2686	return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
Kojto	122:f9eeca106725	2687	}
Kojto	122:f9eeca106725	2688	#endif /* DFSDM1_Channel0 */
Kojto	122:f9eeca106725	2689
Kojto	122:f9eeca106725	2690	/**
Kojto	122:f9eeca106725	2691	* @}
Kojto	122:f9eeca106725	2692	*/
Kojto	122:f9eeca106725	2693
Kojto	122:f9eeca106725	2694	/** @defgroup RCC_LL_EF_RTC RTC
Kojto	122:f9eeca106725	2695	* @{
Kojto	122:f9eeca106725	2696	*/
Kojto	122:f9eeca106725	2697
Kojto	122:f9eeca106725	2698	/**
Kojto	122:f9eeca106725	2699	* @brief Set RTC Clock Source
Kojto	122:f9eeca106725	2700	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
Kojto	122:f9eeca106725	2701	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
Kojto	122:f9eeca106725	2702	* set). The BDRST bit can be used to reset them.
Kojto	122:f9eeca106725	2703	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
Kojto	122:f9eeca106725	2704	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	2705	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2706	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2707	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
Kojto	122:f9eeca106725	2708	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
Kojto	122:f9eeca106725	2709	* @retval None
Kojto	122:f9eeca106725	2710	*/
Kojto	122:f9eeca106725	2711	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
Kojto	122:f9eeca106725	2712	{
Kojto	122:f9eeca106725	2713	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
Kojto	122:f9eeca106725	2714	}
Kojto	122:f9eeca106725	2715
Kojto	122:f9eeca106725	2716	/**
Kojto	122:f9eeca106725	2717	* @brief Get RTC Clock Source
Kojto	122:f9eeca106725	2718	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
Kojto	122:f9eeca106725	2719	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	2720	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
Kojto	122:f9eeca106725	2721	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
Kojto	122:f9eeca106725	2722	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
Kojto	122:f9eeca106725	2723	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
Kojto	122:f9eeca106725	2724	*/
Kojto	122:f9eeca106725	2725	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
Kojto	122:f9eeca106725	2726	{
Kojto	122:f9eeca106725	2727	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
Kojto	122:f9eeca106725	2728	}
Kojto	122:f9eeca106725	2729
Kojto	122:f9eeca106725	2730	/**
Kojto	122:f9eeca106725	2731	* @brief Enable RTC
Kojto	122:f9eeca106725	2732	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
Kojto	122:f9eeca106725	2733	* @retval None
Kojto	122:f9eeca106725	2734	*/
Kojto	122:f9eeca106725	2735	__STATIC_INLINE void LL_RCC_EnableRTC(void)
Kojto	122:f9eeca106725	2736	{
Kojto	122:f9eeca106725	2737	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
Kojto	122:f9eeca106725	2738	}
Kojto	122:f9eeca106725	2739
Kojto	122:f9eeca106725	2740	/**
Kojto	122:f9eeca106725	2741	* @brief Disable RTC
Kojto	122:f9eeca106725	2742	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
Kojto	122:f9eeca106725	2743	* @retval None
Kojto	122:f9eeca106725	2744	*/
Kojto	122:f9eeca106725	2745	__STATIC_INLINE void LL_RCC_DisableRTC(void)
Kojto	122:f9eeca106725	2746	{
Kojto	122:f9eeca106725	2747	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
Kojto	122:f9eeca106725	2748	}
Kojto	122:f9eeca106725	2749
Kojto	122:f9eeca106725	2750	/**
Kojto	122:f9eeca106725	2751	* @brief Check if RTC has been enabled or not
Kojto	122:f9eeca106725	2752	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
Kojto	122:f9eeca106725	2753	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	2754	*/
Kojto	122:f9eeca106725	2755	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
Kojto	122:f9eeca106725	2756	{
Kojto	122:f9eeca106725	2757	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
Kojto	122:f9eeca106725	2758	}
Kojto	122:f9eeca106725	2759
Kojto	122:f9eeca106725	2760	/**
Kojto	122:f9eeca106725	2761	* @brief Force the Backup domain reset
Kojto	122:f9eeca106725	2762	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
Kojto	122:f9eeca106725	2763	* @retval None
Kojto	122:f9eeca106725	2764	*/
Kojto	122:f9eeca106725	2765	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
Kojto	122:f9eeca106725	2766	{
Kojto	122:f9eeca106725	2767	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
Kojto	122:f9eeca106725	2768	}
Kojto	122:f9eeca106725	2769
Kojto	122:f9eeca106725	2770	/**
Kojto	122:f9eeca106725	2771	* @brief Release the Backup domain reset
Kojto	122:f9eeca106725	2772	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
Kojto	122:f9eeca106725	2773	* @retval None
Kojto	122:f9eeca106725	2774	*/
Kojto	122:f9eeca106725	2775	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
Kojto	122:f9eeca106725	2776	{
Kojto	122:f9eeca106725	2777	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
Kojto	122:f9eeca106725	2778	}
Kojto	122:f9eeca106725	2779
Kojto	122:f9eeca106725	2780	/**
Kojto	122:f9eeca106725	2781	* @}
Kojto	122:f9eeca106725	2782	*/
Kojto	122:f9eeca106725	2783
AnnaBridge	145:64910690c574	2784
Kojto	122:f9eeca106725	2785	/** @defgroup RCC_LL_EF_PLL PLL
Kojto	122:f9eeca106725	2786	* @{
Kojto	122:f9eeca106725	2787	*/
Kojto	122:f9eeca106725	2788
Kojto	122:f9eeca106725	2789	/**
Kojto	122:f9eeca106725	2790	* @brief Enable PLL
Kojto	122:f9eeca106725	2791	* @rmtoll CR PLLON LL_RCC_PLL_Enable
Kojto	122:f9eeca106725	2792	* @retval None
Kojto	122:f9eeca106725	2793	*/
Kojto	122:f9eeca106725	2794	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
Kojto	122:f9eeca106725	2795	{
Kojto	122:f9eeca106725	2796	SET_BIT(RCC->CR, RCC_CR_PLLON);
Kojto	122:f9eeca106725	2797	}
Kojto	122:f9eeca106725	2798
Kojto	122:f9eeca106725	2799	/**
Kojto	122:f9eeca106725	2800	* @brief Disable PLL
Kojto	122:f9eeca106725	2801	* @note Cannot be disabled if the PLL clock is used as the system clock
Kojto	122:f9eeca106725	2802	* @rmtoll CR PLLON LL_RCC_PLL_Disable
Kojto	122:f9eeca106725	2803	* @retval None
Kojto	122:f9eeca106725	2804	*/
Kojto	122:f9eeca106725	2805	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
Kojto	122:f9eeca106725	2806	{
Kojto	122:f9eeca106725	2807	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
Kojto	122:f9eeca106725	2808	}
Kojto	122:f9eeca106725	2809
Kojto	122:f9eeca106725	2810	/**
Kojto	122:f9eeca106725	2811	* @brief Check if PLL Ready
Kojto	122:f9eeca106725	2812	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
Kojto	122:f9eeca106725	2813	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	2814	*/
Kojto	122:f9eeca106725	2815	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
Kojto	122:f9eeca106725	2816	{
Kojto	122:f9eeca106725	2817	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
Kojto	122:f9eeca106725	2818	}
Kojto	122:f9eeca106725	2819
Kojto	122:f9eeca106725	2820	/**
Kojto	122:f9eeca106725	2821	* @brief Configure PLL used for SYSCLK Domain
Kojto	122:f9eeca106725	2822	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	2823	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	2824	* @note PLLN/PLLR can be written only when PLL is disabled
Kojto	122:f9eeca106725	2825	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
Kojto	122:f9eeca106725	2826	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
Kojto	122:f9eeca106725	2827	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
Kojto	122:f9eeca106725	2828	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
Kojto	122:f9eeca106725	2829	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	2830	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	2831	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	2832	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	2833	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	2834	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	2835	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	2836	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	2837	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	2838	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	2839	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	2840	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	2841	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	2842	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	2843	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	2844	* @param PLLR This parameter can be one of the following values:
Kojto	122:f9eeca106725	2845	* @arg @ref LL_RCC_PLLR_DIV_2
Kojto	122:f9eeca106725	2846	* @arg @ref LL_RCC_PLLR_DIV_4
Kojto	122:f9eeca106725	2847	* @arg @ref LL_RCC_PLLR_DIV_6
Kojto	122:f9eeca106725	2848	* @arg @ref LL_RCC_PLLR_DIV_8
Kojto	122:f9eeca106725	2849	* @retval None
Kojto	122:f9eeca106725	2850	*/
Kojto	122:f9eeca106725	2851	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Kojto	122:f9eeca106725	2852	{
Kojto	122:f9eeca106725	2853	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
AnnaBridge	145:64910690c574	2854	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
Kojto	122:f9eeca106725	2855	}
Kojto	122:f9eeca106725	2856
Kojto	122:f9eeca106725	2857	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	2858	/**
Kojto	122:f9eeca106725	2859	* @brief Configure PLL used for SAI domain clock
Kojto	122:f9eeca106725	2860	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	2861	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	2862	* @note PLLN/PLLP can be written only when PLL is disabled
Kojto	122:f9eeca106725	2863	* @note This can be selected for SAI1 or SAI2 (*)
Kojto	122:f9eeca106725	2864	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	2865	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	2866	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	2867	* PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI
Kojto	122:f9eeca106725	2868	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	2869	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	2870	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	2871	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	2872	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	2873	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	2874	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	2875	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	2876	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	2877	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	2878	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	2879	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	2880	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	2881	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	2882	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	2883	* @param PLLP This parameter can be one of the following values:
Kojto	122:f9eeca106725	2884	* @arg @ref LL_RCC_PLLP_DIV_2
Kojto	122:f9eeca106725	2885	* @arg @ref LL_RCC_PLLP_DIV_3
Kojto	122:f9eeca106725	2886	* @arg @ref LL_RCC_PLLP_DIV_4
Kojto	122:f9eeca106725	2887	* @arg @ref LL_RCC_PLLP_DIV_5
Kojto	122:f9eeca106725	2888	* @arg @ref LL_RCC_PLLP_DIV_6
Kojto	122:f9eeca106725	2889	* @arg @ref LL_RCC_PLLP_DIV_7
Kojto	122:f9eeca106725	2890	* @arg @ref LL_RCC_PLLP_DIV_8
Kojto	122:f9eeca106725	2891	* @arg @ref LL_RCC_PLLP_DIV_9
Kojto	122:f9eeca106725	2892	* @arg @ref LL_RCC_PLLP_DIV_10
Kojto	122:f9eeca106725	2893	* @arg @ref LL_RCC_PLLP_DIV_11
Kojto	122:f9eeca106725	2894	* @arg @ref LL_RCC_PLLP_DIV_12
Kojto	122:f9eeca106725	2895	* @arg @ref LL_RCC_PLLP_DIV_13
Kojto	122:f9eeca106725	2896	* @arg @ref LL_RCC_PLLP_DIV_14
Kojto	122:f9eeca106725	2897	* @arg @ref LL_RCC_PLLP_DIV_15
Kojto	122:f9eeca106725	2898	* @arg @ref LL_RCC_PLLP_DIV_16
Kojto	122:f9eeca106725	2899	* @arg @ref LL_RCC_PLLP_DIV_17
Kojto	122:f9eeca106725	2900	* @arg @ref LL_RCC_PLLP_DIV_18
Kojto	122:f9eeca106725	2901	* @arg @ref LL_RCC_PLLP_DIV_19
Kojto	122:f9eeca106725	2902	* @arg @ref LL_RCC_PLLP_DIV_20
Kojto	122:f9eeca106725	2903	* @arg @ref LL_RCC_PLLP_DIV_21
Kojto	122:f9eeca106725	2904	* @arg @ref LL_RCC_PLLP_DIV_22
Kojto	122:f9eeca106725	2905	* @arg @ref LL_RCC_PLLP_DIV_23
Kojto	122:f9eeca106725	2906	* @arg @ref LL_RCC_PLLP_DIV_24
Kojto	122:f9eeca106725	2907	* @arg @ref LL_RCC_PLLP_DIV_25
Kojto	122:f9eeca106725	2908	* @arg @ref LL_RCC_PLLP_DIV_26
Kojto	122:f9eeca106725	2909	* @arg @ref LL_RCC_PLLP_DIV_27
Kojto	122:f9eeca106725	2910	* @arg @ref LL_RCC_PLLP_DIV_28
Kojto	122:f9eeca106725	2911	* @arg @ref LL_RCC_PLLP_DIV_29
Kojto	122:f9eeca106725	2912	* @arg @ref LL_RCC_PLLP_DIV_30
Kojto	122:f9eeca106725	2913	* @arg @ref LL_RCC_PLLP_DIV_31
Kojto	122:f9eeca106725	2914	* @retval None
Kojto	122:f9eeca106725	2915	*/
Kojto	122:f9eeca106725	2916	#else
Kojto	122:f9eeca106725	2917	/**
Kojto	122:f9eeca106725	2918	* @brief Configure PLL used for SAI domain clock
Kojto	122:f9eeca106725	2919	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	2920	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	2921	* @note PLLN/PLLP can be written only when PLL is disabled
Kojto	122:f9eeca106725	2922	* @note This can be selected for SAI1 or SAI2 (*)
Kojto	122:f9eeca106725	2923	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	2924	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	2925	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	2926	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
Kojto	122:f9eeca106725	2927	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	2928	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	2929	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	2930	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	2931	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	2932	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	2933	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	2934	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	2935	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	2936	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	2937	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	2938	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	2939	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	2940	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	2941	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	2942	* @param PLLP This parameter can be one of the following values:
Kojto	122:f9eeca106725	2943	* @arg @ref LL_RCC_PLLP_DIV_7
Kojto	122:f9eeca106725	2944	* @arg @ref LL_RCC_PLLP_DIV_17
Kojto	122:f9eeca106725	2945	* @retval None
Kojto	122:f9eeca106725	2946	*/
Kojto	122:f9eeca106725	2947	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	2948	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Kojto	122:f9eeca106725	2949	{
Kojto	122:f9eeca106725	2950	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	2951	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLPDIV,
AnnaBridge	145:64910690c574	2952	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLP);
Kojto	122:f9eeca106725	2953	#else
Kojto	122:f9eeca106725	2954	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLP,
AnnaBridge	145:64910690c574	2955	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLP);
Kojto	122:f9eeca106725	2956	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	2957	}
Kojto	122:f9eeca106725	2958
Kojto	122:f9eeca106725	2959	/**
Kojto	122:f9eeca106725	2960	* @brief Configure PLL used for 48Mhz domain clock
Kojto	122:f9eeca106725	2961	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	2962	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	2963	* @note PLLN/PLLQ can be written only when PLL is disabled
Kojto	122:f9eeca106725	2964	* @note This can be selected for USB, RNG, SDMMC
Kojto	122:f9eeca106725	2965	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
Kojto	122:f9eeca106725	2966	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
Kojto	122:f9eeca106725	2967	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
Kojto	122:f9eeca106725	2968	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
Kojto	122:f9eeca106725	2969	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	2970	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	2971	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	2972	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	2973	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	2974	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	2975	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	2976	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	2977	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	2978	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	2979	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	2980	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	2981	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	2982	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	2983	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	2984	* @param PLLQ This parameter can be one of the following values:
Kojto	122:f9eeca106725	2985	* @arg @ref LL_RCC_PLLQ_DIV_2
Kojto	122:f9eeca106725	2986	* @arg @ref LL_RCC_PLLQ_DIV_4
Kojto	122:f9eeca106725	2987	* @arg @ref LL_RCC_PLLQ_DIV_6
Kojto	122:f9eeca106725	2988	* @arg @ref LL_RCC_PLLQ_DIV_8
Kojto	122:f9eeca106725	2989	* @retval None
Kojto	122:f9eeca106725	2990	*/
Kojto	122:f9eeca106725	2991	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Kojto	122:f9eeca106725	2992	{
Kojto	122:f9eeca106725	2993	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
AnnaBridge	145:64910690c574	2994	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLQ);
Kojto	122:f9eeca106725	2995	}
Kojto	122:f9eeca106725	2996
Kojto	122:f9eeca106725	2997	/**
Kojto	122:f9eeca106725	2998	* @brief Get Main PLL multiplication factor for VCO
Kojto	122:f9eeca106725	2999	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
Kojto	122:f9eeca106725	3000	* @retval Between 8 and 86
Kojto	122:f9eeca106725	3001	*/
Kojto	122:f9eeca106725	3002	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
Kojto	122:f9eeca106725	3003	{
AnnaBridge	145:64910690c574	3004	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
Kojto	122:f9eeca106725	3005	}
Kojto	122:f9eeca106725	3006
Kojto	122:f9eeca106725	3007	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	3008	/**
Kojto	122:f9eeca106725	3009	* @brief Get Main PLL division factor for PLLP
Kojto	122:f9eeca106725	3010	* @note used for PLLSAI3CLK (SAI1 and SAI2 clock)
Kojto	122:f9eeca106725	3011	* @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP
Kojto	122:f9eeca106725	3012	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3013	* @arg @ref LL_RCC_PLLP_DIV_2
Kojto	122:f9eeca106725	3014	* @arg @ref LL_RCC_PLLP_DIV_3
Kojto	122:f9eeca106725	3015	* @arg @ref LL_RCC_PLLP_DIV_4
Kojto	122:f9eeca106725	3016	* @arg @ref LL_RCC_PLLP_DIV_5
Kojto	122:f9eeca106725	3017	* @arg @ref LL_RCC_PLLP_DIV_6
Kojto	122:f9eeca106725	3018	* @arg @ref LL_RCC_PLLP_DIV_7
Kojto	122:f9eeca106725	3019	* @arg @ref LL_RCC_PLLP_DIV_8
Kojto	122:f9eeca106725	3020	* @arg @ref LL_RCC_PLLP_DIV_9
Kojto	122:f9eeca106725	3021	* @arg @ref LL_RCC_PLLP_DIV_10
Kojto	122:f9eeca106725	3022	* @arg @ref LL_RCC_PLLP_DIV_11
Kojto	122:f9eeca106725	3023	* @arg @ref LL_RCC_PLLP_DIV_12
Kojto	122:f9eeca106725	3024	* @arg @ref LL_RCC_PLLP_DIV_13
Kojto	122:f9eeca106725	3025	* @arg @ref LL_RCC_PLLP_DIV_14
Kojto	122:f9eeca106725	3026	* @arg @ref LL_RCC_PLLP_DIV_15
Kojto	122:f9eeca106725	3027	* @arg @ref LL_RCC_PLLP_DIV_16
Kojto	122:f9eeca106725	3028	* @arg @ref LL_RCC_PLLP_DIV_17
Kojto	122:f9eeca106725	3029	* @arg @ref LL_RCC_PLLP_DIV_18
Kojto	122:f9eeca106725	3030	* @arg @ref LL_RCC_PLLP_DIV_19
Kojto	122:f9eeca106725	3031	* @arg @ref LL_RCC_PLLP_DIV_20
Kojto	122:f9eeca106725	3032	* @arg @ref LL_RCC_PLLP_DIV_21
Kojto	122:f9eeca106725	3033	* @arg @ref LL_RCC_PLLP_DIV_22
Kojto	122:f9eeca106725	3034	* @arg @ref LL_RCC_PLLP_DIV_23
Kojto	122:f9eeca106725	3035	* @arg @ref LL_RCC_PLLP_DIV_24
Kojto	122:f9eeca106725	3036	* @arg @ref LL_RCC_PLLP_DIV_25
Kojto	122:f9eeca106725	3037	* @arg @ref LL_RCC_PLLP_DIV_26
Kojto	122:f9eeca106725	3038	* @arg @ref LL_RCC_PLLP_DIV_27
Kojto	122:f9eeca106725	3039	* @arg @ref LL_RCC_PLLP_DIV_28
Kojto	122:f9eeca106725	3040	* @arg @ref LL_RCC_PLLP_DIV_29
Kojto	122:f9eeca106725	3041	* @arg @ref LL_RCC_PLLP_DIV_30
Kojto	122:f9eeca106725	3042	* @arg @ref LL_RCC_PLLP_DIV_31
Kojto	122:f9eeca106725	3043	*/
Kojto	122:f9eeca106725	3044	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
Kojto	122:f9eeca106725	3045	{
Kojto	122:f9eeca106725	3046	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
Kojto	122:f9eeca106725	3047	}
Kojto	122:f9eeca106725	3048	#else
Kojto	122:f9eeca106725	3049	/**
Kojto	122:f9eeca106725	3050	* @brief Get Main PLL division factor for PLLP
Kojto	122:f9eeca106725	3051	* @note used for PLLSAI3CLK (SAI1 and SAI2 clock)
Kojto	122:f9eeca106725	3052	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
Kojto	122:f9eeca106725	3053	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3054	* @arg @ref LL_RCC_PLLP_DIV_7
Kojto	122:f9eeca106725	3055	* @arg @ref LL_RCC_PLLP_DIV_17
Kojto	122:f9eeca106725	3056	*/
Kojto	122:f9eeca106725	3057	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
Kojto	122:f9eeca106725	3058	{
Kojto	122:f9eeca106725	3059	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
Kojto	122:f9eeca106725	3060	}
Kojto	122:f9eeca106725	3061	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	3062
Kojto	122:f9eeca106725	3063	/**
Kojto	122:f9eeca106725	3064	* @brief Get Main PLL division factor for PLLQ
Kojto	122:f9eeca106725	3065	* @note used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
Kojto	122:f9eeca106725	3066	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
Kojto	122:f9eeca106725	3067	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3068	* @arg @ref LL_RCC_PLLQ_DIV_2
Kojto	122:f9eeca106725	3069	* @arg @ref LL_RCC_PLLQ_DIV_4
Kojto	122:f9eeca106725	3070	* @arg @ref LL_RCC_PLLQ_DIV_6
Kojto	122:f9eeca106725	3071	* @arg @ref LL_RCC_PLLQ_DIV_8
Kojto	122:f9eeca106725	3072	*/
Kojto	122:f9eeca106725	3073	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
Kojto	122:f9eeca106725	3074	{
Kojto	122:f9eeca106725	3075	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
Kojto	122:f9eeca106725	3076	}
Kojto	122:f9eeca106725	3077
Kojto	122:f9eeca106725	3078	/**
Kojto	122:f9eeca106725	3079	* @brief Get Main PLL division factor for PLLR
Kojto	122:f9eeca106725	3080	* @note used for PLLCLK (system clock)
Kojto	122:f9eeca106725	3081	* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
Kojto	122:f9eeca106725	3082	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3083	* @arg @ref LL_RCC_PLLR_DIV_2
Kojto	122:f9eeca106725	3084	* @arg @ref LL_RCC_PLLR_DIV_4
Kojto	122:f9eeca106725	3085	* @arg @ref LL_RCC_PLLR_DIV_6
Kojto	122:f9eeca106725	3086	* @arg @ref LL_RCC_PLLR_DIV_8
Kojto	122:f9eeca106725	3087	*/
Kojto	122:f9eeca106725	3088	__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
Kojto	122:f9eeca106725	3089	{
Kojto	122:f9eeca106725	3090	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
Kojto	122:f9eeca106725	3091	}
Kojto	122:f9eeca106725	3092
Kojto	122:f9eeca106725	3093	/**
Kojto	122:f9eeca106725	3094	* @brief Get the oscillator used as PLL clock source.
Kojto	122:f9eeca106725	3095	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
Kojto	122:f9eeca106725	3096	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3097	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3098	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3099	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3100	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3101	*/
Kojto	122:f9eeca106725	3102	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
Kojto	122:f9eeca106725	3103	{
Kojto	122:f9eeca106725	3104	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
Kojto	122:f9eeca106725	3105	}
Kojto	122:f9eeca106725	3106
Kojto	122:f9eeca106725	3107	/**
Kojto	122:f9eeca106725	3108	* @brief Get Division factor for the main PLL and other PLL
Kojto	122:f9eeca106725	3109	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
Kojto	122:f9eeca106725	3110	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3111	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3112	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3113	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3114	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3115	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3116	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3117	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3118	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3119	*/
Kojto	122:f9eeca106725	3120	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
Kojto	122:f9eeca106725	3121	{
Kojto	122:f9eeca106725	3122	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
Kojto	122:f9eeca106725	3123	}
Kojto	122:f9eeca106725	3124
Kojto	122:f9eeca106725	3125	/**
Kojto	122:f9eeca106725	3126	* @brief Enable PLL output mapped on SAI domain clock
Kojto	122:f9eeca106725	3127	* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
Kojto	122:f9eeca106725	3128	* @retval None
Kojto	122:f9eeca106725	3129	*/
Kojto	122:f9eeca106725	3130	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
Kojto	122:f9eeca106725	3131	{
Kojto	122:f9eeca106725	3132	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
Kojto	122:f9eeca106725	3133	}
Kojto	122:f9eeca106725	3134
Kojto	122:f9eeca106725	3135	/**
Kojto	122:f9eeca106725	3136	* @brief Disable PLL output mapped on SAI domain clock
Kojto	122:f9eeca106725	3137	* @note Cannot be disabled if the PLL clock is used as the system
Kojto	122:f9eeca106725	3138	* clock
Kojto	122:f9eeca106725	3139	* @note In order to save power, when the PLLCLK of the PLL is
Kojto	122:f9eeca106725	3140	* not used, should be 0
Kojto	122:f9eeca106725	3141	* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
Kojto	122:f9eeca106725	3142	* @retval None
Kojto	122:f9eeca106725	3143	*/
Kojto	122:f9eeca106725	3144	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
Kojto	122:f9eeca106725	3145	{
Kojto	122:f9eeca106725	3146	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
Kojto	122:f9eeca106725	3147	}
Kojto	122:f9eeca106725	3148
Kojto	122:f9eeca106725	3149	/**
Kojto	122:f9eeca106725	3150	* @brief Enable PLL output mapped on 48MHz domain clock
Kojto	122:f9eeca106725	3151	* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
Kojto	122:f9eeca106725	3152	* @retval None
Kojto	122:f9eeca106725	3153	*/
Kojto	122:f9eeca106725	3154	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
Kojto	122:f9eeca106725	3155	{
Kojto	122:f9eeca106725	3156	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
Kojto	122:f9eeca106725	3157	}
Kojto	122:f9eeca106725	3158
Kojto	122:f9eeca106725	3159	/**
Kojto	122:f9eeca106725	3160	* @brief Disable PLL output mapped on 48MHz domain clock
Kojto	122:f9eeca106725	3161	* @note Cannot be disabled if the PLL clock is used as the system
Kojto	122:f9eeca106725	3162	* clock
Kojto	122:f9eeca106725	3163	* @note In order to save power, when the PLLCLK of the PLL is
Kojto	122:f9eeca106725	3164	* not used, should be 0
Kojto	122:f9eeca106725	3165	* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
Kojto	122:f9eeca106725	3166	* @retval None
Kojto	122:f9eeca106725	3167	*/
Kojto	122:f9eeca106725	3168	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
Kojto	122:f9eeca106725	3169	{
Kojto	122:f9eeca106725	3170	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
Kojto	122:f9eeca106725	3171	}
Kojto	122:f9eeca106725	3172
Kojto	122:f9eeca106725	3173	/**
Kojto	122:f9eeca106725	3174	* @brief Enable PLL output mapped on SYSCLK domain
Kojto	122:f9eeca106725	3175	* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
Kojto	122:f9eeca106725	3176	* @retval None
Kojto	122:f9eeca106725	3177	*/
Kojto	122:f9eeca106725	3178	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
Kojto	122:f9eeca106725	3179	{
Kojto	122:f9eeca106725	3180	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
Kojto	122:f9eeca106725	3181	}
Kojto	122:f9eeca106725	3182
Kojto	122:f9eeca106725	3183	/**
Kojto	122:f9eeca106725	3184	* @brief Disable PLL output mapped on SYSCLK domain
Kojto	122:f9eeca106725	3185	* @note Cannot be disabled if the PLL clock is used as the system
Kojto	122:f9eeca106725	3186	* clock
Kojto	122:f9eeca106725	3187	* @note In order to save power, when the PLLCLK of the PLL is
Kojto	122:f9eeca106725	3188	* not used, Main PLL should be 0
Kojto	122:f9eeca106725	3189	* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
Kojto	122:f9eeca106725	3190	* @retval None
Kojto	122:f9eeca106725	3191	*/
Kojto	122:f9eeca106725	3192	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
Kojto	122:f9eeca106725	3193	{
Kojto	122:f9eeca106725	3194	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
Kojto	122:f9eeca106725	3195	}
Kojto	122:f9eeca106725	3196
Kojto	122:f9eeca106725	3197	/**
Kojto	122:f9eeca106725	3198	* @}
Kojto	122:f9eeca106725	3199	*/
Kojto	122:f9eeca106725	3200
Kojto	122:f9eeca106725	3201	/** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
Kojto	122:f9eeca106725	3202	* @{
Kojto	122:f9eeca106725	3203	*/
Kojto	122:f9eeca106725	3204
Kojto	122:f9eeca106725	3205	/**
Kojto	122:f9eeca106725	3206	* @brief Enable PLLSAI1
Kojto	122:f9eeca106725	3207	* @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
Kojto	122:f9eeca106725	3208	* @retval None
Kojto	122:f9eeca106725	3209	*/
Kojto	122:f9eeca106725	3210	__STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
Kojto	122:f9eeca106725	3211	{
Kojto	122:f9eeca106725	3212	SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
Kojto	122:f9eeca106725	3213	}
Kojto	122:f9eeca106725	3214
Kojto	122:f9eeca106725	3215	/**
Kojto	122:f9eeca106725	3216	* @brief Disable PLLSAI1
Kojto	122:f9eeca106725	3217	* @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
Kojto	122:f9eeca106725	3218	* @retval None
Kojto	122:f9eeca106725	3219	*/
Kojto	122:f9eeca106725	3220	__STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
Kojto	122:f9eeca106725	3221	{
Kojto	122:f9eeca106725	3222	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
Kojto	122:f9eeca106725	3223	}
Kojto	122:f9eeca106725	3224
Kojto	122:f9eeca106725	3225	/**
Kojto	122:f9eeca106725	3226	* @brief Check if PLLSAI1 Ready
Kojto	122:f9eeca106725	3227	* @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
Kojto	122:f9eeca106725	3228	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3229	*/
Kojto	122:f9eeca106725	3230	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
Kojto	122:f9eeca106725	3231	{
Kojto	122:f9eeca106725	3232	return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY));
Kojto	122:f9eeca106725	3233	}
Kojto	122:f9eeca106725	3234
Kojto	122:f9eeca106725	3235	/**
Kojto	122:f9eeca106725	3236	* @brief Configure PLLSAI1 used for 48Mhz domain clock
Kojto	122:f9eeca106725	3237	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	3238	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	3239	* @note PLLN/PLLQ can be written only when PLLSAI1 is disabled
Kojto	122:f9eeca106725	3240	* @note This can be selected for USB, RNG, SDMMC
Kojto	122:f9eeca106725	3241	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
Kojto	122:f9eeca106725	3242	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
Kojto	122:f9eeca106725	3243	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
Kojto	122:f9eeca106725	3244	* PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
Kojto	122:f9eeca106725	3245	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	3246	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3247	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3248	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3249	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3250	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	3251	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3252	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3253	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3254	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3255	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3256	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3257	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3258	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3259	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	3260	* @param PLLQ This parameter can be one of the following values:
Kojto	122:f9eeca106725	3261	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
Kojto	122:f9eeca106725	3262	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
Kojto	122:f9eeca106725	3263	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
Kojto	122:f9eeca106725	3264	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
Kojto	122:f9eeca106725	3265	* @retval None
Kojto	122:f9eeca106725	3266	*/
Kojto	122:f9eeca106725	3267	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Kojto	122:f9eeca106725	3268	{
Kojto	122:f9eeca106725	3269	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	145:64910690c574	3270	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLQ);
Kojto	122:f9eeca106725	3271	}
Kojto	122:f9eeca106725	3272
Kojto	122:f9eeca106725	3273	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	3274	/**
Kojto	122:f9eeca106725	3275	* @brief Configure PLLSAI1 used for SAI domain clock
Kojto	122:f9eeca106725	3276	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	3277	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	3278	* @note PLLN/PLLP can be written only when PLLSAI1 is disabled
Kojto	122:f9eeca106725	3279	* @note This can be selected for SAI1 or SAI2 (*)
Kojto	122:f9eeca106725	3280	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3281	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3282	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3283	* PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
Kojto	122:f9eeca106725	3284	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	3285	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3286	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3287	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3288	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3289	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	3290	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3291	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3292	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3293	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3294	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3295	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3296	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3297	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3298	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	3299	* @param PLLP This parameter can be one of the following values:
Kojto	122:f9eeca106725	3300	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
Kojto	122:f9eeca106725	3301	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
Kojto	122:f9eeca106725	3302	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
Kojto	122:f9eeca106725	3303	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
Kojto	122:f9eeca106725	3304	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
Kojto	122:f9eeca106725	3305	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
Kojto	122:f9eeca106725	3306	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
Kojto	122:f9eeca106725	3307	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
Kojto	122:f9eeca106725	3308	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
Kojto	122:f9eeca106725	3309	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
Kojto	122:f9eeca106725	3310	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
Kojto	122:f9eeca106725	3311	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
Kojto	122:f9eeca106725	3312	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
Kojto	122:f9eeca106725	3313	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
Kojto	122:f9eeca106725	3314	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
Kojto	122:f9eeca106725	3315	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
Kojto	122:f9eeca106725	3316	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
Kojto	122:f9eeca106725	3317	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
Kojto	122:f9eeca106725	3318	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
Kojto	122:f9eeca106725	3319	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
Kojto	122:f9eeca106725	3320	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
Kojto	122:f9eeca106725	3321	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
Kojto	122:f9eeca106725	3322	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
Kojto	122:f9eeca106725	3323	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
Kojto	122:f9eeca106725	3324	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
Kojto	122:f9eeca106725	3325	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
Kojto	122:f9eeca106725	3326	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
Kojto	122:f9eeca106725	3327	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
Kojto	122:f9eeca106725	3328	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
Kojto	122:f9eeca106725	3329	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
Kojto	122:f9eeca106725	3330	* @retval None
Kojto	122:f9eeca106725	3331	*/
Kojto	122:f9eeca106725	3332	#else
Kojto	122:f9eeca106725	3333	/**
Kojto	122:f9eeca106725	3334	* @brief Configure PLLSAI1 used for SAI domain clock
Kojto	122:f9eeca106725	3335	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	3336	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	3337	* @note PLLN/PLLP can be written only when PLLSAI1 is disabled
Kojto	122:f9eeca106725	3338	* @note This can be selected for SAI1 or SAI2 (*)
Kojto	122:f9eeca106725	3339	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3340	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3341	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3342	* PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI
Kojto	122:f9eeca106725	3343	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	3344	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3345	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3346	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3347	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3348	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	3349	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3350	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3351	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3352	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3353	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3354	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3355	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3356	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3357	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	3358	* @param PLLP This parameter can be one of the following values:
Kojto	122:f9eeca106725	3359	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
Kojto	122:f9eeca106725	3360	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
Kojto	122:f9eeca106725	3361	* @retval None
Kojto	122:f9eeca106725	3362	*/
Kojto	122:f9eeca106725	3363	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	3364	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Kojto	122:f9eeca106725	3365	{
Kojto	122:f9eeca106725	3366	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
Kojto	122:f9eeca106725	3367	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	3368	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1PDIV,
AnnaBridge	145:64910690c574	3369	PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLP);
Kojto	122:f9eeca106725	3370	#else
AnnaBridge	145:64910690c574	3371	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLP);
Kojto	122:f9eeca106725	3372	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	3373	}
Kojto	122:f9eeca106725	3374
Kojto	122:f9eeca106725	3375	/**
Kojto	122:f9eeca106725	3376	* @brief Configure PLLSAI1 used for ADC domain clock
Kojto	122:f9eeca106725	3377	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	3378	* PLLSAI1 and PLLSAI2 (*) are disabled
Kojto	122:f9eeca106725	3379	* @note PLLN/PLLR can be written only when PLLSAI1 is disabled
Kojto	122:f9eeca106725	3380	* @note This can be selected for ADC
Kojto	122:f9eeca106725	3381	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
Kojto	122:f9eeca106725	3382	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
Kojto	122:f9eeca106725	3383	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
Kojto	122:f9eeca106725	3384	* PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
Kojto	122:f9eeca106725	3385	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	3386	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3387	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3388	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3389	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3390	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	3391	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3392	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3393	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3394	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3395	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3396	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3397	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3398	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3399	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	3400	* @param PLLR This parameter can be one of the following values:
Kojto	122:f9eeca106725	3401	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
Kojto	122:f9eeca106725	3402	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
Kojto	122:f9eeca106725	3403	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
Kojto	122:f9eeca106725	3404	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
Kojto	122:f9eeca106725	3405	* @retval None
Kojto	122:f9eeca106725	3406	*/
Kojto	122:f9eeca106725	3407	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Kojto	122:f9eeca106725	3408	{
Kojto	122:f9eeca106725	3409	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	145:64910690c574	3410	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLR);
Kojto	122:f9eeca106725	3411	}
Kojto	122:f9eeca106725	3412
Kojto	122:f9eeca106725	3413	/**
Kojto	122:f9eeca106725	3414	* @brief Get SAI1PLL multiplication factor for VCO
Kojto	122:f9eeca106725	3415	* @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN
Kojto	122:f9eeca106725	3416	* @retval Between 8 and 86
Kojto	122:f9eeca106725	3417	*/
Kojto	122:f9eeca106725	3418	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
Kojto	122:f9eeca106725	3419	{
AnnaBridge	145:64910690c574	3420	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
Kojto	122:f9eeca106725	3421	}
Kojto	122:f9eeca106725	3422
Kojto	122:f9eeca106725	3423	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	3424	/**
Kojto	122:f9eeca106725	3425	* @brief Get SAI1PLL division factor for PLLSAI1P
Kojto	122:f9eeca106725	3426	* @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
Kojto	122:f9eeca106725	3427	* @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP
Kojto	122:f9eeca106725	3428	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3429	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
Kojto	122:f9eeca106725	3430	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
Kojto	122:f9eeca106725	3431	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
Kojto	122:f9eeca106725	3432	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
Kojto	122:f9eeca106725	3433	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
Kojto	122:f9eeca106725	3434	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
Kojto	122:f9eeca106725	3435	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
Kojto	122:f9eeca106725	3436	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
Kojto	122:f9eeca106725	3437	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
Kojto	122:f9eeca106725	3438	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
Kojto	122:f9eeca106725	3439	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
Kojto	122:f9eeca106725	3440	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
Kojto	122:f9eeca106725	3441	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
Kojto	122:f9eeca106725	3442	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
Kojto	122:f9eeca106725	3443	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
Kojto	122:f9eeca106725	3444	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
Kojto	122:f9eeca106725	3445	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
Kojto	122:f9eeca106725	3446	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
Kojto	122:f9eeca106725	3447	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
Kojto	122:f9eeca106725	3448	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
Kojto	122:f9eeca106725	3449	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
Kojto	122:f9eeca106725	3450	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
Kojto	122:f9eeca106725	3451	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
Kojto	122:f9eeca106725	3452	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
Kojto	122:f9eeca106725	3453	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
Kojto	122:f9eeca106725	3454	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
Kojto	122:f9eeca106725	3455	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
Kojto	122:f9eeca106725	3456	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
Kojto	122:f9eeca106725	3457	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
Kojto	122:f9eeca106725	3458	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
Kojto	122:f9eeca106725	3459	*/
Kojto	122:f9eeca106725	3460	#else
Kojto	122:f9eeca106725	3461	/**
Kojto	122:f9eeca106725	3462	* @brief Get SAI1PLL division factor for PLLSAI1P
Kojto	122:f9eeca106725	3463	* @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
Kojto	122:f9eeca106725	3464	* @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP
Kojto	122:f9eeca106725	3465	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3466	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
Kojto	122:f9eeca106725	3467	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
Kojto	122:f9eeca106725	3468	*/
Kojto	122:f9eeca106725	3469	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	3470	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
Kojto	122:f9eeca106725	3471	{
Kojto	122:f9eeca106725	3472	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto	122:f9eeca106725	3473	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
Kojto	122:f9eeca106725	3474	#else
Kojto	122:f9eeca106725	3475	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
Kojto	122:f9eeca106725	3476	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto	122:f9eeca106725	3477	}
Kojto	122:f9eeca106725	3478
Kojto	122:f9eeca106725	3479	/**
Kojto	122:f9eeca106725	3480	* @brief Get SAI1PLL division factor for PLLSAI1Q
Kojto	122:f9eeca106725	3481	* @note used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
Kojto	122:f9eeca106725	3482	* @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
Kojto	122:f9eeca106725	3483	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3484	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
Kojto	122:f9eeca106725	3485	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
Kojto	122:f9eeca106725	3486	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
Kojto	122:f9eeca106725	3487	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
Kojto	122:f9eeca106725	3488	*/
Kojto	122:f9eeca106725	3489	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
Kojto	122:f9eeca106725	3490	{
Kojto	122:f9eeca106725	3491	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
Kojto	122:f9eeca106725	3492	}
Kojto	122:f9eeca106725	3493
Kojto	122:f9eeca106725	3494	/**
Kojto	122:f9eeca106725	3495	* @brief Get PLLSAI1 division factor for PLLSAIR
Kojto	122:f9eeca106725	3496	* @note used for PLLADC1CLK (ADC clock)
Kojto	122:f9eeca106725	3497	* @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
Kojto	122:f9eeca106725	3498	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3499	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
Kojto	122:f9eeca106725	3500	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
Kojto	122:f9eeca106725	3501	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
Kojto	122:f9eeca106725	3502	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
Kojto	122:f9eeca106725	3503	*/
Kojto	122:f9eeca106725	3504	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
Kojto	122:f9eeca106725	3505	{
Kojto	122:f9eeca106725	3506	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
Kojto	122:f9eeca106725	3507	}
Kojto	122:f9eeca106725	3508
Kojto	122:f9eeca106725	3509	/**
Kojto	122:f9eeca106725	3510	* @brief Enable PLLSAI1 output mapped on SAI domain clock
Kojto	122:f9eeca106725	3511	* @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI
Kojto	122:f9eeca106725	3512	* @retval None
Kojto	122:f9eeca106725	3513	*/
Kojto	122:f9eeca106725	3514	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
Kojto	122:f9eeca106725	3515	{
Kojto	122:f9eeca106725	3516	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
Kojto	122:f9eeca106725	3517	}
Kojto	122:f9eeca106725	3518
Kojto	122:f9eeca106725	3519	/**
Kojto	122:f9eeca106725	3520	* @brief Disable PLLSAI1 output mapped on SAI domain clock
Kojto	122:f9eeca106725	3521	* @note In order to save power, when of the PLLSAI1 is
Kojto	122:f9eeca106725	3522	* not used, should be 0
Kojto	122:f9eeca106725	3523	* @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI
Kojto	122:f9eeca106725	3524	* @retval None
Kojto	122:f9eeca106725	3525	*/
Kojto	122:f9eeca106725	3526	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
Kojto	122:f9eeca106725	3527	{
Kojto	122:f9eeca106725	3528	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
Kojto	122:f9eeca106725	3529	}
Kojto	122:f9eeca106725	3530
Kojto	122:f9eeca106725	3531	/**
Kojto	122:f9eeca106725	3532	* @brief Enable PLLSAI1 output mapped on 48MHz domain clock
Kojto	122:f9eeca106725	3533	* @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M
Kojto	122:f9eeca106725	3534	* @retval None
Kojto	122:f9eeca106725	3535	*/
Kojto	122:f9eeca106725	3536	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
Kojto	122:f9eeca106725	3537	{
Kojto	122:f9eeca106725	3538	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
Kojto	122:f9eeca106725	3539	}
Kojto	122:f9eeca106725	3540
Kojto	122:f9eeca106725	3541	/**
Kojto	122:f9eeca106725	3542	* @brief Disable PLLSAI1 output mapped on 48MHz domain clock
Kojto	122:f9eeca106725	3543	* @note In order to save power, when of the PLLSAI1 is
Kojto	122:f9eeca106725	3544	* not used, should be 0
Kojto	122:f9eeca106725	3545	* @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M
Kojto	122:f9eeca106725	3546	* @retval None
Kojto	122:f9eeca106725	3547	*/
Kojto	122:f9eeca106725	3548	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
Kojto	122:f9eeca106725	3549	{
Kojto	122:f9eeca106725	3550	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
Kojto	122:f9eeca106725	3551	}
Kojto	122:f9eeca106725	3552
Kojto	122:f9eeca106725	3553	/**
Kojto	122:f9eeca106725	3554	* @brief Enable PLLSAI1 output mapped on ADC domain clock
Kojto	122:f9eeca106725	3555	* @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC
Kojto	122:f9eeca106725	3556	* @retval None
Kojto	122:f9eeca106725	3557	*/
Kojto	122:f9eeca106725	3558	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
Kojto	122:f9eeca106725	3559	{
Kojto	122:f9eeca106725	3560	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
Kojto	122:f9eeca106725	3561	}
Kojto	122:f9eeca106725	3562
Kojto	122:f9eeca106725	3563	/**
Kojto	122:f9eeca106725	3564	* @brief Disable PLLSAI1 output mapped on ADC domain clock
Kojto	122:f9eeca106725	3565	* @note In order to save power, when of the PLLSAI1 is
Kojto	122:f9eeca106725	3566	* not used, Main PLLSAI1 should be 0
Kojto	122:f9eeca106725	3567	* @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC
Kojto	122:f9eeca106725	3568	* @retval None
Kojto	122:f9eeca106725	3569	*/
Kojto	122:f9eeca106725	3570	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
Kojto	122:f9eeca106725	3571	{
Kojto	122:f9eeca106725	3572	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
Kojto	122:f9eeca106725	3573	}
Kojto	122:f9eeca106725	3574
Kojto	122:f9eeca106725	3575	/**
Kojto	122:f9eeca106725	3576	* @}
Kojto	122:f9eeca106725	3577	*/
Kojto	122:f9eeca106725	3578
Kojto	122:f9eeca106725	3579	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	3580	/** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
Kojto	122:f9eeca106725	3581	* @{
Kojto	122:f9eeca106725	3582	*/
Kojto	122:f9eeca106725	3583
Kojto	122:f9eeca106725	3584	/**
Kojto	122:f9eeca106725	3585	* @brief Enable PLLSAI2
Kojto	122:f9eeca106725	3586	* @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable
Kojto	122:f9eeca106725	3587	* @retval None
Kojto	122:f9eeca106725	3588	*/
Kojto	122:f9eeca106725	3589	__STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
Kojto	122:f9eeca106725	3590	{
Kojto	122:f9eeca106725	3591	SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
Kojto	122:f9eeca106725	3592	}
Kojto	122:f9eeca106725	3593
Kojto	122:f9eeca106725	3594	/**
Kojto	122:f9eeca106725	3595	* @brief Disable PLLSAI2
Kojto	122:f9eeca106725	3596	* @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable
Kojto	122:f9eeca106725	3597	* @retval None
Kojto	122:f9eeca106725	3598	*/
Kojto	122:f9eeca106725	3599	__STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
Kojto	122:f9eeca106725	3600	{
Kojto	122:f9eeca106725	3601	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
Kojto	122:f9eeca106725	3602	}
Kojto	122:f9eeca106725	3603
Kojto	122:f9eeca106725	3604	/**
Kojto	122:f9eeca106725	3605	* @brief Check if PLLSAI2 Ready
Kojto	122:f9eeca106725	3606	* @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady
Kojto	122:f9eeca106725	3607	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3608	*/
Kojto	122:f9eeca106725	3609	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
Kojto	122:f9eeca106725	3610	{
Kojto	122:f9eeca106725	3611	return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY));
Kojto	122:f9eeca106725	3612	}
Kojto	122:f9eeca106725	3613
Kojto	122:f9eeca106725	3614	/**
Kojto	122:f9eeca106725	3615	* @brief Configure PLLSAI2 used for SAI domain clock
Kojto	122:f9eeca106725	3616	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	3617	* PLLSAI2 and PLLSAI2 are disabled
Kojto	122:f9eeca106725	3618	* @note PLLN/PLLP can be written only when PLLSAI2 is disabled
Kojto	122:f9eeca106725	3619	* @note This can be selected for SAI1 or SAI2
Kojto	122:f9eeca106725	3620	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3621	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3622	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
Kojto	122:f9eeca106725	3623	* PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI
Kojto	122:f9eeca106725	3624	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	3625	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3626	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3627	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3628	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3629	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	3630	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3631	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3632	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3633	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3634	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3635	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3636	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3637	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3638	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	3639	* @param PLLP This parameter can be one of the following values:
Kojto	122:f9eeca106725	3640	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
Kojto	122:f9eeca106725	3641	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
Kojto	122:f9eeca106725	3642	* @retval None
Kojto	122:f9eeca106725	3643	*/
Kojto	122:f9eeca106725	3644	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Kojto	122:f9eeca106725	3645	{
Kojto	122:f9eeca106725	3646	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	145:64910690c574	3647	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLP);
Kojto	122:f9eeca106725	3648	}
Kojto	122:f9eeca106725	3649
Kojto	122:f9eeca106725	3650	/**
Kojto	122:f9eeca106725	3651	* @brief Configure PLLSAI2 used for ADC domain clock
Kojto	122:f9eeca106725	3652	* @note PLL Source and PLLM Divider can be written only when PLL,
Kojto	122:f9eeca106725	3653	* PLLSAI2 and PLLSAI2 are disabled
Kojto	122:f9eeca106725	3654	* @note PLLN/PLLR can be written only when PLLSAI2 is disabled
Kojto	122:f9eeca106725	3655	* @note This can be selected for ADC
Kojto	122:f9eeca106725	3656	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n
Kojto	122:f9eeca106725	3657	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n
Kojto	122:f9eeca106725	3658	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n
Kojto	122:f9eeca106725	3659	* PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC
Kojto	122:f9eeca106725	3660	* @param Source This parameter can be one of the following values:
Kojto	122:f9eeca106725	3661	* @arg @ref LL_RCC_PLLSOURCE_NONE
Kojto	122:f9eeca106725	3662	* @arg @ref LL_RCC_PLLSOURCE_MSI
Kojto	122:f9eeca106725	3663	* @arg @ref LL_RCC_PLLSOURCE_HSI
Kojto	122:f9eeca106725	3664	* @arg @ref LL_RCC_PLLSOURCE_HSE
Kojto	122:f9eeca106725	3665	* @param PLLM This parameter can be one of the following values:
Kojto	122:f9eeca106725	3666	* @arg @ref LL_RCC_PLLM_DIV_1
Kojto	122:f9eeca106725	3667	* @arg @ref LL_RCC_PLLM_DIV_2
Kojto	122:f9eeca106725	3668	* @arg @ref LL_RCC_PLLM_DIV_3
Kojto	122:f9eeca106725	3669	* @arg @ref LL_RCC_PLLM_DIV_4
Kojto	122:f9eeca106725	3670	* @arg @ref LL_RCC_PLLM_DIV_5
Kojto	122:f9eeca106725	3671	* @arg @ref LL_RCC_PLLM_DIV_6
Kojto	122:f9eeca106725	3672	* @arg @ref LL_RCC_PLLM_DIV_7
Kojto	122:f9eeca106725	3673	* @arg @ref LL_RCC_PLLM_DIV_8
Kojto	122:f9eeca106725	3674	* @param PLLN Between 8 and 86
Kojto	122:f9eeca106725	3675	* @param PLLR This parameter can be one of the following values:
Kojto	122:f9eeca106725	3676	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
Kojto	122:f9eeca106725	3677	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
Kojto	122:f9eeca106725	3678	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
Kojto	122:f9eeca106725	3679	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
Kojto	122:f9eeca106725	3680	* @retval None
Kojto	122:f9eeca106725	3681	*/
Kojto	122:f9eeca106725	3682	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Kojto	122:f9eeca106725	3683	{
Kojto	122:f9eeca106725	3684	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	145:64910690c574	3685	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLR);
Kojto	122:f9eeca106725	3686	}
Kojto	122:f9eeca106725	3687
Kojto	122:f9eeca106725	3688	/**
Kojto	122:f9eeca106725	3689	* @brief Get SAI2PLL multiplication factor for VCO
Kojto	122:f9eeca106725	3690	* @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN
Kojto	122:f9eeca106725	3691	* @retval Between 8 and 86
Kojto	122:f9eeca106725	3692	*/
Kojto	122:f9eeca106725	3693	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
Kojto	122:f9eeca106725	3694	{
AnnaBridge	145:64910690c574	3695	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
Kojto	122:f9eeca106725	3696	}
Kojto	122:f9eeca106725	3697
Kojto	122:f9eeca106725	3698	/**
Kojto	122:f9eeca106725	3699	* @brief Get SAI2PLL division factor for PLLSAI2P
Kojto	122:f9eeca106725	3700	* @note used for PLLSAI2CLK (SAI1 or SAI2 clock).
Kojto	122:f9eeca106725	3701	* @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP
Kojto	122:f9eeca106725	3702	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3703	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
Kojto	122:f9eeca106725	3704	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
Kojto	122:f9eeca106725	3705	*/
Kojto	122:f9eeca106725	3706	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
Kojto	122:f9eeca106725	3707	{
Kojto	122:f9eeca106725	3708	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
Kojto	122:f9eeca106725	3709	}
Kojto	122:f9eeca106725	3710
Kojto	122:f9eeca106725	3711	/**
Kojto	122:f9eeca106725	3712	* @brief Get SAI2PLL division factor for PLLSAI2R
Kojto	122:f9eeca106725	3713	* @note used for PLLADC2CLK (ADC clock)
Kojto	122:f9eeca106725	3714	* @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR
Kojto	122:f9eeca106725	3715	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	3716	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
Kojto	122:f9eeca106725	3717	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
Kojto	122:f9eeca106725	3718	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
Kojto	122:f9eeca106725	3719	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
Kojto	122:f9eeca106725	3720	*/
Kojto	122:f9eeca106725	3721	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
Kojto	122:f9eeca106725	3722	{
Kojto	122:f9eeca106725	3723	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
Kojto	122:f9eeca106725	3724	}
Kojto	122:f9eeca106725	3725
Kojto	122:f9eeca106725	3726	/**
Kojto	122:f9eeca106725	3727	* @brief Enable PLLSAI2 output mapped on SAI domain clock
Kojto	122:f9eeca106725	3728	* @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI
Kojto	122:f9eeca106725	3729	* @retval None
Kojto	122:f9eeca106725	3730	*/
Kojto	122:f9eeca106725	3731	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
Kojto	122:f9eeca106725	3732	{
Kojto	122:f9eeca106725	3733	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
Kojto	122:f9eeca106725	3734	}
Kojto	122:f9eeca106725	3735
Kojto	122:f9eeca106725	3736	/**
Kojto	122:f9eeca106725	3737	* @brief Disable PLLSAI2 output mapped on SAI domain clock
Kojto	122:f9eeca106725	3738	* @note In order to save power, when of the PLLSAI2 is
Kojto	122:f9eeca106725	3739	* not used, should be 0
Kojto	122:f9eeca106725	3740	* @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI
Kojto	122:f9eeca106725	3741	* @retval None
Kojto	122:f9eeca106725	3742	*/
Kojto	122:f9eeca106725	3743	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
Kojto	122:f9eeca106725	3744	{
Kojto	122:f9eeca106725	3745	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
Kojto	122:f9eeca106725	3746	}
Kojto	122:f9eeca106725	3747
Kojto	122:f9eeca106725	3748	/**
Kojto	122:f9eeca106725	3749	* @brief Enable PLLSAI2 output mapped on ADC domain clock
Kojto	122:f9eeca106725	3750	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC
Kojto	122:f9eeca106725	3751	* @retval None
Kojto	122:f9eeca106725	3752	*/
Kojto	122:f9eeca106725	3753	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
Kojto	122:f9eeca106725	3754	{
Kojto	122:f9eeca106725	3755	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
Kojto	122:f9eeca106725	3756	}
Kojto	122:f9eeca106725	3757
Kojto	122:f9eeca106725	3758	/**
Kojto	122:f9eeca106725	3759	* @brief Disable PLLSAI2 output mapped on ADC domain clock
Kojto	122:f9eeca106725	3760	* @note In order to save power, when of the PLLSAI2 is
Kojto	122:f9eeca106725	3761	* not used, Main PLLSAI2 should be 0
Kojto	122:f9eeca106725	3762	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC
Kojto	122:f9eeca106725	3763	* @retval None
Kojto	122:f9eeca106725	3764	*/
Kojto	122:f9eeca106725	3765	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
Kojto	122:f9eeca106725	3766	{
Kojto	122:f9eeca106725	3767	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
Kojto	122:f9eeca106725	3768	}
Kojto	122:f9eeca106725	3769
Kojto	122:f9eeca106725	3770	/**
Kojto	122:f9eeca106725	3771	* @}
Kojto	122:f9eeca106725	3772	*/
Kojto	122:f9eeca106725	3773	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	145:64910690c574	3774
Kojto	122:f9eeca106725	3775	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
Kojto	122:f9eeca106725	3776	* @{
Kojto	122:f9eeca106725	3777	*/
Kojto	122:f9eeca106725	3778
Kojto	122:f9eeca106725	3779	/**
Kojto	122:f9eeca106725	3780	* @brief Clear LSI ready interrupt flag
Kojto	122:f9eeca106725	3781	* @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
Kojto	122:f9eeca106725	3782	* @retval None
Kojto	122:f9eeca106725	3783	*/
Kojto	122:f9eeca106725	3784	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
Kojto	122:f9eeca106725	3785	{
Kojto	122:f9eeca106725	3786	SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
Kojto	122:f9eeca106725	3787	}
Kojto	122:f9eeca106725	3788
Kojto	122:f9eeca106725	3789	/**
Kojto	122:f9eeca106725	3790	* @brief Clear LSE ready interrupt flag
Kojto	122:f9eeca106725	3791	* @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
Kojto	122:f9eeca106725	3792	* @retval None
Kojto	122:f9eeca106725	3793	*/
Kojto	122:f9eeca106725	3794	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
Kojto	122:f9eeca106725	3795	{
Kojto	122:f9eeca106725	3796	SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
Kojto	122:f9eeca106725	3797	}
Kojto	122:f9eeca106725	3798
Kojto	122:f9eeca106725	3799	/**
Kojto	122:f9eeca106725	3800	* @brief Clear MSI ready interrupt flag
Kojto	122:f9eeca106725	3801	* @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
Kojto	122:f9eeca106725	3802	* @retval None
Kojto	122:f9eeca106725	3803	*/
Kojto	122:f9eeca106725	3804	__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
Kojto	122:f9eeca106725	3805	{
Kojto	122:f9eeca106725	3806	SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
Kojto	122:f9eeca106725	3807	}
Kojto	122:f9eeca106725	3808
Kojto	122:f9eeca106725	3809	/**
Kojto	122:f9eeca106725	3810	* @brief Clear HSI ready interrupt flag
Kojto	122:f9eeca106725	3811	* @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
Kojto	122:f9eeca106725	3812	* @retval None
Kojto	122:f9eeca106725	3813	*/
Kojto	122:f9eeca106725	3814	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
Kojto	122:f9eeca106725	3815	{
Kojto	122:f9eeca106725	3816	SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
Kojto	122:f9eeca106725	3817	}
Kojto	122:f9eeca106725	3818
Kojto	122:f9eeca106725	3819	/**
Kojto	122:f9eeca106725	3820	* @brief Clear HSE ready interrupt flag
Kojto	122:f9eeca106725	3821	* @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
Kojto	122:f9eeca106725	3822	* @retval None
Kojto	122:f9eeca106725	3823	*/
Kojto	122:f9eeca106725	3824	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
Kojto	122:f9eeca106725	3825	{
Kojto	122:f9eeca106725	3826	SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
Kojto	122:f9eeca106725	3827	}
Kojto	122:f9eeca106725	3828
Kojto	122:f9eeca106725	3829	/**
Kojto	122:f9eeca106725	3830	* @brief Clear PLL ready interrupt flag
Kojto	122:f9eeca106725	3831	* @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
Kojto	122:f9eeca106725	3832	* @retval None
Kojto	122:f9eeca106725	3833	*/
Kojto	122:f9eeca106725	3834	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
Kojto	122:f9eeca106725	3835	{
Kojto	122:f9eeca106725	3836	SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
Kojto	122:f9eeca106725	3837	}
Kojto	122:f9eeca106725	3838
Kojto	122:f9eeca106725	3839	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	3840	/**
Kojto	122:f9eeca106725	3841	* @brief Clear HSI48 ready interrupt flag
Kojto	122:f9eeca106725	3842	* @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
Kojto	122:f9eeca106725	3843	* @retval None
Kojto	122:f9eeca106725	3844	*/
Kojto	122:f9eeca106725	3845	__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
Kojto	122:f9eeca106725	3846	{
Kojto	122:f9eeca106725	3847	SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
Kojto	122:f9eeca106725	3848	}
Kojto	122:f9eeca106725	3849	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	3850
Kojto	122:f9eeca106725	3851	/**
Kojto	122:f9eeca106725	3852	* @brief Clear PLLSAI1 ready interrupt flag
Kojto	122:f9eeca106725	3853	* @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
Kojto	122:f9eeca106725	3854	* @retval None
Kojto	122:f9eeca106725	3855	*/
Kojto	122:f9eeca106725	3856	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
Kojto	122:f9eeca106725	3857	{
Kojto	122:f9eeca106725	3858	SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
Kojto	122:f9eeca106725	3859	}
Kojto	122:f9eeca106725	3860
Kojto	122:f9eeca106725	3861	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	3862	/**
Kojto	122:f9eeca106725	3863	* @brief Clear PLLSAI1 ready interrupt flag
Kojto	122:f9eeca106725	3864	* @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY
Kojto	122:f9eeca106725	3865	* @retval None
Kojto	122:f9eeca106725	3866	*/
Kojto	122:f9eeca106725	3867	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
Kojto	122:f9eeca106725	3868	{
Kojto	122:f9eeca106725	3869	SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
Kojto	122:f9eeca106725	3870	}
Kojto	122:f9eeca106725	3871	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	145:64910690c574	3872
Kojto	122:f9eeca106725	3873	/**
Kojto	122:f9eeca106725	3874	* @brief Clear Clock security system interrupt flag
Kojto	122:f9eeca106725	3875	* @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
Kojto	122:f9eeca106725	3876	* @retval None
Kojto	122:f9eeca106725	3877	*/
Kojto	122:f9eeca106725	3878	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
Kojto	122:f9eeca106725	3879	{
Kojto	122:f9eeca106725	3880	SET_BIT(RCC->CICR, RCC_CICR_CSSC);
Kojto	122:f9eeca106725	3881	}
Kojto	122:f9eeca106725	3882
Kojto	122:f9eeca106725	3883	/**
Kojto	122:f9eeca106725	3884	* @brief Clear LSE Clock security system interrupt flag
Kojto	122:f9eeca106725	3885	* @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
Kojto	122:f9eeca106725	3886	* @retval None
Kojto	122:f9eeca106725	3887	*/
Kojto	122:f9eeca106725	3888	__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
Kojto	122:f9eeca106725	3889	{
Kojto	122:f9eeca106725	3890	SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
Kojto	122:f9eeca106725	3891	}
Kojto	122:f9eeca106725	3892
Kojto	122:f9eeca106725	3893	/**
Kojto	122:f9eeca106725	3894	* @brief Check if LSI ready interrupt occurred or not
Kojto	122:f9eeca106725	3895	* @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
Kojto	122:f9eeca106725	3896	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3897	*/
Kojto	122:f9eeca106725	3898	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
Kojto	122:f9eeca106725	3899	{
Kojto	122:f9eeca106725	3900	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF));
Kojto	122:f9eeca106725	3901	}
Kojto	122:f9eeca106725	3902
Kojto	122:f9eeca106725	3903	/**
Kojto	122:f9eeca106725	3904	* @brief Check if LSE ready interrupt occurred or not
Kojto	122:f9eeca106725	3905	* @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
Kojto	122:f9eeca106725	3906	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3907	*/
Kojto	122:f9eeca106725	3908	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
Kojto	122:f9eeca106725	3909	{
Kojto	122:f9eeca106725	3910	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF));
Kojto	122:f9eeca106725	3911	}
Kojto	122:f9eeca106725	3912
Kojto	122:f9eeca106725	3913	/**
Kojto	122:f9eeca106725	3914	* @brief Check if MSI ready interrupt occurred or not
Kojto	122:f9eeca106725	3915	* @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
Kojto	122:f9eeca106725	3916	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3917	*/
Kojto	122:f9eeca106725	3918	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
Kojto	122:f9eeca106725	3919	{
Kojto	122:f9eeca106725	3920	return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF));
Kojto	122:f9eeca106725	3921	}
Kojto	122:f9eeca106725	3922
Kojto	122:f9eeca106725	3923	/**
Kojto	122:f9eeca106725	3924	* @brief Check if HSI ready interrupt occurred or not
Kojto	122:f9eeca106725	3925	* @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
Kojto	122:f9eeca106725	3926	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3927	*/
Kojto	122:f9eeca106725	3928	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
Kojto	122:f9eeca106725	3929	{
Kojto	122:f9eeca106725	3930	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF));
Kojto	122:f9eeca106725	3931	}
Kojto	122:f9eeca106725	3932
Kojto	122:f9eeca106725	3933	/**
Kojto	122:f9eeca106725	3934	* @brief Check if HSE ready interrupt occurred or not
Kojto	122:f9eeca106725	3935	* @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
Kojto	122:f9eeca106725	3936	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3937	*/
Kojto	122:f9eeca106725	3938	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
Kojto	122:f9eeca106725	3939	{
Kojto	122:f9eeca106725	3940	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF));
Kojto	122:f9eeca106725	3941	}
Kojto	122:f9eeca106725	3942
Kojto	122:f9eeca106725	3943	/**
Kojto	122:f9eeca106725	3944	* @brief Check if PLL ready interrupt occurred or not
Kojto	122:f9eeca106725	3945	* @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
Kojto	122:f9eeca106725	3946	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3947	*/
Kojto	122:f9eeca106725	3948	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
Kojto	122:f9eeca106725	3949	{
Kojto	122:f9eeca106725	3950	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF));
Kojto	122:f9eeca106725	3951	}
Kojto	122:f9eeca106725	3952
Kojto	122:f9eeca106725	3953	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	3954	/**
Kojto	122:f9eeca106725	3955	* @brief Check if HSI48 ready interrupt occurred or not
Kojto	122:f9eeca106725	3956	* @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
Kojto	122:f9eeca106725	3957	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3958	*/
Kojto	122:f9eeca106725	3959	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
Kojto	122:f9eeca106725	3960	{
Kojto	122:f9eeca106725	3961	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF));
Kojto	122:f9eeca106725	3962	}
Kojto	122:f9eeca106725	3963	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	3964
Kojto	122:f9eeca106725	3965	/**
Kojto	122:f9eeca106725	3966	* @brief Check if PLLSAI1 ready interrupt occurred or not
Kojto	122:f9eeca106725	3967	* @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
Kojto	122:f9eeca106725	3968	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3969	*/
Kojto	122:f9eeca106725	3970	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
Kojto	122:f9eeca106725	3971	{
Kojto	122:f9eeca106725	3972	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF));
Kojto	122:f9eeca106725	3973	}
Kojto	122:f9eeca106725	3974
Kojto	122:f9eeca106725	3975	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	3976	/**
Kojto	122:f9eeca106725	3977	* @brief Check if PLLSAI1 ready interrupt occurred or not
Kojto	122:f9eeca106725	3978	* @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY
Kojto	122:f9eeca106725	3979	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3980	*/
Kojto	122:f9eeca106725	3981	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
Kojto	122:f9eeca106725	3982	{
Kojto	122:f9eeca106725	3983	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF));
Kojto	122:f9eeca106725	3984	}
Kojto	122:f9eeca106725	3985	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	145:64910690c574	3986
Kojto	122:f9eeca106725	3987	/**
Kojto	122:f9eeca106725	3988	* @brief Check if Clock security system interrupt occurred or not
Kojto	122:f9eeca106725	3989	* @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
Kojto	122:f9eeca106725	3990	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	3991	*/
Kojto	122:f9eeca106725	3992	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
Kojto	122:f9eeca106725	3993	{
Kojto	122:f9eeca106725	3994	return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF));
Kojto	122:f9eeca106725	3995	}
Kojto	122:f9eeca106725	3996
Kojto	122:f9eeca106725	3997	/**
Kojto	122:f9eeca106725	3998	* @brief Check if LSE Clock security system interrupt occurred or not
Kojto	122:f9eeca106725	3999	* @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
Kojto	122:f9eeca106725	4000	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4001	*/
Kojto	122:f9eeca106725	4002	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
Kojto	122:f9eeca106725	4003	{
Kojto	122:f9eeca106725	4004	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF));
Kojto	122:f9eeca106725	4005	}
Kojto	122:f9eeca106725	4006
Kojto	122:f9eeca106725	4007	/**
Kojto	122:f9eeca106725	4008	* @brief Check if RCC flag FW reset is set or not.
Kojto	122:f9eeca106725	4009	* @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST
Kojto	122:f9eeca106725	4010	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4011	*/
Kojto	122:f9eeca106725	4012	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
Kojto	122:f9eeca106725	4013	{
Kojto	122:f9eeca106725	4014	return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF));
Kojto	122:f9eeca106725	4015	}
Kojto	122:f9eeca106725	4016
Kojto	122:f9eeca106725	4017	/**
Kojto	122:f9eeca106725	4018	* @brief Check if RCC flag Independent Watchdog reset is set or not.
Kojto	122:f9eeca106725	4019	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
Kojto	122:f9eeca106725	4020	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4021	*/
Kojto	122:f9eeca106725	4022	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
Kojto	122:f9eeca106725	4023	{
Kojto	122:f9eeca106725	4024	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
Kojto	122:f9eeca106725	4025	}
Kojto	122:f9eeca106725	4026
Kojto	122:f9eeca106725	4027	/**
Kojto	122:f9eeca106725	4028	* @brief Check if RCC flag Low Power reset is set or not.
Kojto	122:f9eeca106725	4029	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
Kojto	122:f9eeca106725	4030	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4031	*/
Kojto	122:f9eeca106725	4032	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
Kojto	122:f9eeca106725	4033	{
Kojto	122:f9eeca106725	4034	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
Kojto	122:f9eeca106725	4035	}
Kojto	122:f9eeca106725	4036
Kojto	122:f9eeca106725	4037	/**
Kojto	122:f9eeca106725	4038	* @brief Check if RCC flag is set or not.
Kojto	122:f9eeca106725	4039	* @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
Kojto	122:f9eeca106725	4040	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4041	*/
Kojto	122:f9eeca106725	4042	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
Kojto	122:f9eeca106725	4043	{
Kojto	122:f9eeca106725	4044	return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
Kojto	122:f9eeca106725	4045	}
Kojto	122:f9eeca106725	4046
Kojto	122:f9eeca106725	4047	/**
Kojto	122:f9eeca106725	4048	* @brief Check if RCC flag Pin reset is set or not.
Kojto	122:f9eeca106725	4049	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
Kojto	122:f9eeca106725	4050	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4051	*/
Kojto	122:f9eeca106725	4052	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
Kojto	122:f9eeca106725	4053	{
Kojto	122:f9eeca106725	4054	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
Kojto	122:f9eeca106725	4055	}
Kojto	122:f9eeca106725	4056
Kojto	122:f9eeca106725	4057	/**
Kojto	122:f9eeca106725	4058	* @brief Check if RCC flag Software reset is set or not.
Kojto	122:f9eeca106725	4059	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
Kojto	122:f9eeca106725	4060	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4061	*/
Kojto	122:f9eeca106725	4062	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
Kojto	122:f9eeca106725	4063	{
Kojto	122:f9eeca106725	4064	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
Kojto	122:f9eeca106725	4065	}
Kojto	122:f9eeca106725	4066
Kojto	122:f9eeca106725	4067	/**
Kojto	122:f9eeca106725	4068	* @brief Check if RCC flag Window Watchdog reset is set or not.
Kojto	122:f9eeca106725	4069	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
Kojto	122:f9eeca106725	4070	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4071	*/
Kojto	122:f9eeca106725	4072	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
Kojto	122:f9eeca106725	4073	{
Kojto	122:f9eeca106725	4074	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
Kojto	122:f9eeca106725	4075	}
Kojto	122:f9eeca106725	4076
Kojto	122:f9eeca106725	4077	/**
Kojto	122:f9eeca106725	4078	* @brief Check if RCC flag BOR reset is set or not.
Kojto	122:f9eeca106725	4079	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
Kojto	122:f9eeca106725	4080	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4081	*/
Kojto	122:f9eeca106725	4082	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
Kojto	122:f9eeca106725	4083	{
Kojto	122:f9eeca106725	4084	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
Kojto	122:f9eeca106725	4085	}
Kojto	122:f9eeca106725	4086
Kojto	122:f9eeca106725	4087	/**
Kojto	122:f9eeca106725	4088	* @brief Set RMVF bit to clear the reset flags.
Kojto	122:f9eeca106725	4089	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
Kojto	122:f9eeca106725	4090	* @retval None
Kojto	122:f9eeca106725	4091	*/
Kojto	122:f9eeca106725	4092	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
Kojto	122:f9eeca106725	4093	{
Kojto	122:f9eeca106725	4094	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
Kojto	122:f9eeca106725	4095	}
Kojto	122:f9eeca106725	4096
Kojto	122:f9eeca106725	4097	/**
Kojto	122:f9eeca106725	4098	* @}
Kojto	122:f9eeca106725	4099	*/
Kojto	122:f9eeca106725	4100
Kojto	122:f9eeca106725	4101	/** @defgroup RCC_LL_EF_IT_Management IT Management
Kojto	122:f9eeca106725	4102	* @{
Kojto	122:f9eeca106725	4103	*/
Kojto	122:f9eeca106725	4104
Kojto	122:f9eeca106725	4105	/**
Kojto	122:f9eeca106725	4106	* @brief Enable LSI ready interrupt
Kojto	122:f9eeca106725	4107	* @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
Kojto	122:f9eeca106725	4108	* @retval None
Kojto	122:f9eeca106725	4109	*/
Kojto	122:f9eeca106725	4110	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
Kojto	122:f9eeca106725	4111	{
Kojto	122:f9eeca106725	4112	SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
Kojto	122:f9eeca106725	4113	}
Kojto	122:f9eeca106725	4114
Kojto	122:f9eeca106725	4115	/**
Kojto	122:f9eeca106725	4116	* @brief Enable LSE ready interrupt
Kojto	122:f9eeca106725	4117	* @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
Kojto	122:f9eeca106725	4118	* @retval None
Kojto	122:f9eeca106725	4119	*/
Kojto	122:f9eeca106725	4120	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
Kojto	122:f9eeca106725	4121	{
Kojto	122:f9eeca106725	4122	SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
Kojto	122:f9eeca106725	4123	}
Kojto	122:f9eeca106725	4124
Kojto	122:f9eeca106725	4125	/**
Kojto	122:f9eeca106725	4126	* @brief Enable MSI ready interrupt
Kojto	122:f9eeca106725	4127	* @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
Kojto	122:f9eeca106725	4128	* @retval None
Kojto	122:f9eeca106725	4129	*/
Kojto	122:f9eeca106725	4130	__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
Kojto	122:f9eeca106725	4131	{
Kojto	122:f9eeca106725	4132	SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
Kojto	122:f9eeca106725	4133	}
Kojto	122:f9eeca106725	4134
Kojto	122:f9eeca106725	4135	/**
Kojto	122:f9eeca106725	4136	* @brief Enable HSI ready interrupt
Kojto	122:f9eeca106725	4137	* @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
Kojto	122:f9eeca106725	4138	* @retval None
Kojto	122:f9eeca106725	4139	*/
Kojto	122:f9eeca106725	4140	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
Kojto	122:f9eeca106725	4141	{
Kojto	122:f9eeca106725	4142	SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
Kojto	122:f9eeca106725	4143	}
Kojto	122:f9eeca106725	4144
Kojto	122:f9eeca106725	4145	/**
Kojto	122:f9eeca106725	4146	* @brief Enable HSE ready interrupt
Kojto	122:f9eeca106725	4147	* @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
Kojto	122:f9eeca106725	4148	* @retval None
Kojto	122:f9eeca106725	4149	*/
Kojto	122:f9eeca106725	4150	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
Kojto	122:f9eeca106725	4151	{
Kojto	122:f9eeca106725	4152	SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
Kojto	122:f9eeca106725	4153	}
Kojto	122:f9eeca106725	4154
Kojto	122:f9eeca106725	4155	/**
Kojto	122:f9eeca106725	4156	* @brief Enable PLL ready interrupt
Kojto	122:f9eeca106725	4157	* @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
Kojto	122:f9eeca106725	4158	* @retval None
Kojto	122:f9eeca106725	4159	*/
Kojto	122:f9eeca106725	4160	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
Kojto	122:f9eeca106725	4161	{
Kojto	122:f9eeca106725	4162	SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
Kojto	122:f9eeca106725	4163	}
Kojto	122:f9eeca106725	4164
Kojto	122:f9eeca106725	4165	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	4166	/**
Kojto	122:f9eeca106725	4167	* @brief Enable HSI48 ready interrupt
Kojto	122:f9eeca106725	4168	* @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
Kojto	122:f9eeca106725	4169	* @retval None
Kojto	122:f9eeca106725	4170	*/
Kojto	122:f9eeca106725	4171	__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
Kojto	122:f9eeca106725	4172	{
Kojto	122:f9eeca106725	4173	SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
Kojto	122:f9eeca106725	4174	}
Kojto	122:f9eeca106725	4175	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	4176
Kojto	122:f9eeca106725	4177	/**
Kojto	122:f9eeca106725	4178	* @brief Enable PLLSAI1 ready interrupt
Kojto	122:f9eeca106725	4179	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
Kojto	122:f9eeca106725	4180	* @retval None
Kojto	122:f9eeca106725	4181	*/
Kojto	122:f9eeca106725	4182	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
Kojto	122:f9eeca106725	4183	{
Kojto	122:f9eeca106725	4184	SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
Kojto	122:f9eeca106725	4185	}
Kojto	122:f9eeca106725	4186
Kojto	122:f9eeca106725	4187	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	4188	/**
Kojto	122:f9eeca106725	4189	* @brief Enable PLLSAI2 ready interrupt
Kojto	122:f9eeca106725	4190	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY
Kojto	122:f9eeca106725	4191	* @retval None
Kojto	122:f9eeca106725	4192	*/
Kojto	122:f9eeca106725	4193	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
Kojto	122:f9eeca106725	4194	{
Kojto	122:f9eeca106725	4195	SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
Kojto	122:f9eeca106725	4196	}
Kojto	122:f9eeca106725	4197	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	145:64910690c574	4198
Kojto	122:f9eeca106725	4199	/**
Kojto	122:f9eeca106725	4200	* @brief Enable LSE clock security system interrupt
Kojto	122:f9eeca106725	4201	* @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
Kojto	122:f9eeca106725	4202	* @retval None
Kojto	122:f9eeca106725	4203	*/
Kojto	122:f9eeca106725	4204	__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
Kojto	122:f9eeca106725	4205	{
Kojto	122:f9eeca106725	4206	SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
Kojto	122:f9eeca106725	4207	}
Kojto	122:f9eeca106725	4208
Kojto	122:f9eeca106725	4209	/**
Kojto	122:f9eeca106725	4210	* @brief Disable LSI ready interrupt
Kojto	122:f9eeca106725	4211	* @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
Kojto	122:f9eeca106725	4212	* @retval None
Kojto	122:f9eeca106725	4213	*/
Kojto	122:f9eeca106725	4214	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
Kojto	122:f9eeca106725	4215	{
Kojto	122:f9eeca106725	4216	CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
Kojto	122:f9eeca106725	4217	}
Kojto	122:f9eeca106725	4218
Kojto	122:f9eeca106725	4219	/**
Kojto	122:f9eeca106725	4220	* @brief Disable LSE ready interrupt
Kojto	122:f9eeca106725	4221	* @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
Kojto	122:f9eeca106725	4222	* @retval None
Kojto	122:f9eeca106725	4223	*/
Kojto	122:f9eeca106725	4224	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
Kojto	122:f9eeca106725	4225	{
Kojto	122:f9eeca106725	4226	CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
Kojto	122:f9eeca106725	4227	}
Kojto	122:f9eeca106725	4228
Kojto	122:f9eeca106725	4229	/**
Kojto	122:f9eeca106725	4230	* @brief Disable MSI ready interrupt
Kojto	122:f9eeca106725	4231	* @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
Kojto	122:f9eeca106725	4232	* @retval None
Kojto	122:f9eeca106725	4233	*/
Kojto	122:f9eeca106725	4234	__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
Kojto	122:f9eeca106725	4235	{
Kojto	122:f9eeca106725	4236	CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
Kojto	122:f9eeca106725	4237	}
Kojto	122:f9eeca106725	4238
Kojto	122:f9eeca106725	4239	/**
Kojto	122:f9eeca106725	4240	* @brief Disable HSI ready interrupt
Kojto	122:f9eeca106725	4241	* @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
Kojto	122:f9eeca106725	4242	* @retval None
Kojto	122:f9eeca106725	4243	*/
Kojto	122:f9eeca106725	4244	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
Kojto	122:f9eeca106725	4245	{
Kojto	122:f9eeca106725	4246	CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
Kojto	122:f9eeca106725	4247	}
Kojto	122:f9eeca106725	4248
Kojto	122:f9eeca106725	4249	/**
Kojto	122:f9eeca106725	4250	* @brief Disable HSE ready interrupt
Kojto	122:f9eeca106725	4251	* @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
Kojto	122:f9eeca106725	4252	* @retval None
Kojto	122:f9eeca106725	4253	*/
Kojto	122:f9eeca106725	4254	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
Kojto	122:f9eeca106725	4255	{
Kojto	122:f9eeca106725	4256	CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
Kojto	122:f9eeca106725	4257	}
Kojto	122:f9eeca106725	4258
Kojto	122:f9eeca106725	4259	/**
Kojto	122:f9eeca106725	4260	* @brief Disable PLL ready interrupt
Kojto	122:f9eeca106725	4261	* @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
Kojto	122:f9eeca106725	4262	* @retval None
Kojto	122:f9eeca106725	4263	*/
Kojto	122:f9eeca106725	4264	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
Kojto	122:f9eeca106725	4265	{
Kojto	122:f9eeca106725	4266	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
Kojto	122:f9eeca106725	4267	}
Kojto	122:f9eeca106725	4268
Kojto	122:f9eeca106725	4269	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	4270	/**
Kojto	122:f9eeca106725	4271	* @brief Disable HSI48 ready interrupt
Kojto	122:f9eeca106725	4272	* @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
Kojto	122:f9eeca106725	4273	* @retval None
Kojto	122:f9eeca106725	4274	*/
Kojto	122:f9eeca106725	4275	__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
Kojto	122:f9eeca106725	4276	{
Kojto	122:f9eeca106725	4277	CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
Kojto	122:f9eeca106725	4278	}
Kojto	122:f9eeca106725	4279	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	4280
Kojto	122:f9eeca106725	4281	/**
Kojto	122:f9eeca106725	4282	* @brief Disable PLLSAI1 ready interrupt
Kojto	122:f9eeca106725	4283	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
Kojto	122:f9eeca106725	4284	* @retval None
Kojto	122:f9eeca106725	4285	*/
Kojto	122:f9eeca106725	4286	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
Kojto	122:f9eeca106725	4287	{
Kojto	122:f9eeca106725	4288	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
Kojto	122:f9eeca106725	4289	}
Kojto	122:f9eeca106725	4290
Kojto	122:f9eeca106725	4291	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	4292	/**
Kojto	122:f9eeca106725	4293	* @brief Disable PLLSAI2 ready interrupt
Kojto	122:f9eeca106725	4294	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY
Kojto	122:f9eeca106725	4295	* @retval None
Kojto	122:f9eeca106725	4296	*/
Kojto	122:f9eeca106725	4297	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
Kojto	122:f9eeca106725	4298	{
Kojto	122:f9eeca106725	4299	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
Kojto	122:f9eeca106725	4300	}
Kojto	122:f9eeca106725	4301	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	145:64910690c574	4302
Kojto	122:f9eeca106725	4303	/**
Kojto	122:f9eeca106725	4304	* @brief Disable LSE clock security system interrupt
Kojto	122:f9eeca106725	4305	* @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
Kojto	122:f9eeca106725	4306	* @retval None
Kojto	122:f9eeca106725	4307	*/
Kojto	122:f9eeca106725	4308	__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
Kojto	122:f9eeca106725	4309	{
Kojto	122:f9eeca106725	4310	CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
Kojto	122:f9eeca106725	4311	}
Kojto	122:f9eeca106725	4312
Kojto	122:f9eeca106725	4313	/**
Kojto	122:f9eeca106725	4314	* @brief Checks if LSI ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4315	* @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
Kojto	122:f9eeca106725	4316	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4317	*/
Kojto	122:f9eeca106725	4318	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
Kojto	122:f9eeca106725	4319	{
Kojto	122:f9eeca106725	4320	return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE));
Kojto	122:f9eeca106725	4321	}
Kojto	122:f9eeca106725	4322
Kojto	122:f9eeca106725	4323	/**
Kojto	122:f9eeca106725	4324	* @brief Checks if LSE ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4325	* @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
Kojto	122:f9eeca106725	4326	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4327	*/
Kojto	122:f9eeca106725	4328	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
Kojto	122:f9eeca106725	4329	{
Kojto	122:f9eeca106725	4330	return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE));
Kojto	122:f9eeca106725	4331	}
Kojto	122:f9eeca106725	4332
Kojto	122:f9eeca106725	4333	/**
Kojto	122:f9eeca106725	4334	* @brief Checks if MSI ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4335	* @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
Kojto	122:f9eeca106725	4336	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4337	*/
Kojto	122:f9eeca106725	4338	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
Kojto	122:f9eeca106725	4339	{
Kojto	122:f9eeca106725	4340	return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE));
Kojto	122:f9eeca106725	4341	}
Kojto	122:f9eeca106725	4342
Kojto	122:f9eeca106725	4343	/**
Kojto	122:f9eeca106725	4344	* @brief Checks if HSI ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4345	* @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
Kojto	122:f9eeca106725	4346	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4347	*/
Kojto	122:f9eeca106725	4348	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
Kojto	122:f9eeca106725	4349	{
Kojto	122:f9eeca106725	4350	return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE));
Kojto	122:f9eeca106725	4351	}
Kojto	122:f9eeca106725	4352
Kojto	122:f9eeca106725	4353	/**
Kojto	122:f9eeca106725	4354	* @brief Checks if HSE ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4355	* @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
Kojto	122:f9eeca106725	4356	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4357	*/
Kojto	122:f9eeca106725	4358	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
Kojto	122:f9eeca106725	4359	{
Kojto	122:f9eeca106725	4360	return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE));
Kojto	122:f9eeca106725	4361	}
Kojto	122:f9eeca106725	4362
Kojto	122:f9eeca106725	4363	/**
Kojto	122:f9eeca106725	4364	* @brief Checks if PLL ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4365	* @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
Kojto	122:f9eeca106725	4366	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4367	*/
Kojto	122:f9eeca106725	4368	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
Kojto	122:f9eeca106725	4369	{
Kojto	122:f9eeca106725	4370	return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE));
Kojto	122:f9eeca106725	4371	}
Kojto	122:f9eeca106725	4372
Kojto	122:f9eeca106725	4373	#if defined(RCC_HSI48_SUPPORT)
Kojto	122:f9eeca106725	4374	/**
Kojto	122:f9eeca106725	4375	* @brief Checks if HSI48 ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4376	* @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
Kojto	122:f9eeca106725	4377	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4378	*/
Kojto	122:f9eeca106725	4379	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
Kojto	122:f9eeca106725	4380	{
Kojto	122:f9eeca106725	4381	return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE));
Kojto	122:f9eeca106725	4382	}
Kojto	122:f9eeca106725	4383	#endif /* RCC_HSI48_SUPPORT */
Kojto	122:f9eeca106725	4384
Kojto	122:f9eeca106725	4385	/**
Kojto	122:f9eeca106725	4386	* @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4387	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
Kojto	122:f9eeca106725	4388	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4389	*/
Kojto	122:f9eeca106725	4390	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
Kojto	122:f9eeca106725	4391	{
Kojto	122:f9eeca106725	4392	return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE));
Kojto	122:f9eeca106725	4393	}
Kojto	122:f9eeca106725	4394
Kojto	122:f9eeca106725	4395	#if defined(RCC_PLLSAI2_SUPPORT)
Kojto	122:f9eeca106725	4396	/**
Kojto	122:f9eeca106725	4397	* @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4398	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY
Kojto	122:f9eeca106725	4399	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4400	*/
Kojto	122:f9eeca106725	4401	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
Kojto	122:f9eeca106725	4402	{
Kojto	122:f9eeca106725	4403	return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE));
Kojto	122:f9eeca106725	4404	}
Kojto	122:f9eeca106725	4405	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	145:64910690c574	4406
Kojto	122:f9eeca106725	4407	/**
Kojto	122:f9eeca106725	4408	* @brief Checks if LSECSS interrupt source is enabled or disabled.
Kojto	122:f9eeca106725	4409	* @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
Kojto	122:f9eeca106725	4410	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	4411	*/
Kojto	122:f9eeca106725	4412	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
Kojto	122:f9eeca106725	4413	{
Kojto	122:f9eeca106725	4414	return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE));
Kojto	122:f9eeca106725	4415	}
Kojto	122:f9eeca106725	4416
Kojto	122:f9eeca106725	4417	/**
Kojto	122:f9eeca106725	4418	* @}
Kojto	122:f9eeca106725	4419	*/
Kojto	122:f9eeca106725	4420
Kojto	122:f9eeca106725	4421	#if defined(USE_FULL_LL_DRIVER)
Kojto	122:f9eeca106725	4422	/** @defgroup RCC_LL_EF_Init De-initialization function
Kojto	122:f9eeca106725	4423	* @{
Kojto	122:f9eeca106725	4424	*/
Kojto	122:f9eeca106725	4425	ErrorStatus LL_RCC_DeInit(void);
Kojto	122:f9eeca106725	4426	/**
Kojto	122:f9eeca106725	4427	* @}
Kojto	122:f9eeca106725	4428	*/
Kojto	122:f9eeca106725	4429
Kojto	122:f9eeca106725	4430	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
Kojto	122:f9eeca106725	4431	* @{
Kojto	122:f9eeca106725	4432	*/
Kojto	122:f9eeca106725	4433	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
Kojto	122:f9eeca106725	4434	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
Kojto	122:f9eeca106725	4435	#if defined(UART4) \|\| defined(UART5)
Kojto	122:f9eeca106725	4436	uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
Kojto	122:f9eeca106725	4437	#endif /* UART4 \|\| UART5 */
Kojto	122:f9eeca106725	4438	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
Kojto	122:f9eeca106725	4439	uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
Kojto	122:f9eeca106725	4440	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
Kojto	122:f9eeca106725	4441	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
Kojto	122:f9eeca106725	4442	uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
Kojto	122:f9eeca106725	4443	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
Kojto	122:f9eeca106725	4444	#if defined(USB_OTG_FS) \|\| defined(USB)
Kojto	122:f9eeca106725	4445	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
Kojto	122:f9eeca106725	4446	#endif /* USB_OTG_FS \|\| USB */
Kojto	122:f9eeca106725	4447	uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
AnnaBridge	145:64910690c574	4448	#if defined(SWPMI1)
Kojto	122:f9eeca106725	4449	uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource);
AnnaBridge	145:64910690c574	4450	#endif /* SWPMI1 */
Kojto	122:f9eeca106725	4451	#if defined(DFSDM1_Channel0)
Kojto	122:f9eeca106725	4452	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
Kojto	122:f9eeca106725	4453	#endif /* DFSDM1_Channel0 */
Kojto	122:f9eeca106725	4454	/**
Kojto	122:f9eeca106725	4455	* @}
Kojto	122:f9eeca106725	4456	*/
Kojto	122:f9eeca106725	4457	#endif /* USE_FULL_LL_DRIVER */
Kojto	122:f9eeca106725	4458
Kojto	122:f9eeca106725	4459	/**
Kojto	122:f9eeca106725	4460	* @}
Kojto	122:f9eeca106725	4461	*/
Kojto	122:f9eeca106725	4462
Kojto	122:f9eeca106725	4463	/**
Kojto	122:f9eeca106725	4464	* @}
Kojto	122:f9eeca106725	4465	*/
Kojto	122:f9eeca106725	4466
Kojto	122:f9eeca106725	4467	#endif /* defined(RCC) */
Kojto	122:f9eeca106725	4468
Kojto	122:f9eeca106725	4469	/**
Kojto	122:f9eeca106725	4470	* @}
Kojto	122:f9eeca106725	4471	*/
Kojto	122:f9eeca106725	4472
Kojto	122:f9eeca106725	4473	#ifdef __cplusplus
Kojto	122:f9eeca106725	4474	}
Kojto	122:f9eeca106725	4475	#endif
Kojto	122:f9eeca106725	4476
Kojto	122:f9eeca106725	4477	#endif /* __STM32L4xx_LL_RCC_H */
Kojto	122:f9eeca106725	4478
Kojto	122:f9eeca106725	4479	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/