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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:: <>
Date:: Wed Apr 12 16:07:08 2017 +0100
Revision:: 140:97feb9bacc10
Parent:: 128:9bcdf88f62b0
Child:: 145:64910690c574

Release 140 of the mbed library

Ports for Upcoming Targets

3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992

Fixes and Changes

3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/**
Kojto	122:f9eeca106725	2	******************************************************************************
Kojto	122:f9eeca106725	3	* @file stm32l4xx_ll_bus.h
Kojto	122:f9eeca106725	4	* @author MCD Application Team
Kojto	122:f9eeca106725	5	* @version V1.5.1
Kojto	122:f9eeca106725	6	* @date 31-May-2016
Kojto	122:f9eeca106725	7	* @brief Header file of BUS LL module.
Kojto	122:f9eeca106725	8
Kojto	122:f9eeca106725	9	@verbatim
Kojto	122:f9eeca106725	10	##### RCC Limitations #####
Kojto	122:f9eeca106725	11	==============================================================================
Kojto	122:f9eeca106725	12	[..]
Kojto	122:f9eeca106725	13	A delay between an RCC peripheral clock enable and the effective peripheral
Kojto	122:f9eeca106725	14	enabling should be taken into account in order to manage the peripheral read/write
Kojto	122:f9eeca106725	15	from/to registers.
Kojto	122:f9eeca106725	16	(+) This delay depends on the peripheral mapping.
Kojto	122:f9eeca106725	17	(++) AHB & APB peripherals, 1 dummy read is necessary
Kojto	122:f9eeca106725	18
Kojto	122:f9eeca106725	19	[..]
Kojto	122:f9eeca106725	20	Workarounds:
Kojto	122:f9eeca106725	21	(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
Kojto	122:f9eeca106725	22	inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
Kojto	122:f9eeca106725	23
Kojto	122:f9eeca106725	24	@endverbatim
Kojto	122:f9eeca106725	25	******************************************************************************
Kojto	122:f9eeca106725	26	* @attention
Kojto	122:f9eeca106725	27	*
Kojto	122:f9eeca106725	28	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto	122:f9eeca106725	29	*
Kojto	122:f9eeca106725	30	* Redistribution and use in source and binary forms, with or without modification,
Kojto	122:f9eeca106725	31	* are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	32	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	122:f9eeca106725	33	* this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	34	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	122:f9eeca106725	35	* this list of conditions and the following disclaimer in the documentation
Kojto	122:f9eeca106725	36	* and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	37	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	122:f9eeca106725	38	* may be used to endorse or promote products derived from this software
Kojto	122:f9eeca106725	39	* without specific prior written permission.
Kojto	122:f9eeca106725	40	*
Kojto	122:f9eeca106725	41	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	42	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	43	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	122:f9eeca106725	44	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	122:f9eeca106725	45	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	122:f9eeca106725	46	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	122:f9eeca106725	47	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	122:f9eeca106725	48	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	122:f9eeca106725	49	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	122:f9eeca106725	50	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	51	*
Kojto	122:f9eeca106725	52	******************************************************************************
Kojto	122:f9eeca106725	53	*/
Kojto	122:f9eeca106725	54
Kojto	122:f9eeca106725	55	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	122:f9eeca106725	56	#ifndef __STM32L4xx_LL_BUS_H
Kojto	122:f9eeca106725	57	#define __STM32L4xx_LL_BUS_H
Kojto	122:f9eeca106725	58
Kojto	122:f9eeca106725	59	#ifdef __cplusplus
Kojto	122:f9eeca106725	60	extern "C" {
Kojto	122:f9eeca106725	61	#endif
Kojto	122:f9eeca106725	62
Kojto	122:f9eeca106725	63	/* Includes ------------------------------------------------------------------*/
Kojto	122:f9eeca106725	64	#include "stm32l4xx.h"
Kojto	122:f9eeca106725	65
Kojto	122:f9eeca106725	66	/** @addtogroup STM32L4xx_LL_Driver
Kojto	122:f9eeca106725	67	* @{
Kojto	122:f9eeca106725	68	*/
Kojto	122:f9eeca106725	69
Kojto	122:f9eeca106725	70	#if defined(RCC)
Kojto	122:f9eeca106725	71
Kojto	122:f9eeca106725	72	/** @defgroup BUS_LL BUS
Kojto	122:f9eeca106725	73	* @{
Kojto	122:f9eeca106725	74	*/
Kojto	122:f9eeca106725	75
Kojto	122:f9eeca106725	76	/* Private types -------------------------------------------------------------*/
Kojto	122:f9eeca106725	77	/* Private variables ---------------------------------------------------------*/
Kojto	122:f9eeca106725	78
Kojto	122:f9eeca106725	79	/* Private constants ---------------------------------------------------------*/
Kojto	122:f9eeca106725	80
Kojto	122:f9eeca106725	81	/* Private macros ------------------------------------------------------------*/
Kojto	122:f9eeca106725	82
Kojto	122:f9eeca106725	83	/* Exported types ------------------------------------------------------------*/
Kojto	122:f9eeca106725	84	/* Exported constants --------------------------------------------------------*/
Kojto	122:f9eeca106725	85	/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
Kojto	122:f9eeca106725	86	* @{
Kojto	122:f9eeca106725	87	*/
Kojto	122:f9eeca106725	88
Kojto	122:f9eeca106725	89	/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
Kojto	122:f9eeca106725	90	* @{
Kojto	122:f9eeca106725	91	*/
Kojto	122:f9eeca106725	92	#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
Kojto	122:f9eeca106725	93	#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
Kojto	122:f9eeca106725	94	#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
Kojto	122:f9eeca106725	95	#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
Kojto	122:f9eeca106725	96	#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
Kojto	122:f9eeca106725	97	#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
Kojto	122:f9eeca106725	98	#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
Kojto	122:f9eeca106725	99	/**
Kojto	122:f9eeca106725	100	* @}
Kojto	122:f9eeca106725	101	*/
Kojto	122:f9eeca106725	102
Kojto	122:f9eeca106725	103	/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
Kojto	122:f9eeca106725	104	* @{
Kojto	122:f9eeca106725	105	*/
Kojto	122:f9eeca106725	106	#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
Kojto	122:f9eeca106725	107	#define LL_AHB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
Kojto	122:f9eeca106725	108	#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
Kojto	122:f9eeca106725	109	#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
Kojto	122:f9eeca106725	110	#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
Kojto	122:f9eeca106725	111	#if defined(GPIOD)
Kojto	122:f9eeca106725	112	#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
Kojto	122:f9eeca106725	113	#endif /GPIOD/
Kojto	122:f9eeca106725	114	#if defined(GPIOE)
Kojto	122:f9eeca106725	115	#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
Kojto	122:f9eeca106725	116	#endif /GPIOE/
Kojto	122:f9eeca106725	117	#if defined(GPIOF)
Kojto	122:f9eeca106725	118	#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
Kojto	122:f9eeca106725	119	#endif /* GPIOF */
Kojto	122:f9eeca106725	120	#if defined(GPIOG)
Kojto	122:f9eeca106725	121	#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
Kojto	122:f9eeca106725	122	#endif /* GPIOG */
Kojto	122:f9eeca106725	123	#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
Kojto	122:f9eeca106725	124	#if defined(USB_OTG_FS)
Kojto	122:f9eeca106725	125	#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
Kojto	122:f9eeca106725	126	#endif /* USB_OTG_FS */
Kojto	122:f9eeca106725	127	#define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
Kojto	122:f9eeca106725	128	#if defined(AES)
Kojto	122:f9eeca106725	129	#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
Kojto	122:f9eeca106725	130	#endif /* AES */
Kojto	122:f9eeca106725	131	#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
Kojto	122:f9eeca106725	132	/**
Kojto	122:f9eeca106725	133	* @}
Kojto	122:f9eeca106725	134	*/
Kojto	122:f9eeca106725	135
Kojto	122:f9eeca106725	136	/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
Kojto	122:f9eeca106725	137	* @{
Kojto	122:f9eeca106725	138	*/
Kojto	122:f9eeca106725	139	#define LL_AHB3_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
Kojto	122:f9eeca106725	140	#if defined(FMC_Bank1_R)
Kojto	122:f9eeca106725	141	#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
Kojto	122:f9eeca106725	142	#endif /* FMC_Bank1_R */
Kojto	122:f9eeca106725	143	#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
Kojto	122:f9eeca106725	144	/**
Kojto	122:f9eeca106725	145	* @}
Kojto	122:f9eeca106725	146	*/
Kojto	122:f9eeca106725	147
Kojto	122:f9eeca106725	148	/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
Kojto	122:f9eeca106725	149	* @{
Kojto	122:f9eeca106725	150	*/
Kojto	122:f9eeca106725	151	#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
Kojto	122:f9eeca106725	152	#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
Kojto	122:f9eeca106725	153	#if defined(TIM3)
Kojto	122:f9eeca106725	154	#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
Kojto	122:f9eeca106725	155	#endif /* TIM3 */
Kojto	122:f9eeca106725	156	#if defined(TIM4)
Kojto	122:f9eeca106725	157	#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
Kojto	122:f9eeca106725	158	#endif /* TIM4 */
Kojto	122:f9eeca106725	159	#if defined(TIM5)
Kojto	122:f9eeca106725	160	#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
Kojto	122:f9eeca106725	161	#endif /* TIM5 */
Kojto	122:f9eeca106725	162	#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
Kojto	122:f9eeca106725	163	#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
Kojto	122:f9eeca106725	164	#if defined(LCD)
Kojto	122:f9eeca106725	165	#define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
Kojto	122:f9eeca106725	166	#endif /* LCD */
Kojto	122:f9eeca106725	167	#if defined(RCC_APB1ENR1_RTCAPBEN)
Kojto	122:f9eeca106725	168	#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
Kojto	122:f9eeca106725	169	#endif /* RCC_APB1ENR1_RTCAPBEN */
Kojto	122:f9eeca106725	170	#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
Kojto	122:f9eeca106725	171	#if defined(SPI2)
Kojto	122:f9eeca106725	172	#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
Kojto	122:f9eeca106725	173	#endif /* SPI2 */
Kojto	122:f9eeca106725	174	#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
Kojto	122:f9eeca106725	175	#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
Kojto	122:f9eeca106725	176	#if defined(USART3)
Kojto	122:f9eeca106725	177	#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
Kojto	122:f9eeca106725	178	#endif /* USART3 */
Kojto	122:f9eeca106725	179	#if defined(UART4)
Kojto	122:f9eeca106725	180	#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
Kojto	122:f9eeca106725	181	#endif /* UART4 */
Kojto	122:f9eeca106725	182	#if defined(UART5)
Kojto	122:f9eeca106725	183	#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
Kojto	122:f9eeca106725	184	#endif /* UART5 */
Kojto	122:f9eeca106725	185	#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
Kojto	122:f9eeca106725	186	#if defined(I2C2)
Kojto	122:f9eeca106725	187	#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
Kojto	122:f9eeca106725	188	#endif /* I2C2 */
Kojto	122:f9eeca106725	189	#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
Kojto	122:f9eeca106725	190	#if defined(CRS)
Kojto	122:f9eeca106725	191	#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
Kojto	122:f9eeca106725	192	#endif /* CRS */
Kojto	122:f9eeca106725	193	#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN
Kojto	122:f9eeca106725	194	#if defined(USB)
Kojto	122:f9eeca106725	195	#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN
Kojto	122:f9eeca106725	196	#endif /* USB */
Kojto	122:f9eeca106725	197	#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
Kojto	122:f9eeca106725	198	#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN
Kojto	122:f9eeca106725	199	#define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN
Kojto	122:f9eeca106725	200	#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
Kojto	122:f9eeca106725	201	/**
Kojto	122:f9eeca106725	202	* @}
Kojto	122:f9eeca106725	203	*/
Kojto	122:f9eeca106725	204
Kojto	122:f9eeca106725	205
Kojto	122:f9eeca106725	206	/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
Kojto	122:f9eeca106725	207	* @{
Kojto	122:f9eeca106725	208	*/
Kojto	122:f9eeca106725	209	#define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU
Kojto	122:f9eeca106725	210	#define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
Kojto	122:f9eeca106725	211	#define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN
Kojto	122:f9eeca106725	212	#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
Kojto	122:f9eeca106725	213	/**
Kojto	122:f9eeca106725	214	* @}
Kojto	122:f9eeca106725	215	*/
Kojto	122:f9eeca106725	216
Kojto	122:f9eeca106725	217	/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
Kojto	122:f9eeca106725	218	* @{
Kojto	122:f9eeca106725	219	*/
Kojto	122:f9eeca106725	220	#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
Kojto	122:f9eeca106725	221	#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
Kojto	122:f9eeca106725	222	#define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN
Kojto	122:f9eeca106725	223	#if defined(SDMMC1)
Kojto	122:f9eeca106725	224	#define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
Kojto	122:f9eeca106725	225	#endif /* SDMMC1 */
Kojto	122:f9eeca106725	226	#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
Kojto	122:f9eeca106725	227	#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
Kojto	122:f9eeca106725	228	#if defined(TIM8)
Kojto	122:f9eeca106725	229	#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
Kojto	122:f9eeca106725	230	#endif /* TIM8 */
Kojto	122:f9eeca106725	231	#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
Kojto	122:f9eeca106725	232	#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
Kojto	122:f9eeca106725	233	#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
Kojto	122:f9eeca106725	234	#if defined(TIM17)
Kojto	122:f9eeca106725	235	#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
Kojto	122:f9eeca106725	236	#endif /* TIM17 */
Kojto	122:f9eeca106725	237	#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
Kojto	122:f9eeca106725	238	#if defined(SAI2)
Kojto	122:f9eeca106725	239	#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
Kojto	122:f9eeca106725	240	#endif /* SAI2 */
Kojto	122:f9eeca106725	241	#if defined(DFSDM1_Channel0)
Kojto	122:f9eeca106725	242	#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
Kojto	122:f9eeca106725	243	#endif /* DFSDM1_Channel0 */
Kojto	122:f9eeca106725	244	/**
Kojto	122:f9eeca106725	245	* @}
Kojto	122:f9eeca106725	246	*/
Kojto	122:f9eeca106725	247
Kojto	122:f9eeca106725	248	/** Legacy definitions for compatibility purpose
Kojto	122:f9eeca106725	249	@cond 0
Kojto	122:f9eeca106725	250	*/
Kojto	122:f9eeca106725	251	#if defined(DFSDM1_Channel0)
Kojto	122:f9eeca106725	252	#define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1
Kojto	122:f9eeca106725	253	#endif /* DFSDM1_Channel0 */
Kojto	122:f9eeca106725	254	/**
Kojto	122:f9eeca106725	255	@endcond
Kojto	122:f9eeca106725	256	*/
Kojto	122:f9eeca106725	257
Kojto	122:f9eeca106725	258	/**
Kojto	122:f9eeca106725	259	* @}
Kojto	122:f9eeca106725	260	*/
Kojto	122:f9eeca106725	261
Kojto	122:f9eeca106725	262	/* Exported macro ------------------------------------------------------------*/
Kojto	122:f9eeca106725	263	/* Exported functions --------------------------------------------------------*/
Kojto	122:f9eeca106725	264	/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
Kojto	122:f9eeca106725	265	* @{
Kojto	122:f9eeca106725	266	*/
Kojto	122:f9eeca106725	267
Kojto	122:f9eeca106725	268	/** @defgroup BUS_LL_EF_AHB1 AHB1
Kojto	122:f9eeca106725	269	* @{
Kojto	122:f9eeca106725	270	*/
Kojto	122:f9eeca106725	271
Kojto	122:f9eeca106725	272	/**
Kojto	122:f9eeca106725	273	* @brief Enable AHB1 peripherals clock.
Kojto	122:f9eeca106725	274	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	275	* AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	276	* AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	277	* AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	278	* AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock
Kojto	122:f9eeca106725	279	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	280	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto	122:f9eeca106725	281	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto	122:f9eeca106725	282	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto	122:f9eeca106725	283	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto	122:f9eeca106725	284	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
Kojto	122:f9eeca106725	285	*
Kojto	122:f9eeca106725	286	* @retval None
Kojto	122:f9eeca106725	287	*/
Kojto	122:f9eeca106725	288	__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
Kojto	122:f9eeca106725	289	{
Kojto	122:f9eeca106725	290	__IO uint32_t tmpreg;
Kojto	122:f9eeca106725	291	SET_BIT(RCC->AHB1ENR, Periphs);
Kojto	122:f9eeca106725	292	/* Delay after an RCC peripheral clock enabling */
Kojto	122:f9eeca106725	293	tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
Kojto	122:f9eeca106725	294	(void)tmpreg;
Kojto	122:f9eeca106725	295	}
Kojto	122:f9eeca106725	296
Kojto	122:f9eeca106725	297	/**
Kojto	122:f9eeca106725	298	* @brief Check if AHB1 peripheral clock is enabled or not
Kojto	122:f9eeca106725	299	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	300	* AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	301	* AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	302	* AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	303	* AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock
Kojto	122:f9eeca106725	304	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	305	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto	122:f9eeca106725	306	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto	122:f9eeca106725	307	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto	122:f9eeca106725	308	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto	122:f9eeca106725	309	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
Kojto	122:f9eeca106725	310	*
Kojto	122:f9eeca106725	311	* @retval State of Periphs (1 or 0).
Kojto	122:f9eeca106725	312	*/
Kojto	122:f9eeca106725	313	__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
Kojto	122:f9eeca106725	314	{
Kojto	122:f9eeca106725	315	return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
Kojto	122:f9eeca106725	316	}
Kojto	122:f9eeca106725	317
Kojto	122:f9eeca106725	318	/**
Kojto	122:f9eeca106725	319	* @brief Disable AHB1 peripherals clock.
Kojto	122:f9eeca106725	320	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	321	* AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	322	* AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	323	* AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	324	* AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock
Kojto	122:f9eeca106725	325	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	326	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto	122:f9eeca106725	327	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto	122:f9eeca106725	328	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto	122:f9eeca106725	329	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto	122:f9eeca106725	330	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
Kojto	122:f9eeca106725	331	*
Kojto	122:f9eeca106725	332	* @retval None
Kojto	122:f9eeca106725	333	*/
Kojto	122:f9eeca106725	334	__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
Kojto	122:f9eeca106725	335	{
Kojto	122:f9eeca106725	336	CLEAR_BIT(RCC->AHB1ENR, Periphs);
Kojto	122:f9eeca106725	337	}
Kojto	122:f9eeca106725	338
Kojto	122:f9eeca106725	339	/**
Kojto	122:f9eeca106725	340	* @brief Force AHB1 peripherals reset.
Kojto	122:f9eeca106725	341	* @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	342	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	343	* AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	344	* AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	345	* AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset
Kojto	122:f9eeca106725	346	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	347	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
Kojto	122:f9eeca106725	348	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto	122:f9eeca106725	349	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto	122:f9eeca106725	350	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto	122:f9eeca106725	351	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto	122:f9eeca106725	352	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
Kojto	122:f9eeca106725	353	*
Kojto	122:f9eeca106725	354	* @retval None
Kojto	122:f9eeca106725	355	*/
Kojto	122:f9eeca106725	356	__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
Kojto	122:f9eeca106725	357	{
Kojto	122:f9eeca106725	358	SET_BIT(RCC->AHB1RSTR, Periphs);
Kojto	122:f9eeca106725	359	}
Kojto	122:f9eeca106725	360
Kojto	122:f9eeca106725	361	/**
Kojto	122:f9eeca106725	362	* @brief Release AHB1 peripherals reset.
Kojto	122:f9eeca106725	363	* @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	364	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	365	* AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	366	* AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	367	* AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset
Kojto	122:f9eeca106725	368	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	369	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
Kojto	122:f9eeca106725	370	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto	122:f9eeca106725	371	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto	122:f9eeca106725	372	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto	122:f9eeca106725	373	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto	122:f9eeca106725	374	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
Kojto	122:f9eeca106725	375	*
Kojto	122:f9eeca106725	376	* @retval None
Kojto	122:f9eeca106725	377	*/
Kojto	122:f9eeca106725	378	__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
Kojto	122:f9eeca106725	379	{
Kojto	122:f9eeca106725	380	CLEAR_BIT(RCC->AHB1RSTR, Periphs);
Kojto	122:f9eeca106725	381	}
Kojto	122:f9eeca106725	382
Kojto	122:f9eeca106725	383	/**
Kojto	122:f9eeca106725	384	* @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
Kojto	122:f9eeca106725	385	* @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	386	* AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	387	* AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	388	* AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	389	* AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	390	* AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep
Kojto	122:f9eeca106725	391	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	392	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto	122:f9eeca106725	393	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto	122:f9eeca106725	394	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto	122:f9eeca106725	395	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
Kojto	122:f9eeca106725	396	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto	122:f9eeca106725	397	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
Kojto	122:f9eeca106725	398	*
Kojto	122:f9eeca106725	399	* @retval None
Kojto	122:f9eeca106725	400	*/
Kojto	122:f9eeca106725	401	__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
Kojto	122:f9eeca106725	402	{
Kojto	122:f9eeca106725	403	__IO uint32_t tmpreg;
Kojto	122:f9eeca106725	404	SET_BIT(RCC->AHB1SMENR, Periphs);
Kojto	122:f9eeca106725	405	/* Delay after an RCC peripheral clock enabling */
Kojto	122:f9eeca106725	406	tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
Kojto	122:f9eeca106725	407	(void)tmpreg;
Kojto	122:f9eeca106725	408	}
Kojto	122:f9eeca106725	409
Kojto	122:f9eeca106725	410	/**
Kojto	122:f9eeca106725	411	* @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
Kojto	122:f9eeca106725	412	* @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	413	* AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	414	* AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	415	* AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	416	* AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	417	* AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep
Kojto	122:f9eeca106725	418	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	419	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto	122:f9eeca106725	420	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto	122:f9eeca106725	421	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto	122:f9eeca106725	422	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
Kojto	122:f9eeca106725	423	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto	122:f9eeca106725	424	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
Kojto	122:f9eeca106725	425	*
Kojto	122:f9eeca106725	426	* @retval None
Kojto	122:f9eeca106725	427	*/
Kojto	122:f9eeca106725	428	__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
Kojto	122:f9eeca106725	429	{
Kojto	122:f9eeca106725	430	CLEAR_BIT(RCC->AHB1SMENR, Periphs);
Kojto	122:f9eeca106725	431	}
Kojto	122:f9eeca106725	432
Kojto	122:f9eeca106725	433	/**
Kojto	122:f9eeca106725	434	* @}
Kojto	122:f9eeca106725	435	*/
Kojto	122:f9eeca106725	436
Kojto	122:f9eeca106725	437	/** @defgroup BUS_LL_EF_AHB2 AHB2
Kojto	122:f9eeca106725	438	* @{
Kojto	122:f9eeca106725	439	*/
Kojto	122:f9eeca106725	440
Kojto	122:f9eeca106725	441	/**
Kojto	122:f9eeca106725	442	* @brief Enable AHB2 peripherals clock.
Kojto	122:f9eeca106725	443	* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	444	* AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	445	* AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	446	* AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	447	* AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	448	* AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	449	* AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	450	* AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	451	* AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	452	* AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	453	* AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	454	* AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
Kojto	122:f9eeca106725	455	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	456	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto	122:f9eeca106725	457	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto	122:f9eeca106725	458	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto	122:f9eeca106725	459	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto	122:f9eeca106725	460	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto	122:f9eeca106725	461	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto	122:f9eeca106725	462	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto	122:f9eeca106725	463	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
Kojto	122:f9eeca106725	464	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto	122:f9eeca106725	465	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
Kojto	122:f9eeca106725	466	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
Kojto	122:f9eeca106725	467	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto	122:f9eeca106725	468	*
Kojto	122:f9eeca106725	469	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	470	* @retval None
Kojto	122:f9eeca106725	471	*/
Kojto	122:f9eeca106725	472	__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
Kojto	122:f9eeca106725	473	{
Kojto	122:f9eeca106725	474	__IO uint32_t tmpreg;
Kojto	122:f9eeca106725	475	SET_BIT(RCC->AHB2ENR, Periphs);
Kojto	122:f9eeca106725	476	/* Delay after an RCC peripheral clock enabling */
Kojto	122:f9eeca106725	477	tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
Kojto	122:f9eeca106725	478	(void)tmpreg;
Kojto	122:f9eeca106725	479	}
Kojto	122:f9eeca106725	480
Kojto	122:f9eeca106725	481	/**
Kojto	122:f9eeca106725	482	* @brief Check if AHB2 peripheral clock is enabled or not
Kojto	122:f9eeca106725	483	* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	484	* AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	485	* AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	486	* AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	487	* AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	488	* AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	489	* AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	490	* AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	491	* AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	492	* AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	493	* AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	494	* AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
Kojto	122:f9eeca106725	495	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	496	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto	122:f9eeca106725	497	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto	122:f9eeca106725	498	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto	122:f9eeca106725	499	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto	122:f9eeca106725	500	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto	122:f9eeca106725	501	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto	122:f9eeca106725	502	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto	122:f9eeca106725	503	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
Kojto	122:f9eeca106725	504	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto	122:f9eeca106725	505	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
Kojto	122:f9eeca106725	506	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
Kojto	122:f9eeca106725	507	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto	122:f9eeca106725	508	*
Kojto	122:f9eeca106725	509	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	510	* @retval State of Periphs (1 or 0).
Kojto	122:f9eeca106725	511	*/
Kojto	122:f9eeca106725	512	__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
Kojto	122:f9eeca106725	513	{
Kojto	122:f9eeca106725	514	return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
Kojto	122:f9eeca106725	515	}
Kojto	122:f9eeca106725	516
Kojto	122:f9eeca106725	517	/**
Kojto	122:f9eeca106725	518	* @brief Disable AHB2 peripherals clock.
Kojto	122:f9eeca106725	519	* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	520	* AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	521	* AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	522	* AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	523	* AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	524	* AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	525	* AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	526	* AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	527	* AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	528	* AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	529	* AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	530	* AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
Kojto	122:f9eeca106725	531	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	532	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto	122:f9eeca106725	533	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto	122:f9eeca106725	534	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto	122:f9eeca106725	535	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto	122:f9eeca106725	536	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto	122:f9eeca106725	537	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto	122:f9eeca106725	538	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto	122:f9eeca106725	539	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
Kojto	122:f9eeca106725	540	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto	122:f9eeca106725	541	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
Kojto	122:f9eeca106725	542	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
Kojto	122:f9eeca106725	543	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto	122:f9eeca106725	544	*
Kojto	122:f9eeca106725	545	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	546	* @retval None
Kojto	122:f9eeca106725	547	*/
Kojto	122:f9eeca106725	548	__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
Kojto	122:f9eeca106725	549	{
Kojto	122:f9eeca106725	550	CLEAR_BIT(RCC->AHB2ENR, Periphs);
Kojto	122:f9eeca106725	551	}
Kojto	122:f9eeca106725	552
Kojto	122:f9eeca106725	553	/**
Kojto	122:f9eeca106725	554	* @brief Force AHB2 peripherals reset.
Kojto	122:f9eeca106725	555	* @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	556	* AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	557	* AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	558	* AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	559	* AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	560	* AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	561	* AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	562	* AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	563	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	564	* AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	565	* AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	566	* AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
Kojto	122:f9eeca106725	567	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	568	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
Kojto	122:f9eeca106725	569	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto	122:f9eeca106725	570	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto	122:f9eeca106725	571	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto	122:f9eeca106725	572	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto	122:f9eeca106725	573	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto	122:f9eeca106725	574	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto	122:f9eeca106725	575	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto	122:f9eeca106725	576	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
Kojto	122:f9eeca106725	577	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto	122:f9eeca106725	578	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
Kojto	122:f9eeca106725	579	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
Kojto	122:f9eeca106725	580	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto	122:f9eeca106725	581	*
Kojto	122:f9eeca106725	582	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	583	* @retval None
Kojto	122:f9eeca106725	584	*/
Kojto	122:f9eeca106725	585	__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
Kojto	122:f9eeca106725	586	{
Kojto	122:f9eeca106725	587	SET_BIT(RCC->AHB2RSTR, Periphs);
Kojto	122:f9eeca106725	588	}
Kojto	122:f9eeca106725	589
Kojto	122:f9eeca106725	590	/**
Kojto	122:f9eeca106725	591	* @brief Release AHB2 peripherals reset.
Kojto	122:f9eeca106725	592	* @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	593	* AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	594	* AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	595	* AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	596	* AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	597	* AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	598	* AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	599	* AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	600	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	601	* AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	602	* AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	603	* AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
Kojto	122:f9eeca106725	604	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	605	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
Kojto	122:f9eeca106725	606	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto	122:f9eeca106725	607	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto	122:f9eeca106725	608	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto	122:f9eeca106725	609	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto	122:f9eeca106725	610	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto	122:f9eeca106725	611	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto	122:f9eeca106725	612	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto	122:f9eeca106725	613	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
Kojto	122:f9eeca106725	614	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto	122:f9eeca106725	615	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
Kojto	122:f9eeca106725	616	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
Kojto	122:f9eeca106725	617	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto	122:f9eeca106725	618	*
Kojto	122:f9eeca106725	619	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	620	* @retval None
Kojto	122:f9eeca106725	621	*/
Kojto	122:f9eeca106725	622	__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
Kojto	122:f9eeca106725	623	{
Kojto	122:f9eeca106725	624	CLEAR_BIT(RCC->AHB2RSTR, Periphs);
Kojto	122:f9eeca106725	625	}
Kojto	122:f9eeca106725	626
Kojto	122:f9eeca106725	627	/**
Kojto	122:f9eeca106725	628	* @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
Kojto	122:f9eeca106725	629	* @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	630	* AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	631	* AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	632	* AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	633	* AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	634	* AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	635	* AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	636	* AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	637	* AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	638	* AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	639	* AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	640	* AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	641	* AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep
Kojto	122:f9eeca106725	642	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	643	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto	122:f9eeca106725	644	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto	122:f9eeca106725	645	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto	122:f9eeca106725	646	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto	122:f9eeca106725	647	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto	122:f9eeca106725	648	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto	122:f9eeca106725	649	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto	122:f9eeca106725	650	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
Kojto	122:f9eeca106725	651	* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
Kojto	122:f9eeca106725	652	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto	122:f9eeca106725	653	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
Kojto	122:f9eeca106725	654	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
Kojto	122:f9eeca106725	655	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto	122:f9eeca106725	656	*
Kojto	122:f9eeca106725	657	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	658	* @retval None
Kojto	122:f9eeca106725	659	*/
Kojto	122:f9eeca106725	660	__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
Kojto	122:f9eeca106725	661	{
Kojto	122:f9eeca106725	662	__IO uint32_t tmpreg;
Kojto	122:f9eeca106725	663	SET_BIT(RCC->AHB2SMENR, Periphs);
Kojto	122:f9eeca106725	664	/* Delay after an RCC peripheral clock enabling */
Kojto	122:f9eeca106725	665	tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
Kojto	122:f9eeca106725	666	(void)tmpreg;
Kojto	122:f9eeca106725	667	}
Kojto	122:f9eeca106725	668
Kojto	122:f9eeca106725	669	/**
Kojto	122:f9eeca106725	670	* @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
Kojto	122:f9eeca106725	671	* @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	672	* AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	673	* AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	674	* AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	675	* AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	676	* AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	677	* AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	678	* AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	679	* AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	680	* AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	681	* AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	682	* AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	683	* AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep
Kojto	122:f9eeca106725	684	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	685	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto	122:f9eeca106725	686	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto	122:f9eeca106725	687	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto	122:f9eeca106725	688	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto	122:f9eeca106725	689	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto	122:f9eeca106725	690	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto	122:f9eeca106725	691	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto	122:f9eeca106725	692	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
Kojto	122:f9eeca106725	693	* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
Kojto	122:f9eeca106725	694	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto	122:f9eeca106725	695	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
Kojto	122:f9eeca106725	696	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
Kojto	122:f9eeca106725	697	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto	122:f9eeca106725	698	*
Kojto	122:f9eeca106725	699	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	700	* @retval None
Kojto	122:f9eeca106725	701	*/
Kojto	122:f9eeca106725	702	__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
Kojto	122:f9eeca106725	703	{
Kojto	122:f9eeca106725	704	CLEAR_BIT(RCC->AHB2SMENR, Periphs);
Kojto	122:f9eeca106725	705	}
Kojto	122:f9eeca106725	706
Kojto	122:f9eeca106725	707	/**
Kojto	122:f9eeca106725	708	* @}
Kojto	122:f9eeca106725	709	*/
Kojto	122:f9eeca106725	710
Kojto	122:f9eeca106725	711	/** @defgroup BUS_LL_EF_AHB3 AHB3
Kojto	122:f9eeca106725	712	* @{
Kojto	122:f9eeca106725	713	*/
Kojto	122:f9eeca106725	714
Kojto	122:f9eeca106725	715	/**
Kojto	122:f9eeca106725	716	* @brief Enable AHB3 peripherals clock.
Kojto	122:f9eeca106725	717	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
Kojto	122:f9eeca106725	718	* AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
Kojto	122:f9eeca106725	719	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	720	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto	122:f9eeca106725	721	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto	122:f9eeca106725	722	*
Kojto	122:f9eeca106725	723	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	724	* @retval None
Kojto	122:f9eeca106725	725	*/
Kojto	122:f9eeca106725	726	__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
Kojto	122:f9eeca106725	727	{
Kojto	122:f9eeca106725	728	__IO uint32_t tmpreg;
Kojto	122:f9eeca106725	729	SET_BIT(RCC->AHB3ENR, Periphs);
Kojto	122:f9eeca106725	730	/* Delay after an RCC peripheral clock enabling */
Kojto	122:f9eeca106725	731	tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
Kojto	122:f9eeca106725	732	(void)tmpreg;
Kojto	122:f9eeca106725	733	}
Kojto	122:f9eeca106725	734
Kojto	122:f9eeca106725	735	/**
Kojto	122:f9eeca106725	736	* @brief Check if AHB3 peripheral clock is enabled or not
Kojto	122:f9eeca106725	737	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	738	* AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
Kojto	122:f9eeca106725	739	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	740	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto	122:f9eeca106725	741	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto	122:f9eeca106725	742	*
Kojto	122:f9eeca106725	743	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	744	* @retval State of Periphs (1 or 0).
Kojto	122:f9eeca106725	745	*/
Kojto	122:f9eeca106725	746	__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
Kojto	122:f9eeca106725	747	{
Kojto	122:f9eeca106725	748	return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
Kojto	122:f9eeca106725	749	}
Kojto	122:f9eeca106725	750
Kojto	122:f9eeca106725	751	/**
Kojto	122:f9eeca106725	752	* @brief Disable AHB3 peripherals clock.
Kojto	122:f9eeca106725	753	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
Kojto	122:f9eeca106725	754	* AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
Kojto	122:f9eeca106725	755	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	756	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto	122:f9eeca106725	757	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto	122:f9eeca106725	758	*
Kojto	122:f9eeca106725	759	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	760	* @retval None
Kojto	122:f9eeca106725	761	*/
Kojto	122:f9eeca106725	762	__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
Kojto	122:f9eeca106725	763	{
Kojto	122:f9eeca106725	764	CLEAR_BIT(RCC->AHB3ENR, Periphs);
Kojto	122:f9eeca106725	765	}
Kojto	122:f9eeca106725	766
Kojto	122:f9eeca106725	767	/**
Kojto	122:f9eeca106725	768	* @brief Force AHB3 peripherals reset.
Kojto	122:f9eeca106725	769	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
Kojto	122:f9eeca106725	770	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
Kojto	122:f9eeca106725	771	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	772	* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
Kojto	122:f9eeca106725	773	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto	122:f9eeca106725	774	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto	122:f9eeca106725	775	*
Kojto	122:f9eeca106725	776	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	777	* @retval None
Kojto	122:f9eeca106725	778	*/
Kojto	122:f9eeca106725	779	__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
Kojto	122:f9eeca106725	780	{
Kojto	122:f9eeca106725	781	SET_BIT(RCC->AHB3RSTR, Periphs);
Kojto	122:f9eeca106725	782	}
Kojto	122:f9eeca106725	783
Kojto	122:f9eeca106725	784	/**
Kojto	122:f9eeca106725	785	* @brief Release AHB3 peripherals reset.
Kojto	122:f9eeca106725	786	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	787	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
Kojto	122:f9eeca106725	788	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	789	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
Kojto	122:f9eeca106725	790	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto	122:f9eeca106725	791	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto	122:f9eeca106725	792	*
Kojto	122:f9eeca106725	793	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	794	* @retval None
Kojto	122:f9eeca106725	795	*/
Kojto	122:f9eeca106725	796	__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
Kojto	122:f9eeca106725	797	{
Kojto	122:f9eeca106725	798	CLEAR_BIT(RCC->AHB3RSTR, Periphs);
Kojto	122:f9eeca106725	799	}
Kojto	122:f9eeca106725	800
Kojto	122:f9eeca106725	801	/**
Kojto	122:f9eeca106725	802	* @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
Kojto	122:f9eeca106725	803	* @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	804	* AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep
Kojto	122:f9eeca106725	805	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	806	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto	122:f9eeca106725	807	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto	122:f9eeca106725	808	*
Kojto	122:f9eeca106725	809	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	810	* @retval None
Kojto	122:f9eeca106725	811	*/
Kojto	122:f9eeca106725	812	__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
Kojto	122:f9eeca106725	813	{
Kojto	122:f9eeca106725	814	__IO uint32_t tmpreg;
Kojto	122:f9eeca106725	815	SET_BIT(RCC->AHB3SMENR, Periphs);
Kojto	122:f9eeca106725	816	/* Delay after an RCC peripheral clock enabling */
Kojto	122:f9eeca106725	817	tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
Kojto	122:f9eeca106725	818	(void)tmpreg;
Kojto	122:f9eeca106725	819	}
Kojto	122:f9eeca106725	820
Kojto	122:f9eeca106725	821	/**
Kojto	122:f9eeca106725	822	* @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
Kojto	122:f9eeca106725	823	* @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	824	* AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep
Kojto	122:f9eeca106725	825	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	826	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto	122:f9eeca106725	827	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto	122:f9eeca106725	828	*
Kojto	122:f9eeca106725	829	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	830	* @retval None
Kojto	122:f9eeca106725	831	*/
Kojto	122:f9eeca106725	832	__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
Kojto	122:f9eeca106725	833	{
Kojto	122:f9eeca106725	834	CLEAR_BIT(RCC->AHB3SMENR, Periphs);
Kojto	122:f9eeca106725	835	}
Kojto	122:f9eeca106725	836
Kojto	122:f9eeca106725	837	/**
Kojto	122:f9eeca106725	838	* @}
Kojto	122:f9eeca106725	839	*/
Kojto	122:f9eeca106725	840
Kojto	122:f9eeca106725	841	/** @defgroup BUS_LL_EF_APB1 APB1
Kojto	122:f9eeca106725	842	* @{
Kojto	122:f9eeca106725	843	*/
Kojto	122:f9eeca106725	844
Kojto	122:f9eeca106725	845	/**
Kojto	122:f9eeca106725	846	* @brief Enable APB1 peripherals clock.
Kojto	122:f9eeca106725	847	* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	848	* APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	849	* APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	850	* APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	851	* APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	852	* APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	853	* APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	854	* APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	855	* APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	856	* APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	857	* APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	858	* APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	859	* APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	860	* APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	861	* APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	862	* APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	863	* APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	864	* APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	865	* APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	866	* APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	867	* APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	868	* APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	869	* APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n
Kojto	122:f9eeca106725	870	* APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
Kojto	122:f9eeca106725	871	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	872	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto	122:f9eeca106725	873	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto	122:f9eeca106725	874	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto	122:f9eeca106725	875	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto	122:f9eeca106725	876	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto	122:f9eeca106725	877	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto	122:f9eeca106725	878	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto	122:f9eeca106725	879	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
Kojto	122:f9eeca106725	880	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
Kojto	122:f9eeca106725	881	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto	122:f9eeca106725	882	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto	122:f9eeca106725	883	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto	122:f9eeca106725	884	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto	122:f9eeca106725	885	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto	122:f9eeca106725	886	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto	122:f9eeca106725	887	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto	122:f9eeca106725	888	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto	122:f9eeca106725	889	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto	122:f9eeca106725	890	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto	122:f9eeca106725	891	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
Kojto	122:f9eeca106725	892	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto	122:f9eeca106725	893	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto	122:f9eeca106725	894	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto	122:f9eeca106725	895	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto	122:f9eeca106725	896	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto	122:f9eeca106725	897	*
Kojto	122:f9eeca106725	898	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	899	* @retval None
Kojto	122:f9eeca106725	900	*/
Kojto	122:f9eeca106725	901	__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
Kojto	122:f9eeca106725	902	{
Kojto	122:f9eeca106725	903	__IO uint32_t tmpreg;
Kojto	122:f9eeca106725	904	SET_BIT(RCC->APB1ENR1, Periphs);
Kojto	122:f9eeca106725	905	/* Delay after an RCC peripheral clock enabling */
Kojto	122:f9eeca106725	906	tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
Kojto	122:f9eeca106725	907	(void)tmpreg;
Kojto	122:f9eeca106725	908	}
Kojto	122:f9eeca106725	909
Kojto	122:f9eeca106725	910	/**
Kojto	122:f9eeca106725	911	* @brief Enable APB1 peripherals clock.
Kojto	122:f9eeca106725	912	* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
Kojto	122:f9eeca106725	913	* APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n
Kojto	122:f9eeca106725	914	* APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
Kojto	122:f9eeca106725	915	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	916	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
Kojto	122:f9eeca106725	917	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
Kojto	122:f9eeca106725	918	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
Kojto	122:f9eeca106725	919	* @retval None
Kojto	122:f9eeca106725	920	*/
Kojto	122:f9eeca106725	921	__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
Kojto	122:f9eeca106725	922	{
Kojto	122:f9eeca106725	923	__IO uint32_t tmpreg;
Kojto	122:f9eeca106725	924	SET_BIT(RCC->APB1ENR2, Periphs);
Kojto	122:f9eeca106725	925	/* Delay after an RCC peripheral clock enabling */
Kojto	122:f9eeca106725	926	tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
Kojto	122:f9eeca106725	927	(void)tmpreg;
Kojto	122:f9eeca106725	928	}
Kojto	122:f9eeca106725	929
Kojto	122:f9eeca106725	930	/**
Kojto	122:f9eeca106725	931	* @brief Check if APB1 peripheral clock is enabled or not
Kojto	122:f9eeca106725	932	* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	933	* APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	934	* APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	935	* APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	936	* APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	937	* APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	938	* APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	939	* APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	940	* APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	941	* APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	942	* APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	943	* APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	944	* APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	945	* APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	946	* APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	947	* APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	948	* APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	949	* APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	950	* APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	951	* APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	952	* APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	953	* APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	954	* APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	955	* APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
Kojto	122:f9eeca106725	956	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	957	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto	122:f9eeca106725	958	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto	122:f9eeca106725	959	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto	122:f9eeca106725	960	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto	122:f9eeca106725	961	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto	122:f9eeca106725	962	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto	122:f9eeca106725	963	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto	122:f9eeca106725	964	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
Kojto	122:f9eeca106725	965	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
Kojto	122:f9eeca106725	966	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto	122:f9eeca106725	967	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto	122:f9eeca106725	968	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto	122:f9eeca106725	969	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto	122:f9eeca106725	970	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto	122:f9eeca106725	971	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto	122:f9eeca106725	972	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto	122:f9eeca106725	973	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto	122:f9eeca106725	974	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto	122:f9eeca106725	975	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto	122:f9eeca106725	976	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
Kojto	122:f9eeca106725	977	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto	122:f9eeca106725	978	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto	122:f9eeca106725	979	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto	122:f9eeca106725	980	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto	122:f9eeca106725	981	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto	122:f9eeca106725	982	*
Kojto	122:f9eeca106725	983	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	984	* @retval State of Periphs (1 or 0).
Kojto	122:f9eeca106725	985	*/
Kojto	122:f9eeca106725	986	__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
Kojto	122:f9eeca106725	987	{
Kojto	122:f9eeca106725	988	return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs);
Kojto	122:f9eeca106725	989	}
Kojto	122:f9eeca106725	990
Kojto	122:f9eeca106725	991	/**
Kojto	122:f9eeca106725	992	* @brief Check if APB1 peripheral clock is enabled or not
Kojto	122:f9eeca106725	993	* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
Kojto	122:f9eeca106725	994	* APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n
Kojto	122:f9eeca106725	995	* APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
Kojto	122:f9eeca106725	996	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	997	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
Kojto	122:f9eeca106725	998	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
Kojto	122:f9eeca106725	999	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
Kojto	122:f9eeca106725	1000	* @retval State of Periphs (1 or 0).
Kojto	122:f9eeca106725	1001	*/
Kojto	122:f9eeca106725	1002	__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
Kojto	122:f9eeca106725	1003	{
Kojto	122:f9eeca106725	1004	return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs);
Kojto	122:f9eeca106725	1005	}
Kojto	122:f9eeca106725	1006
Kojto	122:f9eeca106725	1007	/**
Kojto	122:f9eeca106725	1008	* @brief Disable APB1 peripherals clock.
Kojto	122:f9eeca106725	1009	* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1010	* APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1011	* APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1012	* APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1013	* APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1014	* APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1015	* APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1016	* APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1017	* APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1018	* APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1019	* APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1020	* APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1021	* APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1022	* APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1023	* APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1024	* APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1025	* APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1026	* APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1027	* APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1028	* APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1029	* APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1030	* APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1031	* APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1032	* APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
Kojto	122:f9eeca106725	1033	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1034	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto	122:f9eeca106725	1035	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto	122:f9eeca106725	1036	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto	122:f9eeca106725	1037	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto	122:f9eeca106725	1038	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto	122:f9eeca106725	1039	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto	122:f9eeca106725	1040	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto	122:f9eeca106725	1041	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
Kojto	122:f9eeca106725	1042	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
Kojto	122:f9eeca106725	1043	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto	122:f9eeca106725	1044	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto	122:f9eeca106725	1045	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto	122:f9eeca106725	1046	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto	122:f9eeca106725	1047	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto	122:f9eeca106725	1048	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto	122:f9eeca106725	1049	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto	122:f9eeca106725	1050	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto	122:f9eeca106725	1051	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto	122:f9eeca106725	1052	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto	122:f9eeca106725	1053	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
Kojto	122:f9eeca106725	1054	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto	122:f9eeca106725	1055	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto	122:f9eeca106725	1056	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto	122:f9eeca106725	1057	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto	122:f9eeca106725	1058	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto	122:f9eeca106725	1059	*
Kojto	122:f9eeca106725	1060	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1061	* @retval None
Kojto	122:f9eeca106725	1062	*/
Kojto	122:f9eeca106725	1063	__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
Kojto	122:f9eeca106725	1064	{
Kojto	122:f9eeca106725	1065	CLEAR_BIT(RCC->APB1ENR1, Periphs);
Kojto	122:f9eeca106725	1066	}
Kojto	122:f9eeca106725	1067
Kojto	122:f9eeca106725	1068	/**
Kojto	122:f9eeca106725	1069	* @brief Disable APB1 peripherals clock.
Kojto	122:f9eeca106725	1070	* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
Kojto	122:f9eeca106725	1071	* APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n
Kojto	122:f9eeca106725	1072	* APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
Kojto	122:f9eeca106725	1073	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1074	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
Kojto	122:f9eeca106725	1075	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
Kojto	122:f9eeca106725	1076	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
Kojto	122:f9eeca106725	1077	* @retval None
Kojto	122:f9eeca106725	1078	*/
Kojto	122:f9eeca106725	1079	__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
Kojto	122:f9eeca106725	1080	{
Kojto	122:f9eeca106725	1081	CLEAR_BIT(RCC->APB1ENR2, Periphs);
Kojto	122:f9eeca106725	1082	}
Kojto	122:f9eeca106725	1083
Kojto	122:f9eeca106725	1084	/**
Kojto	122:f9eeca106725	1085	* @brief Force APB1 peripherals reset.
Kojto	122:f9eeca106725	1086	* @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1087	* APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1088	* APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1089	* APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1090	* APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1091	* APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1092	* APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1093	* APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1094	* APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1095	* APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1096	* APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1097	* APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1098	* APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1099	* APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1100	* APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1101	* APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1102	* APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1103	* APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1104	* APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1105	* APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1106	* APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1107	* APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
Kojto	122:f9eeca106725	1108	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1109	* @arg @ref LL_APB1_GRP1_PERIPH_ALL
Kojto	122:f9eeca106725	1110	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto	122:f9eeca106725	1111	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto	122:f9eeca106725	1112	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto	122:f9eeca106725	1113	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto	122:f9eeca106725	1114	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto	122:f9eeca106725	1115	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto	122:f9eeca106725	1116	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto	122:f9eeca106725	1117	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto	122:f9eeca106725	1118	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto	122:f9eeca106725	1119	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto	122:f9eeca106725	1120	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto	122:f9eeca106725	1121	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto	122:f9eeca106725	1122	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto	122:f9eeca106725	1123	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto	122:f9eeca106725	1124	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto	122:f9eeca106725	1125	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto	122:f9eeca106725	1126	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto	122:f9eeca106725	1127	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
Kojto	122:f9eeca106725	1128	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto	122:f9eeca106725	1129	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto	122:f9eeca106725	1130	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto	122:f9eeca106725	1131	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto	122:f9eeca106725	1132	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto	122:f9eeca106725	1133	*
Kojto	122:f9eeca106725	1134	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1135	* @retval None
Kojto	122:f9eeca106725	1136	*/
Kojto	122:f9eeca106725	1137	__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
Kojto	122:f9eeca106725	1138	{
Kojto	122:f9eeca106725	1139	SET_BIT(RCC->APB1RSTR1, Periphs);
Kojto	122:f9eeca106725	1140	}
Kojto	122:f9eeca106725	1141
Kojto	122:f9eeca106725	1142	/**
Kojto	122:f9eeca106725	1143	* @brief Force APB1 peripherals reset.
Kojto	122:f9eeca106725	1144	* @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
Kojto	122:f9eeca106725	1145	* APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n
Kojto	122:f9eeca106725	1146	* APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
Kojto	122:f9eeca106725	1147	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1148	* @arg @ref LL_APB1_GRP2_PERIPH_ALL
Kojto	122:f9eeca106725	1149	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
Kojto	122:f9eeca106725	1150	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
Kojto	122:f9eeca106725	1151	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
Kojto	122:f9eeca106725	1152	* @retval None
Kojto	122:f9eeca106725	1153	*/
Kojto	122:f9eeca106725	1154	__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
Kojto	122:f9eeca106725	1155	{
Kojto	122:f9eeca106725	1156	SET_BIT(RCC->APB1RSTR2, Periphs);
Kojto	122:f9eeca106725	1157	}
Kojto	122:f9eeca106725	1158
Kojto	122:f9eeca106725	1159	/**
Kojto	122:f9eeca106725	1160	* @brief Release APB1 peripherals reset.
Kojto	122:f9eeca106725	1161	* @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1162	* APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1163	* APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1164	* APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1165	* APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1166	* APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1167	* APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1168	* APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1169	* APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1170	* APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1171	* APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1172	* APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1173	* APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1174	* APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1175	* APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1176	* APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1177	* APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1178	* APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1179	* APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1180	* APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1181	* APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1182	* APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
Kojto	122:f9eeca106725	1183	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1184	* @arg @ref LL_APB1_GRP1_PERIPH_ALL
Kojto	122:f9eeca106725	1185	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto	122:f9eeca106725	1186	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto	122:f9eeca106725	1187	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto	122:f9eeca106725	1188	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto	122:f9eeca106725	1189	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto	122:f9eeca106725	1190	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto	122:f9eeca106725	1191	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto	122:f9eeca106725	1192	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto	122:f9eeca106725	1193	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto	122:f9eeca106725	1194	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto	122:f9eeca106725	1195	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto	122:f9eeca106725	1196	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto	122:f9eeca106725	1197	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto	122:f9eeca106725	1198	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto	122:f9eeca106725	1199	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto	122:f9eeca106725	1200	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto	122:f9eeca106725	1201	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto	122:f9eeca106725	1202	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
Kojto	122:f9eeca106725	1203	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto	122:f9eeca106725	1204	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto	122:f9eeca106725	1205	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto	122:f9eeca106725	1206	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto	122:f9eeca106725	1207	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto	122:f9eeca106725	1208	*
Kojto	122:f9eeca106725	1209	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1210	* @retval None
Kojto	122:f9eeca106725	1211	*/
Kojto	122:f9eeca106725	1212	__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
Kojto	122:f9eeca106725	1213	{
Kojto	122:f9eeca106725	1214	CLEAR_BIT(RCC->APB1RSTR1, Periphs);
Kojto	122:f9eeca106725	1215	}
Kojto	122:f9eeca106725	1216
Kojto	122:f9eeca106725	1217	/**
Kojto	122:f9eeca106725	1218	* @brief Release APB1 peripherals reset.
Kojto	122:f9eeca106725	1219	* @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
Kojto	122:f9eeca106725	1220	* APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n
Kojto	122:f9eeca106725	1221	* APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
Kojto	122:f9eeca106725	1222	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1223	* @arg @ref LL_APB1_GRP2_PERIPH_ALL
Kojto	122:f9eeca106725	1224	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
Kojto	122:f9eeca106725	1225	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
Kojto	122:f9eeca106725	1226	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
Kojto	122:f9eeca106725	1227	* @retval None
Kojto	122:f9eeca106725	1228	*/
Kojto	122:f9eeca106725	1229	__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
Kojto	122:f9eeca106725	1230	{
Kojto	122:f9eeca106725	1231	CLEAR_BIT(RCC->APB1RSTR2, Periphs);
Kojto	122:f9eeca106725	1232	}
Kojto	122:f9eeca106725	1233
Kojto	122:f9eeca106725	1234	/**
Kojto	122:f9eeca106725	1235	* @brief Enable APB1 peripheral clocks in Sleep and Stop modes
Kojto	122:f9eeca106725	1236	* @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1237	* APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1238	* APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1239	* APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1240	* APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1241	* APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1242	* APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1243	* APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1244	* APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1245	* APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1246	* APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1247	* APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1248	* APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1249	* APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1250	* APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1251	* APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1252	* APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1253	* APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1254	* APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1255	* APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1256	* APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1257	* APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1258	* APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1259	* APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
Kojto	122:f9eeca106725	1260	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1261	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto	122:f9eeca106725	1262	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto	122:f9eeca106725	1263	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto	122:f9eeca106725	1264	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto	122:f9eeca106725	1265	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto	122:f9eeca106725	1266	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto	122:f9eeca106725	1267	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto	122:f9eeca106725	1268	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
Kojto	122:f9eeca106725	1269	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
Kojto	122:f9eeca106725	1270	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto	122:f9eeca106725	1271	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto	122:f9eeca106725	1272	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto	122:f9eeca106725	1273	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto	122:f9eeca106725	1274	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto	122:f9eeca106725	1275	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto	122:f9eeca106725	1276	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto	122:f9eeca106725	1277	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto	122:f9eeca106725	1278	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto	122:f9eeca106725	1279	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto	122:f9eeca106725	1280	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
Kojto	122:f9eeca106725	1281	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto	122:f9eeca106725	1282	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto	122:f9eeca106725	1283	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto	122:f9eeca106725	1284	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto	122:f9eeca106725	1285	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto	122:f9eeca106725	1286	*
Kojto	122:f9eeca106725	1287	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1288	* @retval None
Kojto	122:f9eeca106725	1289	*/
Kojto	122:f9eeca106725	1290	__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
Kojto	122:f9eeca106725	1291	{
Kojto	122:f9eeca106725	1292	__IO uint32_t tmpreg;
Kojto	122:f9eeca106725	1293	SET_BIT(RCC->APB1SMENR1, Periphs);
Kojto	122:f9eeca106725	1294	/* Delay after an RCC peripheral clock enabling */
Kojto	122:f9eeca106725	1295	tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
Kojto	122:f9eeca106725	1296	(void)tmpreg;
Kojto	122:f9eeca106725	1297	}
Kojto	122:f9eeca106725	1298
Kojto	122:f9eeca106725	1299	/**
Kojto	122:f9eeca106725	1300	* @brief Enable APB1 peripheral clocks in Sleep and Stop modes
Kojto	122:f9eeca106725	1301	* @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1302	* APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1303	* APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep
Kojto	122:f9eeca106725	1304	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1305	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
Kojto	122:f9eeca106725	1306	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
Kojto	122:f9eeca106725	1307	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
Kojto	122:f9eeca106725	1308	* @retval None
Kojto	122:f9eeca106725	1309	*/
Kojto	122:f9eeca106725	1310	__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
Kojto	122:f9eeca106725	1311	{
Kojto	122:f9eeca106725	1312	__IO uint32_t tmpreg;
Kojto	122:f9eeca106725	1313	SET_BIT(RCC->APB1SMENR2, Periphs);
Kojto	122:f9eeca106725	1314	/* Delay after an RCC peripheral clock enabling */
Kojto	122:f9eeca106725	1315	tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
Kojto	122:f9eeca106725	1316	(void)tmpreg;
Kojto	122:f9eeca106725	1317	}
Kojto	122:f9eeca106725	1318
Kojto	122:f9eeca106725	1319	/**
Kojto	122:f9eeca106725	1320	* @brief Disable APB1 peripheral clocks in Sleep and Stop modes
Kojto	122:f9eeca106725	1321	* @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1322	* APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1323	* APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1324	* APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1325	* APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1326	* APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1327	* APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1328	* APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1329	* APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1330	* APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1331	* APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1332	* APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1333	* APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1334	* APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1335	* APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1336	* APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1337	* APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1338	* APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1339	* APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1340	* APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1341	* APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1342	* APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1343	* APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1344	* APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
Kojto	122:f9eeca106725	1345	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1346	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto	122:f9eeca106725	1347	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto	122:f9eeca106725	1348	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto	122:f9eeca106725	1349	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto	122:f9eeca106725	1350	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto	122:f9eeca106725	1351	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto	122:f9eeca106725	1352	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto	122:f9eeca106725	1353	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
Kojto	122:f9eeca106725	1354	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
Kojto	122:f9eeca106725	1355	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto	122:f9eeca106725	1356	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto	122:f9eeca106725	1357	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto	122:f9eeca106725	1358	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto	122:f9eeca106725	1359	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto	122:f9eeca106725	1360	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto	122:f9eeca106725	1361	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto	122:f9eeca106725	1362	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto	122:f9eeca106725	1363	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto	122:f9eeca106725	1364	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto	122:f9eeca106725	1365	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
Kojto	122:f9eeca106725	1366	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto	122:f9eeca106725	1367	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto	122:f9eeca106725	1368	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto	122:f9eeca106725	1369	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto	122:f9eeca106725	1370	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto	122:f9eeca106725	1371	*
Kojto	122:f9eeca106725	1372	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1373	* @retval None
Kojto	122:f9eeca106725	1374	*/
Kojto	122:f9eeca106725	1375	__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
Kojto	122:f9eeca106725	1376	{
Kojto	122:f9eeca106725	1377	CLEAR_BIT(RCC->APB1SMENR1, Periphs);
Kojto	122:f9eeca106725	1378	}
Kojto	122:f9eeca106725	1379
Kojto	122:f9eeca106725	1380	/**
Kojto	122:f9eeca106725	1381	* @brief Disable APB1 peripheral clocks in Sleep and Stop modes
Kojto	122:f9eeca106725	1382	* @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1383	* APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1384	* APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep
Kojto	122:f9eeca106725	1385	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1386	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
Kojto	122:f9eeca106725	1387	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
Kojto	122:f9eeca106725	1388	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
Kojto	122:f9eeca106725	1389	* @retval None
Kojto	122:f9eeca106725	1390	*/
Kojto	122:f9eeca106725	1391	__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
Kojto	122:f9eeca106725	1392	{
Kojto	122:f9eeca106725	1393	CLEAR_BIT(RCC->APB1SMENR2, Periphs);
Kojto	122:f9eeca106725	1394	}
Kojto	122:f9eeca106725	1395
Kojto	122:f9eeca106725	1396	/**
Kojto	122:f9eeca106725	1397	* @}
Kojto	122:f9eeca106725	1398	*/
Kojto	122:f9eeca106725	1399
Kojto	122:f9eeca106725	1400	/** @defgroup BUS_LL_EF_APB2 APB2
Kojto	122:f9eeca106725	1401	* @{
Kojto	122:f9eeca106725	1402	*/
Kojto	122:f9eeca106725	1403
Kojto	122:f9eeca106725	1404	/**
Kojto	122:f9eeca106725	1405	* @brief Enable APB2 peripherals clock.
Kojto	122:f9eeca106725	1406	* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	1407	* APB2ENR FWEN LL_APB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	1408	* APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	1409	* APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	1410	* APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	1411	* APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	1412	* APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	1413	* APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	1414	* APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	1415	* APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	1416	* APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	1417	* APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
Kojto	122:f9eeca106725	1418	* APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock
Kojto	122:f9eeca106725	1419	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1420	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto	122:f9eeca106725	1421	* @arg @ref LL_APB2_GRP1_PERIPH_FW
Kojto	122:f9eeca106725	1422	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto	122:f9eeca106725	1423	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto	122:f9eeca106725	1424	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto	122:f9eeca106725	1425	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto	122:f9eeca106725	1426	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto	122:f9eeca106725	1427	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto	122:f9eeca106725	1428	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto	122:f9eeca106725	1429	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto	122:f9eeca106725	1430	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto	122:f9eeca106725	1431	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto	122:f9eeca106725	1432	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto	122:f9eeca106725	1433	*
Kojto	122:f9eeca106725	1434	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1435	* @retval None
Kojto	122:f9eeca106725	1436	*/
Kojto	122:f9eeca106725	1437	__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
Kojto	122:f9eeca106725	1438	{
Kojto	122:f9eeca106725	1439	__IO uint32_t tmpreg;
Kojto	122:f9eeca106725	1440	SET_BIT(RCC->APB2ENR, Periphs);
Kojto	122:f9eeca106725	1441	/* Delay after an RCC peripheral clock enabling */
Kojto	122:f9eeca106725	1442	tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
Kojto	122:f9eeca106725	1443	(void)tmpreg;
Kojto	122:f9eeca106725	1444	}
Kojto	122:f9eeca106725	1445
Kojto	122:f9eeca106725	1446	/**
Kojto	122:f9eeca106725	1447	* @brief Check if APB2 peripheral clock is enabled or not
Kojto	122:f9eeca106725	1448	* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	1449	* APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	1450	* APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	1451	* APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	1452	* APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	1453	* APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	1454	* APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	1455	* APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	1456	* APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	1457	* APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	1458	* APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	1459	* APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
Kojto	122:f9eeca106725	1460	* APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock
Kojto	122:f9eeca106725	1461	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1462	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto	122:f9eeca106725	1463	* @arg @ref LL_APB2_GRP1_PERIPH_FW
Kojto	122:f9eeca106725	1464	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto	122:f9eeca106725	1465	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto	122:f9eeca106725	1466	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto	122:f9eeca106725	1467	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto	122:f9eeca106725	1468	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto	122:f9eeca106725	1469	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto	122:f9eeca106725	1470	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto	122:f9eeca106725	1471	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto	122:f9eeca106725	1472	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto	122:f9eeca106725	1473	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto	122:f9eeca106725	1474	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto	122:f9eeca106725	1475	*
Kojto	122:f9eeca106725	1476	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1477	* @retval State of Periphs (1 or 0).
Kojto	122:f9eeca106725	1478	*/
Kojto	122:f9eeca106725	1479	__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
Kojto	122:f9eeca106725	1480	{
Kojto	122:f9eeca106725	1481	return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
Kojto	122:f9eeca106725	1482	}
Kojto	122:f9eeca106725	1483
Kojto	122:f9eeca106725	1484	/**
Kojto	122:f9eeca106725	1485	* @brief Disable APB2 peripherals clock.
Kojto	122:f9eeca106725	1486	* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1487	* APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1488	* APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1489	* APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1490	* APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1491	* APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1492	* APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1493	* APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1494	* APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1495	* APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1496	* APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
Kojto	122:f9eeca106725	1497	* APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock
Kojto	122:f9eeca106725	1498	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1499	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto	122:f9eeca106725	1500	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto	122:f9eeca106725	1501	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto	122:f9eeca106725	1502	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto	122:f9eeca106725	1503	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto	122:f9eeca106725	1504	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto	122:f9eeca106725	1505	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto	122:f9eeca106725	1506	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto	122:f9eeca106725	1507	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto	122:f9eeca106725	1508	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto	122:f9eeca106725	1509	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto	122:f9eeca106725	1510	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto	122:f9eeca106725	1511	*
Kojto	122:f9eeca106725	1512	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1513	* @retval None
Kojto	122:f9eeca106725	1514	*/
Kojto	122:f9eeca106725	1515	__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
Kojto	122:f9eeca106725	1516	{
Kojto	122:f9eeca106725	1517	CLEAR_BIT(RCC->APB2ENR, Periphs);
Kojto	122:f9eeca106725	1518	}
Kojto	122:f9eeca106725	1519
Kojto	122:f9eeca106725	1520	/**
Kojto	122:f9eeca106725	1521	* @brief Force APB2 peripherals reset.
Kojto	122:f9eeca106725	1522	* @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1523	* APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1524	* APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1525	* APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1526	* APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1527	* APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1528	* APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1529	* APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1530	* APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1531	* APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1532	* APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
Kojto	122:f9eeca106725	1533	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset
Kojto	122:f9eeca106725	1534	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1535	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
Kojto	122:f9eeca106725	1536	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto	122:f9eeca106725	1537	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto	122:f9eeca106725	1538	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto	122:f9eeca106725	1539	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto	122:f9eeca106725	1540	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto	122:f9eeca106725	1541	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto	122:f9eeca106725	1542	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto	122:f9eeca106725	1543	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto	122:f9eeca106725	1544	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto	122:f9eeca106725	1545	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto	122:f9eeca106725	1546	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto	122:f9eeca106725	1547	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto	122:f9eeca106725	1548	*
Kojto	122:f9eeca106725	1549	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1550	* @retval None
Kojto	122:f9eeca106725	1551	*/
Kojto	122:f9eeca106725	1552	__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
Kojto	122:f9eeca106725	1553	{
Kojto	122:f9eeca106725	1554	SET_BIT(RCC->APB2RSTR, Periphs);
Kojto	122:f9eeca106725	1555	}
Kojto	122:f9eeca106725	1556
Kojto	122:f9eeca106725	1557	/**
Kojto	122:f9eeca106725	1558	* @brief Release APB2 peripherals reset.
Kojto	122:f9eeca106725	1559	* @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1560	* APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1561	* APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1562	* APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1563	* APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1564	* APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1565	* APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1566	* APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1567	* APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1568	* APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1569	* APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
Kojto	122:f9eeca106725	1570	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset
Kojto	122:f9eeca106725	1571	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1572	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
Kojto	122:f9eeca106725	1573	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto	122:f9eeca106725	1574	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto	122:f9eeca106725	1575	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto	122:f9eeca106725	1576	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto	122:f9eeca106725	1577	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto	122:f9eeca106725	1578	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto	122:f9eeca106725	1579	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto	122:f9eeca106725	1580	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto	122:f9eeca106725	1581	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto	122:f9eeca106725	1582	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto	122:f9eeca106725	1583	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto	122:f9eeca106725	1584	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto	122:f9eeca106725	1585	*
Kojto	122:f9eeca106725	1586	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1587	* @retval None
Kojto	122:f9eeca106725	1588	*/
Kojto	122:f9eeca106725	1589	__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
Kojto	122:f9eeca106725	1590	{
Kojto	122:f9eeca106725	1591	CLEAR_BIT(RCC->APB2RSTR, Periphs);
Kojto	122:f9eeca106725	1592	}
Kojto	122:f9eeca106725	1593
Kojto	122:f9eeca106725	1594	/**
Kojto	122:f9eeca106725	1595	* @brief Enable APB2 peripheral clocks in Sleep and Stop modes
Kojto	122:f9eeca106725	1596	* @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1597	* APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1598	* APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1599	* APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1600	* APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1601	* APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1602	* APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1603	* APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1604	* APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1605	* APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1606	* APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto	122:f9eeca106725	1607	* APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep
Kojto	122:f9eeca106725	1608	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1609	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto	122:f9eeca106725	1610	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto	122:f9eeca106725	1611	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto	122:f9eeca106725	1612	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto	122:f9eeca106725	1613	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto	122:f9eeca106725	1614	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto	122:f9eeca106725	1615	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto	122:f9eeca106725	1616	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto	122:f9eeca106725	1617	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto	122:f9eeca106725	1618	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto	122:f9eeca106725	1619	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto	122:f9eeca106725	1620	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto	122:f9eeca106725	1621	*
Kojto	122:f9eeca106725	1622	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1623	* @retval None
Kojto	122:f9eeca106725	1624	*/
Kojto	122:f9eeca106725	1625	__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
Kojto	122:f9eeca106725	1626	{
Kojto	122:f9eeca106725	1627	__IO uint32_t tmpreg;
Kojto	122:f9eeca106725	1628	SET_BIT(RCC->APB2SMENR, Periphs);
Kojto	122:f9eeca106725	1629	/* Delay after an RCC peripheral clock enabling */
Kojto	122:f9eeca106725	1630	tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
Kojto	122:f9eeca106725	1631	(void)tmpreg;
Kojto	122:f9eeca106725	1632	}
Kojto	122:f9eeca106725	1633
Kojto	122:f9eeca106725	1634	/**
Kojto	122:f9eeca106725	1635	* @brief Disable APB2 peripheral clocks in Sleep and Stop modes
Kojto	122:f9eeca106725	1636	* @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1637	* APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1638	* APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1639	* APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1640	* APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1641	* APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1642	* APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1643	* APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1644	* APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1645	* APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1646	* APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto	122:f9eeca106725	1647	* APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep
Kojto	122:f9eeca106725	1648	* @param Periphs This parameter can be a combination of the following values:
Kojto	122:f9eeca106725	1649	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto	122:f9eeca106725	1650	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto	122:f9eeca106725	1651	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto	122:f9eeca106725	1652	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto	122:f9eeca106725	1653	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto	122:f9eeca106725	1654	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto	122:f9eeca106725	1655	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto	122:f9eeca106725	1656	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto	122:f9eeca106725	1657	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto	122:f9eeca106725	1658	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto	122:f9eeca106725	1659	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto	122:f9eeca106725	1660	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto	122:f9eeca106725	1661	*
Kojto	122:f9eeca106725	1662	* (*) value not defined in all devices.
Kojto	122:f9eeca106725	1663	* @retval None
Kojto	122:f9eeca106725	1664	*/
Kojto	122:f9eeca106725	1665	__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
Kojto	122:f9eeca106725	1666	{
Kojto	122:f9eeca106725	1667	CLEAR_BIT(RCC->APB2SMENR, Periphs);
Kojto	122:f9eeca106725	1668	}
Kojto	122:f9eeca106725	1669
Kojto	122:f9eeca106725	1670	/**
Kojto	122:f9eeca106725	1671	* @}
Kojto	122:f9eeca106725	1672	*/
Kojto	122:f9eeca106725	1673
Kojto	122:f9eeca106725	1674
Kojto	122:f9eeca106725	1675	/**
Kojto	122:f9eeca106725	1676	* @}
Kojto	122:f9eeca106725	1677	*/
Kojto	122:f9eeca106725	1678
Kojto	122:f9eeca106725	1679	/**
Kojto	122:f9eeca106725	1680	* @}
Kojto	122:f9eeca106725	1681	*/
Kojto	122:f9eeca106725	1682
Kojto	122:f9eeca106725	1683	#endif /* defined(RCC) */
Kojto	122:f9eeca106725	1684
Kojto	122:f9eeca106725	1685	/**
Kojto	122:f9eeca106725	1686	* @}
Kojto	122:f9eeca106725	1687	*/
Kojto	122:f9eeca106725	1688
Kojto	122:f9eeca106725	1689	#ifdef __cplusplus
Kojto	122:f9eeca106725	1690	}
Kojto	122:f9eeca106725	1691	#endif
Kojto	122:f9eeca106725	1692
Kojto	122:f9eeca106725	1693	#endif /* __STM32L4xx_LL_BUS_H */
Kojto	122:f9eeca106725	1694
Kojto	122:f9eeca106725	1695	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/