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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h@145:64910690c574, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:31:38 2017 +0100
Revision:
145:64910690c574
Parent:
128:9bcdf88f62b0 
Release 145 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**
Kojto 122:f9eeca106725 2 ******************************************************************************
Kojto 122:f9eeca106725 3 * @file stm32l4xx_ll_bus.h
Kojto 122:f9eeca106725 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @version V1.7.1
AnnaBridge 145:64910690c574 6 * @date 21-April-2017
Kojto 122:f9eeca106725 7 * @brief Header file of BUS LL module.
Kojto 122:f9eeca106725 8
Kojto 122:f9eeca106725 9 @verbatim
Kojto 122:f9eeca106725 10 ##### RCC Limitations #####
Kojto 122:f9eeca106725 11 ==============================================================================
Kojto 122:f9eeca106725 12 [..]
Kojto 122:f9eeca106725 13 A delay between an RCC peripheral clock enable and the effective peripheral
Kojto 122:f9eeca106725 14 enabling should be taken into account in order to manage the peripheral read/write
Kojto 122:f9eeca106725 15 from/to registers.
Kojto 122:f9eeca106725 16 (+) This delay depends on the peripheral mapping.
Kojto 122:f9eeca106725 17 (++) AHB & APB peripherals, 1 dummy read is necessary
Kojto 122:f9eeca106725 18
Kojto 122:f9eeca106725 19 [..]
Kojto 122:f9eeca106725 20 Workarounds:
Kojto 122:f9eeca106725 21 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
Kojto 122:f9eeca106725 22 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
Kojto 122:f9eeca106725 23
Kojto 122:f9eeca106725 24 @endverbatim
Kojto 122:f9eeca106725 25 ******************************************************************************
Kojto 122:f9eeca106725 26 * @attention
Kojto 122:f9eeca106725 27 *
AnnaBridge 145:64910690c574 28 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
Kojto 122:f9eeca106725 29 *
Kojto 122:f9eeca106725 30 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 31 * are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 32 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 122:f9eeca106725 33 * this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 34 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 122:f9eeca106725 35 * this list of conditions and the following disclaimer in the documentation
Kojto 122:f9eeca106725 36 * and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 122:f9eeca106725 38 * may be used to endorse or promote products derived from this software
Kojto 122:f9eeca106725 39 * without specific prior written permission.
Kojto 122:f9eeca106725 40 *
Kojto 122:f9eeca106725 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 122:f9eeca106725 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 122:f9eeca106725 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 122:f9eeca106725 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 122:f9eeca106725 48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 122:f9eeca106725 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 122:f9eeca106725 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 51 *
Kojto 122:f9eeca106725 52 ******************************************************************************
Kojto 122:f9eeca106725 53 */
Kojto 122:f9eeca106725 54
Kojto 122:f9eeca106725 55 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 122:f9eeca106725 56 #ifndef __STM32L4xx_LL_BUS_H
Kojto 122:f9eeca106725 57 #define __STM32L4xx_LL_BUS_H
Kojto 122:f9eeca106725 58
Kojto 122:f9eeca106725 59 #ifdef __cplusplus
Kojto 122:f9eeca106725 60 extern "C" {
Kojto 122:f9eeca106725 61 #endif
Kojto 122:f9eeca106725 62
Kojto 122:f9eeca106725 63 /* Includes ------------------------------------------------------------------*/
Kojto 122:f9eeca106725 64 #include "stm32l4xx.h"
Kojto 122:f9eeca106725 65
Kojto 122:f9eeca106725 66 /** @addtogroup STM32L4xx_LL_Driver
Kojto 122:f9eeca106725 67 * @{
Kojto 122:f9eeca106725 68 */
Kojto 122:f9eeca106725 69
Kojto 122:f9eeca106725 70 #if defined(RCC)
Kojto 122:f9eeca106725 71
Kojto 122:f9eeca106725 72 /** @defgroup BUS_LL BUS
Kojto 122:f9eeca106725 73 * @{
Kojto 122:f9eeca106725 74 */
Kojto 122:f9eeca106725 75
Kojto 122:f9eeca106725 76 /* Private types -------------------------------------------------------------*/
Kojto 122:f9eeca106725 77 /* Private variables ---------------------------------------------------------*/
Kojto 122:f9eeca106725 78
Kojto 122:f9eeca106725 79 /* Private constants ---------------------------------------------------------*/
Kojto 122:f9eeca106725 80
Kojto 122:f9eeca106725 81 /* Private macros ------------------------------------------------------------*/
Kojto 122:f9eeca106725 82
Kojto 122:f9eeca106725 83 /* Exported types ------------------------------------------------------------*/
Kojto 122:f9eeca106725 84 /* Exported constants --------------------------------------------------------*/
Kojto 122:f9eeca106725 85 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
Kojto 122:f9eeca106725 86 * @{
Kojto 122:f9eeca106725 87 */
Kojto 122:f9eeca106725 88
Kojto 122:f9eeca106725 89 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
Kojto 122:f9eeca106725 90 * @{
Kojto 122:f9eeca106725 91 */
AnnaBridge 145:64910690c574 92 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
Kojto 122:f9eeca106725 93 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
Kojto 122:f9eeca106725 94 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
Kojto 122:f9eeca106725 95 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
Kojto 122:f9eeca106725 96 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
Kojto 122:f9eeca106725 97 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
AnnaBridge 145:64910690c574 98 #if defined(DMA2D)
AnnaBridge 145:64910690c574 99 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
AnnaBridge 145:64910690c574 100 #endif /* DMA2D */
Kojto 122:f9eeca106725 101 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
Kojto 122:f9eeca106725 102 /**
Kojto 122:f9eeca106725 103 * @}
Kojto 122:f9eeca106725 104 */
Kojto 122:f9eeca106725 105
Kojto 122:f9eeca106725 106 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
Kojto 122:f9eeca106725 107 * @{
Kojto 122:f9eeca106725 108 */
AnnaBridge 145:64910690c574 109 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
Kojto 122:f9eeca106725 110 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
Kojto 122:f9eeca106725 111 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
Kojto 122:f9eeca106725 112 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
Kojto 122:f9eeca106725 113 #if defined(GPIOD)
Kojto 122:f9eeca106725 114 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
Kojto 122:f9eeca106725 115 #endif /*GPIOD*/
Kojto 122:f9eeca106725 116 #if defined(GPIOE)
Kojto 122:f9eeca106725 117 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
Kojto 122:f9eeca106725 118 #endif /*GPIOE*/
Kojto 122:f9eeca106725 119 #if defined(GPIOF)
Kojto 122:f9eeca106725 120 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
Kojto 122:f9eeca106725 121 #endif /* GPIOF */
Kojto 122:f9eeca106725 122 #if defined(GPIOG)
Kojto 122:f9eeca106725 123 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
Kojto 122:f9eeca106725 124 #endif /* GPIOG */
Kojto 122:f9eeca106725 125 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
AnnaBridge 145:64910690c574 126 #if defined(GPIOI)
AnnaBridge 145:64910690c574 127 #define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN
AnnaBridge 145:64910690c574 128 #endif /* GPIOI */
Kojto 122:f9eeca106725 129 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 130 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
Kojto 122:f9eeca106725 131 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 132 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
AnnaBridge 145:64910690c574 133 #if defined(DCMI)
AnnaBridge 145:64910690c574 134 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
AnnaBridge 145:64910690c574 135 #endif /* DCMI */
Kojto 122:f9eeca106725 136 #if defined(AES)
Kojto 122:f9eeca106725 137 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
Kojto 122:f9eeca106725 138 #endif /* AES */
AnnaBridge 145:64910690c574 139 #if defined(HASH)
AnnaBridge 145:64910690c574 140 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
AnnaBridge 145:64910690c574 141 #endif /* HASH */
Kojto 122:f9eeca106725 142 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
AnnaBridge 145:64910690c574 143 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
Kojto 122:f9eeca106725 144 /**
Kojto 122:f9eeca106725 145 * @}
Kojto 122:f9eeca106725 146 */
Kojto 122:f9eeca106725 147
Kojto 122:f9eeca106725 148 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
Kojto 122:f9eeca106725 149 * @{
Kojto 122:f9eeca106725 150 */
AnnaBridge 145:64910690c574 151 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
Kojto 122:f9eeca106725 152 #if defined(FMC_Bank1_R)
Kojto 122:f9eeca106725 153 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
Kojto 122:f9eeca106725 154 #endif /* FMC_Bank1_R */
Kojto 122:f9eeca106725 155 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
Kojto 122:f9eeca106725 156 /**
Kojto 122:f9eeca106725 157 * @}
Kojto 122:f9eeca106725 158 */
Kojto 122:f9eeca106725 159
Kojto 122:f9eeca106725 160 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
Kojto 122:f9eeca106725 161 * @{
Kojto 122:f9eeca106725 162 */
AnnaBridge 145:64910690c574 163 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
Kojto 122:f9eeca106725 164 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
Kojto 122:f9eeca106725 165 #if defined(TIM3)
Kojto 122:f9eeca106725 166 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
Kojto 122:f9eeca106725 167 #endif /* TIM3 */
Kojto 122:f9eeca106725 168 #if defined(TIM4)
Kojto 122:f9eeca106725 169 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
Kojto 122:f9eeca106725 170 #endif /* TIM4 */
Kojto 122:f9eeca106725 171 #if defined(TIM5)
Kojto 122:f9eeca106725 172 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
Kojto 122:f9eeca106725 173 #endif /* TIM5 */
Kojto 122:f9eeca106725 174 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
Kojto 122:f9eeca106725 175 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
Kojto 122:f9eeca106725 176 #if defined(LCD)
Kojto 122:f9eeca106725 177 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
Kojto 122:f9eeca106725 178 #endif /* LCD */
Kojto 122:f9eeca106725 179 #if defined(RCC_APB1ENR1_RTCAPBEN)
Kojto 122:f9eeca106725 180 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
Kojto 122:f9eeca106725 181 #endif /* RCC_APB1ENR1_RTCAPBEN */
Kojto 122:f9eeca106725 182 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
Kojto 122:f9eeca106725 183 #if defined(SPI2)
Kojto 122:f9eeca106725 184 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
Kojto 122:f9eeca106725 185 #endif /* SPI2 */
Kojto 122:f9eeca106725 186 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
Kojto 122:f9eeca106725 187 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
Kojto 122:f9eeca106725 188 #if defined(USART3)
Kojto 122:f9eeca106725 189 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
Kojto 122:f9eeca106725 190 #endif /* USART3 */
Kojto 122:f9eeca106725 191 #if defined(UART4)
Kojto 122:f9eeca106725 192 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
Kojto 122:f9eeca106725 193 #endif /* UART4 */
Kojto 122:f9eeca106725 194 #if defined(UART5)
Kojto 122:f9eeca106725 195 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
Kojto 122:f9eeca106725 196 #endif /* UART5 */
Kojto 122:f9eeca106725 197 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
Kojto 122:f9eeca106725 198 #if defined(I2C2)
Kojto 122:f9eeca106725 199 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
Kojto 122:f9eeca106725 200 #endif /* I2C2 */
Kojto 122:f9eeca106725 201 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
Kojto 122:f9eeca106725 202 #if defined(CRS)
Kojto 122:f9eeca106725 203 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
Kojto 122:f9eeca106725 204 #endif /* CRS */
Kojto 122:f9eeca106725 205 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN
AnnaBridge 145:64910690c574 206 #if defined(CAN2)
AnnaBridge 145:64910690c574 207 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR1_CAN2EN
AnnaBridge 145:64910690c574 208 #endif /* CAN2 */
Kojto 122:f9eeca106725 209 #if defined(USB)
Kojto 122:f9eeca106725 210 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN
Kojto 122:f9eeca106725 211 #endif /* USB */
Kojto 122:f9eeca106725 212 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
Kojto 122:f9eeca106725 213 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN
Kojto 122:f9eeca106725 214 #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN
Kojto 122:f9eeca106725 215 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
Kojto 122:f9eeca106725 216 /**
Kojto 122:f9eeca106725 217 * @}
Kojto 122:f9eeca106725 218 */
Kojto 122:f9eeca106725 219
Kojto 122:f9eeca106725 220
Kojto 122:f9eeca106725 221 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
Kojto 122:f9eeca106725 222 * @{
Kojto 122:f9eeca106725 223 */
AnnaBridge 145:64910690c574 224 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
Kojto 122:f9eeca106725 225 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
AnnaBridge 145:64910690c574 226 #if defined(I2C4)
AnnaBridge 145:64910690c574 227 #define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
AnnaBridge 145:64910690c574 228 #endif /* I2C4 */
AnnaBridge 145:64910690c574 229 #if defined(SWPMI1)
Kojto 122:f9eeca106725 230 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN
AnnaBridge 145:64910690c574 231 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 232 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
Kojto 122:f9eeca106725 233 /**
Kojto 122:f9eeca106725 234 * @}
Kojto 122:f9eeca106725 235 */
Kojto 122:f9eeca106725 236
Kojto 122:f9eeca106725 237 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
Kojto 122:f9eeca106725 238 * @{
Kojto 122:f9eeca106725 239 */
AnnaBridge 145:64910690c574 240 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
Kojto 122:f9eeca106725 241 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
Kojto 122:f9eeca106725 242 #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN
Kojto 122:f9eeca106725 243 #if defined(SDMMC1)
Kojto 122:f9eeca106725 244 #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
Kojto 122:f9eeca106725 245 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 246 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
Kojto 122:f9eeca106725 247 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
Kojto 122:f9eeca106725 248 #if defined(TIM8)
Kojto 122:f9eeca106725 249 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
Kojto 122:f9eeca106725 250 #endif /* TIM8 */
Kojto 122:f9eeca106725 251 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
Kojto 122:f9eeca106725 252 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
Kojto 122:f9eeca106725 253 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
Kojto 122:f9eeca106725 254 #if defined(TIM17)
Kojto 122:f9eeca106725 255 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
Kojto 122:f9eeca106725 256 #endif /* TIM17 */
Kojto 122:f9eeca106725 257 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
Kojto 122:f9eeca106725 258 #if defined(SAI2)
Kojto 122:f9eeca106725 259 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
Kojto 122:f9eeca106725 260 #endif /* SAI2 */
Kojto 122:f9eeca106725 261 #if defined(DFSDM1_Channel0)
Kojto 122:f9eeca106725 262 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
Kojto 122:f9eeca106725 263 #endif /* DFSDM1_Channel0 */
Kojto 122:f9eeca106725 264 /**
Kojto 122:f9eeca106725 265 * @}
Kojto 122:f9eeca106725 266 */
Kojto 122:f9eeca106725 267
Kojto 122:f9eeca106725 268 /** Legacy definitions for compatibility purpose
Kojto 122:f9eeca106725 269 @cond 0
Kojto 122:f9eeca106725 270 */
Kojto 122:f9eeca106725 271 #if defined(DFSDM1_Channel0)
Kojto 122:f9eeca106725 272 #define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1
Kojto 122:f9eeca106725 273 #endif /* DFSDM1_Channel0 */
Kojto 122:f9eeca106725 274 /**
Kojto 122:f9eeca106725 275 @endcond
Kojto 122:f9eeca106725 276 */
Kojto 122:f9eeca106725 277
Kojto 122:f9eeca106725 278 /**
Kojto 122:f9eeca106725 279 * @}
Kojto 122:f9eeca106725 280 */
Kojto 122:f9eeca106725 281
Kojto 122:f9eeca106725 282 /* Exported macro ------------------------------------------------------------*/
Kojto 122:f9eeca106725 283 /* Exported functions --------------------------------------------------------*/
Kojto 122:f9eeca106725 284 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
Kojto 122:f9eeca106725 285 * @{
Kojto 122:f9eeca106725 286 */
Kojto 122:f9eeca106725 287
Kojto 122:f9eeca106725 288 /** @defgroup BUS_LL_EF_AHB1 AHB1
Kojto 122:f9eeca106725 289 * @{
Kojto 122:f9eeca106725 290 */
Kojto 122:f9eeca106725 291
Kojto 122:f9eeca106725 292 /**
Kojto 122:f9eeca106725 293 * @brief Enable AHB1 peripherals clock.
Kojto 122:f9eeca106725 294 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 295 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 296 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 297 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge 145:64910690c574 298 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge 145:64910690c574 299 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock
Kojto 122:f9eeca106725 300 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 301 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto 122:f9eeca106725 302 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto 122:f9eeca106725 303 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto 122:f9eeca106725 304 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto 122:f9eeca106725 305 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge 145:64910690c574 306 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
Kojto 122:f9eeca106725 307 *
AnnaBridge 145:64910690c574 308 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 309 * @retval None
Kojto 122:f9eeca106725 310 */
Kojto 122:f9eeca106725 311 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
Kojto 122:f9eeca106725 312 {
Kojto 122:f9eeca106725 313 __IO uint32_t tmpreg;
Kojto 122:f9eeca106725 314 SET_BIT(RCC->AHB1ENR, Periphs);
Kojto 122:f9eeca106725 315 /* Delay after an RCC peripheral clock enabling */
Kojto 122:f9eeca106725 316 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
Kojto 122:f9eeca106725 317 (void)tmpreg;
Kojto 122:f9eeca106725 318 }
Kojto 122:f9eeca106725 319
Kojto 122:f9eeca106725 320 /**
Kojto 122:f9eeca106725 321 * @brief Check if AHB1 peripheral clock is enabled or not
Kojto 122:f9eeca106725 322 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 323 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 324 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 325 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge 145:64910690c574 326 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge 145:64910690c574 327 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock
Kojto 122:f9eeca106725 328 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 329 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto 122:f9eeca106725 330 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto 122:f9eeca106725 331 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto 122:f9eeca106725 332 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto 122:f9eeca106725 333 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge 145:64910690c574 334 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
Kojto 122:f9eeca106725 335 *
AnnaBridge 145:64910690c574 336 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 337 * @retval State of Periphs (1 or 0).
Kojto 122:f9eeca106725 338 */
Kojto 122:f9eeca106725 339 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
Kojto 122:f9eeca106725 340 {
Kojto 122:f9eeca106725 341 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
Kojto 122:f9eeca106725 342 }
Kojto 122:f9eeca106725 343
Kojto 122:f9eeca106725 344 /**
Kojto 122:f9eeca106725 345 * @brief Disable AHB1 peripherals clock.
Kojto 122:f9eeca106725 346 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 347 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 348 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 349 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge 145:64910690c574 350 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge 145:64910690c574 351 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock
Kojto 122:f9eeca106725 352 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 353 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto 122:f9eeca106725 354 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto 122:f9eeca106725 355 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto 122:f9eeca106725 356 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto 122:f9eeca106725 357 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge 145:64910690c574 358 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
Kojto 122:f9eeca106725 359 *
AnnaBridge 145:64910690c574 360 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 361 * @retval None
Kojto 122:f9eeca106725 362 */
Kojto 122:f9eeca106725 363 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
Kojto 122:f9eeca106725 364 {
Kojto 122:f9eeca106725 365 CLEAR_BIT(RCC->AHB1ENR, Periphs);
Kojto 122:f9eeca106725 366 }
Kojto 122:f9eeca106725 367
Kojto 122:f9eeca106725 368 /**
Kojto 122:f9eeca106725 369 * @brief Force AHB1 peripherals reset.
Kojto 122:f9eeca106725 370 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 371 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 372 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 373 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge 145:64910690c574 374 * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge 145:64910690c574 375 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset
Kojto 122:f9eeca106725 376 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 377 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
Kojto 122:f9eeca106725 378 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto 122:f9eeca106725 379 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto 122:f9eeca106725 380 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto 122:f9eeca106725 381 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto 122:f9eeca106725 382 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge 145:64910690c574 383 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
Kojto 122:f9eeca106725 384 *
AnnaBridge 145:64910690c574 385 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 386 * @retval None
Kojto 122:f9eeca106725 387 */
Kojto 122:f9eeca106725 388 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
Kojto 122:f9eeca106725 389 {
Kojto 122:f9eeca106725 390 SET_BIT(RCC->AHB1RSTR, Periphs);
Kojto 122:f9eeca106725 391 }
Kojto 122:f9eeca106725 392
Kojto 122:f9eeca106725 393 /**
Kojto 122:f9eeca106725 394 * @brief Release AHB1 peripherals reset.
Kojto 122:f9eeca106725 395 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 396 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 397 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 398 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge 145:64910690c574 399 * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge 145:64910690c574 400 * AHB1ENR DMA2DRST LL_AHB1_GRP1_ReleaseReset
Kojto 122:f9eeca106725 401 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 402 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
Kojto 122:f9eeca106725 403 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto 122:f9eeca106725 404 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto 122:f9eeca106725 405 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto 122:f9eeca106725 406 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto 122:f9eeca106725 407 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge 145:64910690c574 408 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
Kojto 122:f9eeca106725 409 *
AnnaBridge 145:64910690c574 410 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 411 * @retval None
Kojto 122:f9eeca106725 412 */
Kojto 122:f9eeca106725 413 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
Kojto 122:f9eeca106725 414 {
Kojto 122:f9eeca106725 415 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
Kojto 122:f9eeca106725 416 }
Kojto 122:f9eeca106725 417
Kojto 122:f9eeca106725 418 /**
Kojto 122:f9eeca106725 419 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
Kojto 122:f9eeca106725 420 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 421 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 422 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 423 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 424 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge 145:64910690c574 425 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge 145:64910690c574 426 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep
Kojto 122:f9eeca106725 427 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 428 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto 122:f9eeca106725 429 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto 122:f9eeca106725 430 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto 122:f9eeca106725 431 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
Kojto 122:f9eeca106725 432 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto 122:f9eeca106725 433 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge 145:64910690c574 434 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
Kojto 122:f9eeca106725 435 *
AnnaBridge 145:64910690c574 436 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 437 * @retval None
Kojto 122:f9eeca106725 438 */
Kojto 122:f9eeca106725 439 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
Kojto 122:f9eeca106725 440 {
Kojto 122:f9eeca106725 441 __IO uint32_t tmpreg;
Kojto 122:f9eeca106725 442 SET_BIT(RCC->AHB1SMENR, Periphs);
Kojto 122:f9eeca106725 443 /* Delay after an RCC peripheral clock enabling */
Kojto 122:f9eeca106725 444 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
Kojto 122:f9eeca106725 445 (void)tmpreg;
Kojto 122:f9eeca106725 446 }
Kojto 122:f9eeca106725 447
Kojto 122:f9eeca106725 448 /**
Kojto 122:f9eeca106725 449 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
Kojto 122:f9eeca106725 450 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 451 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 452 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 453 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 454 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge 145:64910690c574 455 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge 145:64910690c574 456 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep
Kojto 122:f9eeca106725 457 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 458 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
Kojto 122:f9eeca106725 459 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
Kojto 122:f9eeca106725 460 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
Kojto 122:f9eeca106725 461 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
Kojto 122:f9eeca106725 462 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
Kojto 122:f9eeca106725 463 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge 145:64910690c574 464 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
Kojto 122:f9eeca106725 465 *
AnnaBridge 145:64910690c574 466 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 467 * @retval None
Kojto 122:f9eeca106725 468 */
Kojto 122:f9eeca106725 469 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
Kojto 122:f9eeca106725 470 {
Kojto 122:f9eeca106725 471 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
Kojto 122:f9eeca106725 472 }
Kojto 122:f9eeca106725 473
Kojto 122:f9eeca106725 474 /**
Kojto 122:f9eeca106725 475 * @}
Kojto 122:f9eeca106725 476 */
Kojto 122:f9eeca106725 477
Kojto 122:f9eeca106725 478 /** @defgroup BUS_LL_EF_AHB2 AHB2
Kojto 122:f9eeca106725 479 * @{
Kojto 122:f9eeca106725 480 */
Kojto 122:f9eeca106725 481
Kojto 122:f9eeca106725 482 /**
Kojto 122:f9eeca106725 483 * @brief Enable AHB2 peripherals clock.
Kojto 122:f9eeca106725 484 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 485 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 486 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 487 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 488 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 489 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 490 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 491 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge 145:64910690c574 492 * AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 493 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 494 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge 145:64910690c574 495 * AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 496 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge 145:64910690c574 497 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 498 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
Kojto 122:f9eeca106725 499 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 500 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto 122:f9eeca106725 501 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto 122:f9eeca106725 502 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto 122:f9eeca106725 503 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto 122:f9eeca106725 504 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto 122:f9eeca106725 505 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto 122:f9eeca106725 506 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto 122:f9eeca106725 507 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge 145:64910690c574 508 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
Kojto 122:f9eeca106725 509 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto 122:f9eeca106725 510 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge 145:64910690c574 511 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
Kojto 122:f9eeca106725 512 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge 145:64910690c574 513 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
Kojto 122:f9eeca106725 514 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto 122:f9eeca106725 515 *
Kojto 122:f9eeca106725 516 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 517 * @retval None
Kojto 122:f9eeca106725 518 */
Kojto 122:f9eeca106725 519 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
Kojto 122:f9eeca106725 520 {
Kojto 122:f9eeca106725 521 __IO uint32_t tmpreg;
Kojto 122:f9eeca106725 522 SET_BIT(RCC->AHB2ENR, Periphs);
Kojto 122:f9eeca106725 523 /* Delay after an RCC peripheral clock enabling */
Kojto 122:f9eeca106725 524 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
Kojto 122:f9eeca106725 525 (void)tmpreg;
Kojto 122:f9eeca106725 526 }
Kojto 122:f9eeca106725 527
Kojto 122:f9eeca106725 528 /**
Kojto 122:f9eeca106725 529 * @brief Check if AHB2 peripheral clock is enabled or not
Kojto 122:f9eeca106725 530 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 531 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 532 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 533 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 534 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 535 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 536 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 537 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge 145:64910690c574 538 * AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 539 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 540 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge 145:64910690c574 541 * AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 542 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge 145:64910690c574 543 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 544 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
Kojto 122:f9eeca106725 545 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 546 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto 122:f9eeca106725 547 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto 122:f9eeca106725 548 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto 122:f9eeca106725 549 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto 122:f9eeca106725 550 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto 122:f9eeca106725 551 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto 122:f9eeca106725 552 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto 122:f9eeca106725 553 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge 145:64910690c574 554 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
Kojto 122:f9eeca106725 555 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto 122:f9eeca106725 556 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge 145:64910690c574 557 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
Kojto 122:f9eeca106725 558 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge 145:64910690c574 559 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
Kojto 122:f9eeca106725 560 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto 122:f9eeca106725 561 *
Kojto 122:f9eeca106725 562 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 563 * @retval State of Periphs (1 or 0).
Kojto 122:f9eeca106725 564 */
Kojto 122:f9eeca106725 565 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
Kojto 122:f9eeca106725 566 {
Kojto 122:f9eeca106725 567 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
Kojto 122:f9eeca106725 568 }
Kojto 122:f9eeca106725 569
Kojto 122:f9eeca106725 570 /**
Kojto 122:f9eeca106725 571 * @brief Disable AHB2 peripherals clock.
Kojto 122:f9eeca106725 572 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 573 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 574 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 575 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 576 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 577 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 578 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 579 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge 145:64910690c574 580 * AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 581 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 582 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge 145:64910690c574 583 * AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 584 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge 145:64910690c574 585 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 586 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
Kojto 122:f9eeca106725 587 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 588 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto 122:f9eeca106725 589 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto 122:f9eeca106725 590 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto 122:f9eeca106725 591 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto 122:f9eeca106725 592 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto 122:f9eeca106725 593 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto 122:f9eeca106725 594 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto 122:f9eeca106725 595 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge 145:64910690c574 596 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
Kojto 122:f9eeca106725 597 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto 122:f9eeca106725 598 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge 145:64910690c574 599 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
Kojto 122:f9eeca106725 600 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge 145:64910690c574 601 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
Kojto 122:f9eeca106725 602 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto 122:f9eeca106725 603 *
Kojto 122:f9eeca106725 604 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 605 * @retval None
Kojto 122:f9eeca106725 606 */
Kojto 122:f9eeca106725 607 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
Kojto 122:f9eeca106725 608 {
Kojto 122:f9eeca106725 609 CLEAR_BIT(RCC->AHB2ENR, Periphs);
Kojto 122:f9eeca106725 610 }
Kojto 122:f9eeca106725 611
Kojto 122:f9eeca106725 612 /**
Kojto 122:f9eeca106725 613 * @brief Force AHB2 peripherals reset.
Kojto 122:f9eeca106725 614 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 615 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 616 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 617 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 618 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 619 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 620 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 621 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge 145:64910690c574 622 * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 623 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 624 * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge 145:64910690c574 625 * AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 626 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge 145:64910690c574 627 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 628 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
Kojto 122:f9eeca106725 629 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 630 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
Kojto 122:f9eeca106725 631 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto 122:f9eeca106725 632 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto 122:f9eeca106725 633 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto 122:f9eeca106725 634 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto 122:f9eeca106725 635 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto 122:f9eeca106725 636 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto 122:f9eeca106725 637 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto 122:f9eeca106725 638 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge 145:64910690c574 639 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
Kojto 122:f9eeca106725 640 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto 122:f9eeca106725 641 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge 145:64910690c574 642 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
Kojto 122:f9eeca106725 643 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge 145:64910690c574 644 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
Kojto 122:f9eeca106725 645 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto 122:f9eeca106725 646 *
Kojto 122:f9eeca106725 647 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 648 * @retval None
Kojto 122:f9eeca106725 649 */
Kojto 122:f9eeca106725 650 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
Kojto 122:f9eeca106725 651 {
Kojto 122:f9eeca106725 652 SET_BIT(RCC->AHB2RSTR, Periphs);
Kojto 122:f9eeca106725 653 }
Kojto 122:f9eeca106725 654
Kojto 122:f9eeca106725 655 /**
Kojto 122:f9eeca106725 656 * @brief Release AHB2 peripherals reset.
Kojto 122:f9eeca106725 657 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 658 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 659 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 660 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 661 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 662 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 663 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 664 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge 145:64910690c574 665 * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 666 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 667 * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge 145:64910690c574 668 * AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 669 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge 145:64910690c574 670 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 671 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
Kojto 122:f9eeca106725 672 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 673 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
Kojto 122:f9eeca106725 674 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto 122:f9eeca106725 675 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto 122:f9eeca106725 676 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto 122:f9eeca106725 677 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto 122:f9eeca106725 678 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto 122:f9eeca106725 679 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto 122:f9eeca106725 680 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto 122:f9eeca106725 681 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge 145:64910690c574 682 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
Kojto 122:f9eeca106725 683 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto 122:f9eeca106725 684 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge 145:64910690c574 685 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
Kojto 122:f9eeca106725 686 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge 145:64910690c574 687 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
Kojto 122:f9eeca106725 688 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto 122:f9eeca106725 689 *
Kojto 122:f9eeca106725 690 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 691 * @retval None
Kojto 122:f9eeca106725 692 */
Kojto 122:f9eeca106725 693 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
Kojto 122:f9eeca106725 694 {
Kojto 122:f9eeca106725 695 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
Kojto 122:f9eeca106725 696 }
Kojto 122:f9eeca106725 697
Kojto 122:f9eeca106725 698 /**
Kojto 122:f9eeca106725 699 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
Kojto 122:f9eeca106725 700 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 701 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 702 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 703 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 704 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 705 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 706 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 707 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge 145:64910690c574 708 * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 709 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 710 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 711 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge 145:64910690c574 712 * AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 713 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge 145:64910690c574 714 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 715 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep
Kojto 122:f9eeca106725 716 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 717 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto 122:f9eeca106725 718 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto 122:f9eeca106725 719 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto 122:f9eeca106725 720 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto 122:f9eeca106725 721 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto 122:f9eeca106725 722 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto 122:f9eeca106725 723 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto 122:f9eeca106725 724 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge 145:64910690c574 725 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
Kojto 122:f9eeca106725 726 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
Kojto 122:f9eeca106725 727 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto 122:f9eeca106725 728 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge 145:64910690c574 729 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
Kojto 122:f9eeca106725 730 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge 145:64910690c574 731 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
Kojto 122:f9eeca106725 732 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto 122:f9eeca106725 733 *
Kojto 122:f9eeca106725 734 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 735 * @retval None
Kojto 122:f9eeca106725 736 */
Kojto 122:f9eeca106725 737 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
Kojto 122:f9eeca106725 738 {
Kojto 122:f9eeca106725 739 __IO uint32_t tmpreg;
Kojto 122:f9eeca106725 740 SET_BIT(RCC->AHB2SMENR, Periphs);
Kojto 122:f9eeca106725 741 /* Delay after an RCC peripheral clock enabling */
Kojto 122:f9eeca106725 742 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
Kojto 122:f9eeca106725 743 (void)tmpreg;
Kojto 122:f9eeca106725 744 }
Kojto 122:f9eeca106725 745
Kojto 122:f9eeca106725 746 /**
Kojto 122:f9eeca106725 747 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
Kojto 122:f9eeca106725 748 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 749 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 750 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 751 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 752 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 753 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 754 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 755 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge 145:64910690c574 756 * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 757 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 758 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 759 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge 145:64910690c574 760 * AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 761 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge 145:64910690c574 762 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 763 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep
Kojto 122:f9eeca106725 764 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 765 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
Kojto 122:f9eeca106725 766 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
Kojto 122:f9eeca106725 767 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
Kojto 122:f9eeca106725 768 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
Kojto 122:f9eeca106725 769 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
Kojto 122:f9eeca106725 770 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
Kojto 122:f9eeca106725 771 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
Kojto 122:f9eeca106725 772 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge 145:64910690c574 773 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
Kojto 122:f9eeca106725 774 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
Kojto 122:f9eeca106725 775 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
Kojto 122:f9eeca106725 776 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge 145:64910690c574 777 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
Kojto 122:f9eeca106725 778 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge 145:64910690c574 779 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
Kojto 122:f9eeca106725 780 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
Kojto 122:f9eeca106725 781 *
Kojto 122:f9eeca106725 782 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 783 * @retval None
Kojto 122:f9eeca106725 784 */
Kojto 122:f9eeca106725 785 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
Kojto 122:f9eeca106725 786 {
Kojto 122:f9eeca106725 787 CLEAR_BIT(RCC->AHB2SMENR, Periphs);
Kojto 122:f9eeca106725 788 }
Kojto 122:f9eeca106725 789
Kojto 122:f9eeca106725 790 /**
Kojto 122:f9eeca106725 791 * @}
Kojto 122:f9eeca106725 792 */
Kojto 122:f9eeca106725 793
Kojto 122:f9eeca106725 794 /** @defgroup BUS_LL_EF_AHB3 AHB3
Kojto 122:f9eeca106725 795 * @{
Kojto 122:f9eeca106725 796 */
Kojto 122:f9eeca106725 797
Kojto 122:f9eeca106725 798 /**
Kojto 122:f9eeca106725 799 * @brief Enable AHB3 peripherals clock.
Kojto 122:f9eeca106725 800 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
Kojto 122:f9eeca106725 801 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
Kojto 122:f9eeca106725 802 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 803 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto 122:f9eeca106725 804 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto 122:f9eeca106725 805 *
Kojto 122:f9eeca106725 806 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 807 * @retval None
Kojto 122:f9eeca106725 808 */
Kojto 122:f9eeca106725 809 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
Kojto 122:f9eeca106725 810 {
Kojto 122:f9eeca106725 811 __IO uint32_t tmpreg;
Kojto 122:f9eeca106725 812 SET_BIT(RCC->AHB3ENR, Periphs);
Kojto 122:f9eeca106725 813 /* Delay after an RCC peripheral clock enabling */
Kojto 122:f9eeca106725 814 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
Kojto 122:f9eeca106725 815 (void)tmpreg;
Kojto 122:f9eeca106725 816 }
Kojto 122:f9eeca106725 817
Kojto 122:f9eeca106725 818 /**
Kojto 122:f9eeca106725 819 * @brief Check if AHB3 peripheral clock is enabled or not
Kojto 122:f9eeca106725 820 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 821 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
Kojto 122:f9eeca106725 822 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 823 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto 122:f9eeca106725 824 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto 122:f9eeca106725 825 *
Kojto 122:f9eeca106725 826 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 827 * @retval State of Periphs (1 or 0).
Kojto 122:f9eeca106725 828 */
Kojto 122:f9eeca106725 829 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
Kojto 122:f9eeca106725 830 {
Kojto 122:f9eeca106725 831 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
Kojto 122:f9eeca106725 832 }
Kojto 122:f9eeca106725 833
Kojto 122:f9eeca106725 834 /**
Kojto 122:f9eeca106725 835 * @brief Disable AHB3 peripherals clock.
Kojto 122:f9eeca106725 836 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
Kojto 122:f9eeca106725 837 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
Kojto 122:f9eeca106725 838 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 839 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto 122:f9eeca106725 840 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto 122:f9eeca106725 841 *
Kojto 122:f9eeca106725 842 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 843 * @retval None
Kojto 122:f9eeca106725 844 */
Kojto 122:f9eeca106725 845 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
Kojto 122:f9eeca106725 846 {
Kojto 122:f9eeca106725 847 CLEAR_BIT(RCC->AHB3ENR, Periphs);
Kojto 122:f9eeca106725 848 }
Kojto 122:f9eeca106725 849
Kojto 122:f9eeca106725 850 /**
Kojto 122:f9eeca106725 851 * @brief Force AHB3 peripherals reset.
Kojto 122:f9eeca106725 852 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
Kojto 122:f9eeca106725 853 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
Kojto 122:f9eeca106725 854 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 855 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
Kojto 122:f9eeca106725 856 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto 122:f9eeca106725 857 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto 122:f9eeca106725 858 *
Kojto 122:f9eeca106725 859 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 860 * @retval None
Kojto 122:f9eeca106725 861 */
Kojto 122:f9eeca106725 862 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
Kojto 122:f9eeca106725 863 {
Kojto 122:f9eeca106725 864 SET_BIT(RCC->AHB3RSTR, Periphs);
Kojto 122:f9eeca106725 865 }
Kojto 122:f9eeca106725 866
Kojto 122:f9eeca106725 867 /**
Kojto 122:f9eeca106725 868 * @brief Release AHB3 peripherals reset.
Kojto 122:f9eeca106725 869 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 870 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
Kojto 122:f9eeca106725 871 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 872 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
Kojto 122:f9eeca106725 873 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto 122:f9eeca106725 874 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto 122:f9eeca106725 875 *
Kojto 122:f9eeca106725 876 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 877 * @retval None
Kojto 122:f9eeca106725 878 */
Kojto 122:f9eeca106725 879 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
Kojto 122:f9eeca106725 880 {
Kojto 122:f9eeca106725 881 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
Kojto 122:f9eeca106725 882 }
Kojto 122:f9eeca106725 883
Kojto 122:f9eeca106725 884 /**
Kojto 122:f9eeca106725 885 * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
Kojto 122:f9eeca106725 886 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 887 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep
Kojto 122:f9eeca106725 888 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 889 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto 122:f9eeca106725 890 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto 122:f9eeca106725 891 *
Kojto 122:f9eeca106725 892 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 893 * @retval None
Kojto 122:f9eeca106725 894 */
Kojto 122:f9eeca106725 895 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
Kojto 122:f9eeca106725 896 {
Kojto 122:f9eeca106725 897 __IO uint32_t tmpreg;
Kojto 122:f9eeca106725 898 SET_BIT(RCC->AHB3SMENR, Periphs);
Kojto 122:f9eeca106725 899 /* Delay after an RCC peripheral clock enabling */
Kojto 122:f9eeca106725 900 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
Kojto 122:f9eeca106725 901 (void)tmpreg;
Kojto 122:f9eeca106725 902 }
Kojto 122:f9eeca106725 903
Kojto 122:f9eeca106725 904 /**
Kojto 122:f9eeca106725 905 * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
Kojto 122:f9eeca106725 906 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 907 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep
Kojto 122:f9eeca106725 908 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 909 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
Kojto 122:f9eeca106725 910 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
Kojto 122:f9eeca106725 911 *
Kojto 122:f9eeca106725 912 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 913 * @retval None
Kojto 122:f9eeca106725 914 */
Kojto 122:f9eeca106725 915 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
Kojto 122:f9eeca106725 916 {
Kojto 122:f9eeca106725 917 CLEAR_BIT(RCC->AHB3SMENR, Periphs);
Kojto 122:f9eeca106725 918 }
Kojto 122:f9eeca106725 919
Kojto 122:f9eeca106725 920 /**
Kojto 122:f9eeca106725 921 * @}
Kojto 122:f9eeca106725 922 */
Kojto 122:f9eeca106725 923
Kojto 122:f9eeca106725 924 /** @defgroup BUS_LL_EF_APB1 APB1
Kojto 122:f9eeca106725 925 * @{
Kojto 122:f9eeca106725 926 */
Kojto 122:f9eeca106725 927
Kojto 122:f9eeca106725 928 /**
Kojto 122:f9eeca106725 929 * @brief Enable APB1 peripherals clock.
Kojto 122:f9eeca106725 930 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 931 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 932 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 933 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 934 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 935 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 936 * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 937 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 938 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 939 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 940 * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 941 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 942 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 943 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 944 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 945 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 946 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 947 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 948 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 949 * APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge 145:64910690c574 950 * APB1ENR1 USBFSEN LL_APB1_GRP1_EnableClock\n
AnnaBridge 145:64910690c574 951 * APB1ENR1 CAN2EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 952 * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 953 * APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 954 * APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n
Kojto 122:f9eeca106725 955 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
Kojto 122:f9eeca106725 956 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 957 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto 122:f9eeca106725 958 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto 122:f9eeca106725 959 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto 122:f9eeca106725 960 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto 122:f9eeca106725 961 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto 122:f9eeca106725 962 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto 122:f9eeca106725 963 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto 122:f9eeca106725 964 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
Kojto 122:f9eeca106725 965 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
Kojto 122:f9eeca106725 966 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto 122:f9eeca106725 967 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto 122:f9eeca106725 968 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto 122:f9eeca106725 969 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto 122:f9eeca106725 970 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto 122:f9eeca106725 971 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto 122:f9eeca106725 972 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto 122:f9eeca106725 973 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto 122:f9eeca106725 974 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto 122:f9eeca106725 975 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto 122:f9eeca106725 976 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge 145:64910690c574 977 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
Kojto 122:f9eeca106725 978 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto 122:f9eeca106725 979 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto 122:f9eeca106725 980 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto 122:f9eeca106725 981 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto 122:f9eeca106725 982 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto 122:f9eeca106725 983 *
Kojto 122:f9eeca106725 984 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 985 * @retval None
Kojto 122:f9eeca106725 986 */
Kojto 122:f9eeca106725 987 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
Kojto 122:f9eeca106725 988 {
Kojto 122:f9eeca106725 989 __IO uint32_t tmpreg;
Kojto 122:f9eeca106725 990 SET_BIT(RCC->APB1ENR1, Periphs);
Kojto 122:f9eeca106725 991 /* Delay after an RCC peripheral clock enabling */
Kojto 122:f9eeca106725 992 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
Kojto 122:f9eeca106725 993 (void)tmpreg;
Kojto 122:f9eeca106725 994 }
Kojto 122:f9eeca106725 995
Kojto 122:f9eeca106725 996 /**
Kojto 122:f9eeca106725 997 * @brief Enable APB1 peripherals clock.
Kojto 122:f9eeca106725 998 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
AnnaBridge 145:64910690c574 999 * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
Kojto 122:f9eeca106725 1000 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n
Kojto 122:f9eeca106725 1001 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
Kojto 122:f9eeca106725 1002 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1003 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge 145:64910690c574 1004 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge 145:64910690c574 1005 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
Kojto 122:f9eeca106725 1006 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge 145:64910690c574 1007 *
AnnaBridge 145:64910690c574 1008 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1009 * @retval None
Kojto 122:f9eeca106725 1010 */
Kojto 122:f9eeca106725 1011 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
Kojto 122:f9eeca106725 1012 {
Kojto 122:f9eeca106725 1013 __IO uint32_t tmpreg;
Kojto 122:f9eeca106725 1014 SET_BIT(RCC->APB1ENR2, Periphs);
Kojto 122:f9eeca106725 1015 /* Delay after an RCC peripheral clock enabling */
Kojto 122:f9eeca106725 1016 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
Kojto 122:f9eeca106725 1017 (void)tmpreg;
Kojto 122:f9eeca106725 1018 }
Kojto 122:f9eeca106725 1019
Kojto 122:f9eeca106725 1020 /**
Kojto 122:f9eeca106725 1021 * @brief Check if APB1 peripheral clock is enabled or not
Kojto 122:f9eeca106725 1022 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1023 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1024 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1025 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1026 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1027 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1028 * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1029 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1030 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1031 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1032 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1033 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1034 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1035 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1036 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1037 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1038 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1039 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1040 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1041 * APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 145:64910690c574 1042 * APB1ENR1 USBFSEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 145:64910690c574 1043 * APB1ENR1 CAN2EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1044 * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1045 * APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1046 * APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1047 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
Kojto 122:f9eeca106725 1048 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1049 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto 122:f9eeca106725 1050 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto 122:f9eeca106725 1051 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto 122:f9eeca106725 1052 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto 122:f9eeca106725 1053 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto 122:f9eeca106725 1054 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto 122:f9eeca106725 1055 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto 122:f9eeca106725 1056 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
Kojto 122:f9eeca106725 1057 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
Kojto 122:f9eeca106725 1058 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto 122:f9eeca106725 1059 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto 122:f9eeca106725 1060 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto 122:f9eeca106725 1061 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto 122:f9eeca106725 1062 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto 122:f9eeca106725 1063 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto 122:f9eeca106725 1064 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto 122:f9eeca106725 1065 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto 122:f9eeca106725 1066 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto 122:f9eeca106725 1067 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto 122:f9eeca106725 1068 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge 145:64910690c574 1069 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
Kojto 122:f9eeca106725 1070 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto 122:f9eeca106725 1071 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto 122:f9eeca106725 1072 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto 122:f9eeca106725 1073 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto 122:f9eeca106725 1074 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto 122:f9eeca106725 1075 *
Kojto 122:f9eeca106725 1076 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1077 * @retval State of Periphs (1 or 0).
Kojto 122:f9eeca106725 1078 */
Kojto 122:f9eeca106725 1079 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
Kojto 122:f9eeca106725 1080 {
Kojto 122:f9eeca106725 1081 return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs);
Kojto 122:f9eeca106725 1082 }
Kojto 122:f9eeca106725 1083
Kojto 122:f9eeca106725 1084 /**
Kojto 122:f9eeca106725 1085 * @brief Check if APB1 peripheral clock is enabled or not
Kojto 122:f9eeca106725 1086 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
AnnaBridge 145:64910690c574 1087 * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
Kojto 122:f9eeca106725 1088 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n
Kojto 122:f9eeca106725 1089 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
Kojto 122:f9eeca106725 1090 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1091 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge 145:64910690c574 1092 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge 145:64910690c574 1093 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
Kojto 122:f9eeca106725 1094 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge 145:64910690c574 1095 *
AnnaBridge 145:64910690c574 1096 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1097 * @retval State of Periphs (1 or 0).
Kojto 122:f9eeca106725 1098 */
Kojto 122:f9eeca106725 1099 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
Kojto 122:f9eeca106725 1100 {
Kojto 122:f9eeca106725 1101 return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs);
Kojto 122:f9eeca106725 1102 }
Kojto 122:f9eeca106725 1103
Kojto 122:f9eeca106725 1104 /**
Kojto 122:f9eeca106725 1105 * @brief Disable APB1 peripherals clock.
Kojto 122:f9eeca106725 1106 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1107 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1108 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1109 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1110 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1111 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1112 * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1113 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1114 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1115 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1116 * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1117 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1118 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1119 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1120 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1121 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1122 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1123 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1124 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1125 * APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge 145:64910690c574 1126 * APB1ENR1 USBFSEN LL_APB1_GRP1_DisableClock\n
AnnaBridge 145:64910690c574 1127 * APB1ENR1 CAN2EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1128 * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1129 * APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1130 * APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1131 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
Kojto 122:f9eeca106725 1132 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1133 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto 122:f9eeca106725 1134 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto 122:f9eeca106725 1135 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto 122:f9eeca106725 1136 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto 122:f9eeca106725 1137 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto 122:f9eeca106725 1138 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto 122:f9eeca106725 1139 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto 122:f9eeca106725 1140 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
Kojto 122:f9eeca106725 1141 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
Kojto 122:f9eeca106725 1142 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto 122:f9eeca106725 1143 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto 122:f9eeca106725 1144 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto 122:f9eeca106725 1145 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto 122:f9eeca106725 1146 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto 122:f9eeca106725 1147 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto 122:f9eeca106725 1148 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto 122:f9eeca106725 1149 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto 122:f9eeca106725 1150 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto 122:f9eeca106725 1151 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto 122:f9eeca106725 1152 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge 145:64910690c574 1153 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
Kojto 122:f9eeca106725 1154 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto 122:f9eeca106725 1155 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto 122:f9eeca106725 1156 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto 122:f9eeca106725 1157 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto 122:f9eeca106725 1158 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto 122:f9eeca106725 1159 *
Kojto 122:f9eeca106725 1160 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1161 * @retval None
Kojto 122:f9eeca106725 1162 */
Kojto 122:f9eeca106725 1163 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
Kojto 122:f9eeca106725 1164 {
Kojto 122:f9eeca106725 1165 CLEAR_BIT(RCC->APB1ENR1, Periphs);
Kojto 122:f9eeca106725 1166 }
Kojto 122:f9eeca106725 1167
Kojto 122:f9eeca106725 1168 /**
Kojto 122:f9eeca106725 1169 * @brief Disable APB1 peripherals clock.
Kojto 122:f9eeca106725 1170 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
AnnaBridge 145:64910690c574 1171 * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
Kojto 122:f9eeca106725 1172 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n
Kojto 122:f9eeca106725 1173 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
Kojto 122:f9eeca106725 1174 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1175 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge 145:64910690c574 1176 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge 145:64910690c574 1177 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
Kojto 122:f9eeca106725 1178 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge 145:64910690c574 1179 *
AnnaBridge 145:64910690c574 1180 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1181 * @retval None
Kojto 122:f9eeca106725 1182 */
Kojto 122:f9eeca106725 1183 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
Kojto 122:f9eeca106725 1184 {
Kojto 122:f9eeca106725 1185 CLEAR_BIT(RCC->APB1ENR2, Periphs);
Kojto 122:f9eeca106725 1186 }
Kojto 122:f9eeca106725 1187
Kojto 122:f9eeca106725 1188 /**
Kojto 122:f9eeca106725 1189 * @brief Force APB1 peripherals reset.
Kojto 122:f9eeca106725 1190 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1191 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1192 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1193 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1194 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1195 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1196 * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1197 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1198 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1199 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1200 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1201 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1202 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1203 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1204 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1205 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1206 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1207 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge 145:64910690c574 1208 * APB1RSTR1 USBFSRST LL_APB1_GRP1_ForceReset\n
AnnaBridge 145:64910690c574 1209 * APB1RSTR1 CAN2RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1210 * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1211 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1212 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1213 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
Kojto 122:f9eeca106725 1214 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1215 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
Kojto 122:f9eeca106725 1216 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto 122:f9eeca106725 1217 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto 122:f9eeca106725 1218 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto 122:f9eeca106725 1219 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto 122:f9eeca106725 1220 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto 122:f9eeca106725 1221 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto 122:f9eeca106725 1222 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto 122:f9eeca106725 1223 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto 122:f9eeca106725 1224 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto 122:f9eeca106725 1225 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto 122:f9eeca106725 1226 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto 122:f9eeca106725 1227 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto 122:f9eeca106725 1228 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto 122:f9eeca106725 1229 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto 122:f9eeca106725 1230 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto 122:f9eeca106725 1231 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto 122:f9eeca106725 1232 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto 122:f9eeca106725 1233 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge 145:64910690c574 1234 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
Kojto 122:f9eeca106725 1235 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto 122:f9eeca106725 1236 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto 122:f9eeca106725 1237 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto 122:f9eeca106725 1238 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto 122:f9eeca106725 1239 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto 122:f9eeca106725 1240 *
Kojto 122:f9eeca106725 1241 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1242 * @retval None
Kojto 122:f9eeca106725 1243 */
Kojto 122:f9eeca106725 1244 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
Kojto 122:f9eeca106725 1245 {
Kojto 122:f9eeca106725 1246 SET_BIT(RCC->APB1RSTR1, Periphs);
Kojto 122:f9eeca106725 1247 }
Kojto 122:f9eeca106725 1248
Kojto 122:f9eeca106725 1249 /**
Kojto 122:f9eeca106725 1250 * @brief Force APB1 peripherals reset.
Kojto 122:f9eeca106725 1251 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
AnnaBridge 145:64910690c574 1252 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n
Kojto 122:f9eeca106725 1253 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n
Kojto 122:f9eeca106725 1254 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
Kojto 122:f9eeca106725 1255 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1256 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
Kojto 122:f9eeca106725 1257 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge 145:64910690c574 1258 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge 145:64910690c574 1259 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
Kojto 122:f9eeca106725 1260 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge 145:64910690c574 1261 *
AnnaBridge 145:64910690c574 1262 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1263 * @retval None
Kojto 122:f9eeca106725 1264 */
Kojto 122:f9eeca106725 1265 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
Kojto 122:f9eeca106725 1266 {
Kojto 122:f9eeca106725 1267 SET_BIT(RCC->APB1RSTR2, Periphs);
Kojto 122:f9eeca106725 1268 }
Kojto 122:f9eeca106725 1269
Kojto 122:f9eeca106725 1270 /**
Kojto 122:f9eeca106725 1271 * @brief Release APB1 peripherals reset.
Kojto 122:f9eeca106725 1272 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1273 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1274 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1275 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1276 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1277 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1278 * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1279 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1280 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1281 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1282 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1283 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1284 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1285 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1286 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1287 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1288 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1289 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 145:64910690c574 1290 * APB1RSTR1 USBFSRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 145:64910690c574 1291 * APB1RSTR1 CAN2RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1292 * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1293 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1294 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1295 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
Kojto 122:f9eeca106725 1296 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1297 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
Kojto 122:f9eeca106725 1298 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto 122:f9eeca106725 1299 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto 122:f9eeca106725 1300 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto 122:f9eeca106725 1301 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto 122:f9eeca106725 1302 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto 122:f9eeca106725 1303 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto 122:f9eeca106725 1304 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto 122:f9eeca106725 1305 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto 122:f9eeca106725 1306 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto 122:f9eeca106725 1307 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto 122:f9eeca106725 1308 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto 122:f9eeca106725 1309 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto 122:f9eeca106725 1310 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto 122:f9eeca106725 1311 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto 122:f9eeca106725 1312 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto 122:f9eeca106725 1313 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto 122:f9eeca106725 1314 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto 122:f9eeca106725 1315 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge 145:64910690c574 1316 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
Kojto 122:f9eeca106725 1317 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto 122:f9eeca106725 1318 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto 122:f9eeca106725 1319 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto 122:f9eeca106725 1320 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto 122:f9eeca106725 1321 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto 122:f9eeca106725 1322 *
Kojto 122:f9eeca106725 1323 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1324 * @retval None
Kojto 122:f9eeca106725 1325 */
Kojto 122:f9eeca106725 1326 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
Kojto 122:f9eeca106725 1327 {
Kojto 122:f9eeca106725 1328 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
Kojto 122:f9eeca106725 1329 }
Kojto 122:f9eeca106725 1330
Kojto 122:f9eeca106725 1331 /**
Kojto 122:f9eeca106725 1332 * @brief Release APB1 peripherals reset.
Kojto 122:f9eeca106725 1333 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
AnnaBridge 145:64910690c574 1334 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
Kojto 122:f9eeca106725 1335 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n
Kojto 122:f9eeca106725 1336 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
Kojto 122:f9eeca106725 1337 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1338 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
Kojto 122:f9eeca106725 1339 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge 145:64910690c574 1340 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge 145:64910690c574 1341 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
Kojto 122:f9eeca106725 1342 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge 145:64910690c574 1343 *
AnnaBridge 145:64910690c574 1344 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1345 * @retval None
Kojto 122:f9eeca106725 1346 */
Kojto 122:f9eeca106725 1347 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
Kojto 122:f9eeca106725 1348 {
Kojto 122:f9eeca106725 1349 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
Kojto 122:f9eeca106725 1350 }
Kojto 122:f9eeca106725 1351
Kojto 122:f9eeca106725 1352 /**
Kojto 122:f9eeca106725 1353 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
Kojto 122:f9eeca106725 1354 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1355 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1356 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1357 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1358 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1359 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1360 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1361 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1362 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1363 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1364 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1365 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1366 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1367 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1368 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1369 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1370 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1371 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1372 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1373 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge 145:64910690c574 1374 * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge 145:64910690c574 1375 * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1376 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1377 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1378 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1379 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
Kojto 122:f9eeca106725 1380 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1381 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto 122:f9eeca106725 1382 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto 122:f9eeca106725 1383 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto 122:f9eeca106725 1384 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto 122:f9eeca106725 1385 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto 122:f9eeca106725 1386 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto 122:f9eeca106725 1387 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto 122:f9eeca106725 1388 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
Kojto 122:f9eeca106725 1389 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
Kojto 122:f9eeca106725 1390 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto 122:f9eeca106725 1391 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto 122:f9eeca106725 1392 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto 122:f9eeca106725 1393 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto 122:f9eeca106725 1394 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto 122:f9eeca106725 1395 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto 122:f9eeca106725 1396 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto 122:f9eeca106725 1397 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto 122:f9eeca106725 1398 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto 122:f9eeca106725 1399 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto 122:f9eeca106725 1400 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge 145:64910690c574 1401 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
Kojto 122:f9eeca106725 1402 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto 122:f9eeca106725 1403 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto 122:f9eeca106725 1404 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto 122:f9eeca106725 1405 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto 122:f9eeca106725 1406 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto 122:f9eeca106725 1407 *
Kojto 122:f9eeca106725 1408 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1409 * @retval None
Kojto 122:f9eeca106725 1410 */
Kojto 122:f9eeca106725 1411 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
Kojto 122:f9eeca106725 1412 {
Kojto 122:f9eeca106725 1413 __IO uint32_t tmpreg;
Kojto 122:f9eeca106725 1414 SET_BIT(RCC->APB1SMENR1, Periphs);
Kojto 122:f9eeca106725 1415 /* Delay after an RCC peripheral clock enabling */
Kojto 122:f9eeca106725 1416 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
Kojto 122:f9eeca106725 1417 (void)tmpreg;
Kojto 122:f9eeca106725 1418 }
Kojto 122:f9eeca106725 1419
Kojto 122:f9eeca106725 1420 /**
Kojto 122:f9eeca106725 1421 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
Kojto 122:f9eeca106725 1422 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
AnnaBridge 145:64910690c574 1423 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1424 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1425 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep
Kojto 122:f9eeca106725 1426 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1427 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge 145:64910690c574 1428 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge 145:64910690c574 1429 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
Kojto 122:f9eeca106725 1430 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge 145:64910690c574 1431 *
AnnaBridge 145:64910690c574 1432 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1433 * @retval None
Kojto 122:f9eeca106725 1434 */
Kojto 122:f9eeca106725 1435 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
Kojto 122:f9eeca106725 1436 {
Kojto 122:f9eeca106725 1437 __IO uint32_t tmpreg;
Kojto 122:f9eeca106725 1438 SET_BIT(RCC->APB1SMENR2, Periphs);
Kojto 122:f9eeca106725 1439 /* Delay after an RCC peripheral clock enabling */
Kojto 122:f9eeca106725 1440 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
Kojto 122:f9eeca106725 1441 (void)tmpreg;
Kojto 122:f9eeca106725 1442 }
Kojto 122:f9eeca106725 1443
Kojto 122:f9eeca106725 1444 /**
Kojto 122:f9eeca106725 1445 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
Kojto 122:f9eeca106725 1446 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1447 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1448 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1449 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1450 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1451 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1452 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1453 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1454 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1455 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1456 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1457 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1458 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1459 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1460 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1461 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1462 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1463 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1464 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1465 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge 145:64910690c574 1466 * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge 145:64910690c574 1467 * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1468 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1469 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1470 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1471 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
Kojto 122:f9eeca106725 1472 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1473 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
Kojto 122:f9eeca106725 1474 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
Kojto 122:f9eeca106725 1475 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
Kojto 122:f9eeca106725 1476 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
Kojto 122:f9eeca106725 1477 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
Kojto 122:f9eeca106725 1478 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
Kojto 122:f9eeca106725 1479 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
Kojto 122:f9eeca106725 1480 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
Kojto 122:f9eeca106725 1481 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
Kojto 122:f9eeca106725 1482 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
Kojto 122:f9eeca106725 1483 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
Kojto 122:f9eeca106725 1484 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
Kojto 122:f9eeca106725 1485 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
Kojto 122:f9eeca106725 1486 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
Kojto 122:f9eeca106725 1487 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
Kojto 122:f9eeca106725 1488 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
Kojto 122:f9eeca106725 1489 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
Kojto 122:f9eeca106725 1490 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
Kojto 122:f9eeca106725 1491 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
Kojto 122:f9eeca106725 1492 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge 145:64910690c574 1493 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
Kojto 122:f9eeca106725 1494 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
Kojto 122:f9eeca106725 1495 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
Kojto 122:f9eeca106725 1496 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
Kojto 122:f9eeca106725 1497 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
Kojto 122:f9eeca106725 1498 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
Kojto 122:f9eeca106725 1499 *
Kojto 122:f9eeca106725 1500 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1501 * @retval None
Kojto 122:f9eeca106725 1502 */
Kojto 122:f9eeca106725 1503 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
Kojto 122:f9eeca106725 1504 {
Kojto 122:f9eeca106725 1505 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
Kojto 122:f9eeca106725 1506 }
Kojto 122:f9eeca106725 1507
Kojto 122:f9eeca106725 1508 /**
Kojto 122:f9eeca106725 1509 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
Kojto 122:f9eeca106725 1510 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
AnnaBridge 145:64910690c574 1511 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1512 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1513 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep
Kojto 122:f9eeca106725 1514 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1515 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge 145:64910690c574 1516 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge 145:64910690c574 1517 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
Kojto 122:f9eeca106725 1518 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge 145:64910690c574 1519 *
AnnaBridge 145:64910690c574 1520 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1521 * @retval None
Kojto 122:f9eeca106725 1522 */
Kojto 122:f9eeca106725 1523 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
Kojto 122:f9eeca106725 1524 {
Kojto 122:f9eeca106725 1525 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
Kojto 122:f9eeca106725 1526 }
Kojto 122:f9eeca106725 1527
Kojto 122:f9eeca106725 1528 /**
Kojto 122:f9eeca106725 1529 * @}
Kojto 122:f9eeca106725 1530 */
Kojto 122:f9eeca106725 1531
Kojto 122:f9eeca106725 1532 /** @defgroup BUS_LL_EF_APB2 APB2
Kojto 122:f9eeca106725 1533 * @{
Kojto 122:f9eeca106725 1534 */
Kojto 122:f9eeca106725 1535
Kojto 122:f9eeca106725 1536 /**
Kojto 122:f9eeca106725 1537 * @brief Enable APB2 peripherals clock.
Kojto 122:f9eeca106725 1538 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 1539 * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 1540 * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 1541 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 1542 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 1543 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 1544 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 1545 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 1546 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 1547 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 1548 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 1549 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
Kojto 122:f9eeca106725 1550 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock
Kojto 122:f9eeca106725 1551 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1552 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto 122:f9eeca106725 1553 * @arg @ref LL_APB2_GRP1_PERIPH_FW
Kojto 122:f9eeca106725 1554 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto 122:f9eeca106725 1555 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto 122:f9eeca106725 1556 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto 122:f9eeca106725 1557 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto 122:f9eeca106725 1558 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto 122:f9eeca106725 1559 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto 122:f9eeca106725 1560 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto 122:f9eeca106725 1561 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto 122:f9eeca106725 1562 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto 122:f9eeca106725 1563 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto 122:f9eeca106725 1564 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto 122:f9eeca106725 1565 *
Kojto 122:f9eeca106725 1566 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1567 * @retval None
Kojto 122:f9eeca106725 1568 */
Kojto 122:f9eeca106725 1569 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
Kojto 122:f9eeca106725 1570 {
Kojto 122:f9eeca106725 1571 __IO uint32_t tmpreg;
Kojto 122:f9eeca106725 1572 SET_BIT(RCC->APB2ENR, Periphs);
Kojto 122:f9eeca106725 1573 /* Delay after an RCC peripheral clock enabling */
Kojto 122:f9eeca106725 1574 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
Kojto 122:f9eeca106725 1575 (void)tmpreg;
Kojto 122:f9eeca106725 1576 }
Kojto 122:f9eeca106725 1577
Kojto 122:f9eeca106725 1578 /**
Kojto 122:f9eeca106725 1579 * @brief Check if APB2 peripheral clock is enabled or not
Kojto 122:f9eeca106725 1580 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1581 * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1582 * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1583 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1584 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1585 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1586 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1587 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1588 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1589 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1590 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1591 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
Kojto 122:f9eeca106725 1592 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock
Kojto 122:f9eeca106725 1593 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1594 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto 122:f9eeca106725 1595 * @arg @ref LL_APB2_GRP1_PERIPH_FW
Kojto 122:f9eeca106725 1596 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto 122:f9eeca106725 1597 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto 122:f9eeca106725 1598 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto 122:f9eeca106725 1599 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto 122:f9eeca106725 1600 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto 122:f9eeca106725 1601 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto 122:f9eeca106725 1602 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto 122:f9eeca106725 1603 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto 122:f9eeca106725 1604 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto 122:f9eeca106725 1605 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto 122:f9eeca106725 1606 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto 122:f9eeca106725 1607 *
Kojto 122:f9eeca106725 1608 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1609 * @retval State of Periphs (1 or 0).
Kojto 122:f9eeca106725 1610 */
Kojto 122:f9eeca106725 1611 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
Kojto 122:f9eeca106725 1612 {
Kojto 122:f9eeca106725 1613 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
Kojto 122:f9eeca106725 1614 }
Kojto 122:f9eeca106725 1615
Kojto 122:f9eeca106725 1616 /**
Kojto 122:f9eeca106725 1617 * @brief Disable APB2 peripherals clock.
Kojto 122:f9eeca106725 1618 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1619 * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1620 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1621 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1622 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1623 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1624 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1625 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1626 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1627 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1628 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
Kojto 122:f9eeca106725 1629 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock
Kojto 122:f9eeca106725 1630 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1631 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto 122:f9eeca106725 1632 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto 122:f9eeca106725 1633 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto 122:f9eeca106725 1634 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto 122:f9eeca106725 1635 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto 122:f9eeca106725 1636 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto 122:f9eeca106725 1637 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto 122:f9eeca106725 1638 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto 122:f9eeca106725 1639 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto 122:f9eeca106725 1640 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto 122:f9eeca106725 1641 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto 122:f9eeca106725 1642 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto 122:f9eeca106725 1643 *
Kojto 122:f9eeca106725 1644 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1645 * @retval None
Kojto 122:f9eeca106725 1646 */
Kojto 122:f9eeca106725 1647 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
Kojto 122:f9eeca106725 1648 {
Kojto 122:f9eeca106725 1649 CLEAR_BIT(RCC->APB2ENR, Periphs);
Kojto 122:f9eeca106725 1650 }
Kojto 122:f9eeca106725 1651
Kojto 122:f9eeca106725 1652 /**
Kojto 122:f9eeca106725 1653 * @brief Force APB2 peripherals reset.
Kojto 122:f9eeca106725 1654 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1655 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1656 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1657 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1658 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1659 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1660 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1661 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1662 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1663 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1664 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
Kojto 122:f9eeca106725 1665 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset
Kojto 122:f9eeca106725 1666 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1667 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
Kojto 122:f9eeca106725 1668 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto 122:f9eeca106725 1669 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto 122:f9eeca106725 1670 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto 122:f9eeca106725 1671 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto 122:f9eeca106725 1672 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto 122:f9eeca106725 1673 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto 122:f9eeca106725 1674 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto 122:f9eeca106725 1675 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto 122:f9eeca106725 1676 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto 122:f9eeca106725 1677 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto 122:f9eeca106725 1678 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto 122:f9eeca106725 1679 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto 122:f9eeca106725 1680 *
Kojto 122:f9eeca106725 1681 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1682 * @retval None
Kojto 122:f9eeca106725 1683 */
Kojto 122:f9eeca106725 1684 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
Kojto 122:f9eeca106725 1685 {
Kojto 122:f9eeca106725 1686 SET_BIT(RCC->APB2RSTR, Periphs);
Kojto 122:f9eeca106725 1687 }
Kojto 122:f9eeca106725 1688
Kojto 122:f9eeca106725 1689 /**
Kojto 122:f9eeca106725 1690 * @brief Release APB2 peripherals reset.
Kojto 122:f9eeca106725 1691 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1692 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1693 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1694 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1695 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1696 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1697 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1698 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1699 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1700 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1701 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
Kojto 122:f9eeca106725 1702 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset
Kojto 122:f9eeca106725 1703 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1704 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
Kojto 122:f9eeca106725 1705 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto 122:f9eeca106725 1706 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto 122:f9eeca106725 1707 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto 122:f9eeca106725 1708 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto 122:f9eeca106725 1709 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto 122:f9eeca106725 1710 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto 122:f9eeca106725 1711 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto 122:f9eeca106725 1712 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto 122:f9eeca106725 1713 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto 122:f9eeca106725 1714 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto 122:f9eeca106725 1715 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto 122:f9eeca106725 1716 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto 122:f9eeca106725 1717 *
Kojto 122:f9eeca106725 1718 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1719 * @retval None
Kojto 122:f9eeca106725 1720 */
Kojto 122:f9eeca106725 1721 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
Kojto 122:f9eeca106725 1722 {
Kojto 122:f9eeca106725 1723 CLEAR_BIT(RCC->APB2RSTR, Periphs);
Kojto 122:f9eeca106725 1724 }
Kojto 122:f9eeca106725 1725
Kojto 122:f9eeca106725 1726 /**
Kojto 122:f9eeca106725 1727 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
Kojto 122:f9eeca106725 1728 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1729 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1730 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1731 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1732 * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1733 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1734 * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1735 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1736 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1737 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1738 * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
Kojto 122:f9eeca106725 1739 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep
Kojto 122:f9eeca106725 1740 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1741 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto 122:f9eeca106725 1742 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto 122:f9eeca106725 1743 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto 122:f9eeca106725 1744 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto 122:f9eeca106725 1745 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto 122:f9eeca106725 1746 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto 122:f9eeca106725 1747 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto 122:f9eeca106725 1748 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto 122:f9eeca106725 1749 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto 122:f9eeca106725 1750 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto 122:f9eeca106725 1751 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto 122:f9eeca106725 1752 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto 122:f9eeca106725 1753 *
Kojto 122:f9eeca106725 1754 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1755 * @retval None
Kojto 122:f9eeca106725 1756 */
Kojto 122:f9eeca106725 1757 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
Kojto 122:f9eeca106725 1758 {
Kojto 122:f9eeca106725 1759 __IO uint32_t tmpreg;
Kojto 122:f9eeca106725 1760 SET_BIT(RCC->APB2SMENR, Periphs);
Kojto 122:f9eeca106725 1761 /* Delay after an RCC peripheral clock enabling */
Kojto 122:f9eeca106725 1762 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
Kojto 122:f9eeca106725 1763 (void)tmpreg;
Kojto 122:f9eeca106725 1764 }
Kojto 122:f9eeca106725 1765
Kojto 122:f9eeca106725 1766 /**
Kojto 122:f9eeca106725 1767 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
Kojto 122:f9eeca106725 1768 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1769 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1770 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1771 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1772 * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1773 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1774 * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1775 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1776 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1777 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1778 * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n
Kojto 122:f9eeca106725 1779 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep
Kojto 122:f9eeca106725 1780 * @param Periphs This parameter can be a combination of the following values:
Kojto 122:f9eeca106725 1781 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
Kojto 122:f9eeca106725 1782 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
Kojto 122:f9eeca106725 1783 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
Kojto 122:f9eeca106725 1784 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
Kojto 122:f9eeca106725 1785 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
Kojto 122:f9eeca106725 1786 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
Kojto 122:f9eeca106725 1787 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
Kojto 122:f9eeca106725 1788 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
Kojto 122:f9eeca106725 1789 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
Kojto 122:f9eeca106725 1790 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
Kojto 122:f9eeca106725 1791 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
Kojto 122:f9eeca106725 1792 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
Kojto 122:f9eeca106725 1793 *
Kojto 122:f9eeca106725 1794 * (*) value not defined in all devices.
Kojto 122:f9eeca106725 1795 * @retval None
Kojto 122:f9eeca106725 1796 */
Kojto 122:f9eeca106725 1797 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
Kojto 122:f9eeca106725 1798 {
Kojto 122:f9eeca106725 1799 CLEAR_BIT(RCC->APB2SMENR, Periphs);
Kojto 122:f9eeca106725 1800 }
Kojto 122:f9eeca106725 1801
Kojto 122:f9eeca106725 1802 /**
Kojto 122:f9eeca106725 1803 * @}
Kojto 122:f9eeca106725 1804 */
Kojto 122:f9eeca106725 1805
Kojto 122:f9eeca106725 1806
Kojto 122:f9eeca106725 1807 /**
Kojto 122:f9eeca106725 1808 * @}
Kojto 122:f9eeca106725 1809 */
Kojto 122:f9eeca106725 1810
Kojto 122:f9eeca106725 1811 /**
Kojto 122:f9eeca106725 1812 * @}
Kojto 122:f9eeca106725 1813 */
Kojto 122:f9eeca106725 1814
Kojto 122:f9eeca106725 1815 #endif /* defined(RCC) */
Kojto 122:f9eeca106725 1816
Kojto 122:f9eeca106725 1817 /**
Kojto 122:f9eeca106725 1818 * @}
Kojto 122:f9eeca106725 1819 */
Kojto 122:f9eeca106725 1820
Kojto 122:f9eeca106725 1821 #ifdef __cplusplus
Kojto 122:f9eeca106725 1822 }
Kojto 122:f9eeca106725 1823 #endif
Kojto 122:f9eeca106725 1824
Kojto 122:f9eeca106725 1825 #endif /* __STM32L4xx_LL_BUS_H */
Kojto 122:f9eeca106725 1826
Kojto 122:f9eeca106725 1827 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/