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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
128:9bcdf88f62b0
Child:
145:64910690c574
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**
Kojto 122:f9eeca106725 2 ******************************************************************************
Kojto 122:f9eeca106725 3 * @file stm32l4xx_hal_rcc_ex.h
Kojto 122:f9eeca106725 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.1
Kojto 122:f9eeca106725 6 * @date 31-May-2016
Kojto 122:f9eeca106725 7 * @brief Header file of RCC HAL Extended module.
Kojto 122:f9eeca106725 8 ******************************************************************************
Kojto 122:f9eeca106725 9 * @attention
Kojto 122:f9eeca106725 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 122:f9eeca106725 12 *
Kojto 122:f9eeca106725 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 14 * are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 122:f9eeca106725 16 * this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 122:f9eeca106725 18 * this list of conditions and the following disclaimer in the documentation
Kojto 122:f9eeca106725 19 * and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 122:f9eeca106725 21 * may be used to endorse or promote products derived from this software
Kojto 122:f9eeca106725 22 * without specific prior written permission.
Kojto 122:f9eeca106725 23 *
Kojto 122:f9eeca106725 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 122:f9eeca106725 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 122:f9eeca106725 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 122:f9eeca106725 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 122:f9eeca106725 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 122:f9eeca106725 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 122:f9eeca106725 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 34 *
Kojto 122:f9eeca106725 35 ******************************************************************************
Kojto 122:f9eeca106725 36 */
Kojto 122:f9eeca106725 37
Kojto 122:f9eeca106725 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 122:f9eeca106725 39 #ifndef __STM32L4xx_HAL_RCC_EX_H
Kojto 122:f9eeca106725 40 #define __STM32L4xx_HAL_RCC_EX_H
Kojto 122:f9eeca106725 41
Kojto 122:f9eeca106725 42 #ifdef __cplusplus
Kojto 122:f9eeca106725 43 extern "C" {
Kojto 122:f9eeca106725 44 #endif
Kojto 122:f9eeca106725 45
Kojto 122:f9eeca106725 46 /* Includes ------------------------------------------------------------------*/
Kojto 122:f9eeca106725 47 #include "stm32l4xx_hal_def.h"
Kojto 122:f9eeca106725 48
Kojto 122:f9eeca106725 49 /** @addtogroup STM32L4xx_HAL_Driver
Kojto 122:f9eeca106725 50 * @{
Kojto 122:f9eeca106725 51 */
Kojto 122:f9eeca106725 52
Kojto 122:f9eeca106725 53 /** @addtogroup RCCEx
Kojto 122:f9eeca106725 54 * @{
Kojto 122:f9eeca106725 55 */
Kojto 122:f9eeca106725 56
Kojto 122:f9eeca106725 57 /* Exported types ------------------------------------------------------------*/
Kojto 122:f9eeca106725 58
Kojto 122:f9eeca106725 59 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto 122:f9eeca106725 60 * @{
Kojto 122:f9eeca106725 61 */
Kojto 122:f9eeca106725 62
Kojto 122:f9eeca106725 63 /**
Kojto 122:f9eeca106725 64 * @brief PLLSAI1 Clock structure definition
Kojto 122:f9eeca106725 65 */
Kojto 122:f9eeca106725 66 typedef struct
Kojto 122:f9eeca106725 67 {
Kojto 122:f9eeca106725 68
Kojto 122:f9eeca106725 69 uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source.
Kojto 122:f9eeca106725 70 This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto 122:f9eeca106725 71
Kojto 122:f9eeca106725 72 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.
Kojto 122:f9eeca106725 73 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
Kojto 122:f9eeca106725 74
Kojto 122:f9eeca106725 75 uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.
Kojto 122:f9eeca106725 76 This parameter must be a number between 8 and 86 or 127 depending on devices. */
Kojto 122:f9eeca106725 77
Kojto 122:f9eeca106725 78 uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock.
Kojto 122:f9eeca106725 79 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto 122:f9eeca106725 80
Kojto 122:f9eeca106725 81 uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.
Kojto 122:f9eeca106725 82 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
Kojto 122:f9eeca106725 83
Kojto 122:f9eeca106725 84 uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock.
Kojto 122:f9eeca106725 85 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
Kojto 122:f9eeca106725 86
Kojto 122:f9eeca106725 87 uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.
Kojto 122:f9eeca106725 88 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
Kojto 122:f9eeca106725 89 }RCC_PLLSAI1InitTypeDef;
Kojto 122:f9eeca106725 90
Kojto 122:f9eeca106725 91 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 92
Kojto 122:f9eeca106725 93 /**
Kojto 122:f9eeca106725 94 * @brief PLLSAI2 Clock structure definition
Kojto 122:f9eeca106725 95 */
Kojto 122:f9eeca106725 96 typedef struct
Kojto 122:f9eeca106725 97 {
Kojto 122:f9eeca106725 98
Kojto 122:f9eeca106725 99 uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source.
Kojto 122:f9eeca106725 100 This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto 122:f9eeca106725 101
Kojto 122:f9eeca106725 102 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.
Kojto 122:f9eeca106725 103 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
Kojto 122:f9eeca106725 104
Kojto 122:f9eeca106725 105 uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.
Kojto 122:f9eeca106725 106 This parameter must be a number between 8 and 86 or 127 depending on devices. */
Kojto 122:f9eeca106725 107
Kojto 122:f9eeca106725 108 uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock.
Kojto 122:f9eeca106725 109 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto 122:f9eeca106725 110
Kojto 122:f9eeca106725 111 uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock.
Kojto 122:f9eeca106725 112 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
Kojto 122:f9eeca106725 113
Kojto 122:f9eeca106725 114 uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.
Kojto 122:f9eeca106725 115 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */
Kojto 122:f9eeca106725 116 }RCC_PLLSAI2InitTypeDef;
Kojto 122:f9eeca106725 117
Kojto 122:f9eeca106725 118 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 119
Kojto 122:f9eeca106725 120 /**
Kojto 122:f9eeca106725 121 * @brief RCC extended clocks structure definition
Kojto 122:f9eeca106725 122 */
Kojto 122:f9eeca106725 123 typedef struct
Kojto 122:f9eeca106725 124 {
Kojto 122:f9eeca106725 125 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 122:f9eeca106725 126 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 122:f9eeca106725 127
Kojto 122:f9eeca106725 128 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters.
Kojto 122:f9eeca106725 129 This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */
Kojto 122:f9eeca106725 130
Kojto 122:f9eeca106725 131 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 132
Kojto 122:f9eeca106725 133 RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters.
Kojto 122:f9eeca106725 134 This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */
Kojto 122:f9eeca106725 135
Kojto 122:f9eeca106725 136 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 137
Kojto 122:f9eeca106725 138 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
Kojto 122:f9eeca106725 139 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 122:f9eeca106725 140
Kojto 122:f9eeca106725 141 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
Kojto 122:f9eeca106725 142 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto 122:f9eeca106725 143
Kojto 122:f9eeca106725 144 #if defined(USART3)
Kojto 122:f9eeca106725 145
Kojto 122:f9eeca106725 146 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
Kojto 122:f9eeca106725 147 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
Kojto 122:f9eeca106725 148
Kojto 122:f9eeca106725 149 #endif /* USART3 */
Kojto 122:f9eeca106725 150
Kojto 122:f9eeca106725 151 #if defined(UART4)
Kojto 122:f9eeca106725 152
Kojto 122:f9eeca106725 153 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
Kojto 122:f9eeca106725 154 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto 122:f9eeca106725 155
Kojto 122:f9eeca106725 156 #endif /* UART4 */
Kojto 122:f9eeca106725 157
Kojto 122:f9eeca106725 158 #if defined(UART5)
Kojto 122:f9eeca106725 159
Kojto 122:f9eeca106725 160 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
Kojto 122:f9eeca106725 161 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto 122:f9eeca106725 162
Kojto 122:f9eeca106725 163 #endif /* UART5 */
Kojto 122:f9eeca106725 164
Kojto 122:f9eeca106725 165 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
Kojto 122:f9eeca106725 166 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
Kojto 122:f9eeca106725 167
Kojto 122:f9eeca106725 168 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
Kojto 122:f9eeca106725 169 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
Kojto 122:f9eeca106725 170
Kojto 122:f9eeca106725 171 #if defined(I2C2)
Kojto 122:f9eeca106725 172
Kojto 122:f9eeca106725 173 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
Kojto 122:f9eeca106725 174 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 122:f9eeca106725 175
Kojto 122:f9eeca106725 176 #endif /* I2C2 */
Kojto 122:f9eeca106725 177
Kojto 122:f9eeca106725 178 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
Kojto 122:f9eeca106725 179 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto 122:f9eeca106725 180
Kojto 122:f9eeca106725 181 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
Kojto 122:f9eeca106725 182 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
Kojto 122:f9eeca106725 183
Kojto 122:f9eeca106725 184 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source.
Kojto 122:f9eeca106725 185 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
Kojto 122:f9eeca106725 186
Kojto 122:f9eeca106725 187 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
Kojto 122:f9eeca106725 188 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
Kojto 122:f9eeca106725 189
Kojto 122:f9eeca106725 190 #if defined(SAI2)
Kojto 122:f9eeca106725 191
Kojto 122:f9eeca106725 192 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source.
Kojto 122:f9eeca106725 193 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
Kojto 122:f9eeca106725 194
Kojto 122:f9eeca106725 195 #endif /* SAI2 */
Kojto 122:f9eeca106725 196
Kojto 122:f9eeca106725 197 #if defined(USB_OTG_FS) || defined(USB)
Kojto 122:f9eeca106725 198
Kojto 122:f9eeca106725 199 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).
Kojto 122:f9eeca106725 200 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 122:f9eeca106725 201
Kojto 122:f9eeca106725 202 #endif /* USB_OTG_FS || USB */
Kojto 122:f9eeca106725 203
Kojto 122:f9eeca106725 204 #if defined(SDMMC1)
Kojto 122:f9eeca106725 205
Kojto 122:f9eeca106725 206 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
Kojto 122:f9eeca106725 207 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
Kojto 122:f9eeca106725 208
Kojto 122:f9eeca106725 209 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 210
Kojto 122:f9eeca106725 211 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).
Kojto 122:f9eeca106725 212 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
Kojto 122:f9eeca106725 213
Kojto 122:f9eeca106725 214 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source.
Kojto 122:f9eeca106725 215 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
Kojto 122:f9eeca106725 216
Kojto 122:f9eeca106725 217 #if defined(SWPMI1)
Kojto 122:f9eeca106725 218
Kojto 122:f9eeca106725 219 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source.
Kojto 122:f9eeca106725 220 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
Kojto 122:f9eeca106725 221
Kojto 122:f9eeca106725 222 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 223
Kojto 122:f9eeca106725 224 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 225
Kojto 122:f9eeca106725 226 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source.
Kojto 122:f9eeca106725 227 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */
Kojto 122:f9eeca106725 228
Kojto 122:f9eeca106725 229 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 230
Kojto 122:f9eeca106725 231 uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
Kojto 122:f9eeca106725 232 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 122:f9eeca106725 233 }RCC_PeriphCLKInitTypeDef;
Kojto 122:f9eeca106725 234
Kojto 122:f9eeca106725 235 #if defined(CRS)
Kojto 122:f9eeca106725 236
Kojto 122:f9eeca106725 237 /**
Kojto 122:f9eeca106725 238 * @brief RCC_CRS Init structure definition
Kojto 122:f9eeca106725 239 */
Kojto 122:f9eeca106725 240 typedef struct
Kojto 122:f9eeca106725 241 {
Kojto 122:f9eeca106725 242 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
Kojto 122:f9eeca106725 243 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
Kojto 122:f9eeca106725 244
Kojto 122:f9eeca106725 245 uint32_t Source; /*!< Specifies the SYNC signal source.
Kojto 122:f9eeca106725 246 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
Kojto 122:f9eeca106725 247
Kojto 122:f9eeca106725 248 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
Kojto 122:f9eeca106725 249 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
Kojto 122:f9eeca106725 250
Kojto 122:f9eeca106725 251 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
Kojto 122:f9eeca106725 252 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
Kojto 122:f9eeca106725 253 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
Kojto 122:f9eeca106725 254
Kojto 122:f9eeca106725 255 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
Kojto 122:f9eeca106725 256 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
Kojto 122:f9eeca106725 257
Kojto 122:f9eeca106725 258 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
Kojto 122:f9eeca106725 259 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
Kojto 122:f9eeca106725 260
Kojto 122:f9eeca106725 261 }RCC_CRSInitTypeDef;
Kojto 122:f9eeca106725 262
Kojto 122:f9eeca106725 263 /**
Kojto 122:f9eeca106725 264 * @brief RCC_CRS Synchronization structure definition
Kojto 122:f9eeca106725 265 */
Kojto 122:f9eeca106725 266 typedef struct
Kojto 122:f9eeca106725 267 {
Kojto 122:f9eeca106725 268 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
Kojto 122:f9eeca106725 269 This parameter must be a number between 0 and 0xFFFF */
Kojto 122:f9eeca106725 270
Kojto 122:f9eeca106725 271 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
Kojto 122:f9eeca106725 272 This parameter must be a number between 0 and 0x3F */
Kojto 122:f9eeca106725 273
Kojto 122:f9eeca106725 274 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
Kojto 122:f9eeca106725 275 value latched in the time of the last SYNC event.
Kojto 122:f9eeca106725 276 This parameter must be a number between 0 and 0xFFFF */
Kojto 122:f9eeca106725 277
Kojto 122:f9eeca106725 278 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
Kojto 122:f9eeca106725 279 frequency error counter latched in the time of the last SYNC event.
Kojto 122:f9eeca106725 280 It shows whether the actual frequency is below or above the target.
Kojto 122:f9eeca106725 281 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
Kojto 122:f9eeca106725 282
Kojto 122:f9eeca106725 283 }RCC_CRSSynchroInfoTypeDef;
Kojto 122:f9eeca106725 284
Kojto 122:f9eeca106725 285 #endif /* CRS */
Kojto 122:f9eeca106725 286 /**
Kojto 122:f9eeca106725 287 * @}
Kojto 122:f9eeca106725 288 */
Kojto 122:f9eeca106725 289
Kojto 122:f9eeca106725 290 /* Exported constants --------------------------------------------------------*/
Kojto 122:f9eeca106725 291 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto 122:f9eeca106725 292 * @{
Kojto 122:f9eeca106725 293 */
Kojto 122:f9eeca106725 294
Kojto 122:f9eeca106725 295 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
Kojto 122:f9eeca106725 296 * @{
Kojto 122:f9eeca106725 297 */
Kojto 122:f9eeca106725 298 #define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */
Kojto 122:f9eeca106725 299 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */
Kojto 122:f9eeca106725 300 /**
Kojto 122:f9eeca106725 301 * @}
Kojto 122:f9eeca106725 302 */
Kojto 122:f9eeca106725 303
Kojto 122:f9eeca106725 304 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
Kojto 122:f9eeca106725 305 * @{
Kojto 122:f9eeca106725 306 */
Kojto 122:f9eeca106725 307 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 308 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 309 #if defined(USART3)
Kojto 122:f9eeca106725 310 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 311 #endif
Kojto 122:f9eeca106725 312 #if defined(UART4)
Kojto 122:f9eeca106725 313 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 314 #endif
Kojto 122:f9eeca106725 315 #if defined(UART5)
Kojto 122:f9eeca106725 316 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 317 #endif
Kojto 122:f9eeca106725 318 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 319 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 320 #if defined(I2C2)
Kojto 122:f9eeca106725 321 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 322 #endif
Kojto 122:f9eeca106725 323 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 324 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 325 #define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 326 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 327 #if defined(SAI2)
Kojto 122:f9eeca106725 328 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 329 #endif
Kojto 122:f9eeca106725 330 #if defined(USB_OTG_FS) || defined(USB)
Kojto 122:f9eeca106725 331 #define RCC_PERIPHCLK_USB ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 332 #endif
Kojto 122:f9eeca106725 333 #define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 334 #define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 335 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 336 #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 337 #endif
Kojto 122:f9eeca106725 338 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 339 #define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 340 #if defined(SDMMC1)
Kojto 122:f9eeca106725 341 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 342 #endif
Kojto 122:f9eeca106725 343 /**
Kojto 122:f9eeca106725 344 * @}
Kojto 122:f9eeca106725 345 */
Kojto 122:f9eeca106725 346
Kojto 122:f9eeca106725 347
Kojto 122:f9eeca106725 348 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
Kojto 122:f9eeca106725 349 * @{
Kojto 122:f9eeca106725 350 */
Kojto 122:f9eeca106725 351 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 352 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
Kojto 122:f9eeca106725 353 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
Kojto 122:f9eeca106725 354 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
Kojto 122:f9eeca106725 355 /**
Kojto 122:f9eeca106725 356 * @}
Kojto 122:f9eeca106725 357 */
Kojto 122:f9eeca106725 358
Kojto 122:f9eeca106725 359 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
Kojto 122:f9eeca106725 360 * @{
Kojto 122:f9eeca106725 361 */
Kojto 122:f9eeca106725 362 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 363 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
Kojto 122:f9eeca106725 364 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
Kojto 122:f9eeca106725 365 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
Kojto 122:f9eeca106725 366 /**
Kojto 122:f9eeca106725 367 * @}
Kojto 122:f9eeca106725 368 */
Kojto 122:f9eeca106725 369
Kojto 122:f9eeca106725 370 #if defined(USART3)
Kojto 122:f9eeca106725 371 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
Kojto 122:f9eeca106725 372 * @{
Kojto 122:f9eeca106725 373 */
Kojto 122:f9eeca106725 374 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 375 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
Kojto 122:f9eeca106725 376 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
Kojto 122:f9eeca106725 377 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
Kojto 122:f9eeca106725 378 /**
Kojto 122:f9eeca106725 379 * @}
Kojto 122:f9eeca106725 380 */
Kojto 122:f9eeca106725 381 #endif /* USART3 */
Kojto 122:f9eeca106725 382
Kojto 122:f9eeca106725 383 #if defined(UART4)
Kojto 122:f9eeca106725 384 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
Kojto 122:f9eeca106725 385 * @{
Kojto 122:f9eeca106725 386 */
Kojto 122:f9eeca106725 387 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 388 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
Kojto 122:f9eeca106725 389 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
Kojto 122:f9eeca106725 390 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
Kojto 122:f9eeca106725 391 /**
Kojto 122:f9eeca106725 392 * @}
Kojto 122:f9eeca106725 393 */
Kojto 122:f9eeca106725 394 #endif /* UART4 */
Kojto 122:f9eeca106725 395
Kojto 122:f9eeca106725 396 #if defined(UART5)
Kojto 122:f9eeca106725 397 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
Kojto 122:f9eeca106725 398 * @{
Kojto 122:f9eeca106725 399 */
Kojto 122:f9eeca106725 400 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 401 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
Kojto 122:f9eeca106725 402 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
Kojto 122:f9eeca106725 403 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
Kojto 122:f9eeca106725 404 /**
Kojto 122:f9eeca106725 405 * @}
Kojto 122:f9eeca106725 406 */
Kojto 122:f9eeca106725 407 #endif /* UART5 */
Kojto 122:f9eeca106725 408
Kojto 122:f9eeca106725 409 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
Kojto 122:f9eeca106725 410 * @{
Kojto 122:f9eeca106725 411 */
Kojto 122:f9eeca106725 412 #define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 413 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
Kojto 122:f9eeca106725 414 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
Kojto 122:f9eeca106725 415 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
Kojto 122:f9eeca106725 416 /**
Kojto 122:f9eeca106725 417 * @}
Kojto 122:f9eeca106725 418 */
Kojto 122:f9eeca106725 419
Kojto 122:f9eeca106725 420 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
Kojto 122:f9eeca106725 421 * @{
Kojto 122:f9eeca106725 422 */
Kojto 122:f9eeca106725 423 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 424 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
Kojto 122:f9eeca106725 425 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
Kojto 122:f9eeca106725 426 /**
Kojto 122:f9eeca106725 427 * @}
Kojto 122:f9eeca106725 428 */
Kojto 122:f9eeca106725 429
Kojto 122:f9eeca106725 430 #if defined(I2C2)
Kojto 122:f9eeca106725 431 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
Kojto 122:f9eeca106725 432 * @{
Kojto 122:f9eeca106725 433 */
Kojto 122:f9eeca106725 434 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 435 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
Kojto 122:f9eeca106725 436 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
Kojto 122:f9eeca106725 437 /**
Kojto 122:f9eeca106725 438 * @}
Kojto 122:f9eeca106725 439 */
Kojto 122:f9eeca106725 440 #endif /* I2C2 */
Kojto 122:f9eeca106725 441
Kojto 122:f9eeca106725 442 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
Kojto 122:f9eeca106725 443 * @{
Kojto 122:f9eeca106725 444 */
Kojto 122:f9eeca106725 445 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 446 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
Kojto 122:f9eeca106725 447 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
Kojto 122:f9eeca106725 448 /**
Kojto 122:f9eeca106725 449 * @}
Kojto 122:f9eeca106725 450 */
Kojto 122:f9eeca106725 451
Kojto 122:f9eeca106725 452 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
Kojto 122:f9eeca106725 453 * @{
Kojto 122:f9eeca106725 454 */
Kojto 122:f9eeca106725 455 #define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 456 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 457 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0
Kojto 122:f9eeca106725 458 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 459 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1
Kojto 122:f9eeca106725 460 #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL
Kojto 122:f9eeca106725 461 /**
Kojto 122:f9eeca106725 462 * @}
Kojto 122:f9eeca106725 463 */
Kojto 122:f9eeca106725 464
Kojto 122:f9eeca106725 465 #if defined(SAI2)
Kojto 122:f9eeca106725 466 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
Kojto 122:f9eeca106725 467 * @{
Kojto 122:f9eeca106725 468 */
Kojto 122:f9eeca106725 469 #define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 470 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0
Kojto 122:f9eeca106725 471 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1
Kojto 122:f9eeca106725 472 #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL
Kojto 122:f9eeca106725 473 /**
Kojto 122:f9eeca106725 474 * @}
Kojto 122:f9eeca106725 475 */
Kojto 122:f9eeca106725 476 #endif /* SAI2 */
Kojto 122:f9eeca106725 477
Kojto 122:f9eeca106725 478 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
Kojto 122:f9eeca106725 479 * @{
Kojto 122:f9eeca106725 480 */
Kojto 122:f9eeca106725 481 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 482 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
Kojto 122:f9eeca106725 483 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
Kojto 122:f9eeca106725 484 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
Kojto 122:f9eeca106725 485 /**
Kojto 122:f9eeca106725 486 * @}
Kojto 122:f9eeca106725 487 */
Kojto 122:f9eeca106725 488
Kojto 122:f9eeca106725 489 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
Kojto 122:f9eeca106725 490 * @{
Kojto 122:f9eeca106725 491 */
Kojto 122:f9eeca106725 492 #define RCC_LPTIM2CLKSOURCE_PCLK ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 493 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
Kojto 122:f9eeca106725 494 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
Kojto 122:f9eeca106725 495 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
Kojto 122:f9eeca106725 496 /**
Kojto 122:f9eeca106725 497 * @}
Kojto 122:f9eeca106725 498 */
Kojto 122:f9eeca106725 499
Kojto 122:f9eeca106725 500 #if defined(SDMMC1)
Kojto 122:f9eeca106725 501 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source
Kojto 122:f9eeca106725 502 * @{
Kojto 122:f9eeca106725 503 */
Kojto 122:f9eeca106725 504 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 505 #define RCC_SDMMC1CLKSOURCE_HSI48 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 506 #else
Kojto 122:f9eeca106725 507 #define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 508 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 509 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
Kojto 122:f9eeca106725 510 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
Kojto 122:f9eeca106725 511 #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
Kojto 122:f9eeca106725 512 /**
Kojto 122:f9eeca106725 513 * @}
Kojto 122:f9eeca106725 514 */
Kojto 122:f9eeca106725 515 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 516
Kojto 122:f9eeca106725 517 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
Kojto 122:f9eeca106725 518 * @{
Kojto 122:f9eeca106725 519 */
Kojto 122:f9eeca106725 520 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 521 #define RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 522 #else
Kojto 122:f9eeca106725 523 #define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 524 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 525 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
Kojto 122:f9eeca106725 526 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
Kojto 122:f9eeca106725 527 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
Kojto 122:f9eeca106725 528 /**
Kojto 122:f9eeca106725 529 * @}
Kojto 122:f9eeca106725 530 */
Kojto 122:f9eeca106725 531
Kojto 122:f9eeca106725 532 #if defined(USB_OTG_FS) || defined(USB)
Kojto 122:f9eeca106725 533 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source
Kojto 122:f9eeca106725 534 * @{
Kojto 122:f9eeca106725 535 */
Kojto 122:f9eeca106725 536 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 537 #define RCC_USBCLKSOURCE_HSI48 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 538 #else
Kojto 122:f9eeca106725 539 #define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 540 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 541 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
Kojto 122:f9eeca106725 542 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
Kojto 122:f9eeca106725 543 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
Kojto 122:f9eeca106725 544 /**
Kojto 122:f9eeca106725 545 * @}
Kojto 122:f9eeca106725 546 */
Kojto 122:f9eeca106725 547 #endif /* USB_OTG_FS || USB */
Kojto 122:f9eeca106725 548
Kojto 122:f9eeca106725 549 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
Kojto 122:f9eeca106725 550 * @{
Kojto 122:f9eeca106725 551 */
Kojto 122:f9eeca106725 552 #define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 553 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
Kojto 122:f9eeca106725 554 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
Kojto 122:f9eeca106725 555 #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
Kojto 122:f9eeca106725 556 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 122:f9eeca106725 557 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
Kojto 122:f9eeca106725 558 /**
Kojto 122:f9eeca106725 559 * @}
Kojto 122:f9eeca106725 560 */
Kojto 122:f9eeca106725 561
Kojto 122:f9eeca106725 562 #if defined(SWPMI1)
Kojto 122:f9eeca106725 563 /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
Kojto 122:f9eeca106725 564 * @{
Kojto 122:f9eeca106725 565 */
Kojto 122:f9eeca106725 566 #define RCC_SWPMI1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 567 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
Kojto 122:f9eeca106725 568 /**
Kojto 122:f9eeca106725 569 * @}
Kojto 122:f9eeca106725 570 */
Kojto 122:f9eeca106725 571 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 572
Kojto 122:f9eeca106725 573 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 574 /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source
Kojto 122:f9eeca106725 575 * @{
Kojto 122:f9eeca106725 576 */
Kojto 122:f9eeca106725 577 #define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 578 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL
Kojto 122:f9eeca106725 579 /**
Kojto 122:f9eeca106725 580 * @}
Kojto 122:f9eeca106725 581 */
Kojto 122:f9eeca106725 582 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 583
Kojto 122:f9eeca106725 584 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
Kojto 122:f9eeca106725 585 * @{
Kojto 122:f9eeca106725 586 */
Kojto 122:f9eeca106725 587 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
Kojto 122:f9eeca106725 588 /**
Kojto 122:f9eeca106725 589 * @}
Kojto 122:f9eeca106725 590 */
Kojto 122:f9eeca106725 591
Kojto 122:f9eeca106725 592 #if defined(CRS)
Kojto 122:f9eeca106725 593
Kojto 122:f9eeca106725 594 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
Kojto 122:f9eeca106725 595 * @{
Kojto 122:f9eeca106725 596 */
Kojto 122:f9eeca106725 597 #define RCC_CRS_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 598 #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 599 #define RCC_CRS_SYNCOK ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 600 #define RCC_CRS_SYNCWARN ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 601 #define RCC_CRS_SYNCERR ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 602 #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 603 #define RCC_CRS_TRIMOVF ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 604 /**
Kojto 122:f9eeca106725 605 * @}
Kojto 122:f9eeca106725 606 */
Kojto 122:f9eeca106725 607
Kojto 122:f9eeca106725 608 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
Kojto 122:f9eeca106725 609 * @{
Kojto 122:f9eeca106725 610 */
Kojto 122:f9eeca106725 611 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */
Kojto 122:f9eeca106725 612 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
Kojto 122:f9eeca106725 613 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
Kojto 122:f9eeca106725 614 /**
Kojto 122:f9eeca106725 615 * @}
Kojto 122:f9eeca106725 616 */
Kojto 122:f9eeca106725 617
Kojto 122:f9eeca106725 618 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
Kojto 122:f9eeca106725 619 * @{
Kojto 122:f9eeca106725 620 */
Kojto 122:f9eeca106725 621 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */
Kojto 122:f9eeca106725 622 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
Kojto 122:f9eeca106725 623 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
Kojto 122:f9eeca106725 624 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
Kojto 122:f9eeca106725 625 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
Kojto 122:f9eeca106725 626 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
Kojto 122:f9eeca106725 627 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
Kojto 122:f9eeca106725 628 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
Kojto 122:f9eeca106725 629 /**
Kojto 122:f9eeca106725 630 * @}
Kojto 122:f9eeca106725 631 */
Kojto 122:f9eeca106725 632
Kojto 122:f9eeca106725 633 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
Kojto 122:f9eeca106725 634 * @{
Kojto 122:f9eeca106725 635 */
Kojto 122:f9eeca106725 636 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */
Kojto 122:f9eeca106725 637 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
Kojto 122:f9eeca106725 638 /**
Kojto 122:f9eeca106725 639 * @}
Kojto 122:f9eeca106725 640 */
Kojto 122:f9eeca106725 641
Kojto 122:f9eeca106725 642 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
Kojto 122:f9eeca106725 643 * @{
Kojto 122:f9eeca106725 644 */
Kojto 122:f9eeca106725 645 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
Kojto 122:f9eeca106725 646 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
Kojto 122:f9eeca106725 647 /**
Kojto 122:f9eeca106725 648 * @}
Kojto 122:f9eeca106725 649 */
Kojto 122:f9eeca106725 650
Kojto 122:f9eeca106725 651 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
Kojto 122:f9eeca106725 652 * @{
Kojto 122:f9eeca106725 653 */
Kojto 122:f9eeca106725 654 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */
Kojto 122:f9eeca106725 655 /**
Kojto 122:f9eeca106725 656 * @}
Kojto 122:f9eeca106725 657 */
Kojto 122:f9eeca106725 658
Kojto 122:f9eeca106725 659 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
Kojto 122:f9eeca106725 660 * @{
Kojto 122:f9eeca106725 661 */
Kojto 122:f9eeca106725 662 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
Kojto 122:f9eeca106725 663 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
Kojto 122:f9eeca106725 664 corresponds to a higher output frequency */
Kojto 122:f9eeca106725 665 /**
Kojto 122:f9eeca106725 666 * @}
Kojto 122:f9eeca106725 667 */
Kojto 122:f9eeca106725 668
Kojto 122:f9eeca106725 669 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
Kojto 122:f9eeca106725 670 * @{
Kojto 122:f9eeca106725 671 */
Kojto 122:f9eeca106725 672 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */
Kojto 122:f9eeca106725 673 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
Kojto 122:f9eeca106725 674 /**
Kojto 122:f9eeca106725 675 * @}
Kojto 122:f9eeca106725 676 */
Kojto 122:f9eeca106725 677
Kojto 122:f9eeca106725 678 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
Kojto 122:f9eeca106725 679 * @{
Kojto 122:f9eeca106725 680 */
Kojto 122:f9eeca106725 681 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
Kojto 122:f9eeca106725 682 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
Kojto 122:f9eeca106725 683 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
Kojto 122:f9eeca106725 684 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
Kojto 122:f9eeca106725 685 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
Kojto 122:f9eeca106725 686 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
Kojto 122:f9eeca106725 687 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
Kojto 122:f9eeca106725 688
Kojto 122:f9eeca106725 689 /**
Kojto 122:f9eeca106725 690 * @}
Kojto 122:f9eeca106725 691 */
Kojto 122:f9eeca106725 692
Kojto 122:f9eeca106725 693 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
Kojto 122:f9eeca106725 694 * @{
Kojto 122:f9eeca106725 695 */
Kojto 122:f9eeca106725 696 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
Kojto 122:f9eeca106725 697 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
Kojto 122:f9eeca106725 698 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
Kojto 122:f9eeca106725 699 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
Kojto 122:f9eeca106725 700 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
Kojto 122:f9eeca106725 701 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
Kojto 122:f9eeca106725 702 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
Kojto 122:f9eeca106725 703
Kojto 122:f9eeca106725 704 /**
Kojto 122:f9eeca106725 705 * @}
Kojto 122:f9eeca106725 706 */
Kojto 122:f9eeca106725 707
Kojto 122:f9eeca106725 708 #endif /* CRS */
Kojto 122:f9eeca106725 709
Kojto 122:f9eeca106725 710 /**
Kojto 122:f9eeca106725 711 * @}
Kojto 122:f9eeca106725 712 */
Kojto 122:f9eeca106725 713
Kojto 122:f9eeca106725 714 /* Exported macros -----------------------------------------------------------*/
Kojto 122:f9eeca106725 715 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto 122:f9eeca106725 716 * @{
Kojto 122:f9eeca106725 717 */
Kojto 122:f9eeca106725 718
Kojto 122:f9eeca106725 719
Kojto 122:f9eeca106725 720 /**
Kojto 122:f9eeca106725 721 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors.
Kojto 122:f9eeca106725 722 *
Kojto 122:f9eeca106725 723 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 122:f9eeca106725 724 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 725 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 726 *
Kojto 122:f9eeca106725 727 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
Kojto 122:f9eeca106725 728 * This parameter must be a number between 8 and 86.
Kojto 122:f9eeca106725 729 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
Kojto 122:f9eeca106725 730 * output frequency is between 64 and 344 MHz.
Kojto 122:f9eeca106725 731 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
Kojto 122:f9eeca106725 732 *
Kojto 122:f9eeca106725 733 * @param __PLLSAI1P__ specifies the division factor for SAI clock.
Kojto 122:f9eeca106725 734 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
Kojto 122:f9eeca106725 735 * else (2 to 31).
Kojto 122:f9eeca106725 736 * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
Kojto 122:f9eeca106725 737 *
Kojto 122:f9eeca106725 738 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
Kojto 122:f9eeca106725 739 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 740 * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
Kojto 122:f9eeca106725 741 *
Kojto 122:f9eeca106725 742 * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock.
Kojto 122:f9eeca106725 743 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 744 * ADC clock frequency = f(PLLSAI1) / PLLSAI1R
Kojto 122:f9eeca106725 745 *
Kojto 122:f9eeca106725 746 * @retval None
Kojto 122:f9eeca106725 747 */
Kojto 122:f9eeca106725 748 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 749
Kojto 122:f9eeca106725 750 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
Kojto 122:f9eeca106725 751 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
Kojto 122:f9eeca106725 752 ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
Kojto 122:f9eeca106725 753 ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) | \
Kojto 122:f9eeca106725 754 ((__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)))
Kojto 122:f9eeca106725 755
Kojto 122:f9eeca106725 756 #else
Kojto 122:f9eeca106725 757
Kojto 122:f9eeca106725 758 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
Kojto 122:f9eeca106725 759 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
Kojto 122:f9eeca106725 760 (((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \
Kojto 122:f9eeca106725 761 ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
Kojto 122:f9eeca106725 762 ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)))
Kojto 122:f9eeca106725 763
Kojto 122:f9eeca106725 764 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 765
Kojto 122:f9eeca106725 766 /**
Kojto 122:f9eeca106725 767 * @brief Macro to configure the PLLSAI1 clock multiplication factor N.
Kojto 122:f9eeca106725 768 *
Kojto 122:f9eeca106725 769 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 122:f9eeca106725 770 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 771 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 772 *
Kojto 122:f9eeca106725 773 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
Kojto 122:f9eeca106725 774 * This parameter must be a number between 8 and 86.
Kojto 122:f9eeca106725 775 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
Kojto 122:f9eeca106725 776 * output frequency is between 64 and 344 MHz.
Kojto 122:f9eeca106725 777 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
Kojto 122:f9eeca106725 778 *
Kojto 122:f9eeca106725 779 * @retval None
Kojto 122:f9eeca106725 780 */
Kojto 122:f9eeca106725 781 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
Kojto 122:f9eeca106725 782 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))
Kojto 122:f9eeca106725 783
Kojto 122:f9eeca106725 784 /** @brief Macro to configure the PLLSAI1 clock division factor P.
Kojto 122:f9eeca106725 785 *
Kojto 122:f9eeca106725 786 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 122:f9eeca106725 787 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 788 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 789 *
Kojto 122:f9eeca106725 790 * @param __PLLSAI1P__ specifies the division factor for SAI clock.
Kojto 122:f9eeca106725 791 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
Kojto 122:f9eeca106725 792 * else (2 to 31).
Kojto 122:f9eeca106725 793 * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
Kojto 122:f9eeca106725 794 *
Kojto 122:f9eeca106725 795 * @retval None
Kojto 122:f9eeca106725 796 */
Kojto 122:f9eeca106725 797 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 798
Kojto 122:f9eeca106725 799 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
Kojto 122:f9eeca106725 800 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))
Kojto 122:f9eeca106725 801
Kojto 122:f9eeca106725 802 #else
Kojto 122:f9eeca106725 803
Kojto 122:f9eeca106725 804 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
Kojto 122:f9eeca106725 805 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))
Kojto 122:f9eeca106725 806
Kojto 122:f9eeca106725 807 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 808
Kojto 122:f9eeca106725 809 /** @brief Macro to configure the PLLSAI1 clock division factor Q.
Kojto 122:f9eeca106725 810 *
Kojto 122:f9eeca106725 811 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 122:f9eeca106725 812 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 813 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 814 *
Kojto 122:f9eeca106725 815 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
Kojto 122:f9eeca106725 816 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 817 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
Kojto 122:f9eeca106725 818 *
Kojto 122:f9eeca106725 819 * @retval None
Kojto 122:f9eeca106725 820 */
Kojto 122:f9eeca106725 821 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
Kojto 122:f9eeca106725 822 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))
Kojto 122:f9eeca106725 823
Kojto 122:f9eeca106725 824 /** @brief Macro to configure the PLLSAI1 clock division factor R.
Kojto 122:f9eeca106725 825 *
Kojto 122:f9eeca106725 826 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 122:f9eeca106725 827 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 828 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 829 *
Kojto 122:f9eeca106725 830 * @param __PLLSAI1R__ specifies the division factor for ADC clock.
Kojto 122:f9eeca106725 831 * This parameter must be in the range (2, 4, 6 or 8)
Kojto 122:f9eeca106725 832 * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
Kojto 122:f9eeca106725 833 *
Kojto 122:f9eeca106725 834 * @retval None
Kojto 122:f9eeca106725 835 */
Kojto 122:f9eeca106725 836 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
Kojto 122:f9eeca106725 837 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))
Kojto 122:f9eeca106725 838
Kojto 122:f9eeca106725 839 /**
Kojto 122:f9eeca106725 840 * @brief Macros to enable or disable the PLLSAI1.
Kojto 122:f9eeca106725 841 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 842 * @retval None
Kojto 122:f9eeca106725 843 */
Kojto 122:f9eeca106725 844
Kojto 122:f9eeca106725 845 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
Kojto 122:f9eeca106725 846
Kojto 122:f9eeca106725 847 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
Kojto 122:f9eeca106725 848
Kojto 122:f9eeca106725 849 /**
Kojto 122:f9eeca106725 850 * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
Kojto 122:f9eeca106725 851 * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
Kojto 122:f9eeca106725 852 * This is mainly used to save Power.
Kojto 122:f9eeca106725 853 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
Kojto 122:f9eeca106725 854 * This parameter can be one or a combination of the following values:
Kojto 122:f9eeca106725 855 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
Kojto 122:f9eeca106725 856 * high-quality audio performance on SAI interface in case.
Kojto 122:f9eeca106725 857 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
Kojto 122:f9eeca106725 858 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
Kojto 122:f9eeca106725 859 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
Kojto 122:f9eeca106725 860 * @retval None
Kojto 122:f9eeca106725 861 */
Kojto 122:f9eeca106725 862
Kojto 122:f9eeca106725 863 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Kojto 122:f9eeca106725 864
Kojto 122:f9eeca106725 865 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Kojto 122:f9eeca106725 866
Kojto 122:f9eeca106725 867 /**
Kojto 122:f9eeca106725 868 * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
Kojto 122:f9eeca106725 869 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
Kojto 122:f9eeca106725 870 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 871 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
Kojto 122:f9eeca106725 872 * high-quality audio performance on SAI interface in case.
Kojto 122:f9eeca106725 873 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
Kojto 122:f9eeca106725 874 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
Kojto 122:f9eeca106725 875 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
Kojto 122:f9eeca106725 876 * @retval SET / RESET
Kojto 122:f9eeca106725 877 */
Kojto 122:f9eeca106725 878 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Kojto 122:f9eeca106725 879
Kojto 122:f9eeca106725 880 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 881
Kojto 122:f9eeca106725 882 /**
Kojto 122:f9eeca106725 883 * @brief Macro to configure the PLLSAI2 clock multiplication and division factors.
Kojto 122:f9eeca106725 884 *
Kojto 122:f9eeca106725 885 * @note This function must be used only when the PLLSAI2 is disabled.
Kojto 122:f9eeca106725 886 * @note PLLSAI2 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 887 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 888 *
Kojto 122:f9eeca106725 889 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
Kojto 122:f9eeca106725 890 * This parameter must be a number between 8 and 86.
Kojto 122:f9eeca106725 891 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
Kojto 122:f9eeca106725 892 * output frequency is between 64 and 344 MHz.
Kojto 122:f9eeca106725 893 *
Kojto 122:f9eeca106725 894 * @param __PLLSAI2P__ specifies the division factor for SAI clock.
Kojto 122:f9eeca106725 895 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
Kojto 122:f9eeca106725 896 * else (2 to 31).
Kojto 122:f9eeca106725 897 * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P
Kojto 122:f9eeca106725 898 *
Kojto 122:f9eeca106725 899 * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock.
Kojto 122:f9eeca106725 900 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 901 *
Kojto 122:f9eeca106725 902 * @retval None
Kojto 122:f9eeca106725 903 */
Kojto 122:f9eeca106725 904
Kojto 122:f9eeca106725 905 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 906
Kojto 122:f9eeca106725 907 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
Kojto 122:f9eeca106725 908 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
Kojto 122:f9eeca106725 909 ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) | \
Kojto 122:f9eeca106725 910 ((__PLLSAI2P__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV)))
Kojto 122:f9eeca106725 911
Kojto 122:f9eeca106725 912 #else
Kojto 122:f9eeca106725 913
Kojto 122:f9eeca106725 914 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
Kojto 122:f9eeca106725 915 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
Kojto 122:f9eeca106725 916 (((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \
Kojto 122:f9eeca106725 917 ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)))
Kojto 122:f9eeca106725 918
Kojto 122:f9eeca106725 919 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 920
Kojto 122:f9eeca106725 921
Kojto 122:f9eeca106725 922 /**
Kojto 122:f9eeca106725 923 * @brief Macro to configure the PLLSAI2 clock multiplication factor N.
Kojto 122:f9eeca106725 924 *
Kojto 122:f9eeca106725 925 * @note This function must be used only when the PLLSAI2 is disabled.
Kojto 122:f9eeca106725 926 * @note PLLSAI2 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 927 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 928 *
Kojto 122:f9eeca106725 929 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
Kojto 122:f9eeca106725 930 * This parameter must be a number between 8 and 86.
Kojto 122:f9eeca106725 931 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
Kojto 122:f9eeca106725 932 * output frequency is between 64 and 344 MHz.
Kojto 122:f9eeca106725 933 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
Kojto 122:f9eeca106725 934 *
Kojto 122:f9eeca106725 935 * @retval None
Kojto 122:f9eeca106725 936 */
Kojto 122:f9eeca106725 937 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
Kojto 122:f9eeca106725 938 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))
Kojto 122:f9eeca106725 939
Kojto 122:f9eeca106725 940 /** @brief Macro to configure the PLLSAI2 clock division factor P.
Kojto 122:f9eeca106725 941 *
Kojto 122:f9eeca106725 942 * @note This function must be used only when the PLLSAI2 is disabled.
Kojto 122:f9eeca106725 943 * @note PLLSAI2 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 944 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 945 *
Kojto 122:f9eeca106725 946 * @param __PLLSAI2P__ specifies the division factor.
Kojto 122:f9eeca106725 947 * This parameter must be a number in the range (7 or 17).
Kojto 122:f9eeca106725 948 * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
Kojto 122:f9eeca106725 949 *
Kojto 122:f9eeca106725 950 * @retval None
Kojto 122:f9eeca106725 951 */
Kojto 122:f9eeca106725 952 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
Kojto 122:f9eeca106725 953 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))
Kojto 122:f9eeca106725 954
Kojto 122:f9eeca106725 955 /** @brief Macro to configure the PLLSAI2 clock division factor R.
Kojto 122:f9eeca106725 956 *
Kojto 122:f9eeca106725 957 * @note This function must be used only when the PLLSAI2 is disabled.
Kojto 122:f9eeca106725 958 * @note PLLSAI2 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 959 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 960 *
Kojto 122:f9eeca106725 961 * @param __PLLSAI2R__ specifies the division factor.
Kojto 122:f9eeca106725 962 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 963 * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__
Kojto 122:f9eeca106725 964 *
Kojto 122:f9eeca106725 965 * @retval None
Kojto 122:f9eeca106725 966 */
Kojto 122:f9eeca106725 967 #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
Kojto 122:f9eeca106725 968 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))
Kojto 122:f9eeca106725 969
Kojto 122:f9eeca106725 970 /**
Kojto 122:f9eeca106725 971 * @brief Macros to enable or disable the PLLSAI2.
Kojto 122:f9eeca106725 972 * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 973 * @retval None
Kojto 122:f9eeca106725 974 */
Kojto 122:f9eeca106725 975
Kojto 122:f9eeca106725 976 #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
Kojto 122:f9eeca106725 977
Kojto 122:f9eeca106725 978 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
Kojto 122:f9eeca106725 979
Kojto 122:f9eeca106725 980 /**
Kojto 122:f9eeca106725 981 * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).
Kojto 122:f9eeca106725 982 * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
Kojto 122:f9eeca106725 983 * This is mainly used to save Power.
Kojto 122:f9eeca106725 984 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
Kojto 122:f9eeca106725 985 * This parameter can be one or a combination of the following values:
Kojto 122:f9eeca106725 986 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
Kojto 122:f9eeca106725 987 * high-quality audio performance on SAI interface in case.
Kojto 122:f9eeca106725 988 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
Kojto 122:f9eeca106725 989 * @retval None
Kojto 122:f9eeca106725 990 */
Kojto 122:f9eeca106725 991
Kojto 122:f9eeca106725 992 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
Kojto 122:f9eeca106725 993
Kojto 122:f9eeca106725 994 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
Kojto 122:f9eeca106725 995
Kojto 122:f9eeca106725 996 /**
Kojto 122:f9eeca106725 997 * @brief Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).
Kojto 122:f9eeca106725 998 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
Kojto 122:f9eeca106725 999 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1000 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
Kojto 122:f9eeca106725 1001 * high-quality audio performance on SAI interface in case.
Kojto 122:f9eeca106725 1002 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
Kojto 122:f9eeca106725 1003 * @retval SET / RESET
Kojto 122:f9eeca106725 1004 */
Kojto 122:f9eeca106725 1005 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
Kojto 122:f9eeca106725 1006
Kojto 122:f9eeca106725 1007 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 1008
Kojto 122:f9eeca106725 1009 /**
Kojto 122:f9eeca106725 1010 * @brief Macro to configure the SAI1 clock source.
Kojto 122:f9eeca106725 1011 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
Kojto 122:f9eeca106725 1012 * from the PLLSAI1, system PLL or external clock (through a dedicated pin).
Kojto 122:f9eeca106725 1013 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1014 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
Kojto 122:f9eeca106725 1015 @if STM32L486xx
Kojto 122:f9eeca106725 1016 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
Kojto 122:f9eeca106725 1017 @endif
Kojto 122:f9eeca106725 1018 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
Kojto 122:f9eeca106725 1019 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
Kojto 122:f9eeca106725 1020 *
Kojto 122:f9eeca106725 1021 @if STM32L443xx
Kojto 122:f9eeca106725 1022 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
Kojto 122:f9eeca106725 1023 @endif
Kojto 122:f9eeca106725 1024 *
Kojto 122:f9eeca106725 1025 * @retval None
Kojto 122:f9eeca106725 1026 */
Kojto 122:f9eeca106725 1027 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
Kojto 122:f9eeca106725 1028 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
Kojto 122:f9eeca106725 1029
Kojto 122:f9eeca106725 1030 /** @brief Macro to get the SAI1 clock source.
Kojto 122:f9eeca106725 1031 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1032 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
Kojto 122:f9eeca106725 1033 @if STM32L486xx
Kojto 122:f9eeca106725 1034 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
Kojto 122:f9eeca106725 1035 @endif
Kojto 122:f9eeca106725 1036 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
Kojto 122:f9eeca106725 1037 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
Kojto 122:f9eeca106725 1038 *
Kojto 122:f9eeca106725 1039 * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1
Kojto 122:f9eeca106725 1040 * clock source when PLLs are disabled for devices without PLLSAI2.
Kojto 122:f9eeca106725 1041 *
Kojto 122:f9eeca106725 1042 */
Kojto 122:f9eeca106725 1043 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))
Kojto 122:f9eeca106725 1044
Kojto 122:f9eeca106725 1045 #if defined(SAI2)
Kojto 122:f9eeca106725 1046
Kojto 122:f9eeca106725 1047 /**
Kojto 122:f9eeca106725 1048 * @brief Macro to configure the SAI2 clock source.
Kojto 122:f9eeca106725 1049 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
Kojto 122:f9eeca106725 1050 * from the PLLSAI2, system PLL or external clock (through a dedicated pin).
Kojto 122:f9eeca106725 1051 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1052 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
Kojto 122:f9eeca106725 1053 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
Kojto 122:f9eeca106725 1054 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
Kojto 122:f9eeca106725 1055 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
Kojto 122:f9eeca106725 1056 *
Kojto 122:f9eeca106725 1057 * @retval None
Kojto 122:f9eeca106725 1058 */
Kojto 122:f9eeca106725 1059 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
Kojto 122:f9eeca106725 1060 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
Kojto 122:f9eeca106725 1061
Kojto 122:f9eeca106725 1062 /** @brief Macro to get the SAI2 clock source.
Kojto 122:f9eeca106725 1063 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1064 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
Kojto 122:f9eeca106725 1065 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
Kojto 122:f9eeca106725 1066 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
Kojto 122:f9eeca106725 1067 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
Kojto 122:f9eeca106725 1068 */
Kojto 122:f9eeca106725 1069 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))
Kojto 122:f9eeca106725 1070
Kojto 122:f9eeca106725 1071 #endif /* SAI2 */
Kojto 122:f9eeca106725 1072
Kojto 122:f9eeca106725 1073 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
Kojto 122:f9eeca106725 1074 *
Kojto 122:f9eeca106725 1075 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
Kojto 122:f9eeca106725 1076 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1077 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
Kojto 122:f9eeca106725 1078 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
Kojto 122:f9eeca106725 1079 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
Kojto 122:f9eeca106725 1080 * @retval None
Kojto 122:f9eeca106725 1081 */
Kojto 122:f9eeca106725 1082 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1083 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
Kojto 122:f9eeca106725 1084
Kojto 122:f9eeca106725 1085 /** @brief Macro to get the I2C1 clock source.
Kojto 122:f9eeca106725 1086 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1087 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
Kojto 122:f9eeca106725 1088 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
Kojto 122:f9eeca106725 1089 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
Kojto 122:f9eeca106725 1090 */
Kojto 122:f9eeca106725 1091 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
Kojto 122:f9eeca106725 1092
Kojto 122:f9eeca106725 1093 #if defined(I2C2)
Kojto 122:f9eeca106725 1094
Kojto 122:f9eeca106725 1095 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto 122:f9eeca106725 1096 *
Kojto 122:f9eeca106725 1097 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
Kojto 122:f9eeca106725 1098 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1099 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
Kojto 122:f9eeca106725 1100 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
Kojto 122:f9eeca106725 1101 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
Kojto 122:f9eeca106725 1102 * @retval None
Kojto 122:f9eeca106725 1103 */
Kojto 122:f9eeca106725 1104 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
Kojto 122:f9eeca106725 1105 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
Kojto 122:f9eeca106725 1106
Kojto 122:f9eeca106725 1107 /** @brief Macro to get the I2C2 clock source.
Kojto 122:f9eeca106725 1108 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1109 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
Kojto 122:f9eeca106725 1110 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
Kojto 122:f9eeca106725 1111 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
Kojto 122:f9eeca106725 1112 */
Kojto 122:f9eeca106725 1113 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
Kojto 122:f9eeca106725 1114
Kojto 122:f9eeca106725 1115 #endif /* I2C2 */
Kojto 122:f9eeca106725 1116
Kojto 122:f9eeca106725 1117 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto 122:f9eeca106725 1118 *
Kojto 122:f9eeca106725 1119 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
Kojto 122:f9eeca106725 1120 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1121 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
Kojto 122:f9eeca106725 1122 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
Kojto 122:f9eeca106725 1123 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
Kojto 122:f9eeca106725 1124 * @retval None
Kojto 122:f9eeca106725 1125 */
Kojto 122:f9eeca106725 1126 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
Kojto 122:f9eeca106725 1127 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
Kojto 122:f9eeca106725 1128
Kojto 122:f9eeca106725 1129 /** @brief Macro to get the I2C3 clock source.
Kojto 122:f9eeca106725 1130 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1131 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
Kojto 122:f9eeca106725 1132 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
Kojto 122:f9eeca106725 1133 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
Kojto 122:f9eeca106725 1134 */
Kojto 122:f9eeca106725 1135 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
Kojto 122:f9eeca106725 1136
Kojto 122:f9eeca106725 1137 /** @brief Macro to configure the USART1 clock (USART1CLK).
Kojto 122:f9eeca106725 1138 *
Kojto 122:f9eeca106725 1139 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
Kojto 122:f9eeca106725 1140 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1141 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto 122:f9eeca106725 1142 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
Kojto 122:f9eeca106725 1143 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
Kojto 122:f9eeca106725 1144 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock
Kojto 122:f9eeca106725 1145 * @retval None
Kojto 122:f9eeca106725 1146 */
Kojto 122:f9eeca106725 1147 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1148 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
Kojto 122:f9eeca106725 1149
Kojto 122:f9eeca106725 1150 /** @brief Macro to get the USART1 clock source.
Kojto 122:f9eeca106725 1151 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1152 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto 122:f9eeca106725 1153 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
Kojto 122:f9eeca106725 1154 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
Kojto 122:f9eeca106725 1155 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
Kojto 122:f9eeca106725 1156 */
Kojto 122:f9eeca106725 1157 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
Kojto 122:f9eeca106725 1158
Kojto 122:f9eeca106725 1159 /** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto 122:f9eeca106725 1160 *
Kojto 122:f9eeca106725 1161 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
Kojto 122:f9eeca106725 1162 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1163 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
Kojto 122:f9eeca106725 1164 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
Kojto 122:f9eeca106725 1165 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
Kojto 122:f9eeca106725 1166 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
Kojto 122:f9eeca106725 1167 * @retval None
Kojto 122:f9eeca106725 1168 */
Kojto 122:f9eeca106725 1169 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
Kojto 122:f9eeca106725 1170 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
Kojto 122:f9eeca106725 1171
Kojto 122:f9eeca106725 1172 /** @brief Macro to get the USART2 clock source.
Kojto 122:f9eeca106725 1173 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1174 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
Kojto 122:f9eeca106725 1175 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
Kojto 122:f9eeca106725 1176 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
Kojto 122:f9eeca106725 1177 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
Kojto 122:f9eeca106725 1178 */
Kojto 122:f9eeca106725 1179 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
Kojto 122:f9eeca106725 1180
Kojto 122:f9eeca106725 1181 #if defined(USART3)
Kojto 122:f9eeca106725 1182
Kojto 122:f9eeca106725 1183 /** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto 122:f9eeca106725 1184 *
Kojto 122:f9eeca106725 1185 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
Kojto 122:f9eeca106725 1186 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1187 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
Kojto 122:f9eeca106725 1188 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
Kojto 122:f9eeca106725 1189 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
Kojto 122:f9eeca106725 1190 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
Kojto 122:f9eeca106725 1191 * @retval None
Kojto 122:f9eeca106725 1192 */
Kojto 122:f9eeca106725 1193 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
Kojto 122:f9eeca106725 1194 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
Kojto 122:f9eeca106725 1195
Kojto 122:f9eeca106725 1196 /** @brief Macro to get the USART3 clock source.
Kojto 122:f9eeca106725 1197 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1198 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
Kojto 122:f9eeca106725 1199 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
Kojto 122:f9eeca106725 1200 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
Kojto 122:f9eeca106725 1201 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
Kojto 122:f9eeca106725 1202 */
Kojto 122:f9eeca106725 1203 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
Kojto 122:f9eeca106725 1204
Kojto 122:f9eeca106725 1205 #endif /* USART3 */
Kojto 122:f9eeca106725 1206
Kojto 122:f9eeca106725 1207 #if defined(UART4)
Kojto 122:f9eeca106725 1208
Kojto 122:f9eeca106725 1209 /** @brief Macro to configure the UART4 clock (UART4CLK).
Kojto 122:f9eeca106725 1210 *
Kojto 122:f9eeca106725 1211 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
Kojto 122:f9eeca106725 1212 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1213 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
Kojto 122:f9eeca106725 1214 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
Kojto 122:f9eeca106725 1215 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
Kojto 122:f9eeca106725 1216 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
Kojto 122:f9eeca106725 1217 * @retval None
Kojto 122:f9eeca106725 1218 */
Kojto 122:f9eeca106725 1219 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
Kojto 122:f9eeca106725 1220 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
Kojto 122:f9eeca106725 1221
Kojto 122:f9eeca106725 1222 /** @brief Macro to get the UART4 clock source.
Kojto 122:f9eeca106725 1223 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1224 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
Kojto 122:f9eeca106725 1225 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
Kojto 122:f9eeca106725 1226 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
Kojto 122:f9eeca106725 1227 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
Kojto 122:f9eeca106725 1228 */
Kojto 122:f9eeca106725 1229 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))
Kojto 122:f9eeca106725 1230
Kojto 122:f9eeca106725 1231 #endif /* UART4 */
Kojto 122:f9eeca106725 1232
Kojto 122:f9eeca106725 1233 #if defined(UART5)
Kojto 122:f9eeca106725 1234
Kojto 122:f9eeca106725 1235 /** @brief Macro to configure the UART5 clock (UART5CLK).
Kojto 122:f9eeca106725 1236 *
Kojto 122:f9eeca106725 1237 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
Kojto 122:f9eeca106725 1238 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1239 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
Kojto 122:f9eeca106725 1240 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
Kojto 122:f9eeca106725 1241 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
Kojto 122:f9eeca106725 1242 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
Kojto 122:f9eeca106725 1243 * @retval None
Kojto 122:f9eeca106725 1244 */
Kojto 122:f9eeca106725 1245 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
Kojto 122:f9eeca106725 1246 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
Kojto 122:f9eeca106725 1247
Kojto 122:f9eeca106725 1248 /** @brief Macro to get the UART5 clock source.
Kojto 122:f9eeca106725 1249 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1250 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
Kojto 122:f9eeca106725 1251 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
Kojto 122:f9eeca106725 1252 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
Kojto 122:f9eeca106725 1253 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
Kojto 122:f9eeca106725 1254 */
Kojto 122:f9eeca106725 1255 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))
Kojto 122:f9eeca106725 1256
Kojto 122:f9eeca106725 1257 #endif /* UART5 */
Kojto 122:f9eeca106725 1258
Kojto 122:f9eeca106725 1259 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
Kojto 122:f9eeca106725 1260 *
Kojto 122:f9eeca106725 1261 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
Kojto 122:f9eeca106725 1262 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1263 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
Kojto 122:f9eeca106725 1264 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
Kojto 122:f9eeca106725 1265 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
Kojto 122:f9eeca106725 1266 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
Kojto 122:f9eeca106725 1267 * @retval None
Kojto 122:f9eeca106725 1268 */
Kojto 122:f9eeca106725 1269 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1270 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
Kojto 122:f9eeca106725 1271
Kojto 122:f9eeca106725 1272 /** @brief Macro to get the LPUART1 clock source.
Kojto 122:f9eeca106725 1273 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1274 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
Kojto 122:f9eeca106725 1275 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
Kojto 122:f9eeca106725 1276 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
Kojto 122:f9eeca106725 1277 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
Kojto 122:f9eeca106725 1278 */
Kojto 122:f9eeca106725 1279 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
Kojto 122:f9eeca106725 1280
Kojto 122:f9eeca106725 1281 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
Kojto 122:f9eeca106725 1282 *
Kojto 122:f9eeca106725 1283 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
Kojto 122:f9eeca106725 1284 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1285 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPTIM1 clock
Kojto 122:f9eeca106725 1286 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
Kojto 122:f9eeca106725 1287 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
Kojto 122:f9eeca106725 1288 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
Kojto 122:f9eeca106725 1289 * @retval None
Kojto 122:f9eeca106725 1290 */
Kojto 122:f9eeca106725 1291 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1292 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
Kojto 122:f9eeca106725 1293
Kojto 122:f9eeca106725 1294 /** @brief Macro to get the LPTIM1 clock source.
Kojto 122:f9eeca106725 1295 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1296 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPUART1 clock
Kojto 122:f9eeca106725 1297 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
Kojto 122:f9eeca106725 1298 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
Kojto 122:f9eeca106725 1299 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
Kojto 122:f9eeca106725 1300 */
Kojto 122:f9eeca106725 1301 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
Kojto 122:f9eeca106725 1302
Kojto 122:f9eeca106725 1303 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK).
Kojto 122:f9eeca106725 1304 *
Kojto 122:f9eeca106725 1305 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
Kojto 122:f9eeca106725 1306 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1307 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK PCLK selected as LPTIM2 clock
Kojto 122:f9eeca106725 1308 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
Kojto 122:f9eeca106725 1309 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock
Kojto 122:f9eeca106725 1310 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
Kojto 122:f9eeca106725 1311 * @retval None
Kojto 122:f9eeca106725 1312 */
Kojto 122:f9eeca106725 1313 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
Kojto 122:f9eeca106725 1314 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
Kojto 122:f9eeca106725 1315
Kojto 122:f9eeca106725 1316 /** @brief Macro to get the LPTIM2 clock source.
Kojto 122:f9eeca106725 1317 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1318 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK PCLK selected as LPUART1 clock
Kojto 122:f9eeca106725 1319 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock
Kojto 122:f9eeca106725 1320 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock
Kojto 122:f9eeca106725 1321 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock
Kojto 122:f9eeca106725 1322 */
Kojto 122:f9eeca106725 1323 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
Kojto 122:f9eeca106725 1324
Kojto 122:f9eeca106725 1325 #if defined(SDMMC1)
Kojto 122:f9eeca106725 1326
Kojto 122:f9eeca106725 1327 /** @brief Macro to configure the SDMMC1 clock.
Kojto 122:f9eeca106725 1328 *
Kojto 122:f9eeca106725 1329 @if STM32L486xx
Kojto 122:f9eeca106725 1330 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Kojto 122:f9eeca106725 1331 @endif
Kojto 122:f9eeca106725 1332 *
Kojto 122:f9eeca106725 1333 @if STM32L443xx
Kojto 122:f9eeca106725 1334 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Kojto 122:f9eeca106725 1335 @endif
Kojto 122:f9eeca106725 1336 *
Kojto 122:f9eeca106725 1337 * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
Kojto 122:f9eeca106725 1338 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1339 @if STM32L486xx
Kojto 122:f9eeca106725 1340 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
Kojto 122:f9eeca106725 1341 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
Kojto 122:f9eeca106725 1342 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
Kojto 122:f9eeca106725 1343 @endif
Kojto 122:f9eeca106725 1344 @if STM32L443xx
Kojto 122:f9eeca106725 1345 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
Kojto 122:f9eeca106725 1346 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
Kojto 122:f9eeca106725 1347 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
Kojto 122:f9eeca106725 1348 @endif
Kojto 122:f9eeca106725 1349 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
Kojto 122:f9eeca106725 1350 * @retval None
Kojto 122:f9eeca106725 1351 */
Kojto 122:f9eeca106725 1352 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1353 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
Kojto 122:f9eeca106725 1354
Kojto 122:f9eeca106725 1355 /** @brief Macro to get the SDMMC1 clock.
Kojto 122:f9eeca106725 1356 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1357 @if STM32L486xx
Kojto 122:f9eeca106725 1358 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
Kojto 122:f9eeca106725 1359 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
Kojto 122:f9eeca106725 1360 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
Kojto 122:f9eeca106725 1361 @endif
Kojto 122:f9eeca106725 1362 @if STM32L443xx
Kojto 122:f9eeca106725 1363 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
Kojto 122:f9eeca106725 1364 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
Kojto 122:f9eeca106725 1365 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
Kojto 122:f9eeca106725 1366 @endif
Kojto 122:f9eeca106725 1367 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
Kojto 122:f9eeca106725 1368 */
Kojto 122:f9eeca106725 1369 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Kojto 122:f9eeca106725 1370
Kojto 122:f9eeca106725 1371 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 1372
Kojto 122:f9eeca106725 1373 /** @brief Macro to configure the RNG clock.
Kojto 122:f9eeca106725 1374 *
Kojto 122:f9eeca106725 1375 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Kojto 122:f9eeca106725 1376 *
Kojto 122:f9eeca106725 1377 * @param __RNG_CLKSOURCE__ specifies the RNG clock source.
Kojto 122:f9eeca106725 1378 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1379 @if STM32L486xx
Kojto 122:f9eeca106725 1380 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
Kojto 122:f9eeca106725 1381 @endif
Kojto 122:f9eeca106725 1382 @if STM32L443xx
Kojto 122:f9eeca106725 1383 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
Kojto 122:f9eeca106725 1384 @endif
Kojto 122:f9eeca106725 1385 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
Kojto 122:f9eeca106725 1386 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock
Kojto 122:f9eeca106725 1387 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
Kojto 122:f9eeca106725 1388 * @retval None
Kojto 122:f9eeca106725 1389 */
Kojto 122:f9eeca106725 1390 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
Kojto 122:f9eeca106725 1391 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))
Kojto 122:f9eeca106725 1392
Kojto 122:f9eeca106725 1393 /** @brief Macro to get the RNG clock.
Kojto 122:f9eeca106725 1394 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1395 @if STM32L486xx
Kojto 122:f9eeca106725 1396 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
Kojto 122:f9eeca106725 1397 @endif
Kojto 122:f9eeca106725 1398 @if STM32L443xx
Kojto 122:f9eeca106725 1399 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
Kojto 122:f9eeca106725 1400 @endif
Kojto 122:f9eeca106725 1401 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
Kojto 122:f9eeca106725 1402 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
Kojto 122:f9eeca106725 1403 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock
Kojto 122:f9eeca106725 1404 */
Kojto 122:f9eeca106725 1405 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Kojto 122:f9eeca106725 1406
Kojto 122:f9eeca106725 1407 #if defined(USB_OTG_FS) || defined(USB)
Kojto 122:f9eeca106725 1408
Kojto 122:f9eeca106725 1409 /** @brief Macro to configure the USB clock (USBCLK).
Kojto 122:f9eeca106725 1410 *
Kojto 122:f9eeca106725 1411 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Kojto 122:f9eeca106725 1412 *
Kojto 122:f9eeca106725 1413 * @param __USB_CLKSOURCE__ specifies the USB clock source.
Kojto 122:f9eeca106725 1414 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1415 @if STM32L486xx
Kojto 122:f9eeca106725 1416 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
Kojto 122:f9eeca106725 1417 @endif
Kojto 122:f9eeca106725 1418 @if STM32L443xx
Kojto 122:f9eeca106725 1419 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
Kojto 122:f9eeca106725 1420 @endif
Kojto 122:f9eeca106725 1421 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
Kojto 122:f9eeca106725 1422 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
Kojto 122:f9eeca106725 1423 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
Kojto 122:f9eeca106725 1424 * @retval None
Kojto 122:f9eeca106725 1425 */
Kojto 122:f9eeca106725 1426 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
Kojto 122:f9eeca106725 1427 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))
Kojto 122:f9eeca106725 1428
Kojto 122:f9eeca106725 1429 /** @brief Macro to get the USB clock source.
Kojto 122:f9eeca106725 1430 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1431 @if STM32L486xx
Kojto 122:f9eeca106725 1432 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
Kojto 122:f9eeca106725 1433 @endif
Kojto 122:f9eeca106725 1434 @if STM32L443xx
Kojto 122:f9eeca106725 1435 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
Kojto 122:f9eeca106725 1436 @endif
Kojto 122:f9eeca106725 1437 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
Kojto 122:f9eeca106725 1438 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
Kojto 122:f9eeca106725 1439 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
Kojto 122:f9eeca106725 1440 */
Kojto 122:f9eeca106725 1441 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Kojto 122:f9eeca106725 1442
Kojto 122:f9eeca106725 1443 #endif /* USB_OTG_FS || USB */
Kojto 122:f9eeca106725 1444
Kojto 122:f9eeca106725 1445 /** @brief Macro to configure the ADC interface clock.
Kojto 122:f9eeca106725 1446 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
Kojto 122:f9eeca106725 1447 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1448 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
Kojto 122:f9eeca106725 1449 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
Kojto 122:f9eeca106725 1450 @if STM32L486xx
Kojto 122:f9eeca106725 1451 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
Kojto 122:f9eeca106725 1452 @endif
Kojto 122:f9eeca106725 1453 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
Kojto 122:f9eeca106725 1454 * @retval None
Kojto 122:f9eeca106725 1455 */
Kojto 122:f9eeca106725 1456 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
Kojto 122:f9eeca106725 1457 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
Kojto 122:f9eeca106725 1458
Kojto 122:f9eeca106725 1459 /** @brief Macro to get the ADC clock source.
Kojto 122:f9eeca106725 1460 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1461 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
Kojto 122:f9eeca106725 1462 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
Kojto 122:f9eeca106725 1463 @if STM32L486xx
Kojto 122:f9eeca106725 1464 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
Kojto 122:f9eeca106725 1465 @endif
Kojto 122:f9eeca106725 1466 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
Kojto 122:f9eeca106725 1467 */
Kojto 122:f9eeca106725 1468 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
Kojto 122:f9eeca106725 1469
Kojto 122:f9eeca106725 1470 #if defined(SWPMI1)
Kojto 122:f9eeca106725 1471
Kojto 122:f9eeca106725 1472 /** @brief Macro to configure the SWPMI1 clock.
Kojto 122:f9eeca106725 1473 * @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.
Kojto 122:f9eeca106725 1474 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1475 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK PCLK Clock selected as SWPMI1 clock
Kojto 122:f9eeca106725 1476 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
Kojto 122:f9eeca106725 1477 * @retval None
Kojto 122:f9eeca106725 1478 */
Kojto 122:f9eeca106725 1479 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1480 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))
Kojto 122:f9eeca106725 1481
Kojto 122:f9eeca106725 1482 /** @brief Macro to get the SWPMI1 clock source.
Kojto 122:f9eeca106725 1483 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1484 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK PCLK Clock selected as SWPMI1 clock
Kojto 122:f9eeca106725 1485 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
Kojto 122:f9eeca106725 1486 */
Kojto 122:f9eeca106725 1487 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))
Kojto 122:f9eeca106725 1488
Kojto 122:f9eeca106725 1489 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 1490
Kojto 122:f9eeca106725 1491 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 1492 /** @brief Macro to configure the DFSDM1 clock.
Kojto 122:f9eeca106725 1493 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
Kojto 122:f9eeca106725 1494 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1495 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK PCLK Clock selected as DFSDM1 clock
Kojto 122:f9eeca106725 1496 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
Kojto 122:f9eeca106725 1497 * @retval None
Kojto 122:f9eeca106725 1498 */
Kojto 122:f9eeca106725 1499 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1500 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
Kojto 122:f9eeca106725 1501
Kojto 122:f9eeca106725 1502 /** @brief Macro to get the DFSDM1 clock source.
Kojto 122:f9eeca106725 1503 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1504 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK PCLK Clock selected as DFSDM1 clock
Kojto 122:f9eeca106725 1505 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
Kojto 122:f9eeca106725 1506 */
Kojto 122:f9eeca106725 1507 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)))
Kojto 122:f9eeca106725 1508
Kojto 122:f9eeca106725 1509 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 1510
Kojto 122:f9eeca106725 1511
Kojto 122:f9eeca106725 1512 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
Kojto 122:f9eeca106725 1513 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 122:f9eeca106725 1514 * @{
Kojto 122:f9eeca106725 1515 */
Kojto 122:f9eeca106725 1516
Kojto 122:f9eeca106725 1517 /** @brief Enable PLLSAI1RDY interrupt.
Kojto 122:f9eeca106725 1518 * @retval None
Kojto 122:f9eeca106725 1519 */
Kojto 122:f9eeca106725 1520 #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
Kojto 122:f9eeca106725 1521
Kojto 122:f9eeca106725 1522 /** @brief Disable PLLSAI1RDY interrupt.
Kojto 122:f9eeca106725 1523 * @retval None
Kojto 122:f9eeca106725 1524 */
Kojto 122:f9eeca106725 1525 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
Kojto 122:f9eeca106725 1526
Kojto 122:f9eeca106725 1527 /** @brief Clear the PLLSAI1RDY interrupt pending bit.
Kojto 122:f9eeca106725 1528 * @retval None
Kojto 122:f9eeca106725 1529 */
Kojto 122:f9eeca106725 1530 #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
Kojto 122:f9eeca106725 1531
Kojto 122:f9eeca106725 1532 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
Kojto 122:f9eeca106725 1533 * @retval TRUE or FALSE.
Kojto 122:f9eeca106725 1534 */
Kojto 122:f9eeca106725 1535 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
Kojto 122:f9eeca106725 1536
Kojto 122:f9eeca106725 1537 /** @brief Check whether the PLLSAI1RDY flag is set or not.
Kojto 122:f9eeca106725 1538 * @retval TRUE or FALSE.
Kojto 122:f9eeca106725 1539 */
Kojto 122:f9eeca106725 1540 #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
Kojto 122:f9eeca106725 1541
Kojto 122:f9eeca106725 1542 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 1543
Kojto 122:f9eeca106725 1544 /** @brief Enable PLLSAI2RDY interrupt.
Kojto 122:f9eeca106725 1545 * @retval None
Kojto 122:f9eeca106725 1546 */
Kojto 122:f9eeca106725 1547 #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
Kojto 122:f9eeca106725 1548
Kojto 122:f9eeca106725 1549 /** @brief Disable PLLSAI2RDY interrupt.
Kojto 122:f9eeca106725 1550 * @retval None
Kojto 122:f9eeca106725 1551 */
Kojto 122:f9eeca106725 1552 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
Kojto 122:f9eeca106725 1553
Kojto 122:f9eeca106725 1554 /** @brief Clear the PLLSAI2RDY interrupt pending bit.
Kojto 122:f9eeca106725 1555 * @retval None
Kojto 122:f9eeca106725 1556 */
Kojto 122:f9eeca106725 1557 #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
Kojto 122:f9eeca106725 1558
Kojto 122:f9eeca106725 1559 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.
Kojto 122:f9eeca106725 1560 * @retval TRUE or FALSE.
Kojto 122:f9eeca106725 1561 */
Kojto 122:f9eeca106725 1562 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
Kojto 122:f9eeca106725 1563
Kojto 122:f9eeca106725 1564 /** @brief Check whether the PLLSAI2RDY flag is set or not.
Kojto 122:f9eeca106725 1565 * @retval TRUE or FALSE.
Kojto 122:f9eeca106725 1566 */
Kojto 122:f9eeca106725 1567 #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
Kojto 122:f9eeca106725 1568
Kojto 122:f9eeca106725 1569 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 1570
Kojto 122:f9eeca106725 1571
Kojto 122:f9eeca106725 1572 /**
Kojto 122:f9eeca106725 1573 * @brief Enable the RCC LSE CSS Extended Interrupt Line.
Kojto 122:f9eeca106725 1574 * @retval None
Kojto 122:f9eeca106725 1575 */
Kojto 122:f9eeca106725 1576 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1577
Kojto 122:f9eeca106725 1578 /**
Kojto 122:f9eeca106725 1579 * @brief Disable the RCC LSE CSS Extended Interrupt Line.
Kojto 122:f9eeca106725 1580 * @retval None
Kojto 122:f9eeca106725 1581 */
Kojto 122:f9eeca106725 1582 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1583
Kojto 122:f9eeca106725 1584 /**
Kojto 122:f9eeca106725 1585 * @brief Enable the RCC LSE CSS Event Line.
Kojto 122:f9eeca106725 1586 * @retval None.
Kojto 122:f9eeca106725 1587 */
Kojto 122:f9eeca106725 1588 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1589
Kojto 122:f9eeca106725 1590 /**
Kojto 122:f9eeca106725 1591 * @brief Disable the RCC LSE CSS Event Line.
Kojto 122:f9eeca106725 1592 * @retval None.
Kojto 122:f9eeca106725 1593 */
Kojto 122:f9eeca106725 1594 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1595
Kojto 122:f9eeca106725 1596
Kojto 122:f9eeca106725 1597 /**
Kojto 122:f9eeca106725 1598 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
Kojto 122:f9eeca106725 1599 * @retval None.
Kojto 122:f9eeca106725 1600 */
Kojto 122:f9eeca106725 1601 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1602
Kojto 122:f9eeca106725 1603
Kojto 122:f9eeca106725 1604 /**
Kojto 122:f9eeca106725 1605 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
Kojto 122:f9eeca106725 1606 * @retval None.
Kojto 122:f9eeca106725 1607 */
Kojto 122:f9eeca106725 1608 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1609
Kojto 122:f9eeca106725 1610
Kojto 122:f9eeca106725 1611 /**
Kojto 122:f9eeca106725 1612 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
Kojto 122:f9eeca106725 1613 * @retval None.
Kojto 122:f9eeca106725 1614 */
Kojto 122:f9eeca106725 1615 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1616
Kojto 122:f9eeca106725 1617 /**
Kojto 122:f9eeca106725 1618 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
Kojto 122:f9eeca106725 1619 * @retval None.
Kojto 122:f9eeca106725 1620 */
Kojto 122:f9eeca106725 1621 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1622
Kojto 122:f9eeca106725 1623 /**
Kojto 122:f9eeca106725 1624 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
Kojto 122:f9eeca106725 1625 * @retval None.
Kojto 122:f9eeca106725 1626 */
Kojto 122:f9eeca106725 1627 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 1628 do { \
Kojto 122:f9eeca106725 1629 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 1630 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 1631 } while(0)
Kojto 122:f9eeca106725 1632
Kojto 122:f9eeca106725 1633 /**
Kojto 122:f9eeca106725 1634 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
Kojto 122:f9eeca106725 1635 * @retval None.
Kojto 122:f9eeca106725 1636 */
Kojto 122:f9eeca106725 1637 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 1638 do { \
Kojto 122:f9eeca106725 1639 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 1640 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 1641 } while(0)
Kojto 122:f9eeca106725 1642
Kojto 122:f9eeca106725 1643 /**
Kojto 122:f9eeca106725 1644 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
Kojto 122:f9eeca106725 1645 * @retval EXTI RCC LSE CSS Line Status.
Kojto 122:f9eeca106725 1646 */
Kojto 122:f9eeca106725 1647 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1648
Kojto 122:f9eeca106725 1649 /**
Kojto 122:f9eeca106725 1650 * @brief Clear the RCC LSE CSS EXTI flag.
Kojto 122:f9eeca106725 1651 * @retval None.
Kojto 122:f9eeca106725 1652 */
Kojto 122:f9eeca106725 1653 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1654
Kojto 122:f9eeca106725 1655 /**
Kojto 122:f9eeca106725 1656 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
Kojto 122:f9eeca106725 1657 * @retval None.
Kojto 122:f9eeca106725 1658 */
Kojto 122:f9eeca106725 1659 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1660
Kojto 122:f9eeca106725 1661
Kojto 122:f9eeca106725 1662 #if defined(CRS)
Kojto 122:f9eeca106725 1663
Kojto 122:f9eeca106725 1664 /**
Kojto 122:f9eeca106725 1665 * @brief Enable the specified CRS interrupts.
Kojto 122:f9eeca106725 1666 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
Kojto 122:f9eeca106725 1667 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 1668 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
Kojto 122:f9eeca106725 1669 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
Kojto 122:f9eeca106725 1670 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
Kojto 122:f9eeca106725 1671 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
Kojto 122:f9eeca106725 1672 * @retval None
Kojto 122:f9eeca106725 1673 */
Kojto 122:f9eeca106725 1674 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
Kojto 122:f9eeca106725 1675
Kojto 122:f9eeca106725 1676 /**
Kojto 122:f9eeca106725 1677 * @brief Disable the specified CRS interrupts.
Kojto 122:f9eeca106725 1678 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
Kojto 122:f9eeca106725 1679 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 1680 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
Kojto 122:f9eeca106725 1681 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
Kojto 122:f9eeca106725 1682 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
Kojto 122:f9eeca106725 1683 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
Kojto 122:f9eeca106725 1684 * @retval None
Kojto 122:f9eeca106725 1685 */
Kojto 122:f9eeca106725 1686 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
Kojto 122:f9eeca106725 1687
Kojto 122:f9eeca106725 1688 /** @brief Check whether the CRS interrupt has occurred or not.
Kojto 122:f9eeca106725 1689 * @param __INTERRUPT__ specifies the CRS interrupt source to check.
Kojto 122:f9eeca106725 1690 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1691 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
Kojto 122:f9eeca106725 1692 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
Kojto 122:f9eeca106725 1693 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
Kojto 122:f9eeca106725 1694 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
Kojto 122:f9eeca106725 1695 * @retval The new state of __INTERRUPT__ (SET or RESET).
Kojto 122:f9eeca106725 1696 */
Kojto 122:f9eeca106725 1697 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
Kojto 122:f9eeca106725 1698
Kojto 122:f9eeca106725 1699 /** @brief Clear the CRS interrupt pending bits
Kojto 122:f9eeca106725 1700 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
Kojto 122:f9eeca106725 1701 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 1702 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
Kojto 122:f9eeca106725 1703 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
Kojto 122:f9eeca106725 1704 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
Kojto 122:f9eeca106725 1705 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
Kojto 122:f9eeca106725 1706 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
Kojto 122:f9eeca106725 1707 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
Kojto 122:f9eeca106725 1708 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
Kojto 122:f9eeca106725 1709 */
Kojto 122:f9eeca106725 1710 /* CRS IT Error Mask */
Kojto 122:f9eeca106725 1711 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
Kojto 122:f9eeca106725 1712
Kojto 122:f9eeca106725 1713 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
Kojto 122:f9eeca106725 1714 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
Kojto 122:f9eeca106725 1715 { \
Kojto 122:f9eeca106725 1716 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
Kojto 122:f9eeca106725 1717 } \
Kojto 122:f9eeca106725 1718 else \
Kojto 122:f9eeca106725 1719 { \
Kojto 122:f9eeca106725 1720 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
Kojto 122:f9eeca106725 1721 } \
Kojto 122:f9eeca106725 1722 } while(0)
Kojto 122:f9eeca106725 1723
Kojto 122:f9eeca106725 1724 /**
Kojto 122:f9eeca106725 1725 * @brief Check whether the specified CRS flag is set or not.
Kojto 122:f9eeca106725 1726 * @param __FLAG__ specifies the flag to check.
Kojto 122:f9eeca106725 1727 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1728 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
Kojto 122:f9eeca106725 1729 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
Kojto 122:f9eeca106725 1730 * @arg @ref RCC_CRS_FLAG_ERR Error
Kojto 122:f9eeca106725 1731 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
Kojto 122:f9eeca106725 1732 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
Kojto 122:f9eeca106725 1733 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
Kojto 122:f9eeca106725 1734 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
Kojto 122:f9eeca106725 1735 * @retval The new state of _FLAG_ (TRUE or FALSE).
Kojto 122:f9eeca106725 1736 */
Kojto 122:f9eeca106725 1737 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
Kojto 122:f9eeca106725 1738
Kojto 122:f9eeca106725 1739 /**
Kojto 122:f9eeca106725 1740 * @brief Clear the CRS specified FLAG.
Kojto 122:f9eeca106725 1741 * @param __FLAG__ specifies the flag to clear.
Kojto 122:f9eeca106725 1742 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1743 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
Kojto 122:f9eeca106725 1744 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
Kojto 122:f9eeca106725 1745 * @arg @ref RCC_CRS_FLAG_ERR Error
Kojto 122:f9eeca106725 1746 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
Kojto 122:f9eeca106725 1747 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
Kojto 122:f9eeca106725 1748 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
Kojto 122:f9eeca106725 1749 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
Kojto 122:f9eeca106725 1750 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
Kojto 122:f9eeca106725 1751 * @retval None
Kojto 122:f9eeca106725 1752 */
Kojto 122:f9eeca106725 1753
Kojto 122:f9eeca106725 1754 /* CRS Flag Error Mask */
Kojto 122:f9eeca106725 1755 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
Kojto 122:f9eeca106725 1756
Kojto 122:f9eeca106725 1757 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
Kojto 122:f9eeca106725 1758 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
Kojto 122:f9eeca106725 1759 { \
Kojto 122:f9eeca106725 1760 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
Kojto 122:f9eeca106725 1761 } \
Kojto 122:f9eeca106725 1762 else \
Kojto 122:f9eeca106725 1763 { \
Kojto 122:f9eeca106725 1764 WRITE_REG(CRS->ICR, (__FLAG__)); \
Kojto 122:f9eeca106725 1765 } \
Kojto 122:f9eeca106725 1766 } while(0)
Kojto 122:f9eeca106725 1767
Kojto 122:f9eeca106725 1768 #endif /* CRS */
Kojto 122:f9eeca106725 1769
Kojto 122:f9eeca106725 1770 /**
Kojto 122:f9eeca106725 1771 * @}
Kojto 122:f9eeca106725 1772 */
Kojto 122:f9eeca106725 1773
Kojto 122:f9eeca106725 1774 #if defined(CRS)
Kojto 122:f9eeca106725 1775
Kojto 122:f9eeca106725 1776 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
Kojto 122:f9eeca106725 1777 * @{
Kojto 122:f9eeca106725 1778 */
Kojto 122:f9eeca106725 1779 /**
Kojto 122:f9eeca106725 1780 * @brief Enable the oscillator clock for frequency error counter.
Kojto 122:f9eeca106725 1781 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
Kojto 122:f9eeca106725 1782 * @retval None
Kojto 122:f9eeca106725 1783 */
Kojto 122:f9eeca106725 1784 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
Kojto 122:f9eeca106725 1785
Kojto 122:f9eeca106725 1786 /**
Kojto 122:f9eeca106725 1787 * @brief Disable the oscillator clock for frequency error counter.
Kojto 122:f9eeca106725 1788 * @retval None
Kojto 122:f9eeca106725 1789 */
Kojto 122:f9eeca106725 1790 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
Kojto 122:f9eeca106725 1791
Kojto 122:f9eeca106725 1792 /**
Kojto 122:f9eeca106725 1793 * @brief Enable the automatic hardware adjustement of TRIM bits.
Kojto 122:f9eeca106725 1794 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
Kojto 122:f9eeca106725 1795 * @retval None
Kojto 122:f9eeca106725 1796 */
Kojto 122:f9eeca106725 1797 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Kojto 122:f9eeca106725 1798
Kojto 122:f9eeca106725 1799 /**
Kojto 122:f9eeca106725 1800 * @brief Enable or disable the automatic hardware adjustement of TRIM bits.
Kojto 122:f9eeca106725 1801 * @retval None
Kojto 122:f9eeca106725 1802 */
Kojto 122:f9eeca106725 1803 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Kojto 122:f9eeca106725 1804
Kojto 122:f9eeca106725 1805 /**
Kojto 122:f9eeca106725 1806 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
Kojto 122:f9eeca106725 1807 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
Kojto 122:f9eeca106725 1808 * of the synchronization source after prescaling. It is then decreased by one in order to
Kojto 122:f9eeca106725 1809 * reach the expected synchronization on the zero value. The formula is the following:
Kojto 122:f9eeca106725 1810 * RELOAD = (fTARGET / fSYNC) -1
Kojto 122:f9eeca106725 1811 * @param __FTARGET__ Target frequency (value in Hz)
Kojto 122:f9eeca106725 1812 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
Kojto 122:f9eeca106725 1813 * @retval None
Kojto 122:f9eeca106725 1814 */
Kojto 122:f9eeca106725 1815 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Kojto 122:f9eeca106725 1816
Kojto 122:f9eeca106725 1817 /**
Kojto 122:f9eeca106725 1818 * @}
Kojto 122:f9eeca106725 1819 */
Kojto 122:f9eeca106725 1820
Kojto 122:f9eeca106725 1821 #endif /* CRS */
Kojto 122:f9eeca106725 1822
Kojto 122:f9eeca106725 1823 /**
Kojto 122:f9eeca106725 1824 * @}
Kojto 122:f9eeca106725 1825 */
Kojto 122:f9eeca106725 1826
Kojto 122:f9eeca106725 1827 /* Exported functions --------------------------------------------------------*/
Kojto 122:f9eeca106725 1828 /** @addtogroup RCCEx_Exported_Functions
Kojto 122:f9eeca106725 1829 * @{
Kojto 122:f9eeca106725 1830 */
Kojto 122:f9eeca106725 1831
Kojto 122:f9eeca106725 1832 /** @addtogroup RCCEx_Exported_Functions_Group1
Kojto 122:f9eeca106725 1833 * @{
Kojto 122:f9eeca106725 1834 */
Kojto 122:f9eeca106725 1835
Kojto 122:f9eeca106725 1836 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 122:f9eeca106725 1837 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 122:f9eeca106725 1838 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto 122:f9eeca106725 1839
Kojto 122:f9eeca106725 1840 /**
Kojto 122:f9eeca106725 1841 * @}
Kojto 122:f9eeca106725 1842 */
Kojto 122:f9eeca106725 1843
Kojto 122:f9eeca106725 1844 /** @addtogroup RCCEx_Exported_Functions_Group2
Kojto 122:f9eeca106725 1845 * @{
Kojto 122:f9eeca106725 1846 */
Kojto 122:f9eeca106725 1847
Kojto 122:f9eeca106725 1848 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init);
Kojto 122:f9eeca106725 1849 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
Kojto 122:f9eeca106725 1850
Kojto 122:f9eeca106725 1851 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 1852
Kojto 122:f9eeca106725 1853 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init);
Kojto 122:f9eeca106725 1854 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
Kojto 122:f9eeca106725 1855
Kojto 122:f9eeca106725 1856 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 1857
Kojto 122:f9eeca106725 1858 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
Kojto 122:f9eeca106725 1859 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
Kojto 122:f9eeca106725 1860 void HAL_RCCEx_EnableLSECSS(void);
Kojto 122:f9eeca106725 1861 void HAL_RCCEx_DisableLSECSS(void);
Kojto 122:f9eeca106725 1862 void HAL_RCCEx_EnableLSECSS_IT(void);
Kojto 122:f9eeca106725 1863 void HAL_RCCEx_LSECSS_IRQHandler(void);
Kojto 122:f9eeca106725 1864 void HAL_RCCEx_LSECSS_Callback(void);
Kojto 122:f9eeca106725 1865 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
Kojto 122:f9eeca106725 1866 void HAL_RCCEx_DisableLSCO(void);
Kojto 122:f9eeca106725 1867 void HAL_RCCEx_EnableMSIPLLMode(void);
Kojto 122:f9eeca106725 1868 void HAL_RCCEx_DisableMSIPLLMode(void);
Kojto 122:f9eeca106725 1869
Kojto 122:f9eeca106725 1870 /**
Kojto 122:f9eeca106725 1871 * @}
Kojto 122:f9eeca106725 1872 */
Kojto 122:f9eeca106725 1873
Kojto 122:f9eeca106725 1874 #if defined(CRS)
Kojto 122:f9eeca106725 1875
Kojto 122:f9eeca106725 1876 /** @addtogroup RCCEx_Exported_Functions_Group3
Kojto 122:f9eeca106725 1877 * @{
Kojto 122:f9eeca106725 1878 */
Kojto 122:f9eeca106725 1879
Kojto 122:f9eeca106725 1880 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
Kojto 122:f9eeca106725 1881 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
Kojto 122:f9eeca106725 1882 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
Kojto 122:f9eeca106725 1883 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
Kojto 122:f9eeca106725 1884 void HAL_RCCEx_CRS_IRQHandler(void);
Kojto 122:f9eeca106725 1885 void HAL_RCCEx_CRS_SyncOkCallback(void);
Kojto 122:f9eeca106725 1886 void HAL_RCCEx_CRS_SyncWarnCallback(void);
Kojto 122:f9eeca106725 1887 void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
Kojto 122:f9eeca106725 1888 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
Kojto 122:f9eeca106725 1889
Kojto 122:f9eeca106725 1890 /**
Kojto 122:f9eeca106725 1891 * @}
Kojto 122:f9eeca106725 1892 */
Kojto 122:f9eeca106725 1893
Kojto 122:f9eeca106725 1894 #endif /* CRS */
Kojto 122:f9eeca106725 1895
Kojto 122:f9eeca106725 1896 /**
Kojto 122:f9eeca106725 1897 * @}
Kojto 122:f9eeca106725 1898 */
Kojto 122:f9eeca106725 1899
Kojto 122:f9eeca106725 1900 /* Private macros ------------------------------------------------------------*/
Kojto 122:f9eeca106725 1901 /** @addtogroup RCCEx_Private_Macros
Kojto 122:f9eeca106725 1902 * @{
Kojto 122:f9eeca106725 1903 */
Kojto 122:f9eeca106725 1904
Kojto 122:f9eeca106725 1905 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
Kojto 122:f9eeca106725 1906 ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
Kojto 122:f9eeca106725 1907
Kojto 122:f9eeca106725 1908 #if defined(STM32L431xx)
Kojto 122:f9eeca106725 1909
Kojto 122:f9eeca106725 1910 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 122:f9eeca106725 1911 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 122:f9eeca106725 1912 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 122:f9eeca106725 1913 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 122:f9eeca106725 1914 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
Kojto 122:f9eeca106725 1915 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 122:f9eeca106725 1916 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 122:f9eeca106725 1917 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 122:f9eeca106725 1918 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 122:f9eeca106725 1919 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
Kojto 122:f9eeca106725 1920 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 122:f9eeca106725 1921 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 122:f9eeca106725 1922 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
Kojto 122:f9eeca106725 1923 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 122:f9eeca106725 1924 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
Kojto 122:f9eeca106725 1925 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
Kojto 122:f9eeca106725 1926
Kojto 122:f9eeca106725 1927 #elif defined(STM32L432xx) || defined(STM32L442xx)
Kojto 122:f9eeca106725 1928
Kojto 122:f9eeca106725 1929 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 122:f9eeca106725 1930 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 122:f9eeca106725 1931 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 122:f9eeca106725 1932 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
Kojto 122:f9eeca106725 1933 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 122:f9eeca106725 1934 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 122:f9eeca106725 1935 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 122:f9eeca106725 1936 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
Kojto 122:f9eeca106725 1937 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 122:f9eeca106725 1938 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
Kojto 122:f9eeca106725 1939 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 122:f9eeca106725 1940 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
Kojto 122:f9eeca106725 1941 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 122:f9eeca106725 1942 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG))
Kojto 122:f9eeca106725 1943
Kojto 122:f9eeca106725 1944 #elif defined(STM32L433xx) || defined(STM32L443xx)
Kojto 122:f9eeca106725 1945
Kojto 122:f9eeca106725 1946 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 122:f9eeca106725 1947 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 122:f9eeca106725 1948 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 122:f9eeca106725 1949 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 122:f9eeca106725 1950 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
Kojto 122:f9eeca106725 1951 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 122:f9eeca106725 1952 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 122:f9eeca106725 1953 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 122:f9eeca106725 1954 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 122:f9eeca106725 1955 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
Kojto 122:f9eeca106725 1956 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 122:f9eeca106725 1957 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
Kojto 122:f9eeca106725 1958 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 122:f9eeca106725 1959 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
Kojto 122:f9eeca106725 1960 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 122:f9eeca106725 1961 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
Kojto 122:f9eeca106725 1962 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
Kojto 122:f9eeca106725 1963
Kojto 122:f9eeca106725 1964 #elif defined(STM32L471xx)
Kojto 122:f9eeca106725 1965
Kojto 122:f9eeca106725 1966 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 122:f9eeca106725 1967 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 122:f9eeca106725 1968 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 122:f9eeca106725 1969 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 122:f9eeca106725 1970 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
Kojto 122:f9eeca106725 1971 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
Kojto 122:f9eeca106725 1972 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
Kojto 122:f9eeca106725 1973 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 122:f9eeca106725 1974 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 122:f9eeca106725 1975 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 122:f9eeca106725 1976 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 122:f9eeca106725 1977 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
Kojto 122:f9eeca106725 1978 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 122:f9eeca106725 1979 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
Kojto 122:f9eeca106725 1980 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 122:f9eeca106725 1981 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
Kojto 122:f9eeca106725 1982 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
Kojto 122:f9eeca106725 1983 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 122:f9eeca106725 1984 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
Kojto 122:f9eeca106725 1985 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
Kojto 122:f9eeca106725 1986
Kojto 122:f9eeca106725 1987 #else
Kojto 122:f9eeca106725 1988
Kojto 122:f9eeca106725 1989 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 122:f9eeca106725 1990 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 122:f9eeca106725 1991 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 122:f9eeca106725 1992 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 122:f9eeca106725 1993 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
Kojto 122:f9eeca106725 1994 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
Kojto 122:f9eeca106725 1995 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
Kojto 122:f9eeca106725 1996 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 122:f9eeca106725 1997 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 122:f9eeca106725 1998 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 122:f9eeca106725 1999 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 122:f9eeca106725 2000 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
Kojto 122:f9eeca106725 2001 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 122:f9eeca106725 2002 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
Kojto 122:f9eeca106725 2003 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
Kojto 122:f9eeca106725 2004 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 122:f9eeca106725 2005 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
Kojto 122:f9eeca106725 2006 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
Kojto 122:f9eeca106725 2007 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 122:f9eeca106725 2008 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
Kojto 122:f9eeca106725 2009 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
Kojto 122:f9eeca106725 2010
Kojto 122:f9eeca106725 2011 #endif /* STM32L431xx */
Kojto 122:f9eeca106725 2012
Kojto 122:f9eeca106725 2013 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2014 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
Kojto 122:f9eeca106725 2015 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 2016 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 2017 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2018
Kojto 122:f9eeca106725 2019 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2020 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2021 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 2022 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 2023 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2024
Kojto 122:f9eeca106725 2025 #if defined(USART3)
Kojto 122:f9eeca106725 2026
Kojto 122:f9eeca106725 2027 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2028 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2029 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 2030 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 2031 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2032
Kojto 122:f9eeca106725 2033 #endif /* USART3 */
Kojto 122:f9eeca106725 2034
Kojto 122:f9eeca106725 2035 #if defined(UART4)
Kojto 122:f9eeca106725 2036
Kojto 122:f9eeca106725 2037 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2038 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2039 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 2040 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 2041 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2042
Kojto 122:f9eeca106725 2043 #endif /* UART4 */
Kojto 122:f9eeca106725 2044
Kojto 122:f9eeca106725 2045 #if defined(UART5)
Kojto 122:f9eeca106725 2046
Kojto 122:f9eeca106725 2047 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2048 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2049 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 2050 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 2051 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2052
Kojto 122:f9eeca106725 2053 #endif /* UART5 */
Kojto 122:f9eeca106725 2054
Kojto 122:f9eeca106725 2055 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2056 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2057 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 2058 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 2059 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2060
Kojto 122:f9eeca106725 2061 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2062 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2063 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
Kojto 122:f9eeca106725 2064 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2065
Kojto 122:f9eeca106725 2066 #if defined(I2C2)
Kojto 122:f9eeca106725 2067
Kojto 122:f9eeca106725 2068 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2069 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2070 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
Kojto 122:f9eeca106725 2071 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2072
Kojto 122:f9eeca106725 2073 #endif /* I2C2 */
Kojto 122:f9eeca106725 2074
Kojto 122:f9eeca106725 2075 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2076 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2077 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
Kojto 122:f9eeca106725 2078 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2079
Kojto 122:f9eeca106725 2080 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 2081
Kojto 122:f9eeca106725 2082 #define IS_RCC_SAI1CLK(__SOURCE__) \
Kojto 122:f9eeca106725 2083 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2084 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
Kojto 122:f9eeca106725 2085 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2086 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
Kojto 122:f9eeca106725 2087
Kojto 122:f9eeca106725 2088 #else
Kojto 122:f9eeca106725 2089
Kojto 122:f9eeca106725 2090 #define IS_RCC_SAI1CLK(__SOURCE__) \
Kojto 122:f9eeca106725 2091 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2092 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2093 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
Kojto 122:f9eeca106725 2094
Kojto 122:f9eeca106725 2095 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 2096
Kojto 122:f9eeca106725 2097 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 2098
Kojto 122:f9eeca106725 2099 #define IS_RCC_SAI2CLK(__SOURCE__) \
Kojto 122:f9eeca106725 2100 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2101 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
Kojto 122:f9eeca106725 2102 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2103 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
Kojto 122:f9eeca106725 2104
Kojto 122:f9eeca106725 2105 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 2106
Kojto 122:f9eeca106725 2107 #define IS_RCC_LPTIM1CLK(__SOURCE__) \
Kojto 122:f9eeca106725 2108 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK) || \
Kojto 122:f9eeca106725 2109 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
Kojto 122:f9eeca106725 2110 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
Kojto 122:f9eeca106725 2111 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
Kojto 122:f9eeca106725 2112
Kojto 122:f9eeca106725 2113 #define IS_RCC_LPTIM2CLK(__SOURCE__) \
Kojto 122:f9eeca106725 2114 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK) || \
Kojto 122:f9eeca106725 2115 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
Kojto 122:f9eeca106725 2116 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
Kojto 122:f9eeca106725 2117 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
Kojto 122:f9eeca106725 2118
Kojto 122:f9eeca106725 2119 #if defined(SDMMC1)
Kojto 122:f9eeca106725 2120 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 2121
Kojto 122:f9eeca106725 2122 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2123 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \
Kojto 122:f9eeca106725 2124 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2125 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2126 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
Kojto 122:f9eeca106725 2127
Kojto 122:f9eeca106725 2128 #else
Kojto 122:f9eeca106725 2129
Kojto 122:f9eeca106725 2130 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2131 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \
Kojto 122:f9eeca106725 2132 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2133 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2134 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
Kojto 122:f9eeca106725 2135
Kojto 122:f9eeca106725 2136 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 2137 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 2138
Kojto 122:f9eeca106725 2139 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 2140
Kojto 122:f9eeca106725 2141 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2142 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
Kojto 122:f9eeca106725 2143 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2144 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2145 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
Kojto 122:f9eeca106725 2146
Kojto 122:f9eeca106725 2147 #else
Kojto 122:f9eeca106725 2148
Kojto 122:f9eeca106725 2149 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2150 (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \
Kojto 122:f9eeca106725 2151 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2152 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2153 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
Kojto 122:f9eeca106725 2154
Kojto 122:f9eeca106725 2155 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 2156
Kojto 122:f9eeca106725 2157 #if defined(USB_OTG_FS) || defined(USB)
Kojto 122:f9eeca106725 2158 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 2159
Kojto 122:f9eeca106725 2160 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2161 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
Kojto 122:f9eeca106725 2162 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2163 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2164 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
Kojto 122:f9eeca106725 2165
Kojto 122:f9eeca106725 2166 #else
Kojto 122:f9eeca106725 2167
Kojto 122:f9eeca106725 2168 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2169 (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \
Kojto 122:f9eeca106725 2170 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2171 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2172 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
Kojto 122:f9eeca106725 2173
Kojto 122:f9eeca106725 2174 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 2175 #endif /* USB_OTG_FS || USB */
Kojto 122:f9eeca106725 2176
Kojto 122:f9eeca106725 2177 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
Kojto 122:f9eeca106725 2178
Kojto 122:f9eeca106725 2179 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2180 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
Kojto 122:f9eeca106725 2181 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2182 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \
Kojto 122:f9eeca106725 2183 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
Kojto 122:f9eeca106725 2184
Kojto 122:f9eeca106725 2185 #else
Kojto 122:f9eeca106725 2186
Kojto 122:f9eeca106725 2187 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2188 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
Kojto 122:f9eeca106725 2189 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2190 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
Kojto 122:f9eeca106725 2191
Kojto 122:f9eeca106725 2192 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 122:f9eeca106725 2193
Kojto 122:f9eeca106725 2194 #if defined(SWPMI1)
Kojto 122:f9eeca106725 2195
Kojto 122:f9eeca106725 2196 #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2197 (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK) || \
Kojto 122:f9eeca106725 2198 ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2199
Kojto 122:f9eeca106725 2200 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 2201
Kojto 122:f9eeca106725 2202 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 2203
Kojto 122:f9eeca106725 2204 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2205 (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK) || \
Kojto 122:f9eeca106725 2206 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
Kojto 122:f9eeca106725 2207
Kojto 122:f9eeca106725 2208 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 2209
Kojto 122:f9eeca106725 2210 #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
Kojto 122:f9eeca106725 2211
Kojto 122:f9eeca106725 2212 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
Kojto 122:f9eeca106725 2213
Kojto 122:f9eeca106725 2214 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
Kojto 122:f9eeca106725 2215
Kojto 122:f9eeca106725 2216 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 2217 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
Kojto 122:f9eeca106725 2218 #else
Kojto 122:f9eeca106725 2219 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
Kojto 122:f9eeca106725 2220 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 2221
Kojto 122:f9eeca106725 2222 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
Kojto 122:f9eeca106725 2223 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
Kojto 122:f9eeca106725 2224
Kojto 122:f9eeca106725 2225 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
Kojto 122:f9eeca106725 2226 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
Kojto 122:f9eeca106725 2227
Kojto 122:f9eeca106725 2228 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 2229
Kojto 122:f9eeca106725 2230 #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
Kojto 122:f9eeca106725 2231
Kojto 122:f9eeca106725 2232 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
Kojto 122:f9eeca106725 2233
Kojto 122:f9eeca106725 2234 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
Kojto 122:f9eeca106725 2235
Kojto 122:f9eeca106725 2236 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 2237 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
Kojto 122:f9eeca106725 2238 #else
Kojto 122:f9eeca106725 2239 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
Kojto 122:f9eeca106725 2240 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 2241
Kojto 122:f9eeca106725 2242 #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
Kojto 122:f9eeca106725 2243 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
Kojto 122:f9eeca106725 2244
Kojto 122:f9eeca106725 2245 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 2246
Kojto 122:f9eeca106725 2247 #if defined(CRS)
Kojto 122:f9eeca106725 2248
Kojto 122:f9eeca106725 2249 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
Kojto 122:f9eeca106725 2250 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
Kojto 122:f9eeca106725 2251 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
Kojto 122:f9eeca106725 2252
Kojto 122:f9eeca106725 2253 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
Kojto 122:f9eeca106725 2254 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
Kojto 122:f9eeca106725 2255 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
Kojto 122:f9eeca106725 2256 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
Kojto 122:f9eeca106725 2257
Kojto 122:f9eeca106725 2258 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
Kojto 122:f9eeca106725 2259 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
Kojto 122:f9eeca106725 2260
Kojto 122:f9eeca106725 2261 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
Kojto 122:f9eeca106725 2262
Kojto 122:f9eeca106725 2263 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
Kojto 122:f9eeca106725 2264
Kojto 122:f9eeca106725 2265 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
Kojto 122:f9eeca106725 2266
Kojto 122:f9eeca106725 2267 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
Kojto 122:f9eeca106725 2268 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
Kojto 122:f9eeca106725 2269
Kojto 122:f9eeca106725 2270 #endif /* CRS */
Kojto 122:f9eeca106725 2271
Kojto 122:f9eeca106725 2272 /**
Kojto 122:f9eeca106725 2273 * @}
Kojto 122:f9eeca106725 2274 */
Kojto 122:f9eeca106725 2275
Kojto 122:f9eeca106725 2276 /**
Kojto 122:f9eeca106725 2277 * @}
Kojto 122:f9eeca106725 2278 */
Kojto 122:f9eeca106725 2279
Kojto 122:f9eeca106725 2280 /**
Kojto 122:f9eeca106725 2281 * @}
Kojto 122:f9eeca106725 2282 */
Kojto 122:f9eeca106725 2283
Kojto 122:f9eeca106725 2284 #ifdef __cplusplus
Kojto 122:f9eeca106725 2285 }
Kojto 122:f9eeca106725 2286 #endif
Kojto 122:f9eeca106725 2287
Kojto 122:f9eeca106725 2288 #endif /* __STM32L4xx_HAL_RCC_EX_H */
Kojto 122:f9eeca106725 2289
Kojto 122:f9eeca106725 2290 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/