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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h@145:64910690c574, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:31:38 2017 +0100
Revision:
145:64910690c574
Parent:
128:9bcdf88f62b0 
Release 145 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**
Kojto 122:f9eeca106725 2 ******************************************************************************
Kojto 122:f9eeca106725 3 * @file stm32l4xx_hal_rcc_ex.h
Kojto 122:f9eeca106725 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @version V1.7.1
AnnaBridge 145:64910690c574 6 * @date 21-April-2017
Kojto 122:f9eeca106725 7 * @brief Header file of RCC HAL Extended module.
Kojto 122:f9eeca106725 8 ******************************************************************************
Kojto 122:f9eeca106725 9 * @attention
Kojto 122:f9eeca106725 10 *
AnnaBridge 145:64910690c574 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
Kojto 122:f9eeca106725 12 *
Kojto 122:f9eeca106725 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 14 * are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 122:f9eeca106725 16 * this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 122:f9eeca106725 18 * this list of conditions and the following disclaimer in the documentation
Kojto 122:f9eeca106725 19 * and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 122:f9eeca106725 21 * may be used to endorse or promote products derived from this software
Kojto 122:f9eeca106725 22 * without specific prior written permission.
Kojto 122:f9eeca106725 23 *
Kojto 122:f9eeca106725 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 122:f9eeca106725 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 122:f9eeca106725 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 122:f9eeca106725 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 122:f9eeca106725 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 122:f9eeca106725 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 122:f9eeca106725 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 34 *
Kojto 122:f9eeca106725 35 ******************************************************************************
Kojto 122:f9eeca106725 36 */
Kojto 122:f9eeca106725 37
Kojto 122:f9eeca106725 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 122:f9eeca106725 39 #ifndef __STM32L4xx_HAL_RCC_EX_H
Kojto 122:f9eeca106725 40 #define __STM32L4xx_HAL_RCC_EX_H
Kojto 122:f9eeca106725 41
Kojto 122:f9eeca106725 42 #ifdef __cplusplus
Kojto 122:f9eeca106725 43 extern "C" {
Kojto 122:f9eeca106725 44 #endif
Kojto 122:f9eeca106725 45
Kojto 122:f9eeca106725 46 /* Includes ------------------------------------------------------------------*/
Kojto 122:f9eeca106725 47 #include "stm32l4xx_hal_def.h"
Kojto 122:f9eeca106725 48
Kojto 122:f9eeca106725 49 /** @addtogroup STM32L4xx_HAL_Driver
Kojto 122:f9eeca106725 50 * @{
Kojto 122:f9eeca106725 51 */
Kojto 122:f9eeca106725 52
Kojto 122:f9eeca106725 53 /** @addtogroup RCCEx
Kojto 122:f9eeca106725 54 * @{
Kojto 122:f9eeca106725 55 */
Kojto 122:f9eeca106725 56
Kojto 122:f9eeca106725 57 /* Exported types ------------------------------------------------------------*/
Kojto 122:f9eeca106725 58
Kojto 122:f9eeca106725 59 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto 122:f9eeca106725 60 * @{
Kojto 122:f9eeca106725 61 */
Kojto 122:f9eeca106725 62
Kojto 122:f9eeca106725 63 /**
Kojto 122:f9eeca106725 64 * @brief PLLSAI1 Clock structure definition
Kojto 122:f9eeca106725 65 */
Kojto 122:f9eeca106725 66 typedef struct
Kojto 122:f9eeca106725 67 {
Kojto 122:f9eeca106725 68
Kojto 122:f9eeca106725 69 uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source.
Kojto 122:f9eeca106725 70 This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto 122:f9eeca106725 71
Kojto 122:f9eeca106725 72 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.
Kojto 122:f9eeca106725 73 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
Kojto 122:f9eeca106725 74
Kojto 122:f9eeca106725 75 uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.
Kojto 122:f9eeca106725 76 This parameter must be a number between 8 and 86 or 127 depending on devices. */
Kojto 122:f9eeca106725 77
Kojto 122:f9eeca106725 78 uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock.
Kojto 122:f9eeca106725 79 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto 122:f9eeca106725 80
Kojto 122:f9eeca106725 81 uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.
Kojto 122:f9eeca106725 82 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
Kojto 122:f9eeca106725 83
Kojto 122:f9eeca106725 84 uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock.
Kojto 122:f9eeca106725 85 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
Kojto 122:f9eeca106725 86
Kojto 122:f9eeca106725 87 uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.
Kojto 122:f9eeca106725 88 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
Kojto 122:f9eeca106725 89 }RCC_PLLSAI1InitTypeDef;
Kojto 122:f9eeca106725 90
Kojto 122:f9eeca106725 91 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 92
Kojto 122:f9eeca106725 93 /**
Kojto 122:f9eeca106725 94 * @brief PLLSAI2 Clock structure definition
Kojto 122:f9eeca106725 95 */
Kojto 122:f9eeca106725 96 typedef struct
Kojto 122:f9eeca106725 97 {
Kojto 122:f9eeca106725 98
Kojto 122:f9eeca106725 99 uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source.
Kojto 122:f9eeca106725 100 This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto 122:f9eeca106725 101
Kojto 122:f9eeca106725 102 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.
Kojto 122:f9eeca106725 103 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
Kojto 122:f9eeca106725 104
Kojto 122:f9eeca106725 105 uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.
Kojto 122:f9eeca106725 106 This parameter must be a number between 8 and 86 or 127 depending on devices. */
Kojto 122:f9eeca106725 107
Kojto 122:f9eeca106725 108 uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock.
Kojto 122:f9eeca106725 109 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto 122:f9eeca106725 110
Kojto 122:f9eeca106725 111 uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock.
Kojto 122:f9eeca106725 112 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
Kojto 122:f9eeca106725 113
Kojto 122:f9eeca106725 114 uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.
Kojto 122:f9eeca106725 115 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */
Kojto 122:f9eeca106725 116 }RCC_PLLSAI2InitTypeDef;
Kojto 122:f9eeca106725 117
Kojto 122:f9eeca106725 118 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 119
Kojto 122:f9eeca106725 120 /**
Kojto 122:f9eeca106725 121 * @brief RCC extended clocks structure definition
Kojto 122:f9eeca106725 122 */
Kojto 122:f9eeca106725 123 typedef struct
Kojto 122:f9eeca106725 124 {
Kojto 122:f9eeca106725 125 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 122:f9eeca106725 126 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 122:f9eeca106725 127
Kojto 122:f9eeca106725 128 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters.
Kojto 122:f9eeca106725 129 This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */
Kojto 122:f9eeca106725 130
Kojto 122:f9eeca106725 131 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 132
Kojto 122:f9eeca106725 133 RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters.
Kojto 122:f9eeca106725 134 This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */
Kojto 122:f9eeca106725 135
Kojto 122:f9eeca106725 136 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 137
Kojto 122:f9eeca106725 138 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
Kojto 122:f9eeca106725 139 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 122:f9eeca106725 140
Kojto 122:f9eeca106725 141 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
Kojto 122:f9eeca106725 142 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto 122:f9eeca106725 143
Kojto 122:f9eeca106725 144 #if defined(USART3)
Kojto 122:f9eeca106725 145
Kojto 122:f9eeca106725 146 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
Kojto 122:f9eeca106725 147 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
Kojto 122:f9eeca106725 148
Kojto 122:f9eeca106725 149 #endif /* USART3 */
Kojto 122:f9eeca106725 150
Kojto 122:f9eeca106725 151 #if defined(UART4)
Kojto 122:f9eeca106725 152
Kojto 122:f9eeca106725 153 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
Kojto 122:f9eeca106725 154 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto 122:f9eeca106725 155
Kojto 122:f9eeca106725 156 #endif /* UART4 */
Kojto 122:f9eeca106725 157
Kojto 122:f9eeca106725 158 #if defined(UART5)
Kojto 122:f9eeca106725 159
Kojto 122:f9eeca106725 160 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
Kojto 122:f9eeca106725 161 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto 122:f9eeca106725 162
Kojto 122:f9eeca106725 163 #endif /* UART5 */
Kojto 122:f9eeca106725 164
Kojto 122:f9eeca106725 165 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
Kojto 122:f9eeca106725 166 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
Kojto 122:f9eeca106725 167
Kojto 122:f9eeca106725 168 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
Kojto 122:f9eeca106725 169 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
Kojto 122:f9eeca106725 170
Kojto 122:f9eeca106725 171 #if defined(I2C2)
Kojto 122:f9eeca106725 172
Kojto 122:f9eeca106725 173 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
Kojto 122:f9eeca106725 174 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 122:f9eeca106725 175
Kojto 122:f9eeca106725 176 #endif /* I2C2 */
Kojto 122:f9eeca106725 177
Kojto 122:f9eeca106725 178 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
Kojto 122:f9eeca106725 179 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge 145:64910690c574 180
AnnaBridge 145:64910690c574 181 #if defined(I2C4)
AnnaBridge 145:64910690c574 182
AnnaBridge 145:64910690c574 183 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source.
AnnaBridge 145:64910690c574 184 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
AnnaBridge 145:64910690c574 185
AnnaBridge 145:64910690c574 186 #endif /* I2C4 */
Kojto 122:f9eeca106725 187
Kojto 122:f9eeca106725 188 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
Kojto 122:f9eeca106725 189 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
Kojto 122:f9eeca106725 190
Kojto 122:f9eeca106725 191 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source.
Kojto 122:f9eeca106725 192 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
Kojto 122:f9eeca106725 193
Kojto 122:f9eeca106725 194 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
Kojto 122:f9eeca106725 195 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
Kojto 122:f9eeca106725 196
Kojto 122:f9eeca106725 197 #if defined(SAI2)
Kojto 122:f9eeca106725 198
Kojto 122:f9eeca106725 199 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source.
Kojto 122:f9eeca106725 200 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
Kojto 122:f9eeca106725 201
Kojto 122:f9eeca106725 202 #endif /* SAI2 */
Kojto 122:f9eeca106725 203
Kojto 122:f9eeca106725 204 #if defined(USB_OTG_FS) || defined(USB)
Kojto 122:f9eeca106725 205
Kojto 122:f9eeca106725 206 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).
Kojto 122:f9eeca106725 207 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 122:f9eeca106725 208
Kojto 122:f9eeca106725 209 #endif /* USB_OTG_FS || USB */
Kojto 122:f9eeca106725 210
Kojto 122:f9eeca106725 211 #if defined(SDMMC1)
Kojto 122:f9eeca106725 212
Kojto 122:f9eeca106725 213 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
Kojto 122:f9eeca106725 214 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
Kojto 122:f9eeca106725 215
Kojto 122:f9eeca106725 216 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 217
Kojto 122:f9eeca106725 218 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).
Kojto 122:f9eeca106725 219 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
Kojto 122:f9eeca106725 220
Kojto 122:f9eeca106725 221 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source.
Kojto 122:f9eeca106725 222 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
Kojto 122:f9eeca106725 223
Kojto 122:f9eeca106725 224 #if defined(SWPMI1)
Kojto 122:f9eeca106725 225
Kojto 122:f9eeca106725 226 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source.
Kojto 122:f9eeca106725 227 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
Kojto 122:f9eeca106725 228
Kojto 122:f9eeca106725 229 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 230
Kojto 122:f9eeca106725 231 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 232
Kojto 122:f9eeca106725 233 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source.
Kojto 122:f9eeca106725 234 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */
Kojto 122:f9eeca106725 235
Kojto 122:f9eeca106725 236 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 237
Kojto 122:f9eeca106725 238 uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
Kojto 122:f9eeca106725 239 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 122:f9eeca106725 240 }RCC_PeriphCLKInitTypeDef;
Kojto 122:f9eeca106725 241
Kojto 122:f9eeca106725 242 #if defined(CRS)
Kojto 122:f9eeca106725 243
Kojto 122:f9eeca106725 244 /**
Kojto 122:f9eeca106725 245 * @brief RCC_CRS Init structure definition
Kojto 122:f9eeca106725 246 */
Kojto 122:f9eeca106725 247 typedef struct
Kojto 122:f9eeca106725 248 {
Kojto 122:f9eeca106725 249 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
Kojto 122:f9eeca106725 250 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
Kojto 122:f9eeca106725 251
Kojto 122:f9eeca106725 252 uint32_t Source; /*!< Specifies the SYNC signal source.
Kojto 122:f9eeca106725 253 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
Kojto 122:f9eeca106725 254
Kojto 122:f9eeca106725 255 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
Kojto 122:f9eeca106725 256 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
Kojto 122:f9eeca106725 257
Kojto 122:f9eeca106725 258 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
Kojto 122:f9eeca106725 259 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
Kojto 122:f9eeca106725 260 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
Kojto 122:f9eeca106725 261
Kojto 122:f9eeca106725 262 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
Kojto 122:f9eeca106725 263 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
Kojto 122:f9eeca106725 264
Kojto 122:f9eeca106725 265 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
Kojto 122:f9eeca106725 266 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
Kojto 122:f9eeca106725 267
Kojto 122:f9eeca106725 268 }RCC_CRSInitTypeDef;
Kojto 122:f9eeca106725 269
Kojto 122:f9eeca106725 270 /**
Kojto 122:f9eeca106725 271 * @brief RCC_CRS Synchronization structure definition
Kojto 122:f9eeca106725 272 */
Kojto 122:f9eeca106725 273 typedef struct
Kojto 122:f9eeca106725 274 {
Kojto 122:f9eeca106725 275 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
Kojto 122:f9eeca106725 276 This parameter must be a number between 0 and 0xFFFF */
Kojto 122:f9eeca106725 277
Kojto 122:f9eeca106725 278 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
Kojto 122:f9eeca106725 279 This parameter must be a number between 0 and 0x3F */
Kojto 122:f9eeca106725 280
Kojto 122:f9eeca106725 281 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
Kojto 122:f9eeca106725 282 value latched in the time of the last SYNC event.
Kojto 122:f9eeca106725 283 This parameter must be a number between 0 and 0xFFFF */
Kojto 122:f9eeca106725 284
Kojto 122:f9eeca106725 285 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
Kojto 122:f9eeca106725 286 frequency error counter latched in the time of the last SYNC event.
Kojto 122:f9eeca106725 287 It shows whether the actual frequency is below or above the target.
Kojto 122:f9eeca106725 288 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
Kojto 122:f9eeca106725 289
Kojto 122:f9eeca106725 290 }RCC_CRSSynchroInfoTypeDef;
Kojto 122:f9eeca106725 291
Kojto 122:f9eeca106725 292 #endif /* CRS */
Kojto 122:f9eeca106725 293 /**
Kojto 122:f9eeca106725 294 * @}
Kojto 122:f9eeca106725 295 */
Kojto 122:f9eeca106725 296
Kojto 122:f9eeca106725 297 /* Exported constants --------------------------------------------------------*/
Kojto 122:f9eeca106725 298 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto 122:f9eeca106725 299 * @{
Kojto 122:f9eeca106725 300 */
Kojto 122:f9eeca106725 301
Kojto 122:f9eeca106725 302 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
Kojto 122:f9eeca106725 303 * @{
Kojto 122:f9eeca106725 304 */
Kojto 122:f9eeca106725 305 #define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */
Kojto 122:f9eeca106725 306 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */
Kojto 122:f9eeca106725 307 /**
Kojto 122:f9eeca106725 308 * @}
Kojto 122:f9eeca106725 309 */
Kojto 122:f9eeca106725 310
Kojto 122:f9eeca106725 311 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
Kojto 122:f9eeca106725 312 * @{
Kojto 122:f9eeca106725 313 */
Kojto 122:f9eeca106725 314 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 315 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 316 #if defined(USART3)
Kojto 122:f9eeca106725 317 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 318 #endif
Kojto 122:f9eeca106725 319 #if defined(UART4)
Kojto 122:f9eeca106725 320 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 321 #endif
Kojto 122:f9eeca106725 322 #if defined(UART5)
Kojto 122:f9eeca106725 323 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 324 #endif
Kojto 122:f9eeca106725 325 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 326 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 327 #if defined(I2C2)
Kojto 122:f9eeca106725 328 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 329 #endif
Kojto 122:f9eeca106725 330 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 331 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 332 #define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 333 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 334 #if defined(SAI2)
Kojto 122:f9eeca106725 335 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 336 #endif
Kojto 122:f9eeca106725 337 #if defined(USB_OTG_FS) || defined(USB)
Kojto 122:f9eeca106725 338 #define RCC_PERIPHCLK_USB ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 339 #endif
Kojto 122:f9eeca106725 340 #define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000U)
AnnaBridge 145:64910690c574 341 #if defined(SWPMI1)
Kojto 122:f9eeca106725 342 #define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000U)
AnnaBridge 145:64910690c574 343 #endif
Kojto 122:f9eeca106725 344 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 345 #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 346 #endif
Kojto 122:f9eeca106725 347 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 348 #define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 349 #if defined(SDMMC1)
Kojto 122:f9eeca106725 350 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 351 #endif
AnnaBridge 145:64910690c574 352 #if defined(I2C4)
AnnaBridge 145:64910690c574 353 #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00100000U)
AnnaBridge 145:64910690c574 354 #endif
Kojto 122:f9eeca106725 355 /**
Kojto 122:f9eeca106725 356 * @}
Kojto 122:f9eeca106725 357 */
Kojto 122:f9eeca106725 358
Kojto 122:f9eeca106725 359
Kojto 122:f9eeca106725 360 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
Kojto 122:f9eeca106725 361 * @{
Kojto 122:f9eeca106725 362 */
Kojto 122:f9eeca106725 363 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 364 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
Kojto 122:f9eeca106725 365 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
Kojto 122:f9eeca106725 366 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
Kojto 122:f9eeca106725 367 /**
Kojto 122:f9eeca106725 368 * @}
Kojto 122:f9eeca106725 369 */
Kojto 122:f9eeca106725 370
Kojto 122:f9eeca106725 371 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
Kojto 122:f9eeca106725 372 * @{
Kojto 122:f9eeca106725 373 */
Kojto 122:f9eeca106725 374 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 375 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
Kojto 122:f9eeca106725 376 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
Kojto 122:f9eeca106725 377 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
Kojto 122:f9eeca106725 378 /**
Kojto 122:f9eeca106725 379 * @}
Kojto 122:f9eeca106725 380 */
Kojto 122:f9eeca106725 381
Kojto 122:f9eeca106725 382 #if defined(USART3)
Kojto 122:f9eeca106725 383 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
Kojto 122:f9eeca106725 384 * @{
Kojto 122:f9eeca106725 385 */
Kojto 122:f9eeca106725 386 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 387 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
Kojto 122:f9eeca106725 388 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
Kojto 122:f9eeca106725 389 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
Kojto 122:f9eeca106725 390 /**
Kojto 122:f9eeca106725 391 * @}
Kojto 122:f9eeca106725 392 */
Kojto 122:f9eeca106725 393 #endif /* USART3 */
Kojto 122:f9eeca106725 394
Kojto 122:f9eeca106725 395 #if defined(UART4)
Kojto 122:f9eeca106725 396 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
Kojto 122:f9eeca106725 397 * @{
Kojto 122:f9eeca106725 398 */
Kojto 122:f9eeca106725 399 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 400 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
Kojto 122:f9eeca106725 401 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
Kojto 122:f9eeca106725 402 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
Kojto 122:f9eeca106725 403 /**
Kojto 122:f9eeca106725 404 * @}
Kojto 122:f9eeca106725 405 */
Kojto 122:f9eeca106725 406 #endif /* UART4 */
Kojto 122:f9eeca106725 407
Kojto 122:f9eeca106725 408 #if defined(UART5)
Kojto 122:f9eeca106725 409 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
Kojto 122:f9eeca106725 410 * @{
Kojto 122:f9eeca106725 411 */
Kojto 122:f9eeca106725 412 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 413 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
Kojto 122:f9eeca106725 414 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
Kojto 122:f9eeca106725 415 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
Kojto 122:f9eeca106725 416 /**
Kojto 122:f9eeca106725 417 * @}
Kojto 122:f9eeca106725 418 */
Kojto 122:f9eeca106725 419 #endif /* UART5 */
Kojto 122:f9eeca106725 420
Kojto 122:f9eeca106725 421 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
Kojto 122:f9eeca106725 422 * @{
Kojto 122:f9eeca106725 423 */
Kojto 122:f9eeca106725 424 #define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 425 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
Kojto 122:f9eeca106725 426 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
Kojto 122:f9eeca106725 427 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
Kojto 122:f9eeca106725 428 /**
Kojto 122:f9eeca106725 429 * @}
Kojto 122:f9eeca106725 430 */
Kojto 122:f9eeca106725 431
Kojto 122:f9eeca106725 432 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
Kojto 122:f9eeca106725 433 * @{
Kojto 122:f9eeca106725 434 */
Kojto 122:f9eeca106725 435 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 436 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
Kojto 122:f9eeca106725 437 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
Kojto 122:f9eeca106725 438 /**
Kojto 122:f9eeca106725 439 * @}
Kojto 122:f9eeca106725 440 */
Kojto 122:f9eeca106725 441
Kojto 122:f9eeca106725 442 #if defined(I2C2)
Kojto 122:f9eeca106725 443 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
Kojto 122:f9eeca106725 444 * @{
Kojto 122:f9eeca106725 445 */
Kojto 122:f9eeca106725 446 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 447 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
Kojto 122:f9eeca106725 448 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
Kojto 122:f9eeca106725 449 /**
Kojto 122:f9eeca106725 450 * @}
Kojto 122:f9eeca106725 451 */
Kojto 122:f9eeca106725 452 #endif /* I2C2 */
Kojto 122:f9eeca106725 453
Kojto 122:f9eeca106725 454 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
Kojto 122:f9eeca106725 455 * @{
Kojto 122:f9eeca106725 456 */
Kojto 122:f9eeca106725 457 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 458 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
Kojto 122:f9eeca106725 459 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
Kojto 122:f9eeca106725 460 /**
Kojto 122:f9eeca106725 461 * @}
Kojto 122:f9eeca106725 462 */
AnnaBridge 145:64910690c574 463
AnnaBridge 145:64910690c574 464 #if defined(I2C4)
AnnaBridge 145:64910690c574 465 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
AnnaBridge 145:64910690c574 466 * @{
AnnaBridge 145:64910690c574 467 */
AnnaBridge 145:64910690c574 468 #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 145:64910690c574 469 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0
AnnaBridge 145:64910690c574 470 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1
AnnaBridge 145:64910690c574 471 /**
AnnaBridge 145:64910690c574 472 * @}
AnnaBridge 145:64910690c574 473 */
AnnaBridge 145:64910690c574 474 #endif /* I2C4 */
Kojto 122:f9eeca106725 475
Kojto 122:f9eeca106725 476 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
Kojto 122:f9eeca106725 477 * @{
Kojto 122:f9eeca106725 478 */
Kojto 122:f9eeca106725 479 #define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 480 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 481 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0
Kojto 122:f9eeca106725 482 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 483 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1
Kojto 122:f9eeca106725 484 #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL
Kojto 122:f9eeca106725 485 /**
Kojto 122:f9eeca106725 486 * @}
Kojto 122:f9eeca106725 487 */
Kojto 122:f9eeca106725 488
Kojto 122:f9eeca106725 489 #if defined(SAI2)
Kojto 122:f9eeca106725 490 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
Kojto 122:f9eeca106725 491 * @{
Kojto 122:f9eeca106725 492 */
Kojto 122:f9eeca106725 493 #define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 494 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0
Kojto 122:f9eeca106725 495 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1
Kojto 122:f9eeca106725 496 #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL
Kojto 122:f9eeca106725 497 /**
Kojto 122:f9eeca106725 498 * @}
Kojto 122:f9eeca106725 499 */
Kojto 122:f9eeca106725 500 #endif /* SAI2 */
Kojto 122:f9eeca106725 501
Kojto 122:f9eeca106725 502 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
Kojto 122:f9eeca106725 503 * @{
Kojto 122:f9eeca106725 504 */
AnnaBridge 145:64910690c574 505 #define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 506 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
Kojto 122:f9eeca106725 507 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
Kojto 122:f9eeca106725 508 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
Kojto 122:f9eeca106725 509 /**
Kojto 122:f9eeca106725 510 * @}
Kojto 122:f9eeca106725 511 */
Kojto 122:f9eeca106725 512
Kojto 122:f9eeca106725 513 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
Kojto 122:f9eeca106725 514 * @{
Kojto 122:f9eeca106725 515 */
AnnaBridge 145:64910690c574 516 #define RCC_LPTIM2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 517 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
Kojto 122:f9eeca106725 518 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
Kojto 122:f9eeca106725 519 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
Kojto 122:f9eeca106725 520 /**
Kojto 122:f9eeca106725 521 * @}
Kojto 122:f9eeca106725 522 */
Kojto 122:f9eeca106725 523
Kojto 122:f9eeca106725 524 #if defined(SDMMC1)
Kojto 122:f9eeca106725 525 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source
Kojto 122:f9eeca106725 526 * @{
Kojto 122:f9eeca106725 527 */
Kojto 122:f9eeca106725 528 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 529 #define RCC_SDMMC1CLKSOURCE_HSI48 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 530 #else
Kojto 122:f9eeca106725 531 #define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 532 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 533 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
Kojto 122:f9eeca106725 534 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
Kojto 122:f9eeca106725 535 #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
Kojto 122:f9eeca106725 536 /**
Kojto 122:f9eeca106725 537 * @}
Kojto 122:f9eeca106725 538 */
Kojto 122:f9eeca106725 539 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 540
Kojto 122:f9eeca106725 541 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
Kojto 122:f9eeca106725 542 * @{
Kojto 122:f9eeca106725 543 */
Kojto 122:f9eeca106725 544 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 545 #define RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 546 #else
Kojto 122:f9eeca106725 547 #define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 548 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 549 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
Kojto 122:f9eeca106725 550 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
Kojto 122:f9eeca106725 551 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
Kojto 122:f9eeca106725 552 /**
Kojto 122:f9eeca106725 553 * @}
Kojto 122:f9eeca106725 554 */
Kojto 122:f9eeca106725 555
Kojto 122:f9eeca106725 556 #if defined(USB_OTG_FS) || defined(USB)
Kojto 122:f9eeca106725 557 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source
Kojto 122:f9eeca106725 558 * @{
Kojto 122:f9eeca106725 559 */
Kojto 122:f9eeca106725 560 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 561 #define RCC_USBCLKSOURCE_HSI48 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 562 #else
Kojto 122:f9eeca106725 563 #define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 564 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 565 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
Kojto 122:f9eeca106725 566 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
Kojto 122:f9eeca106725 567 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
Kojto 122:f9eeca106725 568 /**
Kojto 122:f9eeca106725 569 * @}
Kojto 122:f9eeca106725 570 */
Kojto 122:f9eeca106725 571 #endif /* USB_OTG_FS || USB */
Kojto 122:f9eeca106725 572
Kojto 122:f9eeca106725 573 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
Kojto 122:f9eeca106725 574 * @{
Kojto 122:f9eeca106725 575 */
Kojto 122:f9eeca106725 576 #define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 577 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
AnnaBridge 145:64910690c574 578 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
Kojto 122:f9eeca106725 579 #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
AnnaBridge 145:64910690c574 580 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
Kojto 122:f9eeca106725 581 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
Kojto 122:f9eeca106725 582 /**
Kojto 122:f9eeca106725 583 * @}
Kojto 122:f9eeca106725 584 */
Kojto 122:f9eeca106725 585
Kojto 122:f9eeca106725 586 #if defined(SWPMI1)
Kojto 122:f9eeca106725 587 /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
Kojto 122:f9eeca106725 588 * @{
Kojto 122:f9eeca106725 589 */
AnnaBridge 145:64910690c574 590 #define RCC_SWPMI1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 591 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
Kojto 122:f9eeca106725 592 /**
Kojto 122:f9eeca106725 593 * @}
Kojto 122:f9eeca106725 594 */
Kojto 122:f9eeca106725 595 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 596
Kojto 122:f9eeca106725 597 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 598 /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source
Kojto 122:f9eeca106725 599 * @{
Kojto 122:f9eeca106725 600 */
AnnaBridge 145:64910690c574 601 #define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 602 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL
Kojto 122:f9eeca106725 603 /**
Kojto 122:f9eeca106725 604 * @}
Kojto 122:f9eeca106725 605 */
Kojto 122:f9eeca106725 606 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 607
Kojto 122:f9eeca106725 608 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
Kojto 122:f9eeca106725 609 * @{
Kojto 122:f9eeca106725 610 */
Kojto 122:f9eeca106725 611 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
Kojto 122:f9eeca106725 612 /**
Kojto 122:f9eeca106725 613 * @}
Kojto 122:f9eeca106725 614 */
Kojto 122:f9eeca106725 615
Kojto 122:f9eeca106725 616 #if defined(CRS)
Kojto 122:f9eeca106725 617
Kojto 122:f9eeca106725 618 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
Kojto 122:f9eeca106725 619 * @{
Kojto 122:f9eeca106725 620 */
Kojto 122:f9eeca106725 621 #define RCC_CRS_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 622 #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 623 #define RCC_CRS_SYNCOK ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 624 #define RCC_CRS_SYNCWARN ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 625 #define RCC_CRS_SYNCERR ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 626 #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 627 #define RCC_CRS_TRIMOVF ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 628 /**
Kojto 122:f9eeca106725 629 * @}
Kojto 122:f9eeca106725 630 */
Kojto 122:f9eeca106725 631
Kojto 122:f9eeca106725 632 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
Kojto 122:f9eeca106725 633 * @{
Kojto 122:f9eeca106725 634 */
Kojto 122:f9eeca106725 635 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */
Kojto 122:f9eeca106725 636 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
Kojto 122:f9eeca106725 637 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
Kojto 122:f9eeca106725 638 /**
Kojto 122:f9eeca106725 639 * @}
Kojto 122:f9eeca106725 640 */
Kojto 122:f9eeca106725 641
Kojto 122:f9eeca106725 642 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
Kojto 122:f9eeca106725 643 * @{
Kojto 122:f9eeca106725 644 */
Kojto 122:f9eeca106725 645 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */
Kojto 122:f9eeca106725 646 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
Kojto 122:f9eeca106725 647 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
Kojto 122:f9eeca106725 648 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
Kojto 122:f9eeca106725 649 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
Kojto 122:f9eeca106725 650 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
Kojto 122:f9eeca106725 651 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
Kojto 122:f9eeca106725 652 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
Kojto 122:f9eeca106725 653 /**
Kojto 122:f9eeca106725 654 * @}
Kojto 122:f9eeca106725 655 */
Kojto 122:f9eeca106725 656
Kojto 122:f9eeca106725 657 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
Kojto 122:f9eeca106725 658 * @{
Kojto 122:f9eeca106725 659 */
Kojto 122:f9eeca106725 660 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */
Kojto 122:f9eeca106725 661 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
Kojto 122:f9eeca106725 662 /**
Kojto 122:f9eeca106725 663 * @}
Kojto 122:f9eeca106725 664 */
Kojto 122:f9eeca106725 665
Kojto 122:f9eeca106725 666 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
Kojto 122:f9eeca106725 667 * @{
Kojto 122:f9eeca106725 668 */
Kojto 122:f9eeca106725 669 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
Kojto 122:f9eeca106725 670 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
Kojto 122:f9eeca106725 671 /**
Kojto 122:f9eeca106725 672 * @}
Kojto 122:f9eeca106725 673 */
Kojto 122:f9eeca106725 674
Kojto 122:f9eeca106725 675 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
Kojto 122:f9eeca106725 676 * @{
Kojto 122:f9eeca106725 677 */
Kojto 122:f9eeca106725 678 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */
Kojto 122:f9eeca106725 679 /**
Kojto 122:f9eeca106725 680 * @}
Kojto 122:f9eeca106725 681 */
Kojto 122:f9eeca106725 682
Kojto 122:f9eeca106725 683 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
Kojto 122:f9eeca106725 684 * @{
Kojto 122:f9eeca106725 685 */
Kojto 122:f9eeca106725 686 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
Kojto 122:f9eeca106725 687 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
Kojto 122:f9eeca106725 688 corresponds to a higher output frequency */
Kojto 122:f9eeca106725 689 /**
Kojto 122:f9eeca106725 690 * @}
Kojto 122:f9eeca106725 691 */
Kojto 122:f9eeca106725 692
Kojto 122:f9eeca106725 693 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
Kojto 122:f9eeca106725 694 * @{
Kojto 122:f9eeca106725 695 */
Kojto 122:f9eeca106725 696 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */
Kojto 122:f9eeca106725 697 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
Kojto 122:f9eeca106725 698 /**
Kojto 122:f9eeca106725 699 * @}
Kojto 122:f9eeca106725 700 */
Kojto 122:f9eeca106725 701
Kojto 122:f9eeca106725 702 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
Kojto 122:f9eeca106725 703 * @{
Kojto 122:f9eeca106725 704 */
Kojto 122:f9eeca106725 705 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
Kojto 122:f9eeca106725 706 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
Kojto 122:f9eeca106725 707 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
Kojto 122:f9eeca106725 708 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
Kojto 122:f9eeca106725 709 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
Kojto 122:f9eeca106725 710 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
Kojto 122:f9eeca106725 711 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
Kojto 122:f9eeca106725 712
Kojto 122:f9eeca106725 713 /**
Kojto 122:f9eeca106725 714 * @}
Kojto 122:f9eeca106725 715 */
Kojto 122:f9eeca106725 716
Kojto 122:f9eeca106725 717 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
Kojto 122:f9eeca106725 718 * @{
Kojto 122:f9eeca106725 719 */
Kojto 122:f9eeca106725 720 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
Kojto 122:f9eeca106725 721 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
Kojto 122:f9eeca106725 722 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
Kojto 122:f9eeca106725 723 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
Kojto 122:f9eeca106725 724 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
Kojto 122:f9eeca106725 725 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
Kojto 122:f9eeca106725 726 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
Kojto 122:f9eeca106725 727
Kojto 122:f9eeca106725 728 /**
Kojto 122:f9eeca106725 729 * @}
Kojto 122:f9eeca106725 730 */
Kojto 122:f9eeca106725 731
Kojto 122:f9eeca106725 732 #endif /* CRS */
Kojto 122:f9eeca106725 733
Kojto 122:f9eeca106725 734 /**
Kojto 122:f9eeca106725 735 * @}
Kojto 122:f9eeca106725 736 */
Kojto 122:f9eeca106725 737
Kojto 122:f9eeca106725 738 /* Exported macros -----------------------------------------------------------*/
Kojto 122:f9eeca106725 739 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto 122:f9eeca106725 740 * @{
Kojto 122:f9eeca106725 741 */
Kojto 122:f9eeca106725 742
Kojto 122:f9eeca106725 743
Kojto 122:f9eeca106725 744 /**
Kojto 122:f9eeca106725 745 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors.
Kojto 122:f9eeca106725 746 *
Kojto 122:f9eeca106725 747 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 122:f9eeca106725 748 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 749 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 750 *
Kojto 122:f9eeca106725 751 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
Kojto 122:f9eeca106725 752 * This parameter must be a number between 8 and 86.
Kojto 122:f9eeca106725 753 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
Kojto 122:f9eeca106725 754 * output frequency is between 64 and 344 MHz.
Kojto 122:f9eeca106725 755 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
Kojto 122:f9eeca106725 756 *
Kojto 122:f9eeca106725 757 * @param __PLLSAI1P__ specifies the division factor for SAI clock.
Kojto 122:f9eeca106725 758 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
Kojto 122:f9eeca106725 759 * else (2 to 31).
Kojto 122:f9eeca106725 760 * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
Kojto 122:f9eeca106725 761 *
Kojto 122:f9eeca106725 762 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
Kojto 122:f9eeca106725 763 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 764 * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
Kojto 122:f9eeca106725 765 *
Kojto 122:f9eeca106725 766 * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock.
Kojto 122:f9eeca106725 767 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 768 * ADC clock frequency = f(PLLSAI1) / PLLSAI1R
Kojto 122:f9eeca106725 769 *
Kojto 122:f9eeca106725 770 * @retval None
Kojto 122:f9eeca106725 771 */
Kojto 122:f9eeca106725 772 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 773
Kojto 122:f9eeca106725 774 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
Kojto 122:f9eeca106725 775 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
Kojto 122:f9eeca106725 776 ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
Kojto 122:f9eeca106725 777 ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) | \
Kojto 122:f9eeca106725 778 ((__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)))
Kojto 122:f9eeca106725 779
Kojto 122:f9eeca106725 780 #else
Kojto 122:f9eeca106725 781
Kojto 122:f9eeca106725 782 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
Kojto 122:f9eeca106725 783 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
Kojto 122:f9eeca106725 784 (((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \
Kojto 122:f9eeca106725 785 ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
Kojto 122:f9eeca106725 786 ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)))
Kojto 122:f9eeca106725 787
Kojto 122:f9eeca106725 788 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 789
Kojto 122:f9eeca106725 790 /**
Kojto 122:f9eeca106725 791 * @brief Macro to configure the PLLSAI1 clock multiplication factor N.
Kojto 122:f9eeca106725 792 *
Kojto 122:f9eeca106725 793 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 122:f9eeca106725 794 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 795 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 796 *
Kojto 122:f9eeca106725 797 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
Kojto 122:f9eeca106725 798 * This parameter must be a number between 8 and 86.
Kojto 122:f9eeca106725 799 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
Kojto 122:f9eeca106725 800 * output frequency is between 64 and 344 MHz.
Kojto 122:f9eeca106725 801 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
Kojto 122:f9eeca106725 802 *
Kojto 122:f9eeca106725 803 * @retval None
Kojto 122:f9eeca106725 804 */
Kojto 122:f9eeca106725 805 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
Kojto 122:f9eeca106725 806 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))
Kojto 122:f9eeca106725 807
Kojto 122:f9eeca106725 808 /** @brief Macro to configure the PLLSAI1 clock division factor P.
Kojto 122:f9eeca106725 809 *
Kojto 122:f9eeca106725 810 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 122:f9eeca106725 811 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 812 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 813 *
Kojto 122:f9eeca106725 814 * @param __PLLSAI1P__ specifies the division factor for SAI clock.
Kojto 122:f9eeca106725 815 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
Kojto 122:f9eeca106725 816 * else (2 to 31).
Kojto 122:f9eeca106725 817 * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
Kojto 122:f9eeca106725 818 *
Kojto 122:f9eeca106725 819 * @retval None
Kojto 122:f9eeca106725 820 */
Kojto 122:f9eeca106725 821 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 822
Kojto 122:f9eeca106725 823 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
Kojto 122:f9eeca106725 824 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))
Kojto 122:f9eeca106725 825
Kojto 122:f9eeca106725 826 #else
Kojto 122:f9eeca106725 827
Kojto 122:f9eeca106725 828 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
Kojto 122:f9eeca106725 829 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))
Kojto 122:f9eeca106725 830
Kojto 122:f9eeca106725 831 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 832
Kojto 122:f9eeca106725 833 /** @brief Macro to configure the PLLSAI1 clock division factor Q.
Kojto 122:f9eeca106725 834 *
Kojto 122:f9eeca106725 835 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 122:f9eeca106725 836 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 837 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 838 *
Kojto 122:f9eeca106725 839 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
Kojto 122:f9eeca106725 840 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 841 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
Kojto 122:f9eeca106725 842 *
Kojto 122:f9eeca106725 843 * @retval None
Kojto 122:f9eeca106725 844 */
Kojto 122:f9eeca106725 845 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
Kojto 122:f9eeca106725 846 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))
Kojto 122:f9eeca106725 847
Kojto 122:f9eeca106725 848 /** @brief Macro to configure the PLLSAI1 clock division factor R.
Kojto 122:f9eeca106725 849 *
Kojto 122:f9eeca106725 850 * @note This function must be used only when the PLLSAI1 is disabled.
Kojto 122:f9eeca106725 851 * @note PLLSAI1 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 852 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 853 *
Kojto 122:f9eeca106725 854 * @param __PLLSAI1R__ specifies the division factor for ADC clock.
Kojto 122:f9eeca106725 855 * This parameter must be in the range (2, 4, 6 or 8)
Kojto 122:f9eeca106725 856 * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
Kojto 122:f9eeca106725 857 *
Kojto 122:f9eeca106725 858 * @retval None
Kojto 122:f9eeca106725 859 */
Kojto 122:f9eeca106725 860 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
Kojto 122:f9eeca106725 861 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))
Kojto 122:f9eeca106725 862
Kojto 122:f9eeca106725 863 /**
Kojto 122:f9eeca106725 864 * @brief Macros to enable or disable the PLLSAI1.
Kojto 122:f9eeca106725 865 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 866 * @retval None
Kojto 122:f9eeca106725 867 */
Kojto 122:f9eeca106725 868
Kojto 122:f9eeca106725 869 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
Kojto 122:f9eeca106725 870
Kojto 122:f9eeca106725 871 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
Kojto 122:f9eeca106725 872
Kojto 122:f9eeca106725 873 /**
Kojto 122:f9eeca106725 874 * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
Kojto 122:f9eeca106725 875 * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
Kojto 122:f9eeca106725 876 * This is mainly used to save Power.
Kojto 122:f9eeca106725 877 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
Kojto 122:f9eeca106725 878 * This parameter can be one or a combination of the following values:
Kojto 122:f9eeca106725 879 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
Kojto 122:f9eeca106725 880 * high-quality audio performance on SAI interface in case.
Kojto 122:f9eeca106725 881 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
Kojto 122:f9eeca106725 882 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
Kojto 122:f9eeca106725 883 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
Kojto 122:f9eeca106725 884 * @retval None
Kojto 122:f9eeca106725 885 */
Kojto 122:f9eeca106725 886
Kojto 122:f9eeca106725 887 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Kojto 122:f9eeca106725 888
Kojto 122:f9eeca106725 889 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Kojto 122:f9eeca106725 890
Kojto 122:f9eeca106725 891 /**
Kojto 122:f9eeca106725 892 * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
Kojto 122:f9eeca106725 893 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
Kojto 122:f9eeca106725 894 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 895 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
Kojto 122:f9eeca106725 896 * high-quality audio performance on SAI interface in case.
Kojto 122:f9eeca106725 897 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
Kojto 122:f9eeca106725 898 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
Kojto 122:f9eeca106725 899 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
Kojto 122:f9eeca106725 900 * @retval SET / RESET
Kojto 122:f9eeca106725 901 */
Kojto 122:f9eeca106725 902 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Kojto 122:f9eeca106725 903
Kojto 122:f9eeca106725 904 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 905
Kojto 122:f9eeca106725 906 /**
Kojto 122:f9eeca106725 907 * @brief Macro to configure the PLLSAI2 clock multiplication and division factors.
Kojto 122:f9eeca106725 908 *
Kojto 122:f9eeca106725 909 * @note This function must be used only when the PLLSAI2 is disabled.
Kojto 122:f9eeca106725 910 * @note PLLSAI2 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 911 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 912 *
Kojto 122:f9eeca106725 913 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
Kojto 122:f9eeca106725 914 * This parameter must be a number between 8 and 86.
Kojto 122:f9eeca106725 915 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
Kojto 122:f9eeca106725 916 * output frequency is between 64 and 344 MHz.
Kojto 122:f9eeca106725 917 *
Kojto 122:f9eeca106725 918 * @param __PLLSAI2P__ specifies the division factor for SAI clock.
Kojto 122:f9eeca106725 919 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
Kojto 122:f9eeca106725 920 * else (2 to 31).
Kojto 122:f9eeca106725 921 * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P
Kojto 122:f9eeca106725 922 *
Kojto 122:f9eeca106725 923 * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock.
Kojto 122:f9eeca106725 924 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 925 *
Kojto 122:f9eeca106725 926 * @retval None
Kojto 122:f9eeca106725 927 */
Kojto 122:f9eeca106725 928
Kojto 122:f9eeca106725 929 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 930
Kojto 122:f9eeca106725 931 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
Kojto 122:f9eeca106725 932 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
Kojto 122:f9eeca106725 933 ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) | \
Kojto 122:f9eeca106725 934 ((__PLLSAI2P__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV)))
Kojto 122:f9eeca106725 935
Kojto 122:f9eeca106725 936 #else
Kojto 122:f9eeca106725 937
Kojto 122:f9eeca106725 938 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
Kojto 122:f9eeca106725 939 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
Kojto 122:f9eeca106725 940 (((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \
Kojto 122:f9eeca106725 941 ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)))
Kojto 122:f9eeca106725 942
Kojto 122:f9eeca106725 943 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 944
Kojto 122:f9eeca106725 945
Kojto 122:f9eeca106725 946 /**
Kojto 122:f9eeca106725 947 * @brief Macro to configure the PLLSAI2 clock multiplication factor N.
Kojto 122:f9eeca106725 948 *
Kojto 122:f9eeca106725 949 * @note This function must be used only when the PLLSAI2 is disabled.
Kojto 122:f9eeca106725 950 * @note PLLSAI2 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 951 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 952 *
Kojto 122:f9eeca106725 953 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
Kojto 122:f9eeca106725 954 * This parameter must be a number between 8 and 86.
Kojto 122:f9eeca106725 955 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
Kojto 122:f9eeca106725 956 * output frequency is between 64 and 344 MHz.
Kojto 122:f9eeca106725 957 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
Kojto 122:f9eeca106725 958 *
Kojto 122:f9eeca106725 959 * @retval None
Kojto 122:f9eeca106725 960 */
Kojto 122:f9eeca106725 961 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
Kojto 122:f9eeca106725 962 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))
Kojto 122:f9eeca106725 963
Kojto 122:f9eeca106725 964 /** @brief Macro to configure the PLLSAI2 clock division factor P.
Kojto 122:f9eeca106725 965 *
Kojto 122:f9eeca106725 966 * @note This function must be used only when the PLLSAI2 is disabled.
Kojto 122:f9eeca106725 967 * @note PLLSAI2 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 968 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 969 *
Kojto 122:f9eeca106725 970 * @param __PLLSAI2P__ specifies the division factor.
Kojto 122:f9eeca106725 971 * This parameter must be a number in the range (7 or 17).
Kojto 122:f9eeca106725 972 * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
Kojto 122:f9eeca106725 973 *
Kojto 122:f9eeca106725 974 * @retval None
Kojto 122:f9eeca106725 975 */
Kojto 122:f9eeca106725 976 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
Kojto 122:f9eeca106725 977 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))
Kojto 122:f9eeca106725 978
Kojto 122:f9eeca106725 979 /** @brief Macro to configure the PLLSAI2 clock division factor R.
Kojto 122:f9eeca106725 980 *
Kojto 122:f9eeca106725 981 * @note This function must be used only when the PLLSAI2 is disabled.
Kojto 122:f9eeca106725 982 * @note PLLSAI2 clock source is common with the main PLL (configured through
Kojto 122:f9eeca106725 983 * __HAL_RCC_PLL_CONFIG() macro)
Kojto 122:f9eeca106725 984 *
Kojto 122:f9eeca106725 985 * @param __PLLSAI2R__ specifies the division factor.
Kojto 122:f9eeca106725 986 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 987 * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__
Kojto 122:f9eeca106725 988 *
Kojto 122:f9eeca106725 989 * @retval None
Kojto 122:f9eeca106725 990 */
Kojto 122:f9eeca106725 991 #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
Kojto 122:f9eeca106725 992 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))
Kojto 122:f9eeca106725 993
Kojto 122:f9eeca106725 994 /**
Kojto 122:f9eeca106725 995 * @brief Macros to enable or disable the PLLSAI2.
Kojto 122:f9eeca106725 996 * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 997 * @retval None
Kojto 122:f9eeca106725 998 */
Kojto 122:f9eeca106725 999
Kojto 122:f9eeca106725 1000 #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
Kojto 122:f9eeca106725 1001
Kojto 122:f9eeca106725 1002 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
Kojto 122:f9eeca106725 1003
Kojto 122:f9eeca106725 1004 /**
Kojto 122:f9eeca106725 1005 * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).
Kojto 122:f9eeca106725 1006 * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
Kojto 122:f9eeca106725 1007 * This is mainly used to save Power.
Kojto 122:f9eeca106725 1008 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
Kojto 122:f9eeca106725 1009 * This parameter can be one or a combination of the following values:
Kojto 122:f9eeca106725 1010 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
Kojto 122:f9eeca106725 1011 * high-quality audio performance on SAI interface in case.
Kojto 122:f9eeca106725 1012 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
Kojto 122:f9eeca106725 1013 * @retval None
Kojto 122:f9eeca106725 1014 */
Kojto 122:f9eeca106725 1015
Kojto 122:f9eeca106725 1016 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
Kojto 122:f9eeca106725 1017
Kojto 122:f9eeca106725 1018 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
Kojto 122:f9eeca106725 1019
Kojto 122:f9eeca106725 1020 /**
Kojto 122:f9eeca106725 1021 * @brief Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).
Kojto 122:f9eeca106725 1022 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
Kojto 122:f9eeca106725 1023 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1024 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
Kojto 122:f9eeca106725 1025 * high-quality audio performance on SAI interface in case.
Kojto 122:f9eeca106725 1026 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
Kojto 122:f9eeca106725 1027 * @retval SET / RESET
Kojto 122:f9eeca106725 1028 */
Kojto 122:f9eeca106725 1029 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
Kojto 122:f9eeca106725 1030
Kojto 122:f9eeca106725 1031 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 1032
Kojto 122:f9eeca106725 1033 /**
Kojto 122:f9eeca106725 1034 * @brief Macro to configure the SAI1 clock source.
Kojto 122:f9eeca106725 1035 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
Kojto 122:f9eeca106725 1036 * from the PLLSAI1, system PLL or external clock (through a dedicated pin).
Kojto 122:f9eeca106725 1037 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1038 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
Kojto 122:f9eeca106725 1039 @if STM32L486xx
Kojto 122:f9eeca106725 1040 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
Kojto 122:f9eeca106725 1041 @endif
AnnaBridge 145:64910690c574 1042 @if STM32L4A6xx
AnnaBridge 145:64910690c574 1043 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
AnnaBridge 145:64910690c574 1044 @endif
Kojto 122:f9eeca106725 1045 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
Kojto 122:f9eeca106725 1046 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
Kojto 122:f9eeca106725 1047 *
Kojto 122:f9eeca106725 1048 @if STM32L443xx
Kojto 122:f9eeca106725 1049 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
Kojto 122:f9eeca106725 1050 @endif
AnnaBridge 145:64910690c574 1051 @if STM32L462xx
AnnaBridge 145:64910690c574 1052 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
AnnaBridge 145:64910690c574 1053 @endif
Kojto 122:f9eeca106725 1054 *
Kojto 122:f9eeca106725 1055 * @retval None
Kojto 122:f9eeca106725 1056 */
Kojto 122:f9eeca106725 1057 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
Kojto 122:f9eeca106725 1058 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
Kojto 122:f9eeca106725 1059
Kojto 122:f9eeca106725 1060 /** @brief Macro to get the SAI1 clock source.
Kojto 122:f9eeca106725 1061 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1062 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
Kojto 122:f9eeca106725 1063 @if STM32L486xx
Kojto 122:f9eeca106725 1064 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
Kojto 122:f9eeca106725 1065 @endif
AnnaBridge 145:64910690c574 1066 @if STM32L4A6xx
AnnaBridge 145:64910690c574 1067 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
AnnaBridge 145:64910690c574 1068 @endif
Kojto 122:f9eeca106725 1069 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
Kojto 122:f9eeca106725 1070 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
Kojto 122:f9eeca106725 1071 *
Kojto 122:f9eeca106725 1072 * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1
Kojto 122:f9eeca106725 1073 * clock source when PLLs are disabled for devices without PLLSAI2.
Kojto 122:f9eeca106725 1074 *
Kojto 122:f9eeca106725 1075 */
Kojto 122:f9eeca106725 1076 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))
Kojto 122:f9eeca106725 1077
Kojto 122:f9eeca106725 1078 #if defined(SAI2)
Kojto 122:f9eeca106725 1079
Kojto 122:f9eeca106725 1080 /**
Kojto 122:f9eeca106725 1081 * @brief Macro to configure the SAI2 clock source.
Kojto 122:f9eeca106725 1082 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
Kojto 122:f9eeca106725 1083 * from the PLLSAI2, system PLL or external clock (through a dedicated pin).
Kojto 122:f9eeca106725 1084 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1085 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
Kojto 122:f9eeca106725 1086 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
Kojto 122:f9eeca106725 1087 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
Kojto 122:f9eeca106725 1088 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
Kojto 122:f9eeca106725 1089 *
Kojto 122:f9eeca106725 1090 * @retval None
Kojto 122:f9eeca106725 1091 */
Kojto 122:f9eeca106725 1092 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
Kojto 122:f9eeca106725 1093 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
Kojto 122:f9eeca106725 1094
Kojto 122:f9eeca106725 1095 /** @brief Macro to get the SAI2 clock source.
Kojto 122:f9eeca106725 1096 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1097 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
Kojto 122:f9eeca106725 1098 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
Kojto 122:f9eeca106725 1099 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
Kojto 122:f9eeca106725 1100 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
Kojto 122:f9eeca106725 1101 */
Kojto 122:f9eeca106725 1102 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))
Kojto 122:f9eeca106725 1103
Kojto 122:f9eeca106725 1104 #endif /* SAI2 */
Kojto 122:f9eeca106725 1105
Kojto 122:f9eeca106725 1106 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
Kojto 122:f9eeca106725 1107 *
Kojto 122:f9eeca106725 1108 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
Kojto 122:f9eeca106725 1109 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1110 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
Kojto 122:f9eeca106725 1111 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
Kojto 122:f9eeca106725 1112 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
Kojto 122:f9eeca106725 1113 * @retval None
Kojto 122:f9eeca106725 1114 */
Kojto 122:f9eeca106725 1115 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1116 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
Kojto 122:f9eeca106725 1117
Kojto 122:f9eeca106725 1118 /** @brief Macro to get the I2C1 clock source.
Kojto 122:f9eeca106725 1119 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1120 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
Kojto 122:f9eeca106725 1121 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
Kojto 122:f9eeca106725 1122 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
Kojto 122:f9eeca106725 1123 */
Kojto 122:f9eeca106725 1124 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
Kojto 122:f9eeca106725 1125
Kojto 122:f9eeca106725 1126 #if defined(I2C2)
Kojto 122:f9eeca106725 1127
Kojto 122:f9eeca106725 1128 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto 122:f9eeca106725 1129 *
Kojto 122:f9eeca106725 1130 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
Kojto 122:f9eeca106725 1131 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1132 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
Kojto 122:f9eeca106725 1133 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
Kojto 122:f9eeca106725 1134 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
Kojto 122:f9eeca106725 1135 * @retval None
Kojto 122:f9eeca106725 1136 */
Kojto 122:f9eeca106725 1137 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
Kojto 122:f9eeca106725 1138 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
Kojto 122:f9eeca106725 1139
Kojto 122:f9eeca106725 1140 /** @brief Macro to get the I2C2 clock source.
Kojto 122:f9eeca106725 1141 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1142 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
Kojto 122:f9eeca106725 1143 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
Kojto 122:f9eeca106725 1144 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
Kojto 122:f9eeca106725 1145 */
Kojto 122:f9eeca106725 1146 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
Kojto 122:f9eeca106725 1147
Kojto 122:f9eeca106725 1148 #endif /* I2C2 */
Kojto 122:f9eeca106725 1149
Kojto 122:f9eeca106725 1150 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto 122:f9eeca106725 1151 *
Kojto 122:f9eeca106725 1152 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
Kojto 122:f9eeca106725 1153 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1154 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
Kojto 122:f9eeca106725 1155 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
Kojto 122:f9eeca106725 1156 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
Kojto 122:f9eeca106725 1157 * @retval None
Kojto 122:f9eeca106725 1158 */
Kojto 122:f9eeca106725 1159 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
Kojto 122:f9eeca106725 1160 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
Kojto 122:f9eeca106725 1161
Kojto 122:f9eeca106725 1162 /** @brief Macro to get the I2C3 clock source.
Kojto 122:f9eeca106725 1163 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1164 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
Kojto 122:f9eeca106725 1165 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
Kojto 122:f9eeca106725 1166 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
Kojto 122:f9eeca106725 1167 */
Kojto 122:f9eeca106725 1168 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
Kojto 122:f9eeca106725 1169
AnnaBridge 145:64910690c574 1170 #if defined(I2C4)
AnnaBridge 145:64910690c574 1171
AnnaBridge 145:64910690c574 1172 /** @brief Macro to configure the I2C4 clock (I2C4CLK).
AnnaBridge 145:64910690c574 1173 *
AnnaBridge 145:64910690c574 1174 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
AnnaBridge 145:64910690c574 1175 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 1176 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
AnnaBridge 145:64910690c574 1177 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
AnnaBridge 145:64910690c574 1178 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
AnnaBridge 145:64910690c574 1179 * @retval None
AnnaBridge 145:64910690c574 1180 */
AnnaBridge 145:64910690c574 1181 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
AnnaBridge 145:64910690c574 1182 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
AnnaBridge 145:64910690c574 1183
AnnaBridge 145:64910690c574 1184 /** @brief Macro to get the I2C4 clock source.
AnnaBridge 145:64910690c574 1185 * @retval The clock source can be one of the following values:
AnnaBridge 145:64910690c574 1186 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
AnnaBridge 145:64910690c574 1187 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
AnnaBridge 145:64910690c574 1188 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
AnnaBridge 145:64910690c574 1189 */
AnnaBridge 145:64910690c574 1190 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)))
AnnaBridge 145:64910690c574 1191
AnnaBridge 145:64910690c574 1192 #endif /* I2C4 */
AnnaBridge 145:64910690c574 1193
AnnaBridge 145:64910690c574 1194
Kojto 122:f9eeca106725 1195 /** @brief Macro to configure the USART1 clock (USART1CLK).
Kojto 122:f9eeca106725 1196 *
Kojto 122:f9eeca106725 1197 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
Kojto 122:f9eeca106725 1198 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1199 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto 122:f9eeca106725 1200 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
Kojto 122:f9eeca106725 1201 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
Kojto 122:f9eeca106725 1202 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock
Kojto 122:f9eeca106725 1203 * @retval None
Kojto 122:f9eeca106725 1204 */
Kojto 122:f9eeca106725 1205 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1206 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
Kojto 122:f9eeca106725 1207
Kojto 122:f9eeca106725 1208 /** @brief Macro to get the USART1 clock source.
Kojto 122:f9eeca106725 1209 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1210 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
Kojto 122:f9eeca106725 1211 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
Kojto 122:f9eeca106725 1212 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
Kojto 122:f9eeca106725 1213 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
Kojto 122:f9eeca106725 1214 */
Kojto 122:f9eeca106725 1215 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
Kojto 122:f9eeca106725 1216
Kojto 122:f9eeca106725 1217 /** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto 122:f9eeca106725 1218 *
Kojto 122:f9eeca106725 1219 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
Kojto 122:f9eeca106725 1220 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1221 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
Kojto 122:f9eeca106725 1222 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
Kojto 122:f9eeca106725 1223 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
Kojto 122:f9eeca106725 1224 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
Kojto 122:f9eeca106725 1225 * @retval None
Kojto 122:f9eeca106725 1226 */
Kojto 122:f9eeca106725 1227 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
Kojto 122:f9eeca106725 1228 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
Kojto 122:f9eeca106725 1229
Kojto 122:f9eeca106725 1230 /** @brief Macro to get the USART2 clock source.
Kojto 122:f9eeca106725 1231 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1232 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
Kojto 122:f9eeca106725 1233 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
Kojto 122:f9eeca106725 1234 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
Kojto 122:f9eeca106725 1235 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
Kojto 122:f9eeca106725 1236 */
Kojto 122:f9eeca106725 1237 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
Kojto 122:f9eeca106725 1238
Kojto 122:f9eeca106725 1239 #if defined(USART3)
Kojto 122:f9eeca106725 1240
Kojto 122:f9eeca106725 1241 /** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto 122:f9eeca106725 1242 *
Kojto 122:f9eeca106725 1243 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
Kojto 122:f9eeca106725 1244 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1245 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
Kojto 122:f9eeca106725 1246 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
Kojto 122:f9eeca106725 1247 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
Kojto 122:f9eeca106725 1248 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
Kojto 122:f9eeca106725 1249 * @retval None
Kojto 122:f9eeca106725 1250 */
Kojto 122:f9eeca106725 1251 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
Kojto 122:f9eeca106725 1252 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
Kojto 122:f9eeca106725 1253
Kojto 122:f9eeca106725 1254 /** @brief Macro to get the USART3 clock source.
Kojto 122:f9eeca106725 1255 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1256 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
Kojto 122:f9eeca106725 1257 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
Kojto 122:f9eeca106725 1258 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
Kojto 122:f9eeca106725 1259 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
Kojto 122:f9eeca106725 1260 */
Kojto 122:f9eeca106725 1261 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
Kojto 122:f9eeca106725 1262
Kojto 122:f9eeca106725 1263 #endif /* USART3 */
Kojto 122:f9eeca106725 1264
Kojto 122:f9eeca106725 1265 #if defined(UART4)
Kojto 122:f9eeca106725 1266
Kojto 122:f9eeca106725 1267 /** @brief Macro to configure the UART4 clock (UART4CLK).
Kojto 122:f9eeca106725 1268 *
Kojto 122:f9eeca106725 1269 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
Kojto 122:f9eeca106725 1270 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1271 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
Kojto 122:f9eeca106725 1272 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
Kojto 122:f9eeca106725 1273 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
Kojto 122:f9eeca106725 1274 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
Kojto 122:f9eeca106725 1275 * @retval None
Kojto 122:f9eeca106725 1276 */
Kojto 122:f9eeca106725 1277 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
Kojto 122:f9eeca106725 1278 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
Kojto 122:f9eeca106725 1279
Kojto 122:f9eeca106725 1280 /** @brief Macro to get the UART4 clock source.
Kojto 122:f9eeca106725 1281 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1282 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
Kojto 122:f9eeca106725 1283 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
Kojto 122:f9eeca106725 1284 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
Kojto 122:f9eeca106725 1285 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
Kojto 122:f9eeca106725 1286 */
Kojto 122:f9eeca106725 1287 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))
Kojto 122:f9eeca106725 1288
Kojto 122:f9eeca106725 1289 #endif /* UART4 */
Kojto 122:f9eeca106725 1290
Kojto 122:f9eeca106725 1291 #if defined(UART5)
Kojto 122:f9eeca106725 1292
Kojto 122:f9eeca106725 1293 /** @brief Macro to configure the UART5 clock (UART5CLK).
Kojto 122:f9eeca106725 1294 *
Kojto 122:f9eeca106725 1295 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
Kojto 122:f9eeca106725 1296 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1297 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
Kojto 122:f9eeca106725 1298 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
Kojto 122:f9eeca106725 1299 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
Kojto 122:f9eeca106725 1300 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
Kojto 122:f9eeca106725 1301 * @retval None
Kojto 122:f9eeca106725 1302 */
Kojto 122:f9eeca106725 1303 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
Kojto 122:f9eeca106725 1304 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
Kojto 122:f9eeca106725 1305
Kojto 122:f9eeca106725 1306 /** @brief Macro to get the UART5 clock source.
Kojto 122:f9eeca106725 1307 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1308 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
Kojto 122:f9eeca106725 1309 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
Kojto 122:f9eeca106725 1310 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
Kojto 122:f9eeca106725 1311 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
Kojto 122:f9eeca106725 1312 */
Kojto 122:f9eeca106725 1313 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))
Kojto 122:f9eeca106725 1314
Kojto 122:f9eeca106725 1315 #endif /* UART5 */
Kojto 122:f9eeca106725 1316
Kojto 122:f9eeca106725 1317 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
Kojto 122:f9eeca106725 1318 *
Kojto 122:f9eeca106725 1319 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
Kojto 122:f9eeca106725 1320 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1321 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
Kojto 122:f9eeca106725 1322 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
Kojto 122:f9eeca106725 1323 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
Kojto 122:f9eeca106725 1324 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
Kojto 122:f9eeca106725 1325 * @retval None
Kojto 122:f9eeca106725 1326 */
Kojto 122:f9eeca106725 1327 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1328 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
Kojto 122:f9eeca106725 1329
Kojto 122:f9eeca106725 1330 /** @brief Macro to get the LPUART1 clock source.
Kojto 122:f9eeca106725 1331 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1332 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
Kojto 122:f9eeca106725 1333 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
Kojto 122:f9eeca106725 1334 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
Kojto 122:f9eeca106725 1335 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
Kojto 122:f9eeca106725 1336 */
Kojto 122:f9eeca106725 1337 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
Kojto 122:f9eeca106725 1338
Kojto 122:f9eeca106725 1339 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
Kojto 122:f9eeca106725 1340 *
Kojto 122:f9eeca106725 1341 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
Kojto 122:f9eeca106725 1342 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 1343 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock
Kojto 122:f9eeca106725 1344 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
Kojto 122:f9eeca106725 1345 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
Kojto 122:f9eeca106725 1346 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
Kojto 122:f9eeca106725 1347 * @retval None
Kojto 122:f9eeca106725 1348 */
Kojto 122:f9eeca106725 1349 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1350 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
Kojto 122:f9eeca106725 1351
Kojto 122:f9eeca106725 1352 /** @brief Macro to get the LPTIM1 clock source.
Kojto 122:f9eeca106725 1353 * @retval The clock source can be one of the following values:
AnnaBridge 145:64910690c574 1354 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
Kojto 122:f9eeca106725 1355 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
Kojto 122:f9eeca106725 1356 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
Kojto 122:f9eeca106725 1357 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
Kojto 122:f9eeca106725 1358 */
Kojto 122:f9eeca106725 1359 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
Kojto 122:f9eeca106725 1360
Kojto 122:f9eeca106725 1361 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK).
Kojto 122:f9eeca106725 1362 *
Kojto 122:f9eeca106725 1363 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
Kojto 122:f9eeca106725 1364 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 1365 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock
Kojto 122:f9eeca106725 1366 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
Kojto 122:f9eeca106725 1367 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock
Kojto 122:f9eeca106725 1368 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
Kojto 122:f9eeca106725 1369 * @retval None
Kojto 122:f9eeca106725 1370 */
Kojto 122:f9eeca106725 1371 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
Kojto 122:f9eeca106725 1372 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
Kojto 122:f9eeca106725 1373
Kojto 122:f9eeca106725 1374 /** @brief Macro to get the LPTIM2 clock source.
Kojto 122:f9eeca106725 1375 * @retval The clock source can be one of the following values:
AnnaBridge 145:64910690c574 1376 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
Kojto 122:f9eeca106725 1377 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock
Kojto 122:f9eeca106725 1378 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock
Kojto 122:f9eeca106725 1379 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock
Kojto 122:f9eeca106725 1380 */
Kojto 122:f9eeca106725 1381 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
Kojto 122:f9eeca106725 1382
Kojto 122:f9eeca106725 1383 #if defined(SDMMC1)
Kojto 122:f9eeca106725 1384
Kojto 122:f9eeca106725 1385 /** @brief Macro to configure the SDMMC1 clock.
Kojto 122:f9eeca106725 1386 *
AnnaBridge 145:64910690c574 1387 @if STM32L443xx
AnnaBridge 145:64910690c574 1388 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
AnnaBridge 145:64910690c574 1389 @endif
AnnaBridge 145:64910690c574 1390 @if STM32L462xx
AnnaBridge 145:64910690c574 1391 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
AnnaBridge 145:64910690c574 1392 @endif
Kojto 122:f9eeca106725 1393 @if STM32L486xx
Kojto 122:f9eeca106725 1394 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Kojto 122:f9eeca106725 1395 @endif
AnnaBridge 145:64910690c574 1396 @if STM32L4A6xx
Kojto 122:f9eeca106725 1397 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Kojto 122:f9eeca106725 1398 @endif
Kojto 122:f9eeca106725 1399 *
Kojto 122:f9eeca106725 1400 * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
Kojto 122:f9eeca106725 1401 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 1402 @if STM32L443xx
AnnaBridge 145:64910690c574 1403 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge 145:64910690c574 1404 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1405 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1406 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1407 @endif
AnnaBridge 145:64910690c574 1408 @if STM32L462xx
AnnaBridge 145:64910690c574 1409 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge 145:64910690c574 1410 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1411 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1412 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1413 @endif
Kojto 122:f9eeca106725 1414 @if STM32L486xx
Kojto 122:f9eeca106725 1415 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
Kojto 122:f9eeca106725 1416 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
Kojto 122:f9eeca106725 1417 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1418 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
Kojto 122:f9eeca106725 1419 @endif
AnnaBridge 145:64910690c574 1420 @if STM32L4A6xx
Kojto 122:f9eeca106725 1421 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
Kojto 122:f9eeca106725 1422 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
Kojto 122:f9eeca106725 1423 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1424 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
Kojto 122:f9eeca106725 1425 @endif
Kojto 122:f9eeca106725 1426 * @retval None
Kojto 122:f9eeca106725 1427 */
Kojto 122:f9eeca106725 1428 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1429 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
Kojto 122:f9eeca106725 1430
Kojto 122:f9eeca106725 1431 /** @brief Macro to get the SDMMC1 clock.
Kojto 122:f9eeca106725 1432 * @retval The clock source can be one of the following values:
AnnaBridge 145:64910690c574 1433 @if STM32L443xx
AnnaBridge 145:64910690c574 1434 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge 145:64910690c574 1435 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1436 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1437 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1438 @endif
AnnaBridge 145:64910690c574 1439 @if STM32L462xx
AnnaBridge 145:64910690c574 1440 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge 145:64910690c574 1441 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1442 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1443 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1444 @endif
Kojto 122:f9eeca106725 1445 @if STM32L486xx
Kojto 122:f9eeca106725 1446 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
Kojto 122:f9eeca106725 1447 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
Kojto 122:f9eeca106725 1448 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1449 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
Kojto 122:f9eeca106725 1450 @endif
AnnaBridge 145:64910690c574 1451 @if STM32L4A6xx
Kojto 122:f9eeca106725 1452 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
Kojto 122:f9eeca106725 1453 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
Kojto 122:f9eeca106725 1454 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
AnnaBridge 145:64910690c574 1455 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
Kojto 122:f9eeca106725 1456 @endif
Kojto 122:f9eeca106725 1457 */
Kojto 122:f9eeca106725 1458 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Kojto 122:f9eeca106725 1459
Kojto 122:f9eeca106725 1460 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 1461
Kojto 122:f9eeca106725 1462 /** @brief Macro to configure the RNG clock.
Kojto 122:f9eeca106725 1463 *
Kojto 122:f9eeca106725 1464 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Kojto 122:f9eeca106725 1465 *
Kojto 122:f9eeca106725 1466 * @param __RNG_CLKSOURCE__ specifies the RNG clock source.
Kojto 122:f9eeca106725 1467 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 1468 @if STM32L443xx
AnnaBridge 145:64910690c574 1469 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
AnnaBridge 145:64910690c574 1470 @endif
AnnaBridge 145:64910690c574 1471 @if STM32L462xx
AnnaBridge 145:64910690c574 1472 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
AnnaBridge 145:64910690c574 1473 @endif
Kojto 122:f9eeca106725 1474 @if STM32L486xx
Kojto 122:f9eeca106725 1475 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
Kojto 122:f9eeca106725 1476 @endif
AnnaBridge 145:64910690c574 1477 @if STM32L4A6xx
Kojto 122:f9eeca106725 1478 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
Kojto 122:f9eeca106725 1479 @endif
Kojto 122:f9eeca106725 1480 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
Kojto 122:f9eeca106725 1481 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock
Kojto 122:f9eeca106725 1482 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
Kojto 122:f9eeca106725 1483 * @retval None
Kojto 122:f9eeca106725 1484 */
Kojto 122:f9eeca106725 1485 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
Kojto 122:f9eeca106725 1486 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))
Kojto 122:f9eeca106725 1487
Kojto 122:f9eeca106725 1488 /** @brief Macro to get the RNG clock.
Kojto 122:f9eeca106725 1489 * @retval The clock source can be one of the following values:
AnnaBridge 145:64910690c574 1490 @if STM32L443xx
AnnaBridge 145:64910690c574 1491 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
AnnaBridge 145:64910690c574 1492 @endif
AnnaBridge 145:64910690c574 1493 @if STM32L462xx
AnnaBridge 145:64910690c574 1494 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
AnnaBridge 145:64910690c574 1495 @endif
Kojto 122:f9eeca106725 1496 @if STM32L486xx
Kojto 122:f9eeca106725 1497 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
Kojto 122:f9eeca106725 1498 @endif
AnnaBridge 145:64910690c574 1499 @if STM32L4A6xx
Kojto 122:f9eeca106725 1500 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
Kojto 122:f9eeca106725 1501 @endif
Kojto 122:f9eeca106725 1502 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
Kojto 122:f9eeca106725 1503 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
Kojto 122:f9eeca106725 1504 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock
Kojto 122:f9eeca106725 1505 */
Kojto 122:f9eeca106725 1506 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Kojto 122:f9eeca106725 1507
Kojto 122:f9eeca106725 1508 #if defined(USB_OTG_FS) || defined(USB)
Kojto 122:f9eeca106725 1509
Kojto 122:f9eeca106725 1510 /** @brief Macro to configure the USB clock (USBCLK).
Kojto 122:f9eeca106725 1511 *
Kojto 122:f9eeca106725 1512 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Kojto 122:f9eeca106725 1513 *
Kojto 122:f9eeca106725 1514 * @param __USB_CLKSOURCE__ specifies the USB clock source.
Kojto 122:f9eeca106725 1515 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 1516 @if STM32L443xx
AnnaBridge 145:64910690c574 1517 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
AnnaBridge 145:64910690c574 1518 @endif
AnnaBridge 145:64910690c574 1519 @if STM32L462xx
AnnaBridge 145:64910690c574 1520 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
AnnaBridge 145:64910690c574 1521 @endif
Kojto 122:f9eeca106725 1522 @if STM32L486xx
Kojto 122:f9eeca106725 1523 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
Kojto 122:f9eeca106725 1524 @endif
AnnaBridge 145:64910690c574 1525 @if STM32L4A6xx
Kojto 122:f9eeca106725 1526 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
Kojto 122:f9eeca106725 1527 @endif
Kojto 122:f9eeca106725 1528 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
Kojto 122:f9eeca106725 1529 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
Kojto 122:f9eeca106725 1530 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
Kojto 122:f9eeca106725 1531 * @retval None
Kojto 122:f9eeca106725 1532 */
Kojto 122:f9eeca106725 1533 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
Kojto 122:f9eeca106725 1534 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))
Kojto 122:f9eeca106725 1535
Kojto 122:f9eeca106725 1536 /** @brief Macro to get the USB clock source.
Kojto 122:f9eeca106725 1537 * @retval The clock source can be one of the following values:
AnnaBridge 145:64910690c574 1538 @if STM32L443xx
AnnaBridge 145:64910690c574 1539 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
AnnaBridge 145:64910690c574 1540 @endif
AnnaBridge 145:64910690c574 1541 @if STM32L462xx
AnnaBridge 145:64910690c574 1542 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
AnnaBridge 145:64910690c574 1543 @endif
Kojto 122:f9eeca106725 1544 @if STM32L486xx
Kojto 122:f9eeca106725 1545 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
Kojto 122:f9eeca106725 1546 @endif
AnnaBridge 145:64910690c574 1547 @if STM32L4A6xx
Kojto 122:f9eeca106725 1548 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
Kojto 122:f9eeca106725 1549 @endif
Kojto 122:f9eeca106725 1550 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
Kojto 122:f9eeca106725 1551 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
Kojto 122:f9eeca106725 1552 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
Kojto 122:f9eeca106725 1553 */
Kojto 122:f9eeca106725 1554 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Kojto 122:f9eeca106725 1555
Kojto 122:f9eeca106725 1556 #endif /* USB_OTG_FS || USB */
Kojto 122:f9eeca106725 1557
Kojto 122:f9eeca106725 1558 /** @brief Macro to configure the ADC interface clock.
Kojto 122:f9eeca106725 1559 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
Kojto 122:f9eeca106725 1560 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1561 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
Kojto 122:f9eeca106725 1562 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
Kojto 122:f9eeca106725 1563 @if STM32L486xx
Kojto 122:f9eeca106725 1564 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
Kojto 122:f9eeca106725 1565 @endif
AnnaBridge 145:64910690c574 1566 @if STM32L4A6xx
AnnaBridge 145:64910690c574 1567 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
AnnaBridge 145:64910690c574 1568 @endif
Kojto 122:f9eeca106725 1569 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
Kojto 122:f9eeca106725 1570 * @retval None
Kojto 122:f9eeca106725 1571 */
Kojto 122:f9eeca106725 1572 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
Kojto 122:f9eeca106725 1573 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
Kojto 122:f9eeca106725 1574
Kojto 122:f9eeca106725 1575 /** @brief Macro to get the ADC clock source.
Kojto 122:f9eeca106725 1576 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1577 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
Kojto 122:f9eeca106725 1578 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
Kojto 122:f9eeca106725 1579 @if STM32L486xx
Kojto 122:f9eeca106725 1580 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
Kojto 122:f9eeca106725 1581 @endif
AnnaBridge 145:64910690c574 1582 @if STM32L4A6xx
AnnaBridge 145:64910690c574 1583 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
AnnaBridge 145:64910690c574 1584 @endif
Kojto 122:f9eeca106725 1585 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
Kojto 122:f9eeca106725 1586 */
Kojto 122:f9eeca106725 1587 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
Kojto 122:f9eeca106725 1588
Kojto 122:f9eeca106725 1589 #if defined(SWPMI1)
Kojto 122:f9eeca106725 1590
Kojto 122:f9eeca106725 1591 /** @brief Macro to configure the SWPMI1 clock.
Kojto 122:f9eeca106725 1592 * @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.
Kojto 122:f9eeca106725 1593 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 1594 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock
Kojto 122:f9eeca106725 1595 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
Kojto 122:f9eeca106725 1596 * @retval None
Kojto 122:f9eeca106725 1597 */
Kojto 122:f9eeca106725 1598 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1599 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))
Kojto 122:f9eeca106725 1600
Kojto 122:f9eeca106725 1601 /** @brief Macro to get the SWPMI1 clock source.
Kojto 122:f9eeca106725 1602 * @retval The clock source can be one of the following values:
AnnaBridge 145:64910690c574 1603 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock
Kojto 122:f9eeca106725 1604 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
Kojto 122:f9eeca106725 1605 */
Kojto 122:f9eeca106725 1606 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))
Kojto 122:f9eeca106725 1607
Kojto 122:f9eeca106725 1608 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 1609
Kojto 122:f9eeca106725 1610 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 1611 /** @brief Macro to configure the DFSDM1 clock.
Kojto 122:f9eeca106725 1612 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
Kojto 122:f9eeca106725 1613 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 1614 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock
Kojto 122:f9eeca106725 1615 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
Kojto 122:f9eeca106725 1616 * @retval None
Kojto 122:f9eeca106725 1617 */
Kojto 122:f9eeca106725 1618 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
Kojto 122:f9eeca106725 1619 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
Kojto 122:f9eeca106725 1620
Kojto 122:f9eeca106725 1621 /** @brief Macro to get the DFSDM1 clock source.
Kojto 122:f9eeca106725 1622 * @retval The clock source can be one of the following values:
AnnaBridge 145:64910690c574 1623 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock
Kojto 122:f9eeca106725 1624 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
Kojto 122:f9eeca106725 1625 */
Kojto 122:f9eeca106725 1626 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)))
Kojto 122:f9eeca106725 1627
Kojto 122:f9eeca106725 1628 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 1629
Kojto 122:f9eeca106725 1630 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
Kojto 122:f9eeca106725 1631 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 122:f9eeca106725 1632 * @{
Kojto 122:f9eeca106725 1633 */
Kojto 122:f9eeca106725 1634
Kojto 122:f9eeca106725 1635 /** @brief Enable PLLSAI1RDY interrupt.
Kojto 122:f9eeca106725 1636 * @retval None
Kojto 122:f9eeca106725 1637 */
Kojto 122:f9eeca106725 1638 #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
Kojto 122:f9eeca106725 1639
Kojto 122:f9eeca106725 1640 /** @brief Disable PLLSAI1RDY interrupt.
Kojto 122:f9eeca106725 1641 * @retval None
Kojto 122:f9eeca106725 1642 */
Kojto 122:f9eeca106725 1643 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
Kojto 122:f9eeca106725 1644
Kojto 122:f9eeca106725 1645 /** @brief Clear the PLLSAI1RDY interrupt pending bit.
Kojto 122:f9eeca106725 1646 * @retval None
Kojto 122:f9eeca106725 1647 */
Kojto 122:f9eeca106725 1648 #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
Kojto 122:f9eeca106725 1649
Kojto 122:f9eeca106725 1650 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
Kojto 122:f9eeca106725 1651 * @retval TRUE or FALSE.
Kojto 122:f9eeca106725 1652 */
Kojto 122:f9eeca106725 1653 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
Kojto 122:f9eeca106725 1654
Kojto 122:f9eeca106725 1655 /** @brief Check whether the PLLSAI1RDY flag is set or not.
Kojto 122:f9eeca106725 1656 * @retval TRUE or FALSE.
Kojto 122:f9eeca106725 1657 */
Kojto 122:f9eeca106725 1658 #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
Kojto 122:f9eeca106725 1659
Kojto 122:f9eeca106725 1660 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 1661
Kojto 122:f9eeca106725 1662 /** @brief Enable PLLSAI2RDY interrupt.
Kojto 122:f9eeca106725 1663 * @retval None
Kojto 122:f9eeca106725 1664 */
Kojto 122:f9eeca106725 1665 #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
Kojto 122:f9eeca106725 1666
Kojto 122:f9eeca106725 1667 /** @brief Disable PLLSAI2RDY interrupt.
Kojto 122:f9eeca106725 1668 * @retval None
Kojto 122:f9eeca106725 1669 */
Kojto 122:f9eeca106725 1670 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
Kojto 122:f9eeca106725 1671
Kojto 122:f9eeca106725 1672 /** @brief Clear the PLLSAI2RDY interrupt pending bit.
Kojto 122:f9eeca106725 1673 * @retval None
Kojto 122:f9eeca106725 1674 */
Kojto 122:f9eeca106725 1675 #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
Kojto 122:f9eeca106725 1676
Kojto 122:f9eeca106725 1677 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.
Kojto 122:f9eeca106725 1678 * @retval TRUE or FALSE.
Kojto 122:f9eeca106725 1679 */
Kojto 122:f9eeca106725 1680 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
Kojto 122:f9eeca106725 1681
Kojto 122:f9eeca106725 1682 /** @brief Check whether the PLLSAI2RDY flag is set or not.
Kojto 122:f9eeca106725 1683 * @retval TRUE or FALSE.
Kojto 122:f9eeca106725 1684 */
Kojto 122:f9eeca106725 1685 #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
Kojto 122:f9eeca106725 1686
Kojto 122:f9eeca106725 1687 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 1688
Kojto 122:f9eeca106725 1689
Kojto 122:f9eeca106725 1690 /**
Kojto 122:f9eeca106725 1691 * @brief Enable the RCC LSE CSS Extended Interrupt Line.
Kojto 122:f9eeca106725 1692 * @retval None
Kojto 122:f9eeca106725 1693 */
Kojto 122:f9eeca106725 1694 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1695
Kojto 122:f9eeca106725 1696 /**
Kojto 122:f9eeca106725 1697 * @brief Disable the RCC LSE CSS Extended Interrupt Line.
Kojto 122:f9eeca106725 1698 * @retval None
Kojto 122:f9eeca106725 1699 */
Kojto 122:f9eeca106725 1700 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1701
Kojto 122:f9eeca106725 1702 /**
Kojto 122:f9eeca106725 1703 * @brief Enable the RCC LSE CSS Event Line.
Kojto 122:f9eeca106725 1704 * @retval None.
Kojto 122:f9eeca106725 1705 */
Kojto 122:f9eeca106725 1706 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1707
Kojto 122:f9eeca106725 1708 /**
Kojto 122:f9eeca106725 1709 * @brief Disable the RCC LSE CSS Event Line.
Kojto 122:f9eeca106725 1710 * @retval None.
Kojto 122:f9eeca106725 1711 */
Kojto 122:f9eeca106725 1712 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1713
Kojto 122:f9eeca106725 1714
Kojto 122:f9eeca106725 1715 /**
Kojto 122:f9eeca106725 1716 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
Kojto 122:f9eeca106725 1717 * @retval None.
Kojto 122:f9eeca106725 1718 */
Kojto 122:f9eeca106725 1719 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1720
Kojto 122:f9eeca106725 1721
Kojto 122:f9eeca106725 1722 /**
Kojto 122:f9eeca106725 1723 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
Kojto 122:f9eeca106725 1724 * @retval None.
Kojto 122:f9eeca106725 1725 */
Kojto 122:f9eeca106725 1726 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1727
Kojto 122:f9eeca106725 1728
Kojto 122:f9eeca106725 1729 /**
Kojto 122:f9eeca106725 1730 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
Kojto 122:f9eeca106725 1731 * @retval None.
Kojto 122:f9eeca106725 1732 */
Kojto 122:f9eeca106725 1733 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1734
Kojto 122:f9eeca106725 1735 /**
Kojto 122:f9eeca106725 1736 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
Kojto 122:f9eeca106725 1737 * @retval None.
Kojto 122:f9eeca106725 1738 */
Kojto 122:f9eeca106725 1739 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1740
Kojto 122:f9eeca106725 1741 /**
Kojto 122:f9eeca106725 1742 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
Kojto 122:f9eeca106725 1743 * @retval None.
Kojto 122:f9eeca106725 1744 */
Kojto 122:f9eeca106725 1745 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 1746 do { \
Kojto 122:f9eeca106725 1747 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 1748 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 1749 } while(0)
Kojto 122:f9eeca106725 1750
Kojto 122:f9eeca106725 1751 /**
Kojto 122:f9eeca106725 1752 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
Kojto 122:f9eeca106725 1753 * @retval None.
Kojto 122:f9eeca106725 1754 */
Kojto 122:f9eeca106725 1755 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 1756 do { \
Kojto 122:f9eeca106725 1757 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 1758 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 1759 } while(0)
Kojto 122:f9eeca106725 1760
Kojto 122:f9eeca106725 1761 /**
Kojto 122:f9eeca106725 1762 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
Kojto 122:f9eeca106725 1763 * @retval EXTI RCC LSE CSS Line Status.
Kojto 122:f9eeca106725 1764 */
Kojto 122:f9eeca106725 1765 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1766
Kojto 122:f9eeca106725 1767 /**
Kojto 122:f9eeca106725 1768 * @brief Clear the RCC LSE CSS EXTI flag.
Kojto 122:f9eeca106725 1769 * @retval None.
Kojto 122:f9eeca106725 1770 */
Kojto 122:f9eeca106725 1771 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1772
Kojto 122:f9eeca106725 1773 /**
Kojto 122:f9eeca106725 1774 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
Kojto 122:f9eeca106725 1775 * @retval None.
Kojto 122:f9eeca106725 1776 */
Kojto 122:f9eeca106725 1777 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1778
Kojto 122:f9eeca106725 1779
Kojto 122:f9eeca106725 1780 #if defined(CRS)
Kojto 122:f9eeca106725 1781
Kojto 122:f9eeca106725 1782 /**
Kojto 122:f9eeca106725 1783 * @brief Enable the specified CRS interrupts.
Kojto 122:f9eeca106725 1784 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
Kojto 122:f9eeca106725 1785 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 1786 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
Kojto 122:f9eeca106725 1787 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
Kojto 122:f9eeca106725 1788 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
Kojto 122:f9eeca106725 1789 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
Kojto 122:f9eeca106725 1790 * @retval None
Kojto 122:f9eeca106725 1791 */
Kojto 122:f9eeca106725 1792 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
Kojto 122:f9eeca106725 1793
Kojto 122:f9eeca106725 1794 /**
Kojto 122:f9eeca106725 1795 * @brief Disable the specified CRS interrupts.
Kojto 122:f9eeca106725 1796 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
Kojto 122:f9eeca106725 1797 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 1798 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
Kojto 122:f9eeca106725 1799 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
Kojto 122:f9eeca106725 1800 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
Kojto 122:f9eeca106725 1801 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
Kojto 122:f9eeca106725 1802 * @retval None
Kojto 122:f9eeca106725 1803 */
Kojto 122:f9eeca106725 1804 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
Kojto 122:f9eeca106725 1805
Kojto 122:f9eeca106725 1806 /** @brief Check whether the CRS interrupt has occurred or not.
Kojto 122:f9eeca106725 1807 * @param __INTERRUPT__ specifies the CRS interrupt source to check.
Kojto 122:f9eeca106725 1808 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1809 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
Kojto 122:f9eeca106725 1810 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
Kojto 122:f9eeca106725 1811 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
Kojto 122:f9eeca106725 1812 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
Kojto 122:f9eeca106725 1813 * @retval The new state of __INTERRUPT__ (SET or RESET).
Kojto 122:f9eeca106725 1814 */
Kojto 122:f9eeca106725 1815 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
Kojto 122:f9eeca106725 1816
Kojto 122:f9eeca106725 1817 /** @brief Clear the CRS interrupt pending bits
Kojto 122:f9eeca106725 1818 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
Kojto 122:f9eeca106725 1819 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 1820 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
Kojto 122:f9eeca106725 1821 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
Kojto 122:f9eeca106725 1822 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
Kojto 122:f9eeca106725 1823 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
Kojto 122:f9eeca106725 1824 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
Kojto 122:f9eeca106725 1825 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
Kojto 122:f9eeca106725 1826 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
Kojto 122:f9eeca106725 1827 */
Kojto 122:f9eeca106725 1828 /* CRS IT Error Mask */
Kojto 122:f9eeca106725 1829 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
Kojto 122:f9eeca106725 1830
Kojto 122:f9eeca106725 1831 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
Kojto 122:f9eeca106725 1832 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
Kojto 122:f9eeca106725 1833 { \
Kojto 122:f9eeca106725 1834 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
Kojto 122:f9eeca106725 1835 } \
Kojto 122:f9eeca106725 1836 else \
Kojto 122:f9eeca106725 1837 { \
Kojto 122:f9eeca106725 1838 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
Kojto 122:f9eeca106725 1839 } \
Kojto 122:f9eeca106725 1840 } while(0)
Kojto 122:f9eeca106725 1841
Kojto 122:f9eeca106725 1842 /**
Kojto 122:f9eeca106725 1843 * @brief Check whether the specified CRS flag is set or not.
Kojto 122:f9eeca106725 1844 * @param __FLAG__ specifies the flag to check.
Kojto 122:f9eeca106725 1845 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1846 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
Kojto 122:f9eeca106725 1847 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
Kojto 122:f9eeca106725 1848 * @arg @ref RCC_CRS_FLAG_ERR Error
Kojto 122:f9eeca106725 1849 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
Kojto 122:f9eeca106725 1850 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
Kojto 122:f9eeca106725 1851 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
Kojto 122:f9eeca106725 1852 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
Kojto 122:f9eeca106725 1853 * @retval The new state of _FLAG_ (TRUE or FALSE).
Kojto 122:f9eeca106725 1854 */
Kojto 122:f9eeca106725 1855 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
Kojto 122:f9eeca106725 1856
Kojto 122:f9eeca106725 1857 /**
Kojto 122:f9eeca106725 1858 * @brief Clear the CRS specified FLAG.
Kojto 122:f9eeca106725 1859 * @param __FLAG__ specifies the flag to clear.
Kojto 122:f9eeca106725 1860 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1861 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
Kojto 122:f9eeca106725 1862 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
Kojto 122:f9eeca106725 1863 * @arg @ref RCC_CRS_FLAG_ERR Error
Kojto 122:f9eeca106725 1864 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
Kojto 122:f9eeca106725 1865 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
Kojto 122:f9eeca106725 1866 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
Kojto 122:f9eeca106725 1867 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
Kojto 122:f9eeca106725 1868 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
Kojto 122:f9eeca106725 1869 * @retval None
Kojto 122:f9eeca106725 1870 */
Kojto 122:f9eeca106725 1871
Kojto 122:f9eeca106725 1872 /* CRS Flag Error Mask */
Kojto 122:f9eeca106725 1873 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
Kojto 122:f9eeca106725 1874
Kojto 122:f9eeca106725 1875 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
Kojto 122:f9eeca106725 1876 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
Kojto 122:f9eeca106725 1877 { \
Kojto 122:f9eeca106725 1878 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
Kojto 122:f9eeca106725 1879 } \
Kojto 122:f9eeca106725 1880 else \
Kojto 122:f9eeca106725 1881 { \
Kojto 122:f9eeca106725 1882 WRITE_REG(CRS->ICR, (__FLAG__)); \
Kojto 122:f9eeca106725 1883 } \
Kojto 122:f9eeca106725 1884 } while(0)
Kojto 122:f9eeca106725 1885
Kojto 122:f9eeca106725 1886 #endif /* CRS */
Kojto 122:f9eeca106725 1887
Kojto 122:f9eeca106725 1888 /**
Kojto 122:f9eeca106725 1889 * @}
Kojto 122:f9eeca106725 1890 */
Kojto 122:f9eeca106725 1891
Kojto 122:f9eeca106725 1892 #if defined(CRS)
Kojto 122:f9eeca106725 1893
Kojto 122:f9eeca106725 1894 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
Kojto 122:f9eeca106725 1895 * @{
Kojto 122:f9eeca106725 1896 */
Kojto 122:f9eeca106725 1897 /**
Kojto 122:f9eeca106725 1898 * @brief Enable the oscillator clock for frequency error counter.
Kojto 122:f9eeca106725 1899 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
Kojto 122:f9eeca106725 1900 * @retval None
Kojto 122:f9eeca106725 1901 */
Kojto 122:f9eeca106725 1902 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
Kojto 122:f9eeca106725 1903
Kojto 122:f9eeca106725 1904 /**
Kojto 122:f9eeca106725 1905 * @brief Disable the oscillator clock for frequency error counter.
Kojto 122:f9eeca106725 1906 * @retval None
Kojto 122:f9eeca106725 1907 */
Kojto 122:f9eeca106725 1908 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
Kojto 122:f9eeca106725 1909
Kojto 122:f9eeca106725 1910 /**
Kojto 122:f9eeca106725 1911 * @brief Enable the automatic hardware adjustement of TRIM bits.
Kojto 122:f9eeca106725 1912 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
Kojto 122:f9eeca106725 1913 * @retval None
Kojto 122:f9eeca106725 1914 */
Kojto 122:f9eeca106725 1915 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Kojto 122:f9eeca106725 1916
Kojto 122:f9eeca106725 1917 /**
Kojto 122:f9eeca106725 1918 * @brief Enable or disable the automatic hardware adjustement of TRIM bits.
Kojto 122:f9eeca106725 1919 * @retval None
Kojto 122:f9eeca106725 1920 */
Kojto 122:f9eeca106725 1921 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
Kojto 122:f9eeca106725 1922
Kojto 122:f9eeca106725 1923 /**
Kojto 122:f9eeca106725 1924 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
Kojto 122:f9eeca106725 1925 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
Kojto 122:f9eeca106725 1926 * of the synchronization source after prescaling. It is then decreased by one in order to
Kojto 122:f9eeca106725 1927 * reach the expected synchronization on the zero value. The formula is the following:
Kojto 122:f9eeca106725 1928 * RELOAD = (fTARGET / fSYNC) -1
Kojto 122:f9eeca106725 1929 * @param __FTARGET__ Target frequency (value in Hz)
Kojto 122:f9eeca106725 1930 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
Kojto 122:f9eeca106725 1931 * @retval None
Kojto 122:f9eeca106725 1932 */
Kojto 122:f9eeca106725 1933 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Kojto 122:f9eeca106725 1934
Kojto 122:f9eeca106725 1935 /**
Kojto 122:f9eeca106725 1936 * @}
Kojto 122:f9eeca106725 1937 */
Kojto 122:f9eeca106725 1938
Kojto 122:f9eeca106725 1939 #endif /* CRS */
Kojto 122:f9eeca106725 1940
Kojto 122:f9eeca106725 1941 /**
Kojto 122:f9eeca106725 1942 * @}
Kojto 122:f9eeca106725 1943 */
Kojto 122:f9eeca106725 1944
Kojto 122:f9eeca106725 1945 /* Exported functions --------------------------------------------------------*/
Kojto 122:f9eeca106725 1946 /** @addtogroup RCCEx_Exported_Functions
Kojto 122:f9eeca106725 1947 * @{
Kojto 122:f9eeca106725 1948 */
Kojto 122:f9eeca106725 1949
Kojto 122:f9eeca106725 1950 /** @addtogroup RCCEx_Exported_Functions_Group1
Kojto 122:f9eeca106725 1951 * @{
Kojto 122:f9eeca106725 1952 */
Kojto 122:f9eeca106725 1953
Kojto 122:f9eeca106725 1954 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 122:f9eeca106725 1955 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 122:f9eeca106725 1956 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto 122:f9eeca106725 1957
Kojto 122:f9eeca106725 1958 /**
Kojto 122:f9eeca106725 1959 * @}
Kojto 122:f9eeca106725 1960 */
Kojto 122:f9eeca106725 1961
Kojto 122:f9eeca106725 1962 /** @addtogroup RCCEx_Exported_Functions_Group2
Kojto 122:f9eeca106725 1963 * @{
Kojto 122:f9eeca106725 1964 */
Kojto 122:f9eeca106725 1965
Kojto 122:f9eeca106725 1966 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init);
Kojto 122:f9eeca106725 1967 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
Kojto 122:f9eeca106725 1968
Kojto 122:f9eeca106725 1969 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 1970
Kojto 122:f9eeca106725 1971 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init);
Kojto 122:f9eeca106725 1972 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
Kojto 122:f9eeca106725 1973
Kojto 122:f9eeca106725 1974 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 1975
Kojto 122:f9eeca106725 1976 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
Kojto 122:f9eeca106725 1977 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
Kojto 122:f9eeca106725 1978 void HAL_RCCEx_EnableLSECSS(void);
Kojto 122:f9eeca106725 1979 void HAL_RCCEx_DisableLSECSS(void);
Kojto 122:f9eeca106725 1980 void HAL_RCCEx_EnableLSECSS_IT(void);
Kojto 122:f9eeca106725 1981 void HAL_RCCEx_LSECSS_IRQHandler(void);
Kojto 122:f9eeca106725 1982 void HAL_RCCEx_LSECSS_Callback(void);
Kojto 122:f9eeca106725 1983 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
Kojto 122:f9eeca106725 1984 void HAL_RCCEx_DisableLSCO(void);
Kojto 122:f9eeca106725 1985 void HAL_RCCEx_EnableMSIPLLMode(void);
Kojto 122:f9eeca106725 1986 void HAL_RCCEx_DisableMSIPLLMode(void);
Kojto 122:f9eeca106725 1987
Kojto 122:f9eeca106725 1988 /**
Kojto 122:f9eeca106725 1989 * @}
Kojto 122:f9eeca106725 1990 */
Kojto 122:f9eeca106725 1991
Kojto 122:f9eeca106725 1992 #if defined(CRS)
Kojto 122:f9eeca106725 1993
Kojto 122:f9eeca106725 1994 /** @addtogroup RCCEx_Exported_Functions_Group3
Kojto 122:f9eeca106725 1995 * @{
Kojto 122:f9eeca106725 1996 */
Kojto 122:f9eeca106725 1997
Kojto 122:f9eeca106725 1998 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
Kojto 122:f9eeca106725 1999 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
Kojto 122:f9eeca106725 2000 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
Kojto 122:f9eeca106725 2001 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
Kojto 122:f9eeca106725 2002 void HAL_RCCEx_CRS_IRQHandler(void);
Kojto 122:f9eeca106725 2003 void HAL_RCCEx_CRS_SyncOkCallback(void);
Kojto 122:f9eeca106725 2004 void HAL_RCCEx_CRS_SyncWarnCallback(void);
Kojto 122:f9eeca106725 2005 void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
Kojto 122:f9eeca106725 2006 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
Kojto 122:f9eeca106725 2007
Kojto 122:f9eeca106725 2008 /**
Kojto 122:f9eeca106725 2009 * @}
Kojto 122:f9eeca106725 2010 */
Kojto 122:f9eeca106725 2011
Kojto 122:f9eeca106725 2012 #endif /* CRS */
Kojto 122:f9eeca106725 2013
Kojto 122:f9eeca106725 2014 /**
Kojto 122:f9eeca106725 2015 * @}
Kojto 122:f9eeca106725 2016 */
Kojto 122:f9eeca106725 2017
Kojto 122:f9eeca106725 2018 /* Private macros ------------------------------------------------------------*/
Kojto 122:f9eeca106725 2019 /** @addtogroup RCCEx_Private_Macros
Kojto 122:f9eeca106725 2020 * @{
Kojto 122:f9eeca106725 2021 */
Kojto 122:f9eeca106725 2022
Kojto 122:f9eeca106725 2023 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
Kojto 122:f9eeca106725 2024 ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
Kojto 122:f9eeca106725 2025
Kojto 122:f9eeca106725 2026 #if defined(STM32L431xx)
Kojto 122:f9eeca106725 2027
Kojto 122:f9eeca106725 2028 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 122:f9eeca106725 2029 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 122:f9eeca106725 2030 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 122:f9eeca106725 2031 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 122:f9eeca106725 2032 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
Kojto 122:f9eeca106725 2033 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 122:f9eeca106725 2034 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 122:f9eeca106725 2035 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 122:f9eeca106725 2036 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 122:f9eeca106725 2037 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
Kojto 122:f9eeca106725 2038 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 122:f9eeca106725 2039 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 122:f9eeca106725 2040 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
Kojto 122:f9eeca106725 2041 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 122:f9eeca106725 2042 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
Kojto 122:f9eeca106725 2043 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
Kojto 122:f9eeca106725 2044
Kojto 122:f9eeca106725 2045 #elif defined(STM32L432xx) || defined(STM32L442xx)
Kojto 122:f9eeca106725 2046
Kojto 122:f9eeca106725 2047 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 122:f9eeca106725 2048 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 122:f9eeca106725 2049 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 122:f9eeca106725 2050 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
Kojto 122:f9eeca106725 2051 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 122:f9eeca106725 2052 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 122:f9eeca106725 2053 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 122:f9eeca106725 2054 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
Kojto 122:f9eeca106725 2055 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 122:f9eeca106725 2056 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
Kojto 122:f9eeca106725 2057 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 122:f9eeca106725 2058 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
Kojto 122:f9eeca106725 2059 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 122:f9eeca106725 2060 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG))
Kojto 122:f9eeca106725 2061
Kojto 122:f9eeca106725 2062 #elif defined(STM32L433xx) || defined(STM32L443xx)
Kojto 122:f9eeca106725 2063
Kojto 122:f9eeca106725 2064 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 122:f9eeca106725 2065 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 122:f9eeca106725 2066 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 122:f9eeca106725 2067 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 122:f9eeca106725 2068 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
Kojto 122:f9eeca106725 2069 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 122:f9eeca106725 2070 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 122:f9eeca106725 2071 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 122:f9eeca106725 2072 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 122:f9eeca106725 2073 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
Kojto 122:f9eeca106725 2074 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 122:f9eeca106725 2075 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
Kojto 122:f9eeca106725 2076 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 122:f9eeca106725 2077 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
Kojto 122:f9eeca106725 2078 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 122:f9eeca106725 2079 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
Kojto 122:f9eeca106725 2080 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
Kojto 122:f9eeca106725 2081
AnnaBridge 145:64910690c574 2082 #elif defined(STM32L451xx)
AnnaBridge 145:64910690c574 2083
AnnaBridge 145:64910690c574 2084 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge 145:64910690c574 2085 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 145:64910690c574 2086 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 145:64910690c574 2087 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 145:64910690c574 2088 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
AnnaBridge 145:64910690c574 2089 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
AnnaBridge 145:64910690c574 2090 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 145:64910690c574 2091 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 145:64910690c574 2092 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 145:64910690c574 2093 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
AnnaBridge 145:64910690c574 2094 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 145:64910690c574 2095 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
AnnaBridge 145:64910690c574 2096 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 145:64910690c574 2097 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
AnnaBridge 145:64910690c574 2098 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
AnnaBridge 145:64910690c574 2099 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
AnnaBridge 145:64910690c574 2100 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
AnnaBridge 145:64910690c574 2101 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge 145:64910690c574 2102
AnnaBridge 145:64910690c574 2103 #elif defined(STM32L452xx) || defined(STM32L462xx)
AnnaBridge 145:64910690c574 2104
AnnaBridge 145:64910690c574 2105 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge 145:64910690c574 2106 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 145:64910690c574 2107 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 145:64910690c574 2108 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 145:64910690c574 2109 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
AnnaBridge 145:64910690c574 2110 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
AnnaBridge 145:64910690c574 2111 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 145:64910690c574 2112 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 145:64910690c574 2113 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 145:64910690c574 2114 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
AnnaBridge 145:64910690c574 2115 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 145:64910690c574 2116 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
AnnaBridge 145:64910690c574 2117 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 145:64910690c574 2118 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
AnnaBridge 145:64910690c574 2119 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
AnnaBridge 145:64910690c574 2120 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
AnnaBridge 145:64910690c574 2121 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
AnnaBridge 145:64910690c574 2122 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
AnnaBridge 145:64910690c574 2123 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge 145:64910690c574 2124
Kojto 122:f9eeca106725 2125 #elif defined(STM32L471xx)
Kojto 122:f9eeca106725 2126
Kojto 122:f9eeca106725 2127 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 122:f9eeca106725 2128 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 122:f9eeca106725 2129 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 122:f9eeca106725 2130 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 122:f9eeca106725 2131 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
Kojto 122:f9eeca106725 2132 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
Kojto 122:f9eeca106725 2133 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
Kojto 122:f9eeca106725 2134 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 122:f9eeca106725 2135 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 122:f9eeca106725 2136 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 122:f9eeca106725 2137 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 122:f9eeca106725 2138 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
Kojto 122:f9eeca106725 2139 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 122:f9eeca106725 2140 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
Kojto 122:f9eeca106725 2141 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 122:f9eeca106725 2142 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
Kojto 122:f9eeca106725 2143 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
Kojto 122:f9eeca106725 2144 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 122:f9eeca106725 2145 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
Kojto 122:f9eeca106725 2146 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
Kojto 122:f9eeca106725 2147
AnnaBridge 145:64910690c574 2148 #elif defined(STM32L496xx) || defined(STM32L4A6xx)
AnnaBridge 145:64910690c574 2149
AnnaBridge 145:64910690c574 2150 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge 145:64910690c574 2151 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 145:64910690c574 2152 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 145:64910690c574 2153 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 145:64910690c574 2154 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
AnnaBridge 145:64910690c574 2155 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
AnnaBridge 145:64910690c574 2156 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
AnnaBridge 145:64910690c574 2157 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 145:64910690c574 2158 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 145:64910690c574 2159 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 145:64910690c574 2160 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
AnnaBridge 145:64910690c574 2161 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 145:64910690c574 2162 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
AnnaBridge 145:64910690c574 2163 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 145:64910690c574 2164 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
AnnaBridge 145:64910690c574 2165 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
AnnaBridge 145:64910690c574 2166 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
AnnaBridge 145:64910690c574 2167 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
AnnaBridge 145:64910690c574 2168 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
AnnaBridge 145:64910690c574 2169 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
AnnaBridge 145:64910690c574 2170 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
AnnaBridge 145:64910690c574 2171 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge 145:64910690c574 2172
Kojto 122:f9eeca106725 2173 #else
Kojto 122:f9eeca106725 2174
Kojto 122:f9eeca106725 2175 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 122:f9eeca106725 2176 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 122:f9eeca106725 2177 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 122:f9eeca106725 2178 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 122:f9eeca106725 2179 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
Kojto 122:f9eeca106725 2180 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
Kojto 122:f9eeca106725 2181 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
Kojto 122:f9eeca106725 2182 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 122:f9eeca106725 2183 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 122:f9eeca106725 2184 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 122:f9eeca106725 2185 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 122:f9eeca106725 2186 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
Kojto 122:f9eeca106725 2187 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 122:f9eeca106725 2188 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
Kojto 122:f9eeca106725 2189 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
Kojto 122:f9eeca106725 2190 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 122:f9eeca106725 2191 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
Kojto 122:f9eeca106725 2192 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
Kojto 122:f9eeca106725 2193 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 122:f9eeca106725 2194 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
Kojto 122:f9eeca106725 2195 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
Kojto 122:f9eeca106725 2196
Kojto 122:f9eeca106725 2197 #endif /* STM32L431xx */
Kojto 122:f9eeca106725 2198
Kojto 122:f9eeca106725 2199 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2200 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
Kojto 122:f9eeca106725 2201 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 2202 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 2203 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2204
Kojto 122:f9eeca106725 2205 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2206 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2207 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 2208 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 2209 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2210
Kojto 122:f9eeca106725 2211 #if defined(USART3)
Kojto 122:f9eeca106725 2212
Kojto 122:f9eeca106725 2213 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2214 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2215 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 2216 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 2217 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2218
Kojto 122:f9eeca106725 2219 #endif /* USART3 */
Kojto 122:f9eeca106725 2220
Kojto 122:f9eeca106725 2221 #if defined(UART4)
Kojto 122:f9eeca106725 2222
Kojto 122:f9eeca106725 2223 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2224 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2225 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 2226 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 2227 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2228
Kojto 122:f9eeca106725 2229 #endif /* UART4 */
Kojto 122:f9eeca106725 2230
Kojto 122:f9eeca106725 2231 #if defined(UART5)
Kojto 122:f9eeca106725 2232
Kojto 122:f9eeca106725 2233 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2234 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2235 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 2236 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 2237 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2238
Kojto 122:f9eeca106725 2239 #endif /* UART5 */
Kojto 122:f9eeca106725 2240
Kojto 122:f9eeca106725 2241 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2242 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2243 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 2244 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 2245 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2246
Kojto 122:f9eeca106725 2247 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2248 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2249 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
Kojto 122:f9eeca106725 2250 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2251
Kojto 122:f9eeca106725 2252 #if defined(I2C2)
Kojto 122:f9eeca106725 2253
Kojto 122:f9eeca106725 2254 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2255 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2256 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
Kojto 122:f9eeca106725 2257 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2258
Kojto 122:f9eeca106725 2259 #endif /* I2C2 */
Kojto 122:f9eeca106725 2260
Kojto 122:f9eeca106725 2261 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2262 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2263 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
Kojto 122:f9eeca106725 2264 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
AnnaBridge 145:64910690c574 2265
AnnaBridge 145:64910690c574 2266 #if defined(I2C4)
AnnaBridge 145:64910690c574 2267
AnnaBridge 145:64910690c574 2268 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
AnnaBridge 145:64910690c574 2269 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
AnnaBridge 145:64910690c574 2270 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
AnnaBridge 145:64910690c574 2271 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
AnnaBridge 145:64910690c574 2272
AnnaBridge 145:64910690c574 2273 #endif /* I2C4 */
Kojto 122:f9eeca106725 2274
Kojto 122:f9eeca106725 2275 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 2276
Kojto 122:f9eeca106725 2277 #define IS_RCC_SAI1CLK(__SOURCE__) \
Kojto 122:f9eeca106725 2278 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2279 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
Kojto 122:f9eeca106725 2280 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2281 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
Kojto 122:f9eeca106725 2282
Kojto 122:f9eeca106725 2283 #else
Kojto 122:f9eeca106725 2284
Kojto 122:f9eeca106725 2285 #define IS_RCC_SAI1CLK(__SOURCE__) \
Kojto 122:f9eeca106725 2286 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2287 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2288 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
Kojto 122:f9eeca106725 2289
Kojto 122:f9eeca106725 2290 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 2291
Kojto 122:f9eeca106725 2292 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 2293
Kojto 122:f9eeca106725 2294 #define IS_RCC_SAI2CLK(__SOURCE__) \
Kojto 122:f9eeca106725 2295 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2296 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
Kojto 122:f9eeca106725 2297 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2298 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
Kojto 122:f9eeca106725 2299
Kojto 122:f9eeca106725 2300 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 2301
Kojto 122:f9eeca106725 2302 #define IS_RCC_LPTIM1CLK(__SOURCE__) \
AnnaBridge 145:64910690c574 2303 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2304 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
Kojto 122:f9eeca106725 2305 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
Kojto 122:f9eeca106725 2306 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
Kojto 122:f9eeca106725 2307
Kojto 122:f9eeca106725 2308 #define IS_RCC_LPTIM2CLK(__SOURCE__) \
AnnaBridge 145:64910690c574 2309 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2310 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
Kojto 122:f9eeca106725 2311 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
Kojto 122:f9eeca106725 2312 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
Kojto 122:f9eeca106725 2313
Kojto 122:f9eeca106725 2314 #if defined(SDMMC1)
Kojto 122:f9eeca106725 2315 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 2316
Kojto 122:f9eeca106725 2317 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2318 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \
Kojto 122:f9eeca106725 2319 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2320 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2321 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
Kojto 122:f9eeca106725 2322
Kojto 122:f9eeca106725 2323 #else
Kojto 122:f9eeca106725 2324
Kojto 122:f9eeca106725 2325 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2326 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \
Kojto 122:f9eeca106725 2327 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2328 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2329 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
Kojto 122:f9eeca106725 2330
Kojto 122:f9eeca106725 2331 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 2332 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 2333
Kojto 122:f9eeca106725 2334 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 2335
Kojto 122:f9eeca106725 2336 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2337 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
Kojto 122:f9eeca106725 2338 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2339 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2340 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
Kojto 122:f9eeca106725 2341
Kojto 122:f9eeca106725 2342 #else
Kojto 122:f9eeca106725 2343
Kojto 122:f9eeca106725 2344 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2345 (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \
Kojto 122:f9eeca106725 2346 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2347 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2348 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
Kojto 122:f9eeca106725 2349
Kojto 122:f9eeca106725 2350 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 2351
Kojto 122:f9eeca106725 2352 #if defined(USB_OTG_FS) || defined(USB)
Kojto 122:f9eeca106725 2353 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 2354
Kojto 122:f9eeca106725 2355 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2356 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
Kojto 122:f9eeca106725 2357 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2358 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2359 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
Kojto 122:f9eeca106725 2360
Kojto 122:f9eeca106725 2361 #else
Kojto 122:f9eeca106725 2362
Kojto 122:f9eeca106725 2363 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2364 (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \
Kojto 122:f9eeca106725 2365 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2366 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 2367 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
Kojto 122:f9eeca106725 2368
Kojto 122:f9eeca106725 2369 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 2370 #endif /* USB_OTG_FS || USB */
Kojto 122:f9eeca106725 2371
AnnaBridge 145:64910690c574 2372 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
Kojto 122:f9eeca106725 2373
Kojto 122:f9eeca106725 2374 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2375 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
Kojto 122:f9eeca106725 2376 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2377 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \
Kojto 122:f9eeca106725 2378 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
Kojto 122:f9eeca106725 2379
Kojto 122:f9eeca106725 2380 #else
Kojto 122:f9eeca106725 2381
Kojto 122:f9eeca106725 2382 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
Kojto 122:f9eeca106725 2383 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
Kojto 122:f9eeca106725 2384 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
Kojto 122:f9eeca106725 2385 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
Kojto 122:f9eeca106725 2386
AnnaBridge 145:64910690c574 2387 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
Kojto 122:f9eeca106725 2388
Kojto 122:f9eeca106725 2389 #if defined(SWPMI1)
Kojto 122:f9eeca106725 2390
Kojto 122:f9eeca106725 2391 #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \
AnnaBridge 145:64910690c574 2392 (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 2393 ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
Kojto 122:f9eeca106725 2394
Kojto 122:f9eeca106725 2395 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 2396
Kojto 122:f9eeca106725 2397 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 2398
Kojto 122:f9eeca106725 2399 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \
AnnaBridge 145:64910690c574 2400 (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
Kojto 122:f9eeca106725 2401 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
Kojto 122:f9eeca106725 2402
Kojto 122:f9eeca106725 2403 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 2404
Kojto 122:f9eeca106725 2405 #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
Kojto 122:f9eeca106725 2406
Kojto 122:f9eeca106725 2407 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
Kojto 122:f9eeca106725 2408
Kojto 122:f9eeca106725 2409 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
Kojto 122:f9eeca106725 2410
Kojto 122:f9eeca106725 2411 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 2412 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
Kojto 122:f9eeca106725 2413 #else
Kojto 122:f9eeca106725 2414 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
Kojto 122:f9eeca106725 2415 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 2416
Kojto 122:f9eeca106725 2417 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
Kojto 122:f9eeca106725 2418 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
Kojto 122:f9eeca106725 2419
Kojto 122:f9eeca106725 2420 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
Kojto 122:f9eeca106725 2421 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
Kojto 122:f9eeca106725 2422
Kojto 122:f9eeca106725 2423 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 2424
Kojto 122:f9eeca106725 2425 #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
Kojto 122:f9eeca106725 2426
Kojto 122:f9eeca106725 2427 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
Kojto 122:f9eeca106725 2428
Kojto 122:f9eeca106725 2429 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
Kojto 122:f9eeca106725 2430
Kojto 122:f9eeca106725 2431 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 2432 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
Kojto 122:f9eeca106725 2433 #else
Kojto 122:f9eeca106725 2434 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
Kojto 122:f9eeca106725 2435 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 2436
Kojto 122:f9eeca106725 2437 #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
Kojto 122:f9eeca106725 2438 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
Kojto 122:f9eeca106725 2439
Kojto 122:f9eeca106725 2440 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 2441
Kojto 122:f9eeca106725 2442 #if defined(CRS)
Kojto 122:f9eeca106725 2443
Kojto 122:f9eeca106725 2444 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
Kojto 122:f9eeca106725 2445 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
Kojto 122:f9eeca106725 2446 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
Kojto 122:f9eeca106725 2447
Kojto 122:f9eeca106725 2448 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
Kojto 122:f9eeca106725 2449 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
Kojto 122:f9eeca106725 2450 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
Kojto 122:f9eeca106725 2451 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
Kojto 122:f9eeca106725 2452
Kojto 122:f9eeca106725 2453 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
Kojto 122:f9eeca106725 2454 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
Kojto 122:f9eeca106725 2455
Kojto 122:f9eeca106725 2456 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
Kojto 122:f9eeca106725 2457
Kojto 122:f9eeca106725 2458 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
Kojto 122:f9eeca106725 2459
Kojto 122:f9eeca106725 2460 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
Kojto 122:f9eeca106725 2461
Kojto 122:f9eeca106725 2462 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
Kojto 122:f9eeca106725 2463 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
Kojto 122:f9eeca106725 2464
Kojto 122:f9eeca106725 2465 #endif /* CRS */
Kojto 122:f9eeca106725 2466
Kojto 122:f9eeca106725 2467 /**
Kojto 122:f9eeca106725 2468 * @}
Kojto 122:f9eeca106725 2469 */
Kojto 122:f9eeca106725 2470
Kojto 122:f9eeca106725 2471 /**
Kojto 122:f9eeca106725 2472 * @}
Kojto 122:f9eeca106725 2473 */
Kojto 122:f9eeca106725 2474
Kojto 122:f9eeca106725 2475 /**
Kojto 122:f9eeca106725 2476 * @}
Kojto 122:f9eeca106725 2477 */
Kojto 122:f9eeca106725 2478
Kojto 122:f9eeca106725 2479 #ifdef __cplusplus
Kojto 122:f9eeca106725 2480 }
Kojto 122:f9eeca106725 2481 #endif
Kojto 122:f9eeca106725 2482
Kojto 122:f9eeca106725 2483 #endif /* __STM32L4xx_HAL_RCC_EX_H */
Kojto 122:f9eeca106725 2484
Kojto 122:f9eeca106725 2485 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/