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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
128:9bcdf88f62b0
Child:
145:64910690c574
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**
Kojto 122:f9eeca106725 2 ******************************************************************************
Kojto 122:f9eeca106725 3 * @file stm32l4xx_hal_rcc.h
Kojto 122:f9eeca106725 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.1
Kojto 122:f9eeca106725 6 * @date 31-May-2016
Kojto 122:f9eeca106725 7 * @brief Header file of RCC HAL module.
Kojto 122:f9eeca106725 8 ******************************************************************************
Kojto 122:f9eeca106725 9 * @attention
Kojto 122:f9eeca106725 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 122:f9eeca106725 12 *
Kojto 122:f9eeca106725 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 14 * are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 122:f9eeca106725 16 * this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 122:f9eeca106725 18 * this list of conditions and the following disclaimer in the documentation
Kojto 122:f9eeca106725 19 * and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 122:f9eeca106725 21 * may be used to endorse or promote products derived from this software
Kojto 122:f9eeca106725 22 * without specific prior written permission.
Kojto 122:f9eeca106725 23 *
Kojto 122:f9eeca106725 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 122:f9eeca106725 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 122:f9eeca106725 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 122:f9eeca106725 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 122:f9eeca106725 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 122:f9eeca106725 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 122:f9eeca106725 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 34 *
Kojto 122:f9eeca106725 35 ******************************************************************************
Kojto 122:f9eeca106725 36 */
Kojto 122:f9eeca106725 37
Kojto 122:f9eeca106725 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 122:f9eeca106725 39 #ifndef __STM32L4xx_HAL_RCC_H
Kojto 122:f9eeca106725 40 #define __STM32L4xx_HAL_RCC_H
Kojto 122:f9eeca106725 41
Kojto 122:f9eeca106725 42 #ifdef __cplusplus
Kojto 122:f9eeca106725 43 extern "C" {
Kojto 122:f9eeca106725 44 #endif
Kojto 122:f9eeca106725 45
Kojto 122:f9eeca106725 46 /* Includes ------------------------------------------------------------------*/
Kojto 122:f9eeca106725 47 #include "stm32l4xx_hal_def.h"
Kojto 122:f9eeca106725 48
Kojto 122:f9eeca106725 49 /** @addtogroup STM32L4xx_HAL_Driver
Kojto 122:f9eeca106725 50 * @{
Kojto 122:f9eeca106725 51 */
Kojto 122:f9eeca106725 52
Kojto 122:f9eeca106725 53 /** @addtogroup RCC
Kojto 122:f9eeca106725 54 * @{
Kojto 122:f9eeca106725 55 */
Kojto 122:f9eeca106725 56
Kojto 122:f9eeca106725 57 /* Exported types ------------------------------------------------------------*/
Kojto 122:f9eeca106725 58 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 122:f9eeca106725 59 * @{
Kojto 122:f9eeca106725 60 */
Kojto 122:f9eeca106725 61
Kojto 122:f9eeca106725 62 /**
Kojto 122:f9eeca106725 63 * @brief RCC PLL configuration structure definition
Kojto 122:f9eeca106725 64 */
Kojto 122:f9eeca106725 65 typedef struct
Kojto 122:f9eeca106725 66 {
Kojto 122:f9eeca106725 67 uint32_t PLLState; /*!< The new state of the PLL.
Kojto 122:f9eeca106725 68 This parameter can be a value of @ref RCC_PLL_Config */
Kojto 122:f9eeca106725 69
Kojto 122:f9eeca106725 70 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto 122:f9eeca106725 71 This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto 122:f9eeca106725 72
Kojto 122:f9eeca106725 73 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto 122:f9eeca106725 74 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
Kojto 122:f9eeca106725 75
Kojto 122:f9eeca106725 76 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto 122:f9eeca106725 77 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
Kojto 122:f9eeca106725 78
Kojto 122:f9eeca106725 79 uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.
Kojto 122:f9eeca106725 80 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto 122:f9eeca106725 81
Kojto 122:f9eeca106725 82 uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
Kojto 122:f9eeca106725 83 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
Kojto 122:f9eeca106725 84
Kojto 122:f9eeca106725 85 uint32_t PLLR; /*!< PLLR: Division for the main system clock.
Kojto 122:f9eeca106725 86 User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
Kojto 122:f9eeca106725 87 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
Kojto 122:f9eeca106725 88
Kojto 122:f9eeca106725 89 }RCC_PLLInitTypeDef;
Kojto 122:f9eeca106725 90
Kojto 122:f9eeca106725 91 /**
Kojto 122:f9eeca106725 92 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
Kojto 122:f9eeca106725 93 */
Kojto 122:f9eeca106725 94 typedef struct
Kojto 122:f9eeca106725 95 {
Kojto 122:f9eeca106725 96 uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto 122:f9eeca106725 97 This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto 122:f9eeca106725 98
Kojto 122:f9eeca106725 99 uint32_t HSEState; /*!< The new state of the HSE.
Kojto 122:f9eeca106725 100 This parameter can be a value of @ref RCC_HSE_Config */
Kojto 122:f9eeca106725 101
Kojto 122:f9eeca106725 102 uint32_t LSEState; /*!< The new state of the LSE.
Kojto 122:f9eeca106725 103 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 122:f9eeca106725 104
Kojto 122:f9eeca106725 105 uint32_t HSIState; /*!< The new state of the HSI.
Kojto 122:f9eeca106725 106 This parameter can be a value of @ref RCC_HSI_Config */
Kojto 122:f9eeca106725 107
Kojto 122:f9eeca106725 108 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 122:f9eeca106725 109 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L47x/STM32L48x devices.
Kojto 122:f9eeca106725 110 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on STM32L43x/STM32L44x/STM32L49x/STM32L4Ax/ devices */
Kojto 122:f9eeca106725 111
Kojto 122:f9eeca106725 112 uint32_t LSIState; /*!< The new state of the LSI.
Kojto 122:f9eeca106725 113 This parameter can be a value of @ref RCC_LSI_Config */
Kojto 122:f9eeca106725 114
Kojto 122:f9eeca106725 115 uint32_t MSIState; /*!< The new state of the MSI.
Kojto 122:f9eeca106725 116 This parameter can be a value of @ref RCC_MSI_Config */
Kojto 122:f9eeca106725 117
Kojto 122:f9eeca106725 118 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
Kojto 122:f9eeca106725 119 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
Kojto 122:f9eeca106725 120
Kojto 122:f9eeca106725 121 uint32_t MSIClockRange; /*!< The MSI frequency range.
Kojto 122:f9eeca106725 122 This parameter can be a value of @ref RCC_MSI_Clock_Range */
Kojto 122:f9eeca106725 123
Kojto 122:f9eeca106725 124 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices).
Kojto 122:f9eeca106725 125 This parameter can be a value of @ref RCC_HSI48_Config */
Kojto 122:f9eeca106725 126
Kojto 122:f9eeca106725 127 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
Kojto 122:f9eeca106725 128
Kojto 122:f9eeca106725 129 }RCC_OscInitTypeDef;
Kojto 122:f9eeca106725 130
Kojto 122:f9eeca106725 131 /**
Kojto 122:f9eeca106725 132 * @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto 122:f9eeca106725 133 */
Kojto 122:f9eeca106725 134 typedef struct
Kojto 122:f9eeca106725 135 {
Kojto 122:f9eeca106725 136 uint32_t ClockType; /*!< The clock to be configured.
Kojto 122:f9eeca106725 137 This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto 122:f9eeca106725 138
Kojto 122:f9eeca106725 139 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
Kojto 122:f9eeca106725 140 This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto 122:f9eeca106725 141
Kojto 122:f9eeca106725 142 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto 122:f9eeca106725 143 This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto 122:f9eeca106725 144
Kojto 122:f9eeca106725 145 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto 122:f9eeca106725 146 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 122:f9eeca106725 147
Kojto 122:f9eeca106725 148 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto 122:f9eeca106725 149 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 122:f9eeca106725 150
Kojto 122:f9eeca106725 151 }RCC_ClkInitTypeDef;
Kojto 122:f9eeca106725 152
Kojto 122:f9eeca106725 153 /**
Kojto 122:f9eeca106725 154 * @}
Kojto 122:f9eeca106725 155 */
Kojto 122:f9eeca106725 156
Kojto 122:f9eeca106725 157 /* Exported constants --------------------------------------------------------*/
Kojto 122:f9eeca106725 158 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 122:f9eeca106725 159 * @{
Kojto 122:f9eeca106725 160 */
Kojto 122:f9eeca106725 161
Kojto 122:f9eeca106725 162 /** @defgroup RCC_Timeout_Value Timeout Values
Kojto 122:f9eeca106725 163 * @{
Kojto 122:f9eeca106725 164 */
Kojto 122:f9eeca106725 165 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
Kojto 122:f9eeca106725 166 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto 122:f9eeca106725 167 /**
Kojto 122:f9eeca106725 168 * @}
Kojto 122:f9eeca106725 169 */
Kojto 122:f9eeca106725 170
Kojto 122:f9eeca106725 171 /** @defgroup RCC_Oscillator_Type Oscillator Type
Kojto 122:f9eeca106725 172 * @{
Kojto 122:f9eeca106725 173 */
Kojto 122:f9eeca106725 174 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /*!< Oscillator configuration unchanged */
Kojto 122:f9eeca106725 175 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /*!< HSE to configure */
Kojto 122:f9eeca106725 176 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /*!< HSI to configure */
Kojto 122:f9eeca106725 177 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /*!< LSE to configure */
Kojto 122:f9eeca106725 178 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /*!< LSI to configure */
Kojto 122:f9eeca106725 179 #define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /*!< MSI to configure */
Kojto 122:f9eeca106725 180 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 181 #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U) /*!< HSI48 to configure */
Kojto 122:f9eeca106725 182 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 183 /**
Kojto 122:f9eeca106725 184 * @}
Kojto 122:f9eeca106725 185 */
Kojto 122:f9eeca106725 186
Kojto 122:f9eeca106725 187 /** @defgroup RCC_HSE_Config HSE Config
Kojto 122:f9eeca106725 188 * @{
Kojto 122:f9eeca106725 189 */
Kojto 122:f9eeca106725 190 #define RCC_HSE_OFF ((uint32_t)0x00000000U) /*!< HSE clock deactivation */
Kojto 122:f9eeca106725 191 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
Kojto 122:f9eeca106725 192 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
Kojto 122:f9eeca106725 193 /**
Kojto 122:f9eeca106725 194 * @}
Kojto 122:f9eeca106725 195 */
Kojto 122:f9eeca106725 196
Kojto 122:f9eeca106725 197 /** @defgroup RCC_LSE_Config LSE Config
Kojto 122:f9eeca106725 198 * @{
Kojto 122:f9eeca106725 199 */
Kojto 122:f9eeca106725 200 #define RCC_LSE_OFF ((uint32_t)0x00000000U) /*!< LSE clock deactivation */
Kojto 122:f9eeca106725 201 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
Kojto 122:f9eeca106725 202 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
Kojto 122:f9eeca106725 203 /**
Kojto 122:f9eeca106725 204 * @}
Kojto 122:f9eeca106725 205 */
Kojto 122:f9eeca106725 206
Kojto 122:f9eeca106725 207 /** @defgroup RCC_HSI_Config HSI Config
Kojto 122:f9eeca106725 208 * @{
Kojto 122:f9eeca106725 209 */
Kojto 122:f9eeca106725 210 #define RCC_HSI_OFF ((uint32_t)0x00000000U) /*!< HSI clock deactivation */
Kojto 122:f9eeca106725 211 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
Kojto 122:f9eeca106725 212
Kojto 122:f9eeca106725 213 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)16) /*!< Default HSI calibration trimming value */
Kojto 122:f9eeca106725 214 /**
Kojto 122:f9eeca106725 215 * @}
Kojto 122:f9eeca106725 216 */
Kojto 122:f9eeca106725 217
Kojto 122:f9eeca106725 218 /** @defgroup RCC_LSI_Config LSI Config
Kojto 122:f9eeca106725 219 * @{
Kojto 122:f9eeca106725 220 */
Kojto 122:f9eeca106725 221 #define RCC_LSI_OFF ((uint32_t)0x00000000U) /*!< LSI clock deactivation */
Kojto 122:f9eeca106725 222 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
Kojto 122:f9eeca106725 223 /**
Kojto 122:f9eeca106725 224 * @}
Kojto 122:f9eeca106725 225 */
Kojto 122:f9eeca106725 226
Kojto 122:f9eeca106725 227 /** @defgroup RCC_MSI_Config MSI Config
Kojto 122:f9eeca106725 228 * @{
Kojto 122:f9eeca106725 229 */
Kojto 122:f9eeca106725 230 #define RCC_MSI_OFF ((uint32_t)0x00000000U) /*!< MSI clock deactivation */
Kojto 122:f9eeca106725 231 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */
Kojto 122:f9eeca106725 232
Kojto 122:f9eeca106725 233 #define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /*!< Default MSI calibration trimming value */
Kojto 122:f9eeca106725 234 /**
Kojto 122:f9eeca106725 235 * @}
Kojto 122:f9eeca106725 236 */
Kojto 122:f9eeca106725 237
Kojto 122:f9eeca106725 238 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 239 /** @defgroup RCC_HSI48_Config HSI48 Config
Kojto 122:f9eeca106725 240 * @{
Kojto 122:f9eeca106725 241 */
Kojto 122:f9eeca106725 242 #define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */
Kojto 122:f9eeca106725 243 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */
Kojto 122:f9eeca106725 244 /**
Kojto 122:f9eeca106725 245 * @}
Kojto 122:f9eeca106725 246 */
Kojto 122:f9eeca106725 247 #else
Kojto 122:f9eeca106725 248 /** @defgroup RCC_HSI48_Config HSI48 Config
Kojto 122:f9eeca106725 249 * @{
Kojto 122:f9eeca106725 250 */
Kojto 122:f9eeca106725 251 #define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */
Kojto 122:f9eeca106725 252 /**
Kojto 122:f9eeca106725 253 * @}
Kojto 122:f9eeca106725 254 */
Kojto 122:f9eeca106725 255 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 256
Kojto 122:f9eeca106725 257 /** @defgroup RCC_PLL_Config PLL Config
Kojto 122:f9eeca106725 258 * @{
Kojto 122:f9eeca106725 259 */
Kojto 122:f9eeca106725 260 #define RCC_PLL_NONE ((uint32_t)0x00000000U) /*!< PLL configuration unchanged */
Kojto 122:f9eeca106725 261 #define RCC_PLL_OFF ((uint32_t)0x00000001U) /*!< PLL deactivation */
Kojto 122:f9eeca106725 262 #define RCC_PLL_ON ((uint32_t)0x00000002U) /*!< PLL activation */
Kojto 122:f9eeca106725 263 /**
Kojto 122:f9eeca106725 264 * @}
Kojto 122:f9eeca106725 265 */
Kojto 122:f9eeca106725 266
Kojto 122:f9eeca106725 267 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
Kojto 122:f9eeca106725 268 * @{
Kojto 122:f9eeca106725 269 */
Kojto 122:f9eeca106725 270 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 271 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) /*!< PLLP division factor = 2 */
Kojto 122:f9eeca106725 272 #define RCC_PLLP_DIV3 ((uint32_t)0x00000003U) /*!< PLLP division factor = 3 */
Kojto 122:f9eeca106725 273 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) /*!< PLLP division factor = 4 */
Kojto 122:f9eeca106725 274 #define RCC_PLLP_DIV5 ((uint32_t)0x00000005U) /*!< PLLP division factor = 5 */
Kojto 122:f9eeca106725 275 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) /*!< PLLP division factor = 6 */
Kojto 122:f9eeca106725 276 #define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */
Kojto 122:f9eeca106725 277 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) /*!< PLLP division factor = 8 */
Kojto 122:f9eeca106725 278 #define RCC_PLLP_DIV9 ((uint32_t)0x00000009U) /*!< PLLP division factor = 9 */
Kojto 122:f9eeca106725 279 #define RCC_PLLP_DIV10 ((uint32_t)0x0000000AU) /*!< PLLP division factor = 10 */
Kojto 122:f9eeca106725 280 #define RCC_PLLP_DIV11 ((uint32_t)0x0000000BU) /*!< PLLP division factor = 11 */
Kojto 122:f9eeca106725 281 #define RCC_PLLP_DIV12 ((uint32_t)0x0000000CU) /*!< PLLP division factor = 12 */
Kojto 122:f9eeca106725 282 #define RCC_PLLP_DIV13 ((uint32_t)0x0000000DU) /*!< PLLP division factor = 13 */
Kojto 122:f9eeca106725 283 #define RCC_PLLP_DIV14 ((uint32_t)0x0000000EU) /*!< PLLP division factor = 14 */
Kojto 122:f9eeca106725 284 #define RCC_PLLP_DIV15 ((uint32_t)0x0000000FU) /*!< PLLP division factor = 15 */
Kojto 122:f9eeca106725 285 #define RCC_PLLP_DIV16 ((uint32_t)0x00000010U) /*!< PLLP division factor = 16 */
Kojto 122:f9eeca106725 286 #define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */
Kojto 122:f9eeca106725 287 #define RCC_PLLP_DIV18 ((uint32_t)0x00000012U) /*!< PLLP division factor = 18 */
Kojto 122:f9eeca106725 288 #define RCC_PLLP_DIV19 ((uint32_t)0x00000013U) /*!< PLLP division factor = 19 */
Kojto 122:f9eeca106725 289 #define RCC_PLLP_DIV20 ((uint32_t)0x00000014U) /*!< PLLP division factor = 20 */
Kojto 122:f9eeca106725 290 #define RCC_PLLP_DIV21 ((uint32_t)0x00000015U) /*!< PLLP division factor = 21 */
Kojto 122:f9eeca106725 291 #define RCC_PLLP_DIV22 ((uint32_t)0x00000016U) /*!< PLLP division factor = 22 */
Kojto 122:f9eeca106725 292 #define RCC_PLLP_DIV23 ((uint32_t)0x00000017U) /*!< PLLP division factor = 23 */
Kojto 122:f9eeca106725 293 #define RCC_PLLP_DIV24 ((uint32_t)0x00000018U) /*!< PLLP division factor = 24 */
Kojto 122:f9eeca106725 294 #define RCC_PLLP_DIV25 ((uint32_t)0x00000019U) /*!< PLLP division factor = 25 */
Kojto 122:f9eeca106725 295 #define RCC_PLLP_DIV26 ((uint32_t)0x0000001AU) /*!< PLLP division factor = 26 */
Kojto 122:f9eeca106725 296 #define RCC_PLLP_DIV27 ((uint32_t)0x0000001BU) /*!< PLLP division factor = 27 */
Kojto 122:f9eeca106725 297 #define RCC_PLLP_DIV28 ((uint32_t)0x0000001CU) /*!< PLLP division factor = 28 */
Kojto 122:f9eeca106725 298 #define RCC_PLLP_DIV29 ((uint32_t)0x0000001DU) /*!< PLLP division factor = 29 */
Kojto 122:f9eeca106725 299 #define RCC_PLLP_DIV30 ((uint32_t)0x0000001EU) /*!< PLLP division factor = 30 */
Kojto 122:f9eeca106725 300 #define RCC_PLLP_DIV31 ((uint32_t)0x0000001FU) /*!< PLLP division factor = 31 */
Kojto 122:f9eeca106725 301 #else
Kojto 122:f9eeca106725 302 #define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */
Kojto 122:f9eeca106725 303 #define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */
Kojto 122:f9eeca106725 304 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 305 /**
Kojto 122:f9eeca106725 306 * @}
Kojto 122:f9eeca106725 307 */
Kojto 122:f9eeca106725 308
Kojto 122:f9eeca106725 309 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
Kojto 122:f9eeca106725 310 * @{
Kojto 122:f9eeca106725 311 */
Kojto 122:f9eeca106725 312 #define RCC_PLLQ_DIV2 ((uint32_t)0x00000002U) /*!< PLLQ division factor = 2 */
Kojto 122:f9eeca106725 313 #define RCC_PLLQ_DIV4 ((uint32_t)0x00000004U) /*!< PLLQ division factor = 4 */
Kojto 122:f9eeca106725 314 #define RCC_PLLQ_DIV6 ((uint32_t)0x00000006U) /*!< PLLQ division factor = 6 */
Kojto 122:f9eeca106725 315 #define RCC_PLLQ_DIV8 ((uint32_t)0x00000008U) /*!< PLLQ division factor = 8 */
Kojto 122:f9eeca106725 316 /**
Kojto 122:f9eeca106725 317 * @}
Kojto 122:f9eeca106725 318 */
Kojto 122:f9eeca106725 319
Kojto 122:f9eeca106725 320 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
Kojto 122:f9eeca106725 321 * @{
Kojto 122:f9eeca106725 322 */
Kojto 122:f9eeca106725 323 #define RCC_PLLR_DIV2 ((uint32_t)0x00000002U) /*!< PLLR division factor = 2 */
Kojto 122:f9eeca106725 324 #define RCC_PLLR_DIV4 ((uint32_t)0x00000004U) /*!< PLLR division factor = 4 */
Kojto 122:f9eeca106725 325 #define RCC_PLLR_DIV6 ((uint32_t)0x00000006U) /*!< PLLR division factor = 6 */
Kojto 122:f9eeca106725 326 #define RCC_PLLR_DIV8 ((uint32_t)0x00000008U) /*!< PLLR division factor = 8 */
Kojto 122:f9eeca106725 327 /**
Kojto 122:f9eeca106725 328 * @}
Kojto 122:f9eeca106725 329 */
Kojto 122:f9eeca106725 330
Kojto 122:f9eeca106725 331 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
Kojto 122:f9eeca106725 332 * @{
Kojto 122:f9eeca106725 333 */
Kojto 122:f9eeca106725 334 #define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U) /*!< No clock selected as PLL entry clock source */
Kojto 122:f9eeca106725 335 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */
Kojto 122:f9eeca106725 336 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
Kojto 122:f9eeca106725 337 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
Kojto 122:f9eeca106725 338 /**
Kojto 122:f9eeca106725 339 * @}
Kojto 122:f9eeca106725 340 */
Kojto 122:f9eeca106725 341
Kojto 122:f9eeca106725 342 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output
Kojto 122:f9eeca106725 343 * @{
Kojto 122:f9eeca106725 344 */
Kojto 122:f9eeca106725 345 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 346 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */
Kojto 122:f9eeca106725 347 #else
Kojto 122:f9eeca106725 348 #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */
Kojto 122:f9eeca106725 349 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 350 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */
Kojto 122:f9eeca106725 351 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */
Kojto 122:f9eeca106725 352 /**
Kojto 122:f9eeca106725 353 * @}
Kojto 122:f9eeca106725 354 */
Kojto 122:f9eeca106725 355
Kojto 122:f9eeca106725 356 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
Kojto 122:f9eeca106725 357 * @{
Kojto 122:f9eeca106725 358 */
Kojto 122:f9eeca106725 359 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */
Kojto 122:f9eeca106725 360 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */
Kojto 122:f9eeca106725 361 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */
Kojto 122:f9eeca106725 362 /**
Kojto 122:f9eeca106725 363 * @}
Kojto 122:f9eeca106725 364 */
Kojto 122:f9eeca106725 365
Kojto 122:f9eeca106725 366 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 367
Kojto 122:f9eeca106725 368 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
Kojto 122:f9eeca106725 369 * @{
Kojto 122:f9eeca106725 370 */
Kojto 122:f9eeca106725 371 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */
Kojto 122:f9eeca106725 372 #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */
Kojto 122:f9eeca106725 373 /**
Kojto 122:f9eeca106725 374 * @}
Kojto 122:f9eeca106725 375 */
Kojto 122:f9eeca106725 376
Kojto 122:f9eeca106725 377 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 378
Kojto 122:f9eeca106725 379 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range
Kojto 122:f9eeca106725 380 * @{
Kojto 122:f9eeca106725 381 */
Kojto 122:f9eeca106725 382 #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
Kojto 122:f9eeca106725 383 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
Kojto 122:f9eeca106725 384 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
Kojto 122:f9eeca106725 385 #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
Kojto 122:f9eeca106725 386 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
Kojto 122:f9eeca106725 387 #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
Kojto 122:f9eeca106725 388 #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
Kojto 122:f9eeca106725 389 #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
Kojto 122:f9eeca106725 390 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
Kojto 122:f9eeca106725 391 #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
Kojto 122:f9eeca106725 392 #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
Kojto 122:f9eeca106725 393 #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
Kojto 122:f9eeca106725 394 /**
Kojto 122:f9eeca106725 395 * @}
Kojto 122:f9eeca106725 396 */
Kojto 122:f9eeca106725 397
Kojto 122:f9eeca106725 398 /** @defgroup RCC_System_Clock_Type System Clock Type
Kojto 122:f9eeca106725 399 * @{
Kojto 122:f9eeca106725 400 */
Kojto 122:f9eeca106725 401 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /*!< SYSCLK to configure */
Kojto 122:f9eeca106725 402 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /*!< HCLK to configure */
Kojto 122:f9eeca106725 403 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /*!< PCLK1 to configure */
Kojto 122:f9eeca106725 404 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /*!< PCLK2 to configure */
Kojto 122:f9eeca106725 405 /**
Kojto 122:f9eeca106725 406 * @}
Kojto 122:f9eeca106725 407 */
Kojto 122:f9eeca106725 408
Kojto 122:f9eeca106725 409 /** @defgroup RCC_System_Clock_Source System Clock Source
Kojto 122:f9eeca106725 410 * @{
Kojto 122:f9eeca106725 411 */
Kojto 122:f9eeca106725 412 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
Kojto 122:f9eeca106725 413 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
Kojto 122:f9eeca106725 414 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
Kojto 122:f9eeca106725 415 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
Kojto 122:f9eeca106725 416 /**
Kojto 122:f9eeca106725 417 * @}
Kojto 122:f9eeca106725 418 */
Kojto 122:f9eeca106725 419
Kojto 122:f9eeca106725 420 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto 122:f9eeca106725 421 * @{
Kojto 122:f9eeca106725 422 */
Kojto 122:f9eeca106725 423 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
Kojto 122:f9eeca106725 424 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Kojto 122:f9eeca106725 425 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Kojto 122:f9eeca106725 426 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Kojto 122:f9eeca106725 427 /**
Kojto 122:f9eeca106725 428 * @}
Kojto 122:f9eeca106725 429 */
Kojto 122:f9eeca106725 430
Kojto 122:f9eeca106725 431 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
Kojto 122:f9eeca106725 432 * @{
Kojto 122:f9eeca106725 433 */
Kojto 122:f9eeca106725 434 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
Kojto 122:f9eeca106725 435 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
Kojto 122:f9eeca106725 436 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
Kojto 122:f9eeca106725 437 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
Kojto 122:f9eeca106725 438 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
Kojto 122:f9eeca106725 439 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
Kojto 122:f9eeca106725 440 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
Kojto 122:f9eeca106725 441 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
Kojto 122:f9eeca106725 442 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
Kojto 122:f9eeca106725 443 /**
Kojto 122:f9eeca106725 444 * @}
Kojto 122:f9eeca106725 445 */
Kojto 122:f9eeca106725 446
Kojto 122:f9eeca106725 447 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
Kojto 122:f9eeca106725 448 * @{
Kojto 122:f9eeca106725 449 */
Kojto 122:f9eeca106725 450 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
Kojto 122:f9eeca106725 451 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 452 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 453 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 454 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
Kojto 122:f9eeca106725 455 /**
Kojto 122:f9eeca106725 456 * @}
Kojto 122:f9eeca106725 457 */
Kojto 122:f9eeca106725 458
Kojto 122:f9eeca106725 459 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
Kojto 122:f9eeca106725 460 * @{
Kojto 122:f9eeca106725 461 */
Kojto 122:f9eeca106725 462 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) /*!< No clock used as RTC clock */
Kojto 122:f9eeca106725 463 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 464 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 465 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
Kojto 122:f9eeca106725 466 /**
Kojto 122:f9eeca106725 467 * @}
Kojto 122:f9eeca106725 468 */
Kojto 122:f9eeca106725 469
Kojto 122:f9eeca106725 470 /** @defgroup RCC_MCO_Index MCO Index
Kojto 122:f9eeca106725 471 * @{
Kojto 122:f9eeca106725 472 */
Kojto 122:f9eeca106725 473 #define RCC_MCO1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 474 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
Kojto 122:f9eeca106725 475 /**
Kojto 122:f9eeca106725 476 * @}
Kojto 122:f9eeca106725 477 */
Kojto 122:f9eeca106725 478
Kojto 122:f9eeca106725 479 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
Kojto 122:f9eeca106725 480 * @{
Kojto 122:f9eeca106725 481 */
Kojto 122:f9eeca106725 482 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U) /*!< MCO1 output disabled, no clock on MCO1 */
Kojto 122:f9eeca106725 483 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
Kojto 122:f9eeca106725 484 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
Kojto 122:f9eeca106725 485 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
Kojto 122:f9eeca106725 486 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
Kojto 122:f9eeca106725 487 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */
Kojto 122:f9eeca106725 488 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
Kojto 122:f9eeca106725 489 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
Kojto 122:f9eeca106725 490 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 491 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */
Kojto 122:f9eeca106725 492 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 493 /**
Kojto 122:f9eeca106725 494 * @}
Kojto 122:f9eeca106725 495 */
Kojto 122:f9eeca106725 496
Kojto 122:f9eeca106725 497 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
Kojto 122:f9eeca106725 498 * @{
Kojto 122:f9eeca106725 499 */
Kojto 122:f9eeca106725 500 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
Kojto 122:f9eeca106725 501 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
Kojto 122:f9eeca106725 502 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
Kojto 122:f9eeca106725 503 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
Kojto 122:f9eeca106725 504 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
Kojto 122:f9eeca106725 505 /**
Kojto 122:f9eeca106725 506 * @}
Kojto 122:f9eeca106725 507 */
Kojto 122:f9eeca106725 508
Kojto 122:f9eeca106725 509 /** @defgroup RCC_Interrupt Interrupts
Kojto 122:f9eeca106725 510 * @{
Kojto 122:f9eeca106725 511 */
Kojto 122:f9eeca106725 512 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
Kojto 122:f9eeca106725 513 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
Kojto 122:f9eeca106725 514 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
Kojto 122:f9eeca106725 515 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */
Kojto 122:f9eeca106725 516 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
Kojto 122:f9eeca106725 517 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
Kojto 122:f9eeca106725 518 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
Kojto 122:f9eeca106725 519 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 520 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */
Kojto 122:f9eeca106725 521 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 522 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
Kojto 122:f9eeca106725 523 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
Kojto 122:f9eeca106725 524 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 525 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
Kojto 122:f9eeca106725 526 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 527 /**
Kojto 122:f9eeca106725 528 * @}
Kojto 122:f9eeca106725 529 */
Kojto 122:f9eeca106725 530
Kojto 122:f9eeca106725 531 /** @defgroup RCC_Flag Flags
Kojto 122:f9eeca106725 532 * Elements values convention: XXXYYYYYb
Kojto 122:f9eeca106725 533 * - YYYYY : Flag position in the register
Kojto 122:f9eeca106725 534 * - XXX : Register index
Kojto 122:f9eeca106725 535 * - 001: CR register
Kojto 122:f9eeca106725 536 * - 010: BDCR register
Kojto 122:f9eeca106725 537 * - 011: CSR register
Kojto 122:f9eeca106725 538 * - 100: CRRCR register
Kojto 122:f9eeca106725 539 * @{
Kojto 122:f9eeca106725 540 */
Kojto 122:f9eeca106725 541 /* Flags in the CR register */
Kojto 122:f9eeca106725 542 #define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI Ready flag */
Kojto 122:f9eeca106725 543 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< HSI Ready flag */
Kojto 122:f9eeca106725 544 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< HSE Ready flag */
Kojto 122:f9eeca106725 545 #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL Ready flag */
Kojto 122:f9eeca106725 546 #define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY))) /*!< PLLSAI1 Ready flag */
Kojto 122:f9eeca106725 547 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 548 #define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY))) /*!< PLLSAI2 Ready flag */
Kojto 122:f9eeca106725 549 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 550
Kojto 122:f9eeca106725 551 /* Flags in the BDCR register */
Kojto 122:f9eeca106725 552 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< LSE Ready flag */
Kojto 122:f9eeca106725 553 #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD))) /*!< LSE Clock Security System Interrupt flag */
Kojto 122:f9eeca106725 554
Kojto 122:f9eeca106725 555 /* Flags in the CSR register */
Kojto 122:f9eeca106725 556 #define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< LSI Ready flag */
Kojto 122:f9eeca106725 557 #define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF))) /*!< Remove reset flag */
Kojto 122:f9eeca106725 558 #define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF))) /*!< Firewall reset flag */
Kojto 122:f9eeca106725 559 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Option Byte Loader reset flag */
Kojto 122:f9eeca106725 560 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
Kojto 122:f9eeca106725 561 #define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF))) /*!< BOR reset flag */
Kojto 122:f9eeca106725 562 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
Kojto 122:f9eeca106725 563 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
Kojto 122:f9eeca106725 564 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
Kojto 122:f9eeca106725 565 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
Kojto 122:f9eeca106725 566
Kojto 122:f9eeca106725 567 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 568 /* Flags in the CRRCR register */
Kojto 122:f9eeca106725 569 #define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) | POSITION_VAL(RCC_CRRCR_HSI48RDY))) /*!< HSI48 Ready flag */
Kojto 122:f9eeca106725 570 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 571 /**
Kojto 122:f9eeca106725 572 * @}
Kojto 122:f9eeca106725 573 */
Kojto 122:f9eeca106725 574
Kojto 122:f9eeca106725 575 /** @defgroup RCC_LSEDrive_Config LSE Drive Config
Kojto 122:f9eeca106725 576 * @{
Kojto 122:f9eeca106725 577 */
Kojto 122:f9eeca106725 578 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< LSE low drive capability */
Kojto 122:f9eeca106725 579 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
Kojto 122:f9eeca106725 580 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
Kojto 122:f9eeca106725 581 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
Kojto 122:f9eeca106725 582 /**
Kojto 122:f9eeca106725 583 * @}
Kojto 122:f9eeca106725 584 */
Kojto 122:f9eeca106725 585
Kojto 122:f9eeca106725 586 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
Kojto 122:f9eeca106725 587 * @{
Kojto 122:f9eeca106725 588 */
Kojto 122:f9eeca106725 589 #define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /*!< MSI selection after wake-up from STOP */
Kojto 122:f9eeca106725 590 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
Kojto 122:f9eeca106725 591 /**
Kojto 122:f9eeca106725 592 * @}
Kojto 122:f9eeca106725 593 */
Kojto 122:f9eeca106725 594
Kojto 122:f9eeca106725 595 /**
Kojto 122:f9eeca106725 596 * @}
Kojto 122:f9eeca106725 597 */
Kojto 122:f9eeca106725 598
Kojto 122:f9eeca106725 599 /* Exported macros -----------------------------------------------------------*/
Kojto 122:f9eeca106725 600
Kojto 122:f9eeca106725 601 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 122:f9eeca106725 602 * @{
Kojto 122:f9eeca106725 603 */
Kojto 122:f9eeca106725 604
Kojto 122:f9eeca106725 605 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto 122:f9eeca106725 606 * @brief Enable or disable the AHB1 peripheral clock.
Kojto 122:f9eeca106725 607 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 608 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 609 * using it.
Kojto 122:f9eeca106725 610 * @{
Kojto 122:f9eeca106725 611 */
Kojto 122:f9eeca106725 612
Kojto 122:f9eeca106725 613 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 614 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 615 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
Kojto 122:f9eeca106725 616 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 617 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
Kojto 122:f9eeca106725 618 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 619 } while(0)
Kojto 122:f9eeca106725 620
Kojto 122:f9eeca106725 621 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 622 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 623 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
Kojto 122:f9eeca106725 624 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 625 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
Kojto 122:f9eeca106725 626 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 627 } while(0)
Kojto 122:f9eeca106725 628
Kojto 122:f9eeca106725 629 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 630 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 631 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
Kojto 122:f9eeca106725 632 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 633 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
Kojto 122:f9eeca106725 634 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 635 } while(0)
Kojto 122:f9eeca106725 636
Kojto 122:f9eeca106725 637 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 638 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 639 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
Kojto 122:f9eeca106725 640 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 641 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
Kojto 122:f9eeca106725 642 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 643 } while(0)
Kojto 122:f9eeca106725 644
Kojto 122:f9eeca106725 645 #define __HAL_RCC_TSC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 646 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 647 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
Kojto 122:f9eeca106725 648 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 649 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
Kojto 122:f9eeca106725 650 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 651 } while(0)
Kojto 122:f9eeca106725 652
Kojto 122:f9eeca106725 653
Kojto 122:f9eeca106725 654 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
Kojto 122:f9eeca106725 655
Kojto 122:f9eeca106725 656 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
Kojto 122:f9eeca106725 657
Kojto 122:f9eeca106725 658 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
Kojto 122:f9eeca106725 659
Kojto 122:f9eeca106725 660 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
Kojto 122:f9eeca106725 661
Kojto 122:f9eeca106725 662 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
Kojto 122:f9eeca106725 663
Kojto 122:f9eeca106725 664 /**
Kojto 122:f9eeca106725 665 * @}
Kojto 122:f9eeca106725 666 */
Kojto 122:f9eeca106725 667
Kojto 122:f9eeca106725 668 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto 122:f9eeca106725 669 * @brief Enable or disable the AHB2 peripheral clock.
Kojto 122:f9eeca106725 670 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 671 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 672 * using it.
Kojto 122:f9eeca106725 673 * @{
Kojto 122:f9eeca106725 674 */
Kojto 122:f9eeca106725 675
Kojto 122:f9eeca106725 676 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 677 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 678 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
Kojto 122:f9eeca106725 679 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 680 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
Kojto 122:f9eeca106725 681 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 682 } while(0)
Kojto 122:f9eeca106725 683
Kojto 122:f9eeca106725 684 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 685 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 686 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
Kojto 122:f9eeca106725 687 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 688 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
Kojto 122:f9eeca106725 689 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 690 } while(0)
Kojto 122:f9eeca106725 691
Kojto 122:f9eeca106725 692 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 693 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 694 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
Kojto 122:f9eeca106725 695 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 696 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
Kojto 122:f9eeca106725 697 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 698 } while(0)
Kojto 122:f9eeca106725 699
Kojto 122:f9eeca106725 700 #if defined(GPIOD)
Kojto 122:f9eeca106725 701 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 702 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 703 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
Kojto 122:f9eeca106725 704 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 705 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
Kojto 122:f9eeca106725 706 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 707 } while(0)
Kojto 122:f9eeca106725 708 #endif /* GPIOD */
Kojto 122:f9eeca106725 709
Kojto 122:f9eeca106725 710 #if defined(GPIOE)
Kojto 122:f9eeca106725 711 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 712 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 713 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
Kojto 122:f9eeca106725 714 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 715 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
Kojto 122:f9eeca106725 716 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 717 } while(0)
Kojto 122:f9eeca106725 718 #endif /* GPIOE */
Kojto 122:f9eeca106725 719
Kojto 122:f9eeca106725 720 #if defined(GPIOF)
Kojto 122:f9eeca106725 721 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 722 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 723 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
Kojto 122:f9eeca106725 724 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 725 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
Kojto 122:f9eeca106725 726 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 727 } while(0)
Kojto 122:f9eeca106725 728 #endif /* GPIOF */
Kojto 122:f9eeca106725 729
Kojto 122:f9eeca106725 730 #if defined(GPIOG)
Kojto 122:f9eeca106725 731 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 732 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 733 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
Kojto 122:f9eeca106725 734 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 735 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
Kojto 122:f9eeca106725 736 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 737 } while(0)
Kojto 122:f9eeca106725 738 #endif /* GPIOG */
Kojto 122:f9eeca106725 739
Kojto 122:f9eeca106725 740 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 741 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 742 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
Kojto 122:f9eeca106725 743 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 744 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
Kojto 122:f9eeca106725 745 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 746 } while(0)
Kojto 122:f9eeca106725 747
Kojto 122:f9eeca106725 748 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 749 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 750 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 751 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
Kojto 122:f9eeca106725 752 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 753 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
Kojto 122:f9eeca106725 754 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 755 } while(0)
Kojto 122:f9eeca106725 756 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 757
Kojto 122:f9eeca106725 758 #define __HAL_RCC_ADC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 759 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 760 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
Kojto 122:f9eeca106725 761 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 762 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
Kojto 122:f9eeca106725 763 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 764 } while(0)
Kojto 122:f9eeca106725 765
Kojto 122:f9eeca106725 766 #if defined(AES)
Kojto 122:f9eeca106725 767 #define __HAL_RCC_AES_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 768 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 769 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
Kojto 122:f9eeca106725 770 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 771 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
Kojto 122:f9eeca106725 772 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 773 } while(0)
Kojto 122:f9eeca106725 774 #endif /* AES */
Kojto 122:f9eeca106725 775
Kojto 122:f9eeca106725 776 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 777 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 778 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
Kojto 122:f9eeca106725 779 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 780 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
Kojto 122:f9eeca106725 781 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 782 } while(0)
Kojto 122:f9eeca106725 783
Kojto 122:f9eeca106725 784
Kojto 122:f9eeca106725 785 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
Kojto 122:f9eeca106725 786
Kojto 122:f9eeca106725 787 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
Kojto 122:f9eeca106725 788
Kojto 122:f9eeca106725 789 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
Kojto 122:f9eeca106725 790
Kojto 122:f9eeca106725 791 #if defined(GPIOD)
Kojto 122:f9eeca106725 792 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
Kojto 122:f9eeca106725 793 #endif /* GPIOD */
Kojto 122:f9eeca106725 794
Kojto 122:f9eeca106725 795 #if defined(GPIOE)
Kojto 122:f9eeca106725 796 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
Kojto 122:f9eeca106725 797 #endif /* GPIOE */
Kojto 122:f9eeca106725 798
Kojto 122:f9eeca106725 799 #if defined(GPIOF)
Kojto 122:f9eeca106725 800 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
Kojto 122:f9eeca106725 801 #endif /* GPIOF */
Kojto 122:f9eeca106725 802
Kojto 122:f9eeca106725 803 #if defined(GPIOG)
Kojto 122:f9eeca106725 804 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
Kojto 122:f9eeca106725 805 #endif /* GPIOG */
Kojto 122:f9eeca106725 806
Kojto 122:f9eeca106725 807 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
Kojto 122:f9eeca106725 808
Kojto 122:f9eeca106725 809 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 810 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
Kojto 122:f9eeca106725 811 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 812
Kojto 122:f9eeca106725 813 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
Kojto 122:f9eeca106725 814
Kojto 122:f9eeca106725 815 #if defined(AES)
Kojto 122:f9eeca106725 816 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
Kojto 122:f9eeca106725 817 #endif /* AES */
Kojto 122:f9eeca106725 818
Kojto 122:f9eeca106725 819 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
Kojto 122:f9eeca106725 820
Kojto 122:f9eeca106725 821 /**
Kojto 122:f9eeca106725 822 * @}
Kojto 122:f9eeca106725 823 */
Kojto 122:f9eeca106725 824
Kojto 122:f9eeca106725 825 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto 122:f9eeca106725 826 * @brief Enable or disable the AHB3 peripheral clock.
Kojto 122:f9eeca106725 827 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 828 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 829 * using it.
Kojto 122:f9eeca106725 830 * @{
Kojto 122:f9eeca106725 831 */
Kojto 122:f9eeca106725 832
Kojto 122:f9eeca106725 833 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 834 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 835 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 836 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
Kojto 122:f9eeca106725 837 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 838 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
Kojto 122:f9eeca106725 839 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 840 } while(0)
Kojto 122:f9eeca106725 841 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 842
Kojto 122:f9eeca106725 843 #if defined(QUADSPI)
Kojto 122:f9eeca106725 844 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 845 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 846 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
Kojto 122:f9eeca106725 847 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 848 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
Kojto 122:f9eeca106725 849 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 850 } while(0)
Kojto 122:f9eeca106725 851 #endif /* QUADSPI */
Kojto 122:f9eeca106725 852
Kojto 122:f9eeca106725 853
Kojto 122:f9eeca106725 854 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 855 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
Kojto 122:f9eeca106725 856 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 857
Kojto 122:f9eeca106725 858 #if defined(QUADSPI)
Kojto 122:f9eeca106725 859 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
Kojto 122:f9eeca106725 860 #endif /* QUADSPI */
Kojto 122:f9eeca106725 861
Kojto 122:f9eeca106725 862 /**
Kojto 122:f9eeca106725 863 * @}
Kojto 122:f9eeca106725 864 */
Kojto 122:f9eeca106725 865
Kojto 122:f9eeca106725 866 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto 122:f9eeca106725 867 * @brief Enable or disable the APB1 peripheral clock.
Kojto 122:f9eeca106725 868 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 869 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 870 * using it.
Kojto 122:f9eeca106725 871 * @{
Kojto 122:f9eeca106725 872 */
Kojto 122:f9eeca106725 873
Kojto 122:f9eeca106725 874 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 875 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 876 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
Kojto 122:f9eeca106725 877 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 878 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
Kojto 122:f9eeca106725 879 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 880 } while(0)
Kojto 122:f9eeca106725 881
Kojto 122:f9eeca106725 882 #if defined(TIM3)
Kojto 122:f9eeca106725 883 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 884 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 885 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
Kojto 122:f9eeca106725 886 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 887 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
Kojto 122:f9eeca106725 888 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 889 } while(0)
Kojto 122:f9eeca106725 890 #endif /* TIM3 */
Kojto 122:f9eeca106725 891
Kojto 122:f9eeca106725 892 #if defined(TIM4)
Kojto 122:f9eeca106725 893 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 894 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 895 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
Kojto 122:f9eeca106725 896 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 897 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
Kojto 122:f9eeca106725 898 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 899 } while(0)
Kojto 122:f9eeca106725 900 #endif /* TIM4 */
Kojto 122:f9eeca106725 901
Kojto 122:f9eeca106725 902 #if defined(TIM5)
Kojto 122:f9eeca106725 903 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 904 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 905 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
Kojto 122:f9eeca106725 906 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 907 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
Kojto 122:f9eeca106725 908 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 909 } while(0)
Kojto 122:f9eeca106725 910 #endif /* TIM5 */
Kojto 122:f9eeca106725 911
Kojto 122:f9eeca106725 912 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 913 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 914 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
Kojto 122:f9eeca106725 915 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 916 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
Kojto 122:f9eeca106725 917 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 918 } while(0)
Kojto 122:f9eeca106725 919
Kojto 122:f9eeca106725 920 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 921 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 922 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
Kojto 122:f9eeca106725 923 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 924 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
Kojto 122:f9eeca106725 925 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 926 } while(0)
Kojto 122:f9eeca106725 927
Kojto 122:f9eeca106725 928 #if defined(LCD)
Kojto 122:f9eeca106725 929 #define __HAL_RCC_LCD_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 930 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 931 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
Kojto 122:f9eeca106725 932 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 933 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
Kojto 122:f9eeca106725 934 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 935 } while(0)
Kojto 122:f9eeca106725 936 #endif /* LCD */
Kojto 122:f9eeca106725 937
Kojto 122:f9eeca106725 938 #if defined(RCC_APB1ENR1_RTCAPBEN)
Kojto 122:f9eeca106725 939 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 940 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 941 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
Kojto 122:f9eeca106725 942 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 943 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
Kojto 122:f9eeca106725 944 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 945 } while(0)
Kojto 122:f9eeca106725 946 #endif /* RCC_APB1ENR1_RTCAPBEN */
Kojto 122:f9eeca106725 947
Kojto 122:f9eeca106725 948 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 949 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 950 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
Kojto 122:f9eeca106725 951 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 952 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
Kojto 122:f9eeca106725 953 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 954 } while(0)
Kojto 122:f9eeca106725 955
Kojto 122:f9eeca106725 956 #if defined(SPI2)
Kojto 122:f9eeca106725 957 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 958 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 959 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
Kojto 122:f9eeca106725 960 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 961 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
Kojto 122:f9eeca106725 962 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 963 } while(0)
Kojto 122:f9eeca106725 964 #endif /* SPI2 */
Kojto 122:f9eeca106725 965
Kojto 122:f9eeca106725 966 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 967 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 968 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
Kojto 122:f9eeca106725 969 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 970 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
Kojto 122:f9eeca106725 971 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 972 } while(0)
Kojto 122:f9eeca106725 973
Kojto 122:f9eeca106725 974 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 975 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 976 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
Kojto 122:f9eeca106725 977 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 978 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
Kojto 122:f9eeca106725 979 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 980 } while(0)
Kojto 122:f9eeca106725 981
Kojto 122:f9eeca106725 982 #if defined(USART3)
Kojto 122:f9eeca106725 983 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 984 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 985 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
Kojto 122:f9eeca106725 986 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 987 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
Kojto 122:f9eeca106725 988 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 989 } while(0)
Kojto 122:f9eeca106725 990 #endif /* USART3 */
Kojto 122:f9eeca106725 991
Kojto 122:f9eeca106725 992 #if defined(UART4)
Kojto 122:f9eeca106725 993 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 994 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 995 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
Kojto 122:f9eeca106725 996 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 997 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
Kojto 122:f9eeca106725 998 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 999 } while(0)
Kojto 122:f9eeca106725 1000 #endif /* UART4 */
Kojto 122:f9eeca106725 1001
Kojto 122:f9eeca106725 1002 #if defined(UART5)
Kojto 122:f9eeca106725 1003 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1004 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1005 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
Kojto 122:f9eeca106725 1006 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1007 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
Kojto 122:f9eeca106725 1008 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1009 } while(0)
Kojto 122:f9eeca106725 1010 #endif /* UART5 */
Kojto 122:f9eeca106725 1011
Kojto 122:f9eeca106725 1012 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1013 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1014 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
Kojto 122:f9eeca106725 1015 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1016 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
Kojto 122:f9eeca106725 1017 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1018 } while(0)
Kojto 122:f9eeca106725 1019
Kojto 122:f9eeca106725 1020 #if defined(I2C2)
Kojto 122:f9eeca106725 1021 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1022 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1023 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
Kojto 122:f9eeca106725 1024 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1025 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
Kojto 122:f9eeca106725 1026 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1027 } while(0)
Kojto 122:f9eeca106725 1028 #endif /* I2C2 */
Kojto 122:f9eeca106725 1029
Kojto 122:f9eeca106725 1030 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1031 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1032 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
Kojto 122:f9eeca106725 1033 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1034 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
Kojto 122:f9eeca106725 1035 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1036 } while(0)
Kojto 122:f9eeca106725 1037
Kojto 122:f9eeca106725 1038 #if defined(CRS)
Kojto 122:f9eeca106725 1039 #define __HAL_RCC_CRS_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1040 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1041 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
Kojto 122:f9eeca106725 1042 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1043 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
Kojto 122:f9eeca106725 1044 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1045 } while(0)
Kojto 122:f9eeca106725 1046 #endif /* CRS */
Kojto 122:f9eeca106725 1047
Kojto 122:f9eeca106725 1048 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1049 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1050 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
Kojto 122:f9eeca106725 1051 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1052 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
Kojto 122:f9eeca106725 1053 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1054 } while(0)
Kojto 122:f9eeca106725 1055
Kojto 122:f9eeca106725 1056 #if defined(USB)
Kojto 122:f9eeca106725 1057 #define __HAL_RCC_USB_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1058 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1059 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
Kojto 122:f9eeca106725 1060 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1061 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
Kojto 122:f9eeca106725 1062 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1063 } while(0)
Kojto 122:f9eeca106725 1064 #endif /* USB */
Kojto 122:f9eeca106725 1065
Kojto 122:f9eeca106725 1066 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1067 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1068 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
Kojto 122:f9eeca106725 1069 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1070 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
Kojto 122:f9eeca106725 1071 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1072 } while(0)
Kojto 122:f9eeca106725 1073
Kojto 122:f9eeca106725 1074 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1075 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1076 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
Kojto 122:f9eeca106725 1077 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1078 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
Kojto 122:f9eeca106725 1079 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1080 } while(0)
Kojto 122:f9eeca106725 1081
Kojto 122:f9eeca106725 1082 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1083 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1084 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
Kojto 122:f9eeca106725 1085 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1086 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
Kojto 122:f9eeca106725 1087 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1088 } while(0)
Kojto 122:f9eeca106725 1089
Kojto 122:f9eeca106725 1090 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1091 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1092 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
Kojto 122:f9eeca106725 1093 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1094 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
Kojto 122:f9eeca106725 1095 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1096 } while(0)
Kojto 122:f9eeca106725 1097
Kojto 122:f9eeca106725 1098 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1099 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1100 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
Kojto 122:f9eeca106725 1101 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1102 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
Kojto 122:f9eeca106725 1103 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1104 } while(0)
Kojto 122:f9eeca106725 1105
Kojto 122:f9eeca106725 1106 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1107 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1108 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
Kojto 122:f9eeca106725 1109 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1110 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
Kojto 122:f9eeca106725 1111 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1112 } while(0)
Kojto 122:f9eeca106725 1113
Kojto 122:f9eeca106725 1114 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1115 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1116 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
Kojto 122:f9eeca106725 1117 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1118 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
Kojto 122:f9eeca106725 1119 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1120 } while(0)
Kojto 122:f9eeca106725 1121
Kojto 122:f9eeca106725 1122
Kojto 122:f9eeca106725 1123 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
Kojto 122:f9eeca106725 1124
Kojto 122:f9eeca106725 1125 #if defined(TIM3)
Kojto 122:f9eeca106725 1126 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
Kojto 122:f9eeca106725 1127 #endif /* TIM3 */
Kojto 122:f9eeca106725 1128
Kojto 122:f9eeca106725 1129 #if defined(TIM4)
Kojto 122:f9eeca106725 1130 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
Kojto 122:f9eeca106725 1131 #endif /* TIM4 */
Kojto 122:f9eeca106725 1132
Kojto 122:f9eeca106725 1133 #if defined(TIM5)
Kojto 122:f9eeca106725 1134 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
Kojto 122:f9eeca106725 1135 #endif /* TIM5 */
Kojto 122:f9eeca106725 1136
Kojto 122:f9eeca106725 1137 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
Kojto 122:f9eeca106725 1138
Kojto 122:f9eeca106725 1139 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
Kojto 122:f9eeca106725 1140
Kojto 122:f9eeca106725 1141 #if defined(LCD)
Kojto 122:f9eeca106725 1142 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
Kojto 122:f9eeca106725 1143 #endif /* LCD */
Kojto 122:f9eeca106725 1144
Kojto 122:f9eeca106725 1145 #if defined(RCC_APB1ENR1_RTCAPBEN)
Kojto 122:f9eeca106725 1146 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
Kojto 122:f9eeca106725 1147 #endif /* RCC_APB1ENR1_RTCAPBEN */
Kojto 122:f9eeca106725 1148
Kojto 122:f9eeca106725 1149 #if defined(SPI2)
Kojto 122:f9eeca106725 1150 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
Kojto 122:f9eeca106725 1151 #endif /* SPI2 */
Kojto 122:f9eeca106725 1152
Kojto 122:f9eeca106725 1153 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
Kojto 122:f9eeca106725 1154
Kojto 122:f9eeca106725 1155 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
Kojto 122:f9eeca106725 1156
Kojto 122:f9eeca106725 1157 #if defined(USART3)
Kojto 122:f9eeca106725 1158 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
Kojto 122:f9eeca106725 1159 #endif /* USART3 */
Kojto 122:f9eeca106725 1160
Kojto 122:f9eeca106725 1161 #if defined(UART4)
Kojto 122:f9eeca106725 1162 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
Kojto 122:f9eeca106725 1163 #endif /* UART4 */
Kojto 122:f9eeca106725 1164
Kojto 122:f9eeca106725 1165 #if defined(UART5)
Kojto 122:f9eeca106725 1166 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
Kojto 122:f9eeca106725 1167 #endif /* UART5 */
Kojto 122:f9eeca106725 1168
Kojto 122:f9eeca106725 1169 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
Kojto 122:f9eeca106725 1170
Kojto 122:f9eeca106725 1171 #if defined(I2C2)
Kojto 122:f9eeca106725 1172 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
Kojto 122:f9eeca106725 1173 #endif /* I2C2 */
Kojto 122:f9eeca106725 1174
Kojto 122:f9eeca106725 1175 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
Kojto 122:f9eeca106725 1176
Kojto 122:f9eeca106725 1177 #if defined(CRS)
Kojto 122:f9eeca106725 1178 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
Kojto 122:f9eeca106725 1179 #endif /* CRS */
Kojto 122:f9eeca106725 1180
Kojto 122:f9eeca106725 1181 #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
Kojto 122:f9eeca106725 1182
Kojto 122:f9eeca106725 1183 #if defined(USB)
Kojto 122:f9eeca106725 1184 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);
Kojto 122:f9eeca106725 1185 #endif /* USB */
Kojto 122:f9eeca106725 1186
Kojto 122:f9eeca106725 1187 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
Kojto 122:f9eeca106725 1188
Kojto 122:f9eeca106725 1189 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
Kojto 122:f9eeca106725 1190
Kojto 122:f9eeca106725 1191 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
Kojto 122:f9eeca106725 1192
Kojto 122:f9eeca106725 1193 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
Kojto 122:f9eeca106725 1194
Kojto 122:f9eeca106725 1195 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
Kojto 122:f9eeca106725 1196
Kojto 122:f9eeca106725 1197 #define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
Kojto 122:f9eeca106725 1198
Kojto 122:f9eeca106725 1199 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
Kojto 122:f9eeca106725 1200
Kojto 122:f9eeca106725 1201 /**
Kojto 122:f9eeca106725 1202 * @}
Kojto 122:f9eeca106725 1203 */
Kojto 122:f9eeca106725 1204
Kojto 122:f9eeca106725 1205 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto 122:f9eeca106725 1206 * @brief Enable or disable the APB2 peripheral clock.
Kojto 122:f9eeca106725 1207 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 1208 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 1209 * using it.
Kojto 122:f9eeca106725 1210 * @{
Kojto 122:f9eeca106725 1211 */
Kojto 122:f9eeca106725 1212
Kojto 122:f9eeca106725 1213 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1214 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1215 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
Kojto 122:f9eeca106725 1216 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1217 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
Kojto 122:f9eeca106725 1218 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1219 } while(0)
Kojto 122:f9eeca106725 1220
Kojto 122:f9eeca106725 1221 #define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1222 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1223 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
Kojto 122:f9eeca106725 1224 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1225 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
Kojto 122:f9eeca106725 1226 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1227 } while(0)
Kojto 122:f9eeca106725 1228
Kojto 122:f9eeca106725 1229 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
Kojto 122:f9eeca106725 1230 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1231 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1232 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
Kojto 122:f9eeca106725 1233 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1234 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
Kojto 122:f9eeca106725 1235 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1236 } while(0)
Kojto 122:f9eeca106725 1237 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
Kojto 122:f9eeca106725 1238
Kojto 122:f9eeca106725 1239 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1240 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1241 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
Kojto 122:f9eeca106725 1242 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1243 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
Kojto 122:f9eeca106725 1244 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1245 } while(0)
Kojto 122:f9eeca106725 1246
Kojto 122:f9eeca106725 1247 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1248 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1249 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
Kojto 122:f9eeca106725 1250 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1251 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
Kojto 122:f9eeca106725 1252 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1253 } while(0)
Kojto 122:f9eeca106725 1254
Kojto 122:f9eeca106725 1255 #if defined(TIM8)
Kojto 122:f9eeca106725 1256 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1257 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1258 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
Kojto 122:f9eeca106725 1259 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1260 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
Kojto 122:f9eeca106725 1261 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1262 } while(0)
Kojto 122:f9eeca106725 1263 #endif /* TIM8 */
Kojto 122:f9eeca106725 1264
Kojto 122:f9eeca106725 1265 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1266 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1267 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
Kojto 122:f9eeca106725 1268 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1269 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
Kojto 122:f9eeca106725 1270 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1271 } while(0)
Kojto 122:f9eeca106725 1272
Kojto 122:f9eeca106725 1273
Kojto 122:f9eeca106725 1274 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1275 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1276 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
Kojto 122:f9eeca106725 1277 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1278 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
Kojto 122:f9eeca106725 1279 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1280 } while(0)
Kojto 122:f9eeca106725 1281
Kojto 122:f9eeca106725 1282 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1283 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1284 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
Kojto 122:f9eeca106725 1285 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1286 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
Kojto 122:f9eeca106725 1287 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1288 } while(0)
Kojto 122:f9eeca106725 1289
Kojto 122:f9eeca106725 1290 #if defined(TIM17)
Kojto 122:f9eeca106725 1291 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1292 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1293 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
Kojto 122:f9eeca106725 1294 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1295 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
Kojto 122:f9eeca106725 1296 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1297 } while(0)
Kojto 122:f9eeca106725 1298 #endif /* TIM17 */
Kojto 122:f9eeca106725 1299
Kojto 122:f9eeca106725 1300 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1301 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1302 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
Kojto 122:f9eeca106725 1303 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1304 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
Kojto 122:f9eeca106725 1305 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1306 } while(0)
Kojto 122:f9eeca106725 1307
Kojto 122:f9eeca106725 1308 #if defined(SAI2)
Kojto 122:f9eeca106725 1309 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1310 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1311 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
Kojto 122:f9eeca106725 1312 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1313 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
Kojto 122:f9eeca106725 1314 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1315 } while(0)
Kojto 122:f9eeca106725 1316 #endif /* SAI2 */
Kojto 122:f9eeca106725 1317
Kojto 122:f9eeca106725 1318 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 1319 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1320 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1321 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
Kojto 122:f9eeca106725 1322 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1323 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
Kojto 122:f9eeca106725 1324 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1325 } while(0)
Kojto 122:f9eeca106725 1326 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 1327
Kojto 122:f9eeca106725 1328
Kojto 122:f9eeca106725 1329 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
Kojto 122:f9eeca106725 1330
Kojto 122:f9eeca106725 1331 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
Kojto 122:f9eeca106725 1332 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
Kojto 122:f9eeca106725 1333 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
Kojto 122:f9eeca106725 1334
Kojto 122:f9eeca106725 1335 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
Kojto 122:f9eeca106725 1336
Kojto 122:f9eeca106725 1337 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
Kojto 122:f9eeca106725 1338
Kojto 122:f9eeca106725 1339 #if defined(TIM8)
Kojto 122:f9eeca106725 1340 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
Kojto 122:f9eeca106725 1341 #endif /* TIM8 */
Kojto 122:f9eeca106725 1342
Kojto 122:f9eeca106725 1343 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
Kojto 122:f9eeca106725 1344
Kojto 122:f9eeca106725 1345 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
Kojto 122:f9eeca106725 1346
Kojto 122:f9eeca106725 1347 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
Kojto 122:f9eeca106725 1348
Kojto 122:f9eeca106725 1349 #if defined(TIM17)
Kojto 122:f9eeca106725 1350 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
Kojto 122:f9eeca106725 1351 #endif /* TIM17 */
Kojto 122:f9eeca106725 1352
Kojto 122:f9eeca106725 1353 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
Kojto 122:f9eeca106725 1354
Kojto 122:f9eeca106725 1355 #if defined(SAI2)
Kojto 122:f9eeca106725 1356 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
Kojto 122:f9eeca106725 1357 #endif /* SAI2 */
Kojto 122:f9eeca106725 1358
Kojto 122:f9eeca106725 1359 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 1360 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)
Kojto 122:f9eeca106725 1361 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 1362
Kojto 122:f9eeca106725 1363 /**
Kojto 122:f9eeca106725 1364 * @}
Kojto 122:f9eeca106725 1365 */
Kojto 122:f9eeca106725 1366
Kojto 122:f9eeca106725 1367 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
Kojto 122:f9eeca106725 1368 * @brief Check whether the AHB1 peripheral clock is enabled or not.
Kojto 122:f9eeca106725 1369 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 1370 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 1371 * using it.
Kojto 122:f9eeca106725 1372 * @{
Kojto 122:f9eeca106725 1373 */
Kojto 122:f9eeca106725 1374
Kojto 122:f9eeca106725 1375 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
Kojto 122:f9eeca106725 1376
Kojto 122:f9eeca106725 1377 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
Kojto 122:f9eeca106725 1378
Kojto 122:f9eeca106725 1379 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
Kojto 122:f9eeca106725 1380
Kojto 122:f9eeca106725 1381 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
Kojto 122:f9eeca106725 1382
Kojto 122:f9eeca106725 1383 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
Kojto 122:f9eeca106725 1384
Kojto 122:f9eeca106725 1385
Kojto 122:f9eeca106725 1386 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
Kojto 122:f9eeca106725 1387
Kojto 122:f9eeca106725 1388 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
Kojto 122:f9eeca106725 1389
Kojto 122:f9eeca106725 1390 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
Kojto 122:f9eeca106725 1391
Kojto 122:f9eeca106725 1392 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
Kojto 122:f9eeca106725 1393
Kojto 122:f9eeca106725 1394 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
Kojto 122:f9eeca106725 1395
Kojto 122:f9eeca106725 1396 /**
Kojto 122:f9eeca106725 1397 * @}
Kojto 122:f9eeca106725 1398 */
Kojto 122:f9eeca106725 1399
Kojto 122:f9eeca106725 1400 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
Kojto 122:f9eeca106725 1401 * @brief Check whether the AHB2 peripheral clock is enabled or not.
Kojto 122:f9eeca106725 1402 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 1403 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 1404 * using it.
Kojto 122:f9eeca106725 1405 * @{
Kojto 122:f9eeca106725 1406 */
Kojto 122:f9eeca106725 1407
Kojto 122:f9eeca106725 1408 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
Kojto 122:f9eeca106725 1409
Kojto 122:f9eeca106725 1410 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
Kojto 122:f9eeca106725 1411
Kojto 122:f9eeca106725 1412 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
Kojto 122:f9eeca106725 1413
Kojto 122:f9eeca106725 1414 #if defined(GPIOD)
Kojto 122:f9eeca106725 1415 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
Kojto 122:f9eeca106725 1416 #endif /* GPIOD */
Kojto 122:f9eeca106725 1417
Kojto 122:f9eeca106725 1418 #if defined(GPIOE)
Kojto 122:f9eeca106725 1419 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
Kojto 122:f9eeca106725 1420 #endif /* GPIOE */
Kojto 122:f9eeca106725 1421
Kojto 122:f9eeca106725 1422 #if defined(GPIOF)
Kojto 122:f9eeca106725 1423 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
Kojto 122:f9eeca106725 1424 #endif /* GPIOF */
Kojto 122:f9eeca106725 1425
Kojto 122:f9eeca106725 1426 #if defined(GPIOG)
Kojto 122:f9eeca106725 1427 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
Kojto 122:f9eeca106725 1428 #endif /* GPIOG */
Kojto 122:f9eeca106725 1429
Kojto 122:f9eeca106725 1430 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
Kojto 122:f9eeca106725 1431
Kojto 122:f9eeca106725 1432 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 1433 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
Kojto 122:f9eeca106725 1434 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 1435
Kojto 122:f9eeca106725 1436 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
Kojto 122:f9eeca106725 1437
Kojto 122:f9eeca106725 1438 #if defined(AES)
Kojto 122:f9eeca106725 1439 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
Kojto 122:f9eeca106725 1440 #endif /* AES */
Kojto 122:f9eeca106725 1441
Kojto 122:f9eeca106725 1442 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
Kojto 122:f9eeca106725 1443
Kojto 122:f9eeca106725 1444
Kojto 122:f9eeca106725 1445 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
Kojto 122:f9eeca106725 1446
Kojto 122:f9eeca106725 1447 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
Kojto 122:f9eeca106725 1448
Kojto 122:f9eeca106725 1449 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
Kojto 122:f9eeca106725 1450
Kojto 122:f9eeca106725 1451 #if defined(GPIOD)
Kojto 122:f9eeca106725 1452 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
Kojto 122:f9eeca106725 1453 #endif /* GPIOD */
Kojto 122:f9eeca106725 1454
Kojto 122:f9eeca106725 1455 #if defined(GPIOE)
Kojto 122:f9eeca106725 1456 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
Kojto 122:f9eeca106725 1457 #endif /* GPIOE */
Kojto 122:f9eeca106725 1458
Kojto 122:f9eeca106725 1459 #if defined(GPIOF)
Kojto 122:f9eeca106725 1460 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
Kojto 122:f9eeca106725 1461 #endif /* GPIOF */
Kojto 122:f9eeca106725 1462
Kojto 122:f9eeca106725 1463 #if defined(GPIOG)
Kojto 122:f9eeca106725 1464 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
Kojto 122:f9eeca106725 1465 #endif /* GPIOG */
Kojto 122:f9eeca106725 1466
Kojto 122:f9eeca106725 1467 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
Kojto 122:f9eeca106725 1468
Kojto 122:f9eeca106725 1469 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 1470 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
Kojto 122:f9eeca106725 1471 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 1472
Kojto 122:f9eeca106725 1473 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
Kojto 122:f9eeca106725 1474
Kojto 122:f9eeca106725 1475 #if defined(AES)
Kojto 122:f9eeca106725 1476 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
Kojto 122:f9eeca106725 1477 #endif /* AES */
Kojto 122:f9eeca106725 1478
Kojto 122:f9eeca106725 1479 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
Kojto 122:f9eeca106725 1480
Kojto 122:f9eeca106725 1481 /**
Kojto 122:f9eeca106725 1482 * @}
Kojto 122:f9eeca106725 1483 */
Kojto 122:f9eeca106725 1484
Kojto 122:f9eeca106725 1485 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
Kojto 122:f9eeca106725 1486 * @brief Check whether the AHB3 peripheral clock is enabled or not.
Kojto 122:f9eeca106725 1487 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 1488 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 1489 * using it.
Kojto 122:f9eeca106725 1490 * @{
Kojto 122:f9eeca106725 1491 */
Kojto 122:f9eeca106725 1492
Kojto 122:f9eeca106725 1493 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 1494 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
Kojto 122:f9eeca106725 1495 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 1496
Kojto 122:f9eeca106725 1497 #if defined(QUADSPI)
Kojto 122:f9eeca106725 1498 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
Kojto 122:f9eeca106725 1499 #endif /* QUADSPI */
Kojto 122:f9eeca106725 1500
Kojto 122:f9eeca106725 1501 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 1502 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
Kojto 122:f9eeca106725 1503 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 1504
Kojto 122:f9eeca106725 1505 #if defined(QUADSPI)
Kojto 122:f9eeca106725 1506 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
Kojto 122:f9eeca106725 1507 #endif /* QUADSPI */
Kojto 122:f9eeca106725 1508
Kojto 122:f9eeca106725 1509 /**
Kojto 122:f9eeca106725 1510 * @}
Kojto 122:f9eeca106725 1511 */
Kojto 122:f9eeca106725 1512
Kojto 122:f9eeca106725 1513 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
Kojto 122:f9eeca106725 1514 * @brief Check whether the APB1 peripheral clock is enabled or not.
Kojto 122:f9eeca106725 1515 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 1516 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 1517 * using it.
Kojto 122:f9eeca106725 1518 * @{
Kojto 122:f9eeca106725 1519 */
Kojto 122:f9eeca106725 1520
Kojto 122:f9eeca106725 1521 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
Kojto 122:f9eeca106725 1522
Kojto 122:f9eeca106725 1523 #if defined(TIM3)
Kojto 122:f9eeca106725 1524 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
Kojto 122:f9eeca106725 1525 #endif /* TIM3 */
Kojto 122:f9eeca106725 1526
Kojto 122:f9eeca106725 1527 #if defined(TIM4)
Kojto 122:f9eeca106725 1528 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
Kojto 122:f9eeca106725 1529 #endif /* TIM4 */
Kojto 122:f9eeca106725 1530
Kojto 122:f9eeca106725 1531 #if defined(TIM5)
Kojto 122:f9eeca106725 1532 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
Kojto 122:f9eeca106725 1533 #endif /* TIM5 */
Kojto 122:f9eeca106725 1534
Kojto 122:f9eeca106725 1535 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
Kojto 122:f9eeca106725 1536
Kojto 122:f9eeca106725 1537 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
Kojto 122:f9eeca106725 1538
Kojto 122:f9eeca106725 1539 #if defined(LCD)
Kojto 122:f9eeca106725 1540 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
Kojto 122:f9eeca106725 1541 #endif /* LCD */
Kojto 122:f9eeca106725 1542
Kojto 122:f9eeca106725 1543 #if defined(RCC_APB1ENR1_RTCAPBEN)
Kojto 122:f9eeca106725 1544 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET)
Kojto 122:f9eeca106725 1545 #endif /* RCC_APB1ENR1_RTCAPBEN */
Kojto 122:f9eeca106725 1546
Kojto 122:f9eeca106725 1547 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
Kojto 122:f9eeca106725 1548
Kojto 122:f9eeca106725 1549 #if defined(SPI2)
Kojto 122:f9eeca106725 1550 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
Kojto 122:f9eeca106725 1551 #endif /* SPI2 */
Kojto 122:f9eeca106725 1552
Kojto 122:f9eeca106725 1553 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
Kojto 122:f9eeca106725 1554
Kojto 122:f9eeca106725 1555 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
Kojto 122:f9eeca106725 1556
Kojto 122:f9eeca106725 1557 #if defined(USART3)
Kojto 122:f9eeca106725 1558 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
Kojto 122:f9eeca106725 1559 #endif /* USART3 */
Kojto 122:f9eeca106725 1560
Kojto 122:f9eeca106725 1561 #if defined(UART4)
Kojto 122:f9eeca106725 1562 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
Kojto 122:f9eeca106725 1563 #endif /* UART4 */
Kojto 122:f9eeca106725 1564
Kojto 122:f9eeca106725 1565 #if defined(UART5)
Kojto 122:f9eeca106725 1566 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
Kojto 122:f9eeca106725 1567 #endif /* UART5 */
Kojto 122:f9eeca106725 1568
Kojto 122:f9eeca106725 1569 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
Kojto 122:f9eeca106725 1570
Kojto 122:f9eeca106725 1571 #if defined(I2C2)
Kojto 122:f9eeca106725 1572 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
Kojto 122:f9eeca106725 1573 #endif /* I2C2 */
Kojto 122:f9eeca106725 1574
Kojto 122:f9eeca106725 1575 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
Kojto 122:f9eeca106725 1576
Kojto 122:f9eeca106725 1577 #if defined(CRS)
Kojto 122:f9eeca106725 1578 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET)
Kojto 122:f9eeca106725 1579 #endif /* CRS */
Kojto 122:f9eeca106725 1580
Kojto 122:f9eeca106725 1581 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
Kojto 122:f9eeca106725 1582
Kojto 122:f9eeca106725 1583 #if defined(USB)
Kojto 122:f9eeca106725 1584 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET)
Kojto 122:f9eeca106725 1585 #endif /* USB */
Kojto 122:f9eeca106725 1586
Kojto 122:f9eeca106725 1587 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
Kojto 122:f9eeca106725 1588
Kojto 122:f9eeca106725 1589 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
Kojto 122:f9eeca106725 1590
Kojto 122:f9eeca106725 1591 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
Kojto 122:f9eeca106725 1592
Kojto 122:f9eeca106725 1593 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
Kojto 122:f9eeca106725 1594
Kojto 122:f9eeca106725 1595 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
Kojto 122:f9eeca106725 1596
Kojto 122:f9eeca106725 1597 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
Kojto 122:f9eeca106725 1598
Kojto 122:f9eeca106725 1599 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
Kojto 122:f9eeca106725 1600
Kojto 122:f9eeca106725 1601
Kojto 122:f9eeca106725 1602 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
Kojto 122:f9eeca106725 1603
Kojto 122:f9eeca106725 1604 #if defined(TIM3)
Kojto 122:f9eeca106725 1605 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
Kojto 122:f9eeca106725 1606 #endif /* TIM3 */
Kojto 122:f9eeca106725 1607
Kojto 122:f9eeca106725 1608 #if defined(TIM4)
Kojto 122:f9eeca106725 1609 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
Kojto 122:f9eeca106725 1610 #endif /* TIM4 */
Kojto 122:f9eeca106725 1611
Kojto 122:f9eeca106725 1612 #if defined(TIM5)
Kojto 122:f9eeca106725 1613 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
Kojto 122:f9eeca106725 1614 #endif /* TIM5 */
Kojto 122:f9eeca106725 1615
Kojto 122:f9eeca106725 1616 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
Kojto 122:f9eeca106725 1617
Kojto 122:f9eeca106725 1618 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
Kojto 122:f9eeca106725 1619
Kojto 122:f9eeca106725 1620 #if defined(LCD)
Kojto 122:f9eeca106725 1621 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
Kojto 122:f9eeca106725 1622 #endif /* LCD */
Kojto 122:f9eeca106725 1623
Kojto 122:f9eeca106725 1624 #if defined(RCC_APB1ENR1_RTCAPBEN)
Kojto 122:f9eeca106725 1625 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET)
Kojto 122:f9eeca106725 1626 #endif /* RCC_APB1ENR1_RTCAPBEN */
Kojto 122:f9eeca106725 1627
Kojto 122:f9eeca106725 1628 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
Kojto 122:f9eeca106725 1629
Kojto 122:f9eeca106725 1630 #if defined(SPI2)
Kojto 122:f9eeca106725 1631 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
Kojto 122:f9eeca106725 1632 #endif /* SPI2 */
Kojto 122:f9eeca106725 1633
Kojto 122:f9eeca106725 1634 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
Kojto 122:f9eeca106725 1635
Kojto 122:f9eeca106725 1636 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
Kojto 122:f9eeca106725 1637
Kojto 122:f9eeca106725 1638 #if defined(USART3)
Kojto 122:f9eeca106725 1639 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
Kojto 122:f9eeca106725 1640 #endif /* USART3 */
Kojto 122:f9eeca106725 1641
Kojto 122:f9eeca106725 1642 #if defined(UART4)
Kojto 122:f9eeca106725 1643 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
Kojto 122:f9eeca106725 1644 #endif /* UART4 */
Kojto 122:f9eeca106725 1645
Kojto 122:f9eeca106725 1646 #if defined(UART5)
Kojto 122:f9eeca106725 1647 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
Kojto 122:f9eeca106725 1648 #endif /* UART5 */
Kojto 122:f9eeca106725 1649
Kojto 122:f9eeca106725 1650 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
Kojto 122:f9eeca106725 1651
Kojto 122:f9eeca106725 1652 #if defined(I2C2)
Kojto 122:f9eeca106725 1653 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
Kojto 122:f9eeca106725 1654 #endif /* I2C2 */
Kojto 122:f9eeca106725 1655
Kojto 122:f9eeca106725 1656 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
Kojto 122:f9eeca106725 1657
Kojto 122:f9eeca106725 1658 #if defined(CRS)
Kojto 122:f9eeca106725 1659 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET)
Kojto 122:f9eeca106725 1660 #endif /* CRS */
Kojto 122:f9eeca106725 1661
Kojto 122:f9eeca106725 1662 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
Kojto 122:f9eeca106725 1663
Kojto 122:f9eeca106725 1664 #if defined(USB)
Kojto 122:f9eeca106725 1665 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET)
Kojto 122:f9eeca106725 1666 #endif /* USB */
Kojto 122:f9eeca106725 1667
Kojto 122:f9eeca106725 1668 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
Kojto 122:f9eeca106725 1669
Kojto 122:f9eeca106725 1670 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
Kojto 122:f9eeca106725 1671
Kojto 122:f9eeca106725 1672 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
Kojto 122:f9eeca106725 1673
Kojto 122:f9eeca106725 1674 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
Kojto 122:f9eeca106725 1675
Kojto 122:f9eeca106725 1676 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
Kojto 122:f9eeca106725 1677
Kojto 122:f9eeca106725 1678 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
Kojto 122:f9eeca106725 1679
Kojto 122:f9eeca106725 1680 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
Kojto 122:f9eeca106725 1681
Kojto 122:f9eeca106725 1682 /**
Kojto 122:f9eeca106725 1683 * @}
Kojto 122:f9eeca106725 1684 */
Kojto 122:f9eeca106725 1685
Kojto 122:f9eeca106725 1686 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
Kojto 122:f9eeca106725 1687 * @brief Check whether the APB2 peripheral clock is enabled or not.
Kojto 122:f9eeca106725 1688 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 1689 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 1690 * using it.
Kojto 122:f9eeca106725 1691 * @{
Kojto 122:f9eeca106725 1692 */
Kojto 122:f9eeca106725 1693
Kojto 122:f9eeca106725 1694 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
Kojto 122:f9eeca106725 1695
Kojto 122:f9eeca106725 1696 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
Kojto 122:f9eeca106725 1697
Kojto 122:f9eeca106725 1698 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
Kojto 122:f9eeca106725 1699 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
Kojto 122:f9eeca106725 1700 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
Kojto 122:f9eeca106725 1701
Kojto 122:f9eeca106725 1702 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
Kojto 122:f9eeca106725 1703
Kojto 122:f9eeca106725 1704 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
Kojto 122:f9eeca106725 1705
Kojto 122:f9eeca106725 1706 #if defined(TIM8)
Kojto 122:f9eeca106725 1707 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
Kojto 122:f9eeca106725 1708 #endif /* TIM8 */
Kojto 122:f9eeca106725 1709
Kojto 122:f9eeca106725 1710 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
Kojto 122:f9eeca106725 1711
Kojto 122:f9eeca106725 1712 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
Kojto 122:f9eeca106725 1713
Kojto 122:f9eeca106725 1714 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
Kojto 122:f9eeca106725 1715
Kojto 122:f9eeca106725 1716 #if defined(TIM17)
Kojto 122:f9eeca106725 1717 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
Kojto 122:f9eeca106725 1718 #endif /* TIM17 */
Kojto 122:f9eeca106725 1719
Kojto 122:f9eeca106725 1720 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
Kojto 122:f9eeca106725 1721
Kojto 122:f9eeca106725 1722 #if defined(SAI2)
Kojto 122:f9eeca106725 1723 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
Kojto 122:f9eeca106725 1724 #endif /* SAI2 */
Kojto 122:f9eeca106725 1725
Kojto 122:f9eeca106725 1726 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 1727 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET)
Kojto 122:f9eeca106725 1728 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 1729
Kojto 122:f9eeca106725 1730
Kojto 122:f9eeca106725 1731 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
Kojto 122:f9eeca106725 1732
Kojto 122:f9eeca106725 1733 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
Kojto 122:f9eeca106725 1734 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
Kojto 122:f9eeca106725 1735 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
Kojto 122:f9eeca106725 1736
Kojto 122:f9eeca106725 1737 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
Kojto 122:f9eeca106725 1738
Kojto 122:f9eeca106725 1739 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
Kojto 122:f9eeca106725 1740
Kojto 122:f9eeca106725 1741 #if defined(TIM8)
Kojto 122:f9eeca106725 1742 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
Kojto 122:f9eeca106725 1743 #endif /* TIM8 */
Kojto 122:f9eeca106725 1744
Kojto 122:f9eeca106725 1745 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
Kojto 122:f9eeca106725 1746
Kojto 122:f9eeca106725 1747 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
Kojto 122:f9eeca106725 1748
Kojto 122:f9eeca106725 1749 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
Kojto 122:f9eeca106725 1750
Kojto 122:f9eeca106725 1751 #if defined(TIM17)
Kojto 122:f9eeca106725 1752 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
Kojto 122:f9eeca106725 1753 #endif /* TIM17 */
Kojto 122:f9eeca106725 1754
Kojto 122:f9eeca106725 1755 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
Kojto 122:f9eeca106725 1756
Kojto 122:f9eeca106725 1757 #if defined(SAI2)
Kojto 122:f9eeca106725 1758 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
Kojto 122:f9eeca106725 1759 #endif /* SAI2 */
Kojto 122:f9eeca106725 1760
Kojto 122:f9eeca106725 1761 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 1762 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET)
Kojto 122:f9eeca106725 1763 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 1764
Kojto 122:f9eeca106725 1765 /**
Kojto 122:f9eeca106725 1766 * @}
Kojto 122:f9eeca106725 1767 */
Kojto 122:f9eeca106725 1768
Kojto 122:f9eeca106725 1769 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
Kojto 122:f9eeca106725 1770 * @brief Force or release AHB1 peripheral reset.
Kojto 122:f9eeca106725 1771 * @{
Kojto 122:f9eeca106725 1772 */
Kojto 122:f9eeca106725 1773 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
Kojto 122:f9eeca106725 1774
Kojto 122:f9eeca106725 1775 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
Kojto 122:f9eeca106725 1776
Kojto 122:f9eeca106725 1777 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
Kojto 122:f9eeca106725 1778
Kojto 122:f9eeca106725 1779 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
Kojto 122:f9eeca106725 1780
Kojto 122:f9eeca106725 1781 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
Kojto 122:f9eeca106725 1782
Kojto 122:f9eeca106725 1783 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
Kojto 122:f9eeca106725 1784
Kojto 122:f9eeca106725 1785
Kojto 122:f9eeca106725 1786 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
Kojto 122:f9eeca106725 1787
Kojto 122:f9eeca106725 1788 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
Kojto 122:f9eeca106725 1789
Kojto 122:f9eeca106725 1790 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
Kojto 122:f9eeca106725 1791
Kojto 122:f9eeca106725 1792 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
Kojto 122:f9eeca106725 1793
Kojto 122:f9eeca106725 1794 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
Kojto 122:f9eeca106725 1795
Kojto 122:f9eeca106725 1796 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
Kojto 122:f9eeca106725 1797
Kojto 122:f9eeca106725 1798 /**
Kojto 122:f9eeca106725 1799 * @}
Kojto 122:f9eeca106725 1800 */
Kojto 122:f9eeca106725 1801
Kojto 122:f9eeca106725 1802 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
Kojto 122:f9eeca106725 1803 * @brief Force or release AHB2 peripheral reset.
Kojto 122:f9eeca106725 1804 * @{
Kojto 122:f9eeca106725 1805 */
Kojto 122:f9eeca106725 1806 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
Kojto 122:f9eeca106725 1807
Kojto 122:f9eeca106725 1808 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
Kojto 122:f9eeca106725 1809
Kojto 122:f9eeca106725 1810 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
Kojto 122:f9eeca106725 1811
Kojto 122:f9eeca106725 1812 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
Kojto 122:f9eeca106725 1813
Kojto 122:f9eeca106725 1814 #if defined(GPIOD)
Kojto 122:f9eeca106725 1815 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
Kojto 122:f9eeca106725 1816 #endif /* GPIOD */
Kojto 122:f9eeca106725 1817
Kojto 122:f9eeca106725 1818 #if defined(GPIOE)
Kojto 122:f9eeca106725 1819 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
Kojto 122:f9eeca106725 1820 #endif /* GPIOE */
Kojto 122:f9eeca106725 1821
Kojto 122:f9eeca106725 1822 #if defined(GPIOF)
Kojto 122:f9eeca106725 1823 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
Kojto 122:f9eeca106725 1824 #endif /* GPIOF */
Kojto 122:f9eeca106725 1825
Kojto 122:f9eeca106725 1826 #if defined(GPIOG)
Kojto 122:f9eeca106725 1827 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
Kojto 122:f9eeca106725 1828 #endif /* GPIOG */
Kojto 122:f9eeca106725 1829
Kojto 122:f9eeca106725 1830 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
Kojto 122:f9eeca106725 1831
Kojto 122:f9eeca106725 1832 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 1833 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
Kojto 122:f9eeca106725 1834 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 1835
Kojto 122:f9eeca106725 1836 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
Kojto 122:f9eeca106725 1837
Kojto 122:f9eeca106725 1838 #if defined(AES)
Kojto 122:f9eeca106725 1839 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
Kojto 122:f9eeca106725 1840 #endif /* AES */
Kojto 122:f9eeca106725 1841
Kojto 122:f9eeca106725 1842 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
Kojto 122:f9eeca106725 1843
Kojto 122:f9eeca106725 1844
Kojto 122:f9eeca106725 1845 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
Kojto 122:f9eeca106725 1846
Kojto 122:f9eeca106725 1847 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
Kojto 122:f9eeca106725 1848
Kojto 122:f9eeca106725 1849 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
Kojto 122:f9eeca106725 1850
Kojto 122:f9eeca106725 1851 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
Kojto 122:f9eeca106725 1852
Kojto 122:f9eeca106725 1853 #if defined(GPIOD)
Kojto 122:f9eeca106725 1854 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
Kojto 122:f9eeca106725 1855 #endif /* GPIOD */
Kojto 122:f9eeca106725 1856
Kojto 122:f9eeca106725 1857 #if defined(GPIOE)
Kojto 122:f9eeca106725 1858 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
Kojto 122:f9eeca106725 1859 #endif /* GPIOE */
Kojto 122:f9eeca106725 1860
Kojto 122:f9eeca106725 1861 #if defined(GPIOF)
Kojto 122:f9eeca106725 1862 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
Kojto 122:f9eeca106725 1863 #endif /* GPIOF */
Kojto 122:f9eeca106725 1864
Kojto 122:f9eeca106725 1865 #if defined(GPIOG)
Kojto 122:f9eeca106725 1866 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
Kojto 122:f9eeca106725 1867 #endif /* GPIOG */
Kojto 122:f9eeca106725 1868
Kojto 122:f9eeca106725 1869 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
Kojto 122:f9eeca106725 1870
Kojto 122:f9eeca106725 1871 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 1872 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
Kojto 122:f9eeca106725 1873 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 1874
Kojto 122:f9eeca106725 1875 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
Kojto 122:f9eeca106725 1876
Kojto 122:f9eeca106725 1877 #if defined(AES)
Kojto 122:f9eeca106725 1878 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
Kojto 122:f9eeca106725 1879 #endif /* AES */
Kojto 122:f9eeca106725 1880
Kojto 122:f9eeca106725 1881 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
Kojto 122:f9eeca106725 1882
Kojto 122:f9eeca106725 1883 /**
Kojto 122:f9eeca106725 1884 * @}
Kojto 122:f9eeca106725 1885 */
Kojto 122:f9eeca106725 1886
Kojto 122:f9eeca106725 1887 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
Kojto 122:f9eeca106725 1888 * @brief Force or release AHB3 peripheral reset.
Kojto 122:f9eeca106725 1889 * @{
Kojto 122:f9eeca106725 1890 */
Kojto 122:f9eeca106725 1891 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
Kojto 122:f9eeca106725 1892
Kojto 122:f9eeca106725 1893 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 1894 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
Kojto 122:f9eeca106725 1895 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 1896
Kojto 122:f9eeca106725 1897 #if defined(QUADSPI)
Kojto 122:f9eeca106725 1898 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
Kojto 122:f9eeca106725 1899 #endif /* QUADSPI */
Kojto 122:f9eeca106725 1900
Kojto 122:f9eeca106725 1901
Kojto 122:f9eeca106725 1902 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
Kojto 122:f9eeca106725 1903
Kojto 122:f9eeca106725 1904 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 1905 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
Kojto 122:f9eeca106725 1906 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 1907
Kojto 122:f9eeca106725 1908 #if defined(QUADSPI)
Kojto 122:f9eeca106725 1909 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
Kojto 122:f9eeca106725 1910 #endif /* QUADSPI */
Kojto 122:f9eeca106725 1911
Kojto 122:f9eeca106725 1912 /**
Kojto 122:f9eeca106725 1913 * @}
Kojto 122:f9eeca106725 1914 */
Kojto 122:f9eeca106725 1915
Kojto 122:f9eeca106725 1916 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
Kojto 122:f9eeca106725 1917 * @brief Force or release APB1 peripheral reset.
Kojto 122:f9eeca106725 1918 * @{
Kojto 122:f9eeca106725 1919 */
Kojto 122:f9eeca106725 1920 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
Kojto 122:f9eeca106725 1921
Kojto 122:f9eeca106725 1922 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
Kojto 122:f9eeca106725 1923
Kojto 122:f9eeca106725 1924 #if defined(TIM3)
Kojto 122:f9eeca106725 1925 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
Kojto 122:f9eeca106725 1926 #endif /* TIM3 */
Kojto 122:f9eeca106725 1927
Kojto 122:f9eeca106725 1928 #if defined(TIM4)
Kojto 122:f9eeca106725 1929 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
Kojto 122:f9eeca106725 1930 #endif /* TIM4 */
Kojto 122:f9eeca106725 1931
Kojto 122:f9eeca106725 1932 #if defined(TIM5)
Kojto 122:f9eeca106725 1933 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
Kojto 122:f9eeca106725 1934 #endif /* TIM5 */
Kojto 122:f9eeca106725 1935
Kojto 122:f9eeca106725 1936 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
Kojto 122:f9eeca106725 1937
Kojto 122:f9eeca106725 1938 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
Kojto 122:f9eeca106725 1939
Kojto 122:f9eeca106725 1940 #if defined(LCD)
Kojto 122:f9eeca106725 1941 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
Kojto 122:f9eeca106725 1942 #endif /* LCD */
Kojto 122:f9eeca106725 1943
Kojto 122:f9eeca106725 1944 #if defined(SPI2)
Kojto 122:f9eeca106725 1945 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
Kojto 122:f9eeca106725 1946 #endif /* SPI2 */
Kojto 122:f9eeca106725 1947
Kojto 122:f9eeca106725 1948 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
Kojto 122:f9eeca106725 1949
Kojto 122:f9eeca106725 1950 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
Kojto 122:f9eeca106725 1951
Kojto 122:f9eeca106725 1952 #if defined(USART3)
Kojto 122:f9eeca106725 1953 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
Kojto 122:f9eeca106725 1954 #endif /* USART3 */
Kojto 122:f9eeca106725 1955
Kojto 122:f9eeca106725 1956 #if defined(UART4)
Kojto 122:f9eeca106725 1957 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
Kojto 122:f9eeca106725 1958 #endif /* UART4 */
Kojto 122:f9eeca106725 1959
Kojto 122:f9eeca106725 1960 #if defined(UART5)
Kojto 122:f9eeca106725 1961 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
Kojto 122:f9eeca106725 1962 #endif /* UART5 */
Kojto 122:f9eeca106725 1963
Kojto 122:f9eeca106725 1964 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
Kojto 122:f9eeca106725 1965
Kojto 122:f9eeca106725 1966 #if defined(I2C2)
Kojto 122:f9eeca106725 1967 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
Kojto 122:f9eeca106725 1968 #endif /* I2C2 */
Kojto 122:f9eeca106725 1969
Kojto 122:f9eeca106725 1970 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
Kojto 122:f9eeca106725 1971
Kojto 122:f9eeca106725 1972 #if defined(CRS)
Kojto 122:f9eeca106725 1973 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
Kojto 122:f9eeca106725 1974 #endif /* CRS */
Kojto 122:f9eeca106725 1975
Kojto 122:f9eeca106725 1976 #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
Kojto 122:f9eeca106725 1977
Kojto 122:f9eeca106725 1978 #if defined(USB)
Kojto 122:f9eeca106725 1979 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
Kojto 122:f9eeca106725 1980 #endif /* USB */
Kojto 122:f9eeca106725 1981
Kojto 122:f9eeca106725 1982 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
Kojto 122:f9eeca106725 1983
Kojto 122:f9eeca106725 1984 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
Kojto 122:f9eeca106725 1985
Kojto 122:f9eeca106725 1986 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
Kojto 122:f9eeca106725 1987
Kojto 122:f9eeca106725 1988 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
Kojto 122:f9eeca106725 1989
Kojto 122:f9eeca106725 1990 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
Kojto 122:f9eeca106725 1991
Kojto 122:f9eeca106725 1992 #define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
Kojto 122:f9eeca106725 1993
Kojto 122:f9eeca106725 1994 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
Kojto 122:f9eeca106725 1995
Kojto 122:f9eeca106725 1996
Kojto 122:f9eeca106725 1997 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
Kojto 122:f9eeca106725 1998
Kojto 122:f9eeca106725 1999 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
Kojto 122:f9eeca106725 2000
Kojto 122:f9eeca106725 2001 #if defined(TIM3)
Kojto 122:f9eeca106725 2002 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
Kojto 122:f9eeca106725 2003 #endif /* TIM3 */
Kojto 122:f9eeca106725 2004
Kojto 122:f9eeca106725 2005 #if defined(TIM4)
Kojto 122:f9eeca106725 2006 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
Kojto 122:f9eeca106725 2007 #endif /* TIM4 */
Kojto 122:f9eeca106725 2008
Kojto 122:f9eeca106725 2009 #if defined(TIM5)
Kojto 122:f9eeca106725 2010 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
Kojto 122:f9eeca106725 2011 #endif /* TIM5 */
Kojto 122:f9eeca106725 2012
Kojto 122:f9eeca106725 2013 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
Kojto 122:f9eeca106725 2014
Kojto 122:f9eeca106725 2015 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
Kojto 122:f9eeca106725 2016
Kojto 122:f9eeca106725 2017 #if defined(LCD)
Kojto 122:f9eeca106725 2018 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
Kojto 122:f9eeca106725 2019 #endif /* LCD */
Kojto 122:f9eeca106725 2020
Kojto 122:f9eeca106725 2021 #if defined(SPI2)
Kojto 122:f9eeca106725 2022 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
Kojto 122:f9eeca106725 2023 #endif /* SPI2 */
Kojto 122:f9eeca106725 2024
Kojto 122:f9eeca106725 2025 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
Kojto 122:f9eeca106725 2026
Kojto 122:f9eeca106725 2027 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
Kojto 122:f9eeca106725 2028
Kojto 122:f9eeca106725 2029 #if defined(USART3)
Kojto 122:f9eeca106725 2030 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
Kojto 122:f9eeca106725 2031 #endif /* USART3 */
Kojto 122:f9eeca106725 2032
Kojto 122:f9eeca106725 2033 #if defined(UART4)
Kojto 122:f9eeca106725 2034 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
Kojto 122:f9eeca106725 2035 #endif /* UART4 */
Kojto 122:f9eeca106725 2036
Kojto 122:f9eeca106725 2037 #if defined(UART5)
Kojto 122:f9eeca106725 2038 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
Kojto 122:f9eeca106725 2039 #endif /* UART5 */
Kojto 122:f9eeca106725 2040
Kojto 122:f9eeca106725 2041 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
Kojto 122:f9eeca106725 2042
Kojto 122:f9eeca106725 2043 #if defined(I2C2)
Kojto 122:f9eeca106725 2044 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
Kojto 122:f9eeca106725 2045 #endif /* I2C2 */
Kojto 122:f9eeca106725 2046
Kojto 122:f9eeca106725 2047 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
Kojto 122:f9eeca106725 2048
Kojto 122:f9eeca106725 2049 #if defined(CRS)
Kojto 122:f9eeca106725 2050 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
Kojto 122:f9eeca106725 2051 #endif /* CRS */
Kojto 122:f9eeca106725 2052
Kojto 122:f9eeca106725 2053 #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
Kojto 122:f9eeca106725 2054
Kojto 122:f9eeca106725 2055 #if defined(USB)
Kojto 122:f9eeca106725 2056 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
Kojto 122:f9eeca106725 2057 #endif /* USB */
Kojto 122:f9eeca106725 2058
Kojto 122:f9eeca106725 2059 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
Kojto 122:f9eeca106725 2060
Kojto 122:f9eeca106725 2061 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
Kojto 122:f9eeca106725 2062
Kojto 122:f9eeca106725 2063 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
Kojto 122:f9eeca106725 2064
Kojto 122:f9eeca106725 2065 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
Kojto 122:f9eeca106725 2066
Kojto 122:f9eeca106725 2067 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
Kojto 122:f9eeca106725 2068
Kojto 122:f9eeca106725 2069 #define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
Kojto 122:f9eeca106725 2070
Kojto 122:f9eeca106725 2071 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
Kojto 122:f9eeca106725 2072
Kojto 122:f9eeca106725 2073 /**
Kojto 122:f9eeca106725 2074 * @}
Kojto 122:f9eeca106725 2075 */
Kojto 122:f9eeca106725 2076
Kojto 122:f9eeca106725 2077 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
Kojto 122:f9eeca106725 2078 * @brief Force or release APB2 peripheral reset.
Kojto 122:f9eeca106725 2079 * @{
Kojto 122:f9eeca106725 2080 */
Kojto 122:f9eeca106725 2081 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
Kojto 122:f9eeca106725 2082
Kojto 122:f9eeca106725 2083 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
Kojto 122:f9eeca106725 2084
Kojto 122:f9eeca106725 2085 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
Kojto 122:f9eeca106725 2086 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
Kojto 122:f9eeca106725 2087 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
Kojto 122:f9eeca106725 2088
Kojto 122:f9eeca106725 2089 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
Kojto 122:f9eeca106725 2090
Kojto 122:f9eeca106725 2091 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
Kojto 122:f9eeca106725 2092
Kojto 122:f9eeca106725 2093 #if defined(TIM8)
Kojto 122:f9eeca106725 2094 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
Kojto 122:f9eeca106725 2095 #endif /* TIM8 */
Kojto 122:f9eeca106725 2096
Kojto 122:f9eeca106725 2097 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
Kojto 122:f9eeca106725 2098
Kojto 122:f9eeca106725 2099 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
Kojto 122:f9eeca106725 2100
Kojto 122:f9eeca106725 2101 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
Kojto 122:f9eeca106725 2102
Kojto 122:f9eeca106725 2103 #if defined(TIM17)
Kojto 122:f9eeca106725 2104 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
Kojto 122:f9eeca106725 2105 #endif /* TIM17 */
Kojto 122:f9eeca106725 2106
Kojto 122:f9eeca106725 2107 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
Kojto 122:f9eeca106725 2108
Kojto 122:f9eeca106725 2109 #if defined(SAI2)
Kojto 122:f9eeca106725 2110 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
Kojto 122:f9eeca106725 2111 #endif /* SAI2 */
Kojto 122:f9eeca106725 2112
Kojto 122:f9eeca106725 2113 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 2114 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
Kojto 122:f9eeca106725 2115 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 2116
Kojto 122:f9eeca106725 2117
Kojto 122:f9eeca106725 2118 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
Kojto 122:f9eeca106725 2119
Kojto 122:f9eeca106725 2120 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
Kojto 122:f9eeca106725 2121
Kojto 122:f9eeca106725 2122 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
Kojto 122:f9eeca106725 2123 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
Kojto 122:f9eeca106725 2124 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
Kojto 122:f9eeca106725 2125
Kojto 122:f9eeca106725 2126 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
Kojto 122:f9eeca106725 2127
Kojto 122:f9eeca106725 2128 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
Kojto 122:f9eeca106725 2129
Kojto 122:f9eeca106725 2130 #if defined(TIM8)
Kojto 122:f9eeca106725 2131 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
Kojto 122:f9eeca106725 2132 #endif /* TIM8 */
Kojto 122:f9eeca106725 2133
Kojto 122:f9eeca106725 2134 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
Kojto 122:f9eeca106725 2135
Kojto 122:f9eeca106725 2136 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
Kojto 122:f9eeca106725 2137
Kojto 122:f9eeca106725 2138 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
Kojto 122:f9eeca106725 2139
Kojto 122:f9eeca106725 2140 #if defined(TIM17)
Kojto 122:f9eeca106725 2141 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
Kojto 122:f9eeca106725 2142 #endif /* TIM17 */
Kojto 122:f9eeca106725 2143
Kojto 122:f9eeca106725 2144 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
Kojto 122:f9eeca106725 2145
Kojto 122:f9eeca106725 2146 #if defined(SAI2)
Kojto 122:f9eeca106725 2147 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
Kojto 122:f9eeca106725 2148 #endif /* SAI2 */
Kojto 122:f9eeca106725 2149
Kojto 122:f9eeca106725 2150 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 2151 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
Kojto 122:f9eeca106725 2152 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 2153
Kojto 122:f9eeca106725 2154 /**
Kojto 122:f9eeca106725 2155 * @}
Kojto 122:f9eeca106725 2156 */
Kojto 122:f9eeca106725 2157
Kojto 122:f9eeca106725 2158 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
Kojto 122:f9eeca106725 2159 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 122:f9eeca106725 2160 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2161 * power consumption.
Kojto 122:f9eeca106725 2162 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2163 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2164 * @{
Kojto 122:f9eeca106725 2165 */
Kojto 122:f9eeca106725 2166
Kojto 122:f9eeca106725 2167 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
Kojto 122:f9eeca106725 2168
Kojto 122:f9eeca106725 2169 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
Kojto 122:f9eeca106725 2170
Kojto 122:f9eeca106725 2171 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
Kojto 122:f9eeca106725 2172
Kojto 122:f9eeca106725 2173 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
Kojto 122:f9eeca106725 2174
Kojto 122:f9eeca106725 2175 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
Kojto 122:f9eeca106725 2176
Kojto 122:f9eeca106725 2177 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
Kojto 122:f9eeca106725 2178
Kojto 122:f9eeca106725 2179
Kojto 122:f9eeca106725 2180 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
Kojto 122:f9eeca106725 2181
Kojto 122:f9eeca106725 2182 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
Kojto 122:f9eeca106725 2183
Kojto 122:f9eeca106725 2184 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
Kojto 122:f9eeca106725 2185
Kojto 122:f9eeca106725 2186 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
Kojto 122:f9eeca106725 2187
Kojto 122:f9eeca106725 2188 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
Kojto 122:f9eeca106725 2189
Kojto 122:f9eeca106725 2190 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
Kojto 122:f9eeca106725 2191
Kojto 122:f9eeca106725 2192 /**
Kojto 122:f9eeca106725 2193 * @}
Kojto 122:f9eeca106725 2194 */
Kojto 122:f9eeca106725 2195
Kojto 122:f9eeca106725 2196 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
Kojto 122:f9eeca106725 2197 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 122:f9eeca106725 2198 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2199 * power consumption.
Kojto 122:f9eeca106725 2200 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2201 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2202 * @{
Kojto 122:f9eeca106725 2203 */
Kojto 122:f9eeca106725 2204
Kojto 122:f9eeca106725 2205 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
Kojto 122:f9eeca106725 2206
Kojto 122:f9eeca106725 2207 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
Kojto 122:f9eeca106725 2208
Kojto 122:f9eeca106725 2209 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
Kojto 122:f9eeca106725 2210
Kojto 122:f9eeca106725 2211 #if defined(GPIOD)
Kojto 122:f9eeca106725 2212 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
Kojto 122:f9eeca106725 2213 #endif /* GPIOD */
Kojto 122:f9eeca106725 2214
Kojto 122:f9eeca106725 2215 #if defined(GPIOE)
Kojto 122:f9eeca106725 2216 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
Kojto 122:f9eeca106725 2217 #endif /* GPIOE */
Kojto 122:f9eeca106725 2218
Kojto 122:f9eeca106725 2219 #if defined(GPIOF)
Kojto 122:f9eeca106725 2220 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
Kojto 122:f9eeca106725 2221 #endif /* GPIOF */
Kojto 122:f9eeca106725 2222
Kojto 122:f9eeca106725 2223 #if defined(GPIOG)
Kojto 122:f9eeca106725 2224 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
Kojto 122:f9eeca106725 2225 #endif /* GPIOG */
Kojto 122:f9eeca106725 2226
Kojto 122:f9eeca106725 2227 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
Kojto 122:f9eeca106725 2228
Kojto 122:f9eeca106725 2229 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
Kojto 122:f9eeca106725 2230
Kojto 122:f9eeca106725 2231 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 2232 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
Kojto 122:f9eeca106725 2233 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 2234
Kojto 122:f9eeca106725 2235 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
Kojto 122:f9eeca106725 2236
Kojto 122:f9eeca106725 2237 #if defined(AES)
Kojto 122:f9eeca106725 2238 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
Kojto 122:f9eeca106725 2239 #endif /* AES */
Kojto 122:f9eeca106725 2240
Kojto 122:f9eeca106725 2241 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
Kojto 122:f9eeca106725 2242
Kojto 122:f9eeca106725 2243
Kojto 122:f9eeca106725 2244 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
Kojto 122:f9eeca106725 2245
Kojto 122:f9eeca106725 2246 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
Kojto 122:f9eeca106725 2247
Kojto 122:f9eeca106725 2248 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
Kojto 122:f9eeca106725 2249
Kojto 122:f9eeca106725 2250 #if defined(GPIOD)
Kojto 122:f9eeca106725 2251 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
Kojto 122:f9eeca106725 2252 #endif /* GPIOD */
Kojto 122:f9eeca106725 2253
Kojto 122:f9eeca106725 2254 #if defined(GPIOE)
Kojto 122:f9eeca106725 2255 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
Kojto 122:f9eeca106725 2256 #endif /* GPIOE */
Kojto 122:f9eeca106725 2257
Kojto 122:f9eeca106725 2258 #if defined(GPIOF)
Kojto 122:f9eeca106725 2259 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
Kojto 122:f9eeca106725 2260 #endif /* GPIOF */
Kojto 122:f9eeca106725 2261
Kojto 122:f9eeca106725 2262 #if defined(GPIOG)
Kojto 122:f9eeca106725 2263 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
Kojto 122:f9eeca106725 2264 #endif /* GPIOG */
Kojto 122:f9eeca106725 2265
Kojto 122:f9eeca106725 2266 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
Kojto 122:f9eeca106725 2267
Kojto 122:f9eeca106725 2268 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
Kojto 122:f9eeca106725 2269
Kojto 122:f9eeca106725 2270 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 2271 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
Kojto 122:f9eeca106725 2272 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 2273
Kojto 122:f9eeca106725 2274 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
Kojto 122:f9eeca106725 2275
Kojto 122:f9eeca106725 2276 #if defined(AES)
Kojto 122:f9eeca106725 2277 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
Kojto 122:f9eeca106725 2278 #endif /* AES */
Kojto 122:f9eeca106725 2279
Kojto 122:f9eeca106725 2280 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
Kojto 122:f9eeca106725 2281
Kojto 122:f9eeca106725 2282 /**
Kojto 122:f9eeca106725 2283 * @}
Kojto 122:f9eeca106725 2284 */
Kojto 122:f9eeca106725 2285
Kojto 122:f9eeca106725 2286 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
Kojto 122:f9eeca106725 2287 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto 122:f9eeca106725 2288 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2289 * power consumption.
Kojto 122:f9eeca106725 2290 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2291 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2292 * @{
Kojto 122:f9eeca106725 2293 */
Kojto 122:f9eeca106725 2294
Kojto 122:f9eeca106725 2295 #if defined(QUADSPI)
Kojto 122:f9eeca106725 2296 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
Kojto 122:f9eeca106725 2297 #endif /* QUADSPI */
Kojto 122:f9eeca106725 2298
Kojto 122:f9eeca106725 2299 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 2300 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
Kojto 122:f9eeca106725 2301 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 2302
Kojto 122:f9eeca106725 2303
Kojto 122:f9eeca106725 2304 #if defined(QUADSPI)
Kojto 122:f9eeca106725 2305 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
Kojto 122:f9eeca106725 2306 #endif /* QUADSPI */
Kojto 122:f9eeca106725 2307
Kojto 122:f9eeca106725 2308 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 2309 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
Kojto 122:f9eeca106725 2310 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 2311
Kojto 122:f9eeca106725 2312 /**
Kojto 122:f9eeca106725 2313 * @}
Kojto 122:f9eeca106725 2314 */
Kojto 122:f9eeca106725 2315
Kojto 122:f9eeca106725 2316 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
Kojto 122:f9eeca106725 2317 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 122:f9eeca106725 2318 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2319 * power consumption.
Kojto 122:f9eeca106725 2320 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2321 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2322 * @{
Kojto 122:f9eeca106725 2323 */
Kojto 122:f9eeca106725 2324
Kojto 122:f9eeca106725 2325 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
Kojto 122:f9eeca106725 2326
Kojto 122:f9eeca106725 2327 #if defined(TIM3)
Kojto 122:f9eeca106725 2328 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
Kojto 122:f9eeca106725 2329 #endif /* TIM3 */
Kojto 122:f9eeca106725 2330
Kojto 122:f9eeca106725 2331 #if defined(TIM4)
Kojto 122:f9eeca106725 2332 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
Kojto 122:f9eeca106725 2333 #endif /* TIM4 */
Kojto 122:f9eeca106725 2334
Kojto 122:f9eeca106725 2335 #if defined(TIM5)
Kojto 122:f9eeca106725 2336 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
Kojto 122:f9eeca106725 2337 #endif /* TIM5 */
Kojto 122:f9eeca106725 2338
Kojto 122:f9eeca106725 2339 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
Kojto 122:f9eeca106725 2340
Kojto 122:f9eeca106725 2341 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
Kojto 122:f9eeca106725 2342
Kojto 122:f9eeca106725 2343 #if defined(LCD)
Kojto 122:f9eeca106725 2344 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
Kojto 122:f9eeca106725 2345 #endif /* LCD */
Kojto 122:f9eeca106725 2346
Kojto 122:f9eeca106725 2347 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
Kojto 122:f9eeca106725 2348 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
Kojto 122:f9eeca106725 2349 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
Kojto 122:f9eeca106725 2350
Kojto 122:f9eeca106725 2351 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
Kojto 122:f9eeca106725 2352
Kojto 122:f9eeca106725 2353 #if defined(SPI2)
Kojto 122:f9eeca106725 2354 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
Kojto 122:f9eeca106725 2355 #endif /* SPI2 */
Kojto 122:f9eeca106725 2356
Kojto 122:f9eeca106725 2357 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
Kojto 122:f9eeca106725 2358
Kojto 122:f9eeca106725 2359 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
Kojto 122:f9eeca106725 2360
Kojto 122:f9eeca106725 2361 #if defined(USART3)
Kojto 122:f9eeca106725 2362 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
Kojto 122:f9eeca106725 2363 #endif /* USART3 */
Kojto 122:f9eeca106725 2364
Kojto 122:f9eeca106725 2365 #if defined(UART4)
Kojto 122:f9eeca106725 2366 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
Kojto 122:f9eeca106725 2367 #endif /* UART4 */
Kojto 122:f9eeca106725 2368
Kojto 122:f9eeca106725 2369 #if defined(UART5)
Kojto 122:f9eeca106725 2370 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
Kojto 122:f9eeca106725 2371 #endif /* UART5 */
Kojto 122:f9eeca106725 2372
Kojto 122:f9eeca106725 2373 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
Kojto 122:f9eeca106725 2374
Kojto 122:f9eeca106725 2375 #if defined(I2C2)
Kojto 122:f9eeca106725 2376 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
Kojto 122:f9eeca106725 2377 #endif /* I2C2 */
Kojto 122:f9eeca106725 2378
Kojto 122:f9eeca106725 2379 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
Kojto 122:f9eeca106725 2380
Kojto 122:f9eeca106725 2381 #if defined(CRS)
Kojto 122:f9eeca106725 2382 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
Kojto 122:f9eeca106725 2383 #endif /* CRS */
Kojto 122:f9eeca106725 2384
Kojto 122:f9eeca106725 2385 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
Kojto 122:f9eeca106725 2386
Kojto 122:f9eeca106725 2387 #if defined(USB)
Kojto 122:f9eeca106725 2388 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
Kojto 122:f9eeca106725 2389 #endif /* USB */
Kojto 122:f9eeca106725 2390
Kojto 122:f9eeca106725 2391 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
Kojto 122:f9eeca106725 2392
Kojto 122:f9eeca106725 2393 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
Kojto 122:f9eeca106725 2394
Kojto 122:f9eeca106725 2395 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
Kojto 122:f9eeca106725 2396
Kojto 122:f9eeca106725 2397 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
Kojto 122:f9eeca106725 2398
Kojto 122:f9eeca106725 2399 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
Kojto 122:f9eeca106725 2400
Kojto 122:f9eeca106725 2401 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
Kojto 122:f9eeca106725 2402
Kojto 122:f9eeca106725 2403 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
Kojto 122:f9eeca106725 2404
Kojto 122:f9eeca106725 2405
Kojto 122:f9eeca106725 2406 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
Kojto 122:f9eeca106725 2407
Kojto 122:f9eeca106725 2408 #if defined(TIM3)
Kojto 122:f9eeca106725 2409 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
Kojto 122:f9eeca106725 2410 #endif /* TIM3 */
Kojto 122:f9eeca106725 2411
Kojto 122:f9eeca106725 2412 #if defined(TIM4)
Kojto 122:f9eeca106725 2413 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
Kojto 122:f9eeca106725 2414 #endif /* TIM4 */
Kojto 122:f9eeca106725 2415
Kojto 122:f9eeca106725 2416 #if defined(TIM5)
Kojto 122:f9eeca106725 2417 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
Kojto 122:f9eeca106725 2418 #endif /* TIM5 */
Kojto 122:f9eeca106725 2419
Kojto 122:f9eeca106725 2420 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
Kojto 122:f9eeca106725 2421
Kojto 122:f9eeca106725 2422 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
Kojto 122:f9eeca106725 2423
Kojto 122:f9eeca106725 2424 #if defined(LCD)
Kojto 122:f9eeca106725 2425 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
Kojto 122:f9eeca106725 2426 #endif /* LCD */
Kojto 122:f9eeca106725 2427
Kojto 122:f9eeca106725 2428 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
Kojto 122:f9eeca106725 2429 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
Kojto 122:f9eeca106725 2430 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
Kojto 122:f9eeca106725 2431
Kojto 122:f9eeca106725 2432 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
Kojto 122:f9eeca106725 2433
Kojto 122:f9eeca106725 2434 #if defined(SPI2)
Kojto 122:f9eeca106725 2435 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
Kojto 122:f9eeca106725 2436 #endif /* SPI2 */
Kojto 122:f9eeca106725 2437
Kojto 122:f9eeca106725 2438 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
Kojto 122:f9eeca106725 2439
Kojto 122:f9eeca106725 2440 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
Kojto 122:f9eeca106725 2441
Kojto 122:f9eeca106725 2442 #if defined(USART3)
Kojto 122:f9eeca106725 2443 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
Kojto 122:f9eeca106725 2444 #endif /* USART3 */
Kojto 122:f9eeca106725 2445
Kojto 122:f9eeca106725 2446 #if defined(UART4)
Kojto 122:f9eeca106725 2447 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
Kojto 122:f9eeca106725 2448 #endif /* UART4 */
Kojto 122:f9eeca106725 2449
Kojto 122:f9eeca106725 2450 #if defined(UART5)
Kojto 122:f9eeca106725 2451 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
Kojto 122:f9eeca106725 2452 #endif /* UART5 */
Kojto 122:f9eeca106725 2453
Kojto 122:f9eeca106725 2454 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
Kojto 122:f9eeca106725 2455
Kojto 122:f9eeca106725 2456 #if defined(I2C2)
Kojto 122:f9eeca106725 2457 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
Kojto 122:f9eeca106725 2458 #endif /* I2C2 */
Kojto 122:f9eeca106725 2459
Kojto 122:f9eeca106725 2460 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
Kojto 122:f9eeca106725 2461
Kojto 122:f9eeca106725 2462 #if defined(CRS)
Kojto 122:f9eeca106725 2463 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
Kojto 122:f9eeca106725 2464 #endif /* CRS */
Kojto 122:f9eeca106725 2465
Kojto 122:f9eeca106725 2466 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
Kojto 122:f9eeca106725 2467
Kojto 122:f9eeca106725 2468 #if defined(USB)
Kojto 122:f9eeca106725 2469 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
Kojto 122:f9eeca106725 2470 #endif /* USB */
Kojto 122:f9eeca106725 2471
Kojto 122:f9eeca106725 2472 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
Kojto 122:f9eeca106725 2473
Kojto 122:f9eeca106725 2474 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
Kojto 122:f9eeca106725 2475
Kojto 122:f9eeca106725 2476 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
Kojto 122:f9eeca106725 2477
Kojto 122:f9eeca106725 2478 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
Kojto 122:f9eeca106725 2479
Kojto 122:f9eeca106725 2480 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
Kojto 122:f9eeca106725 2481
Kojto 122:f9eeca106725 2482 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
Kojto 122:f9eeca106725 2483
Kojto 122:f9eeca106725 2484 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
Kojto 122:f9eeca106725 2485
Kojto 122:f9eeca106725 2486 /**
Kojto 122:f9eeca106725 2487 * @}
Kojto 122:f9eeca106725 2488 */
Kojto 122:f9eeca106725 2489
Kojto 122:f9eeca106725 2490 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
Kojto 122:f9eeca106725 2491 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 122:f9eeca106725 2492 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2493 * power consumption.
Kojto 122:f9eeca106725 2494 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2495 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2496 * @{
Kojto 122:f9eeca106725 2497 */
Kojto 122:f9eeca106725 2498
Kojto 122:f9eeca106725 2499 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
Kojto 122:f9eeca106725 2500
Kojto 122:f9eeca106725 2501 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
Kojto 122:f9eeca106725 2502 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
Kojto 122:f9eeca106725 2503 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
Kojto 122:f9eeca106725 2504
Kojto 122:f9eeca106725 2505 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
Kojto 122:f9eeca106725 2506
Kojto 122:f9eeca106725 2507 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
Kojto 122:f9eeca106725 2508
Kojto 122:f9eeca106725 2509 #if defined(TIM8)
Kojto 122:f9eeca106725 2510 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
Kojto 122:f9eeca106725 2511 #endif /* TIM8 */
Kojto 122:f9eeca106725 2512
Kojto 122:f9eeca106725 2513 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
Kojto 122:f9eeca106725 2514
Kojto 122:f9eeca106725 2515 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
Kojto 122:f9eeca106725 2516
Kojto 122:f9eeca106725 2517 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
Kojto 122:f9eeca106725 2518
Kojto 122:f9eeca106725 2519 #if defined(TIM17)
Kojto 122:f9eeca106725 2520 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
Kojto 122:f9eeca106725 2521 #endif /* TIM17 */
Kojto 122:f9eeca106725 2522
Kojto 122:f9eeca106725 2523 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
Kojto 122:f9eeca106725 2524
Kojto 122:f9eeca106725 2525 #if defined(SAI2)
Kojto 122:f9eeca106725 2526 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
Kojto 122:f9eeca106725 2527 #endif /* SAI2 */
Kojto 122:f9eeca106725 2528
Kojto 122:f9eeca106725 2529 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 2530 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
Kojto 122:f9eeca106725 2531 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 2532
Kojto 122:f9eeca106725 2533
Kojto 122:f9eeca106725 2534 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
Kojto 122:f9eeca106725 2535
Kojto 122:f9eeca106725 2536 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
Kojto 122:f9eeca106725 2537 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
Kojto 122:f9eeca106725 2538 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
Kojto 122:f9eeca106725 2539
Kojto 122:f9eeca106725 2540 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
Kojto 122:f9eeca106725 2541
Kojto 122:f9eeca106725 2542 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
Kojto 122:f9eeca106725 2543
Kojto 122:f9eeca106725 2544 #if defined(TIM8)
Kojto 122:f9eeca106725 2545 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
Kojto 122:f9eeca106725 2546 #endif /* TIM8 */
Kojto 122:f9eeca106725 2547
Kojto 122:f9eeca106725 2548 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
Kojto 122:f9eeca106725 2549
Kojto 122:f9eeca106725 2550 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
Kojto 122:f9eeca106725 2551
Kojto 122:f9eeca106725 2552 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
Kojto 122:f9eeca106725 2553
Kojto 122:f9eeca106725 2554 #if defined(TIM17)
Kojto 122:f9eeca106725 2555 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
Kojto 122:f9eeca106725 2556 #endif /* TIM17 */
Kojto 122:f9eeca106725 2557
Kojto 122:f9eeca106725 2558 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
Kojto 122:f9eeca106725 2559
Kojto 122:f9eeca106725 2560 #if defined(SAI2)
Kojto 122:f9eeca106725 2561 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
Kojto 122:f9eeca106725 2562 #endif /* SAI2 */
Kojto 122:f9eeca106725 2563
Kojto 122:f9eeca106725 2564 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 2565 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
Kojto 122:f9eeca106725 2566 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 2567
Kojto 122:f9eeca106725 2568 /**
Kojto 122:f9eeca106725 2569 * @}
Kojto 122:f9eeca106725 2570 */
Kojto 122:f9eeca106725 2571
Kojto 122:f9eeca106725 2572 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
Kojto 122:f9eeca106725 2573 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto 122:f9eeca106725 2574 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2575 * power consumption.
Kojto 122:f9eeca106725 2576 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2577 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2578 * @{
Kojto 122:f9eeca106725 2579 */
Kojto 122:f9eeca106725 2580
Kojto 122:f9eeca106725 2581 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
Kojto 122:f9eeca106725 2582
Kojto 122:f9eeca106725 2583 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
Kojto 122:f9eeca106725 2584
Kojto 122:f9eeca106725 2585 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
Kojto 122:f9eeca106725 2586
Kojto 122:f9eeca106725 2587 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
Kojto 122:f9eeca106725 2588
Kojto 122:f9eeca106725 2589 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
Kojto 122:f9eeca106725 2590
Kojto 122:f9eeca106725 2591 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
Kojto 122:f9eeca106725 2592
Kojto 122:f9eeca106725 2593
Kojto 122:f9eeca106725 2594 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
Kojto 122:f9eeca106725 2595
Kojto 122:f9eeca106725 2596 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
Kojto 122:f9eeca106725 2597
Kojto 122:f9eeca106725 2598 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
Kojto 122:f9eeca106725 2599
Kojto 122:f9eeca106725 2600 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
Kojto 122:f9eeca106725 2601
Kojto 122:f9eeca106725 2602 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
Kojto 122:f9eeca106725 2603
Kojto 122:f9eeca106725 2604 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
Kojto 122:f9eeca106725 2605
Kojto 122:f9eeca106725 2606 /**
Kojto 122:f9eeca106725 2607 * @}
Kojto 122:f9eeca106725 2608 */
Kojto 122:f9eeca106725 2609
Kojto 122:f9eeca106725 2610 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
Kojto 122:f9eeca106725 2611 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto 122:f9eeca106725 2612 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2613 * power consumption.
Kojto 122:f9eeca106725 2614 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2615 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2616 * @{
Kojto 122:f9eeca106725 2617 */
Kojto 122:f9eeca106725 2618
Kojto 122:f9eeca106725 2619 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
Kojto 122:f9eeca106725 2620
Kojto 122:f9eeca106725 2621 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
Kojto 122:f9eeca106725 2622
Kojto 122:f9eeca106725 2623 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
Kojto 122:f9eeca106725 2624
Kojto 122:f9eeca106725 2625 #if defined(GPIOD)
Kojto 122:f9eeca106725 2626 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
Kojto 122:f9eeca106725 2627 #endif /* GPIOD */
Kojto 122:f9eeca106725 2628
Kojto 122:f9eeca106725 2629 #if defined(GPIOE)
Kojto 122:f9eeca106725 2630 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
Kojto 122:f9eeca106725 2631 #endif /* GPIOE */
Kojto 122:f9eeca106725 2632
Kojto 122:f9eeca106725 2633 #if defined(GPIOF)
Kojto 122:f9eeca106725 2634 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
Kojto 122:f9eeca106725 2635 #endif /* GPIOF */
Kojto 122:f9eeca106725 2636
Kojto 122:f9eeca106725 2637 #if defined(GPIOG)
Kojto 122:f9eeca106725 2638 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
Kojto 122:f9eeca106725 2639 #endif /* GPIOG */
Kojto 122:f9eeca106725 2640
Kojto 122:f9eeca106725 2641 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
Kojto 122:f9eeca106725 2642
Kojto 122:f9eeca106725 2643 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
Kojto 122:f9eeca106725 2644
Kojto 122:f9eeca106725 2645 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 2646 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
Kojto 122:f9eeca106725 2647 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 2648
Kojto 122:f9eeca106725 2649 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
Kojto 122:f9eeca106725 2650
Kojto 122:f9eeca106725 2651 #if defined(AES)
Kojto 122:f9eeca106725 2652 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
Kojto 122:f9eeca106725 2653 #endif /* AES */
Kojto 122:f9eeca106725 2654
Kojto 122:f9eeca106725 2655 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
Kojto 122:f9eeca106725 2656
Kojto 122:f9eeca106725 2657
Kojto 122:f9eeca106725 2658 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
Kojto 122:f9eeca106725 2659
Kojto 122:f9eeca106725 2660 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
Kojto 122:f9eeca106725 2661
Kojto 122:f9eeca106725 2662 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
Kojto 122:f9eeca106725 2663
Kojto 122:f9eeca106725 2664 #if defined(GPIOD)
Kojto 122:f9eeca106725 2665 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
Kojto 122:f9eeca106725 2666 #endif /* GPIOD */
Kojto 122:f9eeca106725 2667
Kojto 122:f9eeca106725 2668 #if defined(GPIOE)
Kojto 122:f9eeca106725 2669 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
Kojto 122:f9eeca106725 2670 #endif /* GPIOE */
Kojto 122:f9eeca106725 2671
Kojto 122:f9eeca106725 2672 #if defined(GPIOF)
Kojto 122:f9eeca106725 2673 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
Kojto 122:f9eeca106725 2674 #endif /* GPIOF */
Kojto 122:f9eeca106725 2675
Kojto 122:f9eeca106725 2676 #if defined(GPIOG)
Kojto 122:f9eeca106725 2677 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
Kojto 122:f9eeca106725 2678 #endif /* GPIOG */
Kojto 122:f9eeca106725 2679
Kojto 122:f9eeca106725 2680 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
Kojto 122:f9eeca106725 2681
Kojto 122:f9eeca106725 2682 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
Kojto 122:f9eeca106725 2683
Kojto 122:f9eeca106725 2684 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 2685 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
Kojto 122:f9eeca106725 2686 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 2687
Kojto 122:f9eeca106725 2688 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
Kojto 122:f9eeca106725 2689
Kojto 122:f9eeca106725 2690 #if defined(AES)
Kojto 122:f9eeca106725 2691 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
Kojto 122:f9eeca106725 2692 #endif /* AES */
Kojto 122:f9eeca106725 2693
Kojto 122:f9eeca106725 2694 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
Kojto 122:f9eeca106725 2695
Kojto 122:f9eeca106725 2696 /**
Kojto 122:f9eeca106725 2697 * @}
Kojto 122:f9eeca106725 2698 */
Kojto 122:f9eeca106725 2699
Kojto 122:f9eeca106725 2700 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
Kojto 122:f9eeca106725 2701 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto 122:f9eeca106725 2702 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2703 * power consumption.
Kojto 122:f9eeca106725 2704 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2705 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2706 * @{
Kojto 122:f9eeca106725 2707 */
Kojto 122:f9eeca106725 2708
Kojto 122:f9eeca106725 2709 #if defined(QUADSPI)
Kojto 122:f9eeca106725 2710 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
Kojto 122:f9eeca106725 2711 #endif /* QUADSPI */
Kojto 122:f9eeca106725 2712
Kojto 122:f9eeca106725 2713 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 2714 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
Kojto 122:f9eeca106725 2715 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 2716
Kojto 122:f9eeca106725 2717 #if defined(QUADSPI)
Kojto 122:f9eeca106725 2718 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
Kojto 122:f9eeca106725 2719 #endif /* QUADSPI */
Kojto 122:f9eeca106725 2720
Kojto 122:f9eeca106725 2721 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 2722 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
Kojto 122:f9eeca106725 2723 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 2724
Kojto 122:f9eeca106725 2725 /**
Kojto 122:f9eeca106725 2726 * @}
Kojto 122:f9eeca106725 2727 */
Kojto 122:f9eeca106725 2728
Kojto 122:f9eeca106725 2729 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
Kojto 122:f9eeca106725 2730 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto 122:f9eeca106725 2731 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2732 * power consumption.
Kojto 122:f9eeca106725 2733 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2734 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2735 * @{
Kojto 122:f9eeca106725 2736 */
Kojto 122:f9eeca106725 2737
Kojto 122:f9eeca106725 2738 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
Kojto 122:f9eeca106725 2739
Kojto 122:f9eeca106725 2740 #if defined(TIM3)
Kojto 122:f9eeca106725 2741 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
Kojto 122:f9eeca106725 2742 #endif /* TIM3 */
Kojto 122:f9eeca106725 2743
Kojto 122:f9eeca106725 2744 #if defined(TIM4)
Kojto 122:f9eeca106725 2745 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
Kojto 122:f9eeca106725 2746 #endif /* TIM4 */
Kojto 122:f9eeca106725 2747
Kojto 122:f9eeca106725 2748 #if defined(TIM5)
Kojto 122:f9eeca106725 2749 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
Kojto 122:f9eeca106725 2750 #endif /* TIM5 */
Kojto 122:f9eeca106725 2751
Kojto 122:f9eeca106725 2752 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
Kojto 122:f9eeca106725 2753
Kojto 122:f9eeca106725 2754 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
Kojto 122:f9eeca106725 2755
Kojto 122:f9eeca106725 2756 #if defined(LCD)
Kojto 122:f9eeca106725 2757 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
Kojto 122:f9eeca106725 2758 #endif /* LCD */
Kojto 122:f9eeca106725 2759
Kojto 122:f9eeca106725 2760 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
Kojto 122:f9eeca106725 2761 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET)
Kojto 122:f9eeca106725 2762 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
Kojto 122:f9eeca106725 2763
Kojto 122:f9eeca106725 2764 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
Kojto 122:f9eeca106725 2765
Kojto 122:f9eeca106725 2766 #if defined(SPI2)
Kojto 122:f9eeca106725 2767 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
Kojto 122:f9eeca106725 2768 #endif /* SPI2 */
Kojto 122:f9eeca106725 2769
Kojto 122:f9eeca106725 2770 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
Kojto 122:f9eeca106725 2771
Kojto 122:f9eeca106725 2772 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
Kojto 122:f9eeca106725 2773
Kojto 122:f9eeca106725 2774 #if defined(USART3)
Kojto 122:f9eeca106725 2775 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
Kojto 122:f9eeca106725 2776 #endif /* USART3 */
Kojto 122:f9eeca106725 2777
Kojto 122:f9eeca106725 2778 #if defined(UART4)
Kojto 122:f9eeca106725 2779 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
Kojto 122:f9eeca106725 2780 #endif /* UART4 */
Kojto 122:f9eeca106725 2781
Kojto 122:f9eeca106725 2782 #if defined(UART5)
Kojto 122:f9eeca106725 2783 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
Kojto 122:f9eeca106725 2784 #endif /* UART5 */
Kojto 122:f9eeca106725 2785
Kojto 122:f9eeca106725 2786 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
Kojto 122:f9eeca106725 2787
Kojto 122:f9eeca106725 2788 #if defined(I2C2)
Kojto 122:f9eeca106725 2789 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
Kojto 122:f9eeca106725 2790 #endif /* I2C2 */
Kojto 122:f9eeca106725 2791
Kojto 122:f9eeca106725 2792 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
Kojto 122:f9eeca106725 2793
Kojto 122:f9eeca106725 2794 #if defined(CRS)
Kojto 122:f9eeca106725 2795 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET)
Kojto 122:f9eeca106725 2796 #endif /* CRS */
Kojto 122:f9eeca106725 2797
Kojto 122:f9eeca106725 2798 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
Kojto 122:f9eeca106725 2799
Kojto 122:f9eeca106725 2800 #if defined(USB)
Kojto 122:f9eeca106725 2801 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET)
Kojto 122:f9eeca106725 2802 #endif /* USB */
Kojto 122:f9eeca106725 2803
Kojto 122:f9eeca106725 2804 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
Kojto 122:f9eeca106725 2805
Kojto 122:f9eeca106725 2806 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
Kojto 122:f9eeca106725 2807
Kojto 122:f9eeca106725 2808 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
Kojto 122:f9eeca106725 2809
Kojto 122:f9eeca106725 2810 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
Kojto 122:f9eeca106725 2811
Kojto 122:f9eeca106725 2812 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
Kojto 122:f9eeca106725 2813
Kojto 122:f9eeca106725 2814 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
Kojto 122:f9eeca106725 2815
Kojto 122:f9eeca106725 2816 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
Kojto 122:f9eeca106725 2817
Kojto 122:f9eeca106725 2818
Kojto 122:f9eeca106725 2819 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
Kojto 122:f9eeca106725 2820
Kojto 122:f9eeca106725 2821 #if defined(TIM3)
Kojto 122:f9eeca106725 2822 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
Kojto 122:f9eeca106725 2823 #endif /* TIM3 */
Kojto 122:f9eeca106725 2824
Kojto 122:f9eeca106725 2825 #if defined(TIM4)
Kojto 122:f9eeca106725 2826 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
Kojto 122:f9eeca106725 2827 #endif /* TIM4 */
Kojto 122:f9eeca106725 2828
Kojto 122:f9eeca106725 2829 #if defined(TIM5)
Kojto 122:f9eeca106725 2830 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
Kojto 122:f9eeca106725 2831 #endif /* TIM5 */
Kojto 122:f9eeca106725 2832
Kojto 122:f9eeca106725 2833 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
Kojto 122:f9eeca106725 2834
Kojto 122:f9eeca106725 2835 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
Kojto 122:f9eeca106725 2836
Kojto 122:f9eeca106725 2837 #if defined(LCD)
Kojto 122:f9eeca106725 2838 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
Kojto 122:f9eeca106725 2839 #endif /* LCD */
Kojto 122:f9eeca106725 2840
Kojto 122:f9eeca106725 2841 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
Kojto 122:f9eeca106725 2842 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET)
Kojto 122:f9eeca106725 2843 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
Kojto 122:f9eeca106725 2844
Kojto 122:f9eeca106725 2845 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
Kojto 122:f9eeca106725 2846
Kojto 122:f9eeca106725 2847 #if defined(SPI2)
Kojto 122:f9eeca106725 2848 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
Kojto 122:f9eeca106725 2849 #endif /* SPI2 */
Kojto 122:f9eeca106725 2850
Kojto 122:f9eeca106725 2851 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
Kojto 122:f9eeca106725 2852
Kojto 122:f9eeca106725 2853 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
Kojto 122:f9eeca106725 2854
Kojto 122:f9eeca106725 2855 #if defined(USART3)
Kojto 122:f9eeca106725 2856 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
Kojto 122:f9eeca106725 2857 #endif /* USART3 */
Kojto 122:f9eeca106725 2858
Kojto 122:f9eeca106725 2859 #if defined(UART4)
Kojto 122:f9eeca106725 2860 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
Kojto 122:f9eeca106725 2861 #endif /* UART4 */
Kojto 122:f9eeca106725 2862
Kojto 122:f9eeca106725 2863 #if defined(UART5)
Kojto 122:f9eeca106725 2864 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
Kojto 122:f9eeca106725 2865 #endif /* UART5 */
Kojto 122:f9eeca106725 2866
Kojto 122:f9eeca106725 2867 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
Kojto 122:f9eeca106725 2868
Kojto 122:f9eeca106725 2869 #if defined(I2C2)
Kojto 122:f9eeca106725 2870 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
Kojto 122:f9eeca106725 2871 #endif /* I2C2 */
Kojto 122:f9eeca106725 2872
Kojto 122:f9eeca106725 2873 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
Kojto 122:f9eeca106725 2874
Kojto 122:f9eeca106725 2875 #if defined(CRS)
Kojto 122:f9eeca106725 2876 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET)
Kojto 122:f9eeca106725 2877 #endif /* CRS */
Kojto 122:f9eeca106725 2878
Kojto 122:f9eeca106725 2879 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
Kojto 122:f9eeca106725 2880
Kojto 122:f9eeca106725 2881 #if defined(USB)
Kojto 122:f9eeca106725 2882 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET)
Kojto 122:f9eeca106725 2883 #endif /* USB */
Kojto 122:f9eeca106725 2884
Kojto 122:f9eeca106725 2885 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
Kojto 122:f9eeca106725 2886
Kojto 122:f9eeca106725 2887 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
Kojto 122:f9eeca106725 2888
Kojto 122:f9eeca106725 2889 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
Kojto 122:f9eeca106725 2890
Kojto 122:f9eeca106725 2891 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
Kojto 122:f9eeca106725 2892
Kojto 122:f9eeca106725 2893 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
Kojto 122:f9eeca106725 2894
Kojto 122:f9eeca106725 2895 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
Kojto 122:f9eeca106725 2896
Kojto 122:f9eeca106725 2897 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
Kojto 122:f9eeca106725 2898
Kojto 122:f9eeca106725 2899 /**
Kojto 122:f9eeca106725 2900 * @}
Kojto 122:f9eeca106725 2901 */
Kojto 122:f9eeca106725 2902
Kojto 122:f9eeca106725 2903 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
Kojto 122:f9eeca106725 2904 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto 122:f9eeca106725 2905 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2906 * power consumption.
Kojto 122:f9eeca106725 2907 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2908 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2909 * @{
Kojto 122:f9eeca106725 2910 */
Kojto 122:f9eeca106725 2911
Kojto 122:f9eeca106725 2912 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
Kojto 122:f9eeca106725 2913
Kojto 122:f9eeca106725 2914 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
Kojto 122:f9eeca106725 2915 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
Kojto 122:f9eeca106725 2916 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
Kojto 122:f9eeca106725 2917
Kojto 122:f9eeca106725 2918 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
Kojto 122:f9eeca106725 2919
Kojto 122:f9eeca106725 2920 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
Kojto 122:f9eeca106725 2921
Kojto 122:f9eeca106725 2922 #if defined(TIM8)
Kojto 122:f9eeca106725 2923 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
Kojto 122:f9eeca106725 2924 #endif /* TIM8 */
Kojto 122:f9eeca106725 2925
Kojto 122:f9eeca106725 2926 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
Kojto 122:f9eeca106725 2927
Kojto 122:f9eeca106725 2928 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
Kojto 122:f9eeca106725 2929
Kojto 122:f9eeca106725 2930 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
Kojto 122:f9eeca106725 2931
Kojto 122:f9eeca106725 2932 #if defined(TIM17)
Kojto 122:f9eeca106725 2933 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
Kojto 122:f9eeca106725 2934 #endif /* TIM17 */
Kojto 122:f9eeca106725 2935
Kojto 122:f9eeca106725 2936 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
Kojto 122:f9eeca106725 2937
Kojto 122:f9eeca106725 2938 #if defined(SAI2)
Kojto 122:f9eeca106725 2939 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
Kojto 122:f9eeca106725 2940 #endif /* SAI2 */
Kojto 122:f9eeca106725 2941
Kojto 122:f9eeca106725 2942 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 2943 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET)
Kojto 122:f9eeca106725 2944 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 2945
Kojto 122:f9eeca106725 2946
Kojto 122:f9eeca106725 2947 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
Kojto 122:f9eeca106725 2948
Kojto 122:f9eeca106725 2949 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
Kojto 122:f9eeca106725 2950 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
Kojto 122:f9eeca106725 2951 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
Kojto 122:f9eeca106725 2952
Kojto 122:f9eeca106725 2953 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
Kojto 122:f9eeca106725 2954
Kojto 122:f9eeca106725 2955 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
Kojto 122:f9eeca106725 2956
Kojto 122:f9eeca106725 2957 #if defined(TIM8)
Kojto 122:f9eeca106725 2958 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
Kojto 122:f9eeca106725 2959 #endif /* TIM8 */
Kojto 122:f9eeca106725 2960
Kojto 122:f9eeca106725 2961 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
Kojto 122:f9eeca106725 2962
Kojto 122:f9eeca106725 2963 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
Kojto 122:f9eeca106725 2964
Kojto 122:f9eeca106725 2965 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
Kojto 122:f9eeca106725 2966
Kojto 122:f9eeca106725 2967 #if defined(TIM17)
Kojto 122:f9eeca106725 2968 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
Kojto 122:f9eeca106725 2969 #endif /* TIM17 */
Kojto 122:f9eeca106725 2970
Kojto 122:f9eeca106725 2971 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
Kojto 122:f9eeca106725 2972
Kojto 122:f9eeca106725 2973 #if defined(SAI2)
Kojto 122:f9eeca106725 2974 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
Kojto 122:f9eeca106725 2975 #endif /* SAI2 */
Kojto 122:f9eeca106725 2976
Kojto 122:f9eeca106725 2977 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 2978 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET)
Kojto 122:f9eeca106725 2979 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 2980
Kojto 122:f9eeca106725 2981 /**
Kojto 122:f9eeca106725 2982 * @}
Kojto 122:f9eeca106725 2983 */
Kojto 122:f9eeca106725 2984
Kojto 122:f9eeca106725 2985 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
Kojto 122:f9eeca106725 2986 * @{
Kojto 122:f9eeca106725 2987 */
Kojto 122:f9eeca106725 2988
Kojto 122:f9eeca106725 2989 /** @brief Macros to force or release the Backup domain reset.
Kojto 122:f9eeca106725 2990 * @note This function resets the RTC peripheral (including the backup registers)
Kojto 122:f9eeca106725 2991 * and the RTC clock source selection in RCC_CSR register.
Kojto 122:f9eeca106725 2992 * @note The BKPSRAM is not affected by this reset.
Kojto 122:f9eeca106725 2993 * @retval None
Kojto 122:f9eeca106725 2994 */
Kojto 122:f9eeca106725 2995 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto 122:f9eeca106725 2996
Kojto 122:f9eeca106725 2997 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto 122:f9eeca106725 2998
Kojto 122:f9eeca106725 2999 /**
Kojto 122:f9eeca106725 3000 * @}
Kojto 122:f9eeca106725 3001 */
Kojto 122:f9eeca106725 3002
Kojto 122:f9eeca106725 3003 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
Kojto 122:f9eeca106725 3004 * @{
Kojto 122:f9eeca106725 3005 */
Kojto 122:f9eeca106725 3006
Kojto 122:f9eeca106725 3007 /** @brief Macros to enable or disable the RTC clock.
Kojto 122:f9eeca106725 3008 * @note As the RTC is in the Backup domain and write access is denied to
Kojto 122:f9eeca106725 3009 * this domain after reset, you have to enable write access using
Kojto 122:f9eeca106725 3010 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC
Kojto 122:f9eeca106725 3011 * (to be done once after reset).
Kojto 122:f9eeca106725 3012 * @note These macros must be used after the RTC clock source was selected.
Kojto 122:f9eeca106725 3013 * @retval None
Kojto 122:f9eeca106725 3014 */
Kojto 122:f9eeca106725 3015 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto 122:f9eeca106725 3016
Kojto 122:f9eeca106725 3017 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto 122:f9eeca106725 3018
Kojto 122:f9eeca106725 3019 /**
Kojto 122:f9eeca106725 3020 * @}
Kojto 122:f9eeca106725 3021 */
Kojto 122:f9eeca106725 3022
Kojto 122:f9eeca106725 3023 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
Kojto 122:f9eeca106725 3024 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 3025 * It is used (enabled by hardware) as system clock source after startup
Kojto 122:f9eeca106725 3026 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto 122:f9eeca106725 3027 * of the HSE used directly or indirectly as system clock (if the Clock
Kojto 122:f9eeca106725 3028 * Security System CSS is enabled).
Kojto 122:f9eeca106725 3029 * @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto 122:f9eeca106725 3030 * you have to select another source of the system clock then stop the HSI.
Kojto 122:f9eeca106725 3031 * @note After enabling the HSI, the application software should wait on HSIRDY
Kojto 122:f9eeca106725 3032 * flag to be set indicating that HSI clock is stable and can be used as
Kojto 122:f9eeca106725 3033 * system clock source.
Kojto 122:f9eeca106725 3034 * This parameter can be: ENABLE or DISABLE.
Kojto 122:f9eeca106725 3035 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto 122:f9eeca106725 3036 * clock cycles.
Kojto 122:f9eeca106725 3037 * @retval None
Kojto 122:f9eeca106725 3038 */
Kojto 122:f9eeca106725 3039 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Kojto 122:f9eeca106725 3040
Kojto 122:f9eeca106725 3041 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
Kojto 122:f9eeca106725 3042
Kojto 122:f9eeca106725 3043 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
Kojto 122:f9eeca106725 3044 * @note The calibration is used to compensate for the variations in voltage
Kojto 122:f9eeca106725 3045 * and temperature that influence the frequency of the internal HSI RC.
Kojto 122:f9eeca106725 3046 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value
Kojto 122:f9eeca106725 3047 * (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 122:f9eeca106725 3048 * This parameter must be a number between 0 and 31.
Kojto 122:f9eeca106725 3049 * @retval None
Kojto 122:f9eeca106725 3050 */
Kojto 122:f9eeca106725 3051 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
Kojto 122:f9eeca106725 3052 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
Kojto 122:f9eeca106725 3053
Kojto 122:f9eeca106725 3054 /**
Kojto 122:f9eeca106725 3055 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
Kojto 122:f9eeca106725 3056 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
Kojto 122:f9eeca106725 3057 * @note The enable of this function has not effect on the HSION bit.
Kojto 122:f9eeca106725 3058 * This parameter can be: ENABLE or DISABLE.
Kojto 122:f9eeca106725 3059 * @retval None
Kojto 122:f9eeca106725 3060 */
Kojto 122:f9eeca106725 3061 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
Kojto 122:f9eeca106725 3062
Kojto 122:f9eeca106725 3063 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
Kojto 122:f9eeca106725 3064
Kojto 122:f9eeca106725 3065 /**
Kojto 122:f9eeca106725 3066 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
Kojto 122:f9eeca106725 3067 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
Kojto 122:f9eeca106725 3068 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
Kojto 122:f9eeca106725 3069 * speed because of the HSI startup time.
Kojto 122:f9eeca106725 3070 * @note The enable of this function has not effect on the HSION bit.
Kojto 122:f9eeca106725 3071 * This parameter can be: ENABLE or DISABLE.
Kojto 122:f9eeca106725 3072 * @retval None
Kojto 122:f9eeca106725 3073 */
Kojto 122:f9eeca106725 3074 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Kojto 122:f9eeca106725 3075
Kojto 122:f9eeca106725 3076 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
Kojto 122:f9eeca106725 3077
Kojto 122:f9eeca106725 3078 /**
Kojto 122:f9eeca106725 3079 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
Kojto 122:f9eeca106725 3080 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 3081 * It is used (enabled by hardware) as system clock source after
Kojto 122:f9eeca106725 3082 * startup from Reset, wakeup from STOP and STANDBY mode, or in case
Kojto 122:f9eeca106725 3083 * of failure of the HSE used directly or indirectly as system clock
Kojto 122:f9eeca106725 3084 * (if the Clock Security System CSS is enabled).
Kojto 122:f9eeca106725 3085 * @note MSI can not be stopped if it is used as system clock source.
Kojto 122:f9eeca106725 3086 * In this case, you have to select another source of the system
Kojto 122:f9eeca106725 3087 * clock then stop the MSI.
Kojto 122:f9eeca106725 3088 * @note After enabling the MSI, the application software should wait on
Kojto 122:f9eeca106725 3089 * MSIRDY flag to be set indicating that MSI clock is stable and can
Kojto 122:f9eeca106725 3090 * be used as system clock source.
Kojto 122:f9eeca106725 3091 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
Kojto 122:f9eeca106725 3092 * clock cycles.
Kojto 122:f9eeca106725 3093 * @retval None
Kojto 122:f9eeca106725 3094 */
Kojto 122:f9eeca106725 3095 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
Kojto 122:f9eeca106725 3096
Kojto 122:f9eeca106725 3097 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
Kojto 122:f9eeca106725 3098
Kojto 122:f9eeca106725 3099 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
Kojto 122:f9eeca106725 3100 * @note The calibration is used to compensate for the variations in voltage
Kojto 122:f9eeca106725 3101 * and temperature that influence the frequency of the internal MSI RC.
Kojto 122:f9eeca106725 3102 * Refer to the Application Note AN3300 for more details on how to
Kojto 122:f9eeca106725 3103 * calibrate the MSI.
Kojto 122:f9eeca106725 3104 * @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value
Kojto 122:f9eeca106725 3105 * (default is RCC_MSICALIBRATION_DEFAULT).
Kojto 122:f9eeca106725 3106 * This parameter must be a number between 0 and 255.
Kojto 122:f9eeca106725 3107 * @retval None
Kojto 122:f9eeca106725 3108 */
Kojto 122:f9eeca106725 3109 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
Kojto 122:f9eeca106725 3110 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
Kojto 122:f9eeca106725 3111
Kojto 122:f9eeca106725 3112 /**
Kojto 122:f9eeca106725 3113 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
Kojto 122:f9eeca106725 3114 * @note After restart from Reset , the MSI clock is around 4 MHz.
Kojto 122:f9eeca106725 3115 * After stop the startup clock can be MSI (at any of its possible
Kojto 122:f9eeca106725 3116 * frequencies, the one that was used before entering stop mode) or HSI.
Kojto 122:f9eeca106725 3117 * After Standby its frequency can be selected between 4 possible values
Kojto 122:f9eeca106725 3118 * (1, 2, 4 or 8 MHz).
Kojto 122:f9eeca106725 3119 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
Kojto 122:f9eeca106725 3120 * (MSIRDY=1).
Kojto 122:f9eeca106725 3121 * @note The MSI clock range after reset can be modified on the fly.
Kojto 122:f9eeca106725 3122 * @param __MSIRANGEVALUE__: specifies the MSI clock range.
Kojto 122:f9eeca106725 3123 * This parameter must be one of the following values:
Kojto 122:f9eeca106725 3124 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
Kojto 122:f9eeca106725 3125 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
Kojto 122:f9eeca106725 3126 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
Kojto 122:f9eeca106725 3127 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
Kojto 122:f9eeca106725 3128 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
Kojto 122:f9eeca106725 3129 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2MHz
Kojto 122:f9eeca106725 3130 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset)
Kojto 122:f9eeca106725 3131 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
Kojto 122:f9eeca106725 3132 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
Kojto 122:f9eeca106725 3133 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
Kojto 122:f9eeca106725 3134 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
Kojto 122:f9eeca106725 3135 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
Kojto 122:f9eeca106725 3136 * @retval None
Kojto 122:f9eeca106725 3137 */
Kojto 122:f9eeca106725 3138 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
Kojto 122:f9eeca106725 3139 do { \
Kojto 122:f9eeca106725 3140 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
Kojto 122:f9eeca106725 3141 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
Kojto 122:f9eeca106725 3142 } while(0)
Kojto 122:f9eeca106725 3143
Kojto 122:f9eeca106725 3144 /**
Kojto 122:f9eeca106725 3145 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
Kojto 122:f9eeca106725 3146 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
Kojto 122:f9eeca106725 3147 * @param __MSIRANGEVALUE__: specifies the MSI clock range.
Kojto 122:f9eeca106725 3148 * This parameter must be one of the following values:
Kojto 122:f9eeca106725 3149 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
Kojto 122:f9eeca106725 3150 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2MHz
Kojto 122:f9eeca106725 3151 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset)
Kojto 122:f9eeca106725 3152 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
Kojto 122:f9eeca106725 3153 * @retval None
Kojto 122:f9eeca106725 3154 */
Kojto 122:f9eeca106725 3155 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
Kojto 122:f9eeca106725 3156 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
Kojto 122:f9eeca106725 3157
Kojto 122:f9eeca106725 3158 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
Kojto 122:f9eeca106725 3159 * @retval MSI clock range.
Kojto 122:f9eeca106725 3160 * This parameter must be one of the following values:
Kojto 122:f9eeca106725 3161 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
Kojto 122:f9eeca106725 3162 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
Kojto 122:f9eeca106725 3163 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
Kojto 122:f9eeca106725 3164 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
Kojto 122:f9eeca106725 3165 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
Kojto 122:f9eeca106725 3166 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2MHz
Kojto 122:f9eeca106725 3167 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset)
Kojto 122:f9eeca106725 3168 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
Kojto 122:f9eeca106725 3169 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
Kojto 122:f9eeca106725 3170 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
Kojto 122:f9eeca106725 3171 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
Kojto 122:f9eeca106725 3172 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
Kojto 122:f9eeca106725 3173 */
Kojto 122:f9eeca106725 3174 #define __HAL_RCC_GET_MSI_RANGE() \
Kojto 122:f9eeca106725 3175 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \
Kojto 122:f9eeca106725 3176 (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \
Kojto 122:f9eeca106725 3177 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
Kojto 122:f9eeca106725 3178
Kojto 122:f9eeca106725 3179 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto 122:f9eeca106725 3180 * @note After enabling the LSI, the application software should wait on
Kojto 122:f9eeca106725 3181 * LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto 122:f9eeca106725 3182 * be used to clock the IWDG and/or the RTC.
Kojto 122:f9eeca106725 3183 * @note LSI can not be disabled if the IWDG is running.
Kojto 122:f9eeca106725 3184 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto 122:f9eeca106725 3185 * clock cycles.
Kojto 122:f9eeca106725 3186 * @retval None
Kojto 122:f9eeca106725 3187 */
Kojto 122:f9eeca106725 3188 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto 122:f9eeca106725 3189
Kojto 122:f9eeca106725 3190 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto 122:f9eeca106725 3191
Kojto 122:f9eeca106725 3192 /**
Kojto 122:f9eeca106725 3193 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 122:f9eeca106725 3194 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
Kojto 122:f9eeca106725 3195 * supported by this macro. User should request a transition to HSE Off
Kojto 122:f9eeca106725 3196 * first and then HSE On or HSE Bypass.
Kojto 122:f9eeca106725 3197 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto 122:f9eeca106725 3198 * software should wait on HSERDY flag to be set indicating that HSE clock
Kojto 122:f9eeca106725 3199 * is stable and can be used to clock the PLL and/or system clock.
Kojto 122:f9eeca106725 3200 * @note HSE state can not be changed if it is used directly or through the
Kojto 122:f9eeca106725 3201 * PLL as system clock. In this case, you have to select another source
Kojto 122:f9eeca106725 3202 * of the system clock then change the HSE state (ex. disable it).
Kojto 122:f9eeca106725 3203 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 3204 * @note This function reset the CSSON bit, so if the clock security system(CSS)
Kojto 122:f9eeca106725 3205 * was previously enabled you have to enable it again after calling this
Kojto 122:f9eeca106725 3206 * function.
Kojto 122:f9eeca106725 3207 * @param __STATE__: specifies the new state of the HSE.
Kojto 122:f9eeca106725 3208 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3209 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto 122:f9eeca106725 3210 * 6 HSE oscillator clock cycles.
Kojto 122:f9eeca106725 3211 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
Kojto 122:f9eeca106725 3212 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
Kojto 122:f9eeca106725 3213 * @retval None
Kojto 122:f9eeca106725 3214 */
Kojto 122:f9eeca106725 3215 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
Kojto 122:f9eeca106725 3216 do { \
Kojto 122:f9eeca106725 3217 if((__STATE__) == RCC_HSE_ON) \
Kojto 122:f9eeca106725 3218 { \
Kojto 122:f9eeca106725 3219 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 122:f9eeca106725 3220 } \
Kojto 122:f9eeca106725 3221 else if((__STATE__) == RCC_HSE_BYPASS) \
Kojto 122:f9eeca106725 3222 { \
Kojto 122:f9eeca106725 3223 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 122:f9eeca106725 3224 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 122:f9eeca106725 3225 } \
Kojto 122:f9eeca106725 3226 else \
Kojto 122:f9eeca106725 3227 { \
Kojto 122:f9eeca106725 3228 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 122:f9eeca106725 3229 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 122:f9eeca106725 3230 } \
Kojto 122:f9eeca106725 3231 } while(0)
Kojto 122:f9eeca106725 3232
Kojto 122:f9eeca106725 3233 /**
Kojto 122:f9eeca106725 3234 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 122:f9eeca106725 3235 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
Kojto 122:f9eeca106725 3236 * supported by this macro. User should request a transition to LSE Off
Kojto 122:f9eeca106725 3237 * first and then LSE On or LSE Bypass.
Kojto 122:f9eeca106725 3238 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 122:f9eeca106725 3239 * this domain after reset, you have to enable write access using
Kojto 122:f9eeca106725 3240 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 122:f9eeca106725 3241 * (to be done once after reset).
Kojto 122:f9eeca106725 3242 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto 122:f9eeca106725 3243 * software should wait on LSERDY flag to be set indicating that LSE clock
Kojto 122:f9eeca106725 3244 * is stable and can be used to clock the RTC.
Kojto 122:f9eeca106725 3245 * @param __STATE__: specifies the new state of the LSE.
Kojto 122:f9eeca106725 3246 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3247 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto 122:f9eeca106725 3248 * 6 LSE oscillator clock cycles.
Kojto 122:f9eeca106725 3249 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
Kojto 122:f9eeca106725 3250 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
Kojto 122:f9eeca106725 3251 * @retval None
Kojto 122:f9eeca106725 3252 */
Kojto 122:f9eeca106725 3253 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto 122:f9eeca106725 3254 do { \
Kojto 122:f9eeca106725 3255 if((__STATE__) == RCC_LSE_ON) \
Kojto 122:f9eeca106725 3256 { \
Kojto 122:f9eeca106725 3257 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 122:f9eeca106725 3258 } \
Kojto 122:f9eeca106725 3259 else if((__STATE__) == RCC_LSE_BYPASS) \
Kojto 122:f9eeca106725 3260 { \
Kojto 122:f9eeca106725 3261 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto 122:f9eeca106725 3262 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 122:f9eeca106725 3263 } \
Kojto 122:f9eeca106725 3264 else \
Kojto 122:f9eeca106725 3265 { \
Kojto 122:f9eeca106725 3266 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 122:f9eeca106725 3267 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto 122:f9eeca106725 3268 } \
Kojto 122:f9eeca106725 3269 } while(0)
Kojto 122:f9eeca106725 3270
Kojto 122:f9eeca106725 3271 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 3272
Kojto 122:f9eeca106725 3273 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
Kojto 122:f9eeca106725 3274 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 3275 * @note After enabling the HSI48, the application software should wait on HSI48RDY
Kojto 122:f9eeca106725 3276 * flag to be set indicating that HSI48 clock is stable.
Kojto 122:f9eeca106725 3277 * This parameter can be: ENABLE or DISABLE.
Kojto 122:f9eeca106725 3278 * @retval None
Kojto 122:f9eeca106725 3279 */
Kojto 122:f9eeca106725 3280 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
Kojto 122:f9eeca106725 3281
Kojto 122:f9eeca106725 3282 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
Kojto 122:f9eeca106725 3283
Kojto 122:f9eeca106725 3284 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 3285
Kojto 122:f9eeca106725 3286 /** @brief Macros to configure the RTC clock (RTCCLK).
Kojto 122:f9eeca106725 3287 * @note As the RTC clock configuration bits are in the Backup domain and write
Kojto 122:f9eeca106725 3288 * access is denied to this domain after reset, you have to enable write
Kojto 122:f9eeca106725 3289 * access using the Power Backup Access macro before to configure
Kojto 122:f9eeca106725 3290 * the RTC clock source (to be done once after reset).
Kojto 122:f9eeca106725 3291 * @note Once the RTC clock is configured it cannot be changed unless the
Kojto 122:f9eeca106725 3292 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
Kojto 122:f9eeca106725 3293 * a Power On Reset (POR).
Kojto 122:f9eeca106725 3294 *
Kojto 122:f9eeca106725 3295 * @param __RTC_CLKSOURCE__: specifies the RTC clock source.
Kojto 122:f9eeca106725 3296 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3297 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
Kojto 122:f9eeca106725 3298 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
Kojto 122:f9eeca106725 3299 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
Kojto 122:f9eeca106725 3300 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
Kojto 122:f9eeca106725 3301 *
Kojto 122:f9eeca106725 3302 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto 122:f9eeca106725 3303 * work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto 122:f9eeca106725 3304 * However, when the HSE clock is used as RTC clock source, the RTC
Kojto 122:f9eeca106725 3305 * cannot be used in STOP and STANDBY modes.
Kojto 122:f9eeca106725 3306 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto 122:f9eeca106725 3307 * RTC clock source).
Kojto 122:f9eeca106725 3308 * @retval None
Kojto 122:f9eeca106725 3309 */
Kojto 122:f9eeca106725 3310 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
Kojto 122:f9eeca106725 3311 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Kojto 122:f9eeca106725 3312
Kojto 122:f9eeca106725 3313
Kojto 122:f9eeca106725 3314 /** @brief Macro to get the RTC clock source.
Kojto 122:f9eeca106725 3315 * @retval The returned value can be one of the following:
Kojto 122:f9eeca106725 3316 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
Kojto 122:f9eeca106725 3317 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
Kojto 122:f9eeca106725 3318 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
Kojto 122:f9eeca106725 3319 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
Kojto 122:f9eeca106725 3320 */
Kojto 122:f9eeca106725 3321 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
Kojto 122:f9eeca106725 3322
Kojto 122:f9eeca106725 3323 /** @brief Macros to enable or disable the main PLL.
Kojto 122:f9eeca106725 3324 * @note After enabling the main PLL, the application software should wait on
Kojto 122:f9eeca106725 3325 * PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto 122:f9eeca106725 3326 * be used as system clock source.
Kojto 122:f9eeca106725 3327 * @note The main PLL can not be disabled if it is used as system clock source
Kojto 122:f9eeca106725 3328 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 3329 * @retval None
Kojto 122:f9eeca106725 3330 */
Kojto 122:f9eeca106725 3331 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Kojto 122:f9eeca106725 3332
Kojto 122:f9eeca106725 3333 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
Kojto 122:f9eeca106725 3334
Kojto 122:f9eeca106725 3335 /** @brief Macro to configure the PLL clock source.
Kojto 122:f9eeca106725 3336 * @note This function must be used only when the main PLL is disabled.
Kojto 122:f9eeca106725 3337 * @param __PLLSOURCE__: specifies the PLL entry clock source.
Kojto 122:f9eeca106725 3338 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3339 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
Kojto 122:f9eeca106725 3340 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 3341 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 3342 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 3343 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
Kojto 122:f9eeca106725 3344 * @retval None
Kojto 122:f9eeca106725 3345 *
Kojto 122:f9eeca106725 3346 */
Kojto 122:f9eeca106725 3347 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
Kojto 122:f9eeca106725 3348 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto 122:f9eeca106725 3349
Kojto 122:f9eeca106725 3350 /** @brief Macro to configure the PLL source division factor M.
Kojto 122:f9eeca106725 3351 * @note This function must be used only when the main PLL is disabled.
Kojto 122:f9eeca106725 3352 * @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto 122:f9eeca106725 3353 * This parameter must be a number between Min_Data = 1 and Max_Data = 8.
Kojto 122:f9eeca106725 3354 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 122:f9eeca106725 3355 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
Kojto 122:f9eeca106725 3356 * of 16 MHz to limit PLL jitter.
Kojto 122:f9eeca106725 3357 * @retval None
Kojto 122:f9eeca106725 3358 *
Kojto 122:f9eeca106725 3359 */
Kojto 122:f9eeca106725 3360 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
Kojto 122:f9eeca106725 3361 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
Kojto 122:f9eeca106725 3362
Kojto 122:f9eeca106725 3363 /**
Kojto 122:f9eeca106725 3364 * @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto 122:f9eeca106725 3365 * @note This function must be used only when the main PLL is disabled.
Kojto 122:f9eeca106725 3366 *
Kojto 122:f9eeca106725 3367 * @param __PLLSOURCE__: specifies the PLL entry clock source.
Kojto 122:f9eeca106725 3368 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3369 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
Kojto 122:f9eeca106725 3370 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 3371 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 3372 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 3373 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
Kojto 122:f9eeca106725 3374 *
Kojto 122:f9eeca106725 3375 * @param __PLLM__: specifies the division factor for PLL VCO input clock.
Kojto 122:f9eeca106725 3376 * This parameter must be a number between 1 and 8.
Kojto 122:f9eeca106725 3377 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 122:f9eeca106725 3378 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
Kojto 122:f9eeca106725 3379 * of 16 MHz to limit PLL jitter.
Kojto 122:f9eeca106725 3380 *
Kojto 122:f9eeca106725 3381 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock.
Kojto 122:f9eeca106725 3382 * This parameter must be a number between 8 and 86.
Kojto 122:f9eeca106725 3383 * @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto 122:f9eeca106725 3384 * output frequency is between 64 and 344 MHz.
Kojto 122:f9eeca106725 3385 *
Kojto 122:f9eeca106725 3386 * @param __PLLP__: specifies the division factor for SAI clock.
Kojto 122:f9eeca106725 3387 * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x
Kojto 122:f9eeca106725 3388 * else (2 to 31).
Kojto 122:f9eeca106725 3389 *
Kojto 122:f9eeca106725 3390 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
Kojto 122:f9eeca106725 3391 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 3392 * @note If the USB OTG FS is used in your application, you have to set the
Kojto 122:f9eeca106725 3393 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto 122:f9eeca106725 3394 * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
Kojto 122:f9eeca106725 3395 * correctly.
Kojto 122:f9eeca106725 3396 * @param __PLLR__: specifies the division factor for the main system clock.
Kojto 122:f9eeca106725 3397 * @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
Kojto 122:f9eeca106725 3398 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 3399 * @retval None
Kojto 122:f9eeca106725 3400 */
Kojto 122:f9eeca106725 3401 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 3402
Kojto 122:f9eeca106725 3403 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
Kojto 122:f9eeca106725 3404 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \
Kojto 122:f9eeca106725 3405 (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \
Kojto 122:f9eeca106725 3406 (uint32_t)((__PLLP__) << 27U))
Kojto 122:f9eeca106725 3407
Kojto 122:f9eeca106725 3408 #else
Kojto 122:f9eeca106725 3409
Kojto 122:f9eeca106725 3410 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
Kojto 122:f9eeca106725 3411 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \
Kojto 122:f9eeca106725 3412 (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U))
Kojto 122:f9eeca106725 3413
Kojto 122:f9eeca106725 3414 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 3415
Kojto 122:f9eeca106725 3416 /** @brief Macro to get the oscillator used as PLL clock source.
Kojto 122:f9eeca106725 3417 * @retval The oscillator used as PLL clock source. The returned value can be one
Kojto 122:f9eeca106725 3418 * of the following:
Kojto 122:f9eeca106725 3419 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
Kojto 122:f9eeca106725 3420 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
Kojto 122:f9eeca106725 3421 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto 122:f9eeca106725 3422 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto 122:f9eeca106725 3423 */
Kojto 122:f9eeca106725 3424 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto 122:f9eeca106725 3425
Kojto 122:f9eeca106725 3426 /**
Kojto 122:f9eeca106725 3427 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
Kojto 122:f9eeca106725 3428 * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
Kojto 122:f9eeca106725 3429 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
Kojto 122:f9eeca106725 3430 * be stopped if used as System Clock.
Kojto 122:f9eeca106725 3431 * @param __PLLCLOCKOUT__: specifies the PLL clock to be output.
Kojto 122:f9eeca106725 3432 * This parameter can be one or a combination of the following values:
Kojto 122:f9eeca106725 3433 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
Kojto 122:f9eeca106725 3434 * high-quality audio performance on SAI interface in case.
Kojto 122:f9eeca106725 3435 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
Kojto 122:f9eeca106725 3436 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
Kojto 122:f9eeca106725 3437 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
Kojto 122:f9eeca106725 3438 * @retval None
Kojto 122:f9eeca106725 3439 */
Kojto 122:f9eeca106725 3440 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Kojto 122:f9eeca106725 3441
Kojto 122:f9eeca106725 3442 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Kojto 122:f9eeca106725 3443
Kojto 122:f9eeca106725 3444 /**
Kojto 122:f9eeca106725 3445 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
Kojto 122:f9eeca106725 3446 * @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked.
Kojto 122:f9eeca106725 3447 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3448 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
Kojto 122:f9eeca106725 3449 * high-quality audio performance on SAI interface in case.
Kojto 122:f9eeca106725 3450 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
Kojto 122:f9eeca106725 3451 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
Kojto 122:f9eeca106725 3452 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
Kojto 122:f9eeca106725 3453 * @retval SET / RESET
Kojto 122:f9eeca106725 3454 */
Kojto 122:f9eeca106725 3455 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Kojto 122:f9eeca106725 3456
Kojto 122:f9eeca106725 3457 /**
Kojto 122:f9eeca106725 3458 * @brief Macro to configure the system clock source.
Kojto 122:f9eeca106725 3459 * @param __SYSCLKSOURCE__: specifies the system clock source.
Kojto 122:f9eeca106725 3460 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3461 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
Kojto 122:f9eeca106725 3462 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto 122:f9eeca106725 3463 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto 122:f9eeca106725 3464 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto 122:f9eeca106725 3465 * @retval None
Kojto 122:f9eeca106725 3466 */
Kojto 122:f9eeca106725 3467 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
Kojto 122:f9eeca106725 3468 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Kojto 122:f9eeca106725 3469
Kojto 122:f9eeca106725 3470 /** @brief Macro to get the clock source used as system clock.
Kojto 122:f9eeca106725 3471 * @retval The clock source used as system clock. The returned value can be one
Kojto 122:f9eeca106725 3472 * of the following:
Kojto 122:f9eeca106725 3473 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
Kojto 122:f9eeca106725 3474 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto 122:f9eeca106725 3475 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto 122:f9eeca106725 3476 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto 122:f9eeca106725 3477 */
Kojto 122:f9eeca106725 3478 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto 122:f9eeca106725 3479
Kojto 122:f9eeca106725 3480 /**
Kojto 122:f9eeca106725 3481 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
Kojto 122:f9eeca106725 3482 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 122:f9eeca106725 3483 * this domain after reset, you have to enable write access using
Kojto 122:f9eeca106725 3484 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 122:f9eeca106725 3485 * (to be done once after reset).
Kojto 122:f9eeca106725 3486 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
Kojto 122:f9eeca106725 3487 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3488 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
Kojto 122:f9eeca106725 3489 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
Kojto 122:f9eeca106725 3490 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
Kojto 122:f9eeca106725 3491 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
Kojto 122:f9eeca106725 3492 * @retval None
Kojto 122:f9eeca106725 3493 */
Kojto 122:f9eeca106725 3494 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
Kojto 122:f9eeca106725 3495 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
Kojto 122:f9eeca106725 3496
Kojto 122:f9eeca106725 3497 /**
Kojto 122:f9eeca106725 3498 * @brief Macro to configure the wake up from stop clock.
Kojto 122:f9eeca106725 3499 * @param __STOPWUCLK__: specifies the clock source used after wake up from stop.
Kojto 122:f9eeca106725 3500 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3501 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
Kojto 122:f9eeca106725 3502 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
Kojto 122:f9eeca106725 3503 * @retval None
Kojto 122:f9eeca106725 3504 */
Kojto 122:f9eeca106725 3505 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
Kojto 122:f9eeca106725 3506 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
Kojto 122:f9eeca106725 3507
Kojto 122:f9eeca106725 3508
Kojto 122:f9eeca106725 3509 /** @brief Macro to configure the MCO clock.
Kojto 122:f9eeca106725 3510 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 122:f9eeca106725 3511 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3512 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
Kojto 122:f9eeca106725 3513 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
Kojto 122:f9eeca106725 3514 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
Kojto 122:f9eeca106725 3515 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
Kojto 122:f9eeca106725 3516 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
Kojto 122:f9eeca106725 3517 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
Kojto 122:f9eeca106725 3518 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
Kojto 122:f9eeca106725 3519 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
Kojto 122:f9eeca106725 3520 @if STM32L443xx
Kojto 122:f9eeca106725 3521 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
Kojto 122:f9eeca106725 3522 @endif
Kojto 122:f9eeca106725 3523 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 122:f9eeca106725 3524 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3525 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
Kojto 122:f9eeca106725 3526 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
Kojto 122:f9eeca106725 3527 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
Kojto 122:f9eeca106725 3528 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
Kojto 122:f9eeca106725 3529 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
Kojto 122:f9eeca106725 3530 */
Kojto 122:f9eeca106725 3531 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 122:f9eeca106725 3532 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Kojto 122:f9eeca106725 3533
Kojto 122:f9eeca106725 3534 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto 122:f9eeca106725 3535 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 122:f9eeca106725 3536 * @{
Kojto 122:f9eeca106725 3537 */
Kojto 122:f9eeca106725 3538
Kojto 122:f9eeca106725 3539 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto 122:f9eeca106725 3540 * the selected interrupts).
Kojto 122:f9eeca106725 3541 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto 122:f9eeca106725 3542 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 3543 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Kojto 122:f9eeca106725 3544 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
Kojto 122:f9eeca106725 3545 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 3546 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 3547 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
Kojto 122:f9eeca106725 3548 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
Kojto 122:f9eeca106725 3549 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
Kojto 122:f9eeca106725 3550 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
Kojto 122:f9eeca106725 3551 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
Kojto 122:f9eeca106725 3552 @if STM32L443xx
Kojto 122:f9eeca106725 3553 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Kojto 122:f9eeca106725 3554 @endif
Kojto 122:f9eeca106725 3555 * @retval None
Kojto 122:f9eeca106725 3556 */
Kojto 122:f9eeca106725 3557 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Kojto 122:f9eeca106725 3558
Kojto 122:f9eeca106725 3559 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto 122:f9eeca106725 3560 * the selected interrupts).
Kojto 122:f9eeca106725 3561 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto 122:f9eeca106725 3562 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 3563 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Kojto 122:f9eeca106725 3564 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
Kojto 122:f9eeca106725 3565 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 3566 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 3567 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
Kojto 122:f9eeca106725 3568 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
Kojto 122:f9eeca106725 3569 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
Kojto 122:f9eeca106725 3570 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
Kojto 122:f9eeca106725 3571 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
Kojto 122:f9eeca106725 3572 @if STM32L443xx
Kojto 122:f9eeca106725 3573 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Kojto 122:f9eeca106725 3574 @endif
Kojto 122:f9eeca106725 3575 * @retval None
Kojto 122:f9eeca106725 3576 */
Kojto 122:f9eeca106725 3577 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Kojto 122:f9eeca106725 3578
Kojto 122:f9eeca106725 3579 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Kojto 122:f9eeca106725 3580 * bits to clear the selected interrupt pending bits.
Kojto 122:f9eeca106725 3581 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto 122:f9eeca106725 3582 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 3583 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Kojto 122:f9eeca106725 3584 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
Kojto 122:f9eeca106725 3585 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
Kojto 122:f9eeca106725 3586 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 3587 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
Kojto 122:f9eeca106725 3588 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
Kojto 122:f9eeca106725 3589 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
Kojto 122:f9eeca106725 3590 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
Kojto 122:f9eeca106725 3591 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
Kojto 122:f9eeca106725 3592 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
Kojto 122:f9eeca106725 3593 @if STM32L443xx
Kojto 122:f9eeca106725 3594 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Kojto 122:f9eeca106725 3595 @endif
Kojto 122:f9eeca106725 3596 * @retval None
Kojto 122:f9eeca106725 3597 */
Kojto 122:f9eeca106725 3598 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Kojto 122:f9eeca106725 3599
Kojto 122:f9eeca106725 3600 /** @brief Check whether the RCC interrupt has occurred or not.
Kojto 122:f9eeca106725 3601 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto 122:f9eeca106725 3602 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3603 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Kojto 122:f9eeca106725 3604 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
Kojto 122:f9eeca106725 3605 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
Kojto 122:f9eeca106725 3606 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 3607 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
Kojto 122:f9eeca106725 3608 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
Kojto 122:f9eeca106725 3609 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
Kojto 122:f9eeca106725 3610 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
Kojto 122:f9eeca106725 3611 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
Kojto 122:f9eeca106725 3612 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
Kojto 122:f9eeca106725 3613 @if STM32L443xx
Kojto 122:f9eeca106725 3614 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Kojto 122:f9eeca106725 3615 @endif
Kojto 122:f9eeca106725 3616 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto 122:f9eeca106725 3617 */
Kojto 122:f9eeca106725 3618 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto 122:f9eeca106725 3619
Kojto 122:f9eeca106725 3620 /** @brief Set RMVF bit to clear the reset flags.
Kojto 122:f9eeca106725 3621 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
Kojto 122:f9eeca106725 3622 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
Kojto 122:f9eeca106725 3623 * @retval None
Kojto 122:f9eeca106725 3624 */
Kojto 122:f9eeca106725 3625 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Kojto 122:f9eeca106725 3626
Kojto 122:f9eeca106725 3627 /** @brief Check whether the selected RCC flag is set or not.
Kojto 122:f9eeca106725 3628 * @param __FLAG__: specifies the flag to check.
Kojto 122:f9eeca106725 3629 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3630 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
Kojto 122:f9eeca106725 3631 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
Kojto 122:f9eeca106725 3632 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
Kojto 122:f9eeca106725 3633 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
Kojto 122:f9eeca106725 3634 * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready
Kojto 122:f9eeca106725 3635 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2
Kojto 122:f9eeca106725 3636 @if STM32L443xx
Kojto 122:f9eeca106725 3637 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
Kojto 122:f9eeca106725 3638 @endif
Kojto 122:f9eeca106725 3639 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
Kojto 122:f9eeca106725 3640 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
Kojto 122:f9eeca106725 3641 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
Kojto 122:f9eeca106725 3642 * @arg @ref RCC_FLAG_BORRST BOR reset
Kojto 122:f9eeca106725 3643 * @arg @ref RCC_FLAG_OBLRST OBLRST reset
Kojto 122:f9eeca106725 3644 * @arg @ref RCC_FLAG_PINRST Pin reset
Kojto 122:f9eeca106725 3645 * @arg @ref RCC_FLAG_FWRST FIREWALL reset
Kojto 122:f9eeca106725 3646 * @arg @ref RCC_FLAG_RMVF Remove reset Flag
Kojto 122:f9eeca106725 3647 * @arg @ref RCC_FLAG_SFTRST Software reset
Kojto 122:f9eeca106725 3648 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
Kojto 122:f9eeca106725 3649 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
Kojto 122:f9eeca106725 3650 * @arg @ref RCC_FLAG_LPWRRST Low Power reset
Kojto 122:f9eeca106725 3651 * @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto 122:f9eeca106725 3652 */
Kojto 122:f9eeca106725 3653 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 3654 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
Kojto 122:f9eeca106725 3655 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
Kojto 122:f9eeca106725 3656 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
Kojto 122:f9eeca106725 3657 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
Kojto 122:f9eeca106725 3658 ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
Kojto 122:f9eeca106725 3659 ? 1U : 0U)
Kojto 122:f9eeca106725 3660 #else
Kojto 122:f9eeca106725 3661 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
Kojto 122:f9eeca106725 3662 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
Kojto 122:f9eeca106725 3663 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
Kojto 122:f9eeca106725 3664 ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
Kojto 122:f9eeca106725 3665 ? 1U : 0U)
Kojto 122:f9eeca106725 3666 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 3667
Kojto 122:f9eeca106725 3668 /**
Kojto 122:f9eeca106725 3669 * @}
Kojto 122:f9eeca106725 3670 */
Kojto 122:f9eeca106725 3671
Kojto 122:f9eeca106725 3672 /**
Kojto 122:f9eeca106725 3673 * @}
Kojto 122:f9eeca106725 3674 */
Kojto 122:f9eeca106725 3675
Kojto 122:f9eeca106725 3676 /* Private constants ---------------------------------------------------------*/
Kojto 122:f9eeca106725 3677 /** @defgroup RCC_Private_Constants RCC Private Constants
Kojto 122:f9eeca106725 3678 * @{
Kojto 122:f9eeca106725 3679 */
Kojto 122:f9eeca106725 3680 /* Defines used for Flags */
Kojto 122:f9eeca106725 3681 #define CR_REG_INDEX ((uint32_t)1U)
Kojto 122:f9eeca106725 3682 #define BDCR_REG_INDEX ((uint32_t)2U)
Kojto 122:f9eeca106725 3683 #define CSR_REG_INDEX ((uint32_t)3U)
Kojto 122:f9eeca106725 3684 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 3685 #define CRRCR_REG_INDEX ((uint32_t)4U)
Kojto 122:f9eeca106725 3686 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 3687
Kojto 122:f9eeca106725 3688 #define RCC_FLAG_MASK ((uint32_t)0x1FU)
Kojto 122:f9eeca106725 3689 /**
Kojto 122:f9eeca106725 3690 * @}
Kojto 122:f9eeca106725 3691 */
Kojto 122:f9eeca106725 3692
Kojto 122:f9eeca106725 3693 /* Private macros ------------------------------------------------------------*/
Kojto 122:f9eeca106725 3694 /** @addtogroup RCC_Private_Macros
Kojto 122:f9eeca106725 3695 * @{
Kojto 122:f9eeca106725 3696 */
Kojto 122:f9eeca106725 3697
Kojto 122:f9eeca106725 3698 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 3699 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
Kojto 122:f9eeca106725 3700 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
Kojto 122:f9eeca106725 3701 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
Kojto 122:f9eeca106725 3702 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
Kojto 122:f9eeca106725 3703 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
Kojto 122:f9eeca106725 3704 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
Kojto 122:f9eeca106725 3705 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
Kojto 122:f9eeca106725 3706 #else
Kojto 122:f9eeca106725 3707 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
Kojto 122:f9eeca106725 3708 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
Kojto 122:f9eeca106725 3709 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
Kojto 122:f9eeca106725 3710 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
Kojto 122:f9eeca106725 3711 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
Kojto 122:f9eeca106725 3712 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
Kojto 122:f9eeca106725 3713 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 3714
Kojto 122:f9eeca106725 3715 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
Kojto 122:f9eeca106725 3716 ((__HSE__) == RCC_HSE_BYPASS))
Kojto 122:f9eeca106725 3717
Kojto 122:f9eeca106725 3718 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
Kojto 122:f9eeca106725 3719 ((__LSE__) == RCC_LSE_BYPASS))
Kojto 122:f9eeca106725 3720
Kojto 122:f9eeca106725 3721 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
Kojto 122:f9eeca106725 3722
Kojto 122:f9eeca106725 3723 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)31U)
Kojto 122:f9eeca106725 3724
Kojto 122:f9eeca106725 3725 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
Kojto 122:f9eeca106725 3726
Kojto 122:f9eeca106725 3727 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
Kojto 122:f9eeca106725 3728
Kojto 122:f9eeca106725 3729 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
Kojto 122:f9eeca106725 3730
Kojto 122:f9eeca106725 3731 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 3732 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
Kojto 122:f9eeca106725 3733 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 3734
Kojto 122:f9eeca106725 3735 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
Kojto 122:f9eeca106725 3736 ((__PLL__) == RCC_PLL_ON))
Kojto 122:f9eeca106725 3737
Kojto 122:f9eeca106725 3738 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
Kojto 122:f9eeca106725 3739 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \
Kojto 122:f9eeca106725 3740 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
Kojto 122:f9eeca106725 3741 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
Kojto 122:f9eeca106725 3742
Kojto 122:f9eeca106725 3743 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
Kojto 122:f9eeca106725 3744
Kojto 122:f9eeca106725 3745 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
Kojto 122:f9eeca106725 3746
Kojto 122:f9eeca106725 3747 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 3748 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
Kojto 122:f9eeca106725 3749 #else
Kojto 122:f9eeca106725 3750 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
Kojto 122:f9eeca106725 3751 #endif /*RCC_PLLP_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 3752
Kojto 122:f9eeca106725 3753 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
Kojto 122:f9eeca106725 3754 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
Kojto 122:f9eeca106725 3755
Kojto 122:f9eeca106725 3756 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
Kojto 122:f9eeca106725 3757 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
Kojto 122:f9eeca106725 3758
Kojto 122:f9eeca106725 3759 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \
Kojto 122:f9eeca106725 3760 (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \
Kojto 122:f9eeca106725 3761 (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
Kojto 122:f9eeca106725 3762 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))
Kojto 122:f9eeca106725 3763
Kojto 122:f9eeca106725 3764 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 3765 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \
Kojto 122:f9eeca106725 3766 (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
Kojto 122:f9eeca106725 3767 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))
Kojto 122:f9eeca106725 3768 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 3769
Kojto 122:f9eeca106725 3770 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
Kojto 122:f9eeca106725 3771 ((__RANGE__) == RCC_MSIRANGE_1) || \
Kojto 122:f9eeca106725 3772 ((__RANGE__) == RCC_MSIRANGE_2) || \
Kojto 122:f9eeca106725 3773 ((__RANGE__) == RCC_MSIRANGE_3) || \
Kojto 122:f9eeca106725 3774 ((__RANGE__) == RCC_MSIRANGE_4) || \
Kojto 122:f9eeca106725 3775 ((__RANGE__) == RCC_MSIRANGE_5) || \
Kojto 122:f9eeca106725 3776 ((__RANGE__) == RCC_MSIRANGE_6) || \
Kojto 122:f9eeca106725 3777 ((__RANGE__) == RCC_MSIRANGE_7) || \
Kojto 122:f9eeca106725 3778 ((__RANGE__) == RCC_MSIRANGE_8) || \
Kojto 122:f9eeca106725 3779 ((__RANGE__) == RCC_MSIRANGE_9) || \
Kojto 122:f9eeca106725 3780 ((__RANGE__) == RCC_MSIRANGE_10) || \
Kojto 122:f9eeca106725 3781 ((__RANGE__) == RCC_MSIRANGE_11))
Kojto 122:f9eeca106725 3782
Kojto 122:f9eeca106725 3783 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \
Kojto 122:f9eeca106725 3784 ((__RANGE__) == RCC_MSIRANGE_5) || \
Kojto 122:f9eeca106725 3785 ((__RANGE__) == RCC_MSIRANGE_6) || \
Kojto 122:f9eeca106725 3786 ((__RANGE__) == RCC_MSIRANGE_7))
Kojto 122:f9eeca106725 3787
Kojto 122:f9eeca106725 3788 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
Kojto 122:f9eeca106725 3789
Kojto 122:f9eeca106725 3790 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
Kojto 122:f9eeca106725 3791 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 122:f9eeca106725 3792 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 122:f9eeca106725 3793 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto 122:f9eeca106725 3794
Kojto 122:f9eeca106725 3795 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
Kojto 122:f9eeca106725 3796 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
Kojto 122:f9eeca106725 3797 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
Kojto 122:f9eeca106725 3798 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
Kojto 122:f9eeca106725 3799 ((__HCLK__) == RCC_SYSCLK_DIV512))
Kojto 122:f9eeca106725 3800
Kojto 122:f9eeca106725 3801 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
Kojto 122:f9eeca106725 3802 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
Kojto 122:f9eeca106725 3803 ((__PCLK__) == RCC_HCLK_DIV16))
Kojto 122:f9eeca106725 3804
Kojto 122:f9eeca106725 3805 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
Kojto 122:f9eeca106725 3806 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 3807 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
Kojto 122:f9eeca106725 3808 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
Kojto 122:f9eeca106725 3809
Kojto 122:f9eeca106725 3810 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
Kojto 122:f9eeca106725 3811
Kojto 122:f9eeca106725 3812 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 3813 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
Kojto 122:f9eeca106725 3814 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 3815 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
Kojto 122:f9eeca106725 3816 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
Kojto 122:f9eeca106725 3817 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
Kojto 122:f9eeca106725 3818 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
Kojto 122:f9eeca106725 3819 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
Kojto 122:f9eeca106725 3820 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
Kojto 122:f9eeca106725 3821 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
Kojto 122:f9eeca106725 3822 #else
Kojto 122:f9eeca106725 3823 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
Kojto 122:f9eeca106725 3824 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 3825 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
Kojto 122:f9eeca106725 3826 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
Kojto 122:f9eeca106725 3827 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
Kojto 122:f9eeca106725 3828 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
Kojto 122:f9eeca106725 3829 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
Kojto 122:f9eeca106725 3830 ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
Kojto 122:f9eeca106725 3831 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 3832
Kojto 122:f9eeca106725 3833 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
Kojto 122:f9eeca106725 3834 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
Kojto 122:f9eeca106725 3835 ((__DIV__) == RCC_MCODIV_16))
Kojto 122:f9eeca106725 3836
Kojto 122:f9eeca106725 3837 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
Kojto 122:f9eeca106725 3838 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
Kojto 122:f9eeca106725 3839 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
Kojto 122:f9eeca106725 3840 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
Kojto 122:f9eeca106725 3841
Kojto 122:f9eeca106725 3842 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
Kojto 122:f9eeca106725 3843 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
Kojto 122:f9eeca106725 3844 /**
Kojto 122:f9eeca106725 3845 * @}
Kojto 122:f9eeca106725 3846 */
Kojto 122:f9eeca106725 3847
Kojto 122:f9eeca106725 3848 /* Include RCC HAL Extended module */
Kojto 122:f9eeca106725 3849 #include "stm32l4xx_hal_rcc_ex.h"
Kojto 122:f9eeca106725 3850
Kojto 122:f9eeca106725 3851 /* Exported functions --------------------------------------------------------*/
Kojto 122:f9eeca106725 3852 /** @addtogroup RCC_Exported_Functions
Kojto 122:f9eeca106725 3853 * @{
Kojto 122:f9eeca106725 3854 */
Kojto 122:f9eeca106725 3855
Kojto 122:f9eeca106725 3856
Kojto 122:f9eeca106725 3857 /** @addtogroup RCC_Exported_Functions_Group1
Kojto 122:f9eeca106725 3858 * @{
Kojto 122:f9eeca106725 3859 */
Kojto 122:f9eeca106725 3860
Kojto 122:f9eeca106725 3861 /* Initialization and de-initialization functions ******************************/
Kojto 122:f9eeca106725 3862 void HAL_RCC_DeInit(void);
Kojto 122:f9eeca106725 3863 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 122:f9eeca106725 3864 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 122:f9eeca106725 3865
Kojto 122:f9eeca106725 3866 /**
Kojto 122:f9eeca106725 3867 * @}
Kojto 122:f9eeca106725 3868 */
Kojto 122:f9eeca106725 3869
Kojto 122:f9eeca106725 3870 /** @addtogroup RCC_Exported_Functions_Group2
Kojto 122:f9eeca106725 3871 * @{
Kojto 122:f9eeca106725 3872 */
Kojto 122:f9eeca106725 3873
Kojto 122:f9eeca106725 3874 /* Peripheral Control functions ************************************************/
Kojto 122:f9eeca106725 3875 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto 122:f9eeca106725 3876 void HAL_RCC_EnableCSS(void);
Kojto 122:f9eeca106725 3877 uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto 122:f9eeca106725 3878 uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto 122:f9eeca106725 3879 uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto 122:f9eeca106725 3880 uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto 122:f9eeca106725 3881 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 122:f9eeca106725 3882 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
Kojto 122:f9eeca106725 3883 /* CSS NMI IRQ handler */
Kojto 122:f9eeca106725 3884 void HAL_RCC_NMI_IRQHandler(void);
Kojto 122:f9eeca106725 3885 /* User Callbacks in non blocking mode (IT mode) */
Kojto 122:f9eeca106725 3886 void HAL_RCC_CSSCallback(void);
Kojto 122:f9eeca106725 3887
Kojto 122:f9eeca106725 3888 /**
Kojto 122:f9eeca106725 3889 * @}
Kojto 122:f9eeca106725 3890 */
Kojto 122:f9eeca106725 3891
Kojto 122:f9eeca106725 3892 /**
Kojto 122:f9eeca106725 3893 * @}
Kojto 122:f9eeca106725 3894 */
Kojto 122:f9eeca106725 3895
Kojto 122:f9eeca106725 3896 /**
Kojto 122:f9eeca106725 3897 * @}
Kojto 122:f9eeca106725 3898 */
Kojto 122:f9eeca106725 3899
Kojto 122:f9eeca106725 3900 /**
Kojto 122:f9eeca106725 3901 * @}
Kojto 122:f9eeca106725 3902 */
Kojto 122:f9eeca106725 3903
Kojto 122:f9eeca106725 3904 #ifdef __cplusplus
Kojto 122:f9eeca106725 3905 }
Kojto 122:f9eeca106725 3906 #endif
Kojto 122:f9eeca106725 3907
Kojto 122:f9eeca106725 3908 #endif /* __STM32L4xx_HAL_RCC_H */
Kojto 122:f9eeca106725 3909
Kojto 122:f9eeca106725 3910 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/