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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h@145:64910690c574, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:31:38 2017 +0100
Revision:
145:64910690c574
Parent:
128:9bcdf88f62b0 
Release 145 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**
Kojto 122:f9eeca106725 2 ******************************************************************************
Kojto 122:f9eeca106725 3 * @file stm32l4xx_hal_rcc.h
Kojto 122:f9eeca106725 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @version V1.7.1
AnnaBridge 145:64910690c574 6 * @date 21-April-2017
Kojto 122:f9eeca106725 7 * @brief Header file of RCC HAL module.
Kojto 122:f9eeca106725 8 ******************************************************************************
Kojto 122:f9eeca106725 9 * @attention
Kojto 122:f9eeca106725 10 *
AnnaBridge 145:64910690c574 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
Kojto 122:f9eeca106725 12 *
Kojto 122:f9eeca106725 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 14 * are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 122:f9eeca106725 16 * this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 122:f9eeca106725 18 * this list of conditions and the following disclaimer in the documentation
Kojto 122:f9eeca106725 19 * and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 122:f9eeca106725 21 * may be used to endorse or promote products derived from this software
Kojto 122:f9eeca106725 22 * without specific prior written permission.
Kojto 122:f9eeca106725 23 *
Kojto 122:f9eeca106725 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 122:f9eeca106725 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 122:f9eeca106725 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 122:f9eeca106725 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 122:f9eeca106725 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 122:f9eeca106725 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 122:f9eeca106725 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 34 *
Kojto 122:f9eeca106725 35 ******************************************************************************
Kojto 122:f9eeca106725 36 */
Kojto 122:f9eeca106725 37
Kojto 122:f9eeca106725 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 122:f9eeca106725 39 #ifndef __STM32L4xx_HAL_RCC_H
Kojto 122:f9eeca106725 40 #define __STM32L4xx_HAL_RCC_H
Kojto 122:f9eeca106725 41
Kojto 122:f9eeca106725 42 #ifdef __cplusplus
Kojto 122:f9eeca106725 43 extern "C" {
Kojto 122:f9eeca106725 44 #endif
Kojto 122:f9eeca106725 45
Kojto 122:f9eeca106725 46 /* Includes ------------------------------------------------------------------*/
Kojto 122:f9eeca106725 47 #include "stm32l4xx_hal_def.h"
Kojto 122:f9eeca106725 48
Kojto 122:f9eeca106725 49 /** @addtogroup STM32L4xx_HAL_Driver
Kojto 122:f9eeca106725 50 * @{
Kojto 122:f9eeca106725 51 */
Kojto 122:f9eeca106725 52
Kojto 122:f9eeca106725 53 /** @addtogroup RCC
Kojto 122:f9eeca106725 54 * @{
Kojto 122:f9eeca106725 55 */
Kojto 122:f9eeca106725 56
Kojto 122:f9eeca106725 57 /* Exported types ------------------------------------------------------------*/
Kojto 122:f9eeca106725 58 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 122:f9eeca106725 59 * @{
Kojto 122:f9eeca106725 60 */
Kojto 122:f9eeca106725 61
Kojto 122:f9eeca106725 62 /**
Kojto 122:f9eeca106725 63 * @brief RCC PLL configuration structure definition
Kojto 122:f9eeca106725 64 */
Kojto 122:f9eeca106725 65 typedef struct
Kojto 122:f9eeca106725 66 {
Kojto 122:f9eeca106725 67 uint32_t PLLState; /*!< The new state of the PLL.
Kojto 122:f9eeca106725 68 This parameter can be a value of @ref RCC_PLL_Config */
Kojto 122:f9eeca106725 69
Kojto 122:f9eeca106725 70 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto 122:f9eeca106725 71 This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto 122:f9eeca106725 72
Kojto 122:f9eeca106725 73 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto 122:f9eeca106725 74 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
Kojto 122:f9eeca106725 75
Kojto 122:f9eeca106725 76 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto 122:f9eeca106725 77 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
Kojto 122:f9eeca106725 78
Kojto 122:f9eeca106725 79 uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.
Kojto 122:f9eeca106725 80 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto 122:f9eeca106725 81
Kojto 122:f9eeca106725 82 uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
Kojto 122:f9eeca106725 83 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
Kojto 122:f9eeca106725 84
Kojto 122:f9eeca106725 85 uint32_t PLLR; /*!< PLLR: Division for the main system clock.
Kojto 122:f9eeca106725 86 User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
Kojto 122:f9eeca106725 87 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
Kojto 122:f9eeca106725 88
Kojto 122:f9eeca106725 89 }RCC_PLLInitTypeDef;
Kojto 122:f9eeca106725 90
Kojto 122:f9eeca106725 91 /**
Kojto 122:f9eeca106725 92 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
Kojto 122:f9eeca106725 93 */
Kojto 122:f9eeca106725 94 typedef struct
Kojto 122:f9eeca106725 95 {
Kojto 122:f9eeca106725 96 uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto 122:f9eeca106725 97 This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto 122:f9eeca106725 98
Kojto 122:f9eeca106725 99 uint32_t HSEState; /*!< The new state of the HSE.
Kojto 122:f9eeca106725 100 This parameter can be a value of @ref RCC_HSE_Config */
Kojto 122:f9eeca106725 101
Kojto 122:f9eeca106725 102 uint32_t LSEState; /*!< The new state of the LSE.
Kojto 122:f9eeca106725 103 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 122:f9eeca106725 104
Kojto 122:f9eeca106725 105 uint32_t HSIState; /*!< The new state of the HSI.
Kojto 122:f9eeca106725 106 This parameter can be a value of @ref RCC_HSI_Config */
Kojto 122:f9eeca106725 107
Kojto 122:f9eeca106725 108 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge 145:64910690c574 109 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices.
AnnaBridge 145:64910690c574 110 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */
Kojto 122:f9eeca106725 111
Kojto 122:f9eeca106725 112 uint32_t LSIState; /*!< The new state of the LSI.
Kojto 122:f9eeca106725 113 This parameter can be a value of @ref RCC_LSI_Config */
Kojto 122:f9eeca106725 114
Kojto 122:f9eeca106725 115 uint32_t MSIState; /*!< The new state of the MSI.
Kojto 122:f9eeca106725 116 This parameter can be a value of @ref RCC_MSI_Config */
Kojto 122:f9eeca106725 117
Kojto 122:f9eeca106725 118 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
Kojto 122:f9eeca106725 119 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
Kojto 122:f9eeca106725 120
Kojto 122:f9eeca106725 121 uint32_t MSIClockRange; /*!< The MSI frequency range.
Kojto 122:f9eeca106725 122 This parameter can be a value of @ref RCC_MSI_Clock_Range */
Kojto 122:f9eeca106725 123
AnnaBridge 145:64910690c574 124 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L45x/STM32L46x/STM32L49x/STM32L4Ax devices).
Kojto 122:f9eeca106725 125 This parameter can be a value of @ref RCC_HSI48_Config */
Kojto 122:f9eeca106725 126
Kojto 122:f9eeca106725 127 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
Kojto 122:f9eeca106725 128
Kojto 122:f9eeca106725 129 }RCC_OscInitTypeDef;
Kojto 122:f9eeca106725 130
Kojto 122:f9eeca106725 131 /**
Kojto 122:f9eeca106725 132 * @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto 122:f9eeca106725 133 */
Kojto 122:f9eeca106725 134 typedef struct
Kojto 122:f9eeca106725 135 {
Kojto 122:f9eeca106725 136 uint32_t ClockType; /*!< The clock to be configured.
Kojto 122:f9eeca106725 137 This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto 122:f9eeca106725 138
Kojto 122:f9eeca106725 139 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
Kojto 122:f9eeca106725 140 This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto 122:f9eeca106725 141
Kojto 122:f9eeca106725 142 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto 122:f9eeca106725 143 This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto 122:f9eeca106725 144
Kojto 122:f9eeca106725 145 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto 122:f9eeca106725 146 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 122:f9eeca106725 147
Kojto 122:f9eeca106725 148 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto 122:f9eeca106725 149 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 122:f9eeca106725 150
Kojto 122:f9eeca106725 151 }RCC_ClkInitTypeDef;
Kojto 122:f9eeca106725 152
Kojto 122:f9eeca106725 153 /**
Kojto 122:f9eeca106725 154 * @}
Kojto 122:f9eeca106725 155 */
Kojto 122:f9eeca106725 156
Kojto 122:f9eeca106725 157 /* Exported constants --------------------------------------------------------*/
Kojto 122:f9eeca106725 158 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 122:f9eeca106725 159 * @{
Kojto 122:f9eeca106725 160 */
Kojto 122:f9eeca106725 161
Kojto 122:f9eeca106725 162 /** @defgroup RCC_Timeout_Value Timeout Values
Kojto 122:f9eeca106725 163 * @{
Kojto 122:f9eeca106725 164 */
Kojto 122:f9eeca106725 165 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
Kojto 122:f9eeca106725 166 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto 122:f9eeca106725 167 /**
Kojto 122:f9eeca106725 168 * @}
Kojto 122:f9eeca106725 169 */
Kojto 122:f9eeca106725 170
Kojto 122:f9eeca106725 171 /** @defgroup RCC_Oscillator_Type Oscillator Type
Kojto 122:f9eeca106725 172 * @{
Kojto 122:f9eeca106725 173 */
Kojto 122:f9eeca106725 174 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /*!< Oscillator configuration unchanged */
Kojto 122:f9eeca106725 175 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /*!< HSE to configure */
Kojto 122:f9eeca106725 176 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /*!< HSI to configure */
Kojto 122:f9eeca106725 177 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /*!< LSE to configure */
Kojto 122:f9eeca106725 178 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /*!< LSI to configure */
Kojto 122:f9eeca106725 179 #define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /*!< MSI to configure */
Kojto 122:f9eeca106725 180 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 181 #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U) /*!< HSI48 to configure */
Kojto 122:f9eeca106725 182 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 183 /**
Kojto 122:f9eeca106725 184 * @}
Kojto 122:f9eeca106725 185 */
Kojto 122:f9eeca106725 186
Kojto 122:f9eeca106725 187 /** @defgroup RCC_HSE_Config HSE Config
Kojto 122:f9eeca106725 188 * @{
Kojto 122:f9eeca106725 189 */
Kojto 122:f9eeca106725 190 #define RCC_HSE_OFF ((uint32_t)0x00000000U) /*!< HSE clock deactivation */
Kojto 122:f9eeca106725 191 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
Kojto 122:f9eeca106725 192 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
Kojto 122:f9eeca106725 193 /**
Kojto 122:f9eeca106725 194 * @}
Kojto 122:f9eeca106725 195 */
Kojto 122:f9eeca106725 196
Kojto 122:f9eeca106725 197 /** @defgroup RCC_LSE_Config LSE Config
Kojto 122:f9eeca106725 198 * @{
Kojto 122:f9eeca106725 199 */
Kojto 122:f9eeca106725 200 #define RCC_LSE_OFF ((uint32_t)0x00000000U) /*!< LSE clock deactivation */
Kojto 122:f9eeca106725 201 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
Kojto 122:f9eeca106725 202 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
Kojto 122:f9eeca106725 203 /**
Kojto 122:f9eeca106725 204 * @}
Kojto 122:f9eeca106725 205 */
Kojto 122:f9eeca106725 206
Kojto 122:f9eeca106725 207 /** @defgroup RCC_HSI_Config HSI Config
Kojto 122:f9eeca106725 208 * @{
Kojto 122:f9eeca106725 209 */
Kojto 122:f9eeca106725 210 #define RCC_HSI_OFF ((uint32_t)0x00000000U) /*!< HSI clock deactivation */
Kojto 122:f9eeca106725 211 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
Kojto 122:f9eeca106725 212
AnnaBridge 145:64910690c574 213 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
AnnaBridge 145:64910690c574 214 defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
AnnaBridge 145:64910690c574 215 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
AnnaBridge 145:64910690c574 216 #else
AnnaBridge 145:64910690c574 217 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x40U) /* Default HSI calibration trimming value */
AnnaBridge 145:64910690c574 218 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
AnnaBridge 145:64910690c574 219 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 122:f9eeca106725 220 /**
Kojto 122:f9eeca106725 221 * @}
Kojto 122:f9eeca106725 222 */
Kojto 122:f9eeca106725 223
Kojto 122:f9eeca106725 224 /** @defgroup RCC_LSI_Config LSI Config
Kojto 122:f9eeca106725 225 * @{
Kojto 122:f9eeca106725 226 */
Kojto 122:f9eeca106725 227 #define RCC_LSI_OFF ((uint32_t)0x00000000U) /*!< LSI clock deactivation */
Kojto 122:f9eeca106725 228 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
Kojto 122:f9eeca106725 229 /**
Kojto 122:f9eeca106725 230 * @}
Kojto 122:f9eeca106725 231 */
Kojto 122:f9eeca106725 232
Kojto 122:f9eeca106725 233 /** @defgroup RCC_MSI_Config MSI Config
Kojto 122:f9eeca106725 234 * @{
Kojto 122:f9eeca106725 235 */
Kojto 122:f9eeca106725 236 #define RCC_MSI_OFF ((uint32_t)0x00000000U) /*!< MSI clock deactivation */
Kojto 122:f9eeca106725 237 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */
Kojto 122:f9eeca106725 238
Kojto 122:f9eeca106725 239 #define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /*!< Default MSI calibration trimming value */
Kojto 122:f9eeca106725 240 /**
Kojto 122:f9eeca106725 241 * @}
Kojto 122:f9eeca106725 242 */
Kojto 122:f9eeca106725 243
Kojto 122:f9eeca106725 244 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 245 /** @defgroup RCC_HSI48_Config HSI48 Config
Kojto 122:f9eeca106725 246 * @{
Kojto 122:f9eeca106725 247 */
Kojto 122:f9eeca106725 248 #define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */
Kojto 122:f9eeca106725 249 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */
Kojto 122:f9eeca106725 250 /**
Kojto 122:f9eeca106725 251 * @}
Kojto 122:f9eeca106725 252 */
Kojto 122:f9eeca106725 253 #else
Kojto 122:f9eeca106725 254 /** @defgroup RCC_HSI48_Config HSI48 Config
Kojto 122:f9eeca106725 255 * @{
Kojto 122:f9eeca106725 256 */
Kojto 122:f9eeca106725 257 #define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */
Kojto 122:f9eeca106725 258 /**
Kojto 122:f9eeca106725 259 * @}
Kojto 122:f9eeca106725 260 */
Kojto 122:f9eeca106725 261 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 262
Kojto 122:f9eeca106725 263 /** @defgroup RCC_PLL_Config PLL Config
Kojto 122:f9eeca106725 264 * @{
Kojto 122:f9eeca106725 265 */
Kojto 122:f9eeca106725 266 #define RCC_PLL_NONE ((uint32_t)0x00000000U) /*!< PLL configuration unchanged */
Kojto 122:f9eeca106725 267 #define RCC_PLL_OFF ((uint32_t)0x00000001U) /*!< PLL deactivation */
Kojto 122:f9eeca106725 268 #define RCC_PLL_ON ((uint32_t)0x00000002U) /*!< PLL activation */
Kojto 122:f9eeca106725 269 /**
Kojto 122:f9eeca106725 270 * @}
Kojto 122:f9eeca106725 271 */
Kojto 122:f9eeca106725 272
Kojto 122:f9eeca106725 273 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
Kojto 122:f9eeca106725 274 * @{
Kojto 122:f9eeca106725 275 */
Kojto 122:f9eeca106725 276 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 277 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) /*!< PLLP division factor = 2 */
Kojto 122:f9eeca106725 278 #define RCC_PLLP_DIV3 ((uint32_t)0x00000003U) /*!< PLLP division factor = 3 */
Kojto 122:f9eeca106725 279 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) /*!< PLLP division factor = 4 */
Kojto 122:f9eeca106725 280 #define RCC_PLLP_DIV5 ((uint32_t)0x00000005U) /*!< PLLP division factor = 5 */
Kojto 122:f9eeca106725 281 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) /*!< PLLP division factor = 6 */
Kojto 122:f9eeca106725 282 #define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */
Kojto 122:f9eeca106725 283 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) /*!< PLLP division factor = 8 */
Kojto 122:f9eeca106725 284 #define RCC_PLLP_DIV9 ((uint32_t)0x00000009U) /*!< PLLP division factor = 9 */
Kojto 122:f9eeca106725 285 #define RCC_PLLP_DIV10 ((uint32_t)0x0000000AU) /*!< PLLP division factor = 10 */
Kojto 122:f9eeca106725 286 #define RCC_PLLP_DIV11 ((uint32_t)0x0000000BU) /*!< PLLP division factor = 11 */
Kojto 122:f9eeca106725 287 #define RCC_PLLP_DIV12 ((uint32_t)0x0000000CU) /*!< PLLP division factor = 12 */
Kojto 122:f9eeca106725 288 #define RCC_PLLP_DIV13 ((uint32_t)0x0000000DU) /*!< PLLP division factor = 13 */
Kojto 122:f9eeca106725 289 #define RCC_PLLP_DIV14 ((uint32_t)0x0000000EU) /*!< PLLP division factor = 14 */
Kojto 122:f9eeca106725 290 #define RCC_PLLP_DIV15 ((uint32_t)0x0000000FU) /*!< PLLP division factor = 15 */
Kojto 122:f9eeca106725 291 #define RCC_PLLP_DIV16 ((uint32_t)0x00000010U) /*!< PLLP division factor = 16 */
Kojto 122:f9eeca106725 292 #define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */
Kojto 122:f9eeca106725 293 #define RCC_PLLP_DIV18 ((uint32_t)0x00000012U) /*!< PLLP division factor = 18 */
Kojto 122:f9eeca106725 294 #define RCC_PLLP_DIV19 ((uint32_t)0x00000013U) /*!< PLLP division factor = 19 */
Kojto 122:f9eeca106725 295 #define RCC_PLLP_DIV20 ((uint32_t)0x00000014U) /*!< PLLP division factor = 20 */
Kojto 122:f9eeca106725 296 #define RCC_PLLP_DIV21 ((uint32_t)0x00000015U) /*!< PLLP division factor = 21 */
Kojto 122:f9eeca106725 297 #define RCC_PLLP_DIV22 ((uint32_t)0x00000016U) /*!< PLLP division factor = 22 */
Kojto 122:f9eeca106725 298 #define RCC_PLLP_DIV23 ((uint32_t)0x00000017U) /*!< PLLP division factor = 23 */
Kojto 122:f9eeca106725 299 #define RCC_PLLP_DIV24 ((uint32_t)0x00000018U) /*!< PLLP division factor = 24 */
Kojto 122:f9eeca106725 300 #define RCC_PLLP_DIV25 ((uint32_t)0x00000019U) /*!< PLLP division factor = 25 */
Kojto 122:f9eeca106725 301 #define RCC_PLLP_DIV26 ((uint32_t)0x0000001AU) /*!< PLLP division factor = 26 */
Kojto 122:f9eeca106725 302 #define RCC_PLLP_DIV27 ((uint32_t)0x0000001BU) /*!< PLLP division factor = 27 */
Kojto 122:f9eeca106725 303 #define RCC_PLLP_DIV28 ((uint32_t)0x0000001CU) /*!< PLLP division factor = 28 */
Kojto 122:f9eeca106725 304 #define RCC_PLLP_DIV29 ((uint32_t)0x0000001DU) /*!< PLLP division factor = 29 */
Kojto 122:f9eeca106725 305 #define RCC_PLLP_DIV30 ((uint32_t)0x0000001EU) /*!< PLLP division factor = 30 */
Kojto 122:f9eeca106725 306 #define RCC_PLLP_DIV31 ((uint32_t)0x0000001FU) /*!< PLLP division factor = 31 */
Kojto 122:f9eeca106725 307 #else
Kojto 122:f9eeca106725 308 #define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */
Kojto 122:f9eeca106725 309 #define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */
Kojto 122:f9eeca106725 310 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 311 /**
Kojto 122:f9eeca106725 312 * @}
Kojto 122:f9eeca106725 313 */
Kojto 122:f9eeca106725 314
Kojto 122:f9eeca106725 315 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
Kojto 122:f9eeca106725 316 * @{
Kojto 122:f9eeca106725 317 */
Kojto 122:f9eeca106725 318 #define RCC_PLLQ_DIV2 ((uint32_t)0x00000002U) /*!< PLLQ division factor = 2 */
Kojto 122:f9eeca106725 319 #define RCC_PLLQ_DIV4 ((uint32_t)0x00000004U) /*!< PLLQ division factor = 4 */
Kojto 122:f9eeca106725 320 #define RCC_PLLQ_DIV6 ((uint32_t)0x00000006U) /*!< PLLQ division factor = 6 */
Kojto 122:f9eeca106725 321 #define RCC_PLLQ_DIV8 ((uint32_t)0x00000008U) /*!< PLLQ division factor = 8 */
Kojto 122:f9eeca106725 322 /**
Kojto 122:f9eeca106725 323 * @}
Kojto 122:f9eeca106725 324 */
Kojto 122:f9eeca106725 325
Kojto 122:f9eeca106725 326 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
Kojto 122:f9eeca106725 327 * @{
Kojto 122:f9eeca106725 328 */
Kojto 122:f9eeca106725 329 #define RCC_PLLR_DIV2 ((uint32_t)0x00000002U) /*!< PLLR division factor = 2 */
Kojto 122:f9eeca106725 330 #define RCC_PLLR_DIV4 ((uint32_t)0x00000004U) /*!< PLLR division factor = 4 */
Kojto 122:f9eeca106725 331 #define RCC_PLLR_DIV6 ((uint32_t)0x00000006U) /*!< PLLR division factor = 6 */
Kojto 122:f9eeca106725 332 #define RCC_PLLR_DIV8 ((uint32_t)0x00000008U) /*!< PLLR division factor = 8 */
Kojto 122:f9eeca106725 333 /**
Kojto 122:f9eeca106725 334 * @}
Kojto 122:f9eeca106725 335 */
Kojto 122:f9eeca106725 336
Kojto 122:f9eeca106725 337 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
Kojto 122:f9eeca106725 338 * @{
Kojto 122:f9eeca106725 339 */
Kojto 122:f9eeca106725 340 #define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U) /*!< No clock selected as PLL entry clock source */
Kojto 122:f9eeca106725 341 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */
Kojto 122:f9eeca106725 342 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
Kojto 122:f9eeca106725 343 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
Kojto 122:f9eeca106725 344 /**
Kojto 122:f9eeca106725 345 * @}
Kojto 122:f9eeca106725 346 */
Kojto 122:f9eeca106725 347
Kojto 122:f9eeca106725 348 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output
Kojto 122:f9eeca106725 349 * @{
Kojto 122:f9eeca106725 350 */
Kojto 122:f9eeca106725 351 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 352 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */
Kojto 122:f9eeca106725 353 #else
Kojto 122:f9eeca106725 354 #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */
Kojto 122:f9eeca106725 355 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 356 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */
Kojto 122:f9eeca106725 357 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */
Kojto 122:f9eeca106725 358 /**
Kojto 122:f9eeca106725 359 * @}
Kojto 122:f9eeca106725 360 */
Kojto 122:f9eeca106725 361
Kojto 122:f9eeca106725 362 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
Kojto 122:f9eeca106725 363 * @{
Kojto 122:f9eeca106725 364 */
Kojto 122:f9eeca106725 365 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */
Kojto 122:f9eeca106725 366 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */
Kojto 122:f9eeca106725 367 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */
Kojto 122:f9eeca106725 368 /**
Kojto 122:f9eeca106725 369 * @}
Kojto 122:f9eeca106725 370 */
Kojto 122:f9eeca106725 371
Kojto 122:f9eeca106725 372 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 373
Kojto 122:f9eeca106725 374 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
Kojto 122:f9eeca106725 375 * @{
Kojto 122:f9eeca106725 376 */
Kojto 122:f9eeca106725 377 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */
Kojto 122:f9eeca106725 378 #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */
Kojto 122:f9eeca106725 379 /**
Kojto 122:f9eeca106725 380 * @}
Kojto 122:f9eeca106725 381 */
Kojto 122:f9eeca106725 382
Kojto 122:f9eeca106725 383 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 384
Kojto 122:f9eeca106725 385 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range
Kojto 122:f9eeca106725 386 * @{
Kojto 122:f9eeca106725 387 */
Kojto 122:f9eeca106725 388 #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
Kojto 122:f9eeca106725 389 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
Kojto 122:f9eeca106725 390 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
Kojto 122:f9eeca106725 391 #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
Kojto 122:f9eeca106725 392 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
Kojto 122:f9eeca106725 393 #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
Kojto 122:f9eeca106725 394 #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
Kojto 122:f9eeca106725 395 #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
Kojto 122:f9eeca106725 396 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
Kojto 122:f9eeca106725 397 #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
Kojto 122:f9eeca106725 398 #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
Kojto 122:f9eeca106725 399 #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
Kojto 122:f9eeca106725 400 /**
Kojto 122:f9eeca106725 401 * @}
Kojto 122:f9eeca106725 402 */
Kojto 122:f9eeca106725 403
Kojto 122:f9eeca106725 404 /** @defgroup RCC_System_Clock_Type System Clock Type
Kojto 122:f9eeca106725 405 * @{
Kojto 122:f9eeca106725 406 */
Kojto 122:f9eeca106725 407 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /*!< SYSCLK to configure */
Kojto 122:f9eeca106725 408 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /*!< HCLK to configure */
Kojto 122:f9eeca106725 409 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /*!< PCLK1 to configure */
Kojto 122:f9eeca106725 410 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /*!< PCLK2 to configure */
Kojto 122:f9eeca106725 411 /**
Kojto 122:f9eeca106725 412 * @}
Kojto 122:f9eeca106725 413 */
Kojto 122:f9eeca106725 414
Kojto 122:f9eeca106725 415 /** @defgroup RCC_System_Clock_Source System Clock Source
Kojto 122:f9eeca106725 416 * @{
Kojto 122:f9eeca106725 417 */
Kojto 122:f9eeca106725 418 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
Kojto 122:f9eeca106725 419 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
Kojto 122:f9eeca106725 420 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
Kojto 122:f9eeca106725 421 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
Kojto 122:f9eeca106725 422 /**
Kojto 122:f9eeca106725 423 * @}
Kojto 122:f9eeca106725 424 */
Kojto 122:f9eeca106725 425
Kojto 122:f9eeca106725 426 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto 122:f9eeca106725 427 * @{
Kojto 122:f9eeca106725 428 */
Kojto 122:f9eeca106725 429 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
Kojto 122:f9eeca106725 430 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Kojto 122:f9eeca106725 431 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Kojto 122:f9eeca106725 432 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Kojto 122:f9eeca106725 433 /**
Kojto 122:f9eeca106725 434 * @}
Kojto 122:f9eeca106725 435 */
Kojto 122:f9eeca106725 436
Kojto 122:f9eeca106725 437 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
Kojto 122:f9eeca106725 438 * @{
Kojto 122:f9eeca106725 439 */
Kojto 122:f9eeca106725 440 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
Kojto 122:f9eeca106725 441 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
Kojto 122:f9eeca106725 442 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
Kojto 122:f9eeca106725 443 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
Kojto 122:f9eeca106725 444 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
Kojto 122:f9eeca106725 445 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
Kojto 122:f9eeca106725 446 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
Kojto 122:f9eeca106725 447 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
Kojto 122:f9eeca106725 448 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
Kojto 122:f9eeca106725 449 /**
Kojto 122:f9eeca106725 450 * @}
Kojto 122:f9eeca106725 451 */
Kojto 122:f9eeca106725 452
Kojto 122:f9eeca106725 453 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
Kojto 122:f9eeca106725 454 * @{
Kojto 122:f9eeca106725 455 */
Kojto 122:f9eeca106725 456 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
Kojto 122:f9eeca106725 457 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 458 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 459 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 460 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
Kojto 122:f9eeca106725 461 /**
Kojto 122:f9eeca106725 462 * @}
Kojto 122:f9eeca106725 463 */
Kojto 122:f9eeca106725 464
Kojto 122:f9eeca106725 465 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
Kojto 122:f9eeca106725 466 * @{
Kojto 122:f9eeca106725 467 */
Kojto 122:f9eeca106725 468 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) /*!< No clock used as RTC clock */
Kojto 122:f9eeca106725 469 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 470 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 471 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
Kojto 122:f9eeca106725 472 /**
Kojto 122:f9eeca106725 473 * @}
Kojto 122:f9eeca106725 474 */
Kojto 122:f9eeca106725 475
Kojto 122:f9eeca106725 476 /** @defgroup RCC_MCO_Index MCO Index
Kojto 122:f9eeca106725 477 * @{
Kojto 122:f9eeca106725 478 */
Kojto 122:f9eeca106725 479 #define RCC_MCO1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 480 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
Kojto 122:f9eeca106725 481 /**
Kojto 122:f9eeca106725 482 * @}
Kojto 122:f9eeca106725 483 */
Kojto 122:f9eeca106725 484
Kojto 122:f9eeca106725 485 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
Kojto 122:f9eeca106725 486 * @{
Kojto 122:f9eeca106725 487 */
Kojto 122:f9eeca106725 488 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U) /*!< MCO1 output disabled, no clock on MCO1 */
Kojto 122:f9eeca106725 489 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
Kojto 122:f9eeca106725 490 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
Kojto 122:f9eeca106725 491 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
Kojto 122:f9eeca106725 492 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
Kojto 122:f9eeca106725 493 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */
Kojto 122:f9eeca106725 494 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
Kojto 122:f9eeca106725 495 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
Kojto 122:f9eeca106725 496 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 497 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */
Kojto 122:f9eeca106725 498 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 499 /**
Kojto 122:f9eeca106725 500 * @}
Kojto 122:f9eeca106725 501 */
Kojto 122:f9eeca106725 502
Kojto 122:f9eeca106725 503 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
Kojto 122:f9eeca106725 504 * @{
Kojto 122:f9eeca106725 505 */
Kojto 122:f9eeca106725 506 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
Kojto 122:f9eeca106725 507 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
Kojto 122:f9eeca106725 508 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
Kojto 122:f9eeca106725 509 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
Kojto 122:f9eeca106725 510 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
Kojto 122:f9eeca106725 511 /**
Kojto 122:f9eeca106725 512 * @}
Kojto 122:f9eeca106725 513 */
Kojto 122:f9eeca106725 514
Kojto 122:f9eeca106725 515 /** @defgroup RCC_Interrupt Interrupts
Kojto 122:f9eeca106725 516 * @{
Kojto 122:f9eeca106725 517 */
Kojto 122:f9eeca106725 518 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
Kojto 122:f9eeca106725 519 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
Kojto 122:f9eeca106725 520 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
Kojto 122:f9eeca106725 521 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */
Kojto 122:f9eeca106725 522 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
Kojto 122:f9eeca106725 523 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
Kojto 122:f9eeca106725 524 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
Kojto 122:f9eeca106725 525 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 526 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */
Kojto 122:f9eeca106725 527 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 528 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
Kojto 122:f9eeca106725 529 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
Kojto 122:f9eeca106725 530 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 531 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
Kojto 122:f9eeca106725 532 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 533 /**
Kojto 122:f9eeca106725 534 * @}
Kojto 122:f9eeca106725 535 */
Kojto 122:f9eeca106725 536
Kojto 122:f9eeca106725 537 /** @defgroup RCC_Flag Flags
Kojto 122:f9eeca106725 538 * Elements values convention: XXXYYYYYb
Kojto 122:f9eeca106725 539 * - YYYYY : Flag position in the register
Kojto 122:f9eeca106725 540 * - XXX : Register index
Kojto 122:f9eeca106725 541 * - 001: CR register
Kojto 122:f9eeca106725 542 * - 010: BDCR register
Kojto 122:f9eeca106725 543 * - 011: CSR register
Kojto 122:f9eeca106725 544 * - 100: CRRCR register
Kojto 122:f9eeca106725 545 * @{
Kojto 122:f9eeca106725 546 */
Kojto 122:f9eeca106725 547 /* Flags in the CR register */
Kojto 122:f9eeca106725 548 #define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI Ready flag */
Kojto 122:f9eeca106725 549 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< HSI Ready flag */
Kojto 122:f9eeca106725 550 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< HSE Ready flag */
Kojto 122:f9eeca106725 551 #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL Ready flag */
Kojto 122:f9eeca106725 552 #define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY))) /*!< PLLSAI1 Ready flag */
Kojto 122:f9eeca106725 553 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 554 #define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY))) /*!< PLLSAI2 Ready flag */
Kojto 122:f9eeca106725 555 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 556
Kojto 122:f9eeca106725 557 /* Flags in the BDCR register */
Kojto 122:f9eeca106725 558 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< LSE Ready flag */
Kojto 122:f9eeca106725 559 #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD))) /*!< LSE Clock Security System Interrupt flag */
Kojto 122:f9eeca106725 560
Kojto 122:f9eeca106725 561 /* Flags in the CSR register */
Kojto 122:f9eeca106725 562 #define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< LSI Ready flag */
Kojto 122:f9eeca106725 563 #define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF))) /*!< Remove reset flag */
Kojto 122:f9eeca106725 564 #define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF))) /*!< Firewall reset flag */
Kojto 122:f9eeca106725 565 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Option Byte Loader reset flag */
Kojto 122:f9eeca106725 566 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
Kojto 122:f9eeca106725 567 #define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF))) /*!< BOR reset flag */
Kojto 122:f9eeca106725 568 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
Kojto 122:f9eeca106725 569 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
Kojto 122:f9eeca106725 570 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
Kojto 122:f9eeca106725 571 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
Kojto 122:f9eeca106725 572
Kojto 122:f9eeca106725 573 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 574 /* Flags in the CRRCR register */
Kojto 122:f9eeca106725 575 #define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) | POSITION_VAL(RCC_CRRCR_HSI48RDY))) /*!< HSI48 Ready flag */
Kojto 122:f9eeca106725 576 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 577 /**
Kojto 122:f9eeca106725 578 * @}
Kojto 122:f9eeca106725 579 */
Kojto 122:f9eeca106725 580
Kojto 122:f9eeca106725 581 /** @defgroup RCC_LSEDrive_Config LSE Drive Config
Kojto 122:f9eeca106725 582 * @{
Kojto 122:f9eeca106725 583 */
Kojto 122:f9eeca106725 584 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< LSE low drive capability */
Kojto 122:f9eeca106725 585 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
Kojto 122:f9eeca106725 586 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
Kojto 122:f9eeca106725 587 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
Kojto 122:f9eeca106725 588 /**
Kojto 122:f9eeca106725 589 * @}
Kojto 122:f9eeca106725 590 */
Kojto 122:f9eeca106725 591
Kojto 122:f9eeca106725 592 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
Kojto 122:f9eeca106725 593 * @{
Kojto 122:f9eeca106725 594 */
Kojto 122:f9eeca106725 595 #define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /*!< MSI selection after wake-up from STOP */
Kojto 122:f9eeca106725 596 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
Kojto 122:f9eeca106725 597 /**
Kojto 122:f9eeca106725 598 * @}
Kojto 122:f9eeca106725 599 */
Kojto 122:f9eeca106725 600
Kojto 122:f9eeca106725 601 /**
Kojto 122:f9eeca106725 602 * @}
Kojto 122:f9eeca106725 603 */
Kojto 122:f9eeca106725 604
Kojto 122:f9eeca106725 605 /* Exported macros -----------------------------------------------------------*/
Kojto 122:f9eeca106725 606
Kojto 122:f9eeca106725 607 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 122:f9eeca106725 608 * @{
Kojto 122:f9eeca106725 609 */
Kojto 122:f9eeca106725 610
Kojto 122:f9eeca106725 611 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto 122:f9eeca106725 612 * @brief Enable or disable the AHB1 peripheral clock.
Kojto 122:f9eeca106725 613 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 614 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 615 * using it.
Kojto 122:f9eeca106725 616 * @{
Kojto 122:f9eeca106725 617 */
Kojto 122:f9eeca106725 618
Kojto 122:f9eeca106725 619 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 620 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 621 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
Kojto 122:f9eeca106725 622 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 623 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
Kojto 122:f9eeca106725 624 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 625 } while(0)
Kojto 122:f9eeca106725 626
Kojto 122:f9eeca106725 627 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 628 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 629 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
Kojto 122:f9eeca106725 630 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 631 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
Kojto 122:f9eeca106725 632 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 633 } while(0)
Kojto 122:f9eeca106725 634
Kojto 122:f9eeca106725 635 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 636 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 637 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
Kojto 122:f9eeca106725 638 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 639 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
Kojto 122:f9eeca106725 640 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 641 } while(0)
Kojto 122:f9eeca106725 642
Kojto 122:f9eeca106725 643 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 644 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 645 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
Kojto 122:f9eeca106725 646 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 647 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
Kojto 122:f9eeca106725 648 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 649 } while(0)
Kojto 122:f9eeca106725 650
Kojto 122:f9eeca106725 651 #define __HAL_RCC_TSC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 652 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 653 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
Kojto 122:f9eeca106725 654 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 655 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
Kojto 122:f9eeca106725 656 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 657 } while(0)
AnnaBridge 145:64910690c574 658
AnnaBridge 145:64910690c574 659 #if defined(DMA2D)
AnnaBridge 145:64910690c574 660 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
AnnaBridge 145:64910690c574 661 __IO uint32_t tmpreg; \
AnnaBridge 145:64910690c574 662 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
AnnaBridge 145:64910690c574 663 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 145:64910690c574 664 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
AnnaBridge 145:64910690c574 665 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 666 } while(0)
AnnaBridge 145:64910690c574 667 #endif /* DMA2D */
Kojto 122:f9eeca106725 668
Kojto 122:f9eeca106725 669
Kojto 122:f9eeca106725 670 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
Kojto 122:f9eeca106725 671
Kojto 122:f9eeca106725 672 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
Kojto 122:f9eeca106725 673
Kojto 122:f9eeca106725 674 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
Kojto 122:f9eeca106725 675
Kojto 122:f9eeca106725 676 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
Kojto 122:f9eeca106725 677
Kojto 122:f9eeca106725 678 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
Kojto 122:f9eeca106725 679
AnnaBridge 145:64910690c574 680 #if defined(DMA2D)
AnnaBridge 145:64910690c574 681 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN)
AnnaBridge 145:64910690c574 682 #endif /* DMA2D */
AnnaBridge 145:64910690c574 683
Kojto 122:f9eeca106725 684 /**
Kojto 122:f9eeca106725 685 * @}
Kojto 122:f9eeca106725 686 */
Kojto 122:f9eeca106725 687
Kojto 122:f9eeca106725 688 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto 122:f9eeca106725 689 * @brief Enable or disable the AHB2 peripheral clock.
Kojto 122:f9eeca106725 690 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 691 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 692 * using it.
Kojto 122:f9eeca106725 693 * @{
Kojto 122:f9eeca106725 694 */
Kojto 122:f9eeca106725 695
Kojto 122:f9eeca106725 696 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 697 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 698 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
Kojto 122:f9eeca106725 699 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 700 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
Kojto 122:f9eeca106725 701 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 702 } while(0)
Kojto 122:f9eeca106725 703
Kojto 122:f9eeca106725 704 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 705 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 706 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
Kojto 122:f9eeca106725 707 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 708 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
Kojto 122:f9eeca106725 709 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 710 } while(0)
Kojto 122:f9eeca106725 711
Kojto 122:f9eeca106725 712 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 713 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 714 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
Kojto 122:f9eeca106725 715 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 716 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
Kojto 122:f9eeca106725 717 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 718 } while(0)
Kojto 122:f9eeca106725 719
Kojto 122:f9eeca106725 720 #if defined(GPIOD)
Kojto 122:f9eeca106725 721 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 722 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 723 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
Kojto 122:f9eeca106725 724 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 725 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
Kojto 122:f9eeca106725 726 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 727 } while(0)
Kojto 122:f9eeca106725 728 #endif /* GPIOD */
Kojto 122:f9eeca106725 729
Kojto 122:f9eeca106725 730 #if defined(GPIOE)
Kojto 122:f9eeca106725 731 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 732 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 733 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
Kojto 122:f9eeca106725 734 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 735 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
Kojto 122:f9eeca106725 736 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 737 } while(0)
Kojto 122:f9eeca106725 738 #endif /* GPIOE */
Kojto 122:f9eeca106725 739
Kojto 122:f9eeca106725 740 #if defined(GPIOF)
Kojto 122:f9eeca106725 741 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 742 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 743 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
Kojto 122:f9eeca106725 744 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 745 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
Kojto 122:f9eeca106725 746 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 747 } while(0)
Kojto 122:f9eeca106725 748 #endif /* GPIOF */
Kojto 122:f9eeca106725 749
Kojto 122:f9eeca106725 750 #if defined(GPIOG)
Kojto 122:f9eeca106725 751 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 752 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 753 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
Kojto 122:f9eeca106725 754 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 755 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
Kojto 122:f9eeca106725 756 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 757 } while(0)
Kojto 122:f9eeca106725 758 #endif /* GPIOG */
Kojto 122:f9eeca106725 759
Kojto 122:f9eeca106725 760 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 761 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 762 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
Kojto 122:f9eeca106725 763 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 764 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
Kojto 122:f9eeca106725 765 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 766 } while(0)
Kojto 122:f9eeca106725 767
AnnaBridge 145:64910690c574 768 #if defined(GPIOI)
AnnaBridge 145:64910690c574 769 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
AnnaBridge 145:64910690c574 770 __IO uint32_t tmpreg; \
AnnaBridge 145:64910690c574 771 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
AnnaBridge 145:64910690c574 772 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 145:64910690c574 773 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
AnnaBridge 145:64910690c574 774 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 775 } while(0)
AnnaBridge 145:64910690c574 776 #endif /* GPIOI */
AnnaBridge 145:64910690c574 777
Kojto 122:f9eeca106725 778 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 779 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 780 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 781 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
Kojto 122:f9eeca106725 782 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 783 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
Kojto 122:f9eeca106725 784 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 785 } while(0)
Kojto 122:f9eeca106725 786 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 787
Kojto 122:f9eeca106725 788 #define __HAL_RCC_ADC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 789 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 790 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
Kojto 122:f9eeca106725 791 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 792 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
Kojto 122:f9eeca106725 793 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 794 } while(0)
Kojto 122:f9eeca106725 795
AnnaBridge 145:64910690c574 796 #if defined(DCMI)
AnnaBridge 145:64910690c574 797 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
AnnaBridge 145:64910690c574 798 __IO uint32_t tmpreg; \
AnnaBridge 145:64910690c574 799 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
AnnaBridge 145:64910690c574 800 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 145:64910690c574 801 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
AnnaBridge 145:64910690c574 802 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 803 } while(0)
AnnaBridge 145:64910690c574 804 #endif /* DCMI */
AnnaBridge 145:64910690c574 805
Kojto 122:f9eeca106725 806 #if defined(AES)
Kojto 122:f9eeca106725 807 #define __HAL_RCC_AES_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 808 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 809 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
Kojto 122:f9eeca106725 810 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 811 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
Kojto 122:f9eeca106725 812 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 813 } while(0)
Kojto 122:f9eeca106725 814 #endif /* AES */
Kojto 122:f9eeca106725 815
AnnaBridge 145:64910690c574 816 #if defined(HASH)
AnnaBridge 145:64910690c574 817 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
AnnaBridge 145:64910690c574 818 __IO uint32_t tmpreg; \
AnnaBridge 145:64910690c574 819 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
AnnaBridge 145:64910690c574 820 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 145:64910690c574 821 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
AnnaBridge 145:64910690c574 822 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 823 } while(0)
AnnaBridge 145:64910690c574 824 #endif /* HASH */
AnnaBridge 145:64910690c574 825
Kojto 122:f9eeca106725 826 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 827 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 828 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
Kojto 122:f9eeca106725 829 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 830 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
Kojto 122:f9eeca106725 831 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 832 } while(0)
Kojto 122:f9eeca106725 833
Kojto 122:f9eeca106725 834
Kojto 122:f9eeca106725 835 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
Kojto 122:f9eeca106725 836
Kojto 122:f9eeca106725 837 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
Kojto 122:f9eeca106725 838
Kojto 122:f9eeca106725 839 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
Kojto 122:f9eeca106725 840
Kojto 122:f9eeca106725 841 #if defined(GPIOD)
Kojto 122:f9eeca106725 842 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
Kojto 122:f9eeca106725 843 #endif /* GPIOD */
Kojto 122:f9eeca106725 844
Kojto 122:f9eeca106725 845 #if defined(GPIOE)
Kojto 122:f9eeca106725 846 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
Kojto 122:f9eeca106725 847 #endif /* GPIOE */
Kojto 122:f9eeca106725 848
Kojto 122:f9eeca106725 849 #if defined(GPIOF)
Kojto 122:f9eeca106725 850 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
Kojto 122:f9eeca106725 851 #endif /* GPIOF */
Kojto 122:f9eeca106725 852
Kojto 122:f9eeca106725 853 #if defined(GPIOG)
Kojto 122:f9eeca106725 854 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
Kojto 122:f9eeca106725 855 #endif /* GPIOG */
Kojto 122:f9eeca106725 856
Kojto 122:f9eeca106725 857 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
Kojto 122:f9eeca106725 858
AnnaBridge 145:64910690c574 859 #if defined(GPIOI)
AnnaBridge 145:64910690c574 860 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN)
AnnaBridge 145:64910690c574 861 #endif /* GPIOI */
AnnaBridge 145:64910690c574 862
Kojto 122:f9eeca106725 863 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 864 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
Kojto 122:f9eeca106725 865 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 866
Kojto 122:f9eeca106725 867 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
Kojto 122:f9eeca106725 868
AnnaBridge 145:64910690c574 869 #if defined(DCMI)
AnnaBridge 145:64910690c574 870 #define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN)
AnnaBridge 145:64910690c574 871 #endif /* DCMI */
AnnaBridge 145:64910690c574 872
Kojto 122:f9eeca106725 873 #if defined(AES)
Kojto 122:f9eeca106725 874 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
Kojto 122:f9eeca106725 875 #endif /* AES */
Kojto 122:f9eeca106725 876
AnnaBridge 145:64910690c574 877 #if defined(HASH)
AnnaBridge 145:64910690c574 878 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN)
AnnaBridge 145:64910690c574 879 #endif /* HASH */
AnnaBridge 145:64910690c574 880
Kojto 122:f9eeca106725 881 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
Kojto 122:f9eeca106725 882
Kojto 122:f9eeca106725 883 /**
Kojto 122:f9eeca106725 884 * @}
Kojto 122:f9eeca106725 885 */
Kojto 122:f9eeca106725 886
Kojto 122:f9eeca106725 887 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto 122:f9eeca106725 888 * @brief Enable or disable the AHB3 peripheral clock.
Kojto 122:f9eeca106725 889 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 890 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 891 * using it.
Kojto 122:f9eeca106725 892 * @{
Kojto 122:f9eeca106725 893 */
Kojto 122:f9eeca106725 894
Kojto 122:f9eeca106725 895 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 896 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 897 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 898 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
Kojto 122:f9eeca106725 899 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 900 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
Kojto 122:f9eeca106725 901 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 902 } while(0)
Kojto 122:f9eeca106725 903 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 904
Kojto 122:f9eeca106725 905 #if defined(QUADSPI)
Kojto 122:f9eeca106725 906 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 907 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 908 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
Kojto 122:f9eeca106725 909 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 910 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
Kojto 122:f9eeca106725 911 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 912 } while(0)
Kojto 122:f9eeca106725 913 #endif /* QUADSPI */
Kojto 122:f9eeca106725 914
Kojto 122:f9eeca106725 915 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 916 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
Kojto 122:f9eeca106725 917 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 918
Kojto 122:f9eeca106725 919 #if defined(QUADSPI)
Kojto 122:f9eeca106725 920 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
Kojto 122:f9eeca106725 921 #endif /* QUADSPI */
Kojto 122:f9eeca106725 922
Kojto 122:f9eeca106725 923 /**
Kojto 122:f9eeca106725 924 * @}
Kojto 122:f9eeca106725 925 */
Kojto 122:f9eeca106725 926
Kojto 122:f9eeca106725 927 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto 122:f9eeca106725 928 * @brief Enable or disable the APB1 peripheral clock.
Kojto 122:f9eeca106725 929 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 930 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 931 * using it.
Kojto 122:f9eeca106725 932 * @{
Kojto 122:f9eeca106725 933 */
Kojto 122:f9eeca106725 934
Kojto 122:f9eeca106725 935 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 936 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 937 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
Kojto 122:f9eeca106725 938 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 939 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
Kojto 122:f9eeca106725 940 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 941 } while(0)
Kojto 122:f9eeca106725 942
Kojto 122:f9eeca106725 943 #if defined(TIM3)
Kojto 122:f9eeca106725 944 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 945 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 946 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
Kojto 122:f9eeca106725 947 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 948 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
Kojto 122:f9eeca106725 949 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 950 } while(0)
Kojto 122:f9eeca106725 951 #endif /* TIM3 */
Kojto 122:f9eeca106725 952
Kojto 122:f9eeca106725 953 #if defined(TIM4)
Kojto 122:f9eeca106725 954 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 955 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 956 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
Kojto 122:f9eeca106725 957 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 958 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
Kojto 122:f9eeca106725 959 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 960 } while(0)
Kojto 122:f9eeca106725 961 #endif /* TIM4 */
Kojto 122:f9eeca106725 962
Kojto 122:f9eeca106725 963 #if defined(TIM5)
Kojto 122:f9eeca106725 964 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 965 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 966 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
Kojto 122:f9eeca106725 967 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 968 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
Kojto 122:f9eeca106725 969 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 970 } while(0)
Kojto 122:f9eeca106725 971 #endif /* TIM5 */
Kojto 122:f9eeca106725 972
Kojto 122:f9eeca106725 973 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 974 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 975 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
Kojto 122:f9eeca106725 976 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 977 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
Kojto 122:f9eeca106725 978 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 979 } while(0)
Kojto 122:f9eeca106725 980
Kojto 122:f9eeca106725 981 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 982 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 983 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
Kojto 122:f9eeca106725 984 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 985 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
Kojto 122:f9eeca106725 986 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 987 } while(0)
Kojto 122:f9eeca106725 988
Kojto 122:f9eeca106725 989 #if defined(LCD)
Kojto 122:f9eeca106725 990 #define __HAL_RCC_LCD_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 991 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 992 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
Kojto 122:f9eeca106725 993 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 994 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
Kojto 122:f9eeca106725 995 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 996 } while(0)
Kojto 122:f9eeca106725 997 #endif /* LCD */
Kojto 122:f9eeca106725 998
Kojto 122:f9eeca106725 999 #if defined(RCC_APB1ENR1_RTCAPBEN)
Kojto 122:f9eeca106725 1000 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1001 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1002 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
Kojto 122:f9eeca106725 1003 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1004 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
Kojto 122:f9eeca106725 1005 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1006 } while(0)
Kojto 122:f9eeca106725 1007 #endif /* RCC_APB1ENR1_RTCAPBEN */
Kojto 122:f9eeca106725 1008
Kojto 122:f9eeca106725 1009 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1010 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1011 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
Kojto 122:f9eeca106725 1012 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1013 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
Kojto 122:f9eeca106725 1014 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1015 } while(0)
Kojto 122:f9eeca106725 1016
Kojto 122:f9eeca106725 1017 #if defined(SPI2)
Kojto 122:f9eeca106725 1018 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1019 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1020 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
Kojto 122:f9eeca106725 1021 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1022 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
Kojto 122:f9eeca106725 1023 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1024 } while(0)
Kojto 122:f9eeca106725 1025 #endif /* SPI2 */
Kojto 122:f9eeca106725 1026
Kojto 122:f9eeca106725 1027 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1028 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1029 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
Kojto 122:f9eeca106725 1030 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1031 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
Kojto 122:f9eeca106725 1032 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1033 } while(0)
Kojto 122:f9eeca106725 1034
Kojto 122:f9eeca106725 1035 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1036 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1037 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
Kojto 122:f9eeca106725 1038 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1039 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
Kojto 122:f9eeca106725 1040 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1041 } while(0)
Kojto 122:f9eeca106725 1042
Kojto 122:f9eeca106725 1043 #if defined(USART3)
Kojto 122:f9eeca106725 1044 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1045 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1046 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
Kojto 122:f9eeca106725 1047 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1048 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
Kojto 122:f9eeca106725 1049 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1050 } while(0)
Kojto 122:f9eeca106725 1051 #endif /* USART3 */
Kojto 122:f9eeca106725 1052
Kojto 122:f9eeca106725 1053 #if defined(UART4)
Kojto 122:f9eeca106725 1054 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1055 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1056 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
Kojto 122:f9eeca106725 1057 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1058 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
Kojto 122:f9eeca106725 1059 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1060 } while(0)
Kojto 122:f9eeca106725 1061 #endif /* UART4 */
Kojto 122:f9eeca106725 1062
Kojto 122:f9eeca106725 1063 #if defined(UART5)
Kojto 122:f9eeca106725 1064 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1065 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1066 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
Kojto 122:f9eeca106725 1067 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1068 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
Kojto 122:f9eeca106725 1069 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1070 } while(0)
Kojto 122:f9eeca106725 1071 #endif /* UART5 */
Kojto 122:f9eeca106725 1072
Kojto 122:f9eeca106725 1073 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1074 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1075 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
Kojto 122:f9eeca106725 1076 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1077 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
Kojto 122:f9eeca106725 1078 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1079 } while(0)
Kojto 122:f9eeca106725 1080
Kojto 122:f9eeca106725 1081 #if defined(I2C2)
Kojto 122:f9eeca106725 1082 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1083 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1084 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
Kojto 122:f9eeca106725 1085 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1086 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
Kojto 122:f9eeca106725 1087 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1088 } while(0)
Kojto 122:f9eeca106725 1089 #endif /* I2C2 */
Kojto 122:f9eeca106725 1090
Kojto 122:f9eeca106725 1091 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1092 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1093 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
Kojto 122:f9eeca106725 1094 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1095 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
Kojto 122:f9eeca106725 1096 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1097 } while(0)
Kojto 122:f9eeca106725 1098
AnnaBridge 145:64910690c574 1099 #if defined(I2C4)
AnnaBridge 145:64910690c574 1100 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
AnnaBridge 145:64910690c574 1101 __IO uint32_t tmpreg; \
AnnaBridge 145:64910690c574 1102 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
AnnaBridge 145:64910690c574 1103 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 145:64910690c574 1104 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
AnnaBridge 145:64910690c574 1105 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 1106 } while(0)
AnnaBridge 145:64910690c574 1107 #endif /* I2C4 */
AnnaBridge 145:64910690c574 1108
Kojto 122:f9eeca106725 1109 #if defined(CRS)
Kojto 122:f9eeca106725 1110 #define __HAL_RCC_CRS_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1111 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1112 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
Kojto 122:f9eeca106725 1113 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1114 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
Kojto 122:f9eeca106725 1115 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1116 } while(0)
Kojto 122:f9eeca106725 1117 #endif /* CRS */
Kojto 122:f9eeca106725 1118
Kojto 122:f9eeca106725 1119 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1120 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1121 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
Kojto 122:f9eeca106725 1122 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1123 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
Kojto 122:f9eeca106725 1124 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1125 } while(0)
AnnaBridge 145:64910690c574 1126
AnnaBridge 145:64910690c574 1127 #if defined(CAN2)
AnnaBridge 145:64910690c574 1128 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge 145:64910690c574 1129 __IO uint32_t tmpreg; \
AnnaBridge 145:64910690c574 1130 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
AnnaBridge 145:64910690c574 1131 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 145:64910690c574 1132 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
AnnaBridge 145:64910690c574 1133 UNUSED(tmpreg); \
AnnaBridge 145:64910690c574 1134 } while(0)
AnnaBridge 145:64910690c574 1135 #endif /* CAN2 */
Kojto 122:f9eeca106725 1136
Kojto 122:f9eeca106725 1137 #if defined(USB)
Kojto 122:f9eeca106725 1138 #define __HAL_RCC_USB_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1139 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1140 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
Kojto 122:f9eeca106725 1141 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1142 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
Kojto 122:f9eeca106725 1143 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1144 } while(0)
Kojto 122:f9eeca106725 1145 #endif /* USB */
Kojto 122:f9eeca106725 1146
Kojto 122:f9eeca106725 1147 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1148 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1149 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
Kojto 122:f9eeca106725 1150 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1151 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
Kojto 122:f9eeca106725 1152 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1153 } while(0)
Kojto 122:f9eeca106725 1154
Kojto 122:f9eeca106725 1155 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1156 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1157 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
Kojto 122:f9eeca106725 1158 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1159 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
Kojto 122:f9eeca106725 1160 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1161 } while(0)
Kojto 122:f9eeca106725 1162
Kojto 122:f9eeca106725 1163 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1164 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1165 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
Kojto 122:f9eeca106725 1166 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1167 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
Kojto 122:f9eeca106725 1168 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1169 } while(0)
Kojto 122:f9eeca106725 1170
Kojto 122:f9eeca106725 1171 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1172 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1173 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
Kojto 122:f9eeca106725 1174 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1175 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
Kojto 122:f9eeca106725 1176 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1177 } while(0)
Kojto 122:f9eeca106725 1178
Kojto 122:f9eeca106725 1179 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1180 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1181 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
Kojto 122:f9eeca106725 1182 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1183 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
Kojto 122:f9eeca106725 1184 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1185 } while(0)
Kojto 122:f9eeca106725 1186
AnnaBridge 145:64910690c574 1187 #if defined(SWPMI1)
Kojto 122:f9eeca106725 1188 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1189 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1190 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
Kojto 122:f9eeca106725 1191 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1192 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
Kojto 122:f9eeca106725 1193 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1194 } while(0)
AnnaBridge 145:64910690c574 1195 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 1196
Kojto 122:f9eeca106725 1197 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1198 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1199 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
Kojto 122:f9eeca106725 1200 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1201 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
Kojto 122:f9eeca106725 1202 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1203 } while(0)
Kojto 122:f9eeca106725 1204
Kojto 122:f9eeca106725 1205
Kojto 122:f9eeca106725 1206 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
Kojto 122:f9eeca106725 1207
Kojto 122:f9eeca106725 1208 #if defined(TIM3)
Kojto 122:f9eeca106725 1209 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
Kojto 122:f9eeca106725 1210 #endif /* TIM3 */
Kojto 122:f9eeca106725 1211
Kojto 122:f9eeca106725 1212 #if defined(TIM4)
Kojto 122:f9eeca106725 1213 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
Kojto 122:f9eeca106725 1214 #endif /* TIM4 */
Kojto 122:f9eeca106725 1215
Kojto 122:f9eeca106725 1216 #if defined(TIM5)
Kojto 122:f9eeca106725 1217 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
Kojto 122:f9eeca106725 1218 #endif /* TIM5 */
Kojto 122:f9eeca106725 1219
Kojto 122:f9eeca106725 1220 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
Kojto 122:f9eeca106725 1221
Kojto 122:f9eeca106725 1222 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
Kojto 122:f9eeca106725 1223
Kojto 122:f9eeca106725 1224 #if defined(LCD)
Kojto 122:f9eeca106725 1225 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
Kojto 122:f9eeca106725 1226 #endif /* LCD */
Kojto 122:f9eeca106725 1227
Kojto 122:f9eeca106725 1228 #if defined(RCC_APB1ENR1_RTCAPBEN)
Kojto 122:f9eeca106725 1229 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
Kojto 122:f9eeca106725 1230 #endif /* RCC_APB1ENR1_RTCAPBEN */
Kojto 122:f9eeca106725 1231
Kojto 122:f9eeca106725 1232 #if defined(SPI2)
Kojto 122:f9eeca106725 1233 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
Kojto 122:f9eeca106725 1234 #endif /* SPI2 */
Kojto 122:f9eeca106725 1235
Kojto 122:f9eeca106725 1236 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
Kojto 122:f9eeca106725 1237
Kojto 122:f9eeca106725 1238 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
Kojto 122:f9eeca106725 1239
Kojto 122:f9eeca106725 1240 #if defined(USART3)
Kojto 122:f9eeca106725 1241 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
Kojto 122:f9eeca106725 1242 #endif /* USART3 */
Kojto 122:f9eeca106725 1243
Kojto 122:f9eeca106725 1244 #if defined(UART4)
Kojto 122:f9eeca106725 1245 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
Kojto 122:f9eeca106725 1246 #endif /* UART4 */
Kojto 122:f9eeca106725 1247
Kojto 122:f9eeca106725 1248 #if defined(UART5)
Kojto 122:f9eeca106725 1249 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
Kojto 122:f9eeca106725 1250 #endif /* UART5 */
Kojto 122:f9eeca106725 1251
Kojto 122:f9eeca106725 1252 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
Kojto 122:f9eeca106725 1253
Kojto 122:f9eeca106725 1254 #if defined(I2C2)
Kojto 122:f9eeca106725 1255 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
Kojto 122:f9eeca106725 1256 #endif /* I2C2 */
Kojto 122:f9eeca106725 1257
Kojto 122:f9eeca106725 1258 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
Kojto 122:f9eeca106725 1259
AnnaBridge 145:64910690c574 1260 #if defined(I2C4)
AnnaBridge 145:64910690c574 1261 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
AnnaBridge 145:64910690c574 1262 #endif /* I2C4 */
AnnaBridge 145:64910690c574 1263
Kojto 122:f9eeca106725 1264 #if defined(CRS)
Kojto 122:f9eeca106725 1265 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
Kojto 122:f9eeca106725 1266 #endif /* CRS */
Kojto 122:f9eeca106725 1267
Kojto 122:f9eeca106725 1268 #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
Kojto 122:f9eeca106725 1269
AnnaBridge 145:64910690c574 1270 #if defined(CAN2)
AnnaBridge 145:64910690c574 1271 #define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN)
AnnaBridge 145:64910690c574 1272 #endif /* CAN2 */
AnnaBridge 145:64910690c574 1273
Kojto 122:f9eeca106725 1274 #if defined(USB)
Kojto 122:f9eeca106725 1275 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);
Kojto 122:f9eeca106725 1276 #endif /* USB */
Kojto 122:f9eeca106725 1277
Kojto 122:f9eeca106725 1278 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
Kojto 122:f9eeca106725 1279
Kojto 122:f9eeca106725 1280 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
Kojto 122:f9eeca106725 1281
Kojto 122:f9eeca106725 1282 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
Kojto 122:f9eeca106725 1283
Kojto 122:f9eeca106725 1284 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
Kojto 122:f9eeca106725 1285
Kojto 122:f9eeca106725 1286 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
Kojto 122:f9eeca106725 1287
AnnaBridge 145:64910690c574 1288 #if defined(SWPMI1)
Kojto 122:f9eeca106725 1289 #define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
AnnaBridge 145:64910690c574 1290 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 1291
Kojto 122:f9eeca106725 1292 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
Kojto 122:f9eeca106725 1293
Kojto 122:f9eeca106725 1294 /**
Kojto 122:f9eeca106725 1295 * @}
Kojto 122:f9eeca106725 1296 */
Kojto 122:f9eeca106725 1297
Kojto 122:f9eeca106725 1298 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto 122:f9eeca106725 1299 * @brief Enable or disable the APB2 peripheral clock.
Kojto 122:f9eeca106725 1300 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 1301 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 1302 * using it.
Kojto 122:f9eeca106725 1303 * @{
Kojto 122:f9eeca106725 1304 */
Kojto 122:f9eeca106725 1305
Kojto 122:f9eeca106725 1306 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1307 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1308 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
Kojto 122:f9eeca106725 1309 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1310 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
Kojto 122:f9eeca106725 1311 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1312 } while(0)
Kojto 122:f9eeca106725 1313
Kojto 122:f9eeca106725 1314 #define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1315 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1316 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
Kojto 122:f9eeca106725 1317 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1318 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
Kojto 122:f9eeca106725 1319 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1320 } while(0)
Kojto 122:f9eeca106725 1321
AnnaBridge 145:64910690c574 1322 #if defined(SDMMC1)
Kojto 122:f9eeca106725 1323 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1324 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1325 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
Kojto 122:f9eeca106725 1326 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1327 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
Kojto 122:f9eeca106725 1328 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1329 } while(0)
AnnaBridge 145:64910690c574 1330 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 1331
Kojto 122:f9eeca106725 1332 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1333 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1334 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
Kojto 122:f9eeca106725 1335 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1336 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
Kojto 122:f9eeca106725 1337 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1338 } while(0)
Kojto 122:f9eeca106725 1339
Kojto 122:f9eeca106725 1340 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1341 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1342 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
Kojto 122:f9eeca106725 1343 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1344 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
Kojto 122:f9eeca106725 1345 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1346 } while(0)
Kojto 122:f9eeca106725 1347
Kojto 122:f9eeca106725 1348 #if defined(TIM8)
Kojto 122:f9eeca106725 1349 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1350 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1351 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
Kojto 122:f9eeca106725 1352 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1353 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
Kojto 122:f9eeca106725 1354 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1355 } while(0)
Kojto 122:f9eeca106725 1356 #endif /* TIM8 */
Kojto 122:f9eeca106725 1357
Kojto 122:f9eeca106725 1358 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1359 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1360 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
Kojto 122:f9eeca106725 1361 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1362 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
Kojto 122:f9eeca106725 1363 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1364 } while(0)
Kojto 122:f9eeca106725 1365
Kojto 122:f9eeca106725 1366
Kojto 122:f9eeca106725 1367 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1368 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1369 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
Kojto 122:f9eeca106725 1370 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1371 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
Kojto 122:f9eeca106725 1372 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1373 } while(0)
Kojto 122:f9eeca106725 1374
Kojto 122:f9eeca106725 1375 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1376 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1377 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
Kojto 122:f9eeca106725 1378 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1379 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
Kojto 122:f9eeca106725 1380 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1381 } while(0)
Kojto 122:f9eeca106725 1382
Kojto 122:f9eeca106725 1383 #if defined(TIM17)
Kojto 122:f9eeca106725 1384 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1385 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1386 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
Kojto 122:f9eeca106725 1387 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1388 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
Kojto 122:f9eeca106725 1389 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1390 } while(0)
Kojto 122:f9eeca106725 1391 #endif /* TIM17 */
Kojto 122:f9eeca106725 1392
Kojto 122:f9eeca106725 1393 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1394 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1395 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
Kojto 122:f9eeca106725 1396 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1397 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
Kojto 122:f9eeca106725 1398 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1399 } while(0)
Kojto 122:f9eeca106725 1400
Kojto 122:f9eeca106725 1401 #if defined(SAI2)
Kojto 122:f9eeca106725 1402 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1403 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1404 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
Kojto 122:f9eeca106725 1405 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1406 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
Kojto 122:f9eeca106725 1407 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1408 } while(0)
Kojto 122:f9eeca106725 1409 #endif /* SAI2 */
Kojto 122:f9eeca106725 1410
Kojto 122:f9eeca106725 1411 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 1412 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1413 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1414 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
Kojto 122:f9eeca106725 1415 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1416 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
Kojto 122:f9eeca106725 1417 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1418 } while(0)
Kojto 122:f9eeca106725 1419 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 1420
Kojto 122:f9eeca106725 1421
Kojto 122:f9eeca106725 1422 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
Kojto 122:f9eeca106725 1423
AnnaBridge 145:64910690c574 1424 #if defined(SDMMC1)
Kojto 122:f9eeca106725 1425 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
AnnaBridge 145:64910690c574 1426 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 1427
Kojto 122:f9eeca106725 1428 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
Kojto 122:f9eeca106725 1429
Kojto 122:f9eeca106725 1430 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
Kojto 122:f9eeca106725 1431
Kojto 122:f9eeca106725 1432 #if defined(TIM8)
Kojto 122:f9eeca106725 1433 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
Kojto 122:f9eeca106725 1434 #endif /* TIM8 */
Kojto 122:f9eeca106725 1435
Kojto 122:f9eeca106725 1436 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
Kojto 122:f9eeca106725 1437
Kojto 122:f9eeca106725 1438 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
Kojto 122:f9eeca106725 1439
Kojto 122:f9eeca106725 1440 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
Kojto 122:f9eeca106725 1441
Kojto 122:f9eeca106725 1442 #if defined(TIM17)
Kojto 122:f9eeca106725 1443 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
Kojto 122:f9eeca106725 1444 #endif /* TIM17 */
Kojto 122:f9eeca106725 1445
Kojto 122:f9eeca106725 1446 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
Kojto 122:f9eeca106725 1447
Kojto 122:f9eeca106725 1448 #if defined(SAI2)
Kojto 122:f9eeca106725 1449 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
Kojto 122:f9eeca106725 1450 #endif /* SAI2 */
Kojto 122:f9eeca106725 1451
Kojto 122:f9eeca106725 1452 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 1453 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)
Kojto 122:f9eeca106725 1454 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 1455
Kojto 122:f9eeca106725 1456 /**
Kojto 122:f9eeca106725 1457 * @}
Kojto 122:f9eeca106725 1458 */
Kojto 122:f9eeca106725 1459
Kojto 122:f9eeca106725 1460 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
Kojto 122:f9eeca106725 1461 * @brief Check whether the AHB1 peripheral clock is enabled or not.
Kojto 122:f9eeca106725 1462 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 1463 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 1464 * using it.
Kojto 122:f9eeca106725 1465 * @{
Kojto 122:f9eeca106725 1466 */
Kojto 122:f9eeca106725 1467
Kojto 122:f9eeca106725 1468 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
Kojto 122:f9eeca106725 1469
Kojto 122:f9eeca106725 1470 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
Kojto 122:f9eeca106725 1471
Kojto 122:f9eeca106725 1472 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
Kojto 122:f9eeca106725 1473
Kojto 122:f9eeca106725 1474 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
Kojto 122:f9eeca106725 1475
Kojto 122:f9eeca106725 1476 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
Kojto 122:f9eeca106725 1477
AnnaBridge 145:64910690c574 1478 #if defined(DMA2D)
AnnaBridge 145:64910690c574 1479 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != RESET)
AnnaBridge 145:64910690c574 1480 #endif /* DMA2D */
AnnaBridge 145:64910690c574 1481
Kojto 122:f9eeca106725 1482
Kojto 122:f9eeca106725 1483 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
Kojto 122:f9eeca106725 1484
Kojto 122:f9eeca106725 1485 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
Kojto 122:f9eeca106725 1486
Kojto 122:f9eeca106725 1487 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
Kojto 122:f9eeca106725 1488
Kojto 122:f9eeca106725 1489 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
Kojto 122:f9eeca106725 1490
Kojto 122:f9eeca106725 1491 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
Kojto 122:f9eeca106725 1492
AnnaBridge 145:64910690c574 1493 #if defined(DMA2D)
AnnaBridge 145:64910690c574 1494 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == RESET)
AnnaBridge 145:64910690c574 1495 #endif /* DMA2D */
AnnaBridge 145:64910690c574 1496
Kojto 122:f9eeca106725 1497 /**
Kojto 122:f9eeca106725 1498 * @}
Kojto 122:f9eeca106725 1499 */
Kojto 122:f9eeca106725 1500
Kojto 122:f9eeca106725 1501 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
Kojto 122:f9eeca106725 1502 * @brief Check whether the AHB2 peripheral clock is enabled or not.
Kojto 122:f9eeca106725 1503 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 1504 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 1505 * using it.
Kojto 122:f9eeca106725 1506 * @{
Kojto 122:f9eeca106725 1507 */
Kojto 122:f9eeca106725 1508
Kojto 122:f9eeca106725 1509 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
Kojto 122:f9eeca106725 1510
Kojto 122:f9eeca106725 1511 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
Kojto 122:f9eeca106725 1512
Kojto 122:f9eeca106725 1513 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
Kojto 122:f9eeca106725 1514
Kojto 122:f9eeca106725 1515 #if defined(GPIOD)
Kojto 122:f9eeca106725 1516 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
Kojto 122:f9eeca106725 1517 #endif /* GPIOD */
Kojto 122:f9eeca106725 1518
Kojto 122:f9eeca106725 1519 #if defined(GPIOE)
Kojto 122:f9eeca106725 1520 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
Kojto 122:f9eeca106725 1521 #endif /* GPIOE */
Kojto 122:f9eeca106725 1522
Kojto 122:f9eeca106725 1523 #if defined(GPIOF)
Kojto 122:f9eeca106725 1524 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
Kojto 122:f9eeca106725 1525 #endif /* GPIOF */
Kojto 122:f9eeca106725 1526
Kojto 122:f9eeca106725 1527 #if defined(GPIOG)
Kojto 122:f9eeca106725 1528 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
Kojto 122:f9eeca106725 1529 #endif /* GPIOG */
Kojto 122:f9eeca106725 1530
Kojto 122:f9eeca106725 1531 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
Kojto 122:f9eeca106725 1532
AnnaBridge 145:64910690c574 1533 #if defined(GPIOI)
AnnaBridge 145:64910690c574 1534 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != RESET)
AnnaBridge 145:64910690c574 1535 #endif /* GPIOI */
AnnaBridge 145:64910690c574 1536
Kojto 122:f9eeca106725 1537 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 1538 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
Kojto 122:f9eeca106725 1539 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 1540
Kojto 122:f9eeca106725 1541 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
Kojto 122:f9eeca106725 1542
AnnaBridge 145:64910690c574 1543 #if defined(DCMI)
AnnaBridge 145:64910690c574 1544 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != RESET)
AnnaBridge 145:64910690c574 1545 #endif /* DCMI */
AnnaBridge 145:64910690c574 1546
Kojto 122:f9eeca106725 1547 #if defined(AES)
Kojto 122:f9eeca106725 1548 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
Kojto 122:f9eeca106725 1549 #endif /* AES */
Kojto 122:f9eeca106725 1550
AnnaBridge 145:64910690c574 1551 #if defined(HASH)
AnnaBridge 145:64910690c574 1552 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != RESET)
AnnaBridge 145:64910690c574 1553 #endif /* HASH */
AnnaBridge 145:64910690c574 1554
Kojto 122:f9eeca106725 1555 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
Kojto 122:f9eeca106725 1556
Kojto 122:f9eeca106725 1557
Kojto 122:f9eeca106725 1558 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
Kojto 122:f9eeca106725 1559
Kojto 122:f9eeca106725 1560 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
Kojto 122:f9eeca106725 1561
Kojto 122:f9eeca106725 1562 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
Kojto 122:f9eeca106725 1563
Kojto 122:f9eeca106725 1564 #if defined(GPIOD)
Kojto 122:f9eeca106725 1565 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
Kojto 122:f9eeca106725 1566 #endif /* GPIOD */
Kojto 122:f9eeca106725 1567
Kojto 122:f9eeca106725 1568 #if defined(GPIOE)
Kojto 122:f9eeca106725 1569 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
Kojto 122:f9eeca106725 1570 #endif /* GPIOE */
Kojto 122:f9eeca106725 1571
Kojto 122:f9eeca106725 1572 #if defined(GPIOF)
Kojto 122:f9eeca106725 1573 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
Kojto 122:f9eeca106725 1574 #endif /* GPIOF */
Kojto 122:f9eeca106725 1575
Kojto 122:f9eeca106725 1576 #if defined(GPIOG)
Kojto 122:f9eeca106725 1577 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
Kojto 122:f9eeca106725 1578 #endif /* GPIOG */
Kojto 122:f9eeca106725 1579
Kojto 122:f9eeca106725 1580 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
Kojto 122:f9eeca106725 1581
AnnaBridge 145:64910690c574 1582 #if defined(GPIOI)
AnnaBridge 145:64910690c574 1583 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == RESET)
AnnaBridge 145:64910690c574 1584 #endif /* GPIOI */
AnnaBridge 145:64910690c574 1585
Kojto 122:f9eeca106725 1586 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 1587 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
Kojto 122:f9eeca106725 1588 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 1589
Kojto 122:f9eeca106725 1590 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
Kojto 122:f9eeca106725 1591
AnnaBridge 145:64910690c574 1592 #if defined(DCMI)
AnnaBridge 145:64910690c574 1593 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == RESET)
AnnaBridge 145:64910690c574 1594 #endif /* DCMI */
AnnaBridge 145:64910690c574 1595
Kojto 122:f9eeca106725 1596 #if defined(AES)
Kojto 122:f9eeca106725 1597 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
Kojto 122:f9eeca106725 1598 #endif /* AES */
Kojto 122:f9eeca106725 1599
AnnaBridge 145:64910690c574 1600 #if defined(HASH)
AnnaBridge 145:64910690c574 1601 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == RESET)
AnnaBridge 145:64910690c574 1602 #endif /* HASH */
AnnaBridge 145:64910690c574 1603
Kojto 122:f9eeca106725 1604 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
Kojto 122:f9eeca106725 1605
Kojto 122:f9eeca106725 1606 /**
Kojto 122:f9eeca106725 1607 * @}
Kojto 122:f9eeca106725 1608 */
Kojto 122:f9eeca106725 1609
Kojto 122:f9eeca106725 1610 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
Kojto 122:f9eeca106725 1611 * @brief Check whether the AHB3 peripheral clock is enabled or not.
Kojto 122:f9eeca106725 1612 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 1613 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 1614 * using it.
Kojto 122:f9eeca106725 1615 * @{
Kojto 122:f9eeca106725 1616 */
Kojto 122:f9eeca106725 1617
Kojto 122:f9eeca106725 1618 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 1619 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
Kojto 122:f9eeca106725 1620 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 1621
Kojto 122:f9eeca106725 1622 #if defined(QUADSPI)
Kojto 122:f9eeca106725 1623 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
Kojto 122:f9eeca106725 1624 #endif /* QUADSPI */
Kojto 122:f9eeca106725 1625
Kojto 122:f9eeca106725 1626 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 1627 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
Kojto 122:f9eeca106725 1628 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 1629
Kojto 122:f9eeca106725 1630 #if defined(QUADSPI)
Kojto 122:f9eeca106725 1631 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
Kojto 122:f9eeca106725 1632 #endif /* QUADSPI */
Kojto 122:f9eeca106725 1633
Kojto 122:f9eeca106725 1634 /**
Kojto 122:f9eeca106725 1635 * @}
Kojto 122:f9eeca106725 1636 */
Kojto 122:f9eeca106725 1637
Kojto 122:f9eeca106725 1638 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
Kojto 122:f9eeca106725 1639 * @brief Check whether the APB1 peripheral clock is enabled or not.
Kojto 122:f9eeca106725 1640 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 1641 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 1642 * using it.
Kojto 122:f9eeca106725 1643 * @{
Kojto 122:f9eeca106725 1644 */
Kojto 122:f9eeca106725 1645
Kojto 122:f9eeca106725 1646 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
Kojto 122:f9eeca106725 1647
Kojto 122:f9eeca106725 1648 #if defined(TIM3)
Kojto 122:f9eeca106725 1649 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
Kojto 122:f9eeca106725 1650 #endif /* TIM3 */
Kojto 122:f9eeca106725 1651
Kojto 122:f9eeca106725 1652 #if defined(TIM4)
Kojto 122:f9eeca106725 1653 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
Kojto 122:f9eeca106725 1654 #endif /* TIM4 */
Kojto 122:f9eeca106725 1655
Kojto 122:f9eeca106725 1656 #if defined(TIM5)
Kojto 122:f9eeca106725 1657 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
Kojto 122:f9eeca106725 1658 #endif /* TIM5 */
Kojto 122:f9eeca106725 1659
Kojto 122:f9eeca106725 1660 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
Kojto 122:f9eeca106725 1661
Kojto 122:f9eeca106725 1662 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
Kojto 122:f9eeca106725 1663
Kojto 122:f9eeca106725 1664 #if defined(LCD)
Kojto 122:f9eeca106725 1665 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
Kojto 122:f9eeca106725 1666 #endif /* LCD */
Kojto 122:f9eeca106725 1667
Kojto 122:f9eeca106725 1668 #if defined(RCC_APB1ENR1_RTCAPBEN)
Kojto 122:f9eeca106725 1669 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET)
Kojto 122:f9eeca106725 1670 #endif /* RCC_APB1ENR1_RTCAPBEN */
Kojto 122:f9eeca106725 1671
Kojto 122:f9eeca106725 1672 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
Kojto 122:f9eeca106725 1673
Kojto 122:f9eeca106725 1674 #if defined(SPI2)
Kojto 122:f9eeca106725 1675 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
Kojto 122:f9eeca106725 1676 #endif /* SPI2 */
Kojto 122:f9eeca106725 1677
Kojto 122:f9eeca106725 1678 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
Kojto 122:f9eeca106725 1679
Kojto 122:f9eeca106725 1680 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
Kojto 122:f9eeca106725 1681
Kojto 122:f9eeca106725 1682 #if defined(USART3)
Kojto 122:f9eeca106725 1683 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
Kojto 122:f9eeca106725 1684 #endif /* USART3 */
Kojto 122:f9eeca106725 1685
Kojto 122:f9eeca106725 1686 #if defined(UART4)
Kojto 122:f9eeca106725 1687 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
Kojto 122:f9eeca106725 1688 #endif /* UART4 */
Kojto 122:f9eeca106725 1689
Kojto 122:f9eeca106725 1690 #if defined(UART5)
Kojto 122:f9eeca106725 1691 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
Kojto 122:f9eeca106725 1692 #endif /* UART5 */
Kojto 122:f9eeca106725 1693
Kojto 122:f9eeca106725 1694 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
Kojto 122:f9eeca106725 1695
Kojto 122:f9eeca106725 1696 #if defined(I2C2)
Kojto 122:f9eeca106725 1697 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
Kojto 122:f9eeca106725 1698 #endif /* I2C2 */
Kojto 122:f9eeca106725 1699
Kojto 122:f9eeca106725 1700 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
Kojto 122:f9eeca106725 1701
AnnaBridge 145:64910690c574 1702 #if defined(I2C4)
AnnaBridge 145:64910690c574 1703 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != RESET)
AnnaBridge 145:64910690c574 1704 #endif /* I2C4 */
AnnaBridge 145:64910690c574 1705
Kojto 122:f9eeca106725 1706 #if defined(CRS)
Kojto 122:f9eeca106725 1707 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET)
Kojto 122:f9eeca106725 1708 #endif /* CRS */
Kojto 122:f9eeca106725 1709
Kojto 122:f9eeca106725 1710 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
Kojto 122:f9eeca106725 1711
AnnaBridge 145:64910690c574 1712 #if defined(CAN2)
AnnaBridge 145:64910690c574 1713 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != RESET)
AnnaBridge 145:64910690c574 1714 #endif /* CAN2 */
AnnaBridge 145:64910690c574 1715
Kojto 122:f9eeca106725 1716 #if defined(USB)
Kojto 122:f9eeca106725 1717 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET)
Kojto 122:f9eeca106725 1718 #endif /* USB */
Kojto 122:f9eeca106725 1719
Kojto 122:f9eeca106725 1720 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
Kojto 122:f9eeca106725 1721
Kojto 122:f9eeca106725 1722 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
Kojto 122:f9eeca106725 1723
Kojto 122:f9eeca106725 1724 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
Kojto 122:f9eeca106725 1725
Kojto 122:f9eeca106725 1726 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
Kojto 122:f9eeca106725 1727
Kojto 122:f9eeca106725 1728 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
Kojto 122:f9eeca106725 1729
AnnaBridge 145:64910690c574 1730 #if defined(SWPMI1)
Kojto 122:f9eeca106725 1731 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
AnnaBridge 145:64910690c574 1732 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 1733
Kojto 122:f9eeca106725 1734 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
Kojto 122:f9eeca106725 1735
Kojto 122:f9eeca106725 1736
Kojto 122:f9eeca106725 1737 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
Kojto 122:f9eeca106725 1738
Kojto 122:f9eeca106725 1739 #if defined(TIM3)
Kojto 122:f9eeca106725 1740 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
Kojto 122:f9eeca106725 1741 #endif /* TIM3 */
Kojto 122:f9eeca106725 1742
Kojto 122:f9eeca106725 1743 #if defined(TIM4)
Kojto 122:f9eeca106725 1744 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
Kojto 122:f9eeca106725 1745 #endif /* TIM4 */
Kojto 122:f9eeca106725 1746
Kojto 122:f9eeca106725 1747 #if defined(TIM5)
Kojto 122:f9eeca106725 1748 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
Kojto 122:f9eeca106725 1749 #endif /* TIM5 */
Kojto 122:f9eeca106725 1750
Kojto 122:f9eeca106725 1751 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
Kojto 122:f9eeca106725 1752
Kojto 122:f9eeca106725 1753 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
Kojto 122:f9eeca106725 1754
Kojto 122:f9eeca106725 1755 #if defined(LCD)
Kojto 122:f9eeca106725 1756 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
Kojto 122:f9eeca106725 1757 #endif /* LCD */
Kojto 122:f9eeca106725 1758
Kojto 122:f9eeca106725 1759 #if defined(RCC_APB1ENR1_RTCAPBEN)
Kojto 122:f9eeca106725 1760 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET)
Kojto 122:f9eeca106725 1761 #endif /* RCC_APB1ENR1_RTCAPBEN */
Kojto 122:f9eeca106725 1762
Kojto 122:f9eeca106725 1763 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
Kojto 122:f9eeca106725 1764
Kojto 122:f9eeca106725 1765 #if defined(SPI2)
Kojto 122:f9eeca106725 1766 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
Kojto 122:f9eeca106725 1767 #endif /* SPI2 */
Kojto 122:f9eeca106725 1768
Kojto 122:f9eeca106725 1769 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
Kojto 122:f9eeca106725 1770
Kojto 122:f9eeca106725 1771 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
Kojto 122:f9eeca106725 1772
Kojto 122:f9eeca106725 1773 #if defined(USART3)
Kojto 122:f9eeca106725 1774 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
Kojto 122:f9eeca106725 1775 #endif /* USART3 */
Kojto 122:f9eeca106725 1776
Kojto 122:f9eeca106725 1777 #if defined(UART4)
Kojto 122:f9eeca106725 1778 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
Kojto 122:f9eeca106725 1779 #endif /* UART4 */
Kojto 122:f9eeca106725 1780
Kojto 122:f9eeca106725 1781 #if defined(UART5)
Kojto 122:f9eeca106725 1782 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
Kojto 122:f9eeca106725 1783 #endif /* UART5 */
Kojto 122:f9eeca106725 1784
Kojto 122:f9eeca106725 1785 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
Kojto 122:f9eeca106725 1786
Kojto 122:f9eeca106725 1787 #if defined(I2C2)
Kojto 122:f9eeca106725 1788 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
Kojto 122:f9eeca106725 1789 #endif /* I2C2 */
Kojto 122:f9eeca106725 1790
Kojto 122:f9eeca106725 1791 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
Kojto 122:f9eeca106725 1792
AnnaBridge 145:64910690c574 1793 #if defined(I2C4)
AnnaBridge 145:64910690c574 1794 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == RESET)
AnnaBridge 145:64910690c574 1795 #endif /* I2C4 */
AnnaBridge 145:64910690c574 1796
Kojto 122:f9eeca106725 1797 #if defined(CRS)
Kojto 122:f9eeca106725 1798 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET)
Kojto 122:f9eeca106725 1799 #endif /* CRS */
Kojto 122:f9eeca106725 1800
Kojto 122:f9eeca106725 1801 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
Kojto 122:f9eeca106725 1802
AnnaBridge 145:64910690c574 1803 #if defined(CAN2)
AnnaBridge 145:64910690c574 1804 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == RESET)
AnnaBridge 145:64910690c574 1805 #endif /* CAN2 */
AnnaBridge 145:64910690c574 1806
Kojto 122:f9eeca106725 1807 #if defined(USB)
Kojto 122:f9eeca106725 1808 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET)
Kojto 122:f9eeca106725 1809 #endif /* USB */
Kojto 122:f9eeca106725 1810
Kojto 122:f9eeca106725 1811 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
Kojto 122:f9eeca106725 1812
Kojto 122:f9eeca106725 1813 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
Kojto 122:f9eeca106725 1814
Kojto 122:f9eeca106725 1815 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
Kojto 122:f9eeca106725 1816
Kojto 122:f9eeca106725 1817 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
Kojto 122:f9eeca106725 1818
Kojto 122:f9eeca106725 1819 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
Kojto 122:f9eeca106725 1820
AnnaBridge 145:64910690c574 1821 #if defined(SWPMI1)
Kojto 122:f9eeca106725 1822 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
AnnaBridge 145:64910690c574 1823 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 1824
Kojto 122:f9eeca106725 1825 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
Kojto 122:f9eeca106725 1826
Kojto 122:f9eeca106725 1827 /**
Kojto 122:f9eeca106725 1828 * @}
Kojto 122:f9eeca106725 1829 */
Kojto 122:f9eeca106725 1830
Kojto 122:f9eeca106725 1831 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
Kojto 122:f9eeca106725 1832 * @brief Check whether the APB2 peripheral clock is enabled or not.
Kojto 122:f9eeca106725 1833 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 1834 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 1835 * using it.
Kojto 122:f9eeca106725 1836 * @{
Kojto 122:f9eeca106725 1837 */
Kojto 122:f9eeca106725 1838
Kojto 122:f9eeca106725 1839 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
Kojto 122:f9eeca106725 1840
Kojto 122:f9eeca106725 1841 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
Kojto 122:f9eeca106725 1842
AnnaBridge 145:64910690c574 1843 #if defined(SDMMC1)
Kojto 122:f9eeca106725 1844 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
AnnaBridge 145:64910690c574 1845 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 1846
Kojto 122:f9eeca106725 1847 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
Kojto 122:f9eeca106725 1848
Kojto 122:f9eeca106725 1849 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
Kojto 122:f9eeca106725 1850
Kojto 122:f9eeca106725 1851 #if defined(TIM8)
Kojto 122:f9eeca106725 1852 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
Kojto 122:f9eeca106725 1853 #endif /* TIM8 */
Kojto 122:f9eeca106725 1854
Kojto 122:f9eeca106725 1855 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
Kojto 122:f9eeca106725 1856
Kojto 122:f9eeca106725 1857 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
Kojto 122:f9eeca106725 1858
Kojto 122:f9eeca106725 1859 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
Kojto 122:f9eeca106725 1860
Kojto 122:f9eeca106725 1861 #if defined(TIM17)
Kojto 122:f9eeca106725 1862 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
Kojto 122:f9eeca106725 1863 #endif /* TIM17 */
Kojto 122:f9eeca106725 1864
Kojto 122:f9eeca106725 1865 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
Kojto 122:f9eeca106725 1866
Kojto 122:f9eeca106725 1867 #if defined(SAI2)
Kojto 122:f9eeca106725 1868 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
Kojto 122:f9eeca106725 1869 #endif /* SAI2 */
Kojto 122:f9eeca106725 1870
Kojto 122:f9eeca106725 1871 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 1872 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET)
Kojto 122:f9eeca106725 1873 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 1874
Kojto 122:f9eeca106725 1875
Kojto 122:f9eeca106725 1876 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
Kojto 122:f9eeca106725 1877
AnnaBridge 145:64910690c574 1878 #if defined(SDMMC1)
Kojto 122:f9eeca106725 1879 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
AnnaBridge 145:64910690c574 1880 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 1881
Kojto 122:f9eeca106725 1882 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
Kojto 122:f9eeca106725 1883
Kojto 122:f9eeca106725 1884 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
Kojto 122:f9eeca106725 1885
Kojto 122:f9eeca106725 1886 #if defined(TIM8)
Kojto 122:f9eeca106725 1887 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
Kojto 122:f9eeca106725 1888 #endif /* TIM8 */
Kojto 122:f9eeca106725 1889
Kojto 122:f9eeca106725 1890 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
Kojto 122:f9eeca106725 1891
Kojto 122:f9eeca106725 1892 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
Kojto 122:f9eeca106725 1893
Kojto 122:f9eeca106725 1894 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
Kojto 122:f9eeca106725 1895
Kojto 122:f9eeca106725 1896 #if defined(TIM17)
Kojto 122:f9eeca106725 1897 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
Kojto 122:f9eeca106725 1898 #endif /* TIM17 */
Kojto 122:f9eeca106725 1899
Kojto 122:f9eeca106725 1900 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
Kojto 122:f9eeca106725 1901
Kojto 122:f9eeca106725 1902 #if defined(SAI2)
Kojto 122:f9eeca106725 1903 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
Kojto 122:f9eeca106725 1904 #endif /* SAI2 */
Kojto 122:f9eeca106725 1905
Kojto 122:f9eeca106725 1906 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 1907 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET)
Kojto 122:f9eeca106725 1908 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 1909
Kojto 122:f9eeca106725 1910 /**
Kojto 122:f9eeca106725 1911 * @}
Kojto 122:f9eeca106725 1912 */
Kojto 122:f9eeca106725 1913
Kojto 122:f9eeca106725 1914 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
Kojto 122:f9eeca106725 1915 * @brief Force or release AHB1 peripheral reset.
Kojto 122:f9eeca106725 1916 * @{
Kojto 122:f9eeca106725 1917 */
Kojto 122:f9eeca106725 1918 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
Kojto 122:f9eeca106725 1919
Kojto 122:f9eeca106725 1920 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
Kojto 122:f9eeca106725 1921
Kojto 122:f9eeca106725 1922 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
Kojto 122:f9eeca106725 1923
Kojto 122:f9eeca106725 1924 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
Kojto 122:f9eeca106725 1925
Kojto 122:f9eeca106725 1926 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
Kojto 122:f9eeca106725 1927
Kojto 122:f9eeca106725 1928 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
Kojto 122:f9eeca106725 1929
AnnaBridge 145:64910690c574 1930 #if defined(DMA2D)
AnnaBridge 145:64910690c574 1931 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
AnnaBridge 145:64910690c574 1932 #endif /* DMA2D */
AnnaBridge 145:64910690c574 1933
Kojto 122:f9eeca106725 1934
Kojto 122:f9eeca106725 1935 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
Kojto 122:f9eeca106725 1936
Kojto 122:f9eeca106725 1937 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
Kojto 122:f9eeca106725 1938
Kojto 122:f9eeca106725 1939 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
Kojto 122:f9eeca106725 1940
Kojto 122:f9eeca106725 1941 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
Kojto 122:f9eeca106725 1942
Kojto 122:f9eeca106725 1943 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
Kojto 122:f9eeca106725 1944
Kojto 122:f9eeca106725 1945 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
Kojto 122:f9eeca106725 1946
AnnaBridge 145:64910690c574 1947 #if defined(DMA2D)
AnnaBridge 145:64910690c574 1948 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
AnnaBridge 145:64910690c574 1949 #endif /* DMA2D */
AnnaBridge 145:64910690c574 1950
Kojto 122:f9eeca106725 1951 /**
Kojto 122:f9eeca106725 1952 * @}
Kojto 122:f9eeca106725 1953 */
Kojto 122:f9eeca106725 1954
Kojto 122:f9eeca106725 1955 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
Kojto 122:f9eeca106725 1956 * @brief Force or release AHB2 peripheral reset.
Kojto 122:f9eeca106725 1957 * @{
Kojto 122:f9eeca106725 1958 */
Kojto 122:f9eeca106725 1959 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
Kojto 122:f9eeca106725 1960
Kojto 122:f9eeca106725 1961 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
Kojto 122:f9eeca106725 1962
Kojto 122:f9eeca106725 1963 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
Kojto 122:f9eeca106725 1964
Kojto 122:f9eeca106725 1965 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
Kojto 122:f9eeca106725 1966
Kojto 122:f9eeca106725 1967 #if defined(GPIOD)
Kojto 122:f9eeca106725 1968 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
Kojto 122:f9eeca106725 1969 #endif /* GPIOD */
Kojto 122:f9eeca106725 1970
Kojto 122:f9eeca106725 1971 #if defined(GPIOE)
Kojto 122:f9eeca106725 1972 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
Kojto 122:f9eeca106725 1973 #endif /* GPIOE */
Kojto 122:f9eeca106725 1974
Kojto 122:f9eeca106725 1975 #if defined(GPIOF)
Kojto 122:f9eeca106725 1976 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
Kojto 122:f9eeca106725 1977 #endif /* GPIOF */
Kojto 122:f9eeca106725 1978
Kojto 122:f9eeca106725 1979 #if defined(GPIOG)
Kojto 122:f9eeca106725 1980 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
Kojto 122:f9eeca106725 1981 #endif /* GPIOG */
Kojto 122:f9eeca106725 1982
Kojto 122:f9eeca106725 1983 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
Kojto 122:f9eeca106725 1984
AnnaBridge 145:64910690c574 1985 #if defined(GPIOI)
AnnaBridge 145:64910690c574 1986 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
AnnaBridge 145:64910690c574 1987 #endif /* GPIOI */
AnnaBridge 145:64910690c574 1988
Kojto 122:f9eeca106725 1989 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 1990 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
Kojto 122:f9eeca106725 1991 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 1992
Kojto 122:f9eeca106725 1993 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
Kojto 122:f9eeca106725 1994
AnnaBridge 145:64910690c574 1995 #if defined(DCMI)
AnnaBridge 145:64910690c574 1996 #define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
AnnaBridge 145:64910690c574 1997 #endif /* DCMI */
AnnaBridge 145:64910690c574 1998
Kojto 122:f9eeca106725 1999 #if defined(AES)
Kojto 122:f9eeca106725 2000 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
Kojto 122:f9eeca106725 2001 #endif /* AES */
Kojto 122:f9eeca106725 2002
AnnaBridge 145:64910690c574 2003 #if defined(HASH)
AnnaBridge 145:64910690c574 2004 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
AnnaBridge 145:64910690c574 2005 #endif /* HASH */
AnnaBridge 145:64910690c574 2006
Kojto 122:f9eeca106725 2007 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
Kojto 122:f9eeca106725 2008
Kojto 122:f9eeca106725 2009
Kojto 122:f9eeca106725 2010 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
Kojto 122:f9eeca106725 2011
Kojto 122:f9eeca106725 2012 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
Kojto 122:f9eeca106725 2013
Kojto 122:f9eeca106725 2014 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
Kojto 122:f9eeca106725 2015
Kojto 122:f9eeca106725 2016 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
Kojto 122:f9eeca106725 2017
Kojto 122:f9eeca106725 2018 #if defined(GPIOD)
Kojto 122:f9eeca106725 2019 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
Kojto 122:f9eeca106725 2020 #endif /* GPIOD */
Kojto 122:f9eeca106725 2021
Kojto 122:f9eeca106725 2022 #if defined(GPIOE)
Kojto 122:f9eeca106725 2023 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
Kojto 122:f9eeca106725 2024 #endif /* GPIOE */
Kojto 122:f9eeca106725 2025
Kojto 122:f9eeca106725 2026 #if defined(GPIOF)
Kojto 122:f9eeca106725 2027 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
Kojto 122:f9eeca106725 2028 #endif /* GPIOF */
Kojto 122:f9eeca106725 2029
Kojto 122:f9eeca106725 2030 #if defined(GPIOG)
Kojto 122:f9eeca106725 2031 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
Kojto 122:f9eeca106725 2032 #endif /* GPIOG */
Kojto 122:f9eeca106725 2033
Kojto 122:f9eeca106725 2034 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
Kojto 122:f9eeca106725 2035
AnnaBridge 145:64910690c574 2036 #if defined(GPIOI)
AnnaBridge 145:64910690c574 2037 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
AnnaBridge 145:64910690c574 2038 #endif /* GPIOI */
AnnaBridge 145:64910690c574 2039
Kojto 122:f9eeca106725 2040 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 2041 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
Kojto 122:f9eeca106725 2042 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 2043
Kojto 122:f9eeca106725 2044 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
Kojto 122:f9eeca106725 2045
AnnaBridge 145:64910690c574 2046 #if defined(DCMI)
AnnaBridge 145:64910690c574 2047 #define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
AnnaBridge 145:64910690c574 2048 #endif /* DCMI */
AnnaBridge 145:64910690c574 2049
Kojto 122:f9eeca106725 2050 #if defined(AES)
Kojto 122:f9eeca106725 2051 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
Kojto 122:f9eeca106725 2052 #endif /* AES */
Kojto 122:f9eeca106725 2053
AnnaBridge 145:64910690c574 2054 #if defined(HASH)
AnnaBridge 145:64910690c574 2055 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
AnnaBridge 145:64910690c574 2056 #endif /* HASH */
AnnaBridge 145:64910690c574 2057
Kojto 122:f9eeca106725 2058 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
Kojto 122:f9eeca106725 2059
Kojto 122:f9eeca106725 2060 /**
Kojto 122:f9eeca106725 2061 * @}
Kojto 122:f9eeca106725 2062 */
Kojto 122:f9eeca106725 2063
Kojto 122:f9eeca106725 2064 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
Kojto 122:f9eeca106725 2065 * @brief Force or release AHB3 peripheral reset.
Kojto 122:f9eeca106725 2066 * @{
Kojto 122:f9eeca106725 2067 */
Kojto 122:f9eeca106725 2068 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
Kojto 122:f9eeca106725 2069
Kojto 122:f9eeca106725 2070 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 2071 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
Kojto 122:f9eeca106725 2072 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 2073
Kojto 122:f9eeca106725 2074 #if defined(QUADSPI)
Kojto 122:f9eeca106725 2075 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
Kojto 122:f9eeca106725 2076 #endif /* QUADSPI */
Kojto 122:f9eeca106725 2077
Kojto 122:f9eeca106725 2078 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
Kojto 122:f9eeca106725 2079
Kojto 122:f9eeca106725 2080 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 2081 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
Kojto 122:f9eeca106725 2082 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 2083
Kojto 122:f9eeca106725 2084 #if defined(QUADSPI)
Kojto 122:f9eeca106725 2085 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
Kojto 122:f9eeca106725 2086 #endif /* QUADSPI */
Kojto 122:f9eeca106725 2087
Kojto 122:f9eeca106725 2088 /**
Kojto 122:f9eeca106725 2089 * @}
Kojto 122:f9eeca106725 2090 */
Kojto 122:f9eeca106725 2091
Kojto 122:f9eeca106725 2092 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
Kojto 122:f9eeca106725 2093 * @brief Force or release APB1 peripheral reset.
Kojto 122:f9eeca106725 2094 * @{
Kojto 122:f9eeca106725 2095 */
Kojto 122:f9eeca106725 2096 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
Kojto 122:f9eeca106725 2097
Kojto 122:f9eeca106725 2098 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
Kojto 122:f9eeca106725 2099
Kojto 122:f9eeca106725 2100 #if defined(TIM3)
Kojto 122:f9eeca106725 2101 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
Kojto 122:f9eeca106725 2102 #endif /* TIM3 */
Kojto 122:f9eeca106725 2103
Kojto 122:f9eeca106725 2104 #if defined(TIM4)
Kojto 122:f9eeca106725 2105 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
Kojto 122:f9eeca106725 2106 #endif /* TIM4 */
Kojto 122:f9eeca106725 2107
Kojto 122:f9eeca106725 2108 #if defined(TIM5)
Kojto 122:f9eeca106725 2109 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
Kojto 122:f9eeca106725 2110 #endif /* TIM5 */
Kojto 122:f9eeca106725 2111
Kojto 122:f9eeca106725 2112 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
Kojto 122:f9eeca106725 2113
Kojto 122:f9eeca106725 2114 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
Kojto 122:f9eeca106725 2115
Kojto 122:f9eeca106725 2116 #if defined(LCD)
Kojto 122:f9eeca106725 2117 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
Kojto 122:f9eeca106725 2118 #endif /* LCD */
Kojto 122:f9eeca106725 2119
Kojto 122:f9eeca106725 2120 #if defined(SPI2)
Kojto 122:f9eeca106725 2121 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
Kojto 122:f9eeca106725 2122 #endif /* SPI2 */
Kojto 122:f9eeca106725 2123
Kojto 122:f9eeca106725 2124 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
Kojto 122:f9eeca106725 2125
Kojto 122:f9eeca106725 2126 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
Kojto 122:f9eeca106725 2127
Kojto 122:f9eeca106725 2128 #if defined(USART3)
Kojto 122:f9eeca106725 2129 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
Kojto 122:f9eeca106725 2130 #endif /* USART3 */
Kojto 122:f9eeca106725 2131
Kojto 122:f9eeca106725 2132 #if defined(UART4)
Kojto 122:f9eeca106725 2133 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
Kojto 122:f9eeca106725 2134 #endif /* UART4 */
Kojto 122:f9eeca106725 2135
Kojto 122:f9eeca106725 2136 #if defined(UART5)
Kojto 122:f9eeca106725 2137 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
Kojto 122:f9eeca106725 2138 #endif /* UART5 */
Kojto 122:f9eeca106725 2139
Kojto 122:f9eeca106725 2140 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
Kojto 122:f9eeca106725 2141
Kojto 122:f9eeca106725 2142 #if defined(I2C2)
Kojto 122:f9eeca106725 2143 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
Kojto 122:f9eeca106725 2144 #endif /* I2C2 */
Kojto 122:f9eeca106725 2145
Kojto 122:f9eeca106725 2146 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
Kojto 122:f9eeca106725 2147
AnnaBridge 145:64910690c574 2148 #if defined(I2C4)
AnnaBridge 145:64910690c574 2149 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
AnnaBridge 145:64910690c574 2150 #endif /* I2C4 */
AnnaBridge 145:64910690c574 2151
Kojto 122:f9eeca106725 2152 #if defined(CRS)
Kojto 122:f9eeca106725 2153 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
Kojto 122:f9eeca106725 2154 #endif /* CRS */
Kojto 122:f9eeca106725 2155
Kojto 122:f9eeca106725 2156 #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
Kojto 122:f9eeca106725 2157
AnnaBridge 145:64910690c574 2158 #if defined(CAN2)
AnnaBridge 145:64910690c574 2159 #define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
AnnaBridge 145:64910690c574 2160 #endif /* CAN2 */
AnnaBridge 145:64910690c574 2161
Kojto 122:f9eeca106725 2162 #if defined(USB)
Kojto 122:f9eeca106725 2163 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
Kojto 122:f9eeca106725 2164 #endif /* USB */
Kojto 122:f9eeca106725 2165
Kojto 122:f9eeca106725 2166 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
Kojto 122:f9eeca106725 2167
Kojto 122:f9eeca106725 2168 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
Kojto 122:f9eeca106725 2169
Kojto 122:f9eeca106725 2170 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
Kojto 122:f9eeca106725 2171
Kojto 122:f9eeca106725 2172 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
Kojto 122:f9eeca106725 2173
Kojto 122:f9eeca106725 2174 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
Kojto 122:f9eeca106725 2175
AnnaBridge 145:64910690c574 2176 #if defined(SWPMI1)
Kojto 122:f9eeca106725 2177 #define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
AnnaBridge 145:64910690c574 2178 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 2179
Kojto 122:f9eeca106725 2180 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
Kojto 122:f9eeca106725 2181
Kojto 122:f9eeca106725 2182
Kojto 122:f9eeca106725 2183 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
Kojto 122:f9eeca106725 2184
Kojto 122:f9eeca106725 2185 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
Kojto 122:f9eeca106725 2186
Kojto 122:f9eeca106725 2187 #if defined(TIM3)
Kojto 122:f9eeca106725 2188 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
Kojto 122:f9eeca106725 2189 #endif /* TIM3 */
Kojto 122:f9eeca106725 2190
Kojto 122:f9eeca106725 2191 #if defined(TIM4)
Kojto 122:f9eeca106725 2192 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
Kojto 122:f9eeca106725 2193 #endif /* TIM4 */
Kojto 122:f9eeca106725 2194
Kojto 122:f9eeca106725 2195 #if defined(TIM5)
Kojto 122:f9eeca106725 2196 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
Kojto 122:f9eeca106725 2197 #endif /* TIM5 */
Kojto 122:f9eeca106725 2198
Kojto 122:f9eeca106725 2199 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
Kojto 122:f9eeca106725 2200
Kojto 122:f9eeca106725 2201 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
Kojto 122:f9eeca106725 2202
Kojto 122:f9eeca106725 2203 #if defined(LCD)
Kojto 122:f9eeca106725 2204 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
Kojto 122:f9eeca106725 2205 #endif /* LCD */
Kojto 122:f9eeca106725 2206
Kojto 122:f9eeca106725 2207 #if defined(SPI2)
Kojto 122:f9eeca106725 2208 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
Kojto 122:f9eeca106725 2209 #endif /* SPI2 */
Kojto 122:f9eeca106725 2210
Kojto 122:f9eeca106725 2211 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
Kojto 122:f9eeca106725 2212
Kojto 122:f9eeca106725 2213 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
Kojto 122:f9eeca106725 2214
Kojto 122:f9eeca106725 2215 #if defined(USART3)
Kojto 122:f9eeca106725 2216 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
Kojto 122:f9eeca106725 2217 #endif /* USART3 */
Kojto 122:f9eeca106725 2218
Kojto 122:f9eeca106725 2219 #if defined(UART4)
Kojto 122:f9eeca106725 2220 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
Kojto 122:f9eeca106725 2221 #endif /* UART4 */
Kojto 122:f9eeca106725 2222
Kojto 122:f9eeca106725 2223 #if defined(UART5)
Kojto 122:f9eeca106725 2224 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
Kojto 122:f9eeca106725 2225 #endif /* UART5 */
Kojto 122:f9eeca106725 2226
Kojto 122:f9eeca106725 2227 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
Kojto 122:f9eeca106725 2228
Kojto 122:f9eeca106725 2229 #if defined(I2C2)
Kojto 122:f9eeca106725 2230 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
Kojto 122:f9eeca106725 2231 #endif /* I2C2 */
Kojto 122:f9eeca106725 2232
Kojto 122:f9eeca106725 2233 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
Kojto 122:f9eeca106725 2234
AnnaBridge 145:64910690c574 2235 #if defined(I2C4)
AnnaBridge 145:64910690c574 2236 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
AnnaBridge 145:64910690c574 2237 #endif /* I2C4 */
AnnaBridge 145:64910690c574 2238
Kojto 122:f9eeca106725 2239 #if defined(CRS)
Kojto 122:f9eeca106725 2240 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
Kojto 122:f9eeca106725 2241 #endif /* CRS */
Kojto 122:f9eeca106725 2242
Kojto 122:f9eeca106725 2243 #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
Kojto 122:f9eeca106725 2244
AnnaBridge 145:64910690c574 2245 #if defined(CAN2)
AnnaBridge 145:64910690c574 2246 #define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
AnnaBridge 145:64910690c574 2247 #endif /* CAN2 */
AnnaBridge 145:64910690c574 2248
Kojto 122:f9eeca106725 2249 #if defined(USB)
Kojto 122:f9eeca106725 2250 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
Kojto 122:f9eeca106725 2251 #endif /* USB */
Kojto 122:f9eeca106725 2252
Kojto 122:f9eeca106725 2253 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
Kojto 122:f9eeca106725 2254
Kojto 122:f9eeca106725 2255 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
Kojto 122:f9eeca106725 2256
Kojto 122:f9eeca106725 2257 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
Kojto 122:f9eeca106725 2258
Kojto 122:f9eeca106725 2259 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
Kojto 122:f9eeca106725 2260
Kojto 122:f9eeca106725 2261 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
Kojto 122:f9eeca106725 2262
AnnaBridge 145:64910690c574 2263 #if defined(SWPMI1)
Kojto 122:f9eeca106725 2264 #define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
AnnaBridge 145:64910690c574 2265 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 2266
Kojto 122:f9eeca106725 2267 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
Kojto 122:f9eeca106725 2268
Kojto 122:f9eeca106725 2269 /**
Kojto 122:f9eeca106725 2270 * @}
Kojto 122:f9eeca106725 2271 */
Kojto 122:f9eeca106725 2272
Kojto 122:f9eeca106725 2273 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
Kojto 122:f9eeca106725 2274 * @brief Force or release APB2 peripheral reset.
Kojto 122:f9eeca106725 2275 * @{
Kojto 122:f9eeca106725 2276 */
Kojto 122:f9eeca106725 2277 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
Kojto 122:f9eeca106725 2278
Kojto 122:f9eeca106725 2279 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
Kojto 122:f9eeca106725 2280
AnnaBridge 145:64910690c574 2281 #if defined(SDMMC1)
Kojto 122:f9eeca106725 2282 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
AnnaBridge 145:64910690c574 2283 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 2284
Kojto 122:f9eeca106725 2285 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
Kojto 122:f9eeca106725 2286
Kojto 122:f9eeca106725 2287 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
Kojto 122:f9eeca106725 2288
Kojto 122:f9eeca106725 2289 #if defined(TIM8)
Kojto 122:f9eeca106725 2290 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
Kojto 122:f9eeca106725 2291 #endif /* TIM8 */
Kojto 122:f9eeca106725 2292
Kojto 122:f9eeca106725 2293 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
Kojto 122:f9eeca106725 2294
Kojto 122:f9eeca106725 2295 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
Kojto 122:f9eeca106725 2296
Kojto 122:f9eeca106725 2297 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
Kojto 122:f9eeca106725 2298
Kojto 122:f9eeca106725 2299 #if defined(TIM17)
Kojto 122:f9eeca106725 2300 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
Kojto 122:f9eeca106725 2301 #endif /* TIM17 */
Kojto 122:f9eeca106725 2302
Kojto 122:f9eeca106725 2303 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
Kojto 122:f9eeca106725 2304
Kojto 122:f9eeca106725 2305 #if defined(SAI2)
Kojto 122:f9eeca106725 2306 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
Kojto 122:f9eeca106725 2307 #endif /* SAI2 */
Kojto 122:f9eeca106725 2308
Kojto 122:f9eeca106725 2309 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 2310 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
Kojto 122:f9eeca106725 2311 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 2312
Kojto 122:f9eeca106725 2313
Kojto 122:f9eeca106725 2314 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
Kojto 122:f9eeca106725 2315
Kojto 122:f9eeca106725 2316 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
Kojto 122:f9eeca106725 2317
AnnaBridge 145:64910690c574 2318 #if defined(SDMMC1)
Kojto 122:f9eeca106725 2319 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
AnnaBridge 145:64910690c574 2320 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 2321
Kojto 122:f9eeca106725 2322 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
Kojto 122:f9eeca106725 2323
Kojto 122:f9eeca106725 2324 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
Kojto 122:f9eeca106725 2325
Kojto 122:f9eeca106725 2326 #if defined(TIM8)
Kojto 122:f9eeca106725 2327 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
Kojto 122:f9eeca106725 2328 #endif /* TIM8 */
Kojto 122:f9eeca106725 2329
Kojto 122:f9eeca106725 2330 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
Kojto 122:f9eeca106725 2331
Kojto 122:f9eeca106725 2332 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
Kojto 122:f9eeca106725 2333
Kojto 122:f9eeca106725 2334 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
Kojto 122:f9eeca106725 2335
Kojto 122:f9eeca106725 2336 #if defined(TIM17)
Kojto 122:f9eeca106725 2337 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
Kojto 122:f9eeca106725 2338 #endif /* TIM17 */
Kojto 122:f9eeca106725 2339
Kojto 122:f9eeca106725 2340 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
Kojto 122:f9eeca106725 2341
Kojto 122:f9eeca106725 2342 #if defined(SAI2)
Kojto 122:f9eeca106725 2343 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
Kojto 122:f9eeca106725 2344 #endif /* SAI2 */
Kojto 122:f9eeca106725 2345
Kojto 122:f9eeca106725 2346 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 2347 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
Kojto 122:f9eeca106725 2348 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 2349
Kojto 122:f9eeca106725 2350 /**
Kojto 122:f9eeca106725 2351 * @}
Kojto 122:f9eeca106725 2352 */
Kojto 122:f9eeca106725 2353
Kojto 122:f9eeca106725 2354 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
Kojto 122:f9eeca106725 2355 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 122:f9eeca106725 2356 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2357 * power consumption.
Kojto 122:f9eeca106725 2358 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2359 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2360 * @{
Kojto 122:f9eeca106725 2361 */
Kojto 122:f9eeca106725 2362
Kojto 122:f9eeca106725 2363 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
Kojto 122:f9eeca106725 2364
Kojto 122:f9eeca106725 2365 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
Kojto 122:f9eeca106725 2366
Kojto 122:f9eeca106725 2367 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
Kojto 122:f9eeca106725 2368
Kojto 122:f9eeca106725 2369 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
Kojto 122:f9eeca106725 2370
Kojto 122:f9eeca106725 2371 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
Kojto 122:f9eeca106725 2372
Kojto 122:f9eeca106725 2373 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
Kojto 122:f9eeca106725 2374
AnnaBridge 145:64910690c574 2375 #if defined(DMA2D)
AnnaBridge 145:64910690c574 2376 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
AnnaBridge 145:64910690c574 2377 #endif /* DMA2D */
AnnaBridge 145:64910690c574 2378
Kojto 122:f9eeca106725 2379
Kojto 122:f9eeca106725 2380 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
Kojto 122:f9eeca106725 2381
Kojto 122:f9eeca106725 2382 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
Kojto 122:f9eeca106725 2383
Kojto 122:f9eeca106725 2384 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
Kojto 122:f9eeca106725 2385
Kojto 122:f9eeca106725 2386 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
Kojto 122:f9eeca106725 2387
Kojto 122:f9eeca106725 2388 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
Kojto 122:f9eeca106725 2389
Kojto 122:f9eeca106725 2390 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
Kojto 122:f9eeca106725 2391
AnnaBridge 145:64910690c574 2392 #if defined(DMA2D)
AnnaBridge 145:64910690c574 2393 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
AnnaBridge 145:64910690c574 2394 #endif /* DMA2D */
AnnaBridge 145:64910690c574 2395
Kojto 122:f9eeca106725 2396 /**
Kojto 122:f9eeca106725 2397 * @}
Kojto 122:f9eeca106725 2398 */
Kojto 122:f9eeca106725 2399
Kojto 122:f9eeca106725 2400 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
Kojto 122:f9eeca106725 2401 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 122:f9eeca106725 2402 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2403 * power consumption.
Kojto 122:f9eeca106725 2404 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2405 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2406 * @{
Kojto 122:f9eeca106725 2407 */
Kojto 122:f9eeca106725 2408
Kojto 122:f9eeca106725 2409 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
Kojto 122:f9eeca106725 2410
Kojto 122:f9eeca106725 2411 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
Kojto 122:f9eeca106725 2412
Kojto 122:f9eeca106725 2413 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
Kojto 122:f9eeca106725 2414
Kojto 122:f9eeca106725 2415 #if defined(GPIOD)
Kojto 122:f9eeca106725 2416 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
Kojto 122:f9eeca106725 2417 #endif /* GPIOD */
Kojto 122:f9eeca106725 2418
Kojto 122:f9eeca106725 2419 #if defined(GPIOE)
Kojto 122:f9eeca106725 2420 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
Kojto 122:f9eeca106725 2421 #endif /* GPIOE */
Kojto 122:f9eeca106725 2422
Kojto 122:f9eeca106725 2423 #if defined(GPIOF)
Kojto 122:f9eeca106725 2424 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
Kojto 122:f9eeca106725 2425 #endif /* GPIOF */
Kojto 122:f9eeca106725 2426
Kojto 122:f9eeca106725 2427 #if defined(GPIOG)
Kojto 122:f9eeca106725 2428 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
Kojto 122:f9eeca106725 2429 #endif /* GPIOG */
Kojto 122:f9eeca106725 2430
Kojto 122:f9eeca106725 2431 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
Kojto 122:f9eeca106725 2432
AnnaBridge 145:64910690c574 2433 #if defined(GPIOI)
AnnaBridge 145:64910690c574 2434 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
AnnaBridge 145:64910690c574 2435 #endif /* GPIOI */
AnnaBridge 145:64910690c574 2436
Kojto 122:f9eeca106725 2437 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
Kojto 122:f9eeca106725 2438
Kojto 122:f9eeca106725 2439 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 2440 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
Kojto 122:f9eeca106725 2441 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 2442
Kojto 122:f9eeca106725 2443 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
Kojto 122:f9eeca106725 2444
AnnaBridge 145:64910690c574 2445 #if defined(DCMI)
AnnaBridge 145:64910690c574 2446 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
AnnaBridge 145:64910690c574 2447 #endif /* DCMI */
AnnaBridge 145:64910690c574 2448
Kojto 122:f9eeca106725 2449 #if defined(AES)
Kojto 122:f9eeca106725 2450 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
Kojto 122:f9eeca106725 2451 #endif /* AES */
Kojto 122:f9eeca106725 2452
AnnaBridge 145:64910690c574 2453 #if defined(HASH)
AnnaBridge 145:64910690c574 2454 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
AnnaBridge 145:64910690c574 2455 #endif /* HASH */
AnnaBridge 145:64910690c574 2456
Kojto 122:f9eeca106725 2457 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
Kojto 122:f9eeca106725 2458
Kojto 122:f9eeca106725 2459
Kojto 122:f9eeca106725 2460 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
Kojto 122:f9eeca106725 2461
Kojto 122:f9eeca106725 2462 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
Kojto 122:f9eeca106725 2463
Kojto 122:f9eeca106725 2464 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
Kojto 122:f9eeca106725 2465
Kojto 122:f9eeca106725 2466 #if defined(GPIOD)
Kojto 122:f9eeca106725 2467 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
Kojto 122:f9eeca106725 2468 #endif /* GPIOD */
Kojto 122:f9eeca106725 2469
Kojto 122:f9eeca106725 2470 #if defined(GPIOE)
Kojto 122:f9eeca106725 2471 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
Kojto 122:f9eeca106725 2472 #endif /* GPIOE */
Kojto 122:f9eeca106725 2473
Kojto 122:f9eeca106725 2474 #if defined(GPIOF)
Kojto 122:f9eeca106725 2475 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
Kojto 122:f9eeca106725 2476 #endif /* GPIOF */
Kojto 122:f9eeca106725 2477
Kojto 122:f9eeca106725 2478 #if defined(GPIOG)
Kojto 122:f9eeca106725 2479 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
Kojto 122:f9eeca106725 2480 #endif /* GPIOG */
Kojto 122:f9eeca106725 2481
Kojto 122:f9eeca106725 2482 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
Kojto 122:f9eeca106725 2483
AnnaBridge 145:64910690c574 2484 #if defined(GPIOI)
AnnaBridge 145:64910690c574 2485 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
AnnaBridge 145:64910690c574 2486 #endif /* GPIOI */
AnnaBridge 145:64910690c574 2487
Kojto 122:f9eeca106725 2488 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
Kojto 122:f9eeca106725 2489
Kojto 122:f9eeca106725 2490 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 2491 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
Kojto 122:f9eeca106725 2492 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 2493
Kojto 122:f9eeca106725 2494 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
Kojto 122:f9eeca106725 2495
AnnaBridge 145:64910690c574 2496 #if defined(DCMI)
AnnaBridge 145:64910690c574 2497 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
AnnaBridge 145:64910690c574 2498 #endif /* DCMI */
AnnaBridge 145:64910690c574 2499
Kojto 122:f9eeca106725 2500 #if defined(AES)
Kojto 122:f9eeca106725 2501 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
Kojto 122:f9eeca106725 2502 #endif /* AES */
Kojto 122:f9eeca106725 2503
AnnaBridge 145:64910690c574 2504 #if defined(HASH)
AnnaBridge 145:64910690c574 2505 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
AnnaBridge 145:64910690c574 2506 #endif /* HASH */
AnnaBridge 145:64910690c574 2507
Kojto 122:f9eeca106725 2508 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
Kojto 122:f9eeca106725 2509
Kojto 122:f9eeca106725 2510 /**
Kojto 122:f9eeca106725 2511 * @}
Kojto 122:f9eeca106725 2512 */
Kojto 122:f9eeca106725 2513
Kojto 122:f9eeca106725 2514 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
Kojto 122:f9eeca106725 2515 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto 122:f9eeca106725 2516 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2517 * power consumption.
Kojto 122:f9eeca106725 2518 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2519 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2520 * @{
Kojto 122:f9eeca106725 2521 */
Kojto 122:f9eeca106725 2522
Kojto 122:f9eeca106725 2523 #if defined(QUADSPI)
Kojto 122:f9eeca106725 2524 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
Kojto 122:f9eeca106725 2525 #endif /* QUADSPI */
Kojto 122:f9eeca106725 2526
Kojto 122:f9eeca106725 2527 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 2528 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
Kojto 122:f9eeca106725 2529 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 2530
Kojto 122:f9eeca106725 2531 #if defined(QUADSPI)
Kojto 122:f9eeca106725 2532 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
Kojto 122:f9eeca106725 2533 #endif /* QUADSPI */
Kojto 122:f9eeca106725 2534
Kojto 122:f9eeca106725 2535 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 2536 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
Kojto 122:f9eeca106725 2537 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 2538
Kojto 122:f9eeca106725 2539 /**
Kojto 122:f9eeca106725 2540 * @}
Kojto 122:f9eeca106725 2541 */
Kojto 122:f9eeca106725 2542
Kojto 122:f9eeca106725 2543 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
Kojto 122:f9eeca106725 2544 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 122:f9eeca106725 2545 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2546 * power consumption.
Kojto 122:f9eeca106725 2547 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2548 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2549 * @{
Kojto 122:f9eeca106725 2550 */
Kojto 122:f9eeca106725 2551
Kojto 122:f9eeca106725 2552 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
Kojto 122:f9eeca106725 2553
Kojto 122:f9eeca106725 2554 #if defined(TIM3)
Kojto 122:f9eeca106725 2555 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
Kojto 122:f9eeca106725 2556 #endif /* TIM3 */
Kojto 122:f9eeca106725 2557
Kojto 122:f9eeca106725 2558 #if defined(TIM4)
Kojto 122:f9eeca106725 2559 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
Kojto 122:f9eeca106725 2560 #endif /* TIM4 */
Kojto 122:f9eeca106725 2561
Kojto 122:f9eeca106725 2562 #if defined(TIM5)
Kojto 122:f9eeca106725 2563 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
Kojto 122:f9eeca106725 2564 #endif /* TIM5 */
Kojto 122:f9eeca106725 2565
Kojto 122:f9eeca106725 2566 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
Kojto 122:f9eeca106725 2567
Kojto 122:f9eeca106725 2568 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
Kojto 122:f9eeca106725 2569
Kojto 122:f9eeca106725 2570 #if defined(LCD)
Kojto 122:f9eeca106725 2571 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
Kojto 122:f9eeca106725 2572 #endif /* LCD */
Kojto 122:f9eeca106725 2573
Kojto 122:f9eeca106725 2574 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
Kojto 122:f9eeca106725 2575 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
Kojto 122:f9eeca106725 2576 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
Kojto 122:f9eeca106725 2577
Kojto 122:f9eeca106725 2578 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
Kojto 122:f9eeca106725 2579
Kojto 122:f9eeca106725 2580 #if defined(SPI2)
Kojto 122:f9eeca106725 2581 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
Kojto 122:f9eeca106725 2582 #endif /* SPI2 */
Kojto 122:f9eeca106725 2583
Kojto 122:f9eeca106725 2584 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
Kojto 122:f9eeca106725 2585
Kojto 122:f9eeca106725 2586 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
Kojto 122:f9eeca106725 2587
Kojto 122:f9eeca106725 2588 #if defined(USART3)
Kojto 122:f9eeca106725 2589 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
Kojto 122:f9eeca106725 2590 #endif /* USART3 */
Kojto 122:f9eeca106725 2591
Kojto 122:f9eeca106725 2592 #if defined(UART4)
Kojto 122:f9eeca106725 2593 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
Kojto 122:f9eeca106725 2594 #endif /* UART4 */
Kojto 122:f9eeca106725 2595
Kojto 122:f9eeca106725 2596 #if defined(UART5)
Kojto 122:f9eeca106725 2597 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
Kojto 122:f9eeca106725 2598 #endif /* UART5 */
Kojto 122:f9eeca106725 2599
Kojto 122:f9eeca106725 2600 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
Kojto 122:f9eeca106725 2601
Kojto 122:f9eeca106725 2602 #if defined(I2C2)
Kojto 122:f9eeca106725 2603 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
Kojto 122:f9eeca106725 2604 #endif /* I2C2 */
Kojto 122:f9eeca106725 2605
Kojto 122:f9eeca106725 2606 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
Kojto 122:f9eeca106725 2607
AnnaBridge 145:64910690c574 2608 #if defined(I2C4)
AnnaBridge 145:64910690c574 2609 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
AnnaBridge 145:64910690c574 2610 #endif /* I2C4 */
AnnaBridge 145:64910690c574 2611
Kojto 122:f9eeca106725 2612 #if defined(CRS)
Kojto 122:f9eeca106725 2613 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
Kojto 122:f9eeca106725 2614 #endif /* CRS */
Kojto 122:f9eeca106725 2615
Kojto 122:f9eeca106725 2616 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
Kojto 122:f9eeca106725 2617
AnnaBridge 145:64910690c574 2618 #if defined(CAN2)
AnnaBridge 145:64910690c574 2619 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
AnnaBridge 145:64910690c574 2620 #endif /* CAN2 */
AnnaBridge 145:64910690c574 2621
Kojto 122:f9eeca106725 2622 #if defined(USB)
Kojto 122:f9eeca106725 2623 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
Kojto 122:f9eeca106725 2624 #endif /* USB */
Kojto 122:f9eeca106725 2625
Kojto 122:f9eeca106725 2626 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
Kojto 122:f9eeca106725 2627
Kojto 122:f9eeca106725 2628 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
Kojto 122:f9eeca106725 2629
Kojto 122:f9eeca106725 2630 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
Kojto 122:f9eeca106725 2631
Kojto 122:f9eeca106725 2632 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
Kojto 122:f9eeca106725 2633
Kojto 122:f9eeca106725 2634 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
Kojto 122:f9eeca106725 2635
AnnaBridge 145:64910690c574 2636 #if defined(SWPMI1)
Kojto 122:f9eeca106725 2637 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
AnnaBridge 145:64910690c574 2638 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 2639
Kojto 122:f9eeca106725 2640 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
Kojto 122:f9eeca106725 2641
Kojto 122:f9eeca106725 2642
Kojto 122:f9eeca106725 2643 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
Kojto 122:f9eeca106725 2644
Kojto 122:f9eeca106725 2645 #if defined(TIM3)
Kojto 122:f9eeca106725 2646 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
Kojto 122:f9eeca106725 2647 #endif /* TIM3 */
Kojto 122:f9eeca106725 2648
Kojto 122:f9eeca106725 2649 #if defined(TIM4)
Kojto 122:f9eeca106725 2650 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
Kojto 122:f9eeca106725 2651 #endif /* TIM4 */
Kojto 122:f9eeca106725 2652
Kojto 122:f9eeca106725 2653 #if defined(TIM5)
Kojto 122:f9eeca106725 2654 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
Kojto 122:f9eeca106725 2655 #endif /* TIM5 */
Kojto 122:f9eeca106725 2656
Kojto 122:f9eeca106725 2657 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
Kojto 122:f9eeca106725 2658
Kojto 122:f9eeca106725 2659 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
Kojto 122:f9eeca106725 2660
Kojto 122:f9eeca106725 2661 #if defined(LCD)
Kojto 122:f9eeca106725 2662 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
Kojto 122:f9eeca106725 2663 #endif /* LCD */
Kojto 122:f9eeca106725 2664
Kojto 122:f9eeca106725 2665 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
Kojto 122:f9eeca106725 2666 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
Kojto 122:f9eeca106725 2667 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
Kojto 122:f9eeca106725 2668
Kojto 122:f9eeca106725 2669 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
Kojto 122:f9eeca106725 2670
Kojto 122:f9eeca106725 2671 #if defined(SPI2)
Kojto 122:f9eeca106725 2672 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
Kojto 122:f9eeca106725 2673 #endif /* SPI2 */
Kojto 122:f9eeca106725 2674
Kojto 122:f9eeca106725 2675 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
Kojto 122:f9eeca106725 2676
Kojto 122:f9eeca106725 2677 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
Kojto 122:f9eeca106725 2678
Kojto 122:f9eeca106725 2679 #if defined(USART3)
Kojto 122:f9eeca106725 2680 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
Kojto 122:f9eeca106725 2681 #endif /* USART3 */
Kojto 122:f9eeca106725 2682
Kojto 122:f9eeca106725 2683 #if defined(UART4)
Kojto 122:f9eeca106725 2684 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
Kojto 122:f9eeca106725 2685 #endif /* UART4 */
Kojto 122:f9eeca106725 2686
Kojto 122:f9eeca106725 2687 #if defined(UART5)
Kojto 122:f9eeca106725 2688 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
Kojto 122:f9eeca106725 2689 #endif /* UART5 */
Kojto 122:f9eeca106725 2690
Kojto 122:f9eeca106725 2691 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
Kojto 122:f9eeca106725 2692
Kojto 122:f9eeca106725 2693 #if defined(I2C2)
Kojto 122:f9eeca106725 2694 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
Kojto 122:f9eeca106725 2695 #endif /* I2C2 */
Kojto 122:f9eeca106725 2696
Kojto 122:f9eeca106725 2697 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
Kojto 122:f9eeca106725 2698
AnnaBridge 145:64910690c574 2699 #if defined(I2C4)
AnnaBridge 145:64910690c574 2700 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
AnnaBridge 145:64910690c574 2701 #endif /* I2C4 */
AnnaBridge 145:64910690c574 2702
Kojto 122:f9eeca106725 2703 #if defined(CRS)
Kojto 122:f9eeca106725 2704 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
Kojto 122:f9eeca106725 2705 #endif /* CRS */
Kojto 122:f9eeca106725 2706
Kojto 122:f9eeca106725 2707 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
Kojto 122:f9eeca106725 2708
AnnaBridge 145:64910690c574 2709 #if defined(CAN2)
AnnaBridge 145:64910690c574 2710 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
AnnaBridge 145:64910690c574 2711 #endif /* CAN2 */
AnnaBridge 145:64910690c574 2712
Kojto 122:f9eeca106725 2713 #if defined(USB)
Kojto 122:f9eeca106725 2714 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
Kojto 122:f9eeca106725 2715 #endif /* USB */
Kojto 122:f9eeca106725 2716
Kojto 122:f9eeca106725 2717 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
Kojto 122:f9eeca106725 2718
Kojto 122:f9eeca106725 2719 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
Kojto 122:f9eeca106725 2720
Kojto 122:f9eeca106725 2721 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
Kojto 122:f9eeca106725 2722
Kojto 122:f9eeca106725 2723 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
Kojto 122:f9eeca106725 2724
Kojto 122:f9eeca106725 2725 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
Kojto 122:f9eeca106725 2726
AnnaBridge 145:64910690c574 2727 #if defined(SWPMI1)
Kojto 122:f9eeca106725 2728 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
AnnaBridge 145:64910690c574 2729 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 2730
Kojto 122:f9eeca106725 2731 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
Kojto 122:f9eeca106725 2732
Kojto 122:f9eeca106725 2733 /**
Kojto 122:f9eeca106725 2734 * @}
Kojto 122:f9eeca106725 2735 */
Kojto 122:f9eeca106725 2736
Kojto 122:f9eeca106725 2737 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
Kojto 122:f9eeca106725 2738 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 122:f9eeca106725 2739 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2740 * power consumption.
Kojto 122:f9eeca106725 2741 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2742 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2743 * @{
Kojto 122:f9eeca106725 2744 */
Kojto 122:f9eeca106725 2745
Kojto 122:f9eeca106725 2746 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
Kojto 122:f9eeca106725 2747
AnnaBridge 145:64910690c574 2748 #if defined(SDMMC1)
Kojto 122:f9eeca106725 2749 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
AnnaBridge 145:64910690c574 2750 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 2751
Kojto 122:f9eeca106725 2752 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
Kojto 122:f9eeca106725 2753
Kojto 122:f9eeca106725 2754 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
Kojto 122:f9eeca106725 2755
Kojto 122:f9eeca106725 2756 #if defined(TIM8)
Kojto 122:f9eeca106725 2757 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
Kojto 122:f9eeca106725 2758 #endif /* TIM8 */
Kojto 122:f9eeca106725 2759
Kojto 122:f9eeca106725 2760 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
Kojto 122:f9eeca106725 2761
Kojto 122:f9eeca106725 2762 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
Kojto 122:f9eeca106725 2763
Kojto 122:f9eeca106725 2764 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
Kojto 122:f9eeca106725 2765
Kojto 122:f9eeca106725 2766 #if defined(TIM17)
Kojto 122:f9eeca106725 2767 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
Kojto 122:f9eeca106725 2768 #endif /* TIM17 */
Kojto 122:f9eeca106725 2769
Kojto 122:f9eeca106725 2770 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
Kojto 122:f9eeca106725 2771
Kojto 122:f9eeca106725 2772 #if defined(SAI2)
Kojto 122:f9eeca106725 2773 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
Kojto 122:f9eeca106725 2774 #endif /* SAI2 */
Kojto 122:f9eeca106725 2775
Kojto 122:f9eeca106725 2776 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 2777 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
Kojto 122:f9eeca106725 2778 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 2779
Kojto 122:f9eeca106725 2780
Kojto 122:f9eeca106725 2781 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
Kojto 122:f9eeca106725 2782
AnnaBridge 145:64910690c574 2783 #if defined(SDMMC1)
Kojto 122:f9eeca106725 2784 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
AnnaBridge 145:64910690c574 2785 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 2786
Kojto 122:f9eeca106725 2787 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
Kojto 122:f9eeca106725 2788
Kojto 122:f9eeca106725 2789 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
Kojto 122:f9eeca106725 2790
Kojto 122:f9eeca106725 2791 #if defined(TIM8)
Kojto 122:f9eeca106725 2792 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
Kojto 122:f9eeca106725 2793 #endif /* TIM8 */
Kojto 122:f9eeca106725 2794
Kojto 122:f9eeca106725 2795 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
Kojto 122:f9eeca106725 2796
Kojto 122:f9eeca106725 2797 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
Kojto 122:f9eeca106725 2798
Kojto 122:f9eeca106725 2799 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
Kojto 122:f9eeca106725 2800
Kojto 122:f9eeca106725 2801 #if defined(TIM17)
Kojto 122:f9eeca106725 2802 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
Kojto 122:f9eeca106725 2803 #endif /* TIM17 */
Kojto 122:f9eeca106725 2804
Kojto 122:f9eeca106725 2805 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
Kojto 122:f9eeca106725 2806
Kojto 122:f9eeca106725 2807 #if defined(SAI2)
Kojto 122:f9eeca106725 2808 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
Kojto 122:f9eeca106725 2809 #endif /* SAI2 */
Kojto 122:f9eeca106725 2810
Kojto 122:f9eeca106725 2811 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 2812 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
Kojto 122:f9eeca106725 2813 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 2814
Kojto 122:f9eeca106725 2815 /**
Kojto 122:f9eeca106725 2816 * @}
Kojto 122:f9eeca106725 2817 */
Kojto 122:f9eeca106725 2818
Kojto 122:f9eeca106725 2819 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
Kojto 122:f9eeca106725 2820 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto 122:f9eeca106725 2821 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2822 * power consumption.
Kojto 122:f9eeca106725 2823 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2824 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2825 * @{
Kojto 122:f9eeca106725 2826 */
Kojto 122:f9eeca106725 2827
Kojto 122:f9eeca106725 2828 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
Kojto 122:f9eeca106725 2829
Kojto 122:f9eeca106725 2830 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
Kojto 122:f9eeca106725 2831
Kojto 122:f9eeca106725 2832 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
Kojto 122:f9eeca106725 2833
Kojto 122:f9eeca106725 2834 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
Kojto 122:f9eeca106725 2835
Kojto 122:f9eeca106725 2836 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
Kojto 122:f9eeca106725 2837
Kojto 122:f9eeca106725 2838 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
Kojto 122:f9eeca106725 2839
AnnaBridge 145:64910690c574 2840 #if defined(DMA2D)
AnnaBridge 145:64910690c574 2841 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != RESET)
AnnaBridge 145:64910690c574 2842 #endif /* DMA2D */
AnnaBridge 145:64910690c574 2843
Kojto 122:f9eeca106725 2844
Kojto 122:f9eeca106725 2845 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
Kojto 122:f9eeca106725 2846
Kojto 122:f9eeca106725 2847 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
Kojto 122:f9eeca106725 2848
Kojto 122:f9eeca106725 2849 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
Kojto 122:f9eeca106725 2850
Kojto 122:f9eeca106725 2851 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
Kojto 122:f9eeca106725 2852
Kojto 122:f9eeca106725 2853 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
Kojto 122:f9eeca106725 2854
Kojto 122:f9eeca106725 2855 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
Kojto 122:f9eeca106725 2856
AnnaBridge 145:64910690c574 2857 #if defined(DMA2D)
AnnaBridge 145:64910690c574 2858 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == RESET)
AnnaBridge 145:64910690c574 2859 #endif /* DMA2D */
AnnaBridge 145:64910690c574 2860
Kojto 122:f9eeca106725 2861 /**
Kojto 122:f9eeca106725 2862 * @}
Kojto 122:f9eeca106725 2863 */
Kojto 122:f9eeca106725 2864
Kojto 122:f9eeca106725 2865 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
Kojto 122:f9eeca106725 2866 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto 122:f9eeca106725 2867 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2868 * power consumption.
Kojto 122:f9eeca106725 2869 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2870 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2871 * @{
Kojto 122:f9eeca106725 2872 */
Kojto 122:f9eeca106725 2873
Kojto 122:f9eeca106725 2874 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
Kojto 122:f9eeca106725 2875
Kojto 122:f9eeca106725 2876 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
Kojto 122:f9eeca106725 2877
Kojto 122:f9eeca106725 2878 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
Kojto 122:f9eeca106725 2879
Kojto 122:f9eeca106725 2880 #if defined(GPIOD)
Kojto 122:f9eeca106725 2881 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
Kojto 122:f9eeca106725 2882 #endif /* GPIOD */
Kojto 122:f9eeca106725 2883
Kojto 122:f9eeca106725 2884 #if defined(GPIOE)
Kojto 122:f9eeca106725 2885 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
Kojto 122:f9eeca106725 2886 #endif /* GPIOE */
Kojto 122:f9eeca106725 2887
Kojto 122:f9eeca106725 2888 #if defined(GPIOF)
Kojto 122:f9eeca106725 2889 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
Kojto 122:f9eeca106725 2890 #endif /* GPIOF */
Kojto 122:f9eeca106725 2891
Kojto 122:f9eeca106725 2892 #if defined(GPIOG)
Kojto 122:f9eeca106725 2893 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
Kojto 122:f9eeca106725 2894 #endif /* GPIOG */
Kojto 122:f9eeca106725 2895
Kojto 122:f9eeca106725 2896 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
Kojto 122:f9eeca106725 2897
AnnaBridge 145:64910690c574 2898 #if defined(GPIOI)
AnnaBridge 145:64910690c574 2899 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != RESET)
AnnaBridge 145:64910690c574 2900 #endif /* GPIOI */
AnnaBridge 145:64910690c574 2901
Kojto 122:f9eeca106725 2902 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
Kojto 122:f9eeca106725 2903
Kojto 122:f9eeca106725 2904 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 2905 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
Kojto 122:f9eeca106725 2906 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 2907
Kojto 122:f9eeca106725 2908 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
Kojto 122:f9eeca106725 2909
AnnaBridge 145:64910690c574 2910 #if defined(DCMI)
AnnaBridge 145:64910690c574 2911 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != RESET)
AnnaBridge 145:64910690c574 2912 #endif /* DCMI */
AnnaBridge 145:64910690c574 2913
Kojto 122:f9eeca106725 2914 #if defined(AES)
Kojto 122:f9eeca106725 2915 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
Kojto 122:f9eeca106725 2916 #endif /* AES */
Kojto 122:f9eeca106725 2917
AnnaBridge 145:64910690c574 2918 #if defined(HASH)
AnnaBridge 145:64910690c574 2919 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != RESET)
AnnaBridge 145:64910690c574 2920 #endif /* HASH */
AnnaBridge 145:64910690c574 2921
Kojto 122:f9eeca106725 2922 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
Kojto 122:f9eeca106725 2923
Kojto 122:f9eeca106725 2924
Kojto 122:f9eeca106725 2925 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
Kojto 122:f9eeca106725 2926
Kojto 122:f9eeca106725 2927 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
Kojto 122:f9eeca106725 2928
Kojto 122:f9eeca106725 2929 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
Kojto 122:f9eeca106725 2930
Kojto 122:f9eeca106725 2931 #if defined(GPIOD)
Kojto 122:f9eeca106725 2932 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
Kojto 122:f9eeca106725 2933 #endif /* GPIOD */
Kojto 122:f9eeca106725 2934
Kojto 122:f9eeca106725 2935 #if defined(GPIOE)
Kojto 122:f9eeca106725 2936 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
Kojto 122:f9eeca106725 2937 #endif /* GPIOE */
Kojto 122:f9eeca106725 2938
Kojto 122:f9eeca106725 2939 #if defined(GPIOF)
Kojto 122:f9eeca106725 2940 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
Kojto 122:f9eeca106725 2941 #endif /* GPIOF */
Kojto 122:f9eeca106725 2942
Kojto 122:f9eeca106725 2943 #if defined(GPIOG)
Kojto 122:f9eeca106725 2944 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
Kojto 122:f9eeca106725 2945 #endif /* GPIOG */
Kojto 122:f9eeca106725 2946
Kojto 122:f9eeca106725 2947 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
Kojto 122:f9eeca106725 2948
AnnaBridge 145:64910690c574 2949 #if defined(GPIOI)
AnnaBridge 145:64910690c574 2950 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == RESET)
AnnaBridge 145:64910690c574 2951 #endif /* GPIOI */
AnnaBridge 145:64910690c574 2952
Kojto 122:f9eeca106725 2953 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
Kojto 122:f9eeca106725 2954
Kojto 122:f9eeca106725 2955 #if defined(USB_OTG_FS)
Kojto 122:f9eeca106725 2956 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
Kojto 122:f9eeca106725 2957 #endif /* USB_OTG_FS */
Kojto 122:f9eeca106725 2958
Kojto 122:f9eeca106725 2959 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
Kojto 122:f9eeca106725 2960
AnnaBridge 145:64910690c574 2961 #if defined(DCMI)
AnnaBridge 145:64910690c574 2962 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == RESET)
AnnaBridge 145:64910690c574 2963 #endif /* DCMI */
AnnaBridge 145:64910690c574 2964
Kojto 122:f9eeca106725 2965 #if defined(AES)
Kojto 122:f9eeca106725 2966 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
Kojto 122:f9eeca106725 2967 #endif /* AES */
Kojto 122:f9eeca106725 2968
AnnaBridge 145:64910690c574 2969 #if defined(HASH)
AnnaBridge 145:64910690c574 2970 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == RESET)
AnnaBridge 145:64910690c574 2971 #endif /* HASH */
AnnaBridge 145:64910690c574 2972
Kojto 122:f9eeca106725 2973 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
Kojto 122:f9eeca106725 2974
Kojto 122:f9eeca106725 2975 /**
Kojto 122:f9eeca106725 2976 * @}
Kojto 122:f9eeca106725 2977 */
Kojto 122:f9eeca106725 2978
Kojto 122:f9eeca106725 2979 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
Kojto 122:f9eeca106725 2980 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto 122:f9eeca106725 2981 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 2982 * power consumption.
Kojto 122:f9eeca106725 2983 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 2984 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 2985 * @{
Kojto 122:f9eeca106725 2986 */
Kojto 122:f9eeca106725 2987
Kojto 122:f9eeca106725 2988 #if defined(QUADSPI)
Kojto 122:f9eeca106725 2989 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
Kojto 122:f9eeca106725 2990 #endif /* QUADSPI */
Kojto 122:f9eeca106725 2991
Kojto 122:f9eeca106725 2992 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 2993 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
Kojto 122:f9eeca106725 2994 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 2995
Kojto 122:f9eeca106725 2996 #if defined(QUADSPI)
Kojto 122:f9eeca106725 2997 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
Kojto 122:f9eeca106725 2998 #endif /* QUADSPI */
Kojto 122:f9eeca106725 2999
Kojto 122:f9eeca106725 3000 #if defined(FMC_BANK1)
Kojto 122:f9eeca106725 3001 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
Kojto 122:f9eeca106725 3002 #endif /* FMC_BANK1 */
Kojto 122:f9eeca106725 3003
Kojto 122:f9eeca106725 3004 /**
Kojto 122:f9eeca106725 3005 * @}
Kojto 122:f9eeca106725 3006 */
Kojto 122:f9eeca106725 3007
Kojto 122:f9eeca106725 3008 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
Kojto 122:f9eeca106725 3009 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto 122:f9eeca106725 3010 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 3011 * power consumption.
Kojto 122:f9eeca106725 3012 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 3013 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 3014 * @{
Kojto 122:f9eeca106725 3015 */
Kojto 122:f9eeca106725 3016
Kojto 122:f9eeca106725 3017 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
Kojto 122:f9eeca106725 3018
Kojto 122:f9eeca106725 3019 #if defined(TIM3)
Kojto 122:f9eeca106725 3020 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
Kojto 122:f9eeca106725 3021 #endif /* TIM3 */
Kojto 122:f9eeca106725 3022
Kojto 122:f9eeca106725 3023 #if defined(TIM4)
Kojto 122:f9eeca106725 3024 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
Kojto 122:f9eeca106725 3025 #endif /* TIM4 */
Kojto 122:f9eeca106725 3026
Kojto 122:f9eeca106725 3027 #if defined(TIM5)
Kojto 122:f9eeca106725 3028 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
Kojto 122:f9eeca106725 3029 #endif /* TIM5 */
Kojto 122:f9eeca106725 3030
Kojto 122:f9eeca106725 3031 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
Kojto 122:f9eeca106725 3032
Kojto 122:f9eeca106725 3033 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
Kojto 122:f9eeca106725 3034
Kojto 122:f9eeca106725 3035 #if defined(LCD)
Kojto 122:f9eeca106725 3036 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
Kojto 122:f9eeca106725 3037 #endif /* LCD */
Kojto 122:f9eeca106725 3038
Kojto 122:f9eeca106725 3039 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
Kojto 122:f9eeca106725 3040 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET)
Kojto 122:f9eeca106725 3041 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
Kojto 122:f9eeca106725 3042
Kojto 122:f9eeca106725 3043 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
Kojto 122:f9eeca106725 3044
Kojto 122:f9eeca106725 3045 #if defined(SPI2)
Kojto 122:f9eeca106725 3046 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
Kojto 122:f9eeca106725 3047 #endif /* SPI2 */
Kojto 122:f9eeca106725 3048
Kojto 122:f9eeca106725 3049 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
Kojto 122:f9eeca106725 3050
Kojto 122:f9eeca106725 3051 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
Kojto 122:f9eeca106725 3052
Kojto 122:f9eeca106725 3053 #if defined(USART3)
Kojto 122:f9eeca106725 3054 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
Kojto 122:f9eeca106725 3055 #endif /* USART3 */
Kojto 122:f9eeca106725 3056
Kojto 122:f9eeca106725 3057 #if defined(UART4)
Kojto 122:f9eeca106725 3058 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
Kojto 122:f9eeca106725 3059 #endif /* UART4 */
Kojto 122:f9eeca106725 3060
Kojto 122:f9eeca106725 3061 #if defined(UART5)
Kojto 122:f9eeca106725 3062 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
Kojto 122:f9eeca106725 3063 #endif /* UART5 */
Kojto 122:f9eeca106725 3064
Kojto 122:f9eeca106725 3065 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
Kojto 122:f9eeca106725 3066
Kojto 122:f9eeca106725 3067 #if defined(I2C2)
Kojto 122:f9eeca106725 3068 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
Kojto 122:f9eeca106725 3069 #endif /* I2C2 */
Kojto 122:f9eeca106725 3070
Kojto 122:f9eeca106725 3071 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
Kojto 122:f9eeca106725 3072
AnnaBridge 145:64910690c574 3073 #if defined(I2C4)
AnnaBridge 145:64910690c574 3074 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != RESET)
AnnaBridge 145:64910690c574 3075 #endif /* I2C4 */
AnnaBridge 145:64910690c574 3076
Kojto 122:f9eeca106725 3077 #if defined(CRS)
Kojto 122:f9eeca106725 3078 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET)
Kojto 122:f9eeca106725 3079 #endif /* CRS */
Kojto 122:f9eeca106725 3080
Kojto 122:f9eeca106725 3081 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
Kojto 122:f9eeca106725 3082
AnnaBridge 145:64910690c574 3083 #if defined(CAN2)
AnnaBridge 145:64910690c574 3084 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != RESET)
AnnaBridge 145:64910690c574 3085 #endif /* CAN2 */
AnnaBridge 145:64910690c574 3086
Kojto 122:f9eeca106725 3087 #if defined(USB)
Kojto 122:f9eeca106725 3088 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET)
Kojto 122:f9eeca106725 3089 #endif /* USB */
Kojto 122:f9eeca106725 3090
Kojto 122:f9eeca106725 3091 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
Kojto 122:f9eeca106725 3092
Kojto 122:f9eeca106725 3093 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
Kojto 122:f9eeca106725 3094
Kojto 122:f9eeca106725 3095 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
Kojto 122:f9eeca106725 3096
Kojto 122:f9eeca106725 3097 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
Kojto 122:f9eeca106725 3098
Kojto 122:f9eeca106725 3099 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
Kojto 122:f9eeca106725 3100
AnnaBridge 145:64910690c574 3101 #if defined(SWPMI1)
Kojto 122:f9eeca106725 3102 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
AnnaBridge 145:64910690c574 3103 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 3104
Kojto 122:f9eeca106725 3105 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
Kojto 122:f9eeca106725 3106
Kojto 122:f9eeca106725 3107
Kojto 122:f9eeca106725 3108 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
Kojto 122:f9eeca106725 3109
Kojto 122:f9eeca106725 3110 #if defined(TIM3)
Kojto 122:f9eeca106725 3111 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
Kojto 122:f9eeca106725 3112 #endif /* TIM3 */
Kojto 122:f9eeca106725 3113
Kojto 122:f9eeca106725 3114 #if defined(TIM4)
Kojto 122:f9eeca106725 3115 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
Kojto 122:f9eeca106725 3116 #endif /* TIM4 */
Kojto 122:f9eeca106725 3117
Kojto 122:f9eeca106725 3118 #if defined(TIM5)
Kojto 122:f9eeca106725 3119 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
Kojto 122:f9eeca106725 3120 #endif /* TIM5 */
Kojto 122:f9eeca106725 3121
Kojto 122:f9eeca106725 3122 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
Kojto 122:f9eeca106725 3123
Kojto 122:f9eeca106725 3124 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
Kojto 122:f9eeca106725 3125
Kojto 122:f9eeca106725 3126 #if defined(LCD)
Kojto 122:f9eeca106725 3127 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
Kojto 122:f9eeca106725 3128 #endif /* LCD */
Kojto 122:f9eeca106725 3129
Kojto 122:f9eeca106725 3130 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
Kojto 122:f9eeca106725 3131 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET)
Kojto 122:f9eeca106725 3132 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
Kojto 122:f9eeca106725 3133
Kojto 122:f9eeca106725 3134 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
Kojto 122:f9eeca106725 3135
Kojto 122:f9eeca106725 3136 #if defined(SPI2)
Kojto 122:f9eeca106725 3137 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
Kojto 122:f9eeca106725 3138 #endif /* SPI2 */
Kojto 122:f9eeca106725 3139
Kojto 122:f9eeca106725 3140 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
Kojto 122:f9eeca106725 3141
Kojto 122:f9eeca106725 3142 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
Kojto 122:f9eeca106725 3143
Kojto 122:f9eeca106725 3144 #if defined(USART3)
Kojto 122:f9eeca106725 3145 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
Kojto 122:f9eeca106725 3146 #endif /* USART3 */
Kojto 122:f9eeca106725 3147
Kojto 122:f9eeca106725 3148 #if defined(UART4)
Kojto 122:f9eeca106725 3149 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
Kojto 122:f9eeca106725 3150 #endif /* UART4 */
Kojto 122:f9eeca106725 3151
Kojto 122:f9eeca106725 3152 #if defined(UART5)
Kojto 122:f9eeca106725 3153 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
Kojto 122:f9eeca106725 3154 #endif /* UART5 */
Kojto 122:f9eeca106725 3155
Kojto 122:f9eeca106725 3156 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
Kojto 122:f9eeca106725 3157
Kojto 122:f9eeca106725 3158 #if defined(I2C2)
Kojto 122:f9eeca106725 3159 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
Kojto 122:f9eeca106725 3160 #endif /* I2C2 */
Kojto 122:f9eeca106725 3161
Kojto 122:f9eeca106725 3162 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
Kojto 122:f9eeca106725 3163
AnnaBridge 145:64910690c574 3164 #if defined(I2C4)
AnnaBridge 145:64910690c574 3165 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == RESET)
AnnaBridge 145:64910690c574 3166 #endif /* I2C4 */
AnnaBridge 145:64910690c574 3167
Kojto 122:f9eeca106725 3168 #if defined(CRS)
Kojto 122:f9eeca106725 3169 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET)
Kojto 122:f9eeca106725 3170 #endif /* CRS */
Kojto 122:f9eeca106725 3171
Kojto 122:f9eeca106725 3172 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
Kojto 122:f9eeca106725 3173
AnnaBridge 145:64910690c574 3174 #if defined(CAN2)
AnnaBridge 145:64910690c574 3175 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == RESET)
AnnaBridge 145:64910690c574 3176 #endif /* CAN2 */
AnnaBridge 145:64910690c574 3177
Kojto 122:f9eeca106725 3178 #if defined(USB)
Kojto 122:f9eeca106725 3179 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET)
Kojto 122:f9eeca106725 3180 #endif /* USB */
Kojto 122:f9eeca106725 3181
Kojto 122:f9eeca106725 3182 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
Kojto 122:f9eeca106725 3183
Kojto 122:f9eeca106725 3184 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
Kojto 122:f9eeca106725 3185
Kojto 122:f9eeca106725 3186 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
Kojto 122:f9eeca106725 3187
Kojto 122:f9eeca106725 3188 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
Kojto 122:f9eeca106725 3189
Kojto 122:f9eeca106725 3190 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
Kojto 122:f9eeca106725 3191
AnnaBridge 145:64910690c574 3192 #if defined(SWPMI1)
Kojto 122:f9eeca106725 3193 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
AnnaBridge 145:64910690c574 3194 #endif /* SWPMI1 */
Kojto 122:f9eeca106725 3195
Kojto 122:f9eeca106725 3196 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
Kojto 122:f9eeca106725 3197
Kojto 122:f9eeca106725 3198 /**
Kojto 122:f9eeca106725 3199 * @}
Kojto 122:f9eeca106725 3200 */
Kojto 122:f9eeca106725 3201
Kojto 122:f9eeca106725 3202 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
Kojto 122:f9eeca106725 3203 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto 122:f9eeca106725 3204 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 3205 * power consumption.
Kojto 122:f9eeca106725 3206 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 3207 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 3208 * @{
Kojto 122:f9eeca106725 3209 */
Kojto 122:f9eeca106725 3210
Kojto 122:f9eeca106725 3211 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
Kojto 122:f9eeca106725 3212
AnnaBridge 145:64910690c574 3213 #if defined(SDMMC1)
Kojto 122:f9eeca106725 3214 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
AnnaBridge 145:64910690c574 3215 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 3216
Kojto 122:f9eeca106725 3217 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
Kojto 122:f9eeca106725 3218
Kojto 122:f9eeca106725 3219 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
Kojto 122:f9eeca106725 3220
Kojto 122:f9eeca106725 3221 #if defined(TIM8)
Kojto 122:f9eeca106725 3222 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
Kojto 122:f9eeca106725 3223 #endif /* TIM8 */
Kojto 122:f9eeca106725 3224
Kojto 122:f9eeca106725 3225 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
Kojto 122:f9eeca106725 3226
Kojto 122:f9eeca106725 3227 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
Kojto 122:f9eeca106725 3228
Kojto 122:f9eeca106725 3229 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
Kojto 122:f9eeca106725 3230
Kojto 122:f9eeca106725 3231 #if defined(TIM17)
Kojto 122:f9eeca106725 3232 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
Kojto 122:f9eeca106725 3233 #endif /* TIM17 */
Kojto 122:f9eeca106725 3234
Kojto 122:f9eeca106725 3235 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
Kojto 122:f9eeca106725 3236
Kojto 122:f9eeca106725 3237 #if defined(SAI2)
Kojto 122:f9eeca106725 3238 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
Kojto 122:f9eeca106725 3239 #endif /* SAI2 */
Kojto 122:f9eeca106725 3240
Kojto 122:f9eeca106725 3241 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 3242 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET)
Kojto 122:f9eeca106725 3243 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 3244
Kojto 122:f9eeca106725 3245
Kojto 122:f9eeca106725 3246 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
Kojto 122:f9eeca106725 3247
AnnaBridge 145:64910690c574 3248 #if defined(SDMMC1)
Kojto 122:f9eeca106725 3249 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
AnnaBridge 145:64910690c574 3250 #endif /* SDMMC1 */
Kojto 122:f9eeca106725 3251
Kojto 122:f9eeca106725 3252 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
Kojto 122:f9eeca106725 3253
Kojto 122:f9eeca106725 3254 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
Kojto 122:f9eeca106725 3255
Kojto 122:f9eeca106725 3256 #if defined(TIM8)
Kojto 122:f9eeca106725 3257 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
Kojto 122:f9eeca106725 3258 #endif /* TIM8 */
Kojto 122:f9eeca106725 3259
Kojto 122:f9eeca106725 3260 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
Kojto 122:f9eeca106725 3261
Kojto 122:f9eeca106725 3262 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
Kojto 122:f9eeca106725 3263
Kojto 122:f9eeca106725 3264 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
Kojto 122:f9eeca106725 3265
Kojto 122:f9eeca106725 3266 #if defined(TIM17)
Kojto 122:f9eeca106725 3267 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
Kojto 122:f9eeca106725 3268 #endif /* TIM17 */
Kojto 122:f9eeca106725 3269
Kojto 122:f9eeca106725 3270 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
Kojto 122:f9eeca106725 3271
Kojto 122:f9eeca106725 3272 #if defined(SAI2)
Kojto 122:f9eeca106725 3273 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
Kojto 122:f9eeca106725 3274 #endif /* SAI2 */
Kojto 122:f9eeca106725 3275
Kojto 122:f9eeca106725 3276 #if defined(DFSDM1_Filter0)
Kojto 122:f9eeca106725 3277 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET)
Kojto 122:f9eeca106725 3278 #endif /* DFSDM1_Filter0 */
Kojto 122:f9eeca106725 3279
Kojto 122:f9eeca106725 3280 /**
Kojto 122:f9eeca106725 3281 * @}
Kojto 122:f9eeca106725 3282 */
Kojto 122:f9eeca106725 3283
Kojto 122:f9eeca106725 3284 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
Kojto 122:f9eeca106725 3285 * @{
Kojto 122:f9eeca106725 3286 */
Kojto 122:f9eeca106725 3287
Kojto 122:f9eeca106725 3288 /** @brief Macros to force or release the Backup domain reset.
Kojto 122:f9eeca106725 3289 * @note This function resets the RTC peripheral (including the backup registers)
Kojto 122:f9eeca106725 3290 * and the RTC clock source selection in RCC_CSR register.
Kojto 122:f9eeca106725 3291 * @note The BKPSRAM is not affected by this reset.
Kojto 122:f9eeca106725 3292 * @retval None
Kojto 122:f9eeca106725 3293 */
Kojto 122:f9eeca106725 3294 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto 122:f9eeca106725 3295
Kojto 122:f9eeca106725 3296 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto 122:f9eeca106725 3297
Kojto 122:f9eeca106725 3298 /**
Kojto 122:f9eeca106725 3299 * @}
Kojto 122:f9eeca106725 3300 */
Kojto 122:f9eeca106725 3301
Kojto 122:f9eeca106725 3302 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
Kojto 122:f9eeca106725 3303 * @{
Kojto 122:f9eeca106725 3304 */
Kojto 122:f9eeca106725 3305
Kojto 122:f9eeca106725 3306 /** @brief Macros to enable or disable the RTC clock.
Kojto 122:f9eeca106725 3307 * @note As the RTC is in the Backup domain and write access is denied to
Kojto 122:f9eeca106725 3308 * this domain after reset, you have to enable write access using
Kojto 122:f9eeca106725 3309 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC
Kojto 122:f9eeca106725 3310 * (to be done once after reset).
Kojto 122:f9eeca106725 3311 * @note These macros must be used after the RTC clock source was selected.
Kojto 122:f9eeca106725 3312 * @retval None
Kojto 122:f9eeca106725 3313 */
Kojto 122:f9eeca106725 3314 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto 122:f9eeca106725 3315
Kojto 122:f9eeca106725 3316 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto 122:f9eeca106725 3317
Kojto 122:f9eeca106725 3318 /**
Kojto 122:f9eeca106725 3319 * @}
Kojto 122:f9eeca106725 3320 */
Kojto 122:f9eeca106725 3321
Kojto 122:f9eeca106725 3322 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
Kojto 122:f9eeca106725 3323 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 3324 * It is used (enabled by hardware) as system clock source after startup
Kojto 122:f9eeca106725 3325 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto 122:f9eeca106725 3326 * of the HSE used directly or indirectly as system clock (if the Clock
Kojto 122:f9eeca106725 3327 * Security System CSS is enabled).
Kojto 122:f9eeca106725 3328 * @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto 122:f9eeca106725 3329 * you have to select another source of the system clock then stop the HSI.
Kojto 122:f9eeca106725 3330 * @note After enabling the HSI, the application software should wait on HSIRDY
Kojto 122:f9eeca106725 3331 * flag to be set indicating that HSI clock is stable and can be used as
Kojto 122:f9eeca106725 3332 * system clock source.
Kojto 122:f9eeca106725 3333 * This parameter can be: ENABLE or DISABLE.
Kojto 122:f9eeca106725 3334 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto 122:f9eeca106725 3335 * clock cycles.
Kojto 122:f9eeca106725 3336 * @retval None
Kojto 122:f9eeca106725 3337 */
Kojto 122:f9eeca106725 3338 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Kojto 122:f9eeca106725 3339
Kojto 122:f9eeca106725 3340 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
Kojto 122:f9eeca106725 3341
Kojto 122:f9eeca106725 3342 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
Kojto 122:f9eeca106725 3343 * @note The calibration is used to compensate for the variations in voltage
Kojto 122:f9eeca106725 3344 * and temperature that influence the frequency of the internal HSI RC.
Kojto 122:f9eeca106725 3345 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value
Kojto 122:f9eeca106725 3346 * (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge 145:64910690c574 3347 * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices).
Kojto 122:f9eeca106725 3348 * @retval None
Kojto 122:f9eeca106725 3349 */
Kojto 122:f9eeca106725 3350 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
Kojto 122:f9eeca106725 3351 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
Kojto 122:f9eeca106725 3352
Kojto 122:f9eeca106725 3353 /**
Kojto 122:f9eeca106725 3354 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
Kojto 122:f9eeca106725 3355 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
Kojto 122:f9eeca106725 3356 * @note The enable of this function has not effect on the HSION bit.
Kojto 122:f9eeca106725 3357 * This parameter can be: ENABLE or DISABLE.
Kojto 122:f9eeca106725 3358 * @retval None
Kojto 122:f9eeca106725 3359 */
Kojto 122:f9eeca106725 3360 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
Kojto 122:f9eeca106725 3361
Kojto 122:f9eeca106725 3362 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
Kojto 122:f9eeca106725 3363
Kojto 122:f9eeca106725 3364 /**
Kojto 122:f9eeca106725 3365 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
Kojto 122:f9eeca106725 3366 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
Kojto 122:f9eeca106725 3367 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
Kojto 122:f9eeca106725 3368 * speed because of the HSI startup time.
Kojto 122:f9eeca106725 3369 * @note The enable of this function has not effect on the HSION bit.
Kojto 122:f9eeca106725 3370 * This parameter can be: ENABLE or DISABLE.
Kojto 122:f9eeca106725 3371 * @retval None
Kojto 122:f9eeca106725 3372 */
Kojto 122:f9eeca106725 3373 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Kojto 122:f9eeca106725 3374
Kojto 122:f9eeca106725 3375 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
Kojto 122:f9eeca106725 3376
Kojto 122:f9eeca106725 3377 /**
Kojto 122:f9eeca106725 3378 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
Kojto 122:f9eeca106725 3379 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 3380 * It is used (enabled by hardware) as system clock source after
Kojto 122:f9eeca106725 3381 * startup from Reset, wakeup from STOP and STANDBY mode, or in case
Kojto 122:f9eeca106725 3382 * of failure of the HSE used directly or indirectly as system clock
Kojto 122:f9eeca106725 3383 * (if the Clock Security System CSS is enabled).
Kojto 122:f9eeca106725 3384 * @note MSI can not be stopped if it is used as system clock source.
Kojto 122:f9eeca106725 3385 * In this case, you have to select another source of the system
Kojto 122:f9eeca106725 3386 * clock then stop the MSI.
Kojto 122:f9eeca106725 3387 * @note After enabling the MSI, the application software should wait on
Kojto 122:f9eeca106725 3388 * MSIRDY flag to be set indicating that MSI clock is stable and can
Kojto 122:f9eeca106725 3389 * be used as system clock source.
Kojto 122:f9eeca106725 3390 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
Kojto 122:f9eeca106725 3391 * clock cycles.
Kojto 122:f9eeca106725 3392 * @retval None
Kojto 122:f9eeca106725 3393 */
Kojto 122:f9eeca106725 3394 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
Kojto 122:f9eeca106725 3395
Kojto 122:f9eeca106725 3396 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
Kojto 122:f9eeca106725 3397
Kojto 122:f9eeca106725 3398 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
Kojto 122:f9eeca106725 3399 * @note The calibration is used to compensate for the variations in voltage
Kojto 122:f9eeca106725 3400 * and temperature that influence the frequency of the internal MSI RC.
Kojto 122:f9eeca106725 3401 * Refer to the Application Note AN3300 for more details on how to
Kojto 122:f9eeca106725 3402 * calibrate the MSI.
Kojto 122:f9eeca106725 3403 * @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value
Kojto 122:f9eeca106725 3404 * (default is RCC_MSICALIBRATION_DEFAULT).
Kojto 122:f9eeca106725 3405 * This parameter must be a number between 0 and 255.
Kojto 122:f9eeca106725 3406 * @retval None
Kojto 122:f9eeca106725 3407 */
Kojto 122:f9eeca106725 3408 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
Kojto 122:f9eeca106725 3409 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
Kojto 122:f9eeca106725 3410
Kojto 122:f9eeca106725 3411 /**
Kojto 122:f9eeca106725 3412 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
Kojto 122:f9eeca106725 3413 * @note After restart from Reset , the MSI clock is around 4 MHz.
Kojto 122:f9eeca106725 3414 * After stop the startup clock can be MSI (at any of its possible
Kojto 122:f9eeca106725 3415 * frequencies, the one that was used before entering stop mode) or HSI.
Kojto 122:f9eeca106725 3416 * After Standby its frequency can be selected between 4 possible values
Kojto 122:f9eeca106725 3417 * (1, 2, 4 or 8 MHz).
Kojto 122:f9eeca106725 3418 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
Kojto 122:f9eeca106725 3419 * (MSIRDY=1).
Kojto 122:f9eeca106725 3420 * @note The MSI clock range after reset can be modified on the fly.
Kojto 122:f9eeca106725 3421 * @param __MSIRANGEVALUE__: specifies the MSI clock range.
Kojto 122:f9eeca106725 3422 * This parameter must be one of the following values:
Kojto 122:f9eeca106725 3423 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
Kojto 122:f9eeca106725 3424 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
Kojto 122:f9eeca106725 3425 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
Kojto 122:f9eeca106725 3426 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
Kojto 122:f9eeca106725 3427 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
AnnaBridge 145:64910690c574 3428 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
AnnaBridge 145:64910690c574 3429 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
AnnaBridge 145:64910690c574 3430 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
Kojto 122:f9eeca106725 3431 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
Kojto 122:f9eeca106725 3432 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
Kojto 122:f9eeca106725 3433 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
Kojto 122:f9eeca106725 3434 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
Kojto 122:f9eeca106725 3435 * @retval None
Kojto 122:f9eeca106725 3436 */
Kojto 122:f9eeca106725 3437 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
Kojto 122:f9eeca106725 3438 do { \
Kojto 122:f9eeca106725 3439 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
Kojto 122:f9eeca106725 3440 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
Kojto 122:f9eeca106725 3441 } while(0)
Kojto 122:f9eeca106725 3442
Kojto 122:f9eeca106725 3443 /**
Kojto 122:f9eeca106725 3444 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
Kojto 122:f9eeca106725 3445 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
Kojto 122:f9eeca106725 3446 * @param __MSIRANGEVALUE__: specifies the MSI clock range.
Kojto 122:f9eeca106725 3447 * This parameter must be one of the following values:
Kojto 122:f9eeca106725 3448 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
AnnaBridge 145:64910690c574 3449 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
AnnaBridge 145:64910690c574 3450 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
AnnaBridge 145:64910690c574 3451 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
Kojto 122:f9eeca106725 3452 * @retval None
Kojto 122:f9eeca106725 3453 */
Kojto 122:f9eeca106725 3454 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
Kojto 122:f9eeca106725 3455 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
Kojto 122:f9eeca106725 3456
Kojto 122:f9eeca106725 3457 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
Kojto 122:f9eeca106725 3458 * @retval MSI clock range.
Kojto 122:f9eeca106725 3459 * This parameter must be one of the following values:
Kojto 122:f9eeca106725 3460 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
Kojto 122:f9eeca106725 3461 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
Kojto 122:f9eeca106725 3462 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
Kojto 122:f9eeca106725 3463 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
Kojto 122:f9eeca106725 3464 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
AnnaBridge 145:64910690c574 3465 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
AnnaBridge 145:64910690c574 3466 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
AnnaBridge 145:64910690c574 3467 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
Kojto 122:f9eeca106725 3468 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
Kojto 122:f9eeca106725 3469 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
Kojto 122:f9eeca106725 3470 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
Kojto 122:f9eeca106725 3471 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
Kojto 122:f9eeca106725 3472 */
Kojto 122:f9eeca106725 3473 #define __HAL_RCC_GET_MSI_RANGE() \
Kojto 122:f9eeca106725 3474 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \
Kojto 122:f9eeca106725 3475 (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \
Kojto 122:f9eeca106725 3476 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
Kojto 122:f9eeca106725 3477
Kojto 122:f9eeca106725 3478 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto 122:f9eeca106725 3479 * @note After enabling the LSI, the application software should wait on
Kojto 122:f9eeca106725 3480 * LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto 122:f9eeca106725 3481 * be used to clock the IWDG and/or the RTC.
Kojto 122:f9eeca106725 3482 * @note LSI can not be disabled if the IWDG is running.
Kojto 122:f9eeca106725 3483 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto 122:f9eeca106725 3484 * clock cycles.
Kojto 122:f9eeca106725 3485 * @retval None
Kojto 122:f9eeca106725 3486 */
Kojto 122:f9eeca106725 3487 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto 122:f9eeca106725 3488
Kojto 122:f9eeca106725 3489 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto 122:f9eeca106725 3490
Kojto 122:f9eeca106725 3491 /**
Kojto 122:f9eeca106725 3492 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 122:f9eeca106725 3493 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
Kojto 122:f9eeca106725 3494 * supported by this macro. User should request a transition to HSE Off
Kojto 122:f9eeca106725 3495 * first and then HSE On or HSE Bypass.
Kojto 122:f9eeca106725 3496 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto 122:f9eeca106725 3497 * software should wait on HSERDY flag to be set indicating that HSE clock
Kojto 122:f9eeca106725 3498 * is stable and can be used to clock the PLL and/or system clock.
Kojto 122:f9eeca106725 3499 * @note HSE state can not be changed if it is used directly or through the
Kojto 122:f9eeca106725 3500 * PLL as system clock. In this case, you have to select another source
Kojto 122:f9eeca106725 3501 * of the system clock then change the HSE state (ex. disable it).
Kojto 122:f9eeca106725 3502 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 3503 * @note This function reset the CSSON bit, so if the clock security system(CSS)
Kojto 122:f9eeca106725 3504 * was previously enabled you have to enable it again after calling this
Kojto 122:f9eeca106725 3505 * function.
Kojto 122:f9eeca106725 3506 * @param __STATE__: specifies the new state of the HSE.
Kojto 122:f9eeca106725 3507 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3508 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto 122:f9eeca106725 3509 * 6 HSE oscillator clock cycles.
Kojto 122:f9eeca106725 3510 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
Kojto 122:f9eeca106725 3511 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
Kojto 122:f9eeca106725 3512 * @retval None
Kojto 122:f9eeca106725 3513 */
Kojto 122:f9eeca106725 3514 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
Kojto 122:f9eeca106725 3515 do { \
Kojto 122:f9eeca106725 3516 if((__STATE__) == RCC_HSE_ON) \
Kojto 122:f9eeca106725 3517 { \
Kojto 122:f9eeca106725 3518 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 122:f9eeca106725 3519 } \
Kojto 122:f9eeca106725 3520 else if((__STATE__) == RCC_HSE_BYPASS) \
Kojto 122:f9eeca106725 3521 { \
Kojto 122:f9eeca106725 3522 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 122:f9eeca106725 3523 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 122:f9eeca106725 3524 } \
Kojto 122:f9eeca106725 3525 else \
Kojto 122:f9eeca106725 3526 { \
Kojto 122:f9eeca106725 3527 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 122:f9eeca106725 3528 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 122:f9eeca106725 3529 } \
Kojto 122:f9eeca106725 3530 } while(0)
Kojto 122:f9eeca106725 3531
Kojto 122:f9eeca106725 3532 /**
Kojto 122:f9eeca106725 3533 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 122:f9eeca106725 3534 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
Kojto 122:f9eeca106725 3535 * supported by this macro. User should request a transition to LSE Off
Kojto 122:f9eeca106725 3536 * first and then LSE On or LSE Bypass.
Kojto 122:f9eeca106725 3537 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 122:f9eeca106725 3538 * this domain after reset, you have to enable write access using
Kojto 122:f9eeca106725 3539 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 122:f9eeca106725 3540 * (to be done once after reset).
Kojto 122:f9eeca106725 3541 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto 122:f9eeca106725 3542 * software should wait on LSERDY flag to be set indicating that LSE clock
Kojto 122:f9eeca106725 3543 * is stable and can be used to clock the RTC.
Kojto 122:f9eeca106725 3544 * @param __STATE__: specifies the new state of the LSE.
Kojto 122:f9eeca106725 3545 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3546 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto 122:f9eeca106725 3547 * 6 LSE oscillator clock cycles.
Kojto 122:f9eeca106725 3548 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
Kojto 122:f9eeca106725 3549 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
Kojto 122:f9eeca106725 3550 * @retval None
Kojto 122:f9eeca106725 3551 */
Kojto 122:f9eeca106725 3552 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto 122:f9eeca106725 3553 do { \
Kojto 122:f9eeca106725 3554 if((__STATE__) == RCC_LSE_ON) \
Kojto 122:f9eeca106725 3555 { \
Kojto 122:f9eeca106725 3556 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 122:f9eeca106725 3557 } \
Kojto 122:f9eeca106725 3558 else if((__STATE__) == RCC_LSE_BYPASS) \
Kojto 122:f9eeca106725 3559 { \
Kojto 122:f9eeca106725 3560 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto 122:f9eeca106725 3561 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 122:f9eeca106725 3562 } \
Kojto 122:f9eeca106725 3563 else \
Kojto 122:f9eeca106725 3564 { \
Kojto 122:f9eeca106725 3565 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 122:f9eeca106725 3566 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto 122:f9eeca106725 3567 } \
Kojto 122:f9eeca106725 3568 } while(0)
Kojto 122:f9eeca106725 3569
Kojto 122:f9eeca106725 3570 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 3571
Kojto 122:f9eeca106725 3572 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
Kojto 122:f9eeca106725 3573 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 3574 * @note After enabling the HSI48, the application software should wait on HSI48RDY
Kojto 122:f9eeca106725 3575 * flag to be set indicating that HSI48 clock is stable.
Kojto 122:f9eeca106725 3576 * This parameter can be: ENABLE or DISABLE.
Kojto 122:f9eeca106725 3577 * @retval None
Kojto 122:f9eeca106725 3578 */
Kojto 122:f9eeca106725 3579 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
Kojto 122:f9eeca106725 3580
Kojto 122:f9eeca106725 3581 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
Kojto 122:f9eeca106725 3582
Kojto 122:f9eeca106725 3583 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 3584
Kojto 122:f9eeca106725 3585 /** @brief Macros to configure the RTC clock (RTCCLK).
Kojto 122:f9eeca106725 3586 * @note As the RTC clock configuration bits are in the Backup domain and write
Kojto 122:f9eeca106725 3587 * access is denied to this domain after reset, you have to enable write
Kojto 122:f9eeca106725 3588 * access using the Power Backup Access macro before to configure
Kojto 122:f9eeca106725 3589 * the RTC clock source (to be done once after reset).
Kojto 122:f9eeca106725 3590 * @note Once the RTC clock is configured it cannot be changed unless the
Kojto 122:f9eeca106725 3591 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
Kojto 122:f9eeca106725 3592 * a Power On Reset (POR).
Kojto 122:f9eeca106725 3593 *
Kojto 122:f9eeca106725 3594 * @param __RTC_CLKSOURCE__: specifies the RTC clock source.
Kojto 122:f9eeca106725 3595 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3596 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
Kojto 122:f9eeca106725 3597 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
Kojto 122:f9eeca106725 3598 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
Kojto 122:f9eeca106725 3599 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
Kojto 122:f9eeca106725 3600 *
Kojto 122:f9eeca106725 3601 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto 122:f9eeca106725 3602 * work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto 122:f9eeca106725 3603 * However, when the HSE clock is used as RTC clock source, the RTC
Kojto 122:f9eeca106725 3604 * cannot be used in STOP and STANDBY modes.
Kojto 122:f9eeca106725 3605 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto 122:f9eeca106725 3606 * RTC clock source).
Kojto 122:f9eeca106725 3607 * @retval None
Kojto 122:f9eeca106725 3608 */
Kojto 122:f9eeca106725 3609 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
Kojto 122:f9eeca106725 3610 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Kojto 122:f9eeca106725 3611
Kojto 122:f9eeca106725 3612
Kojto 122:f9eeca106725 3613 /** @brief Macro to get the RTC clock source.
Kojto 122:f9eeca106725 3614 * @retval The returned value can be one of the following:
Kojto 122:f9eeca106725 3615 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
Kojto 122:f9eeca106725 3616 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
Kojto 122:f9eeca106725 3617 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
Kojto 122:f9eeca106725 3618 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
Kojto 122:f9eeca106725 3619 */
Kojto 122:f9eeca106725 3620 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
Kojto 122:f9eeca106725 3621
Kojto 122:f9eeca106725 3622 /** @brief Macros to enable or disable the main PLL.
Kojto 122:f9eeca106725 3623 * @note After enabling the main PLL, the application software should wait on
Kojto 122:f9eeca106725 3624 * PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto 122:f9eeca106725 3625 * be used as system clock source.
Kojto 122:f9eeca106725 3626 * @note The main PLL can not be disabled if it is used as system clock source
Kojto 122:f9eeca106725 3627 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 3628 * @retval None
Kojto 122:f9eeca106725 3629 */
Kojto 122:f9eeca106725 3630 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Kojto 122:f9eeca106725 3631
Kojto 122:f9eeca106725 3632 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
Kojto 122:f9eeca106725 3633
Kojto 122:f9eeca106725 3634 /** @brief Macro to configure the PLL clock source.
Kojto 122:f9eeca106725 3635 * @note This function must be used only when the main PLL is disabled.
Kojto 122:f9eeca106725 3636 * @param __PLLSOURCE__: specifies the PLL entry clock source.
Kojto 122:f9eeca106725 3637 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3638 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
Kojto 122:f9eeca106725 3639 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 3640 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 3641 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 3642 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
Kojto 122:f9eeca106725 3643 * @retval None
Kojto 122:f9eeca106725 3644 *
Kojto 122:f9eeca106725 3645 */
Kojto 122:f9eeca106725 3646 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
Kojto 122:f9eeca106725 3647 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto 122:f9eeca106725 3648
Kojto 122:f9eeca106725 3649 /** @brief Macro to configure the PLL source division factor M.
Kojto 122:f9eeca106725 3650 * @note This function must be used only when the main PLL is disabled.
Kojto 122:f9eeca106725 3651 * @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto 122:f9eeca106725 3652 * This parameter must be a number between Min_Data = 1 and Max_Data = 8.
Kojto 122:f9eeca106725 3653 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 122:f9eeca106725 3654 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
Kojto 122:f9eeca106725 3655 * of 16 MHz to limit PLL jitter.
Kojto 122:f9eeca106725 3656 * @retval None
Kojto 122:f9eeca106725 3657 *
Kojto 122:f9eeca106725 3658 */
Kojto 122:f9eeca106725 3659 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
Kojto 122:f9eeca106725 3660 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
Kojto 122:f9eeca106725 3661
Kojto 122:f9eeca106725 3662 /**
Kojto 122:f9eeca106725 3663 * @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto 122:f9eeca106725 3664 * @note This function must be used only when the main PLL is disabled.
Kojto 122:f9eeca106725 3665 *
Kojto 122:f9eeca106725 3666 * @param __PLLSOURCE__: specifies the PLL entry clock source.
Kojto 122:f9eeca106725 3667 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3668 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
Kojto 122:f9eeca106725 3669 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 3670 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 3671 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 3672 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
Kojto 122:f9eeca106725 3673 *
Kojto 122:f9eeca106725 3674 * @param __PLLM__: specifies the division factor for PLL VCO input clock.
Kojto 122:f9eeca106725 3675 * This parameter must be a number between 1 and 8.
Kojto 122:f9eeca106725 3676 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 122:f9eeca106725 3677 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
Kojto 122:f9eeca106725 3678 * of 16 MHz to limit PLL jitter.
Kojto 122:f9eeca106725 3679 *
Kojto 122:f9eeca106725 3680 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock.
Kojto 122:f9eeca106725 3681 * This parameter must be a number between 8 and 86.
Kojto 122:f9eeca106725 3682 * @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto 122:f9eeca106725 3683 * output frequency is between 64 and 344 MHz.
Kojto 122:f9eeca106725 3684 *
Kojto 122:f9eeca106725 3685 * @param __PLLP__: specifies the division factor for SAI clock.
Kojto 122:f9eeca106725 3686 * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x
Kojto 122:f9eeca106725 3687 * else (2 to 31).
Kojto 122:f9eeca106725 3688 *
Kojto 122:f9eeca106725 3689 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
Kojto 122:f9eeca106725 3690 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 3691 * @note If the USB OTG FS is used in your application, you have to set the
Kojto 122:f9eeca106725 3692 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto 122:f9eeca106725 3693 * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
Kojto 122:f9eeca106725 3694 * correctly.
Kojto 122:f9eeca106725 3695 * @param __PLLR__: specifies the division factor for the main system clock.
Kojto 122:f9eeca106725 3696 * @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
Kojto 122:f9eeca106725 3697 * This parameter must be in the range (2, 4, 6 or 8).
Kojto 122:f9eeca106725 3698 * @retval None
Kojto 122:f9eeca106725 3699 */
Kojto 122:f9eeca106725 3700 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 3701
Kojto 122:f9eeca106725 3702 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
Kojto 122:f9eeca106725 3703 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \
Kojto 122:f9eeca106725 3704 (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \
Kojto 122:f9eeca106725 3705 (uint32_t)((__PLLP__) << 27U))
Kojto 122:f9eeca106725 3706
Kojto 122:f9eeca106725 3707 #else
Kojto 122:f9eeca106725 3708
Kojto 122:f9eeca106725 3709 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
Kojto 122:f9eeca106725 3710 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \
Kojto 122:f9eeca106725 3711 (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U))
Kojto 122:f9eeca106725 3712
Kojto 122:f9eeca106725 3713 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 3714
Kojto 122:f9eeca106725 3715 /** @brief Macro to get the oscillator used as PLL clock source.
Kojto 122:f9eeca106725 3716 * @retval The oscillator used as PLL clock source. The returned value can be one
Kojto 122:f9eeca106725 3717 * of the following:
Kojto 122:f9eeca106725 3718 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
Kojto 122:f9eeca106725 3719 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
Kojto 122:f9eeca106725 3720 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto 122:f9eeca106725 3721 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto 122:f9eeca106725 3722 */
Kojto 122:f9eeca106725 3723 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto 122:f9eeca106725 3724
Kojto 122:f9eeca106725 3725 /**
Kojto 122:f9eeca106725 3726 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
Kojto 122:f9eeca106725 3727 * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
Kojto 122:f9eeca106725 3728 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
Kojto 122:f9eeca106725 3729 * be stopped if used as System Clock.
Kojto 122:f9eeca106725 3730 * @param __PLLCLOCKOUT__: specifies the PLL clock to be output.
Kojto 122:f9eeca106725 3731 * This parameter can be one or a combination of the following values:
Kojto 122:f9eeca106725 3732 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
Kojto 122:f9eeca106725 3733 * high-quality audio performance on SAI interface in case.
Kojto 122:f9eeca106725 3734 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
Kojto 122:f9eeca106725 3735 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
Kojto 122:f9eeca106725 3736 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
Kojto 122:f9eeca106725 3737 * @retval None
Kojto 122:f9eeca106725 3738 */
Kojto 122:f9eeca106725 3739 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Kojto 122:f9eeca106725 3740
Kojto 122:f9eeca106725 3741 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Kojto 122:f9eeca106725 3742
Kojto 122:f9eeca106725 3743 /**
Kojto 122:f9eeca106725 3744 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
Kojto 122:f9eeca106725 3745 * @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked.
Kojto 122:f9eeca106725 3746 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3747 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
Kojto 122:f9eeca106725 3748 * high-quality audio performance on SAI interface in case.
Kojto 122:f9eeca106725 3749 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
Kojto 122:f9eeca106725 3750 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
Kojto 122:f9eeca106725 3751 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
Kojto 122:f9eeca106725 3752 * @retval SET / RESET
Kojto 122:f9eeca106725 3753 */
Kojto 122:f9eeca106725 3754 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Kojto 122:f9eeca106725 3755
Kojto 122:f9eeca106725 3756 /**
Kojto 122:f9eeca106725 3757 * @brief Macro to configure the system clock source.
Kojto 122:f9eeca106725 3758 * @param __SYSCLKSOURCE__: specifies the system clock source.
Kojto 122:f9eeca106725 3759 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3760 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
Kojto 122:f9eeca106725 3761 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto 122:f9eeca106725 3762 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto 122:f9eeca106725 3763 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto 122:f9eeca106725 3764 * @retval None
Kojto 122:f9eeca106725 3765 */
Kojto 122:f9eeca106725 3766 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
Kojto 122:f9eeca106725 3767 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Kojto 122:f9eeca106725 3768
Kojto 122:f9eeca106725 3769 /** @brief Macro to get the clock source used as system clock.
Kojto 122:f9eeca106725 3770 * @retval The clock source used as system clock. The returned value can be one
Kojto 122:f9eeca106725 3771 * of the following:
Kojto 122:f9eeca106725 3772 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
Kojto 122:f9eeca106725 3773 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto 122:f9eeca106725 3774 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto 122:f9eeca106725 3775 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto 122:f9eeca106725 3776 */
Kojto 122:f9eeca106725 3777 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto 122:f9eeca106725 3778
Kojto 122:f9eeca106725 3779 /**
Kojto 122:f9eeca106725 3780 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
Kojto 122:f9eeca106725 3781 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 122:f9eeca106725 3782 * this domain after reset, you have to enable write access using
Kojto 122:f9eeca106725 3783 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 122:f9eeca106725 3784 * (to be done once after reset).
Kojto 122:f9eeca106725 3785 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
Kojto 122:f9eeca106725 3786 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3787 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
Kojto 122:f9eeca106725 3788 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
Kojto 122:f9eeca106725 3789 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
Kojto 122:f9eeca106725 3790 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
Kojto 122:f9eeca106725 3791 * @retval None
Kojto 122:f9eeca106725 3792 */
Kojto 122:f9eeca106725 3793 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
Kojto 122:f9eeca106725 3794 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
Kojto 122:f9eeca106725 3795
Kojto 122:f9eeca106725 3796 /**
Kojto 122:f9eeca106725 3797 * @brief Macro to configure the wake up from stop clock.
Kojto 122:f9eeca106725 3798 * @param __STOPWUCLK__: specifies the clock source used after wake up from stop.
Kojto 122:f9eeca106725 3799 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3800 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
Kojto 122:f9eeca106725 3801 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
Kojto 122:f9eeca106725 3802 * @retval None
Kojto 122:f9eeca106725 3803 */
Kojto 122:f9eeca106725 3804 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
Kojto 122:f9eeca106725 3805 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
Kojto 122:f9eeca106725 3806
Kojto 122:f9eeca106725 3807
Kojto 122:f9eeca106725 3808 /** @brief Macro to configure the MCO clock.
Kojto 122:f9eeca106725 3809 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 122:f9eeca106725 3810 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3811 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
Kojto 122:f9eeca106725 3812 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
Kojto 122:f9eeca106725 3813 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
Kojto 122:f9eeca106725 3814 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
Kojto 122:f9eeca106725 3815 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
Kojto 122:f9eeca106725 3816 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
Kojto 122:f9eeca106725 3817 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
Kojto 122:f9eeca106725 3818 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
Kojto 122:f9eeca106725 3819 @if STM32L443xx
Kojto 122:f9eeca106725 3820 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
Kojto 122:f9eeca106725 3821 @endif
AnnaBridge 145:64910690c574 3822 @if STM32L462xx
AnnaBridge 145:64910690c574 3823 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
AnnaBridge 145:64910690c574 3824 @endif
AnnaBridge 145:64910690c574 3825 @if STM32L4A6xx
AnnaBridge 145:64910690c574 3826 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
AnnaBridge 145:64910690c574 3827 @endif
Kojto 122:f9eeca106725 3828 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 122:f9eeca106725 3829 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3830 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
Kojto 122:f9eeca106725 3831 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
Kojto 122:f9eeca106725 3832 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
Kojto 122:f9eeca106725 3833 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
Kojto 122:f9eeca106725 3834 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
Kojto 122:f9eeca106725 3835 */
Kojto 122:f9eeca106725 3836 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 122:f9eeca106725 3837 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Kojto 122:f9eeca106725 3838
Kojto 122:f9eeca106725 3839 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto 122:f9eeca106725 3840 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 122:f9eeca106725 3841 * @{
Kojto 122:f9eeca106725 3842 */
Kojto 122:f9eeca106725 3843
Kojto 122:f9eeca106725 3844 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto 122:f9eeca106725 3845 * the selected interrupts).
Kojto 122:f9eeca106725 3846 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto 122:f9eeca106725 3847 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 3848 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Kojto 122:f9eeca106725 3849 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
Kojto 122:f9eeca106725 3850 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 3851 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 3852 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
Kojto 122:f9eeca106725 3853 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
Kojto 122:f9eeca106725 3854 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
Kojto 122:f9eeca106725 3855 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
Kojto 122:f9eeca106725 3856 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
Kojto 122:f9eeca106725 3857 @if STM32L443xx
Kojto 122:f9eeca106725 3858 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Kojto 122:f9eeca106725 3859 @endif
AnnaBridge 145:64910690c574 3860 @if STM32L462xx
AnnaBridge 145:64910690c574 3861 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 145:64910690c574 3862 @endif
AnnaBridge 145:64910690c574 3863 @if STM32L4A6xx
AnnaBridge 145:64910690c574 3864 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 145:64910690c574 3865 @endif
Kojto 122:f9eeca106725 3866 * @retval None
Kojto 122:f9eeca106725 3867 */
Kojto 122:f9eeca106725 3868 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Kojto 122:f9eeca106725 3869
Kojto 122:f9eeca106725 3870 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto 122:f9eeca106725 3871 * the selected interrupts).
Kojto 122:f9eeca106725 3872 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto 122:f9eeca106725 3873 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 3874 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Kojto 122:f9eeca106725 3875 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
Kojto 122:f9eeca106725 3876 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 3877 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 3878 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
Kojto 122:f9eeca106725 3879 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
Kojto 122:f9eeca106725 3880 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
Kojto 122:f9eeca106725 3881 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
Kojto 122:f9eeca106725 3882 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
Kojto 122:f9eeca106725 3883 @if STM32L443xx
Kojto 122:f9eeca106725 3884 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Kojto 122:f9eeca106725 3885 @endif
AnnaBridge 145:64910690c574 3886 @if STM32L462xx
AnnaBridge 145:64910690c574 3887 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 145:64910690c574 3888 @endif
AnnaBridge 145:64910690c574 3889 @if STM32L4A6xx
AnnaBridge 145:64910690c574 3890 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 145:64910690c574 3891 @endif
Kojto 122:f9eeca106725 3892 * @retval None
Kojto 122:f9eeca106725 3893 */
Kojto 122:f9eeca106725 3894 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Kojto 122:f9eeca106725 3895
Kojto 122:f9eeca106725 3896 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Kojto 122:f9eeca106725 3897 * bits to clear the selected interrupt pending bits.
Kojto 122:f9eeca106725 3898 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto 122:f9eeca106725 3899 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 3900 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Kojto 122:f9eeca106725 3901 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
Kojto 122:f9eeca106725 3902 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
Kojto 122:f9eeca106725 3903 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 3904 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
Kojto 122:f9eeca106725 3905 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
Kojto 122:f9eeca106725 3906 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
Kojto 122:f9eeca106725 3907 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
Kojto 122:f9eeca106725 3908 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
Kojto 122:f9eeca106725 3909 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
Kojto 122:f9eeca106725 3910 @if STM32L443xx
Kojto 122:f9eeca106725 3911 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Kojto 122:f9eeca106725 3912 @endif
AnnaBridge 145:64910690c574 3913 @if STM32L462xx
AnnaBridge 145:64910690c574 3914 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 145:64910690c574 3915 @endif
AnnaBridge 145:64910690c574 3916 @if STM32L4A6xx
AnnaBridge 145:64910690c574 3917 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 145:64910690c574 3918 @endif
Kojto 122:f9eeca106725 3919 * @retval None
Kojto 122:f9eeca106725 3920 */
Kojto 122:f9eeca106725 3921 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Kojto 122:f9eeca106725 3922
Kojto 122:f9eeca106725 3923 /** @brief Check whether the RCC interrupt has occurred or not.
Kojto 122:f9eeca106725 3924 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto 122:f9eeca106725 3925 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3926 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Kojto 122:f9eeca106725 3927 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
Kojto 122:f9eeca106725 3928 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
Kojto 122:f9eeca106725 3929 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 3930 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
Kojto 122:f9eeca106725 3931 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
Kojto 122:f9eeca106725 3932 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
Kojto 122:f9eeca106725 3933 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
Kojto 122:f9eeca106725 3934 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
Kojto 122:f9eeca106725 3935 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
Kojto 122:f9eeca106725 3936 @if STM32L443xx
Kojto 122:f9eeca106725 3937 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
Kojto 122:f9eeca106725 3938 @endif
AnnaBridge 145:64910690c574 3939 @if STM32L462xx
AnnaBridge 145:64910690c574 3940 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 145:64910690c574 3941 @endif
AnnaBridge 145:64910690c574 3942 @if STM32L4A6xx
AnnaBridge 145:64910690c574 3943 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge 145:64910690c574 3944 @endif
Kojto 122:f9eeca106725 3945 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto 122:f9eeca106725 3946 */
Kojto 122:f9eeca106725 3947 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto 122:f9eeca106725 3948
Kojto 122:f9eeca106725 3949 /** @brief Set RMVF bit to clear the reset flags.
Kojto 122:f9eeca106725 3950 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
Kojto 122:f9eeca106725 3951 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
Kojto 122:f9eeca106725 3952 * @retval None
Kojto 122:f9eeca106725 3953 */
Kojto 122:f9eeca106725 3954 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Kojto 122:f9eeca106725 3955
Kojto 122:f9eeca106725 3956 /** @brief Check whether the selected RCC flag is set or not.
Kojto 122:f9eeca106725 3957 * @param __FLAG__: specifies the flag to check.
Kojto 122:f9eeca106725 3958 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3959 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
Kojto 122:f9eeca106725 3960 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
Kojto 122:f9eeca106725 3961 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
Kojto 122:f9eeca106725 3962 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
Kojto 122:f9eeca106725 3963 * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready
Kojto 122:f9eeca106725 3964 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2
Kojto 122:f9eeca106725 3965 @if STM32L443xx
Kojto 122:f9eeca106725 3966 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
Kojto 122:f9eeca106725 3967 @endif
AnnaBridge 145:64910690c574 3968 @if STM32L462xx
AnnaBridge 145:64910690c574 3969 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
AnnaBridge 145:64910690c574 3970 @endif
AnnaBridge 145:64910690c574 3971 @if STM32L4A6xx
AnnaBridge 145:64910690c574 3972 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
AnnaBridge 145:64910690c574 3973 @endif
Kojto 122:f9eeca106725 3974 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
Kojto 122:f9eeca106725 3975 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
Kojto 122:f9eeca106725 3976 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
Kojto 122:f9eeca106725 3977 * @arg @ref RCC_FLAG_BORRST BOR reset
Kojto 122:f9eeca106725 3978 * @arg @ref RCC_FLAG_OBLRST OBLRST reset
Kojto 122:f9eeca106725 3979 * @arg @ref RCC_FLAG_PINRST Pin reset
Kojto 122:f9eeca106725 3980 * @arg @ref RCC_FLAG_FWRST FIREWALL reset
Kojto 122:f9eeca106725 3981 * @arg @ref RCC_FLAG_RMVF Remove reset Flag
Kojto 122:f9eeca106725 3982 * @arg @ref RCC_FLAG_SFTRST Software reset
Kojto 122:f9eeca106725 3983 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
Kojto 122:f9eeca106725 3984 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
Kojto 122:f9eeca106725 3985 * @arg @ref RCC_FLAG_LPWRRST Low Power reset
Kojto 122:f9eeca106725 3986 * @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto 122:f9eeca106725 3987 */
Kojto 122:f9eeca106725 3988 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 3989 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
Kojto 122:f9eeca106725 3990 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
Kojto 122:f9eeca106725 3991 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
Kojto 122:f9eeca106725 3992 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
Kojto 122:f9eeca106725 3993 ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
Kojto 122:f9eeca106725 3994 ? 1U : 0U)
Kojto 122:f9eeca106725 3995 #else
Kojto 122:f9eeca106725 3996 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
Kojto 122:f9eeca106725 3997 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
Kojto 122:f9eeca106725 3998 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
Kojto 122:f9eeca106725 3999 ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
Kojto 122:f9eeca106725 4000 ? 1U : 0U)
Kojto 122:f9eeca106725 4001 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 4002
Kojto 122:f9eeca106725 4003 /**
Kojto 122:f9eeca106725 4004 * @}
Kojto 122:f9eeca106725 4005 */
Kojto 122:f9eeca106725 4006
Kojto 122:f9eeca106725 4007 /**
Kojto 122:f9eeca106725 4008 * @}
Kojto 122:f9eeca106725 4009 */
Kojto 122:f9eeca106725 4010
Kojto 122:f9eeca106725 4011 /* Private constants ---------------------------------------------------------*/
Kojto 122:f9eeca106725 4012 /** @defgroup RCC_Private_Constants RCC Private Constants
Kojto 122:f9eeca106725 4013 * @{
Kojto 122:f9eeca106725 4014 */
Kojto 122:f9eeca106725 4015 /* Defines used for Flags */
Kojto 122:f9eeca106725 4016 #define CR_REG_INDEX ((uint32_t)1U)
Kojto 122:f9eeca106725 4017 #define BDCR_REG_INDEX ((uint32_t)2U)
Kojto 122:f9eeca106725 4018 #define CSR_REG_INDEX ((uint32_t)3U)
Kojto 122:f9eeca106725 4019 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 4020 #define CRRCR_REG_INDEX ((uint32_t)4U)
Kojto 122:f9eeca106725 4021 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 4022
Kojto 122:f9eeca106725 4023 #define RCC_FLAG_MASK ((uint32_t)0x1FU)
Kojto 122:f9eeca106725 4024 /**
Kojto 122:f9eeca106725 4025 * @}
Kojto 122:f9eeca106725 4026 */
Kojto 122:f9eeca106725 4027
Kojto 122:f9eeca106725 4028 /* Private macros ------------------------------------------------------------*/
Kojto 122:f9eeca106725 4029 /** @addtogroup RCC_Private_Macros
Kojto 122:f9eeca106725 4030 * @{
Kojto 122:f9eeca106725 4031 */
Kojto 122:f9eeca106725 4032
Kojto 122:f9eeca106725 4033 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 4034 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
Kojto 122:f9eeca106725 4035 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
Kojto 122:f9eeca106725 4036 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
Kojto 122:f9eeca106725 4037 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
Kojto 122:f9eeca106725 4038 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
Kojto 122:f9eeca106725 4039 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
Kojto 122:f9eeca106725 4040 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
Kojto 122:f9eeca106725 4041 #else
Kojto 122:f9eeca106725 4042 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
Kojto 122:f9eeca106725 4043 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
Kojto 122:f9eeca106725 4044 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
Kojto 122:f9eeca106725 4045 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
Kojto 122:f9eeca106725 4046 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
Kojto 122:f9eeca106725 4047 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
Kojto 122:f9eeca106725 4048 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 4049
Kojto 122:f9eeca106725 4050 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
Kojto 122:f9eeca106725 4051 ((__HSE__) == RCC_HSE_BYPASS))
Kojto 122:f9eeca106725 4052
Kojto 122:f9eeca106725 4053 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
Kojto 122:f9eeca106725 4054 ((__LSE__) == RCC_LSE_BYPASS))
Kojto 122:f9eeca106725 4055
Kojto 122:f9eeca106725 4056 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
Kojto 122:f9eeca106725 4057
AnnaBridge 145:64910690c574 4058 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM >> POSITION_VAL(RCC_ICSCR_HSITRIM)))
Kojto 122:f9eeca106725 4059
Kojto 122:f9eeca106725 4060 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
Kojto 122:f9eeca106725 4061
Kojto 122:f9eeca106725 4062 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
Kojto 122:f9eeca106725 4063
Kojto 122:f9eeca106725 4064 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
Kojto 122:f9eeca106725 4065
Kojto 122:f9eeca106725 4066 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 4067 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
Kojto 122:f9eeca106725 4068 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 4069
Kojto 122:f9eeca106725 4070 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
Kojto 122:f9eeca106725 4071 ((__PLL__) == RCC_PLL_ON))
Kojto 122:f9eeca106725 4072
Kojto 122:f9eeca106725 4073 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
Kojto 122:f9eeca106725 4074 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \
Kojto 122:f9eeca106725 4075 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
Kojto 122:f9eeca106725 4076 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
Kojto 122:f9eeca106725 4077
Kojto 122:f9eeca106725 4078 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
Kojto 122:f9eeca106725 4079
Kojto 122:f9eeca106725 4080 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
Kojto 122:f9eeca106725 4081
Kojto 122:f9eeca106725 4082 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
Kojto 122:f9eeca106725 4083 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
Kojto 122:f9eeca106725 4084 #else
Kojto 122:f9eeca106725 4085 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
Kojto 122:f9eeca106725 4086 #endif /*RCC_PLLP_DIV_2_31_SUPPORT */
Kojto 122:f9eeca106725 4087
Kojto 122:f9eeca106725 4088 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
Kojto 122:f9eeca106725 4089 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
Kojto 122:f9eeca106725 4090
Kojto 122:f9eeca106725 4091 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
Kojto 122:f9eeca106725 4092 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
Kojto 122:f9eeca106725 4093
Kojto 122:f9eeca106725 4094 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \
Kojto 122:f9eeca106725 4095 (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \
Kojto 122:f9eeca106725 4096 (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
Kojto 122:f9eeca106725 4097 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))
Kojto 122:f9eeca106725 4098
Kojto 122:f9eeca106725 4099 #if defined(RCC_PLLSAI2_SUPPORT)
Kojto 122:f9eeca106725 4100 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \
Kojto 122:f9eeca106725 4101 (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
Kojto 122:f9eeca106725 4102 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))
Kojto 122:f9eeca106725 4103 #endif /* RCC_PLLSAI2_SUPPORT */
Kojto 122:f9eeca106725 4104
Kojto 122:f9eeca106725 4105 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
Kojto 122:f9eeca106725 4106 ((__RANGE__) == RCC_MSIRANGE_1) || \
Kojto 122:f9eeca106725 4107 ((__RANGE__) == RCC_MSIRANGE_2) || \
Kojto 122:f9eeca106725 4108 ((__RANGE__) == RCC_MSIRANGE_3) || \
Kojto 122:f9eeca106725 4109 ((__RANGE__) == RCC_MSIRANGE_4) || \
Kojto 122:f9eeca106725 4110 ((__RANGE__) == RCC_MSIRANGE_5) || \
Kojto 122:f9eeca106725 4111 ((__RANGE__) == RCC_MSIRANGE_6) || \
Kojto 122:f9eeca106725 4112 ((__RANGE__) == RCC_MSIRANGE_7) || \
Kojto 122:f9eeca106725 4113 ((__RANGE__) == RCC_MSIRANGE_8) || \
Kojto 122:f9eeca106725 4114 ((__RANGE__) == RCC_MSIRANGE_9) || \
Kojto 122:f9eeca106725 4115 ((__RANGE__) == RCC_MSIRANGE_10) || \
Kojto 122:f9eeca106725 4116 ((__RANGE__) == RCC_MSIRANGE_11))
Kojto 122:f9eeca106725 4117
Kojto 122:f9eeca106725 4118 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \
Kojto 122:f9eeca106725 4119 ((__RANGE__) == RCC_MSIRANGE_5) || \
Kojto 122:f9eeca106725 4120 ((__RANGE__) == RCC_MSIRANGE_6) || \
Kojto 122:f9eeca106725 4121 ((__RANGE__) == RCC_MSIRANGE_7))
Kojto 122:f9eeca106725 4122
Kojto 122:f9eeca106725 4123 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
Kojto 122:f9eeca106725 4124
Kojto 122:f9eeca106725 4125 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
Kojto 122:f9eeca106725 4126 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 122:f9eeca106725 4127 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 122:f9eeca106725 4128 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto 122:f9eeca106725 4129
Kojto 122:f9eeca106725 4130 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
Kojto 122:f9eeca106725 4131 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
Kojto 122:f9eeca106725 4132 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
Kojto 122:f9eeca106725 4133 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
Kojto 122:f9eeca106725 4134 ((__HCLK__) == RCC_SYSCLK_DIV512))
Kojto 122:f9eeca106725 4135
Kojto 122:f9eeca106725 4136 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
Kojto 122:f9eeca106725 4137 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
Kojto 122:f9eeca106725 4138 ((__PCLK__) == RCC_HCLK_DIV16))
Kojto 122:f9eeca106725 4139
Kojto 122:f9eeca106725 4140 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
Kojto 122:f9eeca106725 4141 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 4142 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
Kojto 122:f9eeca106725 4143 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
Kojto 122:f9eeca106725 4144
Kojto 122:f9eeca106725 4145 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
Kojto 122:f9eeca106725 4146
Kojto 122:f9eeca106725 4147 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 4148 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
Kojto 122:f9eeca106725 4149 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 4150 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
Kojto 122:f9eeca106725 4151 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
Kojto 122:f9eeca106725 4152 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
Kojto 122:f9eeca106725 4153 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
Kojto 122:f9eeca106725 4154 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
Kojto 122:f9eeca106725 4155 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
Kojto 122:f9eeca106725 4156 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
Kojto 122:f9eeca106725 4157 #else
Kojto 122:f9eeca106725 4158 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
Kojto 122:f9eeca106725 4159 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 4160 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
Kojto 122:f9eeca106725 4161 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
Kojto 122:f9eeca106725 4162 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
Kojto 122:f9eeca106725 4163 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
Kojto 122:f9eeca106725 4164 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
Kojto 122:f9eeca106725 4165 ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
Kojto 122:f9eeca106725 4166 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 4167
Kojto 122:f9eeca106725 4168 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
Kojto 122:f9eeca106725 4169 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
Kojto 122:f9eeca106725 4170 ((__DIV__) == RCC_MCODIV_16))
Kojto 122:f9eeca106725 4171
Kojto 122:f9eeca106725 4172 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
Kojto 122:f9eeca106725 4173 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
Kojto 122:f9eeca106725 4174 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
Kojto 122:f9eeca106725 4175 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
Kojto 122:f9eeca106725 4176
Kojto 122:f9eeca106725 4177 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
Kojto 122:f9eeca106725 4178 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
Kojto 122:f9eeca106725 4179 /**
Kojto 122:f9eeca106725 4180 * @}
Kojto 122:f9eeca106725 4181 */
Kojto 122:f9eeca106725 4182
Kojto 122:f9eeca106725 4183 /* Include RCC HAL Extended module */
Kojto 122:f9eeca106725 4184 #include "stm32l4xx_hal_rcc_ex.h"
Kojto 122:f9eeca106725 4185
Kojto 122:f9eeca106725 4186 /* Exported functions --------------------------------------------------------*/
Kojto 122:f9eeca106725 4187 /** @addtogroup RCC_Exported_Functions
Kojto 122:f9eeca106725 4188 * @{
Kojto 122:f9eeca106725 4189 */
Kojto 122:f9eeca106725 4190
Kojto 122:f9eeca106725 4191
Kojto 122:f9eeca106725 4192 /** @addtogroup RCC_Exported_Functions_Group1
Kojto 122:f9eeca106725 4193 * @{
Kojto 122:f9eeca106725 4194 */
Kojto 122:f9eeca106725 4195
Kojto 122:f9eeca106725 4196 /* Initialization and de-initialization functions ******************************/
Kojto 122:f9eeca106725 4197 void HAL_RCC_DeInit(void);
Kojto 122:f9eeca106725 4198 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 122:f9eeca106725 4199 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 122:f9eeca106725 4200
Kojto 122:f9eeca106725 4201 /**
Kojto 122:f9eeca106725 4202 * @}
Kojto 122:f9eeca106725 4203 */
Kojto 122:f9eeca106725 4204
Kojto 122:f9eeca106725 4205 /** @addtogroup RCC_Exported_Functions_Group2
Kojto 122:f9eeca106725 4206 * @{
Kojto 122:f9eeca106725 4207 */
Kojto 122:f9eeca106725 4208
Kojto 122:f9eeca106725 4209 /* Peripheral Control functions ************************************************/
Kojto 122:f9eeca106725 4210 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto 122:f9eeca106725 4211 void HAL_RCC_EnableCSS(void);
Kojto 122:f9eeca106725 4212 uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto 122:f9eeca106725 4213 uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto 122:f9eeca106725 4214 uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto 122:f9eeca106725 4215 uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto 122:f9eeca106725 4216 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 122:f9eeca106725 4217 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
Kojto 122:f9eeca106725 4218 /* CSS NMI IRQ handler */
Kojto 122:f9eeca106725 4219 void HAL_RCC_NMI_IRQHandler(void);
Kojto 122:f9eeca106725 4220 /* User Callbacks in non blocking mode (IT mode) */
Kojto 122:f9eeca106725 4221 void HAL_RCC_CSSCallback(void);
Kojto 122:f9eeca106725 4222
Kojto 122:f9eeca106725 4223 /**
Kojto 122:f9eeca106725 4224 * @}
Kojto 122:f9eeca106725 4225 */
Kojto 122:f9eeca106725 4226
Kojto 122:f9eeca106725 4227 /**
Kojto 122:f9eeca106725 4228 * @}
Kojto 122:f9eeca106725 4229 */
Kojto 122:f9eeca106725 4230
Kojto 122:f9eeca106725 4231 /**
Kojto 122:f9eeca106725 4232 * @}
Kojto 122:f9eeca106725 4233 */
Kojto 122:f9eeca106725 4234
Kojto 122:f9eeca106725 4235 /**
Kojto 122:f9eeca106725 4236 * @}
Kojto 122:f9eeca106725 4237 */
Kojto 122:f9eeca106725 4238
Kojto 122:f9eeca106725 4239 #ifdef __cplusplus
Kojto 122:f9eeca106725 4240 }
Kojto 122:f9eeca106725 4241 #endif
Kojto 122:f9eeca106725 4242
Kojto 122:f9eeca106725 4243 #endif /* __STM32L4xx_HAL_RCC_H */
Kojto 122:f9eeca106725 4244
Kojto 122:f9eeca106725 4245 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/