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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_F303K8/stm32f303x8.h@109:9296ab0bfc11, 2015-10-29 (annotated)

Committer:
Kojto
Date:
Thu Oct 29 08:40:18 2015 +0000
Revision:
109:9296ab0bfc11
Child:
122:f9eeca106725
Release 109  of the mbed library



Changes:

- new platforms - NUCLEO_F042K6, WIZNWIKI_W7500ECO

- MTS targets - bootloaders update to 0.1.1

- STM F7 - RTC enable fixes

- STM F4 - i2c pending stop before start fix

- STM all targets - analogout normalization fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 109:9296ab0bfc11 1 /**
Kojto 109:9296ab0bfc11 2 ******************************************************************************
Kojto 109:9296ab0bfc11 3 * @file stm32f303x8.h
Kojto 109:9296ab0bfc11 4 * @author MCD Application Team
Kojto 109:9296ab0bfc11 5 * @version $VERSION$
Kojto 109:9296ab0bfc11 6 * @date 12-Sept-2014
Kojto 109:9296ab0bfc11 7 * @brief CMSIS STM32F303x6/STM32F303x8 Devices Peripheral Access Layer Header File.
Kojto 109:9296ab0bfc11 8 *
Kojto 109:9296ab0bfc11 9 * This file contains:
Kojto 109:9296ab0bfc11 10 * - Data structures and the address mapping for all peripherals
Kojto 109:9296ab0bfc11 11 * - Peripheral's registers declarations and bits definition
Kojto 109:9296ab0bfc11 12 * - Macros to access peripheral’s registers hardware
Kojto 109:9296ab0bfc11 13 *
Kojto 109:9296ab0bfc11 14 ******************************************************************************
Kojto 109:9296ab0bfc11 15 * @attention
Kojto 109:9296ab0bfc11 16 *
Kojto 109:9296ab0bfc11 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 109:9296ab0bfc11 18 *
Kojto 109:9296ab0bfc11 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 109:9296ab0bfc11 20 * are permitted provided that the following conditions are met:
Kojto 109:9296ab0bfc11 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 109:9296ab0bfc11 22 * this list of conditions and the following disclaimer.
Kojto 109:9296ab0bfc11 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 109:9296ab0bfc11 24 * this list of conditions and the following disclaimer in the documentation
Kojto 109:9296ab0bfc11 25 * and/or other materials provided with the distribution.
Kojto 109:9296ab0bfc11 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 109:9296ab0bfc11 27 * may be used to endorse or promote products derived from this software
Kojto 109:9296ab0bfc11 28 * without specific prior written permission.
Kojto 109:9296ab0bfc11 29 *
Kojto 109:9296ab0bfc11 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 109:9296ab0bfc11 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 109:9296ab0bfc11 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 109:9296ab0bfc11 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 109:9296ab0bfc11 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 109:9296ab0bfc11 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 109:9296ab0bfc11 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 109:9296ab0bfc11 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 109:9296ab0bfc11 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 109:9296ab0bfc11 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 109:9296ab0bfc11 40 *
Kojto 109:9296ab0bfc11 41 ******************************************************************************
Kojto 109:9296ab0bfc11 42 */
Kojto 109:9296ab0bfc11 43
Kojto 109:9296ab0bfc11 44 /** @addtogroup CMSIS_Device
Kojto 109:9296ab0bfc11 45 * @{
Kojto 109:9296ab0bfc11 46 */
Kojto 109:9296ab0bfc11 47
Kojto 109:9296ab0bfc11 48 /** @addtogroup stm32f303x8
Kojto 109:9296ab0bfc11 49 * @{
Kojto 109:9296ab0bfc11 50 */
Kojto 109:9296ab0bfc11 51
Kojto 109:9296ab0bfc11 52 #ifndef __STM32F303x8_H
Kojto 109:9296ab0bfc11 53 #define __STM32F303x8_H
Kojto 109:9296ab0bfc11 54
Kojto 109:9296ab0bfc11 55 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 56 extern "C" {
Kojto 109:9296ab0bfc11 57 #endif /* __cplusplus */
Kojto 109:9296ab0bfc11 58
Kojto 109:9296ab0bfc11 59 /** @addtogroup Configuration_section_for_CMSIS
Kojto 109:9296ab0bfc11 60 * @{
Kojto 109:9296ab0bfc11 61 */
Kojto 109:9296ab0bfc11 62
Kojto 109:9296ab0bfc11 63 /**
Kojto 109:9296ab0bfc11 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
Kojto 109:9296ab0bfc11 65 */
Kojto 109:9296ab0bfc11 66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
Kojto 109:9296ab0bfc11 67 #define __MPU_PRESENT 0 /*!< STM32F303x6/STM32F303x8 devices do not provide an MPU */
Kojto 109:9296ab0bfc11 68 #define __NVIC_PRIO_BITS 4 /*!< STM32F303x6/STM32F303x8 devices use 4 Bits for the Priority Levels */
Kojto 109:9296ab0bfc11 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 109:9296ab0bfc11 70 #define __FPU_PRESENT 1 /*!< STM32F303x6/STM32F303x8 devices provide an FPU */
Kojto 109:9296ab0bfc11 71
Kojto 109:9296ab0bfc11 72 /**
Kojto 109:9296ab0bfc11 73 * @}
Kojto 109:9296ab0bfc11 74 */
Kojto 109:9296ab0bfc11 75
Kojto 109:9296ab0bfc11 76 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 109:9296ab0bfc11 77 * @{
Kojto 109:9296ab0bfc11 78 */
Kojto 109:9296ab0bfc11 79
Kojto 109:9296ab0bfc11 80 /**
Kojto 109:9296ab0bfc11 81 * @brief STM32F303x6/STM32F303x8 device Interrupt Number Definition, according to the selected device
Kojto 109:9296ab0bfc11 82 * in @ref Library_configuration_section
Kojto 109:9296ab0bfc11 83 */
Kojto 109:9296ab0bfc11 84 typedef enum
Kojto 109:9296ab0bfc11 85 {
Kojto 109:9296ab0bfc11 86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
Kojto 109:9296ab0bfc11 87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 109:9296ab0bfc11 88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
Kojto 109:9296ab0bfc11 89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
Kojto 109:9296ab0bfc11 90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
Kojto 109:9296ab0bfc11 91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
Kojto 109:9296ab0bfc11 92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
Kojto 109:9296ab0bfc11 93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
Kojto 109:9296ab0bfc11 94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
Kojto 109:9296ab0bfc11 95 /****** STM32 specific Interrupt Numbers **********************************************************************/
Kojto 109:9296ab0bfc11 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 109:9296ab0bfc11 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
Kojto 109:9296ab0bfc11 98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
Kojto 109:9296ab0bfc11 99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
Kojto 109:9296ab0bfc11 100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
Kojto 109:9296ab0bfc11 101 RCC_IRQn = 5, /*!< RCC global Interrupt */
Kojto 109:9296ab0bfc11 102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
Kojto 109:9296ab0bfc11 103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
Kojto 109:9296ab0bfc11 104 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
Kojto 109:9296ab0bfc11 105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
Kojto 109:9296ab0bfc11 106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
Kojto 109:9296ab0bfc11 107 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
Kojto 109:9296ab0bfc11 108 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
Kojto 109:9296ab0bfc11 109 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
Kojto 109:9296ab0bfc11 110 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
Kojto 109:9296ab0bfc11 111 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
Kojto 109:9296ab0bfc11 112 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
Kojto 109:9296ab0bfc11 113 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
Kojto 109:9296ab0bfc11 114 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
Kojto 109:9296ab0bfc11 115 CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */
Kojto 109:9296ab0bfc11 116 CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */
Kojto 109:9296ab0bfc11 117 CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
Kojto 109:9296ab0bfc11 118 CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
Kojto 109:9296ab0bfc11 119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
Kojto 109:9296ab0bfc11 120 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
Kojto 109:9296ab0bfc11 121 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
Kojto 109:9296ab0bfc11 122 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
Kojto 109:9296ab0bfc11 123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
Kojto 109:9296ab0bfc11 124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
Kojto 109:9296ab0bfc11 125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
Kojto 109:9296ab0bfc11 126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
Kojto 109:9296ab0bfc11 127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
Kojto 109:9296ab0bfc11 128 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
Kojto 109:9296ab0bfc11 129 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
Kojto 109:9296ab0bfc11 130 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
Kojto 109:9296ab0bfc11 131 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
Kojto 109:9296ab0bfc11 132 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
Kojto 109:9296ab0bfc11 133 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
Kojto 109:9296ab0bfc11 134 TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */
Kojto 109:9296ab0bfc11 135 TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
Kojto 109:9296ab0bfc11 136 COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */
Kojto 109:9296ab0bfc11 137 COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */
Kojto 109:9296ab0bfc11 138 FPU_IRQn = 81 /*!< Floating point Interrupt */
Kojto 109:9296ab0bfc11 139 } IRQn_Type;
Kojto 109:9296ab0bfc11 140
Kojto 109:9296ab0bfc11 141 /**
Kojto 109:9296ab0bfc11 142 * @}
Kojto 109:9296ab0bfc11 143 */
Kojto 109:9296ab0bfc11 144
Kojto 109:9296ab0bfc11 145 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
Kojto 109:9296ab0bfc11 146 #include "system_stm32f3xx.h" /* STM32F3xx System Header */
Kojto 109:9296ab0bfc11 147 #include <stdint.h>
Kojto 109:9296ab0bfc11 148
Kojto 109:9296ab0bfc11 149 /** @addtogroup Peripheral_registers_structures
Kojto 109:9296ab0bfc11 150 * @{
Kojto 109:9296ab0bfc11 151 */
Kojto 109:9296ab0bfc11 152
Kojto 109:9296ab0bfc11 153 /**
Kojto 109:9296ab0bfc11 154 * @brief Analog to Digital Converter
Kojto 109:9296ab0bfc11 155 */
Kojto 109:9296ab0bfc11 156
Kojto 109:9296ab0bfc11 157 typedef struct
Kojto 109:9296ab0bfc11 158 {
Kojto 109:9296ab0bfc11 159 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 160 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 161 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 162 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 163 uint32_t RESERVED0; /*!< Reserved, 0x010 */
Kojto 109:9296ab0bfc11 164 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 165 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 166 uint32_t RESERVED1; /*!< Reserved, 0x01C */
Kojto 109:9296ab0bfc11 167 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 168 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 169 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 170 uint32_t RESERVED2; /*!< Reserved, 0x02C */
Kojto 109:9296ab0bfc11 171 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 172 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
Kojto 109:9296ab0bfc11 173 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
Kojto 109:9296ab0bfc11 174 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
Kojto 109:9296ab0bfc11 175 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
Kojto 109:9296ab0bfc11 176 uint32_t RESERVED3; /*!< Reserved, 0x044 */
Kojto 109:9296ab0bfc11 177 uint32_t RESERVED4; /*!< Reserved, 0x048 */
Kojto 109:9296ab0bfc11 178 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
Kojto 109:9296ab0bfc11 179 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
Kojto 109:9296ab0bfc11 180 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
Kojto 109:9296ab0bfc11 181 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
Kojto 109:9296ab0bfc11 182 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
Kojto 109:9296ab0bfc11 183 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
Kojto 109:9296ab0bfc11 184 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
Kojto 109:9296ab0bfc11 185 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
Kojto 109:9296ab0bfc11 186 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
Kojto 109:9296ab0bfc11 187 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
Kojto 109:9296ab0bfc11 188 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
Kojto 109:9296ab0bfc11 189 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
Kojto 109:9296ab0bfc11 190 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
Kojto 109:9296ab0bfc11 191 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
Kojto 109:9296ab0bfc11 192 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
Kojto 109:9296ab0bfc11 193 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
Kojto 109:9296ab0bfc11 194 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
Kojto 109:9296ab0bfc11 195 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
Kojto 109:9296ab0bfc11 196
Kojto 109:9296ab0bfc11 197 } ADC_TypeDef;
Kojto 109:9296ab0bfc11 198
Kojto 109:9296ab0bfc11 199 typedef struct
Kojto 109:9296ab0bfc11 200 {
Kojto 109:9296ab0bfc11 201 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
Kojto 109:9296ab0bfc11 202 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
Kojto 109:9296ab0bfc11 203 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
Kojto 109:9296ab0bfc11 204 __IO uint32_t CDR; /*!< ADC common regular data register for dual
Kojto 109:9296ab0bfc11 205 AND triple modes, Address offset: ADC1/3 base address + 0x30C */
Kojto 109:9296ab0bfc11 206 } ADC_Common_TypeDef;
Kojto 109:9296ab0bfc11 207
Kojto 109:9296ab0bfc11 208 /**
Kojto 109:9296ab0bfc11 209 * @brief Controller Area Network TxMailBox
Kojto 109:9296ab0bfc11 210 */
Kojto 109:9296ab0bfc11 211 typedef struct
Kojto 109:9296ab0bfc11 212 {
Kojto 109:9296ab0bfc11 213 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
Kojto 109:9296ab0bfc11 214 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
Kojto 109:9296ab0bfc11 215 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
Kojto 109:9296ab0bfc11 216 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
Kojto 109:9296ab0bfc11 217 } CAN_TxMailBox_TypeDef;
Kojto 109:9296ab0bfc11 218
Kojto 109:9296ab0bfc11 219 /**
Kojto 109:9296ab0bfc11 220 * @brief Controller Area Network FIFOMailBox
Kojto 109:9296ab0bfc11 221 */
Kojto 109:9296ab0bfc11 222 typedef struct
Kojto 109:9296ab0bfc11 223 {
Kojto 109:9296ab0bfc11 224 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
Kojto 109:9296ab0bfc11 225 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
Kojto 109:9296ab0bfc11 226 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
Kojto 109:9296ab0bfc11 227 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
Kojto 109:9296ab0bfc11 228 } CAN_FIFOMailBox_TypeDef;
Kojto 109:9296ab0bfc11 229
Kojto 109:9296ab0bfc11 230 /**
Kojto 109:9296ab0bfc11 231 * @brief Controller Area Network FilterRegister
Kojto 109:9296ab0bfc11 232 */
Kojto 109:9296ab0bfc11 233 typedef struct
Kojto 109:9296ab0bfc11 234 {
Kojto 109:9296ab0bfc11 235 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
Kojto 109:9296ab0bfc11 236 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
Kojto 109:9296ab0bfc11 237 } CAN_FilterRegister_TypeDef;
Kojto 109:9296ab0bfc11 238
Kojto 109:9296ab0bfc11 239 /**
Kojto 109:9296ab0bfc11 240 * @brief Controller Area Network
Kojto 109:9296ab0bfc11 241 */
Kojto 109:9296ab0bfc11 242 typedef struct
Kojto 109:9296ab0bfc11 243 {
Kojto 109:9296ab0bfc11 244 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 245 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 246 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 247 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 248 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 249 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 250 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 251 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 252 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
Kojto 109:9296ab0bfc11 253 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
Kojto 109:9296ab0bfc11 254 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
Kojto 109:9296ab0bfc11 255 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
Kojto 109:9296ab0bfc11 256 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
Kojto 109:9296ab0bfc11 257 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
Kojto 109:9296ab0bfc11 258 uint32_t RESERVED2; /*!< Reserved, 0x208 */
Kojto 109:9296ab0bfc11 259 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
Kojto 109:9296ab0bfc11 260 uint32_t RESERVED3; /*!< Reserved, 0x210 */
Kojto 109:9296ab0bfc11 261 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
Kojto 109:9296ab0bfc11 262 uint32_t RESERVED4; /*!< Reserved, 0x218 */
Kojto 109:9296ab0bfc11 263 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
Kojto 109:9296ab0bfc11 264 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
Kojto 109:9296ab0bfc11 265 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
Kojto 109:9296ab0bfc11 266 } CAN_TypeDef;
Kojto 109:9296ab0bfc11 267
Kojto 109:9296ab0bfc11 268 /**
Kojto 109:9296ab0bfc11 269 * @brief Analog Comparators
Kojto 109:9296ab0bfc11 270 */
Kojto 109:9296ab0bfc11 271
Kojto 109:9296ab0bfc11 272 typedef struct
Kojto 109:9296ab0bfc11 273 {
Kojto 109:9296ab0bfc11 274 __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 275 } COMP_TypeDef;
Kojto 109:9296ab0bfc11 276
Kojto 109:9296ab0bfc11 277 /**
Kojto 109:9296ab0bfc11 278 * @brief CRC calculation unit
Kojto 109:9296ab0bfc11 279 */
Kojto 109:9296ab0bfc11 280
Kojto 109:9296ab0bfc11 281 typedef struct
Kojto 109:9296ab0bfc11 282 {
Kojto 109:9296ab0bfc11 283 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 284 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 285 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 109:9296ab0bfc11 286 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 109:9296ab0bfc11 287 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 288 uint32_t RESERVED2; /*!< Reserved, 0x0C */
Kojto 109:9296ab0bfc11 289 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 290 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 291 } CRC_TypeDef;
Kojto 109:9296ab0bfc11 292
Kojto 109:9296ab0bfc11 293 /**
Kojto 109:9296ab0bfc11 294 * @brief Digital to Analog Converter
Kojto 109:9296ab0bfc11 295 */
Kojto 109:9296ab0bfc11 296
Kojto 109:9296ab0bfc11 297 typedef struct
Kojto 109:9296ab0bfc11 298 {
Kojto 109:9296ab0bfc11 299 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 300 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 301 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 302 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 303 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 304 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 305 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 306 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 307 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 308 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 309 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 310 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
Kojto 109:9296ab0bfc11 311 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 312 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
Kojto 109:9296ab0bfc11 313 } DAC_TypeDef;
Kojto 109:9296ab0bfc11 314
Kojto 109:9296ab0bfc11 315 /**
Kojto 109:9296ab0bfc11 316 * @brief Debug MCU
Kojto 109:9296ab0bfc11 317 */
Kojto 109:9296ab0bfc11 318
Kojto 109:9296ab0bfc11 319 typedef struct
Kojto 109:9296ab0bfc11 320 {
Kojto 109:9296ab0bfc11 321 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 322 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 323 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 324 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 325 }DBGMCU_TypeDef;
Kojto 109:9296ab0bfc11 326
Kojto 109:9296ab0bfc11 327 /**
Kojto 109:9296ab0bfc11 328 * @brief DMA Controller
Kojto 109:9296ab0bfc11 329 */
Kojto 109:9296ab0bfc11 330
Kojto 109:9296ab0bfc11 331 typedef struct
Kojto 109:9296ab0bfc11 332 {
Kojto 109:9296ab0bfc11 333 __IO uint32_t CCR; /*!< DMA channel x configuration register */
Kojto 109:9296ab0bfc11 334 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
Kojto 109:9296ab0bfc11 335 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
Kojto 109:9296ab0bfc11 336 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
Kojto 109:9296ab0bfc11 337 } DMA_Channel_TypeDef;
Kojto 109:9296ab0bfc11 338
Kojto 109:9296ab0bfc11 339 typedef struct
Kojto 109:9296ab0bfc11 340 {
Kojto 109:9296ab0bfc11 341 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 342 __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 343 } DMA_TypeDef;
Kojto 109:9296ab0bfc11 344
Kojto 109:9296ab0bfc11 345 /**
Kojto 109:9296ab0bfc11 346 * @brief External Interrupt/Event Controller
Kojto 109:9296ab0bfc11 347 */
Kojto 109:9296ab0bfc11 348
Kojto 109:9296ab0bfc11 349 typedef struct
Kojto 109:9296ab0bfc11 350 {
Kojto 109:9296ab0bfc11 351 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 352 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 353 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 354 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 355 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 356 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 357 uint32_t RESERVED1; /*!< Reserved, 0x18 */
Kojto 109:9296ab0bfc11 358 uint32_t RESERVED2; /*!< Reserved, 0x1C */
Kojto 109:9296ab0bfc11 359 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 360 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 361 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 362 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
Kojto 109:9296ab0bfc11 363 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 364 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
Kojto 109:9296ab0bfc11 365 }EXTI_TypeDef;
Kojto 109:9296ab0bfc11 366
Kojto 109:9296ab0bfc11 367 /**
Kojto 109:9296ab0bfc11 368 * @brief FLASH Registers
Kojto 109:9296ab0bfc11 369 */
Kojto 109:9296ab0bfc11 370
Kojto 109:9296ab0bfc11 371 typedef struct
Kojto 109:9296ab0bfc11 372 {
Kojto 109:9296ab0bfc11 373 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 374 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 375 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 376 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 377 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 378 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 379 uint32_t RESERVED; /*!< Reserved, 0x18 */
Kojto 109:9296ab0bfc11 380 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 381 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 382
Kojto 109:9296ab0bfc11 383 } FLASH_TypeDef;
Kojto 109:9296ab0bfc11 384
Kojto 109:9296ab0bfc11 385 /**
Kojto 109:9296ab0bfc11 386 * @brief Option Bytes Registers
Kojto 109:9296ab0bfc11 387 */
Kojto 109:9296ab0bfc11 388 typedef struct
Kojto 109:9296ab0bfc11 389 {
Kojto 109:9296ab0bfc11 390 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 391 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
Kojto 109:9296ab0bfc11 392 uint16_t RESERVED0; /*!< Reserved, 0x04 */
Kojto 109:9296ab0bfc11 393 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 109:9296ab0bfc11 394 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 395 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 396 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 397 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
Kojto 109:9296ab0bfc11 398 } OB_TypeDef;
Kojto 109:9296ab0bfc11 399
Kojto 109:9296ab0bfc11 400 /**
Kojto 109:9296ab0bfc11 401 * @brief General Purpose I/O
Kojto 109:9296ab0bfc11 402 */
Kojto 109:9296ab0bfc11 403
Kojto 109:9296ab0bfc11 404 typedef struct
Kojto 109:9296ab0bfc11 405 {
Kojto 109:9296ab0bfc11 406 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 407 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 408 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 409 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 410 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 411 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 412 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 413 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
Kojto 109:9296ab0bfc11 414 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 415 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
Kojto 109:9296ab0bfc11 416 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 417 }GPIO_TypeDef;
Kojto 109:9296ab0bfc11 418
Kojto 109:9296ab0bfc11 419 /**
Kojto 109:9296ab0bfc11 420 * @brief Operational Amplifier (OPAMP)
Kojto 109:9296ab0bfc11 421 */
Kojto 109:9296ab0bfc11 422
Kojto 109:9296ab0bfc11 423 typedef struct
Kojto 109:9296ab0bfc11 424 {
Kojto 109:9296ab0bfc11 425 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 426 } OPAMP_TypeDef;
Kojto 109:9296ab0bfc11 427
Kojto 109:9296ab0bfc11 428 /**
Kojto 109:9296ab0bfc11 429 * @brief System configuration controller
Kojto 109:9296ab0bfc11 430 */
Kojto 109:9296ab0bfc11 431
Kojto 109:9296ab0bfc11 432 typedef struct
Kojto 109:9296ab0bfc11 433 {
Kojto 109:9296ab0bfc11 434 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 435 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 436 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
Kojto 109:9296ab0bfc11 437 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 438 __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
Kojto 109:9296ab0bfc11 439 __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
Kojto 109:9296ab0bfc11 440 __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
Kojto 109:9296ab0bfc11 441 __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
Kojto 109:9296ab0bfc11 442 __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
Kojto 109:9296ab0bfc11 443 __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
Kojto 109:9296ab0bfc11 444 __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
Kojto 109:9296ab0bfc11 445 __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
Kojto 109:9296ab0bfc11 446 __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
Kojto 109:9296ab0bfc11 447 __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
Kojto 109:9296ab0bfc11 448 __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
Kojto 109:9296ab0bfc11 449 __IO uint32_t RESERVED12; /*!< Reserved, 0x48 */
Kojto 109:9296ab0bfc11 450 __IO uint32_t RESERVED13; /*!< Reserved, 0x4C */
Kojto 109:9296ab0bfc11 451 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x50 */
Kojto 109:9296ab0bfc11 452 } SYSCFG_TypeDef;
Kojto 109:9296ab0bfc11 453
Kojto 109:9296ab0bfc11 454 /**
Kojto 109:9296ab0bfc11 455 * @brief Inter-integrated Circuit Interface
Kojto 109:9296ab0bfc11 456 */
Kojto 109:9296ab0bfc11 457
Kojto 109:9296ab0bfc11 458 typedef struct
Kojto 109:9296ab0bfc11 459 {
Kojto 109:9296ab0bfc11 460 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 461 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 462 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 463 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 464 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 465 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 466 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 467 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 468 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 469 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 470 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 471 }I2C_TypeDef;
Kojto 109:9296ab0bfc11 472
Kojto 109:9296ab0bfc11 473 /**
Kojto 109:9296ab0bfc11 474 * @brief Independent WATCHDOG
Kojto 109:9296ab0bfc11 475 */
Kojto 109:9296ab0bfc11 476
Kojto 109:9296ab0bfc11 477 typedef struct
Kojto 109:9296ab0bfc11 478 {
Kojto 109:9296ab0bfc11 479 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 480 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 481 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 482 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 483 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 484 } IWDG_TypeDef;
Kojto 109:9296ab0bfc11 485
Kojto 109:9296ab0bfc11 486 /**
Kojto 109:9296ab0bfc11 487 * @brief Power Control
Kojto 109:9296ab0bfc11 488 */
Kojto 109:9296ab0bfc11 489
Kojto 109:9296ab0bfc11 490 typedef struct
Kojto 109:9296ab0bfc11 491 {
Kojto 109:9296ab0bfc11 492 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 493 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 494 } PWR_TypeDef;
Kojto 109:9296ab0bfc11 495
Kojto 109:9296ab0bfc11 496 /**
Kojto 109:9296ab0bfc11 497 * @brief Reset and Clock Control
Kojto 109:9296ab0bfc11 498 */
Kojto 109:9296ab0bfc11 499 typedef struct
Kojto 109:9296ab0bfc11 500 {
Kojto 109:9296ab0bfc11 501 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 502 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 503 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 504 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 505 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 506 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 507 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 508 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 509 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 510 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 511 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 512 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
Kojto 109:9296ab0bfc11 513 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 514 } RCC_TypeDef;
Kojto 109:9296ab0bfc11 515
Kojto 109:9296ab0bfc11 516 /**
Kojto 109:9296ab0bfc11 517 * @brief Real-Time Clock
Kojto 109:9296ab0bfc11 518 */
Kojto 109:9296ab0bfc11 519
Kojto 109:9296ab0bfc11 520 typedef struct
Kojto 109:9296ab0bfc11 521 {
Kojto 109:9296ab0bfc11 522 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 523 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 524 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 525 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 526 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 527 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 528 uint32_t RESERVED0; /*!< Reserved, 0x18 */
Kojto 109:9296ab0bfc11 529 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 530 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 531 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 532 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 533 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 109:9296ab0bfc11 534 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 535 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 109:9296ab0bfc11 536 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 109:9296ab0bfc11 537 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 109:9296ab0bfc11 538 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 109:9296ab0bfc11 539 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 109:9296ab0bfc11 540 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
Kojto 109:9296ab0bfc11 541 uint32_t RESERVED7; /*!< Reserved, 0x4C */
Kojto 109:9296ab0bfc11 542 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
Kojto 109:9296ab0bfc11 543 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 109:9296ab0bfc11 544 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 109:9296ab0bfc11 545 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 109:9296ab0bfc11 546 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 109:9296ab0bfc11 547 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
Kojto 109:9296ab0bfc11 548 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
Kojto 109:9296ab0bfc11 549 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
Kojto 109:9296ab0bfc11 550 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
Kojto 109:9296ab0bfc11 551 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
Kojto 109:9296ab0bfc11 552 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
Kojto 109:9296ab0bfc11 553 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
Kojto 109:9296ab0bfc11 554 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
Kojto 109:9296ab0bfc11 555 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
Kojto 109:9296ab0bfc11 556 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
Kojto 109:9296ab0bfc11 557 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
Kojto 109:9296ab0bfc11 558 } RTC_TypeDef;
Kojto 109:9296ab0bfc11 559
Kojto 109:9296ab0bfc11 560
Kojto 109:9296ab0bfc11 561 /**
Kojto 109:9296ab0bfc11 562 * @brief Serial Peripheral Interface
Kojto 109:9296ab0bfc11 563 */
Kojto 109:9296ab0bfc11 564
Kojto 109:9296ab0bfc11 565 typedef struct
Kojto 109:9296ab0bfc11 566 {
Kojto 109:9296ab0bfc11 567 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 568 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 569 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 570 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 571 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 572 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 573 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 574 } SPI_TypeDef;
Kojto 109:9296ab0bfc11 575
Kojto 109:9296ab0bfc11 576 /**
Kojto 109:9296ab0bfc11 577 * @brief TIM
Kojto 109:9296ab0bfc11 578 */
Kojto 109:9296ab0bfc11 579 typedef struct
Kojto 109:9296ab0bfc11 580 {
Kojto 109:9296ab0bfc11 581 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 582 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 583 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 584 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 585 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 586 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 587 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 588 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 589 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 590 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 591 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 592 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 109:9296ab0bfc11 593 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 594 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 109:9296ab0bfc11 595 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 109:9296ab0bfc11 596 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 109:9296ab0bfc11 597 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 109:9296ab0bfc11 598 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 109:9296ab0bfc11 599 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 109:9296ab0bfc11 600 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
Kojto 109:9296ab0bfc11 601 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 109:9296ab0bfc11 602 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
Kojto 109:9296ab0bfc11 603 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
Kojto 109:9296ab0bfc11 604 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
Kojto 109:9296ab0bfc11 605 } TIM_TypeDef;
Kojto 109:9296ab0bfc11 606
Kojto 109:9296ab0bfc11 607 /**
Kojto 109:9296ab0bfc11 608 * @brief Touch Sensing Controller (TSC)
Kojto 109:9296ab0bfc11 609 */
Kojto 109:9296ab0bfc11 610 typedef struct
Kojto 109:9296ab0bfc11 611 {
Kojto 109:9296ab0bfc11 612 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 613 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 614 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 615 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 616 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 617 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 618 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 619 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 620 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 621 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 622 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 623 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
Kojto 109:9296ab0bfc11 624 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 625 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
Kojto 109:9296ab0bfc11 626 } TSC_TypeDef;
Kojto 109:9296ab0bfc11 627
Kojto 109:9296ab0bfc11 628 /**
Kojto 109:9296ab0bfc11 629 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 109:9296ab0bfc11 630 */
Kojto 109:9296ab0bfc11 631
Kojto 109:9296ab0bfc11 632 typedef struct
Kojto 109:9296ab0bfc11 633 {
Kojto 109:9296ab0bfc11 634 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 635 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 636 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 637 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 638 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 639 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 640 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 641 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 642 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 643 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 644 uint16_t RESERVED1; /*!< Reserved, 0x26 */
Kojto 109:9296ab0bfc11 645 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 646 uint16_t RESERVED2; /*!< Reserved, 0x2A */
Kojto 109:9296ab0bfc11 647 } USART_TypeDef;
Kojto 109:9296ab0bfc11 648
Kojto 109:9296ab0bfc11 649 /**
Kojto 109:9296ab0bfc11 650 * @brief Window WATCHDOG
Kojto 109:9296ab0bfc11 651 */
Kojto 109:9296ab0bfc11 652 typedef struct
Kojto 109:9296ab0bfc11 653 {
Kojto 109:9296ab0bfc11 654 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 655 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 656 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 657 } WWDG_TypeDef;
Kojto 109:9296ab0bfc11 658
Kojto 109:9296ab0bfc11 659 /** @addtogroup Peripheral_memory_map
Kojto 109:9296ab0bfc11 660 * @{
Kojto 109:9296ab0bfc11 661 */
Kojto 109:9296ab0bfc11 662
Kojto 109:9296ab0bfc11 663 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 64KB) base address in the alias region */
Kojto 109:9296ab0bfc11 664 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the alias region */
Kojto 109:9296ab0bfc11 665 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 12KB) base address in the alias region */
Kojto 109:9296ab0bfc11 666 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
Kojto 109:9296ab0bfc11 667
Kojto 109:9296ab0bfc11 668 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the bit-band region */
Kojto 109:9296ab0bfc11 669 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 12KB) base address in the bit-band region */
Kojto 109:9296ab0bfc11 670 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
Kojto 109:9296ab0bfc11 671
Kojto 109:9296ab0bfc11 672
Kojto 109:9296ab0bfc11 673 /*!< Peripheral memory map */
Kojto 109:9296ab0bfc11 674 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 109:9296ab0bfc11 675 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
Kojto 109:9296ab0bfc11 676 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto 109:9296ab0bfc11 677 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
Kojto 109:9296ab0bfc11 678 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
Kojto 109:9296ab0bfc11 679
Kojto 109:9296ab0bfc11 680 /*!< APB1 peripherals */
Kojto 109:9296ab0bfc11 681 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
Kojto 109:9296ab0bfc11 682 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
Kojto 109:9296ab0bfc11 683 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
Kojto 109:9296ab0bfc11 684 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
Kojto 109:9296ab0bfc11 685 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
Kojto 109:9296ab0bfc11 686 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
Kojto 109:9296ab0bfc11 687 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
Kojto 109:9296ab0bfc11 688 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
Kojto 109:9296ab0bfc11 689 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
Kojto 109:9296ab0bfc11 690 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
Kojto 109:9296ab0bfc11 691 #define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
Kojto 109:9296ab0bfc11 692 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
Kojto 109:9296ab0bfc11 693 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
Kojto 109:9296ab0bfc11 694 #define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
Kojto 109:9296ab0bfc11 695 #define DAC_BASE DAC1_BASE
Kojto 109:9296ab0bfc11 696
Kojto 109:9296ab0bfc11 697 /*!< APB2 peripherals */
Kojto 109:9296ab0bfc11 698 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
Kojto 109:9296ab0bfc11 699 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
Kojto 109:9296ab0bfc11 700 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
Kojto 109:9296ab0bfc11 701 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
Kojto 109:9296ab0bfc11 702 #define COMP_BASE COMP2_BASE
Kojto 109:9296ab0bfc11 703 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
Kojto 109:9296ab0bfc11 704 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
Kojto 109:9296ab0bfc11 705 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
Kojto 109:9296ab0bfc11 706 #define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
Kojto 109:9296ab0bfc11 707 #define OPAMP_BASE OPAMP1_BASE
Kojto 109:9296ab0bfc11 708 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
Kojto 109:9296ab0bfc11 709 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
Kojto 109:9296ab0bfc11 710 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
Kojto 109:9296ab0bfc11 711 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
Kojto 109:9296ab0bfc11 712 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
Kojto 109:9296ab0bfc11 713 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
Kojto 109:9296ab0bfc11 714 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
Kojto 109:9296ab0bfc11 715
Kojto 109:9296ab0bfc11 716 /*!< AHB1 peripherals */
Kojto 109:9296ab0bfc11 717 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
Kojto 109:9296ab0bfc11 718 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
Kojto 109:9296ab0bfc11 719 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
Kojto 109:9296ab0bfc11 720 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
Kojto 109:9296ab0bfc11 721 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
Kojto 109:9296ab0bfc11 722 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
Kojto 109:9296ab0bfc11 723 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
Kojto 109:9296ab0bfc11 724 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
Kojto 109:9296ab0bfc11 725 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
Kojto 109:9296ab0bfc11 726 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
Kojto 109:9296ab0bfc11 727 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
Kojto 109:9296ab0bfc11 728 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
Kojto 109:9296ab0bfc11 729 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
Kojto 109:9296ab0bfc11 730
Kojto 109:9296ab0bfc11 731 /*!< AHB2 peripherals */
Kojto 109:9296ab0bfc11 732 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
Kojto 109:9296ab0bfc11 733 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
Kojto 109:9296ab0bfc11 734 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
Kojto 109:9296ab0bfc11 735 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
Kojto 109:9296ab0bfc11 736 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
Kojto 109:9296ab0bfc11 737
Kojto 109:9296ab0bfc11 738 /*!< AHB3 peripherals */
Kojto 109:9296ab0bfc11 739 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
Kojto 109:9296ab0bfc11 740 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
Kojto 109:9296ab0bfc11 741 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
Kojto 109:9296ab0bfc11 742
Kojto 109:9296ab0bfc11 743 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
Kojto 109:9296ab0bfc11 744 /**
Kojto 109:9296ab0bfc11 745 * @}
Kojto 109:9296ab0bfc11 746 */
Kojto 109:9296ab0bfc11 747
Kojto 109:9296ab0bfc11 748 /** @addtogroup Peripheral_declaration
Kojto 109:9296ab0bfc11 749 * @{
Kojto 109:9296ab0bfc11 750 */
Kojto 109:9296ab0bfc11 751 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 109:9296ab0bfc11 752 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 109:9296ab0bfc11 753 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto 109:9296ab0bfc11 754 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto 109:9296ab0bfc11 755 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 109:9296ab0bfc11 756 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 109:9296ab0bfc11 757 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 109:9296ab0bfc11 758 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 109:9296ab0bfc11 759 #define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto 109:9296ab0bfc11 760 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 109:9296ab0bfc11 761 #define CAN ((CAN_TypeDef *) CAN_BASE)
Kojto 109:9296ab0bfc11 762 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 109:9296ab0bfc11 763 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
Kojto 109:9296ab0bfc11 764 #define DAC2 ((DAC_TypeDef *) DAC2_BASE)
Kojto 109:9296ab0bfc11 765 #define DAC ((DAC_TypeDef *) DAC_BASE)
Kojto 109:9296ab0bfc11 766 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 109:9296ab0bfc11 767 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
Kojto 109:9296ab0bfc11 768 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
Kojto 109:9296ab0bfc11 769 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
Kojto 109:9296ab0bfc11 770 #define COMP ((COMP_TypeDef *) COMP_BASE)
Kojto 109:9296ab0bfc11 771 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
Kojto 109:9296ab0bfc11 772 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
Kojto 109:9296ab0bfc11 773 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 109:9296ab0bfc11 774 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 109:9296ab0bfc11 775 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 109:9296ab0bfc11 776 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 109:9296ab0bfc11 777 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
Kojto 109:9296ab0bfc11 778 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
Kojto 109:9296ab0bfc11 779 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
Kojto 109:9296ab0bfc11 780 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 109:9296ab0bfc11 781 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 109:9296ab0bfc11 782 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Kojto 109:9296ab0bfc11 783 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Kojto 109:9296ab0bfc11 784 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Kojto 109:9296ab0bfc11 785 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Kojto 109:9296ab0bfc11 786 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Kojto 109:9296ab0bfc11 787 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
Kojto 109:9296ab0bfc11 788 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
Kojto 109:9296ab0bfc11 789 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 109:9296ab0bfc11 790 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 109:9296ab0bfc11 791 #define OB ((OB_TypeDef *) OB_BASE)
Kojto 109:9296ab0bfc11 792 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 109:9296ab0bfc11 793 #define TSC ((TSC_TypeDef *) TSC_BASE)
Kojto 109:9296ab0bfc11 794 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 109:9296ab0bfc11 795 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 109:9296ab0bfc11 796 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 109:9296ab0bfc11 797 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 109:9296ab0bfc11 798 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto 109:9296ab0bfc11 799 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 109:9296ab0bfc11 800 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
Kojto 109:9296ab0bfc11 801 #define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
Kojto 109:9296ab0bfc11 802 /**
Kojto 109:9296ab0bfc11 803 * @}
Kojto 109:9296ab0bfc11 804 */
Kojto 109:9296ab0bfc11 805
Kojto 109:9296ab0bfc11 806 /** @addtogroup Exported_constants
Kojto 109:9296ab0bfc11 807 * @{
Kojto 109:9296ab0bfc11 808 */
Kojto 109:9296ab0bfc11 809
Kojto 109:9296ab0bfc11 810 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 109:9296ab0bfc11 811 * @{
Kojto 109:9296ab0bfc11 812 */
Kojto 109:9296ab0bfc11 813
Kojto 109:9296ab0bfc11 814 /******************************************************************************/
Kojto 109:9296ab0bfc11 815 /* Peripheral Registers_Bits_Definition */
Kojto 109:9296ab0bfc11 816 /******************************************************************************/
Kojto 109:9296ab0bfc11 817
Kojto 109:9296ab0bfc11 818 /******************************************************************************/
Kojto 109:9296ab0bfc11 819 /* */
Kojto 109:9296ab0bfc11 820 /* Analog to Digital Converter SAR (ADC) */
Kojto 109:9296ab0bfc11 821 /* */
Kojto 109:9296ab0bfc11 822 /******************************************************************************/
Kojto 109:9296ab0bfc11 823 /******************** Bit definition for ADC_ISR register ********************/
Kojto 109:9296ab0bfc11 824 #define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
Kojto 109:9296ab0bfc11 825 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
Kojto 109:9296ab0bfc11 826 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
Kojto 109:9296ab0bfc11 827 #define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
Kojto 109:9296ab0bfc11 828 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
Kojto 109:9296ab0bfc11 829 #define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
Kojto 109:9296ab0bfc11 830 #define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
Kojto 109:9296ab0bfc11 831 #define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
Kojto 109:9296ab0bfc11 832 #define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
Kojto 109:9296ab0bfc11 833 #define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
Kojto 109:9296ab0bfc11 834 #define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
Kojto 109:9296ab0bfc11 835
Kojto 109:9296ab0bfc11 836 /******************** Bit definition for ADC_IER register ********************/
Kojto 109:9296ab0bfc11 837 #define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
Kojto 109:9296ab0bfc11 838 #define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
Kojto 109:9296ab0bfc11 839 #define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
Kojto 109:9296ab0bfc11 840 #define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
Kojto 109:9296ab0bfc11 841 #define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
Kojto 109:9296ab0bfc11 842 #define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
Kojto 109:9296ab0bfc11 843 #define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
Kojto 109:9296ab0bfc11 844 #define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
Kojto 109:9296ab0bfc11 845 #define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
Kojto 109:9296ab0bfc11 846 #define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
Kojto 109:9296ab0bfc11 847 #define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
Kojto 109:9296ab0bfc11 848
Kojto 109:9296ab0bfc11 849 /******************** Bit definition for ADC_CR register ********************/
Kojto 109:9296ab0bfc11 850 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
Kojto 109:9296ab0bfc11 851 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
Kojto 109:9296ab0bfc11 852 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
Kojto 109:9296ab0bfc11 853 #define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
Kojto 109:9296ab0bfc11 854 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
Kojto 109:9296ab0bfc11 855 #define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
Kojto 109:9296ab0bfc11 856 #define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
Kojto 109:9296ab0bfc11 857 #define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
Kojto 109:9296ab0bfc11 858 #define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
Kojto 109:9296ab0bfc11 859 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
Kojto 109:9296ab0bfc11 860 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
Kojto 109:9296ab0bfc11 861
Kojto 109:9296ab0bfc11 862 /******************** Bit definition for ADC_CFGR register ********************/
Kojto 109:9296ab0bfc11 863 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
Kojto 109:9296ab0bfc11 864 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
Kojto 109:9296ab0bfc11 865
Kojto 109:9296ab0bfc11 866 #define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
Kojto 109:9296ab0bfc11 867 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
Kojto 109:9296ab0bfc11 868 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
Kojto 109:9296ab0bfc11 869
Kojto 109:9296ab0bfc11 870 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */
Kojto 109:9296ab0bfc11 871
Kojto 109:9296ab0bfc11 872 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
Kojto 109:9296ab0bfc11 873 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
Kojto 109:9296ab0bfc11 874 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
Kojto 109:9296ab0bfc11 875 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
Kojto 109:9296ab0bfc11 876 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
Kojto 109:9296ab0bfc11 877
Kojto 109:9296ab0bfc11 878 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
Kojto 109:9296ab0bfc11 879 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
Kojto 109:9296ab0bfc11 880 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
Kojto 109:9296ab0bfc11 881
Kojto 109:9296ab0bfc11 882 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
Kojto 109:9296ab0bfc11 883 #define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
Kojto 109:9296ab0bfc11 884 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
Kojto 109:9296ab0bfc11 885 #define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
Kojto 109:9296ab0bfc11 886 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
Kojto 109:9296ab0bfc11 887
Kojto 109:9296ab0bfc11 888 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
Kojto 109:9296ab0bfc11 889 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
Kojto 109:9296ab0bfc11 890 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
Kojto 109:9296ab0bfc11 891 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
Kojto 109:9296ab0bfc11 892
Kojto 109:9296ab0bfc11 893 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
Kojto 109:9296ab0bfc11 894 #define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
Kojto 109:9296ab0bfc11 895 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
Kojto 109:9296ab0bfc11 896 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
Kojto 109:9296ab0bfc11 897 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
Kojto 109:9296ab0bfc11 898 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
Kojto 109:9296ab0bfc11 899
Kojto 109:9296ab0bfc11 900 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
Kojto 109:9296ab0bfc11 901 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
Kojto 109:9296ab0bfc11 902 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
Kojto 109:9296ab0bfc11 903 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
Kojto 109:9296ab0bfc11 904 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
Kojto 109:9296ab0bfc11 905 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
Kojto 109:9296ab0bfc11 906
Kojto 109:9296ab0bfc11 907 /******************** Bit definition for ADC_SMPR1 register ********************/
Kojto 109:9296ab0bfc11 908 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
Kojto 109:9296ab0bfc11 909 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
Kojto 109:9296ab0bfc11 910 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
Kojto 109:9296ab0bfc11 911 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
Kojto 109:9296ab0bfc11 912
Kojto 109:9296ab0bfc11 913 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
Kojto 109:9296ab0bfc11 914 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
Kojto 109:9296ab0bfc11 915 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
Kojto 109:9296ab0bfc11 916 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
Kojto 109:9296ab0bfc11 917
Kojto 109:9296ab0bfc11 918 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
Kojto 109:9296ab0bfc11 919 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
Kojto 109:9296ab0bfc11 920 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
Kojto 109:9296ab0bfc11 921 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
Kojto 109:9296ab0bfc11 922
Kojto 109:9296ab0bfc11 923 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
Kojto 109:9296ab0bfc11 924 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
Kojto 109:9296ab0bfc11 925 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
Kojto 109:9296ab0bfc11 926 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
Kojto 109:9296ab0bfc11 927
Kojto 109:9296ab0bfc11 928 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
Kojto 109:9296ab0bfc11 929 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
Kojto 109:9296ab0bfc11 930 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
Kojto 109:9296ab0bfc11 931 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
Kojto 109:9296ab0bfc11 932
Kojto 109:9296ab0bfc11 933 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
Kojto 109:9296ab0bfc11 934 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
Kojto 109:9296ab0bfc11 935 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
Kojto 109:9296ab0bfc11 936 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
Kojto 109:9296ab0bfc11 937
Kojto 109:9296ab0bfc11 938 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
Kojto 109:9296ab0bfc11 939 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
Kojto 109:9296ab0bfc11 940 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
Kojto 109:9296ab0bfc11 941 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
Kojto 109:9296ab0bfc11 942
Kojto 109:9296ab0bfc11 943 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
Kojto 109:9296ab0bfc11 944 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
Kojto 109:9296ab0bfc11 945 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
Kojto 109:9296ab0bfc11 946 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
Kojto 109:9296ab0bfc11 947
Kojto 109:9296ab0bfc11 948 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
Kojto 109:9296ab0bfc11 949 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
Kojto 109:9296ab0bfc11 950 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
Kojto 109:9296ab0bfc11 951 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
Kojto 109:9296ab0bfc11 952
Kojto 109:9296ab0bfc11 953 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
Kojto 109:9296ab0bfc11 954 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
Kojto 109:9296ab0bfc11 955 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
Kojto 109:9296ab0bfc11 956 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
Kojto 109:9296ab0bfc11 957
Kojto 109:9296ab0bfc11 958 /******************** Bit definition for ADC_SMPR2 register ********************/
Kojto 109:9296ab0bfc11 959 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
Kojto 109:9296ab0bfc11 960 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
Kojto 109:9296ab0bfc11 961 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
Kojto 109:9296ab0bfc11 962 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
Kojto 109:9296ab0bfc11 963
Kojto 109:9296ab0bfc11 964 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
Kojto 109:9296ab0bfc11 965 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
Kojto 109:9296ab0bfc11 966 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
Kojto 109:9296ab0bfc11 967 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
Kojto 109:9296ab0bfc11 968
Kojto 109:9296ab0bfc11 969 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
Kojto 109:9296ab0bfc11 970 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
Kojto 109:9296ab0bfc11 971 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
Kojto 109:9296ab0bfc11 972 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
Kojto 109:9296ab0bfc11 973
Kojto 109:9296ab0bfc11 974 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
Kojto 109:9296ab0bfc11 975 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
Kojto 109:9296ab0bfc11 976 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
Kojto 109:9296ab0bfc11 977 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
Kojto 109:9296ab0bfc11 978
Kojto 109:9296ab0bfc11 979 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
Kojto 109:9296ab0bfc11 980 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
Kojto 109:9296ab0bfc11 981 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
Kojto 109:9296ab0bfc11 982 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
Kojto 109:9296ab0bfc11 983
Kojto 109:9296ab0bfc11 984 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
Kojto 109:9296ab0bfc11 985 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
Kojto 109:9296ab0bfc11 986 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
Kojto 109:9296ab0bfc11 987 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
Kojto 109:9296ab0bfc11 988
Kojto 109:9296ab0bfc11 989 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
Kojto 109:9296ab0bfc11 990 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
Kojto 109:9296ab0bfc11 991 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
Kojto 109:9296ab0bfc11 992 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
Kojto 109:9296ab0bfc11 993
Kojto 109:9296ab0bfc11 994 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
Kojto 109:9296ab0bfc11 995 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
Kojto 109:9296ab0bfc11 996 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
Kojto 109:9296ab0bfc11 997 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
Kojto 109:9296ab0bfc11 998
Kojto 109:9296ab0bfc11 999 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
Kojto 109:9296ab0bfc11 1000 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
Kojto 109:9296ab0bfc11 1001 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
Kojto 109:9296ab0bfc11 1002 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
Kojto 109:9296ab0bfc11 1003
Kojto 109:9296ab0bfc11 1004 /******************** Bit definition for ADC_TR1 register ********************/
Kojto 109:9296ab0bfc11 1005 #define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
Kojto 109:9296ab0bfc11 1006 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
Kojto 109:9296ab0bfc11 1007 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
Kojto 109:9296ab0bfc11 1008 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
Kojto 109:9296ab0bfc11 1009 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
Kojto 109:9296ab0bfc11 1010 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
Kojto 109:9296ab0bfc11 1011 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
Kojto 109:9296ab0bfc11 1012 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
Kojto 109:9296ab0bfc11 1013 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
Kojto 109:9296ab0bfc11 1014 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
Kojto 109:9296ab0bfc11 1015 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
Kojto 109:9296ab0bfc11 1016 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
Kojto 109:9296ab0bfc11 1017 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
Kojto 109:9296ab0bfc11 1018
Kojto 109:9296ab0bfc11 1019 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
Kojto 109:9296ab0bfc11 1020 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
Kojto 109:9296ab0bfc11 1021 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
Kojto 109:9296ab0bfc11 1022 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
Kojto 109:9296ab0bfc11 1023 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
Kojto 109:9296ab0bfc11 1024 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
Kojto 109:9296ab0bfc11 1025 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
Kojto 109:9296ab0bfc11 1026 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
Kojto 109:9296ab0bfc11 1027 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
Kojto 109:9296ab0bfc11 1028 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
Kojto 109:9296ab0bfc11 1029 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
Kojto 109:9296ab0bfc11 1030 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
Kojto 109:9296ab0bfc11 1031 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
Kojto 109:9296ab0bfc11 1032
Kojto 109:9296ab0bfc11 1033 /******************** Bit definition for ADC_TR2 register ********************/
Kojto 109:9296ab0bfc11 1034 #define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
Kojto 109:9296ab0bfc11 1035 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
Kojto 109:9296ab0bfc11 1036 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
Kojto 109:9296ab0bfc11 1037 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
Kojto 109:9296ab0bfc11 1038 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
Kojto 109:9296ab0bfc11 1039 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
Kojto 109:9296ab0bfc11 1040 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
Kojto 109:9296ab0bfc11 1041 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
Kojto 109:9296ab0bfc11 1042 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
Kojto 109:9296ab0bfc11 1043
Kojto 109:9296ab0bfc11 1044 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
Kojto 109:9296ab0bfc11 1045 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
Kojto 109:9296ab0bfc11 1046 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
Kojto 109:9296ab0bfc11 1047 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
Kojto 109:9296ab0bfc11 1048 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
Kojto 109:9296ab0bfc11 1049 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
Kojto 109:9296ab0bfc11 1050 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
Kojto 109:9296ab0bfc11 1051 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
Kojto 109:9296ab0bfc11 1052 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
Kojto 109:9296ab0bfc11 1053
Kojto 109:9296ab0bfc11 1054 /******************** Bit definition for ADC_TR3 register ********************/
Kojto 109:9296ab0bfc11 1055 #define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
Kojto 109:9296ab0bfc11 1056 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
Kojto 109:9296ab0bfc11 1057 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
Kojto 109:9296ab0bfc11 1058 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
Kojto 109:9296ab0bfc11 1059 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
Kojto 109:9296ab0bfc11 1060 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
Kojto 109:9296ab0bfc11 1061 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
Kojto 109:9296ab0bfc11 1062 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
Kojto 109:9296ab0bfc11 1063 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
Kojto 109:9296ab0bfc11 1064
Kojto 109:9296ab0bfc11 1065 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
Kojto 109:9296ab0bfc11 1066 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
Kojto 109:9296ab0bfc11 1067 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
Kojto 109:9296ab0bfc11 1068 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
Kojto 109:9296ab0bfc11 1069 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
Kojto 109:9296ab0bfc11 1070 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
Kojto 109:9296ab0bfc11 1071 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
Kojto 109:9296ab0bfc11 1072 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
Kojto 109:9296ab0bfc11 1073 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
Kojto 109:9296ab0bfc11 1074
Kojto 109:9296ab0bfc11 1075 /******************** Bit definition for ADC_SQR1 register ********************/
Kojto 109:9296ab0bfc11 1076 #define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
Kojto 109:9296ab0bfc11 1077 #define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
Kojto 109:9296ab0bfc11 1078 #define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
Kojto 109:9296ab0bfc11 1079 #define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
Kojto 109:9296ab0bfc11 1080 #define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
Kojto 109:9296ab0bfc11 1081
Kojto 109:9296ab0bfc11 1082 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
Kojto 109:9296ab0bfc11 1083 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
Kojto 109:9296ab0bfc11 1084 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
Kojto 109:9296ab0bfc11 1085 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
Kojto 109:9296ab0bfc11 1086 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
Kojto 109:9296ab0bfc11 1087 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
Kojto 109:9296ab0bfc11 1088
Kojto 109:9296ab0bfc11 1089 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
Kojto 109:9296ab0bfc11 1090 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
Kojto 109:9296ab0bfc11 1091 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
Kojto 109:9296ab0bfc11 1092 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
Kojto 109:9296ab0bfc11 1093 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
Kojto 109:9296ab0bfc11 1094 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
Kojto 109:9296ab0bfc11 1095
Kojto 109:9296ab0bfc11 1096 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
Kojto 109:9296ab0bfc11 1097 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
Kojto 109:9296ab0bfc11 1098 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
Kojto 109:9296ab0bfc11 1099 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
Kojto 109:9296ab0bfc11 1100 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
Kojto 109:9296ab0bfc11 1101 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
Kojto 109:9296ab0bfc11 1102
Kojto 109:9296ab0bfc11 1103 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
Kojto 109:9296ab0bfc11 1104 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
Kojto 109:9296ab0bfc11 1105 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
Kojto 109:9296ab0bfc11 1106 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
Kojto 109:9296ab0bfc11 1107 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
Kojto 109:9296ab0bfc11 1108 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
Kojto 109:9296ab0bfc11 1109
Kojto 109:9296ab0bfc11 1110 /******************** Bit definition for ADC_SQR2 register ********************/
Kojto 109:9296ab0bfc11 1111 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
Kojto 109:9296ab0bfc11 1112 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
Kojto 109:9296ab0bfc11 1113 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
Kojto 109:9296ab0bfc11 1114 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
Kojto 109:9296ab0bfc11 1115 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
Kojto 109:9296ab0bfc11 1116 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
Kojto 109:9296ab0bfc11 1117
Kojto 109:9296ab0bfc11 1118 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
Kojto 109:9296ab0bfc11 1119 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
Kojto 109:9296ab0bfc11 1120 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
Kojto 109:9296ab0bfc11 1121 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
Kojto 109:9296ab0bfc11 1122 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
Kojto 109:9296ab0bfc11 1123 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
Kojto 109:9296ab0bfc11 1124
Kojto 109:9296ab0bfc11 1125 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
Kojto 109:9296ab0bfc11 1126 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
Kojto 109:9296ab0bfc11 1127 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
Kojto 109:9296ab0bfc11 1128 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
Kojto 109:9296ab0bfc11 1129 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
Kojto 109:9296ab0bfc11 1130 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
Kojto 109:9296ab0bfc11 1131
Kojto 109:9296ab0bfc11 1132 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
Kojto 109:9296ab0bfc11 1133 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
Kojto 109:9296ab0bfc11 1134 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
Kojto 109:9296ab0bfc11 1135 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
Kojto 109:9296ab0bfc11 1136 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
Kojto 109:9296ab0bfc11 1137 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
Kojto 109:9296ab0bfc11 1138
Kojto 109:9296ab0bfc11 1139 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
Kojto 109:9296ab0bfc11 1140 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
Kojto 109:9296ab0bfc11 1141 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
Kojto 109:9296ab0bfc11 1142 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
Kojto 109:9296ab0bfc11 1143 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
Kojto 109:9296ab0bfc11 1144 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
Kojto 109:9296ab0bfc11 1145
Kojto 109:9296ab0bfc11 1146 /******************** Bit definition for ADC_SQR3 register ********************/
Kojto 109:9296ab0bfc11 1147 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
Kojto 109:9296ab0bfc11 1148 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
Kojto 109:9296ab0bfc11 1149 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
Kojto 109:9296ab0bfc11 1150 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
Kojto 109:9296ab0bfc11 1151 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
Kojto 109:9296ab0bfc11 1152 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
Kojto 109:9296ab0bfc11 1153
Kojto 109:9296ab0bfc11 1154 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
Kojto 109:9296ab0bfc11 1155 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
Kojto 109:9296ab0bfc11 1156 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
Kojto 109:9296ab0bfc11 1157 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
Kojto 109:9296ab0bfc11 1158 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
Kojto 109:9296ab0bfc11 1159 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
Kojto 109:9296ab0bfc11 1160
Kojto 109:9296ab0bfc11 1161 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
Kojto 109:9296ab0bfc11 1162 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
Kojto 109:9296ab0bfc11 1163 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
Kojto 109:9296ab0bfc11 1164 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
Kojto 109:9296ab0bfc11 1165 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
Kojto 109:9296ab0bfc11 1166 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
Kojto 109:9296ab0bfc11 1167
Kojto 109:9296ab0bfc11 1168 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
Kojto 109:9296ab0bfc11 1169 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
Kojto 109:9296ab0bfc11 1170 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
Kojto 109:9296ab0bfc11 1171 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
Kojto 109:9296ab0bfc11 1172 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
Kojto 109:9296ab0bfc11 1173 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
Kojto 109:9296ab0bfc11 1174
Kojto 109:9296ab0bfc11 1175 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
Kojto 109:9296ab0bfc11 1176 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
Kojto 109:9296ab0bfc11 1177 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
Kojto 109:9296ab0bfc11 1178 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
Kojto 109:9296ab0bfc11 1179 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
Kojto 109:9296ab0bfc11 1180 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
Kojto 109:9296ab0bfc11 1181
Kojto 109:9296ab0bfc11 1182 /******************** Bit definition for ADC_SQR4 register ********************/
Kojto 109:9296ab0bfc11 1183 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
Kojto 109:9296ab0bfc11 1184 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
Kojto 109:9296ab0bfc11 1185 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
Kojto 109:9296ab0bfc11 1186 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
Kojto 109:9296ab0bfc11 1187 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
Kojto 109:9296ab0bfc11 1188 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
Kojto 109:9296ab0bfc11 1189
Kojto 109:9296ab0bfc11 1190 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
Kojto 109:9296ab0bfc11 1191 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
Kojto 109:9296ab0bfc11 1192 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
Kojto 109:9296ab0bfc11 1193 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
Kojto 109:9296ab0bfc11 1194 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
Kojto 109:9296ab0bfc11 1195 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
Kojto 109:9296ab0bfc11 1196 /******************** Bit definition for ADC_DR register ********************/
Kojto 109:9296ab0bfc11 1197 #define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
Kojto 109:9296ab0bfc11 1198 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
Kojto 109:9296ab0bfc11 1199 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
Kojto 109:9296ab0bfc11 1200 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
Kojto 109:9296ab0bfc11 1201 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
Kojto 109:9296ab0bfc11 1202 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
Kojto 109:9296ab0bfc11 1203 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
Kojto 109:9296ab0bfc11 1204 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
Kojto 109:9296ab0bfc11 1205 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
Kojto 109:9296ab0bfc11 1206 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
Kojto 109:9296ab0bfc11 1207 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
Kojto 109:9296ab0bfc11 1208 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
Kojto 109:9296ab0bfc11 1209 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
Kojto 109:9296ab0bfc11 1210 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
Kojto 109:9296ab0bfc11 1211 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
Kojto 109:9296ab0bfc11 1212 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
Kojto 109:9296ab0bfc11 1213 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
Kojto 109:9296ab0bfc11 1214
Kojto 109:9296ab0bfc11 1215 /******************** Bit definition for ADC_JSQR register ********************/
Kojto 109:9296ab0bfc11 1216 #define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
Kojto 109:9296ab0bfc11 1217 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
Kojto 109:9296ab0bfc11 1218 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
Kojto 109:9296ab0bfc11 1219
Kojto 109:9296ab0bfc11 1220 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
Kojto 109:9296ab0bfc11 1221 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
Kojto 109:9296ab0bfc11 1222 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
Kojto 109:9296ab0bfc11 1223 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
Kojto 109:9296ab0bfc11 1224 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
Kojto 109:9296ab0bfc11 1225
Kojto 109:9296ab0bfc11 1226 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
Kojto 109:9296ab0bfc11 1227 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
Kojto 109:9296ab0bfc11 1228 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
Kojto 109:9296ab0bfc11 1229
Kojto 109:9296ab0bfc11 1230 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
Kojto 109:9296ab0bfc11 1231 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
Kojto 109:9296ab0bfc11 1232 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
Kojto 109:9296ab0bfc11 1233 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
Kojto 109:9296ab0bfc11 1234 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
Kojto 109:9296ab0bfc11 1235 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
Kojto 109:9296ab0bfc11 1236
Kojto 109:9296ab0bfc11 1237 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
Kojto 109:9296ab0bfc11 1238 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
Kojto 109:9296ab0bfc11 1239 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
Kojto 109:9296ab0bfc11 1240 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
Kojto 109:9296ab0bfc11 1241 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
Kojto 109:9296ab0bfc11 1242 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
Kojto 109:9296ab0bfc11 1243
Kojto 109:9296ab0bfc11 1244 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
Kojto 109:9296ab0bfc11 1245 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
Kojto 109:9296ab0bfc11 1246 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
Kojto 109:9296ab0bfc11 1247 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
Kojto 109:9296ab0bfc11 1248 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
Kojto 109:9296ab0bfc11 1249 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
Kojto 109:9296ab0bfc11 1250
Kojto 109:9296ab0bfc11 1251 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
Kojto 109:9296ab0bfc11 1252 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
Kojto 109:9296ab0bfc11 1253 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
Kojto 109:9296ab0bfc11 1254 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
Kojto 109:9296ab0bfc11 1255 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
Kojto 109:9296ab0bfc11 1256 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
Kojto 109:9296ab0bfc11 1257
Kojto 109:9296ab0bfc11 1258 /******************** Bit definition for ADC_OFR1 register ********************/
Kojto 109:9296ab0bfc11 1259 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
Kojto 109:9296ab0bfc11 1260 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
Kojto 109:9296ab0bfc11 1261 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
Kojto 109:9296ab0bfc11 1262 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
Kojto 109:9296ab0bfc11 1263 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
Kojto 109:9296ab0bfc11 1264 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
Kojto 109:9296ab0bfc11 1265 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
Kojto 109:9296ab0bfc11 1266 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
Kojto 109:9296ab0bfc11 1267 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
Kojto 109:9296ab0bfc11 1268 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
Kojto 109:9296ab0bfc11 1269 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
Kojto 109:9296ab0bfc11 1270 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
Kojto 109:9296ab0bfc11 1271 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
Kojto 109:9296ab0bfc11 1272
Kojto 109:9296ab0bfc11 1273 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
Kojto 109:9296ab0bfc11 1274 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
Kojto 109:9296ab0bfc11 1275 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
Kojto 109:9296ab0bfc11 1276 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
Kojto 109:9296ab0bfc11 1277 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
Kojto 109:9296ab0bfc11 1278 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
Kojto 109:9296ab0bfc11 1279
Kojto 109:9296ab0bfc11 1280 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
Kojto 109:9296ab0bfc11 1281
Kojto 109:9296ab0bfc11 1282 /******************** Bit definition for ADC_OFR2 register ********************/
Kojto 109:9296ab0bfc11 1283 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
Kojto 109:9296ab0bfc11 1284 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
Kojto 109:9296ab0bfc11 1285 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
Kojto 109:9296ab0bfc11 1286 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
Kojto 109:9296ab0bfc11 1287 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
Kojto 109:9296ab0bfc11 1288 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
Kojto 109:9296ab0bfc11 1289 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
Kojto 109:9296ab0bfc11 1290 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
Kojto 109:9296ab0bfc11 1291 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
Kojto 109:9296ab0bfc11 1292 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
Kojto 109:9296ab0bfc11 1293 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
Kojto 109:9296ab0bfc11 1294 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
Kojto 109:9296ab0bfc11 1295 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
Kojto 109:9296ab0bfc11 1296
Kojto 109:9296ab0bfc11 1297 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
Kojto 109:9296ab0bfc11 1298 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
Kojto 109:9296ab0bfc11 1299 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
Kojto 109:9296ab0bfc11 1300 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
Kojto 109:9296ab0bfc11 1301 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
Kojto 109:9296ab0bfc11 1302 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
Kojto 109:9296ab0bfc11 1303
Kojto 109:9296ab0bfc11 1304 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
Kojto 109:9296ab0bfc11 1305
Kojto 109:9296ab0bfc11 1306 /******************** Bit definition for ADC_OFR3 register ********************/
Kojto 109:9296ab0bfc11 1307 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
Kojto 109:9296ab0bfc11 1308 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
Kojto 109:9296ab0bfc11 1309 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
Kojto 109:9296ab0bfc11 1310 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
Kojto 109:9296ab0bfc11 1311 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
Kojto 109:9296ab0bfc11 1312 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
Kojto 109:9296ab0bfc11 1313 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
Kojto 109:9296ab0bfc11 1314 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
Kojto 109:9296ab0bfc11 1315 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
Kojto 109:9296ab0bfc11 1316 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
Kojto 109:9296ab0bfc11 1317 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
Kojto 109:9296ab0bfc11 1318 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
Kojto 109:9296ab0bfc11 1319 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
Kojto 109:9296ab0bfc11 1320
Kojto 109:9296ab0bfc11 1321 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
Kojto 109:9296ab0bfc11 1322 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
Kojto 109:9296ab0bfc11 1323 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
Kojto 109:9296ab0bfc11 1324 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
Kojto 109:9296ab0bfc11 1325 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
Kojto 109:9296ab0bfc11 1326 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
Kojto 109:9296ab0bfc11 1327
Kojto 109:9296ab0bfc11 1328 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
Kojto 109:9296ab0bfc11 1329
Kojto 109:9296ab0bfc11 1330 /******************** Bit definition for ADC_OFR4 register ********************/
Kojto 109:9296ab0bfc11 1331 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
Kojto 109:9296ab0bfc11 1332 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
Kojto 109:9296ab0bfc11 1333 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
Kojto 109:9296ab0bfc11 1334 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
Kojto 109:9296ab0bfc11 1335 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
Kojto 109:9296ab0bfc11 1336 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
Kojto 109:9296ab0bfc11 1337 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
Kojto 109:9296ab0bfc11 1338 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
Kojto 109:9296ab0bfc11 1339 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
Kojto 109:9296ab0bfc11 1340 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
Kojto 109:9296ab0bfc11 1341 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
Kojto 109:9296ab0bfc11 1342 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
Kojto 109:9296ab0bfc11 1343 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
Kojto 109:9296ab0bfc11 1344
Kojto 109:9296ab0bfc11 1345 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
Kojto 109:9296ab0bfc11 1346 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
Kojto 109:9296ab0bfc11 1347 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
Kojto 109:9296ab0bfc11 1348 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
Kojto 109:9296ab0bfc11 1349 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
Kojto 109:9296ab0bfc11 1350 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
Kojto 109:9296ab0bfc11 1351
Kojto 109:9296ab0bfc11 1352 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
Kojto 109:9296ab0bfc11 1353
Kojto 109:9296ab0bfc11 1354 /******************** Bit definition for ADC_JDR1 register ********************/
Kojto 109:9296ab0bfc11 1355 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
Kojto 109:9296ab0bfc11 1356 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
Kojto 109:9296ab0bfc11 1357 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
Kojto 109:9296ab0bfc11 1358 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
Kojto 109:9296ab0bfc11 1359 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
Kojto 109:9296ab0bfc11 1360 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
Kojto 109:9296ab0bfc11 1361 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
Kojto 109:9296ab0bfc11 1362 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
Kojto 109:9296ab0bfc11 1363 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
Kojto 109:9296ab0bfc11 1364 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
Kojto 109:9296ab0bfc11 1365 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
Kojto 109:9296ab0bfc11 1366 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
Kojto 109:9296ab0bfc11 1367 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
Kojto 109:9296ab0bfc11 1368 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
Kojto 109:9296ab0bfc11 1369 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
Kojto 109:9296ab0bfc11 1370 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
Kojto 109:9296ab0bfc11 1371 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
Kojto 109:9296ab0bfc11 1372
Kojto 109:9296ab0bfc11 1373 /******************** Bit definition for ADC_JDR2 register ********************/
Kojto 109:9296ab0bfc11 1374 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
Kojto 109:9296ab0bfc11 1375 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
Kojto 109:9296ab0bfc11 1376 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
Kojto 109:9296ab0bfc11 1377 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
Kojto 109:9296ab0bfc11 1378 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
Kojto 109:9296ab0bfc11 1379 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
Kojto 109:9296ab0bfc11 1380 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
Kojto 109:9296ab0bfc11 1381 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
Kojto 109:9296ab0bfc11 1382 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
Kojto 109:9296ab0bfc11 1383 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
Kojto 109:9296ab0bfc11 1384 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
Kojto 109:9296ab0bfc11 1385 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
Kojto 109:9296ab0bfc11 1386 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
Kojto 109:9296ab0bfc11 1387 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
Kojto 109:9296ab0bfc11 1388 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
Kojto 109:9296ab0bfc11 1389 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
Kojto 109:9296ab0bfc11 1390 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
Kojto 109:9296ab0bfc11 1391
Kojto 109:9296ab0bfc11 1392 /******************** Bit definition for ADC_JDR3 register ********************/
Kojto 109:9296ab0bfc11 1393 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
Kojto 109:9296ab0bfc11 1394 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
Kojto 109:9296ab0bfc11 1395 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
Kojto 109:9296ab0bfc11 1396 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
Kojto 109:9296ab0bfc11 1397 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
Kojto 109:9296ab0bfc11 1398 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
Kojto 109:9296ab0bfc11 1399 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
Kojto 109:9296ab0bfc11 1400 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
Kojto 109:9296ab0bfc11 1401 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
Kojto 109:9296ab0bfc11 1402 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
Kojto 109:9296ab0bfc11 1403 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
Kojto 109:9296ab0bfc11 1404 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
Kojto 109:9296ab0bfc11 1405 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
Kojto 109:9296ab0bfc11 1406 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
Kojto 109:9296ab0bfc11 1407 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
Kojto 109:9296ab0bfc11 1408 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
Kojto 109:9296ab0bfc11 1409 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
Kojto 109:9296ab0bfc11 1410
Kojto 109:9296ab0bfc11 1411 /******************** Bit definition for ADC_JDR4 register ********************/
Kojto 109:9296ab0bfc11 1412 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
Kojto 109:9296ab0bfc11 1413 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
Kojto 109:9296ab0bfc11 1414 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
Kojto 109:9296ab0bfc11 1415 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
Kojto 109:9296ab0bfc11 1416 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
Kojto 109:9296ab0bfc11 1417 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
Kojto 109:9296ab0bfc11 1418 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
Kojto 109:9296ab0bfc11 1419 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
Kojto 109:9296ab0bfc11 1420 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
Kojto 109:9296ab0bfc11 1421 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
Kojto 109:9296ab0bfc11 1422 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
Kojto 109:9296ab0bfc11 1423 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
Kojto 109:9296ab0bfc11 1424 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
Kojto 109:9296ab0bfc11 1425 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
Kojto 109:9296ab0bfc11 1426 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
Kojto 109:9296ab0bfc11 1427 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
Kojto 109:9296ab0bfc11 1428 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
Kojto 109:9296ab0bfc11 1429
Kojto 109:9296ab0bfc11 1430 /******************** Bit definition for ADC_AWD2CR register ********************/
Kojto 109:9296ab0bfc11 1431 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
Kojto 109:9296ab0bfc11 1432 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
Kojto 109:9296ab0bfc11 1433 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
Kojto 109:9296ab0bfc11 1434 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
Kojto 109:9296ab0bfc11 1435 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
Kojto 109:9296ab0bfc11 1436 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
Kojto 109:9296ab0bfc11 1437 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
Kojto 109:9296ab0bfc11 1438 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
Kojto 109:9296ab0bfc11 1439 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
Kojto 109:9296ab0bfc11 1440 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
Kojto 109:9296ab0bfc11 1441 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
Kojto 109:9296ab0bfc11 1442 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
Kojto 109:9296ab0bfc11 1443 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
Kojto 109:9296ab0bfc11 1444 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
Kojto 109:9296ab0bfc11 1445 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
Kojto 109:9296ab0bfc11 1446 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
Kojto 109:9296ab0bfc11 1447 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
Kojto 109:9296ab0bfc11 1448 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
Kojto 109:9296ab0bfc11 1449 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
Kojto 109:9296ab0bfc11 1450
Kojto 109:9296ab0bfc11 1451 /******************** Bit definition for ADC_AWD3CR register ********************/
Kojto 109:9296ab0bfc11 1452 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
Kojto 109:9296ab0bfc11 1453 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
Kojto 109:9296ab0bfc11 1454 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
Kojto 109:9296ab0bfc11 1455 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
Kojto 109:9296ab0bfc11 1456 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
Kojto 109:9296ab0bfc11 1457 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
Kojto 109:9296ab0bfc11 1458 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
Kojto 109:9296ab0bfc11 1459 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
Kojto 109:9296ab0bfc11 1460 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
Kojto 109:9296ab0bfc11 1461 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
Kojto 109:9296ab0bfc11 1462 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
Kojto 109:9296ab0bfc11 1463 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
Kojto 109:9296ab0bfc11 1464 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
Kojto 109:9296ab0bfc11 1465 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
Kojto 109:9296ab0bfc11 1466 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
Kojto 109:9296ab0bfc11 1467 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
Kojto 109:9296ab0bfc11 1468 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
Kojto 109:9296ab0bfc11 1469 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
Kojto 109:9296ab0bfc11 1470 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
Kojto 109:9296ab0bfc11 1471
Kojto 109:9296ab0bfc11 1472 /******************** Bit definition for ADC_DIFSEL register ********************/
Kojto 109:9296ab0bfc11 1473 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
Kojto 109:9296ab0bfc11 1474 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
Kojto 109:9296ab0bfc11 1475 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
Kojto 109:9296ab0bfc11 1476 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
Kojto 109:9296ab0bfc11 1477 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
Kojto 109:9296ab0bfc11 1478 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
Kojto 109:9296ab0bfc11 1479 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
Kojto 109:9296ab0bfc11 1480 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
Kojto 109:9296ab0bfc11 1481 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
Kojto 109:9296ab0bfc11 1482 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
Kojto 109:9296ab0bfc11 1483 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
Kojto 109:9296ab0bfc11 1484 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
Kojto 109:9296ab0bfc11 1485 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
Kojto 109:9296ab0bfc11 1486 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
Kojto 109:9296ab0bfc11 1487 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
Kojto 109:9296ab0bfc11 1488 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
Kojto 109:9296ab0bfc11 1489 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
Kojto 109:9296ab0bfc11 1490 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
Kojto 109:9296ab0bfc11 1491 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
Kojto 109:9296ab0bfc11 1492
Kojto 109:9296ab0bfc11 1493 /******************** Bit definition for ADC_CALFACT register ********************/
Kojto 109:9296ab0bfc11 1494 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
Kojto 109:9296ab0bfc11 1495 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
Kojto 109:9296ab0bfc11 1496 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
Kojto 109:9296ab0bfc11 1497 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
Kojto 109:9296ab0bfc11 1498 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
Kojto 109:9296ab0bfc11 1499 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
Kojto 109:9296ab0bfc11 1500 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
Kojto 109:9296ab0bfc11 1501 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
Kojto 109:9296ab0bfc11 1502 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
Kojto 109:9296ab0bfc11 1503 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
Kojto 109:9296ab0bfc11 1504 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
Kojto 109:9296ab0bfc11 1505 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
Kojto 109:9296ab0bfc11 1506 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
Kojto 109:9296ab0bfc11 1507 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
Kojto 109:9296ab0bfc11 1508 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
Kojto 109:9296ab0bfc11 1509 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
Kojto 109:9296ab0bfc11 1510
Kojto 109:9296ab0bfc11 1511 /************************* ADC Common registers *****************************/
Kojto 109:9296ab0bfc11 1512 /******************** Bit definition for ADC12_CSR register ********************/
Kojto 109:9296ab0bfc11 1513 #define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
Kojto 109:9296ab0bfc11 1514 #define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
Kojto 109:9296ab0bfc11 1515 #define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
Kojto 109:9296ab0bfc11 1516 #define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
Kojto 109:9296ab0bfc11 1517 #define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
Kojto 109:9296ab0bfc11 1518 #define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
Kojto 109:9296ab0bfc11 1519 #define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
Kojto 109:9296ab0bfc11 1520 #define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
Kojto 109:9296ab0bfc11 1521 #define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
Kojto 109:9296ab0bfc11 1522 #define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
Kojto 109:9296ab0bfc11 1523 #define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
Kojto 109:9296ab0bfc11 1524 #define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
Kojto 109:9296ab0bfc11 1525 #define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
Kojto 109:9296ab0bfc11 1526 #define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
Kojto 109:9296ab0bfc11 1527 #define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
Kojto 109:9296ab0bfc11 1528 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
Kojto 109:9296ab0bfc11 1529 #define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
Kojto 109:9296ab0bfc11 1530 #define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
Kojto 109:9296ab0bfc11 1531 #define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
Kojto 109:9296ab0bfc11 1532 #define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
Kojto 109:9296ab0bfc11 1533 #define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
Kojto 109:9296ab0bfc11 1534 #define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
Kojto 109:9296ab0bfc11 1535
Kojto 109:9296ab0bfc11 1536 /******************** Bit definition for ADC_CCR register ********************/
Kojto 109:9296ab0bfc11 1537 #define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
Kojto 109:9296ab0bfc11 1538 #define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
Kojto 109:9296ab0bfc11 1539 #define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
Kojto 109:9296ab0bfc11 1540 #define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
Kojto 109:9296ab0bfc11 1541 #define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
Kojto 109:9296ab0bfc11 1542 #define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
Kojto 109:9296ab0bfc11 1543 #define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
Kojto 109:9296ab0bfc11 1544 #define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
Kojto 109:9296ab0bfc11 1545 #define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
Kojto 109:9296ab0bfc11 1546 #define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
Kojto 109:9296ab0bfc11 1547 #define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
Kojto 109:9296ab0bfc11 1548 #define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
Kojto 109:9296ab0bfc11 1549 #define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
Kojto 109:9296ab0bfc11 1550 #define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
Kojto 109:9296ab0bfc11 1551 #define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
Kojto 109:9296ab0bfc11 1552 #define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
Kojto 109:9296ab0bfc11 1553 #define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
Kojto 109:9296ab0bfc11 1554 #define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
Kojto 109:9296ab0bfc11 1555 #define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
Kojto 109:9296ab0bfc11 1556 #define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
Kojto 109:9296ab0bfc11 1557 #define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
Kojto 109:9296ab0bfc11 1558
Kojto 109:9296ab0bfc11 1559 /******************** Bit definition for ADC_CDR register ********************/
Kojto 109:9296ab0bfc11 1560 #define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
Kojto 109:9296ab0bfc11 1561 #define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
Kojto 109:9296ab0bfc11 1562 #define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
Kojto 109:9296ab0bfc11 1563 #define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
Kojto 109:9296ab0bfc11 1564 #define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
Kojto 109:9296ab0bfc11 1565 #define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
Kojto 109:9296ab0bfc11 1566 #define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
Kojto 109:9296ab0bfc11 1567 #define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
Kojto 109:9296ab0bfc11 1568 #define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
Kojto 109:9296ab0bfc11 1569 #define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
Kojto 109:9296ab0bfc11 1570 #define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
Kojto 109:9296ab0bfc11 1571 #define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
Kojto 109:9296ab0bfc11 1572 #define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
Kojto 109:9296ab0bfc11 1573 #define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
Kojto 109:9296ab0bfc11 1574 #define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
Kojto 109:9296ab0bfc11 1575 #define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
Kojto 109:9296ab0bfc11 1576 #define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
Kojto 109:9296ab0bfc11 1577
Kojto 109:9296ab0bfc11 1578 #define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
Kojto 109:9296ab0bfc11 1579 #define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
Kojto 109:9296ab0bfc11 1580 #define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
Kojto 109:9296ab0bfc11 1581 #define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
Kojto 109:9296ab0bfc11 1582 #define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
Kojto 109:9296ab0bfc11 1583 #define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
Kojto 109:9296ab0bfc11 1584 #define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
Kojto 109:9296ab0bfc11 1585 #define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
Kojto 109:9296ab0bfc11 1586 #define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
Kojto 109:9296ab0bfc11 1587 #define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
Kojto 109:9296ab0bfc11 1588 #define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
Kojto 109:9296ab0bfc11 1589 #define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
Kojto 109:9296ab0bfc11 1590 #define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
Kojto 109:9296ab0bfc11 1591 #define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
Kojto 109:9296ab0bfc11 1592 #define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
Kojto 109:9296ab0bfc11 1593 #define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
Kojto 109:9296ab0bfc11 1594 #define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
Kojto 109:9296ab0bfc11 1595
Kojto 109:9296ab0bfc11 1596 /******************************************************************************/
Kojto 109:9296ab0bfc11 1597 /* */
Kojto 109:9296ab0bfc11 1598 /* Analog Comparators (COMP) */
Kojto 109:9296ab0bfc11 1599 /* */
Kojto 109:9296ab0bfc11 1600 /******************************************************************************/
Kojto 109:9296ab0bfc11 1601 /********************** Bit definition for COMP2_CSR register ***************/
Kojto 109:9296ab0bfc11 1602 #define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
Kojto 109:9296ab0bfc11 1603 #define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
Kojto 109:9296ab0bfc11 1604 #define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
Kojto 109:9296ab0bfc11 1605 #define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
Kojto 109:9296ab0bfc11 1606 #define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
Kojto 109:9296ab0bfc11 1607 #define COMP2_CSR_COMP2INSEL_3 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 3 */
Kojto 109:9296ab0bfc11 1608 #define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
Kojto 109:9296ab0bfc11 1609 #define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
Kojto 109:9296ab0bfc11 1610 #define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
Kojto 109:9296ab0bfc11 1611 #define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
Kojto 109:9296ab0bfc11 1612 #define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
Kojto 109:9296ab0bfc11 1613 #define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
Kojto 109:9296ab0bfc11 1614 #define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
Kojto 109:9296ab0bfc11 1615 #define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
Kojto 109:9296ab0bfc11 1616 #define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
Kojto 109:9296ab0bfc11 1617 #define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
Kojto 109:9296ab0bfc11 1618 #define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
Kojto 109:9296ab0bfc11 1619 #define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
Kojto 109:9296ab0bfc11 1620
Kojto 109:9296ab0bfc11 1621 /********************** Bit definition for COMP4_CSR register ***************/
Kojto 109:9296ab0bfc11 1622 #define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
Kojto 109:9296ab0bfc11 1623 #define COMP4_CSR_COMP4INSEL ((uint32_t)0x00400070) /*!< COMP4 inverting input select */
Kojto 109:9296ab0bfc11 1624 #define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
Kojto 109:9296ab0bfc11 1625 #define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
Kojto 109:9296ab0bfc11 1626 #define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
Kojto 109:9296ab0bfc11 1627 #define COMP4_CSR_COMP4INSEL_3 ((uint32_t)0x00400000) /*!< COMP4 inverting input select bit 3 */
Kojto 109:9296ab0bfc11 1628 #define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
Kojto 109:9296ab0bfc11 1629 #define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
Kojto 109:9296ab0bfc11 1630 #define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
Kojto 109:9296ab0bfc11 1631 #define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
Kojto 109:9296ab0bfc11 1632 #define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
Kojto 109:9296ab0bfc11 1633 #define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
Kojto 109:9296ab0bfc11 1634 #define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
Kojto 109:9296ab0bfc11 1635 #define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
Kojto 109:9296ab0bfc11 1636 #define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
Kojto 109:9296ab0bfc11 1637 #define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
Kojto 109:9296ab0bfc11 1638 #define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
Kojto 109:9296ab0bfc11 1639 #define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
Kojto 109:9296ab0bfc11 1640
Kojto 109:9296ab0bfc11 1641 /********************** Bit definition for COMP6_CSR register ***************/
Kojto 109:9296ab0bfc11 1642 #define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
Kojto 109:9296ab0bfc11 1643 #define COMP6_CSR_COMP6INSEL ((uint32_t)0x00400070) /*!< COMP6 inverting input select */
Kojto 109:9296ab0bfc11 1644 #define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
Kojto 109:9296ab0bfc11 1645 #define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
Kojto 109:9296ab0bfc11 1646 #define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
Kojto 109:9296ab0bfc11 1647 #define COMP6_CSR_COMP6INSEL_3 ((uint32_t)0x00400000) /*!< COMP6 inverting input select bit 3 */
Kojto 109:9296ab0bfc11 1648 #define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
Kojto 109:9296ab0bfc11 1649 #define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
Kojto 109:9296ab0bfc11 1650 #define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
Kojto 109:9296ab0bfc11 1651 #define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
Kojto 109:9296ab0bfc11 1652 #define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
Kojto 109:9296ab0bfc11 1653 #define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
Kojto 109:9296ab0bfc11 1654 #define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
Kojto 109:9296ab0bfc11 1655 #define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
Kojto 109:9296ab0bfc11 1656 #define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
Kojto 109:9296ab0bfc11 1657 #define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
Kojto 109:9296ab0bfc11 1658 #define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
Kojto 109:9296ab0bfc11 1659 #define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
Kojto 109:9296ab0bfc11 1660
Kojto 109:9296ab0bfc11 1661 /********************** Bit definition for COMP_CSR register ****************/
Kojto 109:9296ab0bfc11 1662 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
Kojto 109:9296ab0bfc11 1663 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00400070) /*!< COMPx inverting input select */
Kojto 109:9296ab0bfc11 1664 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
Kojto 109:9296ab0bfc11 1665 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
Kojto 109:9296ab0bfc11 1666 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
Kojto 109:9296ab0bfc11 1667 #define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
Kojto 109:9296ab0bfc11 1668 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
Kojto 109:9296ab0bfc11 1669 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
Kojto 109:9296ab0bfc11 1670 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
Kojto 109:9296ab0bfc11 1671 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
Kojto 109:9296ab0bfc11 1672 #define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
Kojto 109:9296ab0bfc11 1673 #define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
Kojto 109:9296ab0bfc11 1674 #define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
Kojto 109:9296ab0bfc11 1675 #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
Kojto 109:9296ab0bfc11 1676 #define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
Kojto 109:9296ab0bfc11 1677 #define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
Kojto 109:9296ab0bfc11 1678 #define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
Kojto 109:9296ab0bfc11 1679 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
Kojto 109:9296ab0bfc11 1680
Kojto 109:9296ab0bfc11 1681 /******************************************************************************/
Kojto 109:9296ab0bfc11 1682 /* */
Kojto 109:9296ab0bfc11 1683 /* Operational Amplifier (OPAMP) */
Kojto 109:9296ab0bfc11 1684 /* */
Kojto 109:9296ab0bfc11 1685 /******************************************************************************/
Kojto 109:9296ab0bfc11 1686 /********************* Bit definition for OPAMP2_CSR register ***************/
Kojto 109:9296ab0bfc11 1687 #define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
Kojto 109:9296ab0bfc11 1688 #define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
Kojto 109:9296ab0bfc11 1689 #define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
Kojto 109:9296ab0bfc11 1690 #define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1691 #define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1692 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
Kojto 109:9296ab0bfc11 1693 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1694 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1695 #define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
Kojto 109:9296ab0bfc11 1696 #define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
Kojto 109:9296ab0bfc11 1697 #define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
Kojto 109:9296ab0bfc11 1698 #define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1699 #define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1700 #define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
Kojto 109:9296ab0bfc11 1701 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
Kojto 109:9296ab0bfc11 1702 #define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1703 #define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1704 #define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
Kojto 109:9296ab0bfc11 1705 #define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1706 #define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1707 #define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 1708 #define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 1709 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
Kojto 109:9296ab0bfc11 1710 #define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
Kojto 109:9296ab0bfc11 1711 #define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
Kojto 109:9296ab0bfc11 1712 #define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
Kojto 109:9296ab0bfc11 1713 #define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
Kojto 109:9296ab0bfc11 1714 #define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
Kojto 109:9296ab0bfc11 1715
Kojto 109:9296ab0bfc11 1716 /********************* Bit definition for OPAMPx_CSR register ***************/
Kojto 109:9296ab0bfc11 1717 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
Kojto 109:9296ab0bfc11 1718 #define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
Kojto 109:9296ab0bfc11 1719 #define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
Kojto 109:9296ab0bfc11 1720 #define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1721 #define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1722 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
Kojto 109:9296ab0bfc11 1723 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1724 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1725 #define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
Kojto 109:9296ab0bfc11 1726 #define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
Kojto 109:9296ab0bfc11 1727 #define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
Kojto 109:9296ab0bfc11 1728 #define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1729 #define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1730 #define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
Kojto 109:9296ab0bfc11 1731 #define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
Kojto 109:9296ab0bfc11 1732 #define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1733 #define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1734 #define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
Kojto 109:9296ab0bfc11 1735 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1736 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1737 #define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 1738 #define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 1739 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
Kojto 109:9296ab0bfc11 1740 #define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
Kojto 109:9296ab0bfc11 1741 #define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
Kojto 109:9296ab0bfc11 1742 #define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
Kojto 109:9296ab0bfc11 1743 #define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
Kojto 109:9296ab0bfc11 1744 #define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
Kojto 109:9296ab0bfc11 1745
Kojto 109:9296ab0bfc11 1746 /******************************************************************************/
Kojto 109:9296ab0bfc11 1747 /* */
Kojto 109:9296ab0bfc11 1748 /* Controller Area Network (CAN ) */
Kojto 109:9296ab0bfc11 1749 /* */
Kojto 109:9296ab0bfc11 1750 /******************************************************************************/
Kojto 109:9296ab0bfc11 1751 /******************* Bit definition for CAN_MCR register ********************/
Kojto 109:9296ab0bfc11 1752 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
Kojto 109:9296ab0bfc11 1753 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
Kojto 109:9296ab0bfc11 1754 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
Kojto 109:9296ab0bfc11 1755 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
Kojto 109:9296ab0bfc11 1756 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
Kojto 109:9296ab0bfc11 1757 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
Kojto 109:9296ab0bfc11 1758 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
Kojto 109:9296ab0bfc11 1759 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
Kojto 109:9296ab0bfc11 1760 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
Kojto 109:9296ab0bfc11 1761
Kojto 109:9296ab0bfc11 1762 /******************* Bit definition for CAN_MSR register ********************/
Kojto 109:9296ab0bfc11 1763 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
Kojto 109:9296ab0bfc11 1764 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
Kojto 109:9296ab0bfc11 1765 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
Kojto 109:9296ab0bfc11 1766 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
Kojto 109:9296ab0bfc11 1767 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
Kojto 109:9296ab0bfc11 1768 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
Kojto 109:9296ab0bfc11 1769 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
Kojto 109:9296ab0bfc11 1770 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
Kojto 109:9296ab0bfc11 1771 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
Kojto 109:9296ab0bfc11 1772
Kojto 109:9296ab0bfc11 1773 /******************* Bit definition for CAN_TSR register ********************/
Kojto 109:9296ab0bfc11 1774 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
Kojto 109:9296ab0bfc11 1775 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
Kojto 109:9296ab0bfc11 1776 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
Kojto 109:9296ab0bfc11 1777 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
Kojto 109:9296ab0bfc11 1778 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
Kojto 109:9296ab0bfc11 1779 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
Kojto 109:9296ab0bfc11 1780 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
Kojto 109:9296ab0bfc11 1781 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
Kojto 109:9296ab0bfc11 1782 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
Kojto 109:9296ab0bfc11 1783 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
Kojto 109:9296ab0bfc11 1784 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
Kojto 109:9296ab0bfc11 1785 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
Kojto 109:9296ab0bfc11 1786 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
Kojto 109:9296ab0bfc11 1787 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
Kojto 109:9296ab0bfc11 1788 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
Kojto 109:9296ab0bfc11 1789 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
Kojto 109:9296ab0bfc11 1790
Kojto 109:9296ab0bfc11 1791 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
Kojto 109:9296ab0bfc11 1792 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
Kojto 109:9296ab0bfc11 1793 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
Kojto 109:9296ab0bfc11 1794 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
Kojto 109:9296ab0bfc11 1795
Kojto 109:9296ab0bfc11 1796 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
Kojto 109:9296ab0bfc11 1797 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
Kojto 109:9296ab0bfc11 1798 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
Kojto 109:9296ab0bfc11 1799 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
Kojto 109:9296ab0bfc11 1800
Kojto 109:9296ab0bfc11 1801 /******************* Bit definition for CAN_RF0R register *******************/
Kojto 109:9296ab0bfc11 1802 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
Kojto 109:9296ab0bfc11 1803 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
Kojto 109:9296ab0bfc11 1804 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
Kojto 109:9296ab0bfc11 1805 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
Kojto 109:9296ab0bfc11 1806
Kojto 109:9296ab0bfc11 1807 /******************* Bit definition for CAN_RF1R register *******************/
Kojto 109:9296ab0bfc11 1808 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
Kojto 109:9296ab0bfc11 1809 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
Kojto 109:9296ab0bfc11 1810 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
Kojto 109:9296ab0bfc11 1811 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
Kojto 109:9296ab0bfc11 1812
Kojto 109:9296ab0bfc11 1813 /******************** Bit definition for CAN_IER register *******************/
Kojto 109:9296ab0bfc11 1814 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
Kojto 109:9296ab0bfc11 1815 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
Kojto 109:9296ab0bfc11 1816 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
Kojto 109:9296ab0bfc11 1817 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
Kojto 109:9296ab0bfc11 1818 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
Kojto 109:9296ab0bfc11 1819 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
Kojto 109:9296ab0bfc11 1820 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
Kojto 109:9296ab0bfc11 1821 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
Kojto 109:9296ab0bfc11 1822 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
Kojto 109:9296ab0bfc11 1823 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
Kojto 109:9296ab0bfc11 1824 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
Kojto 109:9296ab0bfc11 1825 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
Kojto 109:9296ab0bfc11 1826 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
Kojto 109:9296ab0bfc11 1827 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
Kojto 109:9296ab0bfc11 1828
Kojto 109:9296ab0bfc11 1829 /******************** Bit definition for CAN_ESR register *******************/
Kojto 109:9296ab0bfc11 1830 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
Kojto 109:9296ab0bfc11 1831 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
Kojto 109:9296ab0bfc11 1832 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
Kojto 109:9296ab0bfc11 1833
Kojto 109:9296ab0bfc11 1834 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
Kojto 109:9296ab0bfc11 1835 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 1836 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 1837 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 1838
Kojto 109:9296ab0bfc11 1839 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
Kojto 109:9296ab0bfc11 1840 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
Kojto 109:9296ab0bfc11 1841
Kojto 109:9296ab0bfc11 1842 /******************* Bit definition for CAN_BTR register ********************/
Kojto 109:9296ab0bfc11 1843 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
Kojto 109:9296ab0bfc11 1844 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
Kojto 109:9296ab0bfc11 1845 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
Kojto 109:9296ab0bfc11 1846 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
Kojto 109:9296ab0bfc11 1847 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
Kojto 109:9296ab0bfc11 1848 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
Kojto 109:9296ab0bfc11 1849 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
Kojto 109:9296ab0bfc11 1850 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
Kojto 109:9296ab0bfc11 1851 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
Kojto 109:9296ab0bfc11 1852 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
Kojto 109:9296ab0bfc11 1853 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
Kojto 109:9296ab0bfc11 1854 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
Kojto 109:9296ab0bfc11 1855 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
Kojto 109:9296ab0bfc11 1856 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
Kojto 109:9296ab0bfc11 1857 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
Kojto 109:9296ab0bfc11 1858
Kojto 109:9296ab0bfc11 1859 /*!<Mailbox registers */
Kojto 109:9296ab0bfc11 1860 /****************** Bit definition for CAN_TI0R register ********************/
Kojto 109:9296ab0bfc11 1861 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 109:9296ab0bfc11 1862 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 109:9296ab0bfc11 1863 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 109:9296ab0bfc11 1864 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 109:9296ab0bfc11 1865 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 109:9296ab0bfc11 1866
Kojto 109:9296ab0bfc11 1867 /****************** Bit definition for CAN_TDT0R register *******************/
Kojto 109:9296ab0bfc11 1868 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 109:9296ab0bfc11 1869 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 109:9296ab0bfc11 1870 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 109:9296ab0bfc11 1871
Kojto 109:9296ab0bfc11 1872 /****************** Bit definition for CAN_TDL0R register *******************/
Kojto 109:9296ab0bfc11 1873 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 109:9296ab0bfc11 1874 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 109:9296ab0bfc11 1875 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 109:9296ab0bfc11 1876 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 109:9296ab0bfc11 1877
Kojto 109:9296ab0bfc11 1878 /****************** Bit definition for CAN_TDH0R register *******************/
Kojto 109:9296ab0bfc11 1879 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 109:9296ab0bfc11 1880 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 109:9296ab0bfc11 1881 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 109:9296ab0bfc11 1882 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 109:9296ab0bfc11 1883
Kojto 109:9296ab0bfc11 1884 /******************* Bit definition for CAN_TI1R register *******************/
Kojto 109:9296ab0bfc11 1885 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 109:9296ab0bfc11 1886 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 109:9296ab0bfc11 1887 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 109:9296ab0bfc11 1888 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 109:9296ab0bfc11 1889 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 109:9296ab0bfc11 1890
Kojto 109:9296ab0bfc11 1891 /******************* Bit definition for CAN_TDT1R register ******************/
Kojto 109:9296ab0bfc11 1892 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 109:9296ab0bfc11 1893 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 109:9296ab0bfc11 1894 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 109:9296ab0bfc11 1895
Kojto 109:9296ab0bfc11 1896 /******************* Bit definition for CAN_TDL1R register ******************/
Kojto 109:9296ab0bfc11 1897 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 109:9296ab0bfc11 1898 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 109:9296ab0bfc11 1899 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 109:9296ab0bfc11 1900 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 109:9296ab0bfc11 1901
Kojto 109:9296ab0bfc11 1902 /******************* Bit definition for CAN_TDH1R register ******************/
Kojto 109:9296ab0bfc11 1903 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 109:9296ab0bfc11 1904 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 109:9296ab0bfc11 1905 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 109:9296ab0bfc11 1906 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 109:9296ab0bfc11 1907
Kojto 109:9296ab0bfc11 1908 /******************* Bit definition for CAN_TI2R register *******************/
Kojto 109:9296ab0bfc11 1909 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 109:9296ab0bfc11 1910 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 109:9296ab0bfc11 1911 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 109:9296ab0bfc11 1912 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Kojto 109:9296ab0bfc11 1913 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 109:9296ab0bfc11 1914
Kojto 109:9296ab0bfc11 1915 /******************* Bit definition for CAN_TDT2R register ******************/
Kojto 109:9296ab0bfc11 1916 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 109:9296ab0bfc11 1917 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 109:9296ab0bfc11 1918 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 109:9296ab0bfc11 1919
Kojto 109:9296ab0bfc11 1920 /******************* Bit definition for CAN_TDL2R register ******************/
Kojto 109:9296ab0bfc11 1921 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 109:9296ab0bfc11 1922 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 109:9296ab0bfc11 1923 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 109:9296ab0bfc11 1924 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 109:9296ab0bfc11 1925
Kojto 109:9296ab0bfc11 1926 /******************* Bit definition for CAN_TDH2R register ******************/
Kojto 109:9296ab0bfc11 1927 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 109:9296ab0bfc11 1928 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 109:9296ab0bfc11 1929 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 109:9296ab0bfc11 1930 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 109:9296ab0bfc11 1931
Kojto 109:9296ab0bfc11 1932 /******************* Bit definition for CAN_RI0R register *******************/
Kojto 109:9296ab0bfc11 1933 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 109:9296ab0bfc11 1934 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 109:9296ab0bfc11 1935 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 109:9296ab0bfc11 1936 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 109:9296ab0bfc11 1937
Kojto 109:9296ab0bfc11 1938 /******************* Bit definition for CAN_RDT0R register ******************/
Kojto 109:9296ab0bfc11 1939 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 109:9296ab0bfc11 1940 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Kojto 109:9296ab0bfc11 1941 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 109:9296ab0bfc11 1942
Kojto 109:9296ab0bfc11 1943 /******************* Bit definition for CAN_RDL0R register ******************/
Kojto 109:9296ab0bfc11 1944 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 109:9296ab0bfc11 1945 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 109:9296ab0bfc11 1946 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 109:9296ab0bfc11 1947 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 109:9296ab0bfc11 1948
Kojto 109:9296ab0bfc11 1949 /******************* Bit definition for CAN_RDH0R register ******************/
Kojto 109:9296ab0bfc11 1950 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 109:9296ab0bfc11 1951 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 109:9296ab0bfc11 1952 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 109:9296ab0bfc11 1953 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 109:9296ab0bfc11 1954
Kojto 109:9296ab0bfc11 1955 /******************* Bit definition for CAN_RI1R register *******************/
Kojto 109:9296ab0bfc11 1956 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 109:9296ab0bfc11 1957 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 109:9296ab0bfc11 1958 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Kojto 109:9296ab0bfc11 1959 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 109:9296ab0bfc11 1960
Kojto 109:9296ab0bfc11 1961 /******************* Bit definition for CAN_RDT1R register ******************/
Kojto 109:9296ab0bfc11 1962 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 109:9296ab0bfc11 1963 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Kojto 109:9296ab0bfc11 1964 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 109:9296ab0bfc11 1965
Kojto 109:9296ab0bfc11 1966 /******************* Bit definition for CAN_RDL1R register ******************/
Kojto 109:9296ab0bfc11 1967 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 109:9296ab0bfc11 1968 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 109:9296ab0bfc11 1969 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 109:9296ab0bfc11 1970 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 109:9296ab0bfc11 1971
Kojto 109:9296ab0bfc11 1972 /******************* Bit definition for CAN_RDH1R register ******************/
Kojto 109:9296ab0bfc11 1973 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 109:9296ab0bfc11 1974 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 109:9296ab0bfc11 1975 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 109:9296ab0bfc11 1976 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 109:9296ab0bfc11 1977
Kojto 109:9296ab0bfc11 1978 /*!<CAN filter registers */
Kojto 109:9296ab0bfc11 1979 /******************* Bit definition for CAN_FMR register ********************/
Kojto 109:9296ab0bfc11 1980 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
Kojto 109:9296ab0bfc11 1981
Kojto 109:9296ab0bfc11 1982 /******************* Bit definition for CAN_FM1R register *******************/
Kojto 109:9296ab0bfc11 1983 #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
Kojto 109:9296ab0bfc11 1984 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
Kojto 109:9296ab0bfc11 1985 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
Kojto 109:9296ab0bfc11 1986 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
Kojto 109:9296ab0bfc11 1987 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
Kojto 109:9296ab0bfc11 1988 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
Kojto 109:9296ab0bfc11 1989 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
Kojto 109:9296ab0bfc11 1990 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
Kojto 109:9296ab0bfc11 1991 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
Kojto 109:9296ab0bfc11 1992 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
Kojto 109:9296ab0bfc11 1993 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
Kojto 109:9296ab0bfc11 1994 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
Kojto 109:9296ab0bfc11 1995 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
Kojto 109:9296ab0bfc11 1996 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
Kojto 109:9296ab0bfc11 1997 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
Kojto 109:9296ab0bfc11 1998
Kojto 109:9296ab0bfc11 1999 /******************* Bit definition for CAN_FS1R register *******************/
Kojto 109:9296ab0bfc11 2000 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
Kojto 109:9296ab0bfc11 2001 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
Kojto 109:9296ab0bfc11 2002 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
Kojto 109:9296ab0bfc11 2003 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
Kojto 109:9296ab0bfc11 2004 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
Kojto 109:9296ab0bfc11 2005 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
Kojto 109:9296ab0bfc11 2006 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
Kojto 109:9296ab0bfc11 2007 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
Kojto 109:9296ab0bfc11 2008 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
Kojto 109:9296ab0bfc11 2009 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
Kojto 109:9296ab0bfc11 2010 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
Kojto 109:9296ab0bfc11 2011 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
Kojto 109:9296ab0bfc11 2012 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
Kojto 109:9296ab0bfc11 2013 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
Kojto 109:9296ab0bfc11 2014 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
Kojto 109:9296ab0bfc11 2015
Kojto 109:9296ab0bfc11 2016 /****************** Bit definition for CAN_FFA1R register *******************/
Kojto 109:9296ab0bfc11 2017 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
Kojto 109:9296ab0bfc11 2018 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
Kojto 109:9296ab0bfc11 2019 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
Kojto 109:9296ab0bfc11 2020 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
Kojto 109:9296ab0bfc11 2021 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
Kojto 109:9296ab0bfc11 2022 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
Kojto 109:9296ab0bfc11 2023 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
Kojto 109:9296ab0bfc11 2024 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
Kojto 109:9296ab0bfc11 2025 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
Kojto 109:9296ab0bfc11 2026 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
Kojto 109:9296ab0bfc11 2027 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
Kojto 109:9296ab0bfc11 2028 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
Kojto 109:9296ab0bfc11 2029 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
Kojto 109:9296ab0bfc11 2030 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
Kojto 109:9296ab0bfc11 2031 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
Kojto 109:9296ab0bfc11 2032
Kojto 109:9296ab0bfc11 2033 /******************* Bit definition for CAN_FA1R register *******************/
Kojto 109:9296ab0bfc11 2034 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
Kojto 109:9296ab0bfc11 2035 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
Kojto 109:9296ab0bfc11 2036 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
Kojto 109:9296ab0bfc11 2037 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
Kojto 109:9296ab0bfc11 2038 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
Kojto 109:9296ab0bfc11 2039 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
Kojto 109:9296ab0bfc11 2040 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
Kojto 109:9296ab0bfc11 2041 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
Kojto 109:9296ab0bfc11 2042 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
Kojto 109:9296ab0bfc11 2043 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
Kojto 109:9296ab0bfc11 2044 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
Kojto 109:9296ab0bfc11 2045 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
Kojto 109:9296ab0bfc11 2046 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
Kojto 109:9296ab0bfc11 2047 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
Kojto 109:9296ab0bfc11 2048 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
Kojto 109:9296ab0bfc11 2049
Kojto 109:9296ab0bfc11 2050 /******************* Bit definition for CAN_F0R1 register *******************/
Kojto 109:9296ab0bfc11 2051 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2052 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2053 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2054 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2055 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2056 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2057 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2058 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2059 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2060 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2061 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2062 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2063 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2064 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2065 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2066 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2067 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2068 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2069 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2070 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2071 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2072 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2073 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2074 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2075 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2076 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2077 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2078 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2079 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2080 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2081 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2082 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2083
Kojto 109:9296ab0bfc11 2084 /******************* Bit definition for CAN_F1R1 register *******************/
Kojto 109:9296ab0bfc11 2085 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2086 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2087 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2088 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2089 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2090 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2091 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2092 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2093 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2094 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2095 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2096 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2097 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2098 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2099 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2100 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2101 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2102 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2103 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2104 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2105 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2106 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2107 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2108 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2109 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2110 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2111 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2112 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2113 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2114 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2115 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2116 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2117
Kojto 109:9296ab0bfc11 2118 /******************* Bit definition for CAN_F2R1 register *******************/
Kojto 109:9296ab0bfc11 2119 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2120 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2121 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2122 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2123 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2124 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2125 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2126 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2127 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2128 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2129 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2130 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2131 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2132 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2133 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2134 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2135 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2136 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2137 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2138 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2139 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2140 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2141 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2142 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2143 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2144 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2145 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2146 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2147 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2148 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2149 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2150 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2151
Kojto 109:9296ab0bfc11 2152 /******************* Bit definition for CAN_F3R1 register *******************/
Kojto 109:9296ab0bfc11 2153 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2154 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2155 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2156 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2157 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2158 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2159 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2160 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2161 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2162 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2163 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2164 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2165 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2166 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2167 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2168 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2169 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2170 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2171 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2172 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2173 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2174 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2175 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2176 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2177 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2178 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2179 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2180 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2181 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2182 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2183 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2184 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2185
Kojto 109:9296ab0bfc11 2186 /******************* Bit definition for CAN_F4R1 register *******************/
Kojto 109:9296ab0bfc11 2187 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2188 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2189 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2190 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2191 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2192 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2193 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2194 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2195 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2196 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2197 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2198 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2199 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2200 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2201 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2202 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2203 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2204 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2205 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2206 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2207 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2208 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2209 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2210 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2211 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2212 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2213 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2214 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2215 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2216 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2217 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2218 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2219
Kojto 109:9296ab0bfc11 2220 /******************* Bit definition for CAN_F5R1 register *******************/
Kojto 109:9296ab0bfc11 2221 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2222 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2223 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2224 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2225 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2226 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2227 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2228 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2229 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2230 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2231 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2232 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2233 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2234 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2235 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2236 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2237 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2238 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2239 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2240 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2241 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2242 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2243 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2244 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2245 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2246 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2247 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2248 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2249 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2250 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2251 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2252 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2253
Kojto 109:9296ab0bfc11 2254 /******************* Bit definition for CAN_F6R1 register *******************/
Kojto 109:9296ab0bfc11 2255 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2256 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2257 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2258 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2259 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2260 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2261 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2262 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2263 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2264 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2265 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2266 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2267 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2268 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2269 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2270 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2271 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2272 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2273 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2274 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2275 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2276 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2277 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2278 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2279 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2280 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2281 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2282 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2283 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2284 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2285 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2286 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2287
Kojto 109:9296ab0bfc11 2288 /******************* Bit definition for CAN_F7R1 register *******************/
Kojto 109:9296ab0bfc11 2289 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2290 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2291 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2292 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2293 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2294 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2295 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2296 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2297 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2298 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2299 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2300 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2301 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2302 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2303 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2304 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2305 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2306 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2307 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2308 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2309 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2310 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2311 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2312 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2313 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2314 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2315 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2316 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2317 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2318 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2319 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2320 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2321
Kojto 109:9296ab0bfc11 2322 /******************* Bit definition for CAN_F8R1 register *******************/
Kojto 109:9296ab0bfc11 2323 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2324 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2325 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2326 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2327 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2328 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2329 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2330 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2331 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2332 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2333 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2334 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2335 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2336 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2337 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2338 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2339 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2340 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2341 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2342 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2343 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2344 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2345 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2346 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2347 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2348 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2349 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2350 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2351 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2352 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2353 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2354 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2355
Kojto 109:9296ab0bfc11 2356 /******************* Bit definition for CAN_F9R1 register *******************/
Kojto 109:9296ab0bfc11 2357 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2358 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2359 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2360 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2361 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2362 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2363 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2364 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2365 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2366 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2367 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2368 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2369 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2370 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2371 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2372 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2373 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2374 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2375 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2376 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2377 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2378 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2379 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2380 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2381 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2382 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2383 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2384 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2385 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2386 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2387 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2388 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2389
Kojto 109:9296ab0bfc11 2390 /******************* Bit definition for CAN_F10R1 register ******************/
Kojto 109:9296ab0bfc11 2391 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2392 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2393 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2394 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2395 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2396 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2397 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2398 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2399 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2400 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2401 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2402 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2403 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2404 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2405 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2406 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2407 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2408 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2409 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2410 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2411 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2412 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2413 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2414 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2415 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2416 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2417 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2418 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2419 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2420 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2421 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2422 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2423
Kojto 109:9296ab0bfc11 2424 /******************* Bit definition for CAN_F11R1 register ******************/
Kojto 109:9296ab0bfc11 2425 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2426 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2427 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2428 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2429 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2430 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2431 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2432 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2433 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2434 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2435 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2436 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2437 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2438 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2439 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2440 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2441 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2442 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2443 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2444 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2445 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2446 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2447 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2448 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2449 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2450 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2451 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2452 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2453 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2454 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2455 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2456 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2457
Kojto 109:9296ab0bfc11 2458 /******************* Bit definition for CAN_F12R1 register ******************/
Kojto 109:9296ab0bfc11 2459 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2460 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2461 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2462 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2463 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2464 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2465 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2466 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2467 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2468 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2469 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2470 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2471 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2472 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2473 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2474 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2475 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2476 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2477 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2478 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2479 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2480 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2481 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2482 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2483 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2484 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2485 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2486 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2487 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2488 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2489 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2490 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2491
Kojto 109:9296ab0bfc11 2492 /******************* Bit definition for CAN_F13R1 register ******************/
Kojto 109:9296ab0bfc11 2493 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2494 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2495 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2496 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2497 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2498 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2499 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2500 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2501 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2502 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2503 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2504 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2505 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2506 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2507 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2508 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2509 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2510 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2511 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2512 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2513 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2514 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2515 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2516 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2517 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2518 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2519 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2520 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2521 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2522 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2523 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2524 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2525
Kojto 109:9296ab0bfc11 2526 /******************* Bit definition for CAN_F0R2 register *******************/
Kojto 109:9296ab0bfc11 2527 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2528 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2529 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2530 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2531 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2532 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2533 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2534 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2535 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2536 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2537 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2538 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2539 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2540 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2541 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2542 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2543 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2544 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2545 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2546 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2547 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2548 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2549 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2550 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2551 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2552 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2553 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2554 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2555 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2556 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2557 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2558 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2559
Kojto 109:9296ab0bfc11 2560 /******************* Bit definition for CAN_F1R2 register *******************/
Kojto 109:9296ab0bfc11 2561 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2562 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2563 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2564 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2565 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2566 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2567 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2568 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2569 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2570 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2571 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2572 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2573 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2574 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2575 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2576 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2577 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2578 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2579 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2580 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2581 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2582 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2583 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2584 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2585 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2586 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2587 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2588 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2589 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2590 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2591 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2592 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2593
Kojto 109:9296ab0bfc11 2594 /******************* Bit definition for CAN_F2R2 register *******************/
Kojto 109:9296ab0bfc11 2595 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2596 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2597 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2598 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2599 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2600 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2601 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2602 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2603 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2604 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2605 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2606 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2607 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2608 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2609 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2610 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2611 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2612 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2613 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2614 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2615 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2616 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2617 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2618 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2619 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2620 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2621 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2622 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2623 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2624 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2625 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2626 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2627
Kojto 109:9296ab0bfc11 2628 /******************* Bit definition for CAN_F3R2 register *******************/
Kojto 109:9296ab0bfc11 2629 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2630 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2631 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2632 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2633 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2634 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2635 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2636 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2637 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2638 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2639 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2640 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2641 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2642 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2643 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2644 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2645 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2646 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2647 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2648 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2649 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2650 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2651 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2652 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2653 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2654 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2655 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2656 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2657 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2658 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2659 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2660 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2661
Kojto 109:9296ab0bfc11 2662 /******************* Bit definition for CAN_F4R2 register *******************/
Kojto 109:9296ab0bfc11 2663 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2664 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2665 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2666 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2667 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2668 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2669 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2670 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2671 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2672 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2673 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2674 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2675 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2676 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2677 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2678 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2679 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2680 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2681 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2682 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2683 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2684 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2685 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2686 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2687 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2688 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2689 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2690 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2691 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2692 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2693 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2694 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2695
Kojto 109:9296ab0bfc11 2696 /******************* Bit definition for CAN_F5R2 register *******************/
Kojto 109:9296ab0bfc11 2697 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2698 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2699 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2700 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2701 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2702 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2703 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2704 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2705 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2706 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2707 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2708 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2709 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2710 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2711 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2712 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2713 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2714 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2715 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2716 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2717 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2718 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2719 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2720 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2721 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2722 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2723 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2724 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2725 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2726 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2727 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2728 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2729
Kojto 109:9296ab0bfc11 2730 /******************* Bit definition for CAN_F6R2 register *******************/
Kojto 109:9296ab0bfc11 2731 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2732 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2733 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2734 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2735 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2736 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2737 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2738 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2739 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2740 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2741 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2742 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2743 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2744 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2745 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2746 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2747 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2748 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2749 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2750 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2751 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2752 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2753 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2754 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2755 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2756 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2757 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2758 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2759 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2760 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2761 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2762 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2763
Kojto 109:9296ab0bfc11 2764 /******************* Bit definition for CAN_F7R2 register *******************/
Kojto 109:9296ab0bfc11 2765 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2766 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2767 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2768 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2769 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2770 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2771 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2772 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2773 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2774 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2775 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2776 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2777 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2778 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2779 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2780 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2781 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2782 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2783 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2784 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2785 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2786 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2787 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2788 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2789 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2790 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2791 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2792 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2793 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2794 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2795 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2796 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2797
Kojto 109:9296ab0bfc11 2798 /******************* Bit definition for CAN_F8R2 register *******************/
Kojto 109:9296ab0bfc11 2799 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2800 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2801 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2802 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2803 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2804 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2805 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2806 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2807 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2808 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2809 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2810 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2811 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2812 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2813 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2814 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2815 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2816 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2817 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2818 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2819 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2820 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2821 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2822 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2823 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2824 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2825 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2826 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2827 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2828 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2829 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2830 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2831
Kojto 109:9296ab0bfc11 2832 /******************* Bit definition for CAN_F9R2 register *******************/
Kojto 109:9296ab0bfc11 2833 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2834 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2835 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2836 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2837 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2838 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2839 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2840 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2841 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2842 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2843 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2844 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2845 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2846 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2847 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2848 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2849 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2850 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2851 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2852 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2853 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2854 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2855 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2856 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2857 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2858 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2859 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2860 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2861 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2862 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2863 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2864 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2865
Kojto 109:9296ab0bfc11 2866 /******************* Bit definition for CAN_F10R2 register ******************/
Kojto 109:9296ab0bfc11 2867 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2868 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2869 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2870 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2871 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2872 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2873 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2874 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2875 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2876 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2877 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2878 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2879 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2880 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2881 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2882 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2883 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2884 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2885 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2886 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2887 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2888 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2889 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2890 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2891 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2892 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2893 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2894 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2895 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2896 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2897 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2898 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2899
Kojto 109:9296ab0bfc11 2900 /******************* Bit definition for CAN_F11R2 register ******************/
Kojto 109:9296ab0bfc11 2901 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2902 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2903 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2904 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2905 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2906 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2907 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2908 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2909 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2910 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2911 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2912 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2913 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2914 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2915 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2916 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2917 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2918 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2919 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2920 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2921 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2922 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2923 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2924 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2925 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2926 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2927 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2928 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2929 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2930 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2931 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2932 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2933
Kojto 109:9296ab0bfc11 2934 /******************* Bit definition for CAN_F12R2 register ******************/
Kojto 109:9296ab0bfc11 2935 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2936 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2937 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2938 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2939 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2940 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2941 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2942 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2943 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2944 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2945 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2946 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2947 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2948 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2949 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2950 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2951 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2952 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2953 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2954 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2955 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2956 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2957 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2958 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2959 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2960 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2961 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2962 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2963 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2964 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2965 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 2966 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 2967
Kojto 109:9296ab0bfc11 2968 /******************* Bit definition for CAN_F13R2 register ******************/
Kojto 109:9296ab0bfc11 2969 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 109:9296ab0bfc11 2970 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 109:9296ab0bfc11 2971 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 109:9296ab0bfc11 2972 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 109:9296ab0bfc11 2973 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 109:9296ab0bfc11 2974 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 109:9296ab0bfc11 2975 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 109:9296ab0bfc11 2976 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 109:9296ab0bfc11 2977 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 109:9296ab0bfc11 2978 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 109:9296ab0bfc11 2979 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 109:9296ab0bfc11 2980 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 109:9296ab0bfc11 2981 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 109:9296ab0bfc11 2982 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 109:9296ab0bfc11 2983 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 109:9296ab0bfc11 2984 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 109:9296ab0bfc11 2985 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 109:9296ab0bfc11 2986 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 109:9296ab0bfc11 2987 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 109:9296ab0bfc11 2988 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 109:9296ab0bfc11 2989 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 109:9296ab0bfc11 2990 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 109:9296ab0bfc11 2991 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 109:9296ab0bfc11 2992 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 109:9296ab0bfc11 2993 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 109:9296ab0bfc11 2994 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 109:9296ab0bfc11 2995 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 109:9296ab0bfc11 2996 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 109:9296ab0bfc11 2997 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 109:9296ab0bfc11 2998 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 109:9296ab0bfc11 2999 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 109:9296ab0bfc11 3000 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 109:9296ab0bfc11 3001
Kojto 109:9296ab0bfc11 3002 /******************************************************************************/
Kojto 109:9296ab0bfc11 3003 /* */
Kojto 109:9296ab0bfc11 3004 /* CRC calculation unit (CRC) */
Kojto 109:9296ab0bfc11 3005 /* */
Kojto 109:9296ab0bfc11 3006 /******************************************************************************/
Kojto 109:9296ab0bfc11 3007 /******************* Bit definition for CRC_DR register *********************/
Kojto 109:9296ab0bfc11 3008 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
Kojto 109:9296ab0bfc11 3009
Kojto 109:9296ab0bfc11 3010 /******************* Bit definition for CRC_IDR register ********************/
Kojto 109:9296ab0bfc11 3011 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
Kojto 109:9296ab0bfc11 3012
Kojto 109:9296ab0bfc11 3013 /******************** Bit definition for CRC_CR register ********************/
Kojto 109:9296ab0bfc11 3014 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
Kojto 109:9296ab0bfc11 3015 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
Kojto 109:9296ab0bfc11 3016 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
Kojto 109:9296ab0bfc11 3017 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
Kojto 109:9296ab0bfc11 3018 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
Kojto 109:9296ab0bfc11 3019 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3020 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3021 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
Kojto 109:9296ab0bfc11 3022
Kojto 109:9296ab0bfc11 3023 /******************* Bit definition for CRC_INIT register *******************/
Kojto 109:9296ab0bfc11 3024 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
Kojto 109:9296ab0bfc11 3025
Kojto 109:9296ab0bfc11 3026 /******************* Bit definition for CRC_POL register ********************/
Kojto 109:9296ab0bfc11 3027 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
Kojto 109:9296ab0bfc11 3028
Kojto 109:9296ab0bfc11 3029 /******************************************************************************/
Kojto 109:9296ab0bfc11 3030 /* */
Kojto 109:9296ab0bfc11 3031 /* Digital to Analog Converter (DAC) */
Kojto 109:9296ab0bfc11 3032 /* */
Kojto 109:9296ab0bfc11 3033 /******************************************************************************/
Kojto 109:9296ab0bfc11 3034 /******************** Bit definition for DAC_CR register ********************/
Kojto 109:9296ab0bfc11 3035 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
Kojto 109:9296ab0bfc11 3036 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
Kojto 109:9296ab0bfc11 3037 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
Kojto 109:9296ab0bfc11 3038
Kojto 109:9296ab0bfc11 3039 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
Kojto 109:9296ab0bfc11 3040 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3041 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3042 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3043
Kojto 109:9296ab0bfc11 3044 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
Kojto 109:9296ab0bfc11 3045 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3046 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3047
Kojto 109:9296ab0bfc11 3048 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Kojto 109:9296ab0bfc11 3049 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3050 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3051 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3052 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 3053
Kojto 109:9296ab0bfc11 3054 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
Kojto 109:9296ab0bfc11 3055 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
Kojto 109:9296ab0bfc11 3056 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
Kojto 109:9296ab0bfc11 3057 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
Kojto 109:9296ab0bfc11 3058 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
Kojto 109:9296ab0bfc11 3059
Kojto 109:9296ab0bfc11 3060 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
Kojto 109:9296ab0bfc11 3061 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3062 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3063 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3064
Kojto 109:9296ab0bfc11 3065 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
Kojto 109:9296ab0bfc11 3066 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3067 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3068
Kojto 109:9296ab0bfc11 3069 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
Kojto 109:9296ab0bfc11 3070 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3071 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3072 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3073 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 3074
Kojto 109:9296ab0bfc11 3075 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
Kojto 109:9296ab0bfc11 3076 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */
Kojto 109:9296ab0bfc11 3077
Kojto 109:9296ab0bfc11 3078 /***************** Bit definition for DAC_SWTRIGR register ******************/
Kojto 109:9296ab0bfc11 3079 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
Kojto 109:9296ab0bfc11 3080 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
Kojto 109:9296ab0bfc11 3081
Kojto 109:9296ab0bfc11 3082 /***************** Bit definition for DAC_DHR12R1 register ******************/
Kojto 109:9296ab0bfc11 3083 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
Kojto 109:9296ab0bfc11 3084
Kojto 109:9296ab0bfc11 3085 /***************** Bit definition for DAC_DHR12L1 register ******************/
Kojto 109:9296ab0bfc11 3086 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
Kojto 109:9296ab0bfc11 3087
Kojto 109:9296ab0bfc11 3088 /****************** Bit definition for DAC_DHR8R1 register ******************/
Kojto 109:9296ab0bfc11 3089 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
Kojto 109:9296ab0bfc11 3090
Kojto 109:9296ab0bfc11 3091 /***************** Bit definition for DAC_DHR12R2 register ******************/
Kojto 109:9296ab0bfc11 3092 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
Kojto 109:9296ab0bfc11 3093
Kojto 109:9296ab0bfc11 3094 /***************** Bit definition for DAC_DHR12L2 register ******************/
Kojto 109:9296ab0bfc11 3095 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
Kojto 109:9296ab0bfc11 3096
Kojto 109:9296ab0bfc11 3097 /****************** Bit definition for DAC_DHR8R2 register ******************/
Kojto 109:9296ab0bfc11 3098 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
Kojto 109:9296ab0bfc11 3099
Kojto 109:9296ab0bfc11 3100 /***************** Bit definition for DAC_DHR12RD register ******************/
Kojto 109:9296ab0bfc11 3101 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
Kojto 109:9296ab0bfc11 3102 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
Kojto 109:9296ab0bfc11 3103
Kojto 109:9296ab0bfc11 3104 /***************** Bit definition for DAC_DHR12LD register ******************/
Kojto 109:9296ab0bfc11 3105 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
Kojto 109:9296ab0bfc11 3106 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
Kojto 109:9296ab0bfc11 3107
Kojto 109:9296ab0bfc11 3108 /****************** Bit definition for DAC_DHR8RD register ******************/
Kojto 109:9296ab0bfc11 3109 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
Kojto 109:9296ab0bfc11 3110 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
Kojto 109:9296ab0bfc11 3111
Kojto 109:9296ab0bfc11 3112 /******************* Bit definition for DAC_DOR1 register *******************/
Kojto 109:9296ab0bfc11 3113 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
Kojto 109:9296ab0bfc11 3114
Kojto 109:9296ab0bfc11 3115 /******************* Bit definition for DAC_DOR2 register *******************/
Kojto 109:9296ab0bfc11 3116 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
Kojto 109:9296ab0bfc11 3117
Kojto 109:9296ab0bfc11 3118 /******************** Bit definition for DAC_SR register ********************/
Kojto 109:9296ab0bfc11 3119 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
Kojto 109:9296ab0bfc11 3120 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
Kojto 109:9296ab0bfc11 3121
Kojto 109:9296ab0bfc11 3122 /******************************************************************************/
Kojto 109:9296ab0bfc11 3123 /* */
Kojto 109:9296ab0bfc11 3124 /* Debug MCU (DBGMCU) */
Kojto 109:9296ab0bfc11 3125 /* */
Kojto 109:9296ab0bfc11 3126 /******************************************************************************/
Kojto 109:9296ab0bfc11 3127 /******************** Bit definition for DBGMCU_IDCODE register *************/
Kojto 109:9296ab0bfc11 3128 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
Kojto 109:9296ab0bfc11 3129 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
Kojto 109:9296ab0bfc11 3130
Kojto 109:9296ab0bfc11 3131 /******************** Bit definition for DBGMCU_CR register *****************/
Kojto 109:9296ab0bfc11 3132 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3133 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3134 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3135 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3136
Kojto 109:9296ab0bfc11 3137 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
Kojto 109:9296ab0bfc11 3138 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
Kojto 109:9296ab0bfc11 3139 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
Kojto 109:9296ab0bfc11 3140
Kojto 109:9296ab0bfc11 3141 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
Kojto 109:9296ab0bfc11 3142 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3143 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3144 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3145 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3146 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3147 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3148 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3149 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 3150 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 3151
Kojto 109:9296ab0bfc11 3152 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
Kojto 109:9296ab0bfc11 3153 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3154 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3155 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3156 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3157
Kojto 109:9296ab0bfc11 3158 /******************************************************************************/
Kojto 109:9296ab0bfc11 3159 /* */
Kojto 109:9296ab0bfc11 3160 /* DMA Controller (DMA) */
Kojto 109:9296ab0bfc11 3161 /* */
Kojto 109:9296ab0bfc11 3162 /******************************************************************************/
Kojto 109:9296ab0bfc11 3163 /******************* Bit definition for DMA_ISR register ********************/
Kojto 109:9296ab0bfc11 3164 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
Kojto 109:9296ab0bfc11 3165 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
Kojto 109:9296ab0bfc11 3166 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
Kojto 109:9296ab0bfc11 3167 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
Kojto 109:9296ab0bfc11 3168 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
Kojto 109:9296ab0bfc11 3169 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
Kojto 109:9296ab0bfc11 3170 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
Kojto 109:9296ab0bfc11 3171 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
Kojto 109:9296ab0bfc11 3172 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
Kojto 109:9296ab0bfc11 3173 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
Kojto 109:9296ab0bfc11 3174 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
Kojto 109:9296ab0bfc11 3175 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
Kojto 109:9296ab0bfc11 3176 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
Kojto 109:9296ab0bfc11 3177 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
Kojto 109:9296ab0bfc11 3178 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
Kojto 109:9296ab0bfc11 3179 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
Kojto 109:9296ab0bfc11 3180 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
Kojto 109:9296ab0bfc11 3181 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
Kojto 109:9296ab0bfc11 3182 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
Kojto 109:9296ab0bfc11 3183 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
Kojto 109:9296ab0bfc11 3184 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
Kojto 109:9296ab0bfc11 3185 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
Kojto 109:9296ab0bfc11 3186 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
Kojto 109:9296ab0bfc11 3187 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
Kojto 109:9296ab0bfc11 3188 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
Kojto 109:9296ab0bfc11 3189 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
Kojto 109:9296ab0bfc11 3190 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
Kojto 109:9296ab0bfc11 3191 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
Kojto 109:9296ab0bfc11 3192
Kojto 109:9296ab0bfc11 3193 /******************* Bit definition for DMA_IFCR register *******************/
Kojto 109:9296ab0bfc11 3194 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
Kojto 109:9296ab0bfc11 3195 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
Kojto 109:9296ab0bfc11 3196 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
Kojto 109:9296ab0bfc11 3197 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
Kojto 109:9296ab0bfc11 3198 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
Kojto 109:9296ab0bfc11 3199 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
Kojto 109:9296ab0bfc11 3200 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
Kojto 109:9296ab0bfc11 3201 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
Kojto 109:9296ab0bfc11 3202 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
Kojto 109:9296ab0bfc11 3203 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
Kojto 109:9296ab0bfc11 3204 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
Kojto 109:9296ab0bfc11 3205 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
Kojto 109:9296ab0bfc11 3206 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
Kojto 109:9296ab0bfc11 3207 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
Kojto 109:9296ab0bfc11 3208 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
Kojto 109:9296ab0bfc11 3209 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
Kojto 109:9296ab0bfc11 3210 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
Kojto 109:9296ab0bfc11 3211 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
Kojto 109:9296ab0bfc11 3212 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
Kojto 109:9296ab0bfc11 3213 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
Kojto 109:9296ab0bfc11 3214 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
Kojto 109:9296ab0bfc11 3215 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
Kojto 109:9296ab0bfc11 3216 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
Kojto 109:9296ab0bfc11 3217 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
Kojto 109:9296ab0bfc11 3218 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
Kojto 109:9296ab0bfc11 3219 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
Kojto 109:9296ab0bfc11 3220 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
Kojto 109:9296ab0bfc11 3221 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
Kojto 109:9296ab0bfc11 3222
Kojto 109:9296ab0bfc11 3223 /******************* Bit definition for DMA_CCR register ********************/
Kojto 109:9296ab0bfc11 3224 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
Kojto 109:9296ab0bfc11 3225 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
Kojto 109:9296ab0bfc11 3226 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
Kojto 109:9296ab0bfc11 3227 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
Kojto 109:9296ab0bfc11 3228 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
Kojto 109:9296ab0bfc11 3229 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
Kojto 109:9296ab0bfc11 3230 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
Kojto 109:9296ab0bfc11 3231 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
Kojto 109:9296ab0bfc11 3232
Kojto 109:9296ab0bfc11 3233 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
Kojto 109:9296ab0bfc11 3234 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3235 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3236
Kojto 109:9296ab0bfc11 3237 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
Kojto 109:9296ab0bfc11 3238 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3239 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3240
Kojto 109:9296ab0bfc11 3241 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
Kojto 109:9296ab0bfc11 3242 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3243 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3244
Kojto 109:9296ab0bfc11 3245 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
Kojto 109:9296ab0bfc11 3246
Kojto 109:9296ab0bfc11 3247 /****************** Bit definition for DMA_CNDTR register *******************/
Kojto 109:9296ab0bfc11 3248 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
Kojto 109:9296ab0bfc11 3249
Kojto 109:9296ab0bfc11 3250 /****************** Bit definition for DMA_CPAR register ********************/
Kojto 109:9296ab0bfc11 3251 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
Kojto 109:9296ab0bfc11 3252
Kojto 109:9296ab0bfc11 3253 /****************** Bit definition for DMA_CMAR register ********************/
Kojto 109:9296ab0bfc11 3254 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 109:9296ab0bfc11 3255
Kojto 109:9296ab0bfc11 3256 /******************************************************************************/
Kojto 109:9296ab0bfc11 3257 /* */
Kojto 109:9296ab0bfc11 3258 /* External Interrupt/Event Controller (EXTI) */
Kojto 109:9296ab0bfc11 3259 /* */
Kojto 109:9296ab0bfc11 3260 /******************************************************************************/
Kojto 109:9296ab0bfc11 3261 /******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
Kojto 109:9296ab0bfc11 3262 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
Kojto 109:9296ab0bfc11 3263 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
Kojto 109:9296ab0bfc11 3264 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
Kojto 109:9296ab0bfc11 3265 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
Kojto 109:9296ab0bfc11 3266 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
Kojto 109:9296ab0bfc11 3267 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
Kojto 109:9296ab0bfc11 3268 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
Kojto 109:9296ab0bfc11 3269 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
Kojto 109:9296ab0bfc11 3270 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
Kojto 109:9296ab0bfc11 3271 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
Kojto 109:9296ab0bfc11 3272 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
Kojto 109:9296ab0bfc11 3273 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
Kojto 109:9296ab0bfc11 3274 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
Kojto 109:9296ab0bfc11 3275 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
Kojto 109:9296ab0bfc11 3276 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
Kojto 109:9296ab0bfc11 3277 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
Kojto 109:9296ab0bfc11 3278 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
Kojto 109:9296ab0bfc11 3279 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
Kojto 109:9296ab0bfc11 3280 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
Kojto 109:9296ab0bfc11 3281 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
Kojto 109:9296ab0bfc11 3282 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
Kojto 109:9296ab0bfc11 3283 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
Kojto 109:9296ab0bfc11 3284 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
Kojto 109:9296ab0bfc11 3285 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
Kojto 109:9296ab0bfc11 3286 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
Kojto 109:9296ab0bfc11 3287 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
Kojto 109:9296ab0bfc11 3288 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
Kojto 109:9296ab0bfc11 3289 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
Kojto 109:9296ab0bfc11 3290 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
Kojto 109:9296ab0bfc11 3291
Kojto 109:9296ab0bfc11 3292 /******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
Kojto 109:9296ab0bfc11 3293 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
Kojto 109:9296ab0bfc11 3294 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
Kojto 109:9296ab0bfc11 3295 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
Kojto 109:9296ab0bfc11 3296 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
Kojto 109:9296ab0bfc11 3297 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
Kojto 109:9296ab0bfc11 3298 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
Kojto 109:9296ab0bfc11 3299 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
Kojto 109:9296ab0bfc11 3300 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
Kojto 109:9296ab0bfc11 3301 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
Kojto 109:9296ab0bfc11 3302 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
Kojto 109:9296ab0bfc11 3303 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
Kojto 109:9296ab0bfc11 3304 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
Kojto 109:9296ab0bfc11 3305 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
Kojto 109:9296ab0bfc11 3306 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
Kojto 109:9296ab0bfc11 3307 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
Kojto 109:9296ab0bfc11 3308 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
Kojto 109:9296ab0bfc11 3309 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
Kojto 109:9296ab0bfc11 3310 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
Kojto 109:9296ab0bfc11 3311 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
Kojto 109:9296ab0bfc11 3312 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
Kojto 109:9296ab0bfc11 3313 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
Kojto 109:9296ab0bfc11 3314 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
Kojto 109:9296ab0bfc11 3315 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
Kojto 109:9296ab0bfc11 3316 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
Kojto 109:9296ab0bfc11 3317 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
Kojto 109:9296ab0bfc11 3318 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
Kojto 109:9296ab0bfc11 3319 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
Kojto 109:9296ab0bfc11 3320 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
Kojto 109:9296ab0bfc11 3321 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
Kojto 109:9296ab0bfc11 3322
Kojto 109:9296ab0bfc11 3323 /****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
Kojto 109:9296ab0bfc11 3324 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
Kojto 109:9296ab0bfc11 3325 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
Kojto 109:9296ab0bfc11 3326 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
Kojto 109:9296ab0bfc11 3327 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
Kojto 109:9296ab0bfc11 3328 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
Kojto 109:9296ab0bfc11 3329 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
Kojto 109:9296ab0bfc11 3330 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
Kojto 109:9296ab0bfc11 3331 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
Kojto 109:9296ab0bfc11 3332 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
Kojto 109:9296ab0bfc11 3333 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
Kojto 109:9296ab0bfc11 3334 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
Kojto 109:9296ab0bfc11 3335 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
Kojto 109:9296ab0bfc11 3336 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
Kojto 109:9296ab0bfc11 3337 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
Kojto 109:9296ab0bfc11 3338 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
Kojto 109:9296ab0bfc11 3339 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
Kojto 109:9296ab0bfc11 3340 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
Kojto 109:9296ab0bfc11 3341 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
Kojto 109:9296ab0bfc11 3342 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
Kojto 109:9296ab0bfc11 3343 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
Kojto 109:9296ab0bfc11 3344 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
Kojto 109:9296ab0bfc11 3345 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
Kojto 109:9296ab0bfc11 3346 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
Kojto 109:9296ab0bfc11 3347 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
Kojto 109:9296ab0bfc11 3348 #define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
Kojto 109:9296ab0bfc11 3349 #define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
Kojto 109:9296ab0bfc11 3350 #define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
Kojto 109:9296ab0bfc11 3351 #define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
Kojto 109:9296ab0bfc11 3352 #define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
Kojto 109:9296ab0bfc11 3353
Kojto 109:9296ab0bfc11 3354 /****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
Kojto 109:9296ab0bfc11 3355 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
Kojto 109:9296ab0bfc11 3356 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
Kojto 109:9296ab0bfc11 3357 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
Kojto 109:9296ab0bfc11 3358 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
Kojto 109:9296ab0bfc11 3359 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
Kojto 109:9296ab0bfc11 3360 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
Kojto 109:9296ab0bfc11 3361 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
Kojto 109:9296ab0bfc11 3362 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
Kojto 109:9296ab0bfc11 3363 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
Kojto 109:9296ab0bfc11 3364 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
Kojto 109:9296ab0bfc11 3365 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
Kojto 109:9296ab0bfc11 3366 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
Kojto 109:9296ab0bfc11 3367 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
Kojto 109:9296ab0bfc11 3368 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
Kojto 109:9296ab0bfc11 3369 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
Kojto 109:9296ab0bfc11 3370 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
Kojto 109:9296ab0bfc11 3371 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
Kojto 109:9296ab0bfc11 3372 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
Kojto 109:9296ab0bfc11 3373 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
Kojto 109:9296ab0bfc11 3374 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
Kojto 109:9296ab0bfc11 3375 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
Kojto 109:9296ab0bfc11 3376 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
Kojto 109:9296ab0bfc11 3377 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
Kojto 109:9296ab0bfc11 3378 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
Kojto 109:9296ab0bfc11 3379 #define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
Kojto 109:9296ab0bfc11 3380 #define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
Kojto 109:9296ab0bfc11 3381 #define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
Kojto 109:9296ab0bfc11 3382 #define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
Kojto 109:9296ab0bfc11 3383 #define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
Kojto 109:9296ab0bfc11 3384
Kojto 109:9296ab0bfc11 3385 /****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
Kojto 109:9296ab0bfc11 3386 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
Kojto 109:9296ab0bfc11 3387 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
Kojto 109:9296ab0bfc11 3388 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
Kojto 109:9296ab0bfc11 3389 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
Kojto 109:9296ab0bfc11 3390 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
Kojto 109:9296ab0bfc11 3391 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
Kojto 109:9296ab0bfc11 3392 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
Kojto 109:9296ab0bfc11 3393 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
Kojto 109:9296ab0bfc11 3394 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
Kojto 109:9296ab0bfc11 3395 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
Kojto 109:9296ab0bfc11 3396 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
Kojto 109:9296ab0bfc11 3397 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
Kojto 109:9296ab0bfc11 3398 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
Kojto 109:9296ab0bfc11 3399 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
Kojto 109:9296ab0bfc11 3400 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
Kojto 109:9296ab0bfc11 3401 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
Kojto 109:9296ab0bfc11 3402 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
Kojto 109:9296ab0bfc11 3403 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
Kojto 109:9296ab0bfc11 3404 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
Kojto 109:9296ab0bfc11 3405 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
Kojto 109:9296ab0bfc11 3406 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
Kojto 109:9296ab0bfc11 3407 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
Kojto 109:9296ab0bfc11 3408 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
Kojto 109:9296ab0bfc11 3409 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
Kojto 109:9296ab0bfc11 3410 #define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
Kojto 109:9296ab0bfc11 3411 #define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
Kojto 109:9296ab0bfc11 3412 #define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
Kojto 109:9296ab0bfc11 3413 #define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
Kojto 109:9296ab0bfc11 3414 #define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
Kojto 109:9296ab0bfc11 3415
Kojto 109:9296ab0bfc11 3416 /******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
Kojto 109:9296ab0bfc11 3417 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
Kojto 109:9296ab0bfc11 3418 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
Kojto 109:9296ab0bfc11 3419 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
Kojto 109:9296ab0bfc11 3420 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
Kojto 109:9296ab0bfc11 3421 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
Kojto 109:9296ab0bfc11 3422 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
Kojto 109:9296ab0bfc11 3423 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
Kojto 109:9296ab0bfc11 3424 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
Kojto 109:9296ab0bfc11 3425 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
Kojto 109:9296ab0bfc11 3426 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
Kojto 109:9296ab0bfc11 3427 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
Kojto 109:9296ab0bfc11 3428 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
Kojto 109:9296ab0bfc11 3429 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
Kojto 109:9296ab0bfc11 3430 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
Kojto 109:9296ab0bfc11 3431 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
Kojto 109:9296ab0bfc11 3432 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
Kojto 109:9296ab0bfc11 3433 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
Kojto 109:9296ab0bfc11 3434 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
Kojto 109:9296ab0bfc11 3435 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
Kojto 109:9296ab0bfc11 3436 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
Kojto 109:9296ab0bfc11 3437 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
Kojto 109:9296ab0bfc11 3438 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
Kojto 109:9296ab0bfc11 3439 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
Kojto 109:9296ab0bfc11 3440 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
Kojto 109:9296ab0bfc11 3441 #define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
Kojto 109:9296ab0bfc11 3442 #define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
Kojto 109:9296ab0bfc11 3443 #define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
Kojto 109:9296ab0bfc11 3444 #define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
Kojto 109:9296ab0bfc11 3445 #define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
Kojto 109:9296ab0bfc11 3446
Kojto 109:9296ab0bfc11 3447 /******************************************************************************/
Kojto 109:9296ab0bfc11 3448 /* */
Kojto 109:9296ab0bfc11 3449 /* FLASH */
Kojto 109:9296ab0bfc11 3450 /* */
Kojto 109:9296ab0bfc11 3451 /******************************************************************************/
Kojto 109:9296ab0bfc11 3452 /******************* Bit definition for FLASH_ACR register ******************/
Kojto 109:9296ab0bfc11 3453 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
Kojto 109:9296ab0bfc11 3454 #define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3455 #define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3456 #define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3457
Kojto 109:9296ab0bfc11 3458 #define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
Kojto 109:9296ab0bfc11 3459 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
Kojto 109:9296ab0bfc11 3460 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
Kojto 109:9296ab0bfc11 3461
Kojto 109:9296ab0bfc11 3462 /****************** Bit definition for FLASH_KEYR register ******************/
Kojto 109:9296ab0bfc11 3463 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
Kojto 109:9296ab0bfc11 3464
Kojto 109:9296ab0bfc11 3465 #define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
Kojto 109:9296ab0bfc11 3466 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
Kojto 109:9296ab0bfc11 3467 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
Kojto 109:9296ab0bfc11 3468
Kojto 109:9296ab0bfc11 3469 /***************** Bit definition for FLASH_OPTKEYR register ****************/
Kojto 109:9296ab0bfc11 3470 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
Kojto 109:9296ab0bfc11 3471
Kojto 109:9296ab0bfc11 3472 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
Kojto 109:9296ab0bfc11 3473 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
Kojto 109:9296ab0bfc11 3474
Kojto 109:9296ab0bfc11 3475 /****************** Bit definition for FLASH_SR register *******************/
Kojto 109:9296ab0bfc11 3476 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
Kojto 109:9296ab0bfc11 3477 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
Kojto 109:9296ab0bfc11 3478 #define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
Kojto 109:9296ab0bfc11 3479 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
Kojto 109:9296ab0bfc11 3480
Kojto 109:9296ab0bfc11 3481 /******************* Bit definition for FLASH_CR register *******************/
Kojto 109:9296ab0bfc11 3482 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
Kojto 109:9296ab0bfc11 3483 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
Kojto 109:9296ab0bfc11 3484 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
Kojto 109:9296ab0bfc11 3485 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
Kojto 109:9296ab0bfc11 3486 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
Kojto 109:9296ab0bfc11 3487 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
Kojto 109:9296ab0bfc11 3488 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
Kojto 109:9296ab0bfc11 3489 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
Kojto 109:9296ab0bfc11 3490 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
Kojto 109:9296ab0bfc11 3491 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
Kojto 109:9296ab0bfc11 3492 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
Kojto 109:9296ab0bfc11 3493
Kojto 109:9296ab0bfc11 3494 /******************* Bit definition for FLASH_AR register *******************/
Kojto 109:9296ab0bfc11 3495 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
Kojto 109:9296ab0bfc11 3496
Kojto 109:9296ab0bfc11 3497 /****************** Bit definition for FLASH_OBR register *******************/
Kojto 109:9296ab0bfc11 3498 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
Kojto 109:9296ab0bfc11 3499 #define FLASH_OBR_RDPRT ((uint32_t)0x00000006) /*!< Read protection */
Kojto 109:9296ab0bfc11 3500 #define FLASH_OBR_RDPRT_1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
Kojto 109:9296ab0bfc11 3501 #define FLASH_OBR_RDPRT_2 ((uint32_t)0x00000006) /*!< Read protection Level 2 */
Kojto 109:9296ab0bfc11 3502
Kojto 109:9296ab0bfc11 3503 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
Kojto 109:9296ab0bfc11 3504 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
Kojto 109:9296ab0bfc11 3505 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
Kojto 109:9296ab0bfc11 3506 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
Kojto 109:9296ab0bfc11 3507 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
Kojto 109:9296ab0bfc11 3508 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
Kojto 109:9296ab0bfc11 3509 #define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
Kojto 109:9296ab0bfc11 3510
Kojto 109:9296ab0bfc11 3511 /****************** Bit definition for FLASH_WRPR register ******************/
Kojto 109:9296ab0bfc11 3512 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
Kojto 109:9296ab0bfc11 3513
Kojto 109:9296ab0bfc11 3514 /*----------------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 3515
Kojto 109:9296ab0bfc11 3516 /****************** Bit definition for OB_RDP register **********************/
Kojto 109:9296ab0bfc11 3517 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
Kojto 109:9296ab0bfc11 3518 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
Kojto 109:9296ab0bfc11 3519
Kojto 109:9296ab0bfc11 3520 /****************** Bit definition for OB_USER register *********************/
Kojto 109:9296ab0bfc11 3521 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
Kojto 109:9296ab0bfc11 3522 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
Kojto 109:9296ab0bfc11 3523
Kojto 109:9296ab0bfc11 3524 /****************** Bit definition for FLASH_WRP0 register ******************/
Kojto 109:9296ab0bfc11 3525 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
Kojto 109:9296ab0bfc11 3526 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
Kojto 109:9296ab0bfc11 3527
Kojto 109:9296ab0bfc11 3528 /****************** Bit definition for FLASH_WRP1 register ******************/
Kojto 109:9296ab0bfc11 3529 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
Kojto 109:9296ab0bfc11 3530 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
Kojto 109:9296ab0bfc11 3531
Kojto 109:9296ab0bfc11 3532 /****************** Bit definition for FLASH_WRP2 register ******************/
Kojto 109:9296ab0bfc11 3533 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
Kojto 109:9296ab0bfc11 3534 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
Kojto 109:9296ab0bfc11 3535
Kojto 109:9296ab0bfc11 3536 /****************** Bit definition for FLASH_WRP3 register ******************/
Kojto 109:9296ab0bfc11 3537 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
Kojto 109:9296ab0bfc11 3538 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
Kojto 109:9296ab0bfc11 3539 /******************************************************************************/
Kojto 109:9296ab0bfc11 3540 /* */
Kojto 109:9296ab0bfc11 3541 /* General Purpose I/O (GPIO) */
Kojto 109:9296ab0bfc11 3542 /* */
Kojto 109:9296ab0bfc11 3543 /******************************************************************************/
Kojto 109:9296ab0bfc11 3544 /******************* Bit definition for GPIO_MODER register *****************/
Kojto 109:9296ab0bfc11 3545 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Kojto 109:9296ab0bfc11 3546 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3547 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3548 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Kojto 109:9296ab0bfc11 3549 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3550 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3551 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 3552 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3553 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3554 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Kojto 109:9296ab0bfc11 3555 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3556 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3557 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Kojto 109:9296ab0bfc11 3558 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3559 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3560 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Kojto 109:9296ab0bfc11 3561 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3562 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3563 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Kojto 109:9296ab0bfc11 3564 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3565 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3566 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Kojto 109:9296ab0bfc11 3567 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3568 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3569 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Kojto 109:9296ab0bfc11 3570 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 3571 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 3572 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Kojto 109:9296ab0bfc11 3573 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 3574 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 3575 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 3576 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 3577 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 3578 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Kojto 109:9296ab0bfc11 3579 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 3580 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 3581 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Kojto 109:9296ab0bfc11 3582 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 3583 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 3584 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Kojto 109:9296ab0bfc11 3585 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 3586 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 3587 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 3588 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 3589 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 3590 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Kojto 109:9296ab0bfc11 3591 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 3592 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 3593
Kojto 109:9296ab0bfc11 3594 /****************** Bit definition for GPIO_OTYPER register *****************/
Kojto 109:9296ab0bfc11 3595 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3596 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3597 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3598 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3599 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3600 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3601 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3602 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3603 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3604 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3605 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3606 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3607 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3608 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3609 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3610 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3611
Kojto 109:9296ab0bfc11 3612 /**************** Bit definition for GPIO_OSPEEDR register ******************/
Kojto 109:9296ab0bfc11 3613 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
Kojto 109:9296ab0bfc11 3614 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3615 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3616 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
Kojto 109:9296ab0bfc11 3617 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3618 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3619 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 3620 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3621 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3622 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
Kojto 109:9296ab0bfc11 3623 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3624 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3625 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
Kojto 109:9296ab0bfc11 3626 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3627 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3628 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
Kojto 109:9296ab0bfc11 3629 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3630 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3631 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
Kojto 109:9296ab0bfc11 3632 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3633 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3634 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
Kojto 109:9296ab0bfc11 3635 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3636 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3637 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
Kojto 109:9296ab0bfc11 3638 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 3639 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 3640 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
Kojto 109:9296ab0bfc11 3641 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 3642 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 3643 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 3644 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 3645 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 3646 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
Kojto 109:9296ab0bfc11 3647 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 3648 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 3649 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
Kojto 109:9296ab0bfc11 3650 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 3651 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 3652 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
Kojto 109:9296ab0bfc11 3653 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 3654 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 3655 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 3656 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 3657 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 3658 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
Kojto 109:9296ab0bfc11 3659 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 3660 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 3661
Kojto 109:9296ab0bfc11 3662 /******************* Bit definition for GPIO_PUPDR register ******************/
Kojto 109:9296ab0bfc11 3663 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Kojto 109:9296ab0bfc11 3664 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3665 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3666 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Kojto 109:9296ab0bfc11 3667 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3668 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3669 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 3670 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3671 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3672 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Kojto 109:9296ab0bfc11 3673 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3674 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3675 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Kojto 109:9296ab0bfc11 3676 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3677 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3678 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Kojto 109:9296ab0bfc11 3679 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3680 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3681 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Kojto 109:9296ab0bfc11 3682 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3683 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3684 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Kojto 109:9296ab0bfc11 3685 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3686 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3687 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Kojto 109:9296ab0bfc11 3688 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 3689 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 3690 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Kojto 109:9296ab0bfc11 3691 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 3692 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 3693 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 3694 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 3695 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 3696 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Kojto 109:9296ab0bfc11 3697 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 3698 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 3699 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Kojto 109:9296ab0bfc11 3700 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 3701 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 3702 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Kojto 109:9296ab0bfc11 3703 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 3704 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 3705 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 3706 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 3707 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 3708 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Kojto 109:9296ab0bfc11 3709 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 3710 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 3711
Kojto 109:9296ab0bfc11 3712 /******************* Bit definition for GPIO_IDR register *******************/
Kojto 109:9296ab0bfc11 3713 #define GPIO_IDR_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3714 #define GPIO_IDR_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3715 #define GPIO_IDR_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3716 #define GPIO_IDR_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3717 #define GPIO_IDR_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3718 #define GPIO_IDR_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3719 #define GPIO_IDR_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3720 #define GPIO_IDR_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3721 #define GPIO_IDR_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3722 #define GPIO_IDR_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3723 #define GPIO_IDR_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3724 #define GPIO_IDR_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3725 #define GPIO_IDR_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3726 #define GPIO_IDR_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3727 #define GPIO_IDR_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3728 #define GPIO_IDR_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3729
Kojto 109:9296ab0bfc11 3730 /****************** Bit definition for GPIO_ODR register ********************/
Kojto 109:9296ab0bfc11 3731 #define GPIO_ODR_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3732 #define GPIO_ODR_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3733 #define GPIO_ODR_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3734 #define GPIO_ODR_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3735 #define GPIO_ODR_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3736 #define GPIO_ODR_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3737 #define GPIO_ODR_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3738 #define GPIO_ODR_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3739 #define GPIO_ODR_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3740 #define GPIO_ODR_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3741 #define GPIO_ODR_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3742 #define GPIO_ODR_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3743 #define GPIO_ODR_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3744 #define GPIO_ODR_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3745 #define GPIO_ODR_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3746 #define GPIO_ODR_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3747
Kojto 109:9296ab0bfc11 3748 /****************** Bit definition for GPIO_BSRR register ********************/
Kojto 109:9296ab0bfc11 3749 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3750 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3751 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3752 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3753 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3754 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3755 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3756 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3757 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3758 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3759 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3760 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3761 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3762 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3763 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3764 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3765 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 3766 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 3767 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 3768 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 3769 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 3770 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 3771 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 3772 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 3773 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 3774 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 3775 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 3776 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 3777 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 3778 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 3779 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 3780 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 3781
Kojto 109:9296ab0bfc11 3782 /****************** Bit definition for GPIO_LCKR register ********************/
Kojto 109:9296ab0bfc11 3783 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3784 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3785 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3786 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3787 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3788 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3789 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3790 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3791 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3792 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3793 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3794 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3795 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3796 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3797 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3798 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3799 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 3800
Kojto 109:9296ab0bfc11 3801 /****************** Bit definition for GPIO_AFRL register ********************/
Kojto 109:9296ab0bfc11 3802 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 3803 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
Kojto 109:9296ab0bfc11 3804 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 3805 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
Kojto 109:9296ab0bfc11 3806 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 3807 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
Kojto 109:9296ab0bfc11 3808 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 3809 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
Kojto 109:9296ab0bfc11 3810
Kojto 109:9296ab0bfc11 3811 /****************** Bit definition for GPIO_AFRH register ********************/
Kojto 109:9296ab0bfc11 3812 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 3813 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
Kojto 109:9296ab0bfc11 3814 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 3815 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
Kojto 109:9296ab0bfc11 3816 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 3817 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
Kojto 109:9296ab0bfc11 3818 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 3819 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
Kojto 109:9296ab0bfc11 3820
Kojto 109:9296ab0bfc11 3821 /****************** Bit definition for GPIO_BRR register *********************/
Kojto 109:9296ab0bfc11 3822 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 3823 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 3824 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 3825 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 3826 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 3827 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 3828 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 3829 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 3830 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 3831 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 3832 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 3833 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 3834 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 3835 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 3836 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 3837 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 3838
Kojto 109:9296ab0bfc11 3839 /******************************************************************************/
Kojto 109:9296ab0bfc11 3840 /* */
Kojto 109:9296ab0bfc11 3841 /* Inter-integrated Circuit Interface (I2C) */
Kojto 109:9296ab0bfc11 3842 /* */
Kojto 109:9296ab0bfc11 3843 /******************************************************************************/
Kojto 109:9296ab0bfc11 3844 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 109:9296ab0bfc11 3845 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
Kojto 109:9296ab0bfc11 3846 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
Kojto 109:9296ab0bfc11 3847 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
Kojto 109:9296ab0bfc11 3848 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
Kojto 109:9296ab0bfc11 3849 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
Kojto 109:9296ab0bfc11 3850 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
Kojto 109:9296ab0bfc11 3851 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
Kojto 109:9296ab0bfc11 3852 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
Kojto 109:9296ab0bfc11 3853 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
Kojto 109:9296ab0bfc11 3854 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
Kojto 109:9296ab0bfc11 3855 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
Kojto 109:9296ab0bfc11 3856 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
Kojto 109:9296ab0bfc11 3857 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
Kojto 109:9296ab0bfc11 3858 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
Kojto 109:9296ab0bfc11 3859 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
Kojto 109:9296ab0bfc11 3860 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
Kojto 109:9296ab0bfc11 3861 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
Kojto 109:9296ab0bfc11 3862 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
Kojto 109:9296ab0bfc11 3863 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
Kojto 109:9296ab0bfc11 3864 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
Kojto 109:9296ab0bfc11 3865 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
Kojto 109:9296ab0bfc11 3866
Kojto 109:9296ab0bfc11 3867 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 109:9296ab0bfc11 3868 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
Kojto 109:9296ab0bfc11 3869 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
Kojto 109:9296ab0bfc11 3870 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
Kojto 109:9296ab0bfc11 3871 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
Kojto 109:9296ab0bfc11 3872 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
Kojto 109:9296ab0bfc11 3873 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
Kojto 109:9296ab0bfc11 3874 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
Kojto 109:9296ab0bfc11 3875 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
Kojto 109:9296ab0bfc11 3876 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
Kojto 109:9296ab0bfc11 3877 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
Kojto 109:9296ab0bfc11 3878 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
Kojto 109:9296ab0bfc11 3879
Kojto 109:9296ab0bfc11 3880 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 109:9296ab0bfc11 3881 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
Kojto 109:9296ab0bfc11 3882 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
Kojto 109:9296ab0bfc11 3883 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
Kojto 109:9296ab0bfc11 3884
Kojto 109:9296ab0bfc11 3885 /******************* Bit definition for I2C_OAR2 register *******************/
Kojto 109:9296ab0bfc11 3886 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
Kojto 109:9296ab0bfc11 3887 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
Kojto 109:9296ab0bfc11 3888 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
Kojto 109:9296ab0bfc11 3889
Kojto 109:9296ab0bfc11 3890 /******************* Bit definition for I2C_TIMINGR register *****************/
Kojto 109:9296ab0bfc11 3891 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
Kojto 109:9296ab0bfc11 3892 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
Kojto 109:9296ab0bfc11 3893 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
Kojto 109:9296ab0bfc11 3894 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
Kojto 109:9296ab0bfc11 3895 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
Kojto 109:9296ab0bfc11 3896
Kojto 109:9296ab0bfc11 3897 /******************* Bit definition for I2C_TIMEOUTR register *****************/
Kojto 109:9296ab0bfc11 3898 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
Kojto 109:9296ab0bfc11 3899 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
Kojto 109:9296ab0bfc11 3900 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
Kojto 109:9296ab0bfc11 3901 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
Kojto 109:9296ab0bfc11 3902 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
Kojto 109:9296ab0bfc11 3903
Kojto 109:9296ab0bfc11 3904 /****************** Bit definition for I2C_ISR register *********************/
Kojto 109:9296ab0bfc11 3905 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
Kojto 109:9296ab0bfc11 3906 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
Kojto 109:9296ab0bfc11 3907 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
Kojto 109:9296ab0bfc11 3908 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
Kojto 109:9296ab0bfc11 3909 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
Kojto 109:9296ab0bfc11 3910 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
Kojto 109:9296ab0bfc11 3911 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
Kojto 109:9296ab0bfc11 3912 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
Kojto 109:9296ab0bfc11 3913 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
Kojto 109:9296ab0bfc11 3914 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
Kojto 109:9296ab0bfc11 3915 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
Kojto 109:9296ab0bfc11 3916 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
Kojto 109:9296ab0bfc11 3917 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
Kojto 109:9296ab0bfc11 3918 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
Kojto 109:9296ab0bfc11 3919 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
Kojto 109:9296ab0bfc11 3920 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
Kojto 109:9296ab0bfc11 3921 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
Kojto 109:9296ab0bfc11 3922
Kojto 109:9296ab0bfc11 3923 /****************** Bit definition for I2C_ICR register *********************/
Kojto 109:9296ab0bfc11 3924 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
Kojto 109:9296ab0bfc11 3925 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
Kojto 109:9296ab0bfc11 3926 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
Kojto 109:9296ab0bfc11 3927 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
Kojto 109:9296ab0bfc11 3928 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
Kojto 109:9296ab0bfc11 3929 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
Kojto 109:9296ab0bfc11 3930 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
Kojto 109:9296ab0bfc11 3931 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
Kojto 109:9296ab0bfc11 3932 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
Kojto 109:9296ab0bfc11 3933
Kojto 109:9296ab0bfc11 3934 /****************** Bit definition for I2C_PECR register ********************/
Kojto 109:9296ab0bfc11 3935 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
Kojto 109:9296ab0bfc11 3936
Kojto 109:9296ab0bfc11 3937 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 109:9296ab0bfc11 3938 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
Kojto 109:9296ab0bfc11 3939
Kojto 109:9296ab0bfc11 3940 /****************** Bit definition for I2C_TXDR register *********************/
Kojto 109:9296ab0bfc11 3941 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
Kojto 109:9296ab0bfc11 3942
Kojto 109:9296ab0bfc11 3943
Kojto 109:9296ab0bfc11 3944 /******************************************************************************/
Kojto 109:9296ab0bfc11 3945 /* */
Kojto 109:9296ab0bfc11 3946 /* Independent WATCHDOG (IWDG) */
Kojto 109:9296ab0bfc11 3947 /* */
Kojto 109:9296ab0bfc11 3948 /******************************************************************************/
Kojto 109:9296ab0bfc11 3949 /******************* Bit definition for IWDG_KR register ********************/
Kojto 109:9296ab0bfc11 3950 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
Kojto 109:9296ab0bfc11 3951
Kojto 109:9296ab0bfc11 3952 /******************* Bit definition for IWDG_PR register ********************/
Kojto 109:9296ab0bfc11 3953 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
Kojto 109:9296ab0bfc11 3954 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3955 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3956 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3957
Kojto 109:9296ab0bfc11 3958 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 109:9296ab0bfc11 3959 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
Kojto 109:9296ab0bfc11 3960
Kojto 109:9296ab0bfc11 3961 /******************* Bit definition for IWDG_SR register ********************/
Kojto 109:9296ab0bfc11 3962 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
Kojto 109:9296ab0bfc11 3963 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
Kojto 109:9296ab0bfc11 3964 #define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
Kojto 109:9296ab0bfc11 3965
Kojto 109:9296ab0bfc11 3966 /******************* Bit definition for IWDG_KR register ********************/
Kojto 109:9296ab0bfc11 3967 #define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
Kojto 109:9296ab0bfc11 3968
Kojto 109:9296ab0bfc11 3969 /******************************************************************************/
Kojto 109:9296ab0bfc11 3970 /* */
Kojto 109:9296ab0bfc11 3971 /* Power Control */
Kojto 109:9296ab0bfc11 3972 /* */
Kojto 109:9296ab0bfc11 3973 /******************************************************************************/
Kojto 109:9296ab0bfc11 3974 /******************** Bit definition for PWR_CR register ********************/
Kojto 109:9296ab0bfc11 3975 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
Kojto 109:9296ab0bfc11 3976 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
Kojto 109:9296ab0bfc11 3977 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
Kojto 109:9296ab0bfc11 3978 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
Kojto 109:9296ab0bfc11 3979 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
Kojto 109:9296ab0bfc11 3980
Kojto 109:9296ab0bfc11 3981 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 109:9296ab0bfc11 3982 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 3983 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 3984 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 3985
Kojto 109:9296ab0bfc11 3986 /*!< PVD level configuration */
Kojto 109:9296ab0bfc11 3987 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
Kojto 109:9296ab0bfc11 3988 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
Kojto 109:9296ab0bfc11 3989 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
Kojto 109:9296ab0bfc11 3990 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
Kojto 109:9296ab0bfc11 3991 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
Kojto 109:9296ab0bfc11 3992 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
Kojto 109:9296ab0bfc11 3993 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
Kojto 109:9296ab0bfc11 3994 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
Kojto 109:9296ab0bfc11 3995
Kojto 109:9296ab0bfc11 3996 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
Kojto 109:9296ab0bfc11 3997
Kojto 109:9296ab0bfc11 3998 /******************* Bit definition for PWR_CSR register ********************/
Kojto 109:9296ab0bfc11 3999 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
Kojto 109:9296ab0bfc11 4000 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
Kojto 109:9296ab0bfc11 4001 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
Kojto 109:9296ab0bfc11 4002
Kojto 109:9296ab0bfc11 4003 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
Kojto 109:9296ab0bfc11 4004 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
Kojto 109:9296ab0bfc11 4005 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
Kojto 109:9296ab0bfc11 4006
Kojto 109:9296ab0bfc11 4007 /******************************************************************************/
Kojto 109:9296ab0bfc11 4008 /* */
Kojto 109:9296ab0bfc11 4009 /* Reset and Clock Control */
Kojto 109:9296ab0bfc11 4010 /* */
Kojto 109:9296ab0bfc11 4011 /******************************************************************************/
Kojto 109:9296ab0bfc11 4012 /******************** Bit definition for RCC_CR register ********************/
Kojto 109:9296ab0bfc11 4013 #define RCC_CR_HSION ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 4014 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 4015
Kojto 109:9296ab0bfc11 4016 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
Kojto 109:9296ab0bfc11 4017 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
Kojto 109:9296ab0bfc11 4018 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
Kojto 109:9296ab0bfc11 4019 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
Kojto 109:9296ab0bfc11 4020 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
Kojto 109:9296ab0bfc11 4021 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
Kojto 109:9296ab0bfc11 4022
Kojto 109:9296ab0bfc11 4023 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
Kojto 109:9296ab0bfc11 4024 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
Kojto 109:9296ab0bfc11 4025 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
Kojto 109:9296ab0bfc11 4026 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
Kojto 109:9296ab0bfc11 4027 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
Kojto 109:9296ab0bfc11 4028 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
Kojto 109:9296ab0bfc11 4029 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
Kojto 109:9296ab0bfc11 4030 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
Kojto 109:9296ab0bfc11 4031 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
Kojto 109:9296ab0bfc11 4032
Kojto 109:9296ab0bfc11 4033 #define RCC_CR_HSEON ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 4034 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 4035 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 4036 #define RCC_CR_CSSON ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 4037 #define RCC_CR_PLLON ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 4038 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 4039
Kojto 109:9296ab0bfc11 4040 /******************** Bit definition for RCC_CFGR register ******************/
Kojto 109:9296ab0bfc11 4041 /*!< SW configuration */
Kojto 109:9296ab0bfc11 4042 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
Kojto 109:9296ab0bfc11 4043 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4044 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4045
Kojto 109:9296ab0bfc11 4046 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
Kojto 109:9296ab0bfc11 4047 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
Kojto 109:9296ab0bfc11 4048 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
Kojto 109:9296ab0bfc11 4049
Kojto 109:9296ab0bfc11 4050 /*!< SWS configuration */
Kojto 109:9296ab0bfc11 4051 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 109:9296ab0bfc11 4052 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4053 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4054
Kojto 109:9296ab0bfc11 4055 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
Kojto 109:9296ab0bfc11 4056 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
Kojto 109:9296ab0bfc11 4057 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
Kojto 109:9296ab0bfc11 4058
Kojto 109:9296ab0bfc11 4059 /*!< HPRE configuration */
Kojto 109:9296ab0bfc11 4060 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 109:9296ab0bfc11 4061 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4062 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4063 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 4064 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 4065
Kojto 109:9296ab0bfc11 4066 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
Kojto 109:9296ab0bfc11 4067 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
Kojto 109:9296ab0bfc11 4068 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
Kojto 109:9296ab0bfc11 4069 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
Kojto 109:9296ab0bfc11 4070 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
Kojto 109:9296ab0bfc11 4071 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
Kojto 109:9296ab0bfc11 4072 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
Kojto 109:9296ab0bfc11 4073 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
Kojto 109:9296ab0bfc11 4074 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
Kojto 109:9296ab0bfc11 4075
Kojto 109:9296ab0bfc11 4076 /*!< PPRE1 configuration */
Kojto 109:9296ab0bfc11 4077 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 109:9296ab0bfc11 4078 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4079 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4080 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 4081
Kojto 109:9296ab0bfc11 4082 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 109:9296ab0bfc11 4083 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
Kojto 109:9296ab0bfc11 4084 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
Kojto 109:9296ab0bfc11 4085 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
Kojto 109:9296ab0bfc11 4086 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
Kojto 109:9296ab0bfc11 4087
Kojto 109:9296ab0bfc11 4088 /*!< PPRE2 configuration */
Kojto 109:9296ab0bfc11 4089 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 109:9296ab0bfc11 4090 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4091 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4092 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 4093
Kojto 109:9296ab0bfc11 4094 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 109:9296ab0bfc11 4095 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
Kojto 109:9296ab0bfc11 4096 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
Kojto 109:9296ab0bfc11 4097 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
Kojto 109:9296ab0bfc11 4098 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
Kojto 109:9296ab0bfc11 4099
Kojto 109:9296ab0bfc11 4100 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
Kojto 109:9296ab0bfc11 4101 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
Kojto 109:9296ab0bfc11 4102 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
Kojto 109:9296ab0bfc11 4103
Kojto 109:9296ab0bfc11 4104 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
Kojto 109:9296ab0bfc11 4105 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
Kojto 109:9296ab0bfc11 4106 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
Kojto 109:9296ab0bfc11 4107
Kojto 109:9296ab0bfc11 4108 /*!< PLLMUL configuration */
Kojto 109:9296ab0bfc11 4109 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
Kojto 109:9296ab0bfc11 4110 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4111 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4112 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 4113 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 4114
Kojto 109:9296ab0bfc11 4115 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
Kojto 109:9296ab0bfc11 4116 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
Kojto 109:9296ab0bfc11 4117 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
Kojto 109:9296ab0bfc11 4118 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
Kojto 109:9296ab0bfc11 4119 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
Kojto 109:9296ab0bfc11 4120 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
Kojto 109:9296ab0bfc11 4121 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
Kojto 109:9296ab0bfc11 4122 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
Kojto 109:9296ab0bfc11 4123 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
Kojto 109:9296ab0bfc11 4124 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
Kojto 109:9296ab0bfc11 4125 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
Kojto 109:9296ab0bfc11 4126 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
Kojto 109:9296ab0bfc11 4127 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
Kojto 109:9296ab0bfc11 4128 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
Kojto 109:9296ab0bfc11 4129 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
Kojto 109:9296ab0bfc11 4130
Kojto 109:9296ab0bfc11 4131 /*!< MCO configuration */
Kojto 109:9296ab0bfc11 4132 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
Kojto 109:9296ab0bfc11 4133 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4134 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4135 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 4136
Kojto 109:9296ab0bfc11 4137 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Kojto 109:9296ab0bfc11 4138 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
Kojto 109:9296ab0bfc11 4139 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
Kojto 109:9296ab0bfc11 4140 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
Kojto 109:9296ab0bfc11 4141 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
Kojto 109:9296ab0bfc11 4142 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
Kojto 109:9296ab0bfc11 4143 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
Kojto 109:9296ab0bfc11 4144
Kojto 109:9296ab0bfc11 4145 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
Kojto 109:9296ab0bfc11 4146 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
Kojto 109:9296ab0bfc11 4147 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
Kojto 109:9296ab0bfc11 4148 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
Kojto 109:9296ab0bfc11 4149 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
Kojto 109:9296ab0bfc11 4150 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
Kojto 109:9296ab0bfc11 4151 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
Kojto 109:9296ab0bfc11 4152 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
Kojto 109:9296ab0bfc11 4153 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
Kojto 109:9296ab0bfc11 4154
Kojto 109:9296ab0bfc11 4155 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
Kojto 109:9296ab0bfc11 4156
Kojto 109:9296ab0bfc11 4157 /********************* Bit definition for RCC_CIR register ********************/
Kojto 109:9296ab0bfc11 4158 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
Kojto 109:9296ab0bfc11 4159 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
Kojto 109:9296ab0bfc11 4160 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
Kojto 109:9296ab0bfc11 4161 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
Kojto 109:9296ab0bfc11 4162 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
Kojto 109:9296ab0bfc11 4163 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
Kojto 109:9296ab0bfc11 4164 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 4165 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 4166 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 4167 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 4168 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 4169 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 4170 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 4171 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 4172 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 4173 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 4174 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
Kojto 109:9296ab0bfc11 4175
Kojto 109:9296ab0bfc11 4176 /****************** Bit definition for RCC_APB2RSTR register *****************/
Kojto 109:9296ab0bfc11 4177 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
Kojto 109:9296ab0bfc11 4178 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 reset */
Kojto 109:9296ab0bfc11 4179 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
Kojto 109:9296ab0bfc11 4180 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
Kojto 109:9296ab0bfc11 4181 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
Kojto 109:9296ab0bfc11 4182 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
Kojto 109:9296ab0bfc11 4183 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
Kojto 109:9296ab0bfc11 4184
Kojto 109:9296ab0bfc11 4185 /****************** Bit definition for RCC_APB1RSTR register ******************/
Kojto 109:9296ab0bfc11 4186 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
Kojto 109:9296ab0bfc11 4187 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
Kojto 109:9296ab0bfc11 4188 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
Kojto 109:9296ab0bfc11 4189 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
Kojto 109:9296ab0bfc11 4190 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
Kojto 109:9296ab0bfc11 4191 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
Kojto 109:9296ab0bfc11 4192 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
Kojto 109:9296ab0bfc11 4193 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
Kojto 109:9296ab0bfc11 4194 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
Kojto 109:9296ab0bfc11 4195 #define RCC_APB1RSTR_DAC2RST ((uint32_t)0x04000000) /*!< DAC 2 reset */
Kojto 109:9296ab0bfc11 4196 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
Kojto 109:9296ab0bfc11 4197 #define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
Kojto 109:9296ab0bfc11 4198
Kojto 109:9296ab0bfc11 4199 /****************** Bit definition for RCC_AHBENR register ******************/
Kojto 109:9296ab0bfc11 4200 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
Kojto 109:9296ab0bfc11 4201 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
Kojto 109:9296ab0bfc11 4202 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
Kojto 109:9296ab0bfc11 4203 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
Kojto 109:9296ab0bfc11 4204 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
Kojto 109:9296ab0bfc11 4205 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
Kojto 109:9296ab0bfc11 4206 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
Kojto 109:9296ab0bfc11 4207 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
Kojto 109:9296ab0bfc11 4208 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
Kojto 109:9296ab0bfc11 4209 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
Kojto 109:9296ab0bfc11 4210 #define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
Kojto 109:9296ab0bfc11 4211
Kojto 109:9296ab0bfc11 4212 /***************** Bit definition for RCC_APB2ENR register ******************/
Kojto 109:9296ab0bfc11 4213 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
Kojto 109:9296ab0bfc11 4214 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
Kojto 109:9296ab0bfc11 4215 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
Kojto 109:9296ab0bfc11 4216 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
Kojto 109:9296ab0bfc11 4217 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
Kojto 109:9296ab0bfc11 4218 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
Kojto 109:9296ab0bfc11 4219 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
Kojto 109:9296ab0bfc11 4220
Kojto 109:9296ab0bfc11 4221 /****************** Bit definition for RCC_APB1ENR register ******************/
Kojto 109:9296ab0bfc11 4222 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
Kojto 109:9296ab0bfc11 4223 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
Kojto 109:9296ab0bfc11 4224 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
Kojto 109:9296ab0bfc11 4225 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
Kojto 109:9296ab0bfc11 4226 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
Kojto 109:9296ab0bfc11 4227 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
Kojto 109:9296ab0bfc11 4228 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
Kojto 109:9296ab0bfc11 4229 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
Kojto 109:9296ab0bfc11 4230 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
Kojto 109:9296ab0bfc11 4231 #define RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) /*!< DAC 2 clock enable */
Kojto 109:9296ab0bfc11 4232 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
Kojto 109:9296ab0bfc11 4233 #define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC 1 clock enable */
Kojto 109:9296ab0bfc11 4234
Kojto 109:9296ab0bfc11 4235 /******************** Bit definition for RCC_BDCR register ******************/
Kojto 109:9296ab0bfc11 4236 #define RCC_BDCR_LSE ((uint32_t)0x00000007) /*!< External Low Speed oscillator [2:0] bits */
Kojto 109:9296ab0bfc11 4237 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
Kojto 109:9296ab0bfc11 4238 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
Kojto 109:9296ab0bfc11 4239 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
Kojto 109:9296ab0bfc11 4240
Kojto 109:9296ab0bfc11 4241 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
Kojto 109:9296ab0bfc11 4242 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4243 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4244
Kojto 109:9296ab0bfc11 4245 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
Kojto 109:9296ab0bfc11 4246 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4247 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4248
Kojto 109:9296ab0bfc11 4249 /*!< RTC configuration */
Kojto 109:9296ab0bfc11 4250 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Kojto 109:9296ab0bfc11 4251 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
Kojto 109:9296ab0bfc11 4252 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
Kojto 109:9296ab0bfc11 4253 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
Kojto 109:9296ab0bfc11 4254
Kojto 109:9296ab0bfc11 4255 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
Kojto 109:9296ab0bfc11 4256 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
Kojto 109:9296ab0bfc11 4257
Kojto 109:9296ab0bfc11 4258 /******************** Bit definition for RCC_CSR register *******************/
Kojto 109:9296ab0bfc11 4259 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
Kojto 109:9296ab0bfc11 4260 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
Kojto 109:9296ab0bfc11 4261 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
Kojto 109:9296ab0bfc11 4262 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
Kojto 109:9296ab0bfc11 4263 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
Kojto 109:9296ab0bfc11 4264 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
Kojto 109:9296ab0bfc11 4265 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
Kojto 109:9296ab0bfc11 4266 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
Kojto 109:9296ab0bfc11 4267 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
Kojto 109:9296ab0bfc11 4268 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
Kojto 109:9296ab0bfc11 4269
Kojto 109:9296ab0bfc11 4270 /******************* Bit definition for RCC_AHBRSTR register ****************/
Kojto 109:9296ab0bfc11 4271 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
Kojto 109:9296ab0bfc11 4272 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
Kojto 109:9296ab0bfc11 4273 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
Kojto 109:9296ab0bfc11 4274 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD reset */
Kojto 109:9296ab0bfc11 4275 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */
Kojto 109:9296ab0bfc11 4276 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TSC reset */
Kojto 109:9296ab0bfc11 4277 #define RCC_AHBRSTR_ADC12RST ((uint32_t)0x10000000) /*!< ADC1 & ADC2 reset */
Kojto 109:9296ab0bfc11 4278
Kojto 109:9296ab0bfc11 4279 /******************* Bit definition for RCC_CFGR2 register ******************/
Kojto 109:9296ab0bfc11 4280 /*!< PREDIV configuration */
Kojto 109:9296ab0bfc11 4281 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
Kojto 109:9296ab0bfc11 4282 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4283 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4284 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 4285 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 4286
Kojto 109:9296ab0bfc11 4287 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
Kojto 109:9296ab0bfc11 4288 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
Kojto 109:9296ab0bfc11 4289 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
Kojto 109:9296ab0bfc11 4290 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
Kojto 109:9296ab0bfc11 4291 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
Kojto 109:9296ab0bfc11 4292 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
Kojto 109:9296ab0bfc11 4293 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
Kojto 109:9296ab0bfc11 4294 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
Kojto 109:9296ab0bfc11 4295 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
Kojto 109:9296ab0bfc11 4296 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
Kojto 109:9296ab0bfc11 4297 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
Kojto 109:9296ab0bfc11 4298 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
Kojto 109:9296ab0bfc11 4299 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
Kojto 109:9296ab0bfc11 4300 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
Kojto 109:9296ab0bfc11 4301 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
Kojto 109:9296ab0bfc11 4302 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
Kojto 109:9296ab0bfc11 4303
Kojto 109:9296ab0bfc11 4304 /*!< ADCPRE12 configuration */
Kojto 109:9296ab0bfc11 4305 #define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
Kojto 109:9296ab0bfc11 4306 #define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4307 #define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4308 #define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 4309 #define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 4310 #define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
Kojto 109:9296ab0bfc11 4311
Kojto 109:9296ab0bfc11 4312 #define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
Kojto 109:9296ab0bfc11 4313 #define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
Kojto 109:9296ab0bfc11 4314 #define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
Kojto 109:9296ab0bfc11 4315 #define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
Kojto 109:9296ab0bfc11 4316 #define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
Kojto 109:9296ab0bfc11 4317 #define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
Kojto 109:9296ab0bfc11 4318 #define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
Kojto 109:9296ab0bfc11 4319 #define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
Kojto 109:9296ab0bfc11 4320 #define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
Kojto 109:9296ab0bfc11 4321 #define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
Kojto 109:9296ab0bfc11 4322 #define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
Kojto 109:9296ab0bfc11 4323 #define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
Kojto 109:9296ab0bfc11 4324 #define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
Kojto 109:9296ab0bfc11 4325
Kojto 109:9296ab0bfc11 4326 /******************* Bit definition for RCC_CFGR3 register ******************/
Kojto 109:9296ab0bfc11 4327 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
Kojto 109:9296ab0bfc11 4328 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4329 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4330
Kojto 109:9296ab0bfc11 4331 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
Kojto 109:9296ab0bfc11 4332 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
Kojto 109:9296ab0bfc11 4333 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
Kojto 109:9296ab0bfc11 4334 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
Kojto 109:9296ab0bfc11 4335
Kojto 109:9296ab0bfc11 4336 #define RCC_CFGR3_I2CSW ((uint32_t)0x00000010) /*!< I2CSW bits */
Kojto 109:9296ab0bfc11 4337 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
Kojto 109:9296ab0bfc11 4338
Kojto 109:9296ab0bfc11 4339 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
Kojto 109:9296ab0bfc11 4340 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
Kojto 109:9296ab0bfc11 4341
Kojto 109:9296ab0bfc11 4342 #define RCC_CFGR3_TIMSW ((uint32_t)0x00000100) /*!< TIMSW bits */
Kojto 109:9296ab0bfc11 4343 #define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
Kojto 109:9296ab0bfc11 4344
Kojto 109:9296ab0bfc11 4345 #define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
Kojto 109:9296ab0bfc11 4346 #define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
Kojto 109:9296ab0bfc11 4347
Kojto 109:9296ab0bfc11 4348 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
Kojto 109:9296ab0bfc11 4349 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4350 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4351
Kojto 109:9296ab0bfc11 4352 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
Kojto 109:9296ab0bfc11 4353 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
Kojto 109:9296ab0bfc11 4354 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
Kojto 109:9296ab0bfc11 4355 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
Kojto 109:9296ab0bfc11 4356
Kojto 109:9296ab0bfc11 4357 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
Kojto 109:9296ab0bfc11 4358 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4359 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4360
Kojto 109:9296ab0bfc11 4361 #define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
Kojto 109:9296ab0bfc11 4362 #define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
Kojto 109:9296ab0bfc11 4363 #define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
Kojto 109:9296ab0bfc11 4364 #define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
Kojto 109:9296ab0bfc11 4365
Kojto 109:9296ab0bfc11 4366 /******************************************************************************/
Kojto 109:9296ab0bfc11 4367 /* */
Kojto 109:9296ab0bfc11 4368 /* Real-Time Clock (RTC) */
Kojto 109:9296ab0bfc11 4369 /* */
Kojto 109:9296ab0bfc11 4370 /******************************************************************************/
Kojto 109:9296ab0bfc11 4371 /******************** Bits definition for RTC_TR register *******************/
Kojto 109:9296ab0bfc11 4372 #define RTC_TR_PM ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 4373 #define RTC_TR_HT ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 4374 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 4375 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 4376 #define RTC_TR_HU ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 4377 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 4378 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 4379 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 4380 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 4381 #define RTC_TR_MNT ((uint32_t)0x00007000)
Kojto 109:9296ab0bfc11 4382 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 4383 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 4384 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 4385 #define RTC_TR_MNU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 4386 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 4387 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 4388 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 4389 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 4390 #define RTC_TR_ST ((uint32_t)0x00000070)
Kojto 109:9296ab0bfc11 4391 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 4392 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 4393 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 4394 #define RTC_TR_SU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 4395 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 4396 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 4397 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 4398 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 4399
Kojto 109:9296ab0bfc11 4400 /******************** Bits definition for RTC_DR register *******************/
Kojto 109:9296ab0bfc11 4401 #define RTC_DR_YT ((uint32_t)0x00F00000)
Kojto 109:9296ab0bfc11 4402 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 4403 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 4404 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 4405 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 4406 #define RTC_DR_YU ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 4407 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 4408 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 4409 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 4410 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 4411 #define RTC_DR_WDU ((uint32_t)0x0000E000)
Kojto 109:9296ab0bfc11 4412 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 4413 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 4414 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 4415 #define RTC_DR_MT ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 4416 #define RTC_DR_MU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 4417 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 4418 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 4419 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 4420 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 4421 #define RTC_DR_DT ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 4422 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 4423 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 4424 #define RTC_DR_DU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 4425 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 4426 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 4427 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 4428 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 4429
Kojto 109:9296ab0bfc11 4430 /******************** Bits definition for RTC_CR register *******************/
Kojto 109:9296ab0bfc11 4431 #define RTC_CR_COE ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 4432 #define RTC_CR_OSEL ((uint32_t)0x00600000)
Kojto 109:9296ab0bfc11 4433 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 4434 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 4435 #define RTC_CR_POL ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 4436 #define RTC_CR_COSEL ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 4437 #define RTC_CR_BCK ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 4438 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 4439 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 4440 #define RTC_CR_TSIE ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 4441 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 4442 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 4443 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 4444 #define RTC_CR_TSE ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 4445 #define RTC_CR_WUTE ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 4446 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 4447 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 4448 #define RTC_CR_FMT ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 4449 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 4450 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 4451 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 4452 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
Kojto 109:9296ab0bfc11 4453 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 4454 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 4455 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 4456
Kojto 109:9296ab0bfc11 4457 /******************** Bits definition for RTC_ISR register ******************/
Kojto 109:9296ab0bfc11 4458 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 4459 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 4460 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 4461 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 4462 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 4463 #define RTC_ISR_TSF ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 4464 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 4465 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 4466 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 4467 #define RTC_ISR_INIT ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 4468 #define RTC_ISR_INITF ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 4469 #define RTC_ISR_RSF ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 4470 #define RTC_ISR_INITS ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 4471 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 4472 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 4473 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 4474 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 4475
Kojto 109:9296ab0bfc11 4476 /******************** Bits definition for RTC_PRER register *****************/
Kojto 109:9296ab0bfc11 4477 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Kojto 109:9296ab0bfc11 4478 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Kojto 109:9296ab0bfc11 4479
Kojto 109:9296ab0bfc11 4480 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 109:9296ab0bfc11 4481 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
Kojto 109:9296ab0bfc11 4482
Kojto 109:9296ab0bfc11 4483 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 109:9296ab0bfc11 4484 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 4485 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 4486 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 4487 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 4488 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 4489 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 4490 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 4491 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 4492 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 4493 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 4494 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 4495 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 4496 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 4497 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 4498 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 4499 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 4500 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 4501 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 4502 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 4503 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 4504 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 4505 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Kojto 109:9296ab0bfc11 4506 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 4507 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 4508 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 4509 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 4510 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 4511 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 4512 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 4513 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 4514 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 4515 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Kojto 109:9296ab0bfc11 4516 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 4517 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 4518 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 4519 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 4520 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 4521 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 4522 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 4523 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 4524
Kojto 109:9296ab0bfc11 4525 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 109:9296ab0bfc11 4526 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 4527 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 4528 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 4529 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 4530 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 4531 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 4532 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 4533 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 4534 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 4535 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 4536 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 4537 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 4538 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 4539 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 4540 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 4541 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 4542 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 4543 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 4544 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 4545 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 4546 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 4547 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
Kojto 109:9296ab0bfc11 4548 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 4549 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 4550 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 4551 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 4552 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 4553 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 4554 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 4555 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 4556 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 4557 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
Kojto 109:9296ab0bfc11 4558 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 4559 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 4560 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 4561 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 4562 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 4563 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 4564 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 4565 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 4566
Kojto 109:9296ab0bfc11 4567 /******************** Bits definition for RTC_WPR register ******************/
Kojto 109:9296ab0bfc11 4568 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
Kojto 109:9296ab0bfc11 4569
Kojto 109:9296ab0bfc11 4570 /******************** Bits definition for RTC_SSR register ******************/
Kojto 109:9296ab0bfc11 4571 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Kojto 109:9296ab0bfc11 4572
Kojto 109:9296ab0bfc11 4573 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 109:9296ab0bfc11 4574 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Kojto 109:9296ab0bfc11 4575 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 4576
Kojto 109:9296ab0bfc11 4577 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 109:9296ab0bfc11 4578 #define RTC_TSTR_PM ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 4579 #define RTC_TSTR_HT ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 4580 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 4581 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 4582 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 4583 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 4584 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 4585 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 4586 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 4587 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
Kojto 109:9296ab0bfc11 4588 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 4589 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 4590 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 4591 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 4592 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 4593 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 4594 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 4595 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 4596 #define RTC_TSTR_ST ((uint32_t)0x00000070)
Kojto 109:9296ab0bfc11 4597 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 4598 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 4599 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 4600 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 4601 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 4602 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 4603 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 4604 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 4605
Kojto 109:9296ab0bfc11 4606 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 109:9296ab0bfc11 4607 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Kojto 109:9296ab0bfc11 4608 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 4609 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 4610 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 4611 #define RTC_TSDR_MT ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 4612 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 4613 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 4614 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 4615 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 4616 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 4617 #define RTC_TSDR_DT ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 4618 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 4619 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 4620 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 4621 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 4622 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 4623 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 4624 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 4625
Kojto 109:9296ab0bfc11 4626 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 109:9296ab0bfc11 4627 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Kojto 109:9296ab0bfc11 4628
Kojto 109:9296ab0bfc11 4629 /******************** Bits definition for RTC_CAL register *****************/
Kojto 109:9296ab0bfc11 4630 #define RTC_CALR_CALP ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 4631 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 4632 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 4633 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
Kojto 109:9296ab0bfc11 4634 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 4635 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 4636 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 4637 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 4638 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 4639 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 4640 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 4641 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 4642 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 4643
Kojto 109:9296ab0bfc11 4644 /******************** Bits definition for RTC_TAFCR register ****************/
Kojto 109:9296ab0bfc11 4645 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 4646 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 4647 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
Kojto 109:9296ab0bfc11 4648 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 4649 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 4650 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
Kojto 109:9296ab0bfc11 4651 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 4652 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 4653 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
Kojto 109:9296ab0bfc11 4654 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 4655 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 4656 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 4657 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 4658 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 4659 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 4660 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 4661 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 4662 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 4663 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 4664 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 4665
Kojto 109:9296ab0bfc11 4666 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 109:9296ab0bfc11 4667 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 4668 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 4669 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 4670 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 4671 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 4672 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Kojto 109:9296ab0bfc11 4673
Kojto 109:9296ab0bfc11 4674 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 109:9296ab0bfc11 4675 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 4676 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 4677 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 4678 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 4679 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 4680 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
Kojto 109:9296ab0bfc11 4681
Kojto 109:9296ab0bfc11 4682 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 109:9296ab0bfc11 4683 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4684
Kojto 109:9296ab0bfc11 4685 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 109:9296ab0bfc11 4686 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4687
Kojto 109:9296ab0bfc11 4688 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 109:9296ab0bfc11 4689 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4690
Kojto 109:9296ab0bfc11 4691 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 109:9296ab0bfc11 4692 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4693
Kojto 109:9296ab0bfc11 4694 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 109:9296ab0bfc11 4695 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4696
Kojto 109:9296ab0bfc11 4697 /******************** Bits definition for RTC_BKP5R register ****************/
Kojto 109:9296ab0bfc11 4698 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4699
Kojto 109:9296ab0bfc11 4700 /******************** Bits definition for RTC_BKP6R register ****************/
Kojto 109:9296ab0bfc11 4701 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4702
Kojto 109:9296ab0bfc11 4703 /******************** Bits definition for RTC_BKP7R register ****************/
Kojto 109:9296ab0bfc11 4704 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4705
Kojto 109:9296ab0bfc11 4706 /******************** Bits definition for RTC_BKP8R register ****************/
Kojto 109:9296ab0bfc11 4707 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4708
Kojto 109:9296ab0bfc11 4709 /******************** Bits definition for RTC_BKP9R register ****************/
Kojto 109:9296ab0bfc11 4710 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4711
Kojto 109:9296ab0bfc11 4712 /******************** Bits definition for RTC_BKP10R register ***************/
Kojto 109:9296ab0bfc11 4713 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4714
Kojto 109:9296ab0bfc11 4715 /******************** Bits definition for RTC_BKP11R register ***************/
Kojto 109:9296ab0bfc11 4716 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4717
Kojto 109:9296ab0bfc11 4718 /******************** Bits definition for RTC_BKP12R register ***************/
Kojto 109:9296ab0bfc11 4719 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4720
Kojto 109:9296ab0bfc11 4721 /******************** Bits definition for RTC_BKP13R register ***************/
Kojto 109:9296ab0bfc11 4722 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4723
Kojto 109:9296ab0bfc11 4724 /******************** Bits definition for RTC_BKP14R register ***************/
Kojto 109:9296ab0bfc11 4725 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4726
Kojto 109:9296ab0bfc11 4727 /******************** Bits definition for RTC_BKP15R register ***************/
Kojto 109:9296ab0bfc11 4728 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 4729
Kojto 109:9296ab0bfc11 4730 /******************** Number of backup registers ******************************/
Kojto 109:9296ab0bfc11 4731 #define RTC_BKP_NUMBER ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 4732
Kojto 109:9296ab0bfc11 4733 /******************************************************************************/
Kojto 109:9296ab0bfc11 4734 /* */
Kojto 109:9296ab0bfc11 4735 /* Serial Peripheral Interface (SPI) */
Kojto 109:9296ab0bfc11 4736 /* */
Kojto 109:9296ab0bfc11 4737 /******************************************************************************/
Kojto 109:9296ab0bfc11 4738 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 109:9296ab0bfc11 4739 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
Kojto 109:9296ab0bfc11 4740 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
Kojto 109:9296ab0bfc11 4741 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
Kojto 109:9296ab0bfc11 4742 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
Kojto 109:9296ab0bfc11 4743 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4744 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4745 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 4746 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
Kojto 109:9296ab0bfc11 4747 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
Kojto 109:9296ab0bfc11 4748 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
Kojto 109:9296ab0bfc11 4749 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
Kojto 109:9296ab0bfc11 4750 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
Kojto 109:9296ab0bfc11 4751 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
Kojto 109:9296ab0bfc11 4752 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
Kojto 109:9296ab0bfc11 4753 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
Kojto 109:9296ab0bfc11 4754 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
Kojto 109:9296ab0bfc11 4755 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
Kojto 109:9296ab0bfc11 4756
Kojto 109:9296ab0bfc11 4757 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 109:9296ab0bfc11 4758 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
Kojto 109:9296ab0bfc11 4759 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
Kojto 109:9296ab0bfc11 4760 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
Kojto 109:9296ab0bfc11 4761 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
Kojto 109:9296ab0bfc11 4762 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
Kojto 109:9296ab0bfc11 4763 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
Kojto 109:9296ab0bfc11 4764 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
Kojto 109:9296ab0bfc11 4765 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
Kojto 109:9296ab0bfc11 4766 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
Kojto 109:9296ab0bfc11 4767 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4768 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4769 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 4770 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 4771 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
Kojto 109:9296ab0bfc11 4772 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
Kojto 109:9296ab0bfc11 4773 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
Kojto 109:9296ab0bfc11 4774
Kojto 109:9296ab0bfc11 4775 /******************** Bit definition for SPI_SR register ********************/
Kojto 109:9296ab0bfc11 4776 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
Kojto 109:9296ab0bfc11 4777 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
Kojto 109:9296ab0bfc11 4778 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
Kojto 109:9296ab0bfc11 4779 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
Kojto 109:9296ab0bfc11 4780 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
Kojto 109:9296ab0bfc11 4781 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
Kojto 109:9296ab0bfc11 4782 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
Kojto 109:9296ab0bfc11 4783 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
Kojto 109:9296ab0bfc11 4784 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
Kojto 109:9296ab0bfc11 4785 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
Kojto 109:9296ab0bfc11 4786 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4787 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4788 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
Kojto 109:9296ab0bfc11 4789 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4790 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4791
Kojto 109:9296ab0bfc11 4792 /******************** Bit definition for SPI_DR register ********************/
Kojto 109:9296ab0bfc11 4793 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
Kojto 109:9296ab0bfc11 4794
Kojto 109:9296ab0bfc11 4795 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 109:9296ab0bfc11 4796 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
Kojto 109:9296ab0bfc11 4797
Kojto 109:9296ab0bfc11 4798 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 109:9296ab0bfc11 4799 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
Kojto 109:9296ab0bfc11 4800
Kojto 109:9296ab0bfc11 4801 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 109:9296ab0bfc11 4802 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
Kojto 109:9296ab0bfc11 4803
Kojto 109:9296ab0bfc11 4804 /******************************************************************************/
Kojto 109:9296ab0bfc11 4805 /* */
Kojto 109:9296ab0bfc11 4806 /* System Configuration(SYSCFG) */
Kojto 109:9296ab0bfc11 4807 /* */
Kojto 109:9296ab0bfc11 4808 /******************************************************************************/
Kojto 109:9296ab0bfc11 4809 /***************** Bit definition for SYSCFG_CFGR1 register *****************/
Kojto 109:9296ab0bfc11 4810 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
Kojto 109:9296ab0bfc11 4811 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 4812 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 4813 #define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
Kojto 109:9296ab0bfc11 4814 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
Kojto 109:9296ab0bfc11 4815 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x0000F800) /*!< DMA remap mask */
Kojto 109:9296ab0bfc11 4816 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
Kojto 109:9296ab0bfc11 4817 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
Kojto 109:9296ab0bfc11 4818 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
Kojto 109:9296ab0bfc11 4819 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
Kojto 109:9296ab0bfc11 4820 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */
Kojto 109:9296ab0bfc11 4821 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
Kojto 109:9296ab0bfc11 4822 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
Kojto 109:9296ab0bfc11 4823 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
Kojto 109:9296ab0bfc11 4824 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
Kojto 109:9296ab0bfc11 4825 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
Kojto 109:9296ab0bfc11 4826 #define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
Kojto 109:9296ab0bfc11 4827 #define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
Kojto 109:9296ab0bfc11 4828 #define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
Kojto 109:9296ab0bfc11 4829 #define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
Kojto 109:9296ab0bfc11 4830 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
Kojto 109:9296ab0bfc11 4831 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
Kojto 109:9296ab0bfc11 4832 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
Kojto 109:9296ab0bfc11 4833 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
Kojto 109:9296ab0bfc11 4834 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
Kojto 109:9296ab0bfc11 4835 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
Kojto 109:9296ab0bfc11 4836
Kojto 109:9296ab0bfc11 4837 /***************** Bit definition for SYSCFG_RCR register *******************/
Kojto 109:9296ab0bfc11 4838 #define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
Kojto 109:9296ab0bfc11 4839 #define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
Kojto 109:9296ab0bfc11 4840 #define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
Kojto 109:9296ab0bfc11 4841 #define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
Kojto 109:9296ab0bfc11 4842
Kojto 109:9296ab0bfc11 4843 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 109:9296ab0bfc11 4844 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
Kojto 109:9296ab0bfc11 4845 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
Kojto 109:9296ab0bfc11 4846 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
Kojto 109:9296ab0bfc11 4847 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
Kojto 109:9296ab0bfc11 4848
Kojto 109:9296ab0bfc11 4849 /*!<*
Kojto 109:9296ab0bfc11 4850 * @brief EXTI0 configuration
Kojto 109:9296ab0bfc11 4851 */
Kojto 109:9296ab0bfc11 4852 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
Kojto 109:9296ab0bfc11 4853 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
Kojto 109:9296ab0bfc11 4854 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
Kojto 109:9296ab0bfc11 4855 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
Kojto 109:9296ab0bfc11 4856 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
Kojto 109:9296ab0bfc11 4857 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
Kojto 109:9296ab0bfc11 4858
Kojto 109:9296ab0bfc11 4859 /*!<*
Kojto 109:9296ab0bfc11 4860 * @brief EXTI1 configuration
Kojto 109:9296ab0bfc11 4861 */
Kojto 109:9296ab0bfc11 4862 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
Kojto 109:9296ab0bfc11 4863 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
Kojto 109:9296ab0bfc11 4864 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
Kojto 109:9296ab0bfc11 4865 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
Kojto 109:9296ab0bfc11 4866 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
Kojto 109:9296ab0bfc11 4867 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
Kojto 109:9296ab0bfc11 4868
Kojto 109:9296ab0bfc11 4869 /*!<*
Kojto 109:9296ab0bfc11 4870 * @brief EXTI2 configuration
Kojto 109:9296ab0bfc11 4871 */
Kojto 109:9296ab0bfc11 4872 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
Kojto 109:9296ab0bfc11 4873 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
Kojto 109:9296ab0bfc11 4874 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
Kojto 109:9296ab0bfc11 4875 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
Kojto 109:9296ab0bfc11 4876 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
Kojto 109:9296ab0bfc11 4877 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
Kojto 109:9296ab0bfc11 4878
Kojto 109:9296ab0bfc11 4879 /*!<*
Kojto 109:9296ab0bfc11 4880 * @brief EXTI3 configuration
Kojto 109:9296ab0bfc11 4881 */
Kojto 109:9296ab0bfc11 4882 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
Kojto 109:9296ab0bfc11 4883 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
Kojto 109:9296ab0bfc11 4884 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
Kojto 109:9296ab0bfc11 4885 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
Kojto 109:9296ab0bfc11 4886 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
Kojto 109:9296ab0bfc11 4887
Kojto 109:9296ab0bfc11 4888 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
Kojto 109:9296ab0bfc11 4889 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
Kojto 109:9296ab0bfc11 4890 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
Kojto 109:9296ab0bfc11 4891 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
Kojto 109:9296ab0bfc11 4892 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
Kojto 109:9296ab0bfc11 4893
Kojto 109:9296ab0bfc11 4894 /*!<*
Kojto 109:9296ab0bfc11 4895 * @brief EXTI4 configuration
Kojto 109:9296ab0bfc11 4896 */
Kojto 109:9296ab0bfc11 4897 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
Kojto 109:9296ab0bfc11 4898 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
Kojto 109:9296ab0bfc11 4899 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
Kojto 109:9296ab0bfc11 4900 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
Kojto 109:9296ab0bfc11 4901 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
Kojto 109:9296ab0bfc11 4902 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
Kojto 109:9296ab0bfc11 4903
Kojto 109:9296ab0bfc11 4904 /*!<*
Kojto 109:9296ab0bfc11 4905 * @brief EXTI5 configuration
Kojto 109:9296ab0bfc11 4906 */
Kojto 109:9296ab0bfc11 4907 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
Kojto 109:9296ab0bfc11 4908 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
Kojto 109:9296ab0bfc11 4909 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
Kojto 109:9296ab0bfc11 4910 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
Kojto 109:9296ab0bfc11 4911 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
Kojto 109:9296ab0bfc11 4912 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
Kojto 109:9296ab0bfc11 4913
Kojto 109:9296ab0bfc11 4914 /*!<*
Kojto 109:9296ab0bfc11 4915 * @brief EXTI6 configuration
Kojto 109:9296ab0bfc11 4916 */
Kojto 109:9296ab0bfc11 4917 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
Kojto 109:9296ab0bfc11 4918 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
Kojto 109:9296ab0bfc11 4919 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
Kojto 109:9296ab0bfc11 4920 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
Kojto 109:9296ab0bfc11 4921 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
Kojto 109:9296ab0bfc11 4922 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
Kojto 109:9296ab0bfc11 4923
Kojto 109:9296ab0bfc11 4924 /*!<*
Kojto 109:9296ab0bfc11 4925 * @brief EXTI7 configuration
Kojto 109:9296ab0bfc11 4926 */
Kojto 109:9296ab0bfc11 4927 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
Kojto 109:9296ab0bfc11 4928 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
Kojto 109:9296ab0bfc11 4929 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
Kojto 109:9296ab0bfc11 4930 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
Kojto 109:9296ab0bfc11 4931 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
Kojto 109:9296ab0bfc11 4932
Kojto 109:9296ab0bfc11 4933 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
Kojto 109:9296ab0bfc11 4934 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
Kojto 109:9296ab0bfc11 4935 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
Kojto 109:9296ab0bfc11 4936 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
Kojto 109:9296ab0bfc11 4937 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
Kojto 109:9296ab0bfc11 4938
Kojto 109:9296ab0bfc11 4939 /*!<*
Kojto 109:9296ab0bfc11 4940 * @brief EXTI8 configuration
Kojto 109:9296ab0bfc11 4941 */
Kojto 109:9296ab0bfc11 4942 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
Kojto 109:9296ab0bfc11 4943 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
Kojto 109:9296ab0bfc11 4944 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
Kojto 109:9296ab0bfc11 4945 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
Kojto 109:9296ab0bfc11 4946 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
Kojto 109:9296ab0bfc11 4947
Kojto 109:9296ab0bfc11 4948 /*!<*
Kojto 109:9296ab0bfc11 4949 * @brief EXTI9 configuration
Kojto 109:9296ab0bfc11 4950 */
Kojto 109:9296ab0bfc11 4951 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
Kojto 109:9296ab0bfc11 4952 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
Kojto 109:9296ab0bfc11 4953 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
Kojto 109:9296ab0bfc11 4954 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
Kojto 109:9296ab0bfc11 4955 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
Kojto 109:9296ab0bfc11 4956 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
Kojto 109:9296ab0bfc11 4957
Kojto 109:9296ab0bfc11 4958 /*!<*
Kojto 109:9296ab0bfc11 4959 * @brief EXTI10 configuration
Kojto 109:9296ab0bfc11 4960 */
Kojto 109:9296ab0bfc11 4961 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
Kojto 109:9296ab0bfc11 4962 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
Kojto 109:9296ab0bfc11 4963 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
Kojto 109:9296ab0bfc11 4964 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
Kojto 109:9296ab0bfc11 4965 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
Kojto 109:9296ab0bfc11 4966 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
Kojto 109:9296ab0bfc11 4967
Kojto 109:9296ab0bfc11 4968 /*!<*
Kojto 109:9296ab0bfc11 4969 * @brief EXTI11 configuration
Kojto 109:9296ab0bfc11 4970 */
Kojto 109:9296ab0bfc11 4971 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
Kojto 109:9296ab0bfc11 4972 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
Kojto 109:9296ab0bfc11 4973 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
Kojto 109:9296ab0bfc11 4974 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
Kojto 109:9296ab0bfc11 4975 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
Kojto 109:9296ab0bfc11 4976
Kojto 109:9296ab0bfc11 4977 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
Kojto 109:9296ab0bfc11 4978 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
Kojto 109:9296ab0bfc11 4979 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
Kojto 109:9296ab0bfc11 4980 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
Kojto 109:9296ab0bfc11 4981 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
Kojto 109:9296ab0bfc11 4982
Kojto 109:9296ab0bfc11 4983 /*!<*
Kojto 109:9296ab0bfc11 4984 * @brief EXTI12 configuration
Kojto 109:9296ab0bfc11 4985 */
Kojto 109:9296ab0bfc11 4986 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
Kojto 109:9296ab0bfc11 4987 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
Kojto 109:9296ab0bfc11 4988 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
Kojto 109:9296ab0bfc11 4989 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
Kojto 109:9296ab0bfc11 4990 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
Kojto 109:9296ab0bfc11 4991
Kojto 109:9296ab0bfc11 4992 /*!<*
Kojto 109:9296ab0bfc11 4993 * @brief EXTI13 configuration
Kojto 109:9296ab0bfc11 4994 */
Kojto 109:9296ab0bfc11 4995 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
Kojto 109:9296ab0bfc11 4996 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
Kojto 109:9296ab0bfc11 4997 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
Kojto 109:9296ab0bfc11 4998 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
Kojto 109:9296ab0bfc11 4999 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
Kojto 109:9296ab0bfc11 5000
Kojto 109:9296ab0bfc11 5001 /*!<*
Kojto 109:9296ab0bfc11 5002 * @brief EXTI14 configuration
Kojto 109:9296ab0bfc11 5003 */
Kojto 109:9296ab0bfc11 5004 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
Kojto 109:9296ab0bfc11 5005 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
Kojto 109:9296ab0bfc11 5006 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
Kojto 109:9296ab0bfc11 5007 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
Kojto 109:9296ab0bfc11 5008 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
Kojto 109:9296ab0bfc11 5009
Kojto 109:9296ab0bfc11 5010 /*!<*
Kojto 109:9296ab0bfc11 5011 * @brief EXTI15 configuration
Kojto 109:9296ab0bfc11 5012 */
Kojto 109:9296ab0bfc11 5013 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
Kojto 109:9296ab0bfc11 5014 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
Kojto 109:9296ab0bfc11 5015 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
Kojto 109:9296ab0bfc11 5016 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
Kojto 109:9296ab0bfc11 5017 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
Kojto 109:9296ab0bfc11 5018
Kojto 109:9296ab0bfc11 5019 /***************** Bit definition for SYSCFG_CFGR2 register *****************/
Kojto 109:9296ab0bfc11 5020 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
Kojto 109:9296ab0bfc11 5021 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */
Kojto 109:9296ab0bfc11 5022 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
Kojto 109:9296ab0bfc11 5023 #define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
Kojto 109:9296ab0bfc11 5024 #define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
Kojto 109:9296ab0bfc11 5025
Kojto 109:9296ab0bfc11 5026 /***************** Bit definition for SYSCFG_CFGR3 register *****************/
Kojto 109:9296ab0bfc11 5027 #define SYSCFG_CFGR3_DMA_RMP ((uint32_t)0x000003FF) /*!< DMA remap mask */
Kojto 109:9296ab0bfc11 5028 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP ((uint32_t)0x00000003) /*!< SPI1 RX DMA remap */
Kojto 109:9296ab0bfc11 5029 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 ((uint32_t)0x00000001) /*!< SPI1 RX DMA remap bit 0 */
Kojto 109:9296ab0bfc11 5030 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 ((uint32_t)0x00000002) /*!< SPI1 RX DMA remap bit 1 */
Kojto 109:9296ab0bfc11 5031 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP ((uint32_t)0x0000000C) /*!< SPI1 TX DMA remap */
Kojto 109:9296ab0bfc11 5032 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 ((uint32_t)0x00000004) /*!< SPI1 TX DMA remap bit 0 */
Kojto 109:9296ab0bfc11 5033 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 ((uint32_t)0x00000008) /*!< SPI1 TX DMA remap bit 1 */
Kojto 109:9296ab0bfc11 5034 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP ((uint32_t)0x00000030) /*!< I2C1 RX DMA remap */
Kojto 109:9296ab0bfc11 5035 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 ((uint32_t)0x00000010) /*!< I2C1 RX DMA remap bit 0 */
Kojto 109:9296ab0bfc11 5036 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 ((uint32_t)0x00000020) /*!< I2C1 RX DMA remap bit 1 */
Kojto 109:9296ab0bfc11 5037 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP ((uint32_t)0x000000C0) /*!< I2C1 RX DMA remap */
Kojto 109:9296ab0bfc11 5038 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 ((uint32_t)0x00000040) /*!< I2C1 TX DMA remap bit 0 */
Kojto 109:9296ab0bfc11 5039 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 ((uint32_t)0x00000080) /*!< I2C1 TX DMA remap bit 1 */
Kojto 109:9296ab0bfc11 5040 #define SYSCFG_CFGR3_ADC2_DMA_RMP ((uint32_t)0x00000300) /*!< ADC2 DMA remap */
Kojto 109:9296ab0bfc11 5041 #define SYSCFG_CFGR3_ADC2_DMA_RMP_0 ((uint32_t)0x00000100) /*!< ADC2 DMA remap bit 0 */
Kojto 109:9296ab0bfc11 5042 #define SYSCFG_CFGR3_ADC2_DMA_RMP_1 ((uint32_t)0x00000200) /*!< ADC2 DMA remap bit 1 */
Kojto 109:9296ab0bfc11 5043
Kojto 109:9296ab0bfc11 5044 /******************************************************************************/
Kojto 109:9296ab0bfc11 5045 /* */
Kojto 109:9296ab0bfc11 5046 /* TIM */
Kojto 109:9296ab0bfc11 5047 /* */
Kojto 109:9296ab0bfc11 5048 /******************************************************************************/
Kojto 109:9296ab0bfc11 5049 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 109:9296ab0bfc11 5050 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
Kojto 109:9296ab0bfc11 5051 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
Kojto 109:9296ab0bfc11 5052 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
Kojto 109:9296ab0bfc11 5053 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
Kojto 109:9296ab0bfc11 5054 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
Kojto 109:9296ab0bfc11 5055
Kojto 109:9296ab0bfc11 5056 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 109:9296ab0bfc11 5057 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5058 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5059
Kojto 109:9296ab0bfc11 5060 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
Kojto 109:9296ab0bfc11 5061
Kojto 109:9296ab0bfc11 5062 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
Kojto 109:9296ab0bfc11 5063 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5064 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5065
Kojto 109:9296ab0bfc11 5066 #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */
Kojto 109:9296ab0bfc11 5067
Kojto 109:9296ab0bfc11 5068 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 109:9296ab0bfc11 5069 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
Kojto 109:9296ab0bfc11 5070 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
Kojto 109:9296ab0bfc11 5071 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
Kojto 109:9296ab0bfc11 5072
Kojto 109:9296ab0bfc11 5073 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 109:9296ab0bfc11 5074 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5075 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5076 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5077
Kojto 109:9296ab0bfc11 5078 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
Kojto 109:9296ab0bfc11 5079 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
Kojto 109:9296ab0bfc11 5080 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
Kojto 109:9296ab0bfc11 5081 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
Kojto 109:9296ab0bfc11 5082 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
Kojto 109:9296ab0bfc11 5083 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
Kojto 109:9296ab0bfc11 5084 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
Kojto 109:9296ab0bfc11 5085 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
Kojto 109:9296ab0bfc11 5086 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
Kojto 109:9296ab0bfc11 5087 #define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
Kojto 109:9296ab0bfc11 5088
Kojto 109:9296ab0bfc11 5089 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 109:9296ab0bfc11 5090 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5091 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5092 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5093 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5094
Kojto 109:9296ab0bfc11 5095 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 109:9296ab0bfc11 5096 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 109:9296ab0bfc11 5097 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5098 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5099 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5100 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5101
Kojto 109:9296ab0bfc11 5102 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
Kojto 109:9296ab0bfc11 5103
Kojto 109:9296ab0bfc11 5104 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
Kojto 109:9296ab0bfc11 5105 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5106 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5107 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5108
Kojto 109:9296ab0bfc11 5109 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
Kojto 109:9296ab0bfc11 5110
Kojto 109:9296ab0bfc11 5111 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
Kojto 109:9296ab0bfc11 5112 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5113 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5114 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5115 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5116
Kojto 109:9296ab0bfc11 5117 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 109:9296ab0bfc11 5118 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5119 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5120
Kojto 109:9296ab0bfc11 5121 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
Kojto 109:9296ab0bfc11 5122 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
Kojto 109:9296ab0bfc11 5123
Kojto 109:9296ab0bfc11 5124 /******************* Bit definition for TIM_DIER register *******************/
Kojto 109:9296ab0bfc11 5125 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
Kojto 109:9296ab0bfc11 5126 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
Kojto 109:9296ab0bfc11 5127 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
Kojto 109:9296ab0bfc11 5128 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
Kojto 109:9296ab0bfc11 5129 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
Kojto 109:9296ab0bfc11 5130 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
Kojto 109:9296ab0bfc11 5131 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
Kojto 109:9296ab0bfc11 5132 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
Kojto 109:9296ab0bfc11 5133 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
Kojto 109:9296ab0bfc11 5134 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
Kojto 109:9296ab0bfc11 5135 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
Kojto 109:9296ab0bfc11 5136 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
Kojto 109:9296ab0bfc11 5137 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
Kojto 109:9296ab0bfc11 5138 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
Kojto 109:9296ab0bfc11 5139 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
Kojto 109:9296ab0bfc11 5140
Kojto 109:9296ab0bfc11 5141 /******************** Bit definition for TIM_SR register ********************/
Kojto 109:9296ab0bfc11 5142 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
Kojto 109:9296ab0bfc11 5143 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
Kojto 109:9296ab0bfc11 5144 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
Kojto 109:9296ab0bfc11 5145 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
Kojto 109:9296ab0bfc11 5146 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
Kojto 109:9296ab0bfc11 5147 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
Kojto 109:9296ab0bfc11 5148 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
Kojto 109:9296ab0bfc11 5149 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
Kojto 109:9296ab0bfc11 5150 #define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
Kojto 109:9296ab0bfc11 5151 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
Kojto 109:9296ab0bfc11 5152 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
Kojto 109:9296ab0bfc11 5153 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
Kojto 109:9296ab0bfc11 5154 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
Kojto 109:9296ab0bfc11 5155 #define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
Kojto 109:9296ab0bfc11 5156 #define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
Kojto 109:9296ab0bfc11 5157
Kojto 109:9296ab0bfc11 5158 /******************* Bit definition for TIM_EGR register ********************/
Kojto 109:9296ab0bfc11 5159 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
Kojto 109:9296ab0bfc11 5160 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
Kojto 109:9296ab0bfc11 5161 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
Kojto 109:9296ab0bfc11 5162 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
Kojto 109:9296ab0bfc11 5163 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
Kojto 109:9296ab0bfc11 5164 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
Kojto 109:9296ab0bfc11 5165 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
Kojto 109:9296ab0bfc11 5166 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
Kojto 109:9296ab0bfc11 5167 #define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break Generation */
Kojto 109:9296ab0bfc11 5168
Kojto 109:9296ab0bfc11 5169 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 109:9296ab0bfc11 5170 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 109:9296ab0bfc11 5171 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5172 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5173
Kojto 109:9296ab0bfc11 5174 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
Kojto 109:9296ab0bfc11 5175 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
Kojto 109:9296ab0bfc11 5176
Kojto 109:9296ab0bfc11 5177 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 109:9296ab0bfc11 5178 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5179 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5180 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5181 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5182
Kojto 109:9296ab0bfc11 5183 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
Kojto 109:9296ab0bfc11 5184
Kojto 109:9296ab0bfc11 5185 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 109:9296ab0bfc11 5186 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5187 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5188
Kojto 109:9296ab0bfc11 5189 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
Kojto 109:9296ab0bfc11 5190 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
Kojto 109:9296ab0bfc11 5191
Kojto 109:9296ab0bfc11 5192 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 109:9296ab0bfc11 5193 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5194 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5195 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5196 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5197
Kojto 109:9296ab0bfc11 5198 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
Kojto 109:9296ab0bfc11 5199
Kojto 109:9296ab0bfc11 5200 /*----------------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 5201
Kojto 109:9296ab0bfc11 5202 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 109:9296ab0bfc11 5203 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5204 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5205
Kojto 109:9296ab0bfc11 5206 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 109:9296ab0bfc11 5207 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5208 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5209 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5210 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5211
Kojto 109:9296ab0bfc11 5212 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 109:9296ab0bfc11 5213 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5214 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5215
Kojto 109:9296ab0bfc11 5216 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 109:9296ab0bfc11 5217 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5218 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5219 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5220 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5221
Kojto 109:9296ab0bfc11 5222 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 109:9296ab0bfc11 5223 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 109:9296ab0bfc11 5224 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5225 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5226
Kojto 109:9296ab0bfc11 5227 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
Kojto 109:9296ab0bfc11 5228 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
Kojto 109:9296ab0bfc11 5229
Kojto 109:9296ab0bfc11 5230 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 109:9296ab0bfc11 5231 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5232 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5233 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5234 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5235
Kojto 109:9296ab0bfc11 5236 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
Kojto 109:9296ab0bfc11 5237
Kojto 109:9296ab0bfc11 5238 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 109:9296ab0bfc11 5239 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5240 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5241
Kojto 109:9296ab0bfc11 5242 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
Kojto 109:9296ab0bfc11 5243 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
Kojto 109:9296ab0bfc11 5244
Kojto 109:9296ab0bfc11 5245 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 109:9296ab0bfc11 5246 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5247 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5248 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5249 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5250
Kojto 109:9296ab0bfc11 5251 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
Kojto 109:9296ab0bfc11 5252
Kojto 109:9296ab0bfc11 5253 /*----------------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 5254
Kojto 109:9296ab0bfc11 5255 #define TIM_CCMR2_IC3PSC ((uint32_t)0x00000000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 109:9296ab0bfc11 5256 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x000000000004) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5257 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x000000000008) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5258
Kojto 109:9296ab0bfc11 5259 #define TIM_CCMR2_IC3F ((uint32_t)0x0000000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 109:9296ab0bfc11 5260 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x000000000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5261 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x000000000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5262 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x000000000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5263 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x000000000080) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5264
Kojto 109:9296ab0bfc11 5265 #define TIM_CCMR2_IC4PSC ((uint32_t)0x000000000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 109:9296ab0bfc11 5266 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x000000000400) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5267 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x000000000800) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5268
Kojto 109:9296ab0bfc11 5269 #define TIM_CCMR2_IC4F ((uint32_t)0x00000000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 109:9296ab0bfc11 5270 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x000000001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5271 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x000000002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5272 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x000000004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5273 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x000000008000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5274
Kojto 109:9296ab0bfc11 5275 /******************* Bit definition for TIM_CCER register *******************/
Kojto 109:9296ab0bfc11 5276 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
Kojto 109:9296ab0bfc11 5277 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
Kojto 109:9296ab0bfc11 5278 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
Kojto 109:9296ab0bfc11 5279 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 109:9296ab0bfc11 5280 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
Kojto 109:9296ab0bfc11 5281 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
Kojto 109:9296ab0bfc11 5282 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
Kojto 109:9296ab0bfc11 5283 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 109:9296ab0bfc11 5284 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
Kojto 109:9296ab0bfc11 5285 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
Kojto 109:9296ab0bfc11 5286 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
Kojto 109:9296ab0bfc11 5287 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 109:9296ab0bfc11 5288 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
Kojto 109:9296ab0bfc11 5289 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
Kojto 109:9296ab0bfc11 5290 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 109:9296ab0bfc11 5291 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
Kojto 109:9296ab0bfc11 5292 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
Kojto 109:9296ab0bfc11 5293 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
Kojto 109:9296ab0bfc11 5294 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
Kojto 109:9296ab0bfc11 5295
Kojto 109:9296ab0bfc11 5296 /******************* Bit definition for TIM_CNT register ********************/
Kojto 109:9296ab0bfc11 5297 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
Kojto 109:9296ab0bfc11 5298 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
Kojto 109:9296ab0bfc11 5299
Kojto 109:9296ab0bfc11 5300 /******************* Bit definition for TIM_PSC register ********************/
Kojto 109:9296ab0bfc11 5301 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
Kojto 109:9296ab0bfc11 5302
Kojto 109:9296ab0bfc11 5303 /******************* Bit definition for TIM_ARR register ********************/
Kojto 109:9296ab0bfc11 5304 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
Kojto 109:9296ab0bfc11 5305
Kojto 109:9296ab0bfc11 5306 /******************* Bit definition for TIM_RCR register ********************/
Kojto 109:9296ab0bfc11 5307 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
Kojto 109:9296ab0bfc11 5308
Kojto 109:9296ab0bfc11 5309 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 109:9296ab0bfc11 5310 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
Kojto 109:9296ab0bfc11 5311
Kojto 109:9296ab0bfc11 5312 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 109:9296ab0bfc11 5313 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
Kojto 109:9296ab0bfc11 5314
Kojto 109:9296ab0bfc11 5315 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 109:9296ab0bfc11 5316 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
Kojto 109:9296ab0bfc11 5317
Kojto 109:9296ab0bfc11 5318 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 109:9296ab0bfc11 5319 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
Kojto 109:9296ab0bfc11 5320
Kojto 109:9296ab0bfc11 5321 /******************* Bit definition for TIM_CCR5 register *******************/
Kojto 109:9296ab0bfc11 5322 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
Kojto 109:9296ab0bfc11 5323 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
Kojto 109:9296ab0bfc11 5324 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
Kojto 109:9296ab0bfc11 5325 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
Kojto 109:9296ab0bfc11 5326
Kojto 109:9296ab0bfc11 5327 /******************* Bit definition for TIM_CCR6 register *******************/
Kojto 109:9296ab0bfc11 5328 #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */
Kojto 109:9296ab0bfc11 5329
Kojto 109:9296ab0bfc11 5330 /******************* Bit definition for TIM_BDTR register *******************/
Kojto 109:9296ab0bfc11 5331 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 109:9296ab0bfc11 5332 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5333 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5334 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5335 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5336 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 5337 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 109:9296ab0bfc11 5338 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 109:9296ab0bfc11 5339 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 109:9296ab0bfc11 5340
Kojto 109:9296ab0bfc11 5341 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 109:9296ab0bfc11 5342 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5343 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5344
Kojto 109:9296ab0bfc11 5345 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
Kojto 109:9296ab0bfc11 5346 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
Kojto 109:9296ab0bfc11 5347 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
Kojto 109:9296ab0bfc11 5348 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
Kojto 109:9296ab0bfc11 5349 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
Kojto 109:9296ab0bfc11 5350 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
Kojto 109:9296ab0bfc11 5351
Kojto 109:9296ab0bfc11 5352 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
Kojto 109:9296ab0bfc11 5353 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
Kojto 109:9296ab0bfc11 5354
Kojto 109:9296ab0bfc11 5355 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
Kojto 109:9296ab0bfc11 5356 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
Kojto 109:9296ab0bfc11 5357
Kojto 109:9296ab0bfc11 5358 /******************* Bit definition for TIM_DCR register ********************/
Kojto 109:9296ab0bfc11 5359 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 109:9296ab0bfc11 5360 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5361 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5362 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5363 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5364 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 5365
Kojto 109:9296ab0bfc11 5366 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 109:9296ab0bfc11 5367 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5368 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5369 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5370 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5371 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 5372
Kojto 109:9296ab0bfc11 5373 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 109:9296ab0bfc11 5374 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
Kojto 109:9296ab0bfc11 5375
Kojto 109:9296ab0bfc11 5376 /******************* Bit definition for TIM16_OR register *********************/
Kojto 109:9296ab0bfc11 5377 #define TIM16_OR_TI1_RMP ((uint32_t)0x000000C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
Kojto 109:9296ab0bfc11 5378 #define TIM16_OR_TI1_RMP_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5379 #define TIM16_OR_TI1_RMP_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5380
Kojto 109:9296ab0bfc11 5381 /******************* Bit definition for TIM1_OR register *********************/
Kojto 109:9296ab0bfc11 5382 #define TIM1_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
Kojto 109:9296ab0bfc11 5383 #define TIM1_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5384 #define TIM1_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5385 #define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5386 #define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5387
Kojto 109:9296ab0bfc11 5388 /****************** Bit definition for TIM_CCMR3 register *******************/
Kojto 109:9296ab0bfc11 5389 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
Kojto 109:9296ab0bfc11 5390 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
Kojto 109:9296ab0bfc11 5391
Kojto 109:9296ab0bfc11 5392 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
Kojto 109:9296ab0bfc11 5393 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5394 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5395 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5396 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5397
Kojto 109:9296ab0bfc11 5398 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
Kojto 109:9296ab0bfc11 5399
Kojto 109:9296ab0bfc11 5400 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */
Kojto 109:9296ab0bfc11 5401 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */
Kojto 109:9296ab0bfc11 5402
Kojto 109:9296ab0bfc11 5403 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
Kojto 109:9296ab0bfc11 5404 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5405 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5406 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5407 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5408
Kojto 109:9296ab0bfc11 5409 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */
Kojto 109:9296ab0bfc11 5410
Kojto 109:9296ab0bfc11 5411 /******************************************************************************/
Kojto 109:9296ab0bfc11 5412 /* */
Kojto 109:9296ab0bfc11 5413 /* Touch Sensing Controller (TSC) */
Kojto 109:9296ab0bfc11 5414 /* */
Kojto 109:9296ab0bfc11 5415 /******************************************************************************/
Kojto 109:9296ab0bfc11 5416 /******************* Bit definition for TSC_CR register *********************/
Kojto 109:9296ab0bfc11 5417 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
Kojto 109:9296ab0bfc11 5418 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
Kojto 109:9296ab0bfc11 5419 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
Kojto 109:9296ab0bfc11 5420 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
Kojto 109:9296ab0bfc11 5421 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
Kojto 109:9296ab0bfc11 5422
Kojto 109:9296ab0bfc11 5423 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
Kojto 109:9296ab0bfc11 5424 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5425 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5426 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5427
Kojto 109:9296ab0bfc11 5428 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
Kojto 109:9296ab0bfc11 5429 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5430 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5431 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5432
Kojto 109:9296ab0bfc11 5433 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
Kojto 109:9296ab0bfc11 5434 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
Kojto 109:9296ab0bfc11 5435
Kojto 109:9296ab0bfc11 5436 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
Kojto 109:9296ab0bfc11 5437 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5438 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5439 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5440 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5441 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 5442 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
Kojto 109:9296ab0bfc11 5443 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
Kojto 109:9296ab0bfc11 5444
Kojto 109:9296ab0bfc11 5445 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
Kojto 109:9296ab0bfc11 5446 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5447 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5448 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5449 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5450
Kojto 109:9296ab0bfc11 5451 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
Kojto 109:9296ab0bfc11 5452 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5453 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5454 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5455 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5456
Kojto 109:9296ab0bfc11 5457 /******************* Bit definition for TSC_IER register ********************/
Kojto 109:9296ab0bfc11 5458 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
Kojto 109:9296ab0bfc11 5459 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
Kojto 109:9296ab0bfc11 5460
Kojto 109:9296ab0bfc11 5461 /******************* Bit definition for TSC_ICR register ********************/
Kojto 109:9296ab0bfc11 5462 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
Kojto 109:9296ab0bfc11 5463 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
Kojto 109:9296ab0bfc11 5464
Kojto 109:9296ab0bfc11 5465 /******************* Bit definition for TSC_ISR register ********************/
Kojto 109:9296ab0bfc11 5466 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
Kojto 109:9296ab0bfc11 5467 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
Kojto 109:9296ab0bfc11 5468
Kojto 109:9296ab0bfc11 5469 /******************* Bit definition for TSC_IOHCR register ******************/
Kojto 109:9296ab0bfc11 5470 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5471 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5472 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5473 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5474 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5475 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5476 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5477 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5478 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5479 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5480 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5481 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5482 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5483 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5484 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5485 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5486 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5487 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5488 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5489 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5490 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5491 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5492 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5493 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5494 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5495 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5496 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5497 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5498 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5499 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5500 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5501 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
Kojto 109:9296ab0bfc11 5502
Kojto 109:9296ab0bfc11 5503 /******************* Bit definition for TSC_IOASCR register *****************/
Kojto 109:9296ab0bfc11 5504 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 5505 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 5506 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 5507 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 5508 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 5509 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 5510 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 5511 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 5512 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 5513 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 5514 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 5515 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 5516 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 5517 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 5518 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 5519 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 5520 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 5521 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 5522 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 5523 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 5524 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 5525 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 5526 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 5527 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 5528 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 5529 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 5530 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 5531 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 5532 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
Kojto 109:9296ab0bfc11 5533 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
Kojto 109:9296ab0bfc11 5534 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
Kojto 109:9296ab0bfc11 5535 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
Kojto 109:9296ab0bfc11 5536
Kojto 109:9296ab0bfc11 5537 /******************* Bit definition for TSC_IOSCR register ******************/
Kojto 109:9296ab0bfc11 5538 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
Kojto 109:9296ab0bfc11 5539 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
Kojto 109:9296ab0bfc11 5540 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
Kojto 109:9296ab0bfc11 5541 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
Kojto 109:9296ab0bfc11 5542 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
Kojto 109:9296ab0bfc11 5543 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
Kojto 109:9296ab0bfc11 5544 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
Kojto 109:9296ab0bfc11 5545 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
Kojto 109:9296ab0bfc11 5546 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
Kojto 109:9296ab0bfc11 5547 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
Kojto 109:9296ab0bfc11 5548 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
Kojto 109:9296ab0bfc11 5549 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
Kojto 109:9296ab0bfc11 5550 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
Kojto 109:9296ab0bfc11 5551 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
Kojto 109:9296ab0bfc11 5552 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
Kojto 109:9296ab0bfc11 5553 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
Kojto 109:9296ab0bfc11 5554 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
Kojto 109:9296ab0bfc11 5555 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
Kojto 109:9296ab0bfc11 5556 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
Kojto 109:9296ab0bfc11 5557 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
Kojto 109:9296ab0bfc11 5558 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
Kojto 109:9296ab0bfc11 5559 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
Kojto 109:9296ab0bfc11 5560 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
Kojto 109:9296ab0bfc11 5561 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
Kojto 109:9296ab0bfc11 5562 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
Kojto 109:9296ab0bfc11 5563 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
Kojto 109:9296ab0bfc11 5564 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
Kojto 109:9296ab0bfc11 5565 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
Kojto 109:9296ab0bfc11 5566 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
Kojto 109:9296ab0bfc11 5567 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
Kojto 109:9296ab0bfc11 5568 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
Kojto 109:9296ab0bfc11 5569 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
Kojto 109:9296ab0bfc11 5570
Kojto 109:9296ab0bfc11 5571 /******************* Bit definition for TSC_IOCCR register ******************/
Kojto 109:9296ab0bfc11 5572 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
Kojto 109:9296ab0bfc11 5573 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
Kojto 109:9296ab0bfc11 5574 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
Kojto 109:9296ab0bfc11 5575 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
Kojto 109:9296ab0bfc11 5576 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
Kojto 109:9296ab0bfc11 5577 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
Kojto 109:9296ab0bfc11 5578 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
Kojto 109:9296ab0bfc11 5579 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
Kojto 109:9296ab0bfc11 5580 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
Kojto 109:9296ab0bfc11 5581 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
Kojto 109:9296ab0bfc11 5582 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
Kojto 109:9296ab0bfc11 5583 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
Kojto 109:9296ab0bfc11 5584 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
Kojto 109:9296ab0bfc11 5585 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
Kojto 109:9296ab0bfc11 5586 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
Kojto 109:9296ab0bfc11 5587 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
Kojto 109:9296ab0bfc11 5588 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
Kojto 109:9296ab0bfc11 5589 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
Kojto 109:9296ab0bfc11 5590 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
Kojto 109:9296ab0bfc11 5591 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
Kojto 109:9296ab0bfc11 5592 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
Kojto 109:9296ab0bfc11 5593 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
Kojto 109:9296ab0bfc11 5594 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
Kojto 109:9296ab0bfc11 5595 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
Kojto 109:9296ab0bfc11 5596 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
Kojto 109:9296ab0bfc11 5597 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
Kojto 109:9296ab0bfc11 5598 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
Kojto 109:9296ab0bfc11 5599 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
Kojto 109:9296ab0bfc11 5600 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
Kojto 109:9296ab0bfc11 5601 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
Kojto 109:9296ab0bfc11 5602 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
Kojto 109:9296ab0bfc11 5603 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
Kojto 109:9296ab0bfc11 5604
Kojto 109:9296ab0bfc11 5605 /******************* Bit definition for TSC_IOGCSR register *****************/
Kojto 109:9296ab0bfc11 5606 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
Kojto 109:9296ab0bfc11 5607 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
Kojto 109:9296ab0bfc11 5608 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
Kojto 109:9296ab0bfc11 5609 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
Kojto 109:9296ab0bfc11 5610 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
Kojto 109:9296ab0bfc11 5611 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
Kojto 109:9296ab0bfc11 5612 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
Kojto 109:9296ab0bfc11 5613 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
Kojto 109:9296ab0bfc11 5614 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
Kojto 109:9296ab0bfc11 5615 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
Kojto 109:9296ab0bfc11 5616 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
Kojto 109:9296ab0bfc11 5617 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
Kojto 109:9296ab0bfc11 5618 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
Kojto 109:9296ab0bfc11 5619 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
Kojto 109:9296ab0bfc11 5620 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
Kojto 109:9296ab0bfc11 5621 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
Kojto 109:9296ab0bfc11 5622
Kojto 109:9296ab0bfc11 5623 /******************* Bit definition for TSC_IOGXCR register *****************/
Kojto 109:9296ab0bfc11 5624 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
Kojto 109:9296ab0bfc11 5625
Kojto 109:9296ab0bfc11 5626 /******************************************************************************/
Kojto 109:9296ab0bfc11 5627 /* */
Kojto 109:9296ab0bfc11 5628 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto 109:9296ab0bfc11 5629 /* */
Kojto 109:9296ab0bfc11 5630 /******************************************************************************/
Kojto 109:9296ab0bfc11 5631 /****************** Bit definition for USART_CR1 register *******************/
Kojto 109:9296ab0bfc11 5632 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
Kojto 109:9296ab0bfc11 5633 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
Kojto 109:9296ab0bfc11 5634 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
Kojto 109:9296ab0bfc11 5635 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
Kojto 109:9296ab0bfc11 5636 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
Kojto 109:9296ab0bfc11 5637 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
Kojto 109:9296ab0bfc11 5638 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
Kojto 109:9296ab0bfc11 5639 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
Kojto 109:9296ab0bfc11 5640 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
Kojto 109:9296ab0bfc11 5641 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
Kojto 109:9296ab0bfc11 5642 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
Kojto 109:9296ab0bfc11 5643 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
Kojto 109:9296ab0bfc11 5644 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
Kojto 109:9296ab0bfc11 5645 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
Kojto 109:9296ab0bfc11 5646 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
Kojto 109:9296ab0bfc11 5647 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
Kojto 109:9296ab0bfc11 5648 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
Kojto 109:9296ab0bfc11 5649 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 5650 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 5651 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 5652 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 5653 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 109:9296ab0bfc11 5654 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
Kojto 109:9296ab0bfc11 5655 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 5656 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 5657 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 5658 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 5659 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
Kojto 109:9296ab0bfc11 5660 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
Kojto 109:9296ab0bfc11 5661 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
Kojto 109:9296ab0bfc11 5662 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
Kojto 109:9296ab0bfc11 5663 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
Kojto 109:9296ab0bfc11 5664
Kojto 109:9296ab0bfc11 5665 /****************** Bit definition for USART_CR2 register *******************/
Kojto 109:9296ab0bfc11 5666 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
Kojto 109:9296ab0bfc11 5667 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
Kojto 109:9296ab0bfc11 5668 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
Kojto 109:9296ab0bfc11 5669 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
Kojto 109:9296ab0bfc11 5670 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
Kojto 109:9296ab0bfc11 5671 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
Kojto 109:9296ab0bfc11 5672 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
Kojto 109:9296ab0bfc11 5673 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
Kojto 109:9296ab0bfc11 5674 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 5675 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 5676 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
Kojto 109:9296ab0bfc11 5677 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
Kojto 109:9296ab0bfc11 5678 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
Kojto 109:9296ab0bfc11 5679 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
Kojto 109:9296ab0bfc11 5680 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
Kojto 109:9296ab0bfc11 5681 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
Kojto 109:9296ab0bfc11 5682 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
Kojto 109:9296ab0bfc11 5683 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
Kojto 109:9296ab0bfc11 5684 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 5685 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 5686 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
Kojto 109:9296ab0bfc11 5687 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
Kojto 109:9296ab0bfc11 5688
Kojto 109:9296ab0bfc11 5689 /****************** Bit definition for USART_CR3 register *******************/
Kojto 109:9296ab0bfc11 5690 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
Kojto 109:9296ab0bfc11 5691 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
Kojto 109:9296ab0bfc11 5692 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
Kojto 109:9296ab0bfc11 5693 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
Kojto 109:9296ab0bfc11 5694 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
Kojto 109:9296ab0bfc11 5695 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
Kojto 109:9296ab0bfc11 5696 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
Kojto 109:9296ab0bfc11 5697 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
Kojto 109:9296ab0bfc11 5698 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
Kojto 109:9296ab0bfc11 5699 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
Kojto 109:9296ab0bfc11 5700 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
Kojto 109:9296ab0bfc11 5701 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
Kojto 109:9296ab0bfc11 5702 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
Kojto 109:9296ab0bfc11 5703 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
Kojto 109:9296ab0bfc11 5704 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
Kojto 109:9296ab0bfc11 5705 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
Kojto 109:9296ab0bfc11 5706 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
Kojto 109:9296ab0bfc11 5707 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 5708 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 5709 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 5710 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
Kojto 109:9296ab0bfc11 5711 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 5712 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 5713 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
Kojto 109:9296ab0bfc11 5714
Kojto 109:9296ab0bfc11 5715 /****************** Bit definition for USART_BRR register *******************/
Kojto 109:9296ab0bfc11 5716 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
Kojto 109:9296ab0bfc11 5717 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
Kojto 109:9296ab0bfc11 5718
Kojto 109:9296ab0bfc11 5719 /****************** Bit definition for USART_GTPR register ******************/
Kojto 109:9296ab0bfc11 5720 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
Kojto 109:9296ab0bfc11 5721 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
Kojto 109:9296ab0bfc11 5722
Kojto 109:9296ab0bfc11 5723
Kojto 109:9296ab0bfc11 5724 /******************* Bit definition for USART_RTOR register *****************/
Kojto 109:9296ab0bfc11 5725 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
Kojto 109:9296ab0bfc11 5726 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
Kojto 109:9296ab0bfc11 5727
Kojto 109:9296ab0bfc11 5728 /******************* Bit definition for USART_RQR register ******************/
Kojto 109:9296ab0bfc11 5729 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
Kojto 109:9296ab0bfc11 5730 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
Kojto 109:9296ab0bfc11 5731 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
Kojto 109:9296ab0bfc11 5732 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
Kojto 109:9296ab0bfc11 5733 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
Kojto 109:9296ab0bfc11 5734
Kojto 109:9296ab0bfc11 5735 /******************* Bit definition for USART_ISR register ******************/
Kojto 109:9296ab0bfc11 5736 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
Kojto 109:9296ab0bfc11 5737 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
Kojto 109:9296ab0bfc11 5738 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
Kojto 109:9296ab0bfc11 5739 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
Kojto 109:9296ab0bfc11 5740 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
Kojto 109:9296ab0bfc11 5741 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
Kojto 109:9296ab0bfc11 5742 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
Kojto 109:9296ab0bfc11 5743 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
Kojto 109:9296ab0bfc11 5744 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
Kojto 109:9296ab0bfc11 5745 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
Kojto 109:9296ab0bfc11 5746 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
Kojto 109:9296ab0bfc11 5747 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
Kojto 109:9296ab0bfc11 5748 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
Kojto 109:9296ab0bfc11 5749 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
Kojto 109:9296ab0bfc11 5750 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
Kojto 109:9296ab0bfc11 5751 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
Kojto 109:9296ab0bfc11 5752 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
Kojto 109:9296ab0bfc11 5753 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
Kojto 109:9296ab0bfc11 5754 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
Kojto 109:9296ab0bfc11 5755 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
Kojto 109:9296ab0bfc11 5756 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
Kojto 109:9296ab0bfc11 5757 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
Kojto 109:9296ab0bfc11 5758
Kojto 109:9296ab0bfc11 5759 /******************* Bit definition for USART_ICR register ******************/
Kojto 109:9296ab0bfc11 5760 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
Kojto 109:9296ab0bfc11 5761 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
Kojto 109:9296ab0bfc11 5762 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
Kojto 109:9296ab0bfc11 5763 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
Kojto 109:9296ab0bfc11 5764 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
Kojto 109:9296ab0bfc11 5765 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
Kojto 109:9296ab0bfc11 5766 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
Kojto 109:9296ab0bfc11 5767 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
Kojto 109:9296ab0bfc11 5768 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
Kojto 109:9296ab0bfc11 5769 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
Kojto 109:9296ab0bfc11 5770 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
Kojto 109:9296ab0bfc11 5771 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
Kojto 109:9296ab0bfc11 5772
Kojto 109:9296ab0bfc11 5773 /******************* Bit definition for USART_RDR register ******************/
Kojto 109:9296ab0bfc11 5774 #define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
Kojto 109:9296ab0bfc11 5775
Kojto 109:9296ab0bfc11 5776 /******************* Bit definition for USART_TDR register ******************/
Kojto 109:9296ab0bfc11 5777 #define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
Kojto 109:9296ab0bfc11 5778
Kojto 109:9296ab0bfc11 5779 /******************************************************************************/
Kojto 109:9296ab0bfc11 5780 /* */
Kojto 109:9296ab0bfc11 5781 /* Window WATCHDOG */
Kojto 109:9296ab0bfc11 5782 /* */
Kojto 109:9296ab0bfc11 5783 /******************************************************************************/
Kojto 109:9296ab0bfc11 5784 /******************* Bit definition for WWDG_CR register ********************/
Kojto 109:9296ab0bfc11 5785 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 109:9296ab0bfc11 5786 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5787 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5788 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5789 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5790 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 5791 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 109:9296ab0bfc11 5792 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 109:9296ab0bfc11 5793
Kojto 109:9296ab0bfc11 5794 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */
Kojto 109:9296ab0bfc11 5795
Kojto 109:9296ab0bfc11 5796 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 109:9296ab0bfc11 5797 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */
Kojto 109:9296ab0bfc11 5798 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5799 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5800 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 5801 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 5802 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 5803 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 109:9296ab0bfc11 5804 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 109:9296ab0bfc11 5805
Kojto 109:9296ab0bfc11 5806 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 109:9296ab0bfc11 5807 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 5808 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 5809
Kojto 109:9296ab0bfc11 5810 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */
Kojto 109:9296ab0bfc11 5811
Kojto 109:9296ab0bfc11 5812 /******************* Bit definition for WWDG_SR register ********************/
Kojto 109:9296ab0bfc11 5813 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */
Kojto 109:9296ab0bfc11 5814
Kojto 109:9296ab0bfc11 5815 /**
Kojto 109:9296ab0bfc11 5816 * @}
Kojto 109:9296ab0bfc11 5817 */
Kojto 109:9296ab0bfc11 5818
Kojto 109:9296ab0bfc11 5819 /**
Kojto 109:9296ab0bfc11 5820 * @}
Kojto 109:9296ab0bfc11 5821 */
Kojto 109:9296ab0bfc11 5822
Kojto 109:9296ab0bfc11 5823 /** @addtogroup Exported_macros
Kojto 109:9296ab0bfc11 5824 * @{
Kojto 109:9296ab0bfc11 5825 */
Kojto 109:9296ab0bfc11 5826
Kojto 109:9296ab0bfc11 5827 /****************************** ADC Instances *********************************/
Kojto 109:9296ab0bfc11 5828 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
Kojto 109:9296ab0bfc11 5829 ((INSTANCE) == ADC2))
Kojto 109:9296ab0bfc11 5830
Kojto 109:9296ab0bfc11 5831 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
Kojto 109:9296ab0bfc11 5832
Kojto 109:9296ab0bfc11 5833 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON))
Kojto 109:9296ab0bfc11 5834
Kojto 109:9296ab0bfc11 5835 /****************************** CAN Instances *********************************/
Kojto 109:9296ab0bfc11 5836 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
Kojto 109:9296ab0bfc11 5837
Kojto 109:9296ab0bfc11 5838 /****************************** COMP Instances ********************************/
Kojto 109:9296ab0bfc11 5839 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
Kojto 109:9296ab0bfc11 5840 ((INSTANCE) == COMP4) || \
Kojto 109:9296ab0bfc11 5841 ((INSTANCE) == COMP6))
Kojto 109:9296ab0bfc11 5842
Kojto 109:9296ab0bfc11 5843 /******************** COMP Instances with switch on DAC1 Channel1 output ******/
Kojto 109:9296ab0bfc11 5844 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) (0)
Kojto 109:9296ab0bfc11 5845
Kojto 109:9296ab0bfc11 5846 /******************** COMP Instances with window mode capability **************/
Kojto 109:9296ab0bfc11 5847 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (0)
Kojto 109:9296ab0bfc11 5848
Kojto 109:9296ab0bfc11 5849 /****************************** CRC Instances *********************************/
Kojto 109:9296ab0bfc11 5850 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 109:9296ab0bfc11 5851
Kojto 109:9296ab0bfc11 5852 /****************************** DAC Instances *********************************/
Kojto 109:9296ab0bfc11 5853 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
Kojto 109:9296ab0bfc11 5854 ((INSTANCE) == DAC2))
Kojto 109:9296ab0bfc11 5855
Kojto 109:9296ab0bfc11 5856 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
Kojto 109:9296ab0bfc11 5857 ((((INSTANCE) == DAC1) && \
Kojto 109:9296ab0bfc11 5858 (((CHANNEL) == DAC_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 5859 ((CHANNEL) == DAC_CHANNEL_2))) \
Kojto 109:9296ab0bfc11 5860 || \
Kojto 109:9296ab0bfc11 5861 (((INSTANCE) == DAC2) && \
Kojto 109:9296ab0bfc11 5862 (((CHANNEL) == DAC_CHANNEL_1))))
Kojto 109:9296ab0bfc11 5863
Kojto 109:9296ab0bfc11 5864 /****************************** DMA Instances *********************************/
Kojto 109:9296ab0bfc11 5865 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 109:9296ab0bfc11 5866 ((INSTANCE) == DMA1_Channel2) || \
Kojto 109:9296ab0bfc11 5867 ((INSTANCE) == DMA1_Channel3) || \
Kojto 109:9296ab0bfc11 5868 ((INSTANCE) == DMA1_Channel4) || \
Kojto 109:9296ab0bfc11 5869 ((INSTANCE) == DMA1_Channel5) || \
Kojto 109:9296ab0bfc11 5870 ((INSTANCE) == DMA1_Channel6) || \
Kojto 109:9296ab0bfc11 5871 ((INSTANCE) == DMA1_Channel7))
Kojto 109:9296ab0bfc11 5872
Kojto 109:9296ab0bfc11 5873 /****************************** GPIO Instances ********************************/
Kojto 109:9296ab0bfc11 5874 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 109:9296ab0bfc11 5875 ((INSTANCE) == GPIOB) || \
Kojto 109:9296ab0bfc11 5876 ((INSTANCE) == GPIOC) || \
Kojto 109:9296ab0bfc11 5877 ((INSTANCE) == GPIOD) || \
Kojto 109:9296ab0bfc11 5878 ((INSTANCE) == GPIOF))
Kojto 109:9296ab0bfc11 5879
Kojto 109:9296ab0bfc11 5880 /****************************** I2C Instances *********************************/
Kojto 109:9296ab0bfc11 5881 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
Kojto 109:9296ab0bfc11 5882
Kojto 109:9296ab0bfc11 5883 /****************************** IWDG Instances ********************************/
Kojto 109:9296ab0bfc11 5884 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 109:9296ab0bfc11 5885
Kojto 109:9296ab0bfc11 5886 /****************************** OPAMP Instances *******************************/
Kojto 109:9296ab0bfc11 5887 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
Kojto 109:9296ab0bfc11 5888
Kojto 109:9296ab0bfc11 5889 /****************************** RTC Instances *********************************/
Kojto 109:9296ab0bfc11 5890 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 109:9296ab0bfc11 5891
Kojto 109:9296ab0bfc11 5892 /****************************** SMBUS Instances *******************************/
Kojto 109:9296ab0bfc11 5893 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
Kojto 109:9296ab0bfc11 5894
Kojto 109:9296ab0bfc11 5895 /****************************** SPI Instances *********************************/
Kojto 109:9296ab0bfc11 5896 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1))
Kojto 109:9296ab0bfc11 5897
Kojto 109:9296ab0bfc11 5898 /******************* TIM Instances : All supported instances ******************/
Kojto 109:9296ab0bfc11 5899 #define IS_TIM_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5900 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5901 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5902 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 5903 ((INSTANCE) == TIM6) || \
Kojto 109:9296ab0bfc11 5904 ((INSTANCE) == TIM7) || \
Kojto 109:9296ab0bfc11 5905 ((INSTANCE) == TIM15) || \
Kojto 109:9296ab0bfc11 5906 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 5907 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 5908
Kojto 109:9296ab0bfc11 5909 /******************* TIM Instances : at least 1 capture/compare channel *******/
Kojto 109:9296ab0bfc11 5910 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5911 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5912 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5913 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 5914 ((INSTANCE) == TIM15) || \
Kojto 109:9296ab0bfc11 5915 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 5916 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 5917
Kojto 109:9296ab0bfc11 5918 /****************** TIM Instances : at least 2 capture/compare channels *******/
Kojto 109:9296ab0bfc11 5919 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5920 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5921 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5922 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 5923 ((INSTANCE) == TIM15))
Kojto 109:9296ab0bfc11 5924
Kojto 109:9296ab0bfc11 5925 /****************** TIM Instances : at least 3 capture/compare channels *******/
Kojto 109:9296ab0bfc11 5926 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5927 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5928 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5929 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5930
Kojto 109:9296ab0bfc11 5931 /****************** TIM Instances : at least 4 capture/compare channels *******/
Kojto 109:9296ab0bfc11 5932 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5933 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5934 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5935 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5936
Kojto 109:9296ab0bfc11 5937 /****************** TIM Instances : at least 5 capture/compare channels *******/
Kojto 109:9296ab0bfc11 5938 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5939 (((INSTANCE) == TIM1))
Kojto 109:9296ab0bfc11 5940
Kojto 109:9296ab0bfc11 5941 /****************** TIM Instances : at least 6 capture/compare channels *******/
Kojto 109:9296ab0bfc11 5942 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5943 (((INSTANCE) == TIM1))
Kojto 109:9296ab0bfc11 5944
Kojto 109:9296ab0bfc11 5945 /************************** TIM Instances : Advanced-control timers ***********/
Kojto 109:9296ab0bfc11 5946
Kojto 109:9296ab0bfc11 5947 /****************** TIM Instances : supporting clock selection ****************/
Kojto 109:9296ab0bfc11 5948 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5949 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5950 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5951 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 5952 ((INSTANCE) == TIM15))
Kojto 109:9296ab0bfc11 5953
Kojto 109:9296ab0bfc11 5954 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
Kojto 109:9296ab0bfc11 5955 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5956 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5957 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5958 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5959
Kojto 109:9296ab0bfc11 5960 /****************** TIM Instances : supporting external clock mode 2 **********/
Kojto 109:9296ab0bfc11 5961 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5962 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5963 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5964 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5965
Kojto 109:9296ab0bfc11 5966 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
Kojto 109:9296ab0bfc11 5967 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5968 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5969 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5970 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 5971 ((INSTANCE) == TIM15))
Kojto 109:9296ab0bfc11 5972
Kojto 109:9296ab0bfc11 5973 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
Kojto 109:9296ab0bfc11 5974 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5975 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5976 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5977 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 5978 ((INSTANCE) == TIM15))
Kojto 109:9296ab0bfc11 5979
Kojto 109:9296ab0bfc11 5980 /****************** TIM Instances : supporting OCxREF clear *******************/
Kojto 109:9296ab0bfc11 5981 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5982 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5983 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5984 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5985
Kojto 109:9296ab0bfc11 5986 /****************** TIM Instances : supporting encoder interface **************/
Kojto 109:9296ab0bfc11 5987 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5988 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5989 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 5990 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 5991
Kojto 109:9296ab0bfc11 5992 /****************** TIM Instances : supporting Hall interface *****************/
Kojto 109:9296ab0bfc11 5993 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5994 (((INSTANCE) == TIM1))
Kojto 109:9296ab0bfc11 5995
Kojto 109:9296ab0bfc11 5996 /****************** TIM Instances : supporting input XOR function *************/
Kojto 109:9296ab0bfc11 5997 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 5998 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 5999 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 6000 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 6001 ((INSTANCE) == TIM15))
Kojto 109:9296ab0bfc11 6002
Kojto 109:9296ab0bfc11 6003 /****************** TIM Instances : supporting master mode ********************/
Kojto 109:9296ab0bfc11 6004 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6005 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 6006 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 6007 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 6008 ((INSTANCE) == TIM6) || \
Kojto 109:9296ab0bfc11 6009 ((INSTANCE) == TIM7) || \
Kojto 109:9296ab0bfc11 6010 ((INSTANCE) == TIM15))
Kojto 109:9296ab0bfc11 6011
Kojto 109:9296ab0bfc11 6012 /****************** TIM Instances : supporting slave mode *********************/
Kojto 109:9296ab0bfc11 6013 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6014 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 6015 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 6016 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 6017 ((INSTANCE) == TIM15))
Kojto 109:9296ab0bfc11 6018
Kojto 109:9296ab0bfc11 6019 /****************** TIM Instances : supporting synchronization ****************/
Kojto 109:9296ab0bfc11 6020 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6021 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 6022 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 6023 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 6024 ((INSTANCE) == TIM6) || \
Kojto 109:9296ab0bfc11 6025 ((INSTANCE) == TIM7) || \
Kojto 109:9296ab0bfc11 6026 ((INSTANCE) == TIM15))
Kojto 109:9296ab0bfc11 6027
Kojto 109:9296ab0bfc11 6028 /****************** TIM Instances : supporting 32 bits counter ****************/
Kojto 109:9296ab0bfc11 6029 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6030 ((INSTANCE) == TIM2)
Kojto 109:9296ab0bfc11 6031
Kojto 109:9296ab0bfc11 6032 /****************** TIM Instances : supporting DMA burst **********************/
Kojto 109:9296ab0bfc11 6033 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6034 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 6035 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 6036 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 6037 ((INSTANCE) == TIM15) || \
Kojto 109:9296ab0bfc11 6038 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 6039 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 6040
Kojto 109:9296ab0bfc11 6041 /****************** TIM Instances : supporting the break function *************/
Kojto 109:9296ab0bfc11 6042 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6043 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 6044 ((INSTANCE) == TIM15) || \
Kojto 109:9296ab0bfc11 6045 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 6046 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 6047
Kojto 109:9296ab0bfc11 6048 /****************** TIM Instances : supporting input/output channel(s) ********/
Kojto 109:9296ab0bfc11 6049 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 109:9296ab0bfc11 6050 ((((INSTANCE) == TIM1) && \
Kojto 109:9296ab0bfc11 6051 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 6052 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 109:9296ab0bfc11 6053 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 109:9296ab0bfc11 6054 ((CHANNEL) == TIM_CHANNEL_4) || \
Kojto 109:9296ab0bfc11 6055 ((CHANNEL) == TIM_CHANNEL_5) || \
Kojto 109:9296ab0bfc11 6056 ((CHANNEL) == TIM_CHANNEL_6))) \
Kojto 109:9296ab0bfc11 6057 || \
Kojto 109:9296ab0bfc11 6058 (((INSTANCE) == TIM2) && \
Kojto 109:9296ab0bfc11 6059 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 6060 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 109:9296ab0bfc11 6061 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 109:9296ab0bfc11 6062 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 109:9296ab0bfc11 6063 || \
Kojto 109:9296ab0bfc11 6064 (((INSTANCE) == TIM3) && \
Kojto 109:9296ab0bfc11 6065 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 6066 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 109:9296ab0bfc11 6067 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 109:9296ab0bfc11 6068 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 109:9296ab0bfc11 6069 || \
Kojto 109:9296ab0bfc11 6070 (((INSTANCE) == TIM15) && \
Kojto 109:9296ab0bfc11 6071 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 6072 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 109:9296ab0bfc11 6073 || \
Kojto 109:9296ab0bfc11 6074 (((INSTANCE) == TIM16) && \
Kojto 109:9296ab0bfc11 6075 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 109:9296ab0bfc11 6076 || \
Kojto 109:9296ab0bfc11 6077 (((INSTANCE) == TIM17) && \
Kojto 109:9296ab0bfc11 6078 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 109:9296ab0bfc11 6079
Kojto 109:9296ab0bfc11 6080 /****************** TIM Instances : supporting complementary output(s) ********/
Kojto 109:9296ab0bfc11 6081 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 109:9296ab0bfc11 6082 ((((INSTANCE) == TIM1) && \
Kojto 109:9296ab0bfc11 6083 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 6084 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 109:9296ab0bfc11 6085 ((CHANNEL) == TIM_CHANNEL_3))) \
Kojto 109:9296ab0bfc11 6086 || \
Kojto 109:9296ab0bfc11 6087 (((INSTANCE) == TIM15) && \
Kojto 109:9296ab0bfc11 6088 ((CHANNEL) == TIM_CHANNEL_1)) \
Kojto 109:9296ab0bfc11 6089 || \
Kojto 109:9296ab0bfc11 6090 (((INSTANCE) == TIM16) && \
Kojto 109:9296ab0bfc11 6091 ((CHANNEL) == TIM_CHANNEL_1)) \
Kojto 109:9296ab0bfc11 6092 || \
Kojto 109:9296ab0bfc11 6093 (((INSTANCE) == TIM17) && \
Kojto 109:9296ab0bfc11 6094 ((CHANNEL) == TIM_CHANNEL_1)))
Kojto 109:9296ab0bfc11 6095
Kojto 109:9296ab0bfc11 6096 /****************** TIM Instances : supporting counting mode selection ********/
Kojto 109:9296ab0bfc11 6097 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6098 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 6099 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 6100 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 6101
Kojto 109:9296ab0bfc11 6102 /****************** TIM Instances : supporting repetition counter *************/
Kojto 109:9296ab0bfc11 6103 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6104 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 6105 ((INSTANCE) == TIM15) || \
Kojto 109:9296ab0bfc11 6106 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 6107 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 6108
Kojto 109:9296ab0bfc11 6109 /****************** TIM Instances : supporting clock division *****************/
Kojto 109:9296ab0bfc11 6110 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6111 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 6112 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 6113 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 6114 ((INSTANCE) == TIM15) || \
Kojto 109:9296ab0bfc11 6115 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 6116 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 6117
Kojto 109:9296ab0bfc11 6118 /****************** TIM Instances : supporting 2 break inputs *****************/
Kojto 109:9296ab0bfc11 6119 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6120 (((INSTANCE) == TIM1))
Kojto 109:9296ab0bfc11 6121
Kojto 109:9296ab0bfc11 6122 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
Kojto 109:9296ab0bfc11 6123 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6124 (((INSTANCE) == TIM1))
Kojto 109:9296ab0bfc11 6125
Kojto 109:9296ab0bfc11 6126 /****************** TIM Instances : supporting DMA generation on Update events*/
Kojto 109:9296ab0bfc11 6127 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6128 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 6129 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 6130 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 6131 ((INSTANCE) == TIM6) || \
Kojto 109:9296ab0bfc11 6132 ((INSTANCE) == TIM7) || \
Kojto 109:9296ab0bfc11 6133 ((INSTANCE) == TIM15) || \
Kojto 109:9296ab0bfc11 6134 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 6135 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 6136
Kojto 109:9296ab0bfc11 6137 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
Kojto 109:9296ab0bfc11 6138 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6139 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 6140 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 6141 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 6142 ((INSTANCE) == TIM15) || \
Kojto 109:9296ab0bfc11 6143 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 6144 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 6145
Kojto 109:9296ab0bfc11 6146 /****************** TIM Instances : supporting commutation event generation ***/
Kojto 109:9296ab0bfc11 6147 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6148 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 6149 ((INSTANCE) == TIM15) || \
Kojto 109:9296ab0bfc11 6150 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 6151 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 6152
Kojto 109:9296ab0bfc11 6153 /****************** TIM Instances : supporting remapping capability ***********/
Kojto 109:9296ab0bfc11 6154 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 6155 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 6156 ((INSTANCE) == TIM16))
Kojto 109:9296ab0bfc11 6157
Kojto 109:9296ab0bfc11 6158 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
Kojto 109:9296ab0bfc11 6159 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
Kojto 109:9296ab0bfc11 6160 (((INSTANCE) == TIM1))
Kojto 109:9296ab0bfc11 6161
Kojto 109:9296ab0bfc11 6162 /****************************** TSC Instances *********************************/
Kojto 109:9296ab0bfc11 6163 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
Kojto 109:9296ab0bfc11 6164
Kojto 109:9296ab0bfc11 6165 /******************** USART Instances : Synchronous mode **********************/
Kojto 109:9296ab0bfc11 6166 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 109:9296ab0bfc11 6167 ((INSTANCE) == USART2) || \
Kojto 109:9296ab0bfc11 6168 ((INSTANCE) == USART3))
Kojto 109:9296ab0bfc11 6169
Kojto 109:9296ab0bfc11 6170 /****************** USART Instances : Auto Baud Rate detection ****************/
Kojto 109:9296ab0bfc11 6171 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 6172
Kojto 109:9296ab0bfc11 6173 /******************** UART Instances : Asynchronous mode **********************/
Kojto 109:9296ab0bfc11 6174 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 109:9296ab0bfc11 6175 ((INSTANCE) == USART2) || \
Kojto 109:9296ab0bfc11 6176 ((INSTANCE) == USART3))
Kojto 109:9296ab0bfc11 6177
Kojto 109:9296ab0bfc11 6178 /******************** UART Instances : Half-Duplex mode **********************/
Kojto 109:9296ab0bfc11 6179 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 109:9296ab0bfc11 6180 ((INSTANCE) == USART2) || \
Kojto 109:9296ab0bfc11 6181 ((INSTANCE) == USART3))
Kojto 109:9296ab0bfc11 6182
Kojto 109:9296ab0bfc11 6183 /******************** UART Instances : LIN mode **********************/
Kojto 109:9296ab0bfc11 6184 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 6185
Kojto 109:9296ab0bfc11 6186 /******************** UART Instances : Wake-up from Stop mode **********************/
Kojto 109:9296ab0bfc11 6187 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 6188
Kojto 109:9296ab0bfc11 6189 /****************** UART Instances : Hardware Flow control ********************/
Kojto 109:9296ab0bfc11 6190 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 109:9296ab0bfc11 6191 ((INSTANCE) == USART2) || \
Kojto 109:9296ab0bfc11 6192 ((INSTANCE) == USART3))
Kojto 109:9296ab0bfc11 6193
Kojto 109:9296ab0bfc11 6194 /****************** UART Instances : Auto Baud Rate detection *****************/
Kojto 109:9296ab0bfc11 6195 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 6196
Kojto 109:9296ab0bfc11 6197 /****************** UART Instances : Driver Enable ****************************/
Kojto 109:9296ab0bfc11 6198 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 109:9296ab0bfc11 6199 ((INSTANCE) == USART2) || \
Kojto 109:9296ab0bfc11 6200 ((INSTANCE) == USART3))
Kojto 109:9296ab0bfc11 6201
Kojto 109:9296ab0bfc11 6202 /********************* UART Instances : Smard card mode ***********************/
Kojto 109:9296ab0bfc11 6203 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 6204
Kojto 109:9296ab0bfc11 6205 /*********************** UART Instances : IRDA mode ***************************/
Kojto 109:9296ab0bfc11 6206 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 6207
Kojto 109:9296ab0bfc11 6208 /****************************** WWDG Instances ********************************/
Kojto 109:9296ab0bfc11 6209 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 109:9296ab0bfc11 6210
Kojto 109:9296ab0bfc11 6211 /**
Kojto 109:9296ab0bfc11 6212 * @}
Kojto 109:9296ab0bfc11 6213 */
Kojto 109:9296ab0bfc11 6214
Kojto 109:9296ab0bfc11 6215
Kojto 109:9296ab0bfc11 6216 /******************************************************************************/
Kojto 109:9296ab0bfc11 6217 /* For a painless codes migration between the STM32F3xx device product */
Kojto 109:9296ab0bfc11 6218 /* lines, the aliases defined below are put in place to overcome the */
Kojto 109:9296ab0bfc11 6219 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 109:9296ab0bfc11 6220 /* No need to update developed interrupt code when moving across */
Kojto 109:9296ab0bfc11 6221 /* product lines within the same STM32F3 Family */
Kojto 109:9296ab0bfc11 6222 /******************************************************************************/
Kojto 109:9296ab0bfc11 6223
Kojto 109:9296ab0bfc11 6224 /* Aliases for __IRQn */
Kojto 109:9296ab0bfc11 6225
Kojto 109:9296ab0bfc11 6226 #define ADC1_IRQn ADC1_2_IRQn
Kojto 109:9296ab0bfc11 6227 #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
Kojto 109:9296ab0bfc11 6228 #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
Kojto 109:9296ab0bfc11 6229 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn
Kojto 109:9296ab0bfc11 6230 #define TIM16_IRQn TIM1_UP_TIM16_IRQn
Kojto 109:9296ab0bfc11 6231 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
Kojto 109:9296ab0bfc11 6232 #define COMP_IRQn COMP2_IRQn
Kojto 109:9296ab0bfc11 6233 #define COMP1_2_3_IRQn COMP2_IRQn
Kojto 109:9296ab0bfc11 6234 #define COMP1_2_IRQn COMP2_IRQn
Kojto 109:9296ab0bfc11 6235 #define COMP4_5_6_IRQn COMP4_6_IRQn
Kojto 109:9296ab0bfc11 6236 #define TIM6_DAC_IRQn TIM6_DAC1_IRQn
Kojto 109:9296ab0bfc11 6237
Kojto 109:9296ab0bfc11 6238 /* Aliases for __IRQHandler */
Kojto 109:9296ab0bfc11 6239 #define ADC1_IRQHandler ADC1_2_IRQHandler
Kojto 109:9296ab0bfc11 6240 #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
Kojto 109:9296ab0bfc11 6241 #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
Kojto 109:9296ab0bfc11 6242 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
Kojto 109:9296ab0bfc11 6243 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
Kojto 109:9296ab0bfc11 6244 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
Kojto 109:9296ab0bfc11 6245 #define COMP_IRQHandler COMP2_IRQHandler
Kojto 109:9296ab0bfc11 6246 #define COMP1_2_3_IRQHandler COMP2_IRQHandler
Kojto 109:9296ab0bfc11 6247 #define COMP1_2_IRQHandler COMP2_IRQHandler
Kojto 109:9296ab0bfc11 6248 #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
Kojto 109:9296ab0bfc11 6249 #define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
Kojto 109:9296ab0bfc11 6250
Kojto 109:9296ab0bfc11 6251 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 6252 }
Kojto 109:9296ab0bfc11 6253 #endif /* __cplusplus */
Kojto 109:9296ab0bfc11 6254
Kojto 109:9296ab0bfc11 6255 #endif /* __STM32F303x8_H */
Kojto 109:9296ab0bfc11 6256
Kojto 109:9296ab0bfc11 6257 /**
Kojto 109:9296ab0bfc11 6258 * @}
Kojto 109:9296ab0bfc11 6259 */
Kojto 109:9296ab0bfc11 6260
Kojto 109:9296ab0bfc11 6261 /**
Kojto 109:9296ab0bfc11 6262 * @}
Kojto 109:9296ab0bfc11 6263 */
Kojto 109:9296ab0bfc11 6264
Kojto 109:9296ab0bfc11 6265 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/