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TARGET_NUCLEO_F334R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_tim.h@143:86740a56073b, 2017-05-26 (annotated)
- Committer:
- AnnaBridge
- Date:
- Fri May 26 12:30:20 2017 +0100
- Revision:
- 143:86740a56073b
- Parent:
- 135:176b8275d35d
- Child:
- 168:b9e159c1930a
Release 143 of the mbed library.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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<> | 135:176b8275d35d | 1 | /** |
<> | 135:176b8275d35d | 2 | ****************************************************************************** |
<> | 135:176b8275d35d | 3 | * @file stm32f3xx_ll_tim.h |
<> | 135:176b8275d35d | 4 | * @author MCD Application Team |
<> | 135:176b8275d35d | 5 | * @version V1.4.0 |
<> | 135:176b8275d35d | 6 | * @date 16-December-2016 |
<> | 135:176b8275d35d | 7 | * @brief Header file of TIM LL module. |
<> | 135:176b8275d35d | 8 | ****************************************************************************** |
<> | 135:176b8275d35d | 9 | * @attention |
<> | 135:176b8275d35d | 10 | * |
<> | 135:176b8275d35d | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 135:176b8275d35d | 12 | * |
<> | 135:176b8275d35d | 13 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 135:176b8275d35d | 14 | * are permitted provided that the following conditions are met: |
<> | 135:176b8275d35d | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 135:176b8275d35d | 16 | * this list of conditions and the following disclaimer. |
<> | 135:176b8275d35d | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 135:176b8275d35d | 18 | * this list of conditions and the following disclaimer in the documentation |
<> | 135:176b8275d35d | 19 | * and/or other materials provided with the distribution. |
<> | 135:176b8275d35d | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 135:176b8275d35d | 21 | * may be used to endorse or promote products derived from this software |
<> | 135:176b8275d35d | 22 | * without specific prior written permission. |
<> | 135:176b8275d35d | 23 | * |
<> | 135:176b8275d35d | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 135:176b8275d35d | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 135:176b8275d35d | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 135:176b8275d35d | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 135:176b8275d35d | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 135:176b8275d35d | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 135:176b8275d35d | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 135:176b8275d35d | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 135:176b8275d35d | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 135:176b8275d35d | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 135:176b8275d35d | 34 | * |
<> | 135:176b8275d35d | 35 | ****************************************************************************** |
<> | 135:176b8275d35d | 36 | */ |
<> | 135:176b8275d35d | 37 | |
<> | 135:176b8275d35d | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 135:176b8275d35d | 39 | #ifndef __STM32F3xx_LL_TIM_H |
<> | 135:176b8275d35d | 40 | #define __STM32F3xx_LL_TIM_H |
<> | 135:176b8275d35d | 41 | |
<> | 135:176b8275d35d | 42 | #ifdef __cplusplus |
<> | 135:176b8275d35d | 43 | extern "C" { |
<> | 135:176b8275d35d | 44 | #endif |
<> | 135:176b8275d35d | 45 | |
<> | 135:176b8275d35d | 46 | /* Includes ------------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 47 | #include "stm32f3xx.h" |
<> | 135:176b8275d35d | 48 | |
<> | 135:176b8275d35d | 49 | /** @addtogroup STM32F3xx_LL_Driver |
<> | 135:176b8275d35d | 50 | * @{ |
<> | 135:176b8275d35d | 51 | */ |
<> | 135:176b8275d35d | 52 | |
<> | 135:176b8275d35d | 53 | #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20) |
<> | 135:176b8275d35d | 54 | |
<> | 135:176b8275d35d | 55 | /** @defgroup TIM_LL TIM |
<> | 135:176b8275d35d | 56 | * @{ |
<> | 135:176b8275d35d | 57 | */ |
<> | 135:176b8275d35d | 58 | |
<> | 135:176b8275d35d | 59 | /* Private types -------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 60 | /* Private variables ---------------------------------------------------------*/ |
<> | 135:176b8275d35d | 61 | /** @defgroup TIM_LL_Private_Variables TIM Private Variables |
<> | 135:176b8275d35d | 62 | * @{ |
<> | 135:176b8275d35d | 63 | */ |
<> | 135:176b8275d35d | 64 | static const uint8_t OFFSET_TAB_CCMRx[] = |
<> | 135:176b8275d35d | 65 | { |
<> | 135:176b8275d35d | 66 | 0x00U, /* 0: TIMx_CH1 */ |
<> | 135:176b8275d35d | 67 | 0x00U, /* 1: TIMx_CH1N */ |
<> | 135:176b8275d35d | 68 | 0x00U, /* 2: TIMx_CH2 */ |
<> | 135:176b8275d35d | 69 | 0x00U, /* 3: TIMx_CH2N */ |
<> | 135:176b8275d35d | 70 | 0x04U, /* 4: TIMx_CH3 */ |
<> | 135:176b8275d35d | 71 | 0x04U, /* 5: TIMx_CH3N */ |
<> | 135:176b8275d35d | 72 | 0x04U, /* 6: TIMx_CH4 */ |
<> | 135:176b8275d35d | 73 | 0x3CU, /* 7: TIMx_CH5 */ |
<> | 135:176b8275d35d | 74 | 0x3CU /* 8: TIMx_CH6 */ |
<> | 135:176b8275d35d | 75 | }; |
<> | 135:176b8275d35d | 76 | |
<> | 135:176b8275d35d | 77 | static const uint8_t SHIFT_TAB_OCxx[] = |
<> | 135:176b8275d35d | 78 | { |
<> | 135:176b8275d35d | 79 | 0U, /* 0: OC1M, OC1FE, OC1PE */ |
<> | 135:176b8275d35d | 80 | 0U, /* 1: - NA */ |
<> | 135:176b8275d35d | 81 | 8U, /* 2: OC2M, OC2FE, OC2PE */ |
<> | 135:176b8275d35d | 82 | 0U, /* 3: - NA */ |
<> | 135:176b8275d35d | 83 | 0U, /* 4: OC3M, OC3FE, OC3PE */ |
<> | 135:176b8275d35d | 84 | 0U, /* 5: - NA */ |
<> | 135:176b8275d35d | 85 | 8U, /* 6: OC4M, OC4FE, OC4PE */ |
<> | 135:176b8275d35d | 86 | 0U, /* 7: OC5M, OC5FE, OC5PE */ |
<> | 135:176b8275d35d | 87 | 8U /* 8: OC6M, OC6FE, OC6PE */ |
<> | 135:176b8275d35d | 88 | }; |
<> | 135:176b8275d35d | 89 | |
<> | 135:176b8275d35d | 90 | static const uint8_t SHIFT_TAB_ICxx[] = |
<> | 135:176b8275d35d | 91 | { |
<> | 135:176b8275d35d | 92 | 0U, /* 0: CC1S, IC1PSC, IC1F */ |
<> | 135:176b8275d35d | 93 | 0U, /* 1: - NA */ |
<> | 135:176b8275d35d | 94 | 8U, /* 2: CC2S, IC2PSC, IC2F */ |
<> | 135:176b8275d35d | 95 | 0U, /* 3: - NA */ |
<> | 135:176b8275d35d | 96 | 0U, /* 4: CC3S, IC3PSC, IC3F */ |
<> | 135:176b8275d35d | 97 | 0U, /* 5: - NA */ |
<> | 135:176b8275d35d | 98 | 8U, /* 6: CC4S, IC4PSC, IC4F */ |
<> | 135:176b8275d35d | 99 | 0U, /* 7: - NA */ |
<> | 135:176b8275d35d | 100 | 0U /* 8: - NA */ |
<> | 135:176b8275d35d | 101 | }; |
<> | 135:176b8275d35d | 102 | |
<> | 135:176b8275d35d | 103 | static const uint8_t SHIFT_TAB_CCxP[] = |
<> | 135:176b8275d35d | 104 | { |
<> | 135:176b8275d35d | 105 | 0U, /* 0: CC1P */ |
<> | 135:176b8275d35d | 106 | 2U, /* 1: CC1NP */ |
<> | 135:176b8275d35d | 107 | 4U, /* 2: CC2P */ |
<> | 135:176b8275d35d | 108 | 6U, /* 3: CC2NP */ |
<> | 135:176b8275d35d | 109 | 8U, /* 4: CC3P */ |
<> | 135:176b8275d35d | 110 | 10U, /* 5: CC3NP */ |
<> | 135:176b8275d35d | 111 | 12U, /* 6: CC4P */ |
<> | 135:176b8275d35d | 112 | 16U, /* 7: CC5P */ |
<> | 135:176b8275d35d | 113 | 20U /* 8: CC6P */ |
<> | 135:176b8275d35d | 114 | }; |
<> | 135:176b8275d35d | 115 | |
<> | 135:176b8275d35d | 116 | static const uint8_t SHIFT_TAB_OISx[] = |
<> | 135:176b8275d35d | 117 | { |
<> | 135:176b8275d35d | 118 | 0U, /* 0: OIS1 */ |
<> | 135:176b8275d35d | 119 | 1U, /* 1: OIS1N */ |
<> | 135:176b8275d35d | 120 | 2U, /* 2: OIS2 */ |
<> | 135:176b8275d35d | 121 | 3U, /* 3: OIS2N */ |
<> | 135:176b8275d35d | 122 | 4U, /* 4: OIS3 */ |
<> | 135:176b8275d35d | 123 | 5U, /* 5: OIS3N */ |
<> | 135:176b8275d35d | 124 | 6U, /* 6: OIS4 */ |
<> | 135:176b8275d35d | 125 | 8U, /* 7: OIS5 */ |
<> | 135:176b8275d35d | 126 | 10U /* 8: OIS6 */ |
<> | 135:176b8275d35d | 127 | }; |
<> | 135:176b8275d35d | 128 | /** |
<> | 135:176b8275d35d | 129 | * @} |
<> | 135:176b8275d35d | 130 | */ |
<> | 135:176b8275d35d | 131 | |
<> | 135:176b8275d35d | 132 | |
<> | 135:176b8275d35d | 133 | /* Private constants ---------------------------------------------------------*/ |
<> | 135:176b8275d35d | 134 | /** @defgroup TIM_LL_Private_Constants TIM Private Constants |
<> | 135:176b8275d35d | 135 | * @{ |
<> | 135:176b8275d35d | 136 | */ |
<> | 135:176b8275d35d | 137 | |
<> | 135:176b8275d35d | 138 | |
<> | 135:176b8275d35d | 139 | #define TIMx_OR_RMP_SHIFT (16U) |
<> | 135:176b8275d35d | 140 | #define TIMx_OR_RMP_MASK (0x0000FFFFU) |
<> | 135:176b8275d35d | 141 | #if defined(TIM1) |
<> | 135:176b8275d35d | 142 | #define TIM1_OR_RMP_MASK ((uint32_t)(TIM1_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)) |
<> | 135:176b8275d35d | 143 | #endif /* TIM1 */ |
<> | 135:176b8275d35d | 144 | #if defined (TIM8) |
<> | 135:176b8275d35d | 145 | #define TIM8_OR_RMP_MASK ((uint32_t)(TIM8_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)) |
<> | 135:176b8275d35d | 146 | #endif /* TIM8 */ |
<> | 135:176b8275d35d | 147 | #if defined(TIM14) |
<> | 135:176b8275d35d | 148 | #define TIM14_OR_RMP_MASK ((uint32_t)(TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)) |
<> | 135:176b8275d35d | 149 | #endif /* TIM14 */ |
<> | 135:176b8275d35d | 150 | #if defined(TIM16) |
<> | 135:176b8275d35d | 151 | #define TIM16_OR_RMP_MASK ((uint32_t)(TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)) |
<> | 135:176b8275d35d | 152 | #endif /* TIM16 */ |
<> | 135:176b8275d35d | 153 | #if defined(TIM20) |
<> | 135:176b8275d35d | 154 | #define TIM20_OR_RMP_MASK ((uint32_t)(TIM20_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)) |
<> | 135:176b8275d35d | 155 | #endif /* TIM20 */ |
<> | 135:176b8275d35d | 156 | |
<> | 135:176b8275d35d | 157 | /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ |
<> | 135:176b8275d35d | 158 | #define DT_DELAY_1 ((uint8_t)0x7FU) |
<> | 135:176b8275d35d | 159 | #define DT_DELAY_2 ((uint8_t)0x3FU) |
<> | 135:176b8275d35d | 160 | #define DT_DELAY_3 ((uint8_t)0x1FU) |
<> | 135:176b8275d35d | 161 | #define DT_DELAY_4 ((uint8_t)0x1FU) |
<> | 135:176b8275d35d | 162 | |
<> | 135:176b8275d35d | 163 | /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ |
<> | 135:176b8275d35d | 164 | #define DT_RANGE_1 ((uint8_t)0x00U) |
<> | 135:176b8275d35d | 165 | #define DT_RANGE_2 ((uint8_t)0x80U) |
<> | 135:176b8275d35d | 166 | #define DT_RANGE_3 ((uint8_t)0xC0U) |
<> | 135:176b8275d35d | 167 | #define DT_RANGE_4 ((uint8_t)0xE0U) |
<> | 135:176b8275d35d | 168 | |
<> | 135:176b8275d35d | 169 | |
<> | 135:176b8275d35d | 170 | /** |
<> | 135:176b8275d35d | 171 | * @} |
<> | 135:176b8275d35d | 172 | */ |
<> | 135:176b8275d35d | 173 | |
<> | 135:176b8275d35d | 174 | |
<> | 135:176b8275d35d | 175 | /* Private macros ------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 176 | /** @defgroup TIM_LL_Private_Macros TIM Private Macros |
<> | 135:176b8275d35d | 177 | * @{ |
<> | 135:176b8275d35d | 178 | */ |
<> | 135:176b8275d35d | 179 | /** @brief Convert channel id into channel index. |
<> | 135:176b8275d35d | 180 | * @param __CHANNEL__ This parameter can be one of the following values: |
<> | 135:176b8275d35d | 181 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 182 | * @arg @ref LL_TIM_CHANNEL_CH1N |
<> | 135:176b8275d35d | 183 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 184 | * @arg @ref LL_TIM_CHANNEL_CH2N |
<> | 135:176b8275d35d | 185 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 186 | * @arg @ref LL_TIM_CHANNEL_CH3N |
<> | 135:176b8275d35d | 187 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 188 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 189 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 190 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 191 | * @retval none |
<> | 135:176b8275d35d | 192 | */ |
<> | 135:176b8275d35d | 193 | #if defined(TIM_CCR5_CCR5) |
<> | 135:176b8275d35d | 194 | #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ |
<> | 135:176b8275d35d | 195 | (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ |
<> | 135:176b8275d35d | 196 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ |
<> | 135:176b8275d35d | 197 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ |
<> | 135:176b8275d35d | 198 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ |
<> | 135:176b8275d35d | 199 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ |
<> | 135:176b8275d35d | 200 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ |
<> | 135:176b8275d35d | 201 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ |
<> | 135:176b8275d35d | 202 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) |
<> | 135:176b8275d35d | 203 | #else |
<> | 135:176b8275d35d | 204 | #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ |
<> | 135:176b8275d35d | 205 | (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ |
<> | 135:176b8275d35d | 206 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ |
<> | 135:176b8275d35d | 207 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ |
<> | 135:176b8275d35d | 208 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ |
<> | 135:176b8275d35d | 209 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ |
<> | 135:176b8275d35d | 210 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U) |
<> | 135:176b8275d35d | 211 | #endif |
<> | 135:176b8275d35d | 212 | |
<> | 135:176b8275d35d | 213 | /** @brief Calculate the deadtime sampling period(in ps). |
<> | 135:176b8275d35d | 214 | * @param __TIMCLK__ timer input clock frequency (in Hz). |
<> | 135:176b8275d35d | 215 | * @param __CKD__ This parameter can be one of the following values: |
<> | 135:176b8275d35d | 216 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
<> | 135:176b8275d35d | 217 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
<> | 135:176b8275d35d | 218 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
<> | 135:176b8275d35d | 219 | * @retval none |
<> | 135:176b8275d35d | 220 | */ |
<> | 135:176b8275d35d | 221 | #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ |
<> | 135:176b8275d35d | 222 | (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ |
<> | 135:176b8275d35d | 223 | ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ |
<> | 135:176b8275d35d | 224 | ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) |
<> | 135:176b8275d35d | 225 | /** |
<> | 135:176b8275d35d | 226 | * @} |
<> | 135:176b8275d35d | 227 | */ |
<> | 135:176b8275d35d | 228 | |
<> | 135:176b8275d35d | 229 | |
<> | 135:176b8275d35d | 230 | /* Exported types ------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 231 | #if defined(USE_FULL_LL_DRIVER) |
<> | 135:176b8275d35d | 232 | /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure |
<> | 135:176b8275d35d | 233 | * @{ |
<> | 135:176b8275d35d | 234 | */ |
<> | 135:176b8275d35d | 235 | |
<> | 135:176b8275d35d | 236 | /** |
<> | 135:176b8275d35d | 237 | * @brief TIM Time Base configuration structure definition. |
<> | 135:176b8275d35d | 238 | */ |
<> | 135:176b8275d35d | 239 | typedef struct |
<> | 135:176b8275d35d | 240 | { |
<> | 135:176b8275d35d | 241 | uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
<> | 135:176b8275d35d | 242 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
<> | 135:176b8275d35d | 243 | |
<> | 135:176b8275d35d | 244 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ |
<> | 135:176b8275d35d | 245 | |
<> | 135:176b8275d35d | 246 | uint32_t CounterMode; /*!< Specifies the counter mode. |
<> | 135:176b8275d35d | 247 | This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. |
<> | 135:176b8275d35d | 248 | |
<> | 135:176b8275d35d | 249 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ |
<> | 135:176b8275d35d | 250 | |
<> | 135:176b8275d35d | 251 | uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active |
<> | 135:176b8275d35d | 252 | Auto-Reload Register at the next update event. |
<> | 135:176b8275d35d | 253 | This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
<> | 135:176b8275d35d | 254 | Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. |
<> | 135:176b8275d35d | 255 | |
<> | 135:176b8275d35d | 256 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ |
<> | 135:176b8275d35d | 257 | |
<> | 135:176b8275d35d | 258 | uint32_t ClockDivision; /*!< Specifies the clock division. |
<> | 135:176b8275d35d | 259 | This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. |
<> | 135:176b8275d35d | 260 | |
<> | 135:176b8275d35d | 261 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ |
<> | 135:176b8275d35d | 262 | |
<> | 135:176b8275d35d | 263 | uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
<> | 135:176b8275d35d | 264 | reaches zero, an update event is generated and counting restarts |
<> | 135:176b8275d35d | 265 | from the RCR value (N). |
<> | 135:176b8275d35d | 266 | This means in PWM mode that (N+1) corresponds to: |
<> | 135:176b8275d35d | 267 | - the number of PWM periods in edge-aligned mode |
<> | 135:176b8275d35d | 268 | - the number of half PWM period in center-aligned mode |
<> | 135:176b8275d35d | 269 | This parameter must be a number between 0x00 and 0xFF. |
<> | 135:176b8275d35d | 270 | |
<> | 135:176b8275d35d | 271 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ |
<> | 135:176b8275d35d | 272 | } LL_TIM_InitTypeDef; |
<> | 135:176b8275d35d | 273 | |
<> | 135:176b8275d35d | 274 | /** |
<> | 135:176b8275d35d | 275 | * @brief TIM Output Compare configuration structure definition. |
<> | 135:176b8275d35d | 276 | */ |
<> | 135:176b8275d35d | 277 | typedef struct |
<> | 135:176b8275d35d | 278 | { |
<> | 135:176b8275d35d | 279 | uint32_t OCMode; /*!< Specifies the output mode. |
<> | 135:176b8275d35d | 280 | This parameter can be a value of @ref TIM_LL_EC_OCMODE. |
<> | 135:176b8275d35d | 281 | |
<> | 135:176b8275d35d | 282 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ |
<> | 135:176b8275d35d | 283 | |
<> | 135:176b8275d35d | 284 | uint32_t OCState; /*!< Specifies the TIM Output Compare state. |
<> | 135:176b8275d35d | 285 | This parameter can be a value of @ref TIM_LL_EC_OCSTATE. |
<> | 135:176b8275d35d | 286 | |
<> | 135:176b8275d35d | 287 | This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ |
<> | 135:176b8275d35d | 288 | |
<> | 135:176b8275d35d | 289 | uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. |
<> | 135:176b8275d35d | 290 | This parameter can be a value of @ref TIM_LL_EC_OCSTATE. |
<> | 135:176b8275d35d | 291 | |
<> | 135:176b8275d35d | 292 | This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ |
<> | 135:176b8275d35d | 293 | |
<> | 135:176b8275d35d | 294 | uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. |
<> | 135:176b8275d35d | 295 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
<> | 135:176b8275d35d | 296 | |
<> | 135:176b8275d35d | 297 | This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ |
<> | 135:176b8275d35d | 298 | |
<> | 135:176b8275d35d | 299 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
<> | 135:176b8275d35d | 300 | This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. |
<> | 135:176b8275d35d | 301 | |
<> | 135:176b8275d35d | 302 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ |
<> | 135:176b8275d35d | 303 | |
<> | 135:176b8275d35d | 304 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
<> | 135:176b8275d35d | 305 | This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. |
<> | 135:176b8275d35d | 306 | |
<> | 135:176b8275d35d | 307 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ |
<> | 135:176b8275d35d | 308 | |
<> | 135:176b8275d35d | 309 | |
<> | 135:176b8275d35d | 310 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
<> | 135:176b8275d35d | 311 | This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. |
<> | 135:176b8275d35d | 312 | |
<> | 135:176b8275d35d | 313 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ |
<> | 135:176b8275d35d | 314 | |
<> | 135:176b8275d35d | 315 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
<> | 135:176b8275d35d | 316 | This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. |
<> | 135:176b8275d35d | 317 | |
<> | 135:176b8275d35d | 318 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ |
<> | 135:176b8275d35d | 319 | } LL_TIM_OC_InitTypeDef; |
<> | 135:176b8275d35d | 320 | |
<> | 135:176b8275d35d | 321 | /** |
<> | 135:176b8275d35d | 322 | * @brief TIM Input Capture configuration structure definition. |
<> | 135:176b8275d35d | 323 | */ |
<> | 135:176b8275d35d | 324 | |
<> | 135:176b8275d35d | 325 | typedef struct |
<> | 135:176b8275d35d | 326 | { |
<> | 135:176b8275d35d | 327 | |
<> | 135:176b8275d35d | 328 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
<> | 135:176b8275d35d | 329 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
<> | 135:176b8275d35d | 330 | |
<> | 135:176b8275d35d | 331 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
<> | 135:176b8275d35d | 332 | |
<> | 135:176b8275d35d | 333 | uint32_t ICActiveInput; /*!< Specifies the input. |
<> | 135:176b8275d35d | 334 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
<> | 135:176b8275d35d | 335 | |
<> | 135:176b8275d35d | 336 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ |
<> | 135:176b8275d35d | 337 | |
<> | 135:176b8275d35d | 338 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
<> | 135:176b8275d35d | 339 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
<> | 135:176b8275d35d | 340 | |
<> | 135:176b8275d35d | 341 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
<> | 135:176b8275d35d | 342 | |
<> | 135:176b8275d35d | 343 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
<> | 135:176b8275d35d | 344 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
<> | 135:176b8275d35d | 345 | |
<> | 135:176b8275d35d | 346 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
<> | 135:176b8275d35d | 347 | } LL_TIM_IC_InitTypeDef; |
<> | 135:176b8275d35d | 348 | |
<> | 135:176b8275d35d | 349 | |
<> | 135:176b8275d35d | 350 | /** |
<> | 135:176b8275d35d | 351 | * @brief TIM Encoder interface configuration structure definition. |
<> | 135:176b8275d35d | 352 | */ |
<> | 135:176b8275d35d | 353 | typedef struct |
<> | 135:176b8275d35d | 354 | { |
<> | 135:176b8275d35d | 355 | uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). |
<> | 135:176b8275d35d | 356 | This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. |
<> | 135:176b8275d35d | 357 | |
<> | 135:176b8275d35d | 358 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ |
<> | 135:176b8275d35d | 359 | |
<> | 135:176b8275d35d | 360 | uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. |
<> | 135:176b8275d35d | 361 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
<> | 135:176b8275d35d | 362 | |
<> | 135:176b8275d35d | 363 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
<> | 135:176b8275d35d | 364 | |
<> | 135:176b8275d35d | 365 | uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source |
<> | 135:176b8275d35d | 366 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
<> | 135:176b8275d35d | 367 | |
<> | 135:176b8275d35d | 368 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ |
<> | 135:176b8275d35d | 369 | |
<> | 135:176b8275d35d | 370 | uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. |
<> | 135:176b8275d35d | 371 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
<> | 135:176b8275d35d | 372 | |
<> | 135:176b8275d35d | 373 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
<> | 135:176b8275d35d | 374 | |
<> | 135:176b8275d35d | 375 | uint32_t IC1Filter; /*!< Specifies the TI1 input filter. |
<> | 135:176b8275d35d | 376 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
<> | 135:176b8275d35d | 377 | |
<> | 135:176b8275d35d | 378 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
<> | 135:176b8275d35d | 379 | |
<> | 135:176b8275d35d | 380 | uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. |
<> | 135:176b8275d35d | 381 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
<> | 135:176b8275d35d | 382 | |
<> | 135:176b8275d35d | 383 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
<> | 135:176b8275d35d | 384 | |
<> | 135:176b8275d35d | 385 | uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source |
<> | 135:176b8275d35d | 386 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
<> | 135:176b8275d35d | 387 | |
<> | 135:176b8275d35d | 388 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ |
<> | 135:176b8275d35d | 389 | |
<> | 135:176b8275d35d | 390 | uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. |
<> | 135:176b8275d35d | 391 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
<> | 135:176b8275d35d | 392 | |
<> | 135:176b8275d35d | 393 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
<> | 135:176b8275d35d | 394 | |
<> | 135:176b8275d35d | 395 | uint32_t IC2Filter; /*!< Specifies the TI2 input filter. |
<> | 135:176b8275d35d | 396 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
<> | 135:176b8275d35d | 397 | |
<> | 135:176b8275d35d | 398 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
<> | 135:176b8275d35d | 399 | |
<> | 135:176b8275d35d | 400 | } LL_TIM_ENCODER_InitTypeDef; |
<> | 135:176b8275d35d | 401 | |
<> | 135:176b8275d35d | 402 | /** |
<> | 135:176b8275d35d | 403 | * @brief TIM Hall sensor interface configuration structure definition. |
<> | 135:176b8275d35d | 404 | */ |
<> | 135:176b8275d35d | 405 | typedef struct |
<> | 135:176b8275d35d | 406 | { |
<> | 135:176b8275d35d | 407 | |
<> | 135:176b8275d35d | 408 | uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. |
<> | 135:176b8275d35d | 409 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
<> | 135:176b8275d35d | 410 | |
<> | 135:176b8275d35d | 411 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
<> | 135:176b8275d35d | 412 | |
<> | 135:176b8275d35d | 413 | uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. |
<> | 135:176b8275d35d | 414 | Prescaler must be set to get a maximum counter period longer than the |
<> | 135:176b8275d35d | 415 | time interval between 2 consecutive changes on the Hall inputs. |
<> | 135:176b8275d35d | 416 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
<> | 135:176b8275d35d | 417 | |
<> | 135:176b8275d35d | 418 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
<> | 135:176b8275d35d | 419 | |
<> | 135:176b8275d35d | 420 | uint32_t IC1Filter; /*!< Specifies the TI1 input filter. |
<> | 135:176b8275d35d | 421 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
<> | 135:176b8275d35d | 422 | |
<> | 135:176b8275d35d | 423 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
<> | 135:176b8275d35d | 424 | |
<> | 135:176b8275d35d | 425 | uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. |
<> | 135:176b8275d35d | 426 | A positive pulse (TRGO event) is generated with a programmable delay every time |
<> | 135:176b8275d35d | 427 | a change occurs on the Hall inputs. |
<> | 135:176b8275d35d | 428 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. |
<> | 135:176b8275d35d | 429 | |
<> | 135:176b8275d35d | 430 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ |
<> | 135:176b8275d35d | 431 | } LL_TIM_HALLSENSOR_InitTypeDef; |
<> | 135:176b8275d35d | 432 | |
<> | 135:176b8275d35d | 433 | /** |
<> | 135:176b8275d35d | 434 | * @brief BDTR (Break and Dead Time) structure definition |
<> | 135:176b8275d35d | 435 | */ |
<> | 135:176b8275d35d | 436 | typedef struct |
<> | 135:176b8275d35d | 437 | { |
<> | 135:176b8275d35d | 438 | uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. |
<> | 135:176b8275d35d | 439 | This parameter can be a value of @ref TIM_LL_EC_OSSR |
<> | 135:176b8275d35d | 440 | |
<> | 135:176b8275d35d | 441 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() |
<> | 135:176b8275d35d | 442 | |
<> | 135:176b8275d35d | 443 | @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ |
<> | 135:176b8275d35d | 444 | |
<> | 135:176b8275d35d | 445 | uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. |
<> | 135:176b8275d35d | 446 | This parameter can be a value of @ref TIM_LL_EC_OSSI |
<> | 135:176b8275d35d | 447 | |
<> | 135:176b8275d35d | 448 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() |
<> | 135:176b8275d35d | 449 | |
<> | 135:176b8275d35d | 450 | @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ |
<> | 135:176b8275d35d | 451 | |
<> | 135:176b8275d35d | 452 | uint32_t LockLevel; /*!< Specifies the LOCK level parameters. |
<> | 135:176b8275d35d | 453 | This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL |
<> | 135:176b8275d35d | 454 | |
<> | 135:176b8275d35d | 455 | @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register |
<> | 135:176b8275d35d | 456 | has been written, their content is frozen until the next reset.*/ |
<> | 135:176b8275d35d | 457 | |
<> | 135:176b8275d35d | 458 | uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the |
<> | 135:176b8275d35d | 459 | switching-on of the outputs. |
<> | 135:176b8275d35d | 460 | This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
<> | 135:176b8275d35d | 461 | |
<> | 135:176b8275d35d | 462 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() |
<> | 135:176b8275d35d | 463 | |
<> | 135:176b8275d35d | 464 | @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ |
<> | 135:176b8275d35d | 465 | |
<> | 135:176b8275d35d | 466 | uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. |
<> | 135:176b8275d35d | 467 | This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE |
<> | 135:176b8275d35d | 468 | |
<> | 135:176b8275d35d | 469 | This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() |
<> | 135:176b8275d35d | 470 | |
<> | 135:176b8275d35d | 471 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
<> | 135:176b8275d35d | 472 | |
<> | 135:176b8275d35d | 473 | uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. |
<> | 135:176b8275d35d | 474 | This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY |
<> | 135:176b8275d35d | 475 | |
<> | 135:176b8275d35d | 476 | This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() |
<> | 135:176b8275d35d | 477 | |
<> | 135:176b8275d35d | 478 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
<> | 135:176b8275d35d | 479 | |
<> | 135:176b8275d35d | 480 | #if defined(TIM_BDTR_BKF) |
<> | 135:176b8275d35d | 481 | uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. |
<> | 135:176b8275d35d | 482 | This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER |
<> | 135:176b8275d35d | 483 | |
<> | 135:176b8275d35d | 484 | This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() |
<> | 135:176b8275d35d | 485 | |
<> | 135:176b8275d35d | 486 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
<> | 135:176b8275d35d | 487 | |
<> | 135:176b8275d35d | 488 | #endif /* TIM_BDTR_BKF */ |
<> | 135:176b8275d35d | 489 | #if defined(TIM_BDTR_BK2E) |
<> | 135:176b8275d35d | 490 | uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. |
<> | 135:176b8275d35d | 491 | This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE |
<> | 135:176b8275d35d | 492 | |
<> | 135:176b8275d35d | 493 | This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() |
<> | 135:176b8275d35d | 494 | |
<> | 135:176b8275d35d | 495 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
<> | 135:176b8275d35d | 496 | |
<> | 135:176b8275d35d | 497 | uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. |
<> | 135:176b8275d35d | 498 | This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY |
<> | 135:176b8275d35d | 499 | |
<> | 135:176b8275d35d | 500 | This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() |
<> | 135:176b8275d35d | 501 | |
<> | 135:176b8275d35d | 502 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
<> | 135:176b8275d35d | 503 | |
<> | 135:176b8275d35d | 504 | uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. |
<> | 135:176b8275d35d | 505 | This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER |
<> | 135:176b8275d35d | 506 | |
<> | 135:176b8275d35d | 507 | This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() |
<> | 135:176b8275d35d | 508 | |
<> | 135:176b8275d35d | 509 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
<> | 135:176b8275d35d | 510 | |
<> | 135:176b8275d35d | 511 | #endif /* TIM_BDTR_BK2E */ |
<> | 135:176b8275d35d | 512 | uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. |
<> | 135:176b8275d35d | 513 | This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE |
<> | 135:176b8275d35d | 514 | |
<> | 135:176b8275d35d | 515 | This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() |
<> | 135:176b8275d35d | 516 | |
<> | 135:176b8275d35d | 517 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
<> | 135:176b8275d35d | 518 | } LL_TIM_BDTR_InitTypeDef; |
<> | 135:176b8275d35d | 519 | |
<> | 135:176b8275d35d | 520 | /** |
<> | 135:176b8275d35d | 521 | * @} |
<> | 135:176b8275d35d | 522 | */ |
<> | 135:176b8275d35d | 523 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 135:176b8275d35d | 524 | |
<> | 135:176b8275d35d | 525 | /* Exported constants --------------------------------------------------------*/ |
<> | 135:176b8275d35d | 526 | /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants |
<> | 135:176b8275d35d | 527 | * @{ |
<> | 135:176b8275d35d | 528 | */ |
<> | 135:176b8275d35d | 529 | |
<> | 135:176b8275d35d | 530 | /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines |
<> | 135:176b8275d35d | 531 | * @brief Flags defines which can be used with LL_TIM_ReadReg function. |
<> | 135:176b8275d35d | 532 | * @{ |
<> | 135:176b8275d35d | 533 | */ |
<> | 135:176b8275d35d | 534 | #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ |
<> | 135:176b8275d35d | 535 | #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ |
<> | 135:176b8275d35d | 536 | #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ |
<> | 135:176b8275d35d | 537 | #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ |
<> | 135:176b8275d35d | 538 | #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ |
<> | 135:176b8275d35d | 539 | #if defined(TIM_CCMR1_OC1M_3) |
<> | 135:176b8275d35d | 540 | #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ |
<> | 135:176b8275d35d | 541 | #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ |
<> | 135:176b8275d35d | 542 | #endif /* TIM_CCMR1_OC1M_3 */ |
<> | 135:176b8275d35d | 543 | #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ |
<> | 135:176b8275d35d | 544 | #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ |
<> | 135:176b8275d35d | 545 | #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ |
<> | 135:176b8275d35d | 546 | #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ |
<> | 135:176b8275d35d | 547 | #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ |
<> | 135:176b8275d35d | 548 | #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ |
<> | 135:176b8275d35d | 549 | #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ |
<> | 135:176b8275d35d | 550 | #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ |
<> | 135:176b8275d35d | 551 | /** |
<> | 135:176b8275d35d | 552 | * @} |
<> | 135:176b8275d35d | 553 | */ |
<> | 135:176b8275d35d | 554 | |
<> | 135:176b8275d35d | 555 | #if defined(USE_FULL_LL_DRIVER) |
<> | 135:176b8275d35d | 556 | /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable |
<> | 135:176b8275d35d | 557 | * @{ |
<> | 135:176b8275d35d | 558 | */ |
<> | 135:176b8275d35d | 559 | #define LL_TIM_BREAK_DISABLE ((uint32_t)0x00000000U) /*!< Break function disabled */ |
<> | 135:176b8275d35d | 560 | #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ |
<> | 135:176b8275d35d | 561 | /** |
<> | 135:176b8275d35d | 562 | * @} |
<> | 135:176b8275d35d | 563 | */ |
<> | 135:176b8275d35d | 564 | #if defined(TIM_BDTR_BK2E) |
<> | 135:176b8275d35d | 565 | |
<> | 135:176b8275d35d | 566 | /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable |
<> | 135:176b8275d35d | 567 | * @{ |
<> | 135:176b8275d35d | 568 | */ |
<> | 135:176b8275d35d | 569 | #define LL_TIM_BREAK2_DISABLE ((uint32_t)0x00000000U) /*!< Break2 function disabled */ |
<> | 135:176b8275d35d | 570 | #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ |
<> | 135:176b8275d35d | 571 | /** |
<> | 135:176b8275d35d | 572 | * @} |
<> | 135:176b8275d35d | 573 | */ |
<> | 135:176b8275d35d | 574 | #endif /* TIM_BDTR_BK2E */ |
<> | 135:176b8275d35d | 575 | |
<> | 135:176b8275d35d | 576 | /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable |
<> | 135:176b8275d35d | 577 | * @{ |
<> | 135:176b8275d35d | 578 | */ |
<> | 135:176b8275d35d | 579 | #define LL_TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< MOE can be set only by software */ |
<> | 135:176b8275d35d | 580 | #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ |
<> | 135:176b8275d35d | 581 | /** |
<> | 135:176b8275d35d | 582 | * @} |
<> | 135:176b8275d35d | 583 | */ |
<> | 135:176b8275d35d | 584 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 135:176b8275d35d | 585 | |
<> | 135:176b8275d35d | 586 | /** @defgroup TIM_LL_EC_IT IT Defines |
<> | 135:176b8275d35d | 587 | * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. |
<> | 135:176b8275d35d | 588 | * @{ |
<> | 135:176b8275d35d | 589 | */ |
<> | 135:176b8275d35d | 590 | #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ |
<> | 135:176b8275d35d | 591 | #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ |
<> | 135:176b8275d35d | 592 | #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ |
<> | 135:176b8275d35d | 593 | #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ |
<> | 135:176b8275d35d | 594 | #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ |
<> | 135:176b8275d35d | 595 | #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ |
<> | 135:176b8275d35d | 596 | #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ |
<> | 135:176b8275d35d | 597 | #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ |
<> | 135:176b8275d35d | 598 | /** |
<> | 135:176b8275d35d | 599 | * @} |
<> | 135:176b8275d35d | 600 | */ |
<> | 135:176b8275d35d | 601 | |
<> | 135:176b8275d35d | 602 | /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source |
<> | 135:176b8275d35d | 603 | * @{ |
<> | 135:176b8275d35d | 604 | */ |
<> | 135:176b8275d35d | 605 | #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ |
<> | 135:176b8275d35d | 606 | #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ |
<> | 135:176b8275d35d | 607 | /** |
<> | 135:176b8275d35d | 608 | * @} |
<> | 135:176b8275d35d | 609 | */ |
<> | 135:176b8275d35d | 610 | |
<> | 135:176b8275d35d | 611 | /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode |
<> | 135:176b8275d35d | 612 | * @{ |
<> | 135:176b8275d35d | 613 | */ |
<> | 135:176b8275d35d | 614 | #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ |
<> | 135:176b8275d35d | 615 | #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ |
<> | 135:176b8275d35d | 616 | /** |
<> | 135:176b8275d35d | 617 | * @} |
<> | 135:176b8275d35d | 618 | */ |
<> | 135:176b8275d35d | 619 | |
<> | 135:176b8275d35d | 620 | /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode |
<> | 135:176b8275d35d | 621 | * @{ |
<> | 135:176b8275d35d | 622 | */ |
<> | 135:176b8275d35d | 623 | #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */ |
<> | 135:176b8275d35d | 624 | #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ |
<> | 135:176b8275d35d | 625 | #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ |
<> | 135:176b8275d35d | 626 | #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ |
<> | 135:176b8275d35d | 627 | #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ |
<> | 135:176b8275d35d | 628 | /** |
<> | 135:176b8275d35d | 629 | * @} |
<> | 135:176b8275d35d | 630 | */ |
<> | 135:176b8275d35d | 631 | |
<> | 135:176b8275d35d | 632 | /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division |
<> | 135:176b8275d35d | 633 | * @{ |
<> | 135:176b8275d35d | 634 | */ |
<> | 135:176b8275d35d | 635 | #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ |
<> | 135:176b8275d35d | 636 | #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ |
<> | 135:176b8275d35d | 637 | #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ |
<> | 135:176b8275d35d | 638 | /** |
<> | 135:176b8275d35d | 639 | * @} |
<> | 135:176b8275d35d | 640 | */ |
<> | 135:176b8275d35d | 641 | |
<> | 135:176b8275d35d | 642 | /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction |
<> | 135:176b8275d35d | 643 | * @{ |
<> | 135:176b8275d35d | 644 | */ |
<> | 135:176b8275d35d | 645 | #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ |
<> | 135:176b8275d35d | 646 | #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ |
<> | 135:176b8275d35d | 647 | /** |
<> | 135:176b8275d35d | 648 | * @} |
<> | 135:176b8275d35d | 649 | */ |
<> | 135:176b8275d35d | 650 | |
<> | 135:176b8275d35d | 651 | /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source |
<> | 135:176b8275d35d | 652 | * @{ |
<> | 135:176b8275d35d | 653 | */ |
<> | 135:176b8275d35d | 654 | #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ |
<> | 135:176b8275d35d | 655 | #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ |
<> | 135:176b8275d35d | 656 | /** |
<> | 135:176b8275d35d | 657 | * @} |
<> | 135:176b8275d35d | 658 | */ |
<> | 135:176b8275d35d | 659 | |
<> | 135:176b8275d35d | 660 | /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request |
<> | 135:176b8275d35d | 661 | * @{ |
<> | 135:176b8275d35d | 662 | */ |
<> | 135:176b8275d35d | 663 | #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ |
<> | 135:176b8275d35d | 664 | #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ |
<> | 135:176b8275d35d | 665 | /** |
<> | 135:176b8275d35d | 666 | * @} |
<> | 135:176b8275d35d | 667 | */ |
<> | 135:176b8275d35d | 668 | |
<> | 135:176b8275d35d | 669 | /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level |
<> | 135:176b8275d35d | 670 | * @{ |
<> | 135:176b8275d35d | 671 | */ |
<> | 135:176b8275d35d | 672 | #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ |
<> | 135:176b8275d35d | 673 | #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ |
<> | 135:176b8275d35d | 674 | #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ |
<> | 135:176b8275d35d | 675 | #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ |
<> | 135:176b8275d35d | 676 | /** |
<> | 135:176b8275d35d | 677 | * @} |
<> | 135:176b8275d35d | 678 | */ |
<> | 135:176b8275d35d | 679 | |
<> | 135:176b8275d35d | 680 | /** @defgroup TIM_LL_EC_CHANNEL Channel |
<> | 135:176b8275d35d | 681 | * @{ |
<> | 135:176b8275d35d | 682 | */ |
<> | 135:176b8275d35d | 683 | #if defined(TIM_CCMR1_OC1M_3) |
<> | 135:176b8275d35d | 684 | #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ |
<> | 135:176b8275d35d | 685 | #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ |
<> | 135:176b8275d35d | 686 | #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ |
<> | 135:176b8275d35d | 687 | #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ |
<> | 135:176b8275d35d | 688 | #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ |
<> | 135:176b8275d35d | 689 | #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ |
<> | 135:176b8275d35d | 690 | #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ |
<> | 135:176b8275d35d | 691 | #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ |
<> | 135:176b8275d35d | 692 | #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ |
<> | 135:176b8275d35d | 693 | #else |
<> | 135:176b8275d35d | 694 | #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ |
<> | 135:176b8275d35d | 695 | #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ |
<> | 135:176b8275d35d | 696 | #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ |
<> | 135:176b8275d35d | 697 | #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ |
<> | 135:176b8275d35d | 698 | #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ |
<> | 135:176b8275d35d | 699 | #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ |
<> | 135:176b8275d35d | 700 | #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ |
<> | 135:176b8275d35d | 701 | #endif |
<> | 135:176b8275d35d | 702 | /** |
<> | 135:176b8275d35d | 703 | * @} |
<> | 135:176b8275d35d | 704 | */ |
<> | 135:176b8275d35d | 705 | |
<> | 135:176b8275d35d | 706 | #if defined(USE_FULL_LL_DRIVER) |
<> | 135:176b8275d35d | 707 | /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State |
<> | 135:176b8275d35d | 708 | * @{ |
<> | 135:176b8275d35d | 709 | */ |
<> | 135:176b8275d35d | 710 | #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ |
<> | 135:176b8275d35d | 711 | #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ |
<> | 135:176b8275d35d | 712 | /** |
<> | 135:176b8275d35d | 713 | * @} |
<> | 135:176b8275d35d | 714 | */ |
<> | 135:176b8275d35d | 715 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 135:176b8275d35d | 716 | |
<> | 135:176b8275d35d | 717 | /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode |
<> | 135:176b8275d35d | 718 | * @{ |
<> | 135:176b8275d35d | 719 | */ |
<> | 135:176b8275d35d | 720 | #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ |
<> | 135:176b8275d35d | 721 | #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ |
<> | 135:176b8275d35d | 722 | #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ |
<> | 135:176b8275d35d | 723 | #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ |
<> | 135:176b8275d35d | 724 | #define LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) /*!<OCyREF is forced low*/ |
<> | 135:176b8275d35d | 725 | #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ |
<> | 135:176b8275d35d | 726 | #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ |
<> | 135:176b8275d35d | 727 | #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ |
<> | 135:176b8275d35d | 728 | #if defined(TIM_CCMR1_OC1M_3) |
<> | 135:176b8275d35d | 729 | #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/ |
<> | 135:176b8275d35d | 730 | #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/ |
<> | 135:176b8275d35d | 731 | #endif |
<> | 135:176b8275d35d | 732 | #if defined(TIM_CCMR1_OC1M_3) |
<> | 135:176b8275d35d | 733 | #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/ |
<> | 135:176b8275d35d | 734 | #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/ |
<> | 135:176b8275d35d | 735 | #endif |
<> | 135:176b8275d35d | 736 | #if defined(TIM_CCMR1_OC1M_3) |
<> | 135:176b8275d35d | 737 | #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/ |
<> | 135:176b8275d35d | 738 | #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/ |
<> | 135:176b8275d35d | 739 | #endif |
<> | 135:176b8275d35d | 740 | /** |
<> | 135:176b8275d35d | 741 | * @} |
<> | 135:176b8275d35d | 742 | */ |
<> | 135:176b8275d35d | 743 | |
<> | 135:176b8275d35d | 744 | /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity |
<> | 135:176b8275d35d | 745 | * @{ |
<> | 135:176b8275d35d | 746 | */ |
<> | 135:176b8275d35d | 747 | #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ |
<> | 135:176b8275d35d | 748 | #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ |
<> | 135:176b8275d35d | 749 | /** |
<> | 135:176b8275d35d | 750 | * @} |
<> | 135:176b8275d35d | 751 | */ |
<> | 135:176b8275d35d | 752 | |
<> | 135:176b8275d35d | 753 | /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State |
<> | 135:176b8275d35d | 754 | * @{ |
<> | 135:176b8275d35d | 755 | */ |
<> | 135:176b8275d35d | 756 | #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/ |
<> | 135:176b8275d35d | 757 | #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/ |
<> | 135:176b8275d35d | 758 | /** |
<> | 135:176b8275d35d | 759 | * @} |
<> | 135:176b8275d35d | 760 | */ |
<> | 135:176b8275d35d | 761 | |
<> | 135:176b8275d35d | 762 | #if defined(TIM_CCR5_CCR5) |
<> | 135:176b8275d35d | 763 | /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5 |
<> | 135:176b8275d35d | 764 | * @{ |
<> | 135:176b8275d35d | 765 | */ |
<> | 135:176b8275d35d | 766 | #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ |
<> | 135:176b8275d35d | 767 | #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ |
<> | 135:176b8275d35d | 768 | #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ |
<> | 135:176b8275d35d | 769 | #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ |
<> | 135:176b8275d35d | 770 | /** |
<> | 135:176b8275d35d | 771 | * @} |
<> | 135:176b8275d35d | 772 | */ |
<> | 135:176b8275d35d | 773 | #endif /* TIM_CCR5_CCR5 */ |
<> | 135:176b8275d35d | 774 | |
<> | 135:176b8275d35d | 775 | /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection |
<> | 135:176b8275d35d | 776 | * @{ |
<> | 135:176b8275d35d | 777 | */ |
<> | 135:176b8275d35d | 778 | #define LL_TIM_ACTIVEINPUT_DIRECTTI TIM_CCMR1_CC1S_0 << 16U /*!< ICx is mapped on TIx */ |
<> | 135:176b8275d35d | 779 | #define LL_TIM_ACTIVEINPUT_INDIRECTTI TIM_CCMR1_CC1S_1 << 16U /*!< ICx is mapped on TIy */ |
<> | 135:176b8275d35d | 780 | #define LL_TIM_ACTIVEINPUT_TRC TIM_CCMR1_CC1S << 16U /*!< ICx is mapped on TRC */ |
<> | 135:176b8275d35d | 781 | /** |
<> | 135:176b8275d35d | 782 | * @} |
<> | 135:176b8275d35d | 783 | */ |
<> | 135:176b8275d35d | 784 | |
<> | 135:176b8275d35d | 785 | /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler |
<> | 135:176b8275d35d | 786 | * @{ |
<> | 135:176b8275d35d | 787 | */ |
<> | 135:176b8275d35d | 788 | #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ |
<> | 135:176b8275d35d | 789 | #define LL_TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 << 16U /*!< Capture is done once every 2 events */ |
<> | 135:176b8275d35d | 790 | #define LL_TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 << 16U /*!< Capture is done once every 4 events */ |
<> | 135:176b8275d35d | 791 | #define LL_TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC << 16U /*!< Capture is done once every 8 events */ |
<> | 135:176b8275d35d | 792 | /** |
<> | 135:176b8275d35d | 793 | * @} |
<> | 135:176b8275d35d | 794 | */ |
<> | 135:176b8275d35d | 795 | |
<> | 135:176b8275d35d | 796 | /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter |
<> | 135:176b8275d35d | 797 | * @{ |
<> | 135:176b8275d35d | 798 | */ |
<> | 135:176b8275d35d | 799 | #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
<> | 135:176b8275d35d | 800 | #define LL_TIM_IC_FILTER_FDIV1_N2 TIM_CCMR1_IC1F_0 << 16U /*!< fSAMPLING=fCK_INT, N=2 */ |
<> | 135:176b8275d35d | 801 | #define LL_TIM_IC_FILTER_FDIV1_N4 TIM_CCMR1_IC1F_1 << 16U /*!< fSAMPLING=fCK_INT, N=4 */ |
<> | 135:176b8275d35d | 802 | #define LL_TIM_IC_FILTER_FDIV1_N8 (TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U /*!< fSAMPLING=fCK_INT, N=8 */ |
<> | 135:176b8275d35d | 803 | #define LL_TIM_IC_FILTER_FDIV2_N6 TIM_CCMR1_IC1F_2 << 16U /*!< fSAMPLING=fDTS/2, N=6 */ |
<> | 135:176b8275d35d | 804 | #define LL_TIM_IC_FILTER_FDIV2_N8 (TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U /*!< fSAMPLING=fDTS/2, N=8 */ |
<> | 135:176b8275d35d | 805 | #define LL_TIM_IC_FILTER_FDIV4_N6 (TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U /*!< fSAMPLING=fDTS/4, N=6 */ |
<> | 135:176b8275d35d | 806 | #define LL_TIM_IC_FILTER_FDIV4_N8 (TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U /*!< fSAMPLING=fDTS/4, N=8 */ |
<> | 135:176b8275d35d | 807 | #define LL_TIM_IC_FILTER_FDIV8_N6 TIM_CCMR1_IC1F_3 << 16U /*!< fSAMPLING=fDTS/8, N=6 */ |
<> | 135:176b8275d35d | 808 | #define LL_TIM_IC_FILTER_FDIV8_N8 (TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U /*!< fSAMPLING=fDTS/8, N=8 */ |
<> | 135:176b8275d35d | 809 | #define LL_TIM_IC_FILTER_FDIV16_N5 (TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U /*!< fSAMPLING=fDTS/16, N=5 */ |
<> | 135:176b8275d35d | 810 | #define LL_TIM_IC_FILTER_FDIV16_N6 (TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U /*!< fSAMPLING=fDTS/16, N=6 */ |
<> | 135:176b8275d35d | 811 | #define LL_TIM_IC_FILTER_FDIV16_N8 (TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U /*!< fSAMPLING=fDTS/16, N=8 */ |
<> | 135:176b8275d35d | 812 | #define LL_TIM_IC_FILTER_FDIV32_N5 (TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U /*!< fSAMPLING=fDTS/32, N=5 */ |
<> | 135:176b8275d35d | 813 | #define LL_TIM_IC_FILTER_FDIV32_N6 (TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U /*!< fSAMPLING=fDTS/32, N=6 */ |
<> | 135:176b8275d35d | 814 | #define LL_TIM_IC_FILTER_FDIV32_N8 TIM_CCMR1_IC1F << 16U /*!< fSAMPLING=fDTS/32, N=8 */ |
<> | 135:176b8275d35d | 815 | /** |
<> | 135:176b8275d35d | 816 | * @} |
<> | 135:176b8275d35d | 817 | */ |
<> | 135:176b8275d35d | 818 | |
<> | 135:176b8275d35d | 819 | /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity |
<> | 135:176b8275d35d | 820 | * @{ |
<> | 135:176b8275d35d | 821 | */ |
<> | 135:176b8275d35d | 822 | #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ |
<> | 135:176b8275d35d | 823 | #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ |
<> | 135:176b8275d35d | 824 | #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ |
<> | 135:176b8275d35d | 825 | /** |
<> | 135:176b8275d35d | 826 | * @} |
<> | 135:176b8275d35d | 827 | */ |
<> | 135:176b8275d35d | 828 | |
<> | 135:176b8275d35d | 829 | /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source |
<> | 135:176b8275d35d | 830 | * @{ |
<> | 135:176b8275d35d | 831 | */ |
<> | 135:176b8275d35d | 832 | #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ |
<> | 135:176b8275d35d | 833 | #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 ) /*!< Counter counts at each rising or falling edge on a selected inpu t*/ |
<> | 135:176b8275d35d | 834 | #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ |
<> | 135:176b8275d35d | 835 | /** |
<> | 135:176b8275d35d | 836 | * @} |
<> | 135:176b8275d35d | 837 | */ |
<> | 135:176b8275d35d | 838 | |
<> | 135:176b8275d35d | 839 | /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode |
<> | 135:176b8275d35d | 840 | * @{ |
<> | 135:176b8275d35d | 841 | */ |
<> | 135:176b8275d35d | 842 | #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ |
<> | 135:176b8275d35d | 843 | #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ |
<> | 135:176b8275d35d | 844 | #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */ |
<> | 135:176b8275d35d | 845 | /** |
<> | 135:176b8275d35d | 846 | * @} |
<> | 135:176b8275d35d | 847 | */ |
<> | 135:176b8275d35d | 848 | |
<> | 135:176b8275d35d | 849 | /** @defgroup TIM_LL_EC_TRGO Trigger Output |
<> | 135:176b8275d35d | 850 | * @{ |
<> | 135:176b8275d35d | 851 | */ |
<> | 135:176b8275d35d | 852 | #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */ |
<> | 135:176b8275d35d | 853 | #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ |
<> | 135:176b8275d35d | 854 | #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ |
<> | 135:176b8275d35d | 855 | #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ |
<> | 135:176b8275d35d | 856 | #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ |
<> | 135:176b8275d35d | 857 | #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ |
<> | 135:176b8275d35d | 858 | #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ |
<> | 135:176b8275d35d | 859 | #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ |
<> | 135:176b8275d35d | 860 | /** |
<> | 135:176b8275d35d | 861 | * @} |
<> | 135:176b8275d35d | 862 | */ |
<> | 135:176b8275d35d | 863 | |
<> | 135:176b8275d35d | 864 | #if defined(TIM_CR2_MMS2) |
<> | 135:176b8275d35d | 865 | /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2 |
<> | 135:176b8275d35d | 866 | * @{ |
<> | 135:176b8275d35d | 867 | */ |
<> | 135:176b8275d35d | 868 | #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */ |
<> | 135:176b8275d35d | 869 | #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */ |
<> | 135:176b8275d35d | 870 | #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */ |
<> | 135:176b8275d35d | 871 | #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */ |
<> | 135:176b8275d35d | 872 | #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */ |
<> | 135:176b8275d35d | 873 | #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */ |
<> | 135:176b8275d35d | 874 | #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */ |
<> | 135:176b8275d35d | 875 | #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */ |
<> | 135:176b8275d35d | 876 | #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */ |
<> | 135:176b8275d35d | 877 | #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */ |
<> | 135:176b8275d35d | 878 | #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */ |
<> | 135:176b8275d35d | 879 | #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */ |
<> | 135:176b8275d35d | 880 | #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */ |
<> | 135:176b8275d35d | 881 | #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */ |
<> | 135:176b8275d35d | 882 | #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */ |
<> | 135:176b8275d35d | 883 | #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */ |
<> | 135:176b8275d35d | 884 | /** |
<> | 135:176b8275d35d | 885 | * @} |
<> | 135:176b8275d35d | 886 | */ |
<> | 135:176b8275d35d | 887 | #endif /* TIM_CR2_MMS2 */ |
<> | 135:176b8275d35d | 888 | |
<> | 135:176b8275d35d | 889 | /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode |
<> | 135:176b8275d35d | 890 | * @{ |
<> | 135:176b8275d35d | 891 | */ |
<> | 135:176b8275d35d | 892 | #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */ |
<> | 135:176b8275d35d | 893 | #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ |
<> | 135:176b8275d35d | 894 | #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ |
<> | 135:176b8275d35d | 895 | #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ |
<> | 135:176b8275d35d | 896 | #if defined (TIM_SMCR_SMS_3) |
<> | 135:176b8275d35d | 897 | #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */ |
<> | 135:176b8275d35d | 898 | #endif /* TIM_SMCR_SMS_3 */ |
<> | 135:176b8275d35d | 899 | /** |
<> | 135:176b8275d35d | 900 | * @} |
<> | 135:176b8275d35d | 901 | */ |
<> | 135:176b8275d35d | 902 | |
<> | 135:176b8275d35d | 903 | /** @defgroup TIM_LL_EC_TS Trigger Selection |
<> | 135:176b8275d35d | 904 | * @{ |
<> | 135:176b8275d35d | 905 | */ |
<> | 135:176b8275d35d | 906 | #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ |
<> | 135:176b8275d35d | 907 | #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ |
<> | 135:176b8275d35d | 908 | #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ |
<> | 135:176b8275d35d | 909 | #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ |
<> | 135:176b8275d35d | 910 | #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ |
<> | 135:176b8275d35d | 911 | #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ |
<> | 135:176b8275d35d | 912 | #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ |
<> | 135:176b8275d35d | 913 | #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ |
<> | 135:176b8275d35d | 914 | /** |
<> | 135:176b8275d35d | 915 | * @} |
<> | 135:176b8275d35d | 916 | */ |
<> | 135:176b8275d35d | 917 | |
<> | 135:176b8275d35d | 918 | /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity |
<> | 135:176b8275d35d | 919 | * @{ |
<> | 135:176b8275d35d | 920 | */ |
<> | 135:176b8275d35d | 921 | #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */ |
<> | 135:176b8275d35d | 922 | #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ |
<> | 135:176b8275d35d | 923 | /** |
<> | 135:176b8275d35d | 924 | * @} |
<> | 135:176b8275d35d | 925 | */ |
<> | 135:176b8275d35d | 926 | |
<> | 135:176b8275d35d | 927 | /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler |
<> | 135:176b8275d35d | 928 | * @{ |
<> | 135:176b8275d35d | 929 | */ |
<> | 135:176b8275d35d | 930 | #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */ |
<> | 135:176b8275d35d | 931 | #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ |
<> | 135:176b8275d35d | 932 | #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ |
<> | 135:176b8275d35d | 933 | #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ |
<> | 135:176b8275d35d | 934 | /** |
<> | 135:176b8275d35d | 935 | * @} |
<> | 135:176b8275d35d | 936 | */ |
<> | 135:176b8275d35d | 937 | |
<> | 135:176b8275d35d | 938 | /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter |
<> | 135:176b8275d35d | 939 | * @{ |
<> | 135:176b8275d35d | 940 | */ |
<> | 135:176b8275d35d | 941 | #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
<> | 135:176b8275d35d | 942 | #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ |
<> | 135:176b8275d35d | 943 | #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ |
<> | 135:176b8275d35d | 944 | #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ |
<> | 135:176b8275d35d | 945 | #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ |
<> | 135:176b8275d35d | 946 | #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ |
<> | 135:176b8275d35d | 947 | #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 ) /*!< fSAMPLING=fDTS/4, N=6 */ |
<> | 135:176b8275d35d | 948 | #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ |
<> | 135:176b8275d35d | 949 | #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ |
<> | 135:176b8275d35d | 950 | #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ |
<> | 135:176b8275d35d | 951 | #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 ) /*!< fSAMPLING=fDTS/16, N=6 */ |
<> | 135:176b8275d35d | 952 | #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ |
<> | 135:176b8275d35d | 953 | #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 ) /*!< fSAMPLING=fDTS/16, N=5 */ |
<> | 135:176b8275d35d | 954 | #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ |
<> | 135:176b8275d35d | 955 | #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ |
<> | 135:176b8275d35d | 956 | #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ |
<> | 135:176b8275d35d | 957 | /** |
<> | 135:176b8275d35d | 958 | * @} |
<> | 135:176b8275d35d | 959 | */ |
<> | 135:176b8275d35d | 960 | |
<> | 135:176b8275d35d | 961 | |
<> | 135:176b8275d35d | 962 | /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity |
<> | 135:176b8275d35d | 963 | * @{ |
<> | 135:176b8275d35d | 964 | */ |
<> | 135:176b8275d35d | 965 | #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ |
<> | 135:176b8275d35d | 966 | #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ |
<> | 135:176b8275d35d | 967 | /** |
<> | 135:176b8275d35d | 968 | * @} |
<> | 135:176b8275d35d | 969 | */ |
<> | 135:176b8275d35d | 970 | |
<> | 135:176b8275d35d | 971 | #if defined(TIM_BDTR_BKF) |
<> | 135:176b8275d35d | 972 | /** @defgroup TIM_LL_EC_BREAK_FILTER break filter |
<> | 135:176b8275d35d | 973 | * @{ |
<> | 135:176b8275d35d | 974 | */ |
<> | 135:176b8275d35d | 975 | #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ |
<> | 135:176b8275d35d | 976 | #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */ |
<> | 135:176b8275d35d | 977 | #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */ |
<> | 135:176b8275d35d | 978 | #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */ |
<> | 135:176b8275d35d | 979 | #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */ |
<> | 135:176b8275d35d | 980 | #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */ |
<> | 135:176b8275d35d | 981 | #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */ |
<> | 135:176b8275d35d | 982 | #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */ |
<> | 135:176b8275d35d | 983 | #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */ |
<> | 135:176b8275d35d | 984 | #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */ |
<> | 135:176b8275d35d | 985 | #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */ |
<> | 135:176b8275d35d | 986 | #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */ |
<> | 135:176b8275d35d | 987 | #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */ |
<> | 135:176b8275d35d | 988 | #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */ |
<> | 135:176b8275d35d | 989 | #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */ |
<> | 135:176b8275d35d | 990 | #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */ |
<> | 135:176b8275d35d | 991 | /** |
<> | 135:176b8275d35d | 992 | * @} |
<> | 135:176b8275d35d | 993 | */ |
<> | 135:176b8275d35d | 994 | #endif /* TIM_BDTR_BKF */ |
<> | 135:176b8275d35d | 995 | |
<> | 135:176b8275d35d | 996 | #if defined(TIM_BDTR_BK2P) |
<> | 135:176b8275d35d | 997 | /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY |
<> | 135:176b8275d35d | 998 | * @{ |
<> | 135:176b8275d35d | 999 | */ |
<> | 135:176b8275d35d | 1000 | #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ |
<> | 135:176b8275d35d | 1001 | #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ |
<> | 135:176b8275d35d | 1002 | /** |
<> | 135:176b8275d35d | 1003 | * @} |
<> | 135:176b8275d35d | 1004 | */ |
<> | 135:176b8275d35d | 1005 | #endif /* TIM_BDTR_BK2P */ |
<> | 135:176b8275d35d | 1006 | |
<> | 135:176b8275d35d | 1007 | #if defined(TIM_BDTR_BK2F) |
<> | 135:176b8275d35d | 1008 | /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER |
<> | 135:176b8275d35d | 1009 | * @{ |
<> | 135:176b8275d35d | 1010 | */ |
<> | 135:176b8275d35d | 1011 | #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ |
<> | 135:176b8275d35d | 1012 | #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */ |
<> | 135:176b8275d35d | 1013 | #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */ |
<> | 135:176b8275d35d | 1014 | #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */ |
<> | 135:176b8275d35d | 1015 | #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */ |
<> | 135:176b8275d35d | 1016 | #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */ |
<> | 135:176b8275d35d | 1017 | #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */ |
<> | 135:176b8275d35d | 1018 | #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */ |
<> | 135:176b8275d35d | 1019 | #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */ |
<> | 135:176b8275d35d | 1020 | #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */ |
<> | 135:176b8275d35d | 1021 | #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */ |
<> | 135:176b8275d35d | 1022 | #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */ |
<> | 135:176b8275d35d | 1023 | #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */ |
<> | 135:176b8275d35d | 1024 | #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */ |
<> | 135:176b8275d35d | 1025 | #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */ |
<> | 135:176b8275d35d | 1026 | #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */ |
<> | 135:176b8275d35d | 1027 | /** |
<> | 135:176b8275d35d | 1028 | * @} |
<> | 135:176b8275d35d | 1029 | */ |
<> | 135:176b8275d35d | 1030 | #endif /* TIM_BDTR_BK2F */ |
<> | 135:176b8275d35d | 1031 | |
<> | 135:176b8275d35d | 1032 | /** @defgroup TIM_LL_EC_OSSI OSSI |
<> | 135:176b8275d35d | 1033 | * @{ |
<> | 135:176b8275d35d | 1034 | */ |
<> | 135:176b8275d35d | 1035 | #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ |
<> | 135:176b8275d35d | 1036 | #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */ |
<> | 135:176b8275d35d | 1037 | /** |
<> | 135:176b8275d35d | 1038 | * @} |
<> | 135:176b8275d35d | 1039 | */ |
<> | 135:176b8275d35d | 1040 | |
<> | 135:176b8275d35d | 1041 | /** @defgroup TIM_LL_EC_OSSR OSSR |
<> | 135:176b8275d35d | 1042 | * @{ |
<> | 135:176b8275d35d | 1043 | */ |
<> | 135:176b8275d35d | 1044 | #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ |
<> | 135:176b8275d35d | 1045 | #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */ |
<> | 135:176b8275d35d | 1046 | /** |
<> | 135:176b8275d35d | 1047 | * @} |
<> | 135:176b8275d35d | 1048 | */ |
<> | 135:176b8275d35d | 1049 | |
<> | 135:176b8275d35d | 1050 | |
<> | 135:176b8275d35d | 1051 | /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address |
<> | 135:176b8275d35d | 1052 | * @{ |
<> | 135:176b8275d35d | 1053 | */ |
<> | 135:176b8275d35d | 1054 | #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1055 | #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1056 | #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1057 | #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1058 | #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1059 | #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1060 | #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1061 | #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1062 | #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1063 | #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1064 | #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1065 | #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1066 | #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1067 | #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1068 | #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1069 | #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1070 | #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1071 | #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1072 | #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1073 | #if defined(TIM_CCR6_CCR6) |
<> | 135:176b8275d35d | 1074 | #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1075 | #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1076 | #endif /* TIM_CCR6_CCR6 */ |
<> | 135:176b8275d35d | 1077 | #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR register is the DMA base address for DMA burst */ |
<> | 135:176b8275d35d | 1078 | /** |
<> | 135:176b8275d35d | 1079 | * @} |
<> | 135:176b8275d35d | 1080 | */ |
<> | 135:176b8275d35d | 1081 | |
<> | 135:176b8275d35d | 1082 | /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length |
<> | 135:176b8275d35d | 1083 | * @{ |
<> | 135:176b8275d35d | 1084 | */ |
<> | 135:176b8275d35d | 1085 | #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1086 | #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1087 | #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1088 | #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1089 | #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1090 | #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1091 | #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1092 | #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1093 | #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1094 | #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1095 | #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1096 | #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1097 | #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1098 | #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1099 | #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1100 | #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1101 | #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1102 | #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ |
<> | 135:176b8275d35d | 1103 | /** |
<> | 135:176b8275d35d | 1104 | * @} |
<> | 135:176b8275d35d | 1105 | */ |
<> | 135:176b8275d35d | 1106 | |
<> | 135:176b8275d35d | 1107 | #if defined(TIM1) |
<> | 135:176b8275d35d | 1108 | /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap |
<> | 135:176b8275d35d | 1109 | * @{ |
<> | 135:176b8275d35d | 1110 | */ |
<> | 135:176b8275d35d | 1111 | #define LL_TIM_TIM1_ETR_ADC1_RMP_NC (0x00000000U | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */ |
<> | 135:176b8275d35d | 1112 | #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_RMP_0 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */ |
<> | 135:176b8275d35d | 1113 | #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_RMP_1 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */ |
<> | 135:176b8275d35d | 1114 | #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_RMP_0 | TIM1_OR_ETR_RMP_1| TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */ |
<> | 135:176b8275d35d | 1115 | /** |
<> | 135:176b8275d35d | 1116 | * @} |
<> | 135:176b8275d35d | 1117 | */ |
<> | 135:176b8275d35d | 1118 | #if defined(ADC4) |
<> | 135:176b8275d35d | 1119 | /** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 External Trigger ADC4 Remap |
<> | 135:176b8275d35d | 1120 | * @{ |
<> | 135:176b8275d35d | 1121 | */ |
<> | 135:176b8275d35d | 1122 | #define LL_TIM_TIM1_ETR_ADC4_RMP_NC (0x00000000U | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is not connected to ADC4 analog watchdog x*/ |
<> | 135:176b8275d35d | 1123 | #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 1 */ |
<> | 135:176b8275d35d | 1124 | #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 2 */ |
<> | 135:176b8275d35d | 1125 | #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 3 */ |
<> | 135:176b8275d35d | 1126 | /** |
<> | 135:176b8275d35d | 1127 | * @} |
<> | 135:176b8275d35d | 1128 | */ |
<> | 135:176b8275d35d | 1129 | #else |
<> | 135:176b8275d35d | 1130 | /** @defgroup TIM_LL_EC_TIM1_ETR_ADC2_RMP TIM1 External Trigger ADC3 Remap |
<> | 135:176b8275d35d | 1131 | * @{ |
<> | 135:176b8275d35d | 1132 | */ |
<> | 135:176b8275d35d | 1133 | #define LL_TIM_TIM1_ETR_ADC2_RMP_NC (0x00000000U | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is not connected to ADC2 analog watchdog x*/ |
<> | 135:176b8275d35d | 1134 | #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 1 */ |
<> | 135:176b8275d35d | 1135 | #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 2 */ |
<> | 135:176b8275d35d | 1136 | #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 3 */ |
<> | 135:176b8275d35d | 1137 | /** |
<> | 135:176b8275d35d | 1138 | * @} |
<> | 135:176b8275d35d | 1139 | */ |
<> | 135:176b8275d35d | 1140 | #endif /* ADC4 */ |
<> | 135:176b8275d35d | 1141 | #endif /* TIM1 */ |
<> | 135:176b8275d35d | 1142 | #if defined(TIM8) |
<> | 135:176b8275d35d | 1143 | /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap |
<> | 135:176b8275d35d | 1144 | * @{ |
<> | 135:176b8275d35d | 1145 | */ |
<> | 135:176b8275d35d | 1146 | #define LL_TIM_TIM8_ETR_ADC2_RMP_NC (0x00000000U | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */ |
<> | 135:176b8275d35d | 1147 | #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR_ETR_RMP_0 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */ |
<> | 135:176b8275d35d | 1148 | #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */ |
<> | 135:176b8275d35d | 1149 | #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR_ETR_RMP_0 | TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */ |
<> | 135:176b8275d35d | 1150 | /** |
<> | 135:176b8275d35d | 1151 | * @} |
<> | 135:176b8275d35d | 1152 | */ |
<> | 135:176b8275d35d | 1153 | |
<> | 135:176b8275d35d | 1154 | /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap |
<> | 135:176b8275d35d | 1155 | * @{ |
<> | 135:176b8275d35d | 1156 | */ |
<> | 135:176b8275d35d | 1157 | #define LL_TIM_TIM8_ETR_ADC3_RMP_NC (0x00000000U | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */ |
<> | 135:176b8275d35d | 1158 | #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR_ETR_RMP_2 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */ |
<> | 135:176b8275d35d | 1159 | #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */ |
<> | 135:176b8275d35d | 1160 | #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR_ETR_RMP_2 | TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */ |
<> | 135:176b8275d35d | 1161 | /** |
<> | 135:176b8275d35d | 1162 | * @} |
<> | 135:176b8275d35d | 1163 | */ |
<> | 135:176b8275d35d | 1164 | #endif /* TIM8 */ |
<> | 135:176b8275d35d | 1165 | #if defined(TIM16) |
<> | 135:176b8275d35d | 1166 | /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap |
<> | 135:176b8275d35d | 1167 | * @{ |
<> | 135:176b8275d35d | 1168 | */ |
<> | 135:176b8275d35d | 1169 | #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input capture 1 is connected to GPIO */ |
<> | 135:176b8275d35d | 1170 | #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */ |
<> | 135:176b8275d35d | 1171 | #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 clock */ |
<> | 135:176b8275d35d | 1172 | #define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */ |
<> | 135:176b8275d35d | 1173 | /** |
<> | 135:176b8275d35d | 1174 | * @} |
<> | 135:176b8275d35d | 1175 | */ |
<> | 135:176b8275d35d | 1176 | #endif /* TIM16 */ |
<> | 135:176b8275d35d | 1177 | #if defined(TIM20) |
<> | 135:176b8275d35d | 1178 | /** @defgroup TIM_LL_EC_TIM20_ETR_ADC3_RMP TIM20 External Trigger ADC3 Remap |
<> | 135:176b8275d35d | 1179 | * @{ |
<> | 135:176b8275d35d | 1180 | */ |
<> | 135:176b8275d35d | 1181 | #define LL_TIM_TIM20_ETR_ADC3_RMP_NC (0x00000000U | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is not connected to ADC3 analog watchdog x */ |
<> | 135:176b8275d35d | 1182 | #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (TIM20_OR_ETR_RMP_0 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog */ |
<> | 135:176b8275d35d | 1183 | #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog 2 */ |
<> | 135:176b8275d35d | 1184 | #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (TIM20_OR_ETR_RMP_0 | TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog 3 */ |
<> | 135:176b8275d35d | 1185 | /** |
<> | 135:176b8275d35d | 1186 | * @} |
<> | 135:176b8275d35d | 1187 | */ |
<> | 135:176b8275d35d | 1188 | |
<> | 135:176b8275d35d | 1189 | /** @defgroup TIM_LL_EC_TIM20_ETR_ADC4_RMP TIM20 External Trigger ADC4 Remap |
<> | 135:176b8275d35d | 1190 | * @{ |
<> | 135:176b8275d35d | 1191 | */ |
<> | 135:176b8275d35d | 1192 | #define LL_TIM_TIM20_ETR_ADC4_RMP_NC (0x00000000U | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is not connected to ADC4 analog watchdog x */ |
<> | 135:176b8275d35d | 1193 | #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (TIM20_OR_ETR_RMP_2 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 1 */ |
<> | 135:176b8275d35d | 1194 | #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 2 */ |
<> | 135:176b8275d35d | 1195 | #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (TIM20_OR_ETR_RMP_2 | TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 3 */ |
<> | 135:176b8275d35d | 1196 | /** |
<> | 135:176b8275d35d | 1197 | * @} |
<> | 135:176b8275d35d | 1198 | */ |
<> | 135:176b8275d35d | 1199 | #endif /* TIM20 */ |
<> | 135:176b8275d35d | 1200 | #if defined(TIM14) |
<> | 135:176b8275d35d | 1201 | /** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input1 Remap |
<> | 135:176b8275d35d | 1202 | * @{ |
<> | 135:176b8275d35d | 1203 | */ |
<> | 135:176b8275d35d | 1204 | #define LL_TIM_TIM14_TI1_RMP_GPIO (0x00000000U | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to GPIO */ |
<> | 135:176b8275d35d | 1205 | #define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to RTC Clock */ |
<> | 135:176b8275d35d | 1206 | #define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to HSE/32 */ |
<> | 135:176b8275d35d | 1207 | #define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 | TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to MCO */ |
<> | 135:176b8275d35d | 1208 | /** |
<> | 135:176b8275d35d | 1209 | * @} |
<> | 135:176b8275d35d | 1210 | */ |
<> | 135:176b8275d35d | 1211 | #endif /* TIM14 */ |
<> | 135:176b8275d35d | 1212 | |
<> | 135:176b8275d35d | 1213 | #if defined(TIM_SMCR_OCCS) |
<> | 135:176b8275d35d | 1214 | /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection |
<> | 135:176b8275d35d | 1215 | * @{ |
<> | 135:176b8275d35d | 1216 | */ |
<> | 135:176b8275d35d | 1217 | #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */ |
<> | 135:176b8275d35d | 1218 | #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */ |
<> | 135:176b8275d35d | 1219 | /** |
<> | 135:176b8275d35d | 1220 | * @} |
<> | 135:176b8275d35d | 1221 | */ |
<> | 135:176b8275d35d | 1222 | #endif /* TIM_SMCR_OCCS*/ |
<> | 135:176b8275d35d | 1223 | |
<> | 135:176b8275d35d | 1224 | /** |
<> | 135:176b8275d35d | 1225 | * @} |
<> | 135:176b8275d35d | 1226 | */ |
<> | 135:176b8275d35d | 1227 | |
<> | 135:176b8275d35d | 1228 | /* Exported macro ------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 1229 | /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros |
<> | 135:176b8275d35d | 1230 | * @{ |
<> | 135:176b8275d35d | 1231 | */ |
<> | 135:176b8275d35d | 1232 | |
<> | 135:176b8275d35d | 1233 | /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros |
<> | 135:176b8275d35d | 1234 | * @{ |
<> | 135:176b8275d35d | 1235 | */ |
<> | 135:176b8275d35d | 1236 | /** |
<> | 135:176b8275d35d | 1237 | * @brief Write a value in TIM register. |
<> | 135:176b8275d35d | 1238 | * @param __INSTANCE__ TIM Instance |
<> | 135:176b8275d35d | 1239 | * @param __REG__ Register to be written |
<> | 135:176b8275d35d | 1240 | * @param __VALUE__ Value to be written in the register |
<> | 135:176b8275d35d | 1241 | * @retval None |
<> | 135:176b8275d35d | 1242 | */ |
<> | 135:176b8275d35d | 1243 | #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
<> | 135:176b8275d35d | 1244 | |
<> | 135:176b8275d35d | 1245 | /** |
<> | 135:176b8275d35d | 1246 | * @brief Read a value in TIM register. |
<> | 135:176b8275d35d | 1247 | * @param __INSTANCE__ TIM Instance |
<> | 135:176b8275d35d | 1248 | * @param __REG__ Register to be read |
<> | 135:176b8275d35d | 1249 | * @retval Register value |
<> | 135:176b8275d35d | 1250 | */ |
<> | 135:176b8275d35d | 1251 | #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
<> | 135:176b8275d35d | 1252 | /** |
<> | 135:176b8275d35d | 1253 | * @} |
<> | 135:176b8275d35d | 1254 | */ |
<> | 135:176b8275d35d | 1255 | |
<> | 135:176b8275d35d | 1256 | /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros |
<> | 135:176b8275d35d | 1257 | * @{ |
<> | 135:176b8275d35d | 1258 | */ |
<> | 135:176b8275d35d | 1259 | /** |
<> | 135:176b8275d35d | 1260 | * @brief HELPER macro retrieving the UIFCPY flag from the counter value. |
<> | 135:176b8275d35d | 1261 | * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); |
<> | 135:176b8275d35d | 1262 | * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied |
<> | 135:176b8275d35d | 1263 | * to TIMx_CNT register bit 31) |
<> | 135:176b8275d35d | 1264 | * @param __CNT__ Counter value |
<> | 135:176b8275d35d | 1265 | * @retval UIF status bit |
<> | 135:176b8275d35d | 1266 | */ |
<> | 135:176b8275d35d | 1267 | #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ |
<> | 135:176b8275d35d | 1268 | (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) |
<> | 135:176b8275d35d | 1269 | |
<> | 135:176b8275d35d | 1270 | /** |
<> | 135:176b8275d35d | 1271 | * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. |
<> | 135:176b8275d35d | 1272 | * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); |
<> | 135:176b8275d35d | 1273 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
<> | 135:176b8275d35d | 1274 | * @param __CKD__ This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1275 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
<> | 135:176b8275d35d | 1276 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
<> | 135:176b8275d35d | 1277 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
<> | 135:176b8275d35d | 1278 | * @param __DT__ deadtime duration (in ns) |
<> | 135:176b8275d35d | 1279 | * @retval DTG[0:7] |
<> | 135:176b8275d35d | 1280 | */ |
<> | 135:176b8275d35d | 1281 | #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ |
<> | 135:176b8275d35d | 1282 | ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ |
<> | 135:176b8275d35d | 1283 | (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\ |
<> | 135:176b8275d35d | 1284 | (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\ |
<> | 135:176b8275d35d | 1285 | (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\ |
<> | 135:176b8275d35d | 1286 | 0U) |
<> | 135:176b8275d35d | 1287 | |
<> | 135:176b8275d35d | 1288 | /** |
<> | 135:176b8275d35d | 1289 | * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. |
<> | 135:176b8275d35d | 1290 | * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); |
<> | 135:176b8275d35d | 1291 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
<> | 135:176b8275d35d | 1292 | * @param __CNTCLK__ counter clock frequency (in Hz) |
<> | 135:176b8275d35d | 1293 | * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 1294 | */ |
<> | 135:176b8275d35d | 1295 | #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ |
<> | 135:176b8275d35d | 1296 | ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U |
<> | 135:176b8275d35d | 1297 | |
<> | 135:176b8275d35d | 1298 | /** |
<> | 135:176b8275d35d | 1299 | * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. |
<> | 135:176b8275d35d | 1300 | * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); |
<> | 135:176b8275d35d | 1301 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
<> | 135:176b8275d35d | 1302 | * @param __PSC__ prescaler |
<> | 135:176b8275d35d | 1303 | * @param __FREQ__ output signal frequency (in Hz) |
<> | 135:176b8275d35d | 1304 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 1305 | */ |
<> | 135:176b8275d35d | 1306 | #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ |
<> | 135:176b8275d35d | 1307 | (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U |
<> | 135:176b8275d35d | 1308 | |
<> | 135:176b8275d35d | 1309 | /** |
<> | 135:176b8275d35d | 1310 | * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. |
<> | 135:176b8275d35d | 1311 | * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); |
<> | 135:176b8275d35d | 1312 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
<> | 135:176b8275d35d | 1313 | * @param __PSC__ prescaler |
<> | 135:176b8275d35d | 1314 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
<> | 135:176b8275d35d | 1315 | * @retval Compare value (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 1316 | */ |
<> | 135:176b8275d35d | 1317 | #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ |
<> | 135:176b8275d35d | 1318 | ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ |
<> | 135:176b8275d35d | 1319 | / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) |
<> | 135:176b8275d35d | 1320 | |
<> | 135:176b8275d35d | 1321 | /** |
<> | 135:176b8275d35d | 1322 | * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). |
<> | 135:176b8275d35d | 1323 | * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); |
<> | 135:176b8275d35d | 1324 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
<> | 135:176b8275d35d | 1325 | * @param __PSC__ prescaler |
<> | 135:176b8275d35d | 1326 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
<> | 135:176b8275d35d | 1327 | * @param __PULSE__ pulse duration (in us) |
<> | 135:176b8275d35d | 1328 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 1329 | */ |
<> | 135:176b8275d35d | 1330 | #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ |
<> | 135:176b8275d35d | 1331 | ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ |
<> | 135:176b8275d35d | 1332 | + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) |
<> | 135:176b8275d35d | 1333 | |
<> | 135:176b8275d35d | 1334 | /** |
<> | 135:176b8275d35d | 1335 | * @brief HELPER macro retrieving the ratio of the input capture prescaler |
<> | 135:176b8275d35d | 1336 | * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); |
<> | 135:176b8275d35d | 1337 | * @param __ICPSC__ This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1338 | * @arg @ref LL_TIM_ICPSC_DIV1 |
<> | 135:176b8275d35d | 1339 | * @arg @ref LL_TIM_ICPSC_DIV2 |
<> | 135:176b8275d35d | 1340 | * @arg @ref LL_TIM_ICPSC_DIV4 |
<> | 135:176b8275d35d | 1341 | * @arg @ref LL_TIM_ICPSC_DIV8 |
<> | 135:176b8275d35d | 1342 | * @retval Input capture prescaler ratio (1, 2, 4 or 8) |
<> | 135:176b8275d35d | 1343 | */ |
<> | 135:176b8275d35d | 1344 | #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ |
<> | 135:176b8275d35d | 1345 | ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) |
<> | 135:176b8275d35d | 1346 | |
<> | 135:176b8275d35d | 1347 | |
<> | 135:176b8275d35d | 1348 | /** |
<> | 135:176b8275d35d | 1349 | * @} |
<> | 135:176b8275d35d | 1350 | */ |
<> | 135:176b8275d35d | 1351 | |
<> | 135:176b8275d35d | 1352 | |
<> | 135:176b8275d35d | 1353 | /** |
<> | 135:176b8275d35d | 1354 | * @} |
<> | 135:176b8275d35d | 1355 | */ |
<> | 135:176b8275d35d | 1356 | |
<> | 135:176b8275d35d | 1357 | /* Exported functions --------------------------------------------------------*/ |
<> | 135:176b8275d35d | 1358 | /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions |
<> | 135:176b8275d35d | 1359 | * @{ |
<> | 135:176b8275d35d | 1360 | */ |
<> | 135:176b8275d35d | 1361 | |
<> | 135:176b8275d35d | 1362 | /** @defgroup TIM_LL_EF_Time_Base Time Base configuration |
<> | 135:176b8275d35d | 1363 | * @{ |
<> | 135:176b8275d35d | 1364 | */ |
<> | 135:176b8275d35d | 1365 | /** |
<> | 135:176b8275d35d | 1366 | * @brief Enable timer counter. |
<> | 135:176b8275d35d | 1367 | * @rmtoll CR1 CEN LL_TIM_EnableCounter |
<> | 135:176b8275d35d | 1368 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1369 | * @retval None |
<> | 135:176b8275d35d | 1370 | */ |
<> | 135:176b8275d35d | 1371 | __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1372 | { |
<> | 135:176b8275d35d | 1373 | SET_BIT(TIMx->CR1, TIM_CR1_CEN); |
<> | 135:176b8275d35d | 1374 | } |
<> | 135:176b8275d35d | 1375 | |
<> | 135:176b8275d35d | 1376 | /** |
<> | 135:176b8275d35d | 1377 | * @brief Disable timer counter. |
<> | 135:176b8275d35d | 1378 | * @rmtoll CR1 CEN LL_TIM_DisableCounter |
<> | 135:176b8275d35d | 1379 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1380 | * @retval None |
<> | 135:176b8275d35d | 1381 | */ |
<> | 135:176b8275d35d | 1382 | __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1383 | { |
<> | 135:176b8275d35d | 1384 | CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); |
<> | 135:176b8275d35d | 1385 | } |
<> | 135:176b8275d35d | 1386 | |
<> | 135:176b8275d35d | 1387 | /** |
<> | 135:176b8275d35d | 1388 | * @brief Indicates whether the timer counter is enabled. |
<> | 135:176b8275d35d | 1389 | * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter |
<> | 135:176b8275d35d | 1390 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1391 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 1392 | */ |
<> | 135:176b8275d35d | 1393 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1394 | { |
<> | 135:176b8275d35d | 1395 | return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)); |
<> | 135:176b8275d35d | 1396 | } |
<> | 135:176b8275d35d | 1397 | |
<> | 135:176b8275d35d | 1398 | /** |
<> | 135:176b8275d35d | 1399 | * @brief Enable update event generation. |
<> | 135:176b8275d35d | 1400 | * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent |
<> | 135:176b8275d35d | 1401 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1402 | * @retval None |
<> | 135:176b8275d35d | 1403 | */ |
<> | 135:176b8275d35d | 1404 | __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1405 | { |
<> | 135:176b8275d35d | 1406 | SET_BIT(TIMx->CR1, TIM_CR1_UDIS); |
<> | 135:176b8275d35d | 1407 | } |
<> | 135:176b8275d35d | 1408 | |
<> | 135:176b8275d35d | 1409 | /** |
<> | 135:176b8275d35d | 1410 | * @brief Disable update event generation. |
<> | 135:176b8275d35d | 1411 | * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent |
<> | 135:176b8275d35d | 1412 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1413 | * @retval None |
<> | 135:176b8275d35d | 1414 | */ |
<> | 135:176b8275d35d | 1415 | __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1416 | { |
<> | 135:176b8275d35d | 1417 | CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); |
<> | 135:176b8275d35d | 1418 | } |
<> | 135:176b8275d35d | 1419 | |
<> | 135:176b8275d35d | 1420 | /** |
<> | 135:176b8275d35d | 1421 | * @brief Indicates whether update event generation is enabled. |
<> | 135:176b8275d35d | 1422 | * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent |
<> | 135:176b8275d35d | 1423 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1424 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 1425 | */ |
<> | 135:176b8275d35d | 1426 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1427 | { |
<> | 135:176b8275d35d | 1428 | return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS)); |
<> | 135:176b8275d35d | 1429 | } |
<> | 135:176b8275d35d | 1430 | |
<> | 135:176b8275d35d | 1431 | /** |
<> | 135:176b8275d35d | 1432 | * @brief Set update event source |
<> | 135:176b8275d35d | 1433 | * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events |
<> | 135:176b8275d35d | 1434 | * generate an update interrupt or DMA request if enabled: |
<> | 135:176b8275d35d | 1435 | * - Counter overflow/underflow |
<> | 135:176b8275d35d | 1436 | * - Setting the UG bit |
<> | 135:176b8275d35d | 1437 | * - Update generation through the slave mode controller |
<> | 135:176b8275d35d | 1438 | * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter |
<> | 135:176b8275d35d | 1439 | * overflow/underflow generates an update interrupt or DMA request if enabled. |
<> | 135:176b8275d35d | 1440 | * @rmtoll CR1 URS LL_TIM_SetUpdateSource |
<> | 135:176b8275d35d | 1441 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1442 | * @param UpdateSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1443 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
<> | 135:176b8275d35d | 1444 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
<> | 135:176b8275d35d | 1445 | * @retval None |
<> | 135:176b8275d35d | 1446 | */ |
<> | 135:176b8275d35d | 1447 | __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) |
<> | 135:176b8275d35d | 1448 | { |
<> | 135:176b8275d35d | 1449 | MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); |
<> | 135:176b8275d35d | 1450 | } |
<> | 135:176b8275d35d | 1451 | |
<> | 135:176b8275d35d | 1452 | /** |
<> | 135:176b8275d35d | 1453 | * @brief Get actual event update source |
<> | 135:176b8275d35d | 1454 | * @rmtoll CR1 URS LL_TIM_GetUpdateSource |
<> | 135:176b8275d35d | 1455 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1456 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1457 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
<> | 135:176b8275d35d | 1458 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
<> | 135:176b8275d35d | 1459 | */ |
<> | 135:176b8275d35d | 1460 | __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1461 | { |
<> | 135:176b8275d35d | 1462 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); |
<> | 135:176b8275d35d | 1463 | } |
<> | 135:176b8275d35d | 1464 | |
<> | 135:176b8275d35d | 1465 | /** |
<> | 135:176b8275d35d | 1466 | * @brief Set one pulse mode (one shot v.s. repetitive). |
<> | 135:176b8275d35d | 1467 | * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode |
<> | 135:176b8275d35d | 1468 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1469 | * @param OnePulseMode This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1470 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
<> | 135:176b8275d35d | 1471 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
<> | 135:176b8275d35d | 1472 | * @retval None |
<> | 135:176b8275d35d | 1473 | */ |
<> | 135:176b8275d35d | 1474 | __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) |
<> | 135:176b8275d35d | 1475 | { |
<> | 135:176b8275d35d | 1476 | MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); |
<> | 135:176b8275d35d | 1477 | } |
<> | 135:176b8275d35d | 1478 | |
<> | 135:176b8275d35d | 1479 | /** |
<> | 135:176b8275d35d | 1480 | * @brief Get actual one pulse mode. |
<> | 135:176b8275d35d | 1481 | * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode |
<> | 135:176b8275d35d | 1482 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1483 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1484 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
<> | 135:176b8275d35d | 1485 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
<> | 135:176b8275d35d | 1486 | */ |
<> | 135:176b8275d35d | 1487 | __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1488 | { |
<> | 135:176b8275d35d | 1489 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); |
<> | 135:176b8275d35d | 1490 | } |
<> | 135:176b8275d35d | 1491 | |
<> | 135:176b8275d35d | 1492 | /** |
<> | 135:176b8275d35d | 1493 | * @brief Set the timer counter counting mode. |
<> | 135:176b8275d35d | 1494 | * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
<> | 135:176b8275d35d | 1495 | * check whether or not the counter mode selection feature is supported |
<> | 135:176b8275d35d | 1496 | * by a timer instance. |
<> | 135:176b8275d35d | 1497 | * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n |
<> | 135:176b8275d35d | 1498 | * CR1 CMS LL_TIM_SetCounterMode |
<> | 135:176b8275d35d | 1499 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1500 | * @param CounterMode This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1501 | * @arg @ref LL_TIM_COUNTERMODE_UP |
<> | 135:176b8275d35d | 1502 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
<> | 135:176b8275d35d | 1503 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
<> | 135:176b8275d35d | 1504 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
<> | 135:176b8275d35d | 1505 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
<> | 135:176b8275d35d | 1506 | * @retval None |
<> | 135:176b8275d35d | 1507 | */ |
<> | 135:176b8275d35d | 1508 | __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) |
<> | 135:176b8275d35d | 1509 | { |
<> | 135:176b8275d35d | 1510 | MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode); |
<> | 135:176b8275d35d | 1511 | } |
<> | 135:176b8275d35d | 1512 | |
<> | 135:176b8275d35d | 1513 | /** |
<> | 135:176b8275d35d | 1514 | * @brief Get actual counter mode. |
<> | 135:176b8275d35d | 1515 | * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
<> | 135:176b8275d35d | 1516 | * check whether or not the counter mode selection feature is supported |
<> | 135:176b8275d35d | 1517 | * by a timer instance. |
<> | 135:176b8275d35d | 1518 | * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n |
<> | 135:176b8275d35d | 1519 | * CR1 CMS LL_TIM_GetCounterMode |
<> | 135:176b8275d35d | 1520 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1521 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1522 | * @arg @ref LL_TIM_COUNTERMODE_UP |
<> | 135:176b8275d35d | 1523 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
<> | 135:176b8275d35d | 1524 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
<> | 135:176b8275d35d | 1525 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
<> | 135:176b8275d35d | 1526 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
<> | 135:176b8275d35d | 1527 | */ |
<> | 135:176b8275d35d | 1528 | __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1529 | { |
<> | 135:176b8275d35d | 1530 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); |
<> | 135:176b8275d35d | 1531 | } |
<> | 135:176b8275d35d | 1532 | |
<> | 135:176b8275d35d | 1533 | /** |
<> | 135:176b8275d35d | 1534 | * @brief Enable auto-reload (ARR) preload. |
<> | 135:176b8275d35d | 1535 | * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload |
<> | 135:176b8275d35d | 1536 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1537 | * @retval None |
<> | 135:176b8275d35d | 1538 | */ |
<> | 135:176b8275d35d | 1539 | __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1540 | { |
<> | 135:176b8275d35d | 1541 | SET_BIT(TIMx->CR1, TIM_CR1_ARPE); |
<> | 135:176b8275d35d | 1542 | } |
<> | 135:176b8275d35d | 1543 | |
<> | 135:176b8275d35d | 1544 | /** |
<> | 135:176b8275d35d | 1545 | * @brief Disable auto-reload (ARR) preload. |
<> | 135:176b8275d35d | 1546 | * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload |
<> | 135:176b8275d35d | 1547 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1548 | * @retval None |
<> | 135:176b8275d35d | 1549 | */ |
<> | 135:176b8275d35d | 1550 | __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1551 | { |
<> | 135:176b8275d35d | 1552 | CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); |
<> | 135:176b8275d35d | 1553 | } |
<> | 135:176b8275d35d | 1554 | |
<> | 135:176b8275d35d | 1555 | /** |
<> | 135:176b8275d35d | 1556 | * @brief Indicates whether auto-reload (ARR) preload is enabled. |
<> | 135:176b8275d35d | 1557 | * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload |
<> | 135:176b8275d35d | 1558 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1559 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 1560 | */ |
<> | 135:176b8275d35d | 1561 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1562 | { |
<> | 135:176b8275d35d | 1563 | return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)); |
<> | 135:176b8275d35d | 1564 | } |
<> | 135:176b8275d35d | 1565 | |
<> | 135:176b8275d35d | 1566 | /** |
<> | 135:176b8275d35d | 1567 | * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. |
<> | 135:176b8275d35d | 1568 | * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 1569 | * whether or not the clock division feature is supported by the timer |
<> | 135:176b8275d35d | 1570 | * instance. |
<> | 135:176b8275d35d | 1571 | * @rmtoll CR1 CKD LL_TIM_SetClockDivision |
<> | 135:176b8275d35d | 1572 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1573 | * @param ClockDivision This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1574 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
<> | 135:176b8275d35d | 1575 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
<> | 135:176b8275d35d | 1576 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
<> | 135:176b8275d35d | 1577 | * @retval None |
<> | 135:176b8275d35d | 1578 | */ |
<> | 135:176b8275d35d | 1579 | __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) |
<> | 135:176b8275d35d | 1580 | { |
<> | 135:176b8275d35d | 1581 | MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); |
<> | 135:176b8275d35d | 1582 | } |
<> | 135:176b8275d35d | 1583 | |
<> | 135:176b8275d35d | 1584 | /** |
<> | 135:176b8275d35d | 1585 | * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. |
<> | 135:176b8275d35d | 1586 | * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 1587 | * whether or not the clock division feature is supported by the timer |
<> | 135:176b8275d35d | 1588 | * instance. |
<> | 135:176b8275d35d | 1589 | * @rmtoll CR1 CKD LL_TIM_GetClockDivision |
<> | 135:176b8275d35d | 1590 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1591 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1592 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
<> | 135:176b8275d35d | 1593 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
<> | 135:176b8275d35d | 1594 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
<> | 135:176b8275d35d | 1595 | */ |
<> | 135:176b8275d35d | 1596 | __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1597 | { |
<> | 135:176b8275d35d | 1598 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); |
<> | 135:176b8275d35d | 1599 | } |
<> | 135:176b8275d35d | 1600 | |
<> | 135:176b8275d35d | 1601 | /** |
<> | 135:176b8275d35d | 1602 | * @brief Set the counter value. |
<> | 135:176b8275d35d | 1603 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 1604 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 1605 | * @rmtoll CNT CNT LL_TIM_SetCounter |
<> | 135:176b8275d35d | 1606 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1607 | * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) |
<> | 135:176b8275d35d | 1608 | * @retval None |
<> | 135:176b8275d35d | 1609 | */ |
<> | 135:176b8275d35d | 1610 | __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) |
<> | 135:176b8275d35d | 1611 | { |
<> | 135:176b8275d35d | 1612 | WRITE_REG(TIMx->CNT, Counter); |
<> | 135:176b8275d35d | 1613 | } |
<> | 135:176b8275d35d | 1614 | |
<> | 135:176b8275d35d | 1615 | /** |
<> | 135:176b8275d35d | 1616 | * @brief Get the counter value. |
<> | 135:176b8275d35d | 1617 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 1618 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 1619 | * @rmtoll CNT CNT LL_TIM_GetCounter |
<> | 135:176b8275d35d | 1620 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1621 | * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) |
<> | 135:176b8275d35d | 1622 | */ |
<> | 135:176b8275d35d | 1623 | __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1624 | { |
<> | 135:176b8275d35d | 1625 | return (uint32_t)(READ_REG(TIMx->CNT)); |
<> | 135:176b8275d35d | 1626 | } |
<> | 135:176b8275d35d | 1627 | |
<> | 135:176b8275d35d | 1628 | /** |
<> | 135:176b8275d35d | 1629 | * @brief Get the current direction of the counter |
<> | 135:176b8275d35d | 1630 | * @rmtoll CR1 DIR LL_TIM_GetDirection |
<> | 135:176b8275d35d | 1631 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1632 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1633 | * @arg @ref LL_TIM_COUNTERDIRECTION_UP |
<> | 135:176b8275d35d | 1634 | * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN |
<> | 135:176b8275d35d | 1635 | */ |
<> | 135:176b8275d35d | 1636 | __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1637 | { |
<> | 135:176b8275d35d | 1638 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); |
<> | 135:176b8275d35d | 1639 | } |
<> | 135:176b8275d35d | 1640 | |
<> | 135:176b8275d35d | 1641 | /** |
<> | 135:176b8275d35d | 1642 | * @brief Set the prescaler value. |
<> | 135:176b8275d35d | 1643 | * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). |
<> | 135:176b8275d35d | 1644 | * @note The prescaler can be changed on the fly as this control register is buffered. The new |
<> | 135:176b8275d35d | 1645 | * prescaler ratio is taken into account at the next update event. |
<> | 135:176b8275d35d | 1646 | * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter |
<> | 135:176b8275d35d | 1647 | * @rmtoll PSC PSC LL_TIM_SetPrescaler |
<> | 135:176b8275d35d | 1648 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1649 | * @param Prescaler between Min_Data=0 and Max_Data=65535 |
<> | 135:176b8275d35d | 1650 | * @retval None |
<> | 135:176b8275d35d | 1651 | */ |
<> | 135:176b8275d35d | 1652 | __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) |
<> | 135:176b8275d35d | 1653 | { |
<> | 135:176b8275d35d | 1654 | WRITE_REG(TIMx->PSC, Prescaler); |
<> | 135:176b8275d35d | 1655 | } |
<> | 135:176b8275d35d | 1656 | |
<> | 135:176b8275d35d | 1657 | /** |
<> | 135:176b8275d35d | 1658 | * @brief Get the prescaler value. |
<> | 135:176b8275d35d | 1659 | * @rmtoll PSC PSC LL_TIM_GetPrescaler |
<> | 135:176b8275d35d | 1660 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1661 | * @retval Prescaler value between Min_Data=0 and Max_Data=65535 |
<> | 135:176b8275d35d | 1662 | */ |
<> | 135:176b8275d35d | 1663 | __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1664 | { |
<> | 135:176b8275d35d | 1665 | return (uint32_t)(READ_REG(TIMx->PSC)); |
<> | 135:176b8275d35d | 1666 | } |
<> | 135:176b8275d35d | 1667 | |
<> | 135:176b8275d35d | 1668 | /** |
<> | 135:176b8275d35d | 1669 | * @brief Set the auto-reload value. |
<> | 135:176b8275d35d | 1670 | * @note The counter is blocked while the auto-reload value is null. |
<> | 135:176b8275d35d | 1671 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 1672 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 1673 | * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter |
<> | 135:176b8275d35d | 1674 | * @rmtoll ARR ARR LL_TIM_SetAutoReload |
<> | 135:176b8275d35d | 1675 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1676 | * @param AutoReload between Min_Data=0 and Max_Data=65535 |
<> | 135:176b8275d35d | 1677 | * @retval None |
<> | 135:176b8275d35d | 1678 | */ |
<> | 135:176b8275d35d | 1679 | __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) |
<> | 135:176b8275d35d | 1680 | { |
<> | 135:176b8275d35d | 1681 | WRITE_REG(TIMx->ARR, AutoReload); |
<> | 135:176b8275d35d | 1682 | } |
<> | 135:176b8275d35d | 1683 | |
<> | 135:176b8275d35d | 1684 | /** |
<> | 135:176b8275d35d | 1685 | * @brief Get the auto-reload value. |
<> | 135:176b8275d35d | 1686 | * @rmtoll ARR ARR LL_TIM_GetAutoReload |
<> | 135:176b8275d35d | 1687 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 1688 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 1689 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1690 | * @retval Auto-reload value |
<> | 135:176b8275d35d | 1691 | */ |
<> | 135:176b8275d35d | 1692 | __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1693 | { |
<> | 135:176b8275d35d | 1694 | return (uint32_t)(READ_REG(TIMx->ARR)); |
<> | 135:176b8275d35d | 1695 | } |
<> | 135:176b8275d35d | 1696 | |
<> | 135:176b8275d35d | 1697 | /** |
<> | 135:176b8275d35d | 1698 | * @brief Set the repetition counter value. |
<> | 135:176b8275d35d | 1699 | * @note For advanced timer instances RepetitionCounter can be up to 65535 except for STM32F373xC and STM32F378xx devices. |
<> | 135:176b8275d35d | 1700 | * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 1701 | * whether or not a timer instance supports a repetition counter. |
<> | 135:176b8275d35d | 1702 | * @rmtoll RCR REP LL_TIM_SetRepetitionCounter |
<> | 135:176b8275d35d | 1703 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1704 | * @param RepetitionCounter between Min_Data=0 and Max_Data=255 |
<> | 135:176b8275d35d | 1705 | * @retval None |
<> | 135:176b8275d35d | 1706 | */ |
<> | 135:176b8275d35d | 1707 | __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) |
<> | 135:176b8275d35d | 1708 | { |
<> | 135:176b8275d35d | 1709 | WRITE_REG(TIMx->RCR, RepetitionCounter); |
<> | 135:176b8275d35d | 1710 | } |
<> | 135:176b8275d35d | 1711 | |
<> | 135:176b8275d35d | 1712 | /** |
<> | 135:176b8275d35d | 1713 | * @brief Get the repetition counter value. |
<> | 135:176b8275d35d | 1714 | * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 1715 | * whether or not a timer instance supports a repetition counter. |
<> | 135:176b8275d35d | 1716 | * @rmtoll RCR REP LL_TIM_GetRepetitionCounter |
<> | 135:176b8275d35d | 1717 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1718 | * @retval Repetition counter value |
<> | 135:176b8275d35d | 1719 | */ |
<> | 135:176b8275d35d | 1720 | __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1721 | { |
<> | 135:176b8275d35d | 1722 | return (uint32_t)(READ_REG(TIMx->RCR)); |
<> | 135:176b8275d35d | 1723 | } |
<> | 135:176b8275d35d | 1724 | |
<> | 135:176b8275d35d | 1725 | #if defined(TIM_CR1_UIFREMAP) |
<> | 135:176b8275d35d | 1726 | /** |
<> | 135:176b8275d35d | 1727 | * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). |
<> | 135:176b8275d35d | 1728 | * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. |
<> | 135:176b8275d35d | 1729 | * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap |
<> | 135:176b8275d35d | 1730 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1731 | * @retval None |
<> | 135:176b8275d35d | 1732 | */ |
<> | 135:176b8275d35d | 1733 | __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1734 | { |
<> | 135:176b8275d35d | 1735 | SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); |
<> | 135:176b8275d35d | 1736 | } |
<> | 135:176b8275d35d | 1737 | |
<> | 135:176b8275d35d | 1738 | /** |
<> | 135:176b8275d35d | 1739 | * @brief Disable update interrupt flag (UIF) remapping. |
<> | 135:176b8275d35d | 1740 | * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap |
<> | 135:176b8275d35d | 1741 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1742 | * @retval None |
<> | 135:176b8275d35d | 1743 | */ |
<> | 135:176b8275d35d | 1744 | __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1745 | { |
<> | 135:176b8275d35d | 1746 | CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); |
<> | 135:176b8275d35d | 1747 | } |
<> | 135:176b8275d35d | 1748 | |
<> | 135:176b8275d35d | 1749 | #endif /* TIM_CR1_UIFREMAP */ |
<> | 135:176b8275d35d | 1750 | /** |
<> | 135:176b8275d35d | 1751 | * @} |
<> | 135:176b8275d35d | 1752 | */ |
<> | 135:176b8275d35d | 1753 | |
<> | 135:176b8275d35d | 1754 | /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration |
<> | 135:176b8275d35d | 1755 | * @{ |
<> | 135:176b8275d35d | 1756 | */ |
<> | 135:176b8275d35d | 1757 | /** |
<> | 135:176b8275d35d | 1758 | * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. |
<> | 135:176b8275d35d | 1759 | * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, |
<> | 135:176b8275d35d | 1760 | * they are updated only when a commutation event (COM) occurs. |
<> | 135:176b8275d35d | 1761 | * @note Only on channels that have a complementary output. |
<> | 135:176b8275d35d | 1762 | * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 1763 | * whether or not a timer instance is able to generate a commutation event. |
<> | 135:176b8275d35d | 1764 | * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload |
<> | 135:176b8275d35d | 1765 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1766 | * @retval None |
<> | 135:176b8275d35d | 1767 | */ |
<> | 135:176b8275d35d | 1768 | __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1769 | { |
<> | 135:176b8275d35d | 1770 | SET_BIT(TIMx->CR2, TIM_CR2_CCPC); |
<> | 135:176b8275d35d | 1771 | } |
<> | 135:176b8275d35d | 1772 | |
<> | 135:176b8275d35d | 1773 | /** |
<> | 135:176b8275d35d | 1774 | * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. |
<> | 135:176b8275d35d | 1775 | * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 1776 | * whether or not a timer instance is able to generate a commutation event. |
<> | 135:176b8275d35d | 1777 | * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload |
<> | 135:176b8275d35d | 1778 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1779 | * @retval None |
<> | 135:176b8275d35d | 1780 | */ |
<> | 135:176b8275d35d | 1781 | __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1782 | { |
<> | 135:176b8275d35d | 1783 | CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); |
<> | 135:176b8275d35d | 1784 | } |
<> | 135:176b8275d35d | 1785 | |
<> | 135:176b8275d35d | 1786 | /** |
<> | 135:176b8275d35d | 1787 | * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). |
<> | 135:176b8275d35d | 1788 | * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 1789 | * whether or not a timer instance is able to generate a commutation event. |
<> | 135:176b8275d35d | 1790 | * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate |
<> | 135:176b8275d35d | 1791 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1792 | * @param CCUpdateSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1793 | * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY |
<> | 135:176b8275d35d | 1794 | * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI |
<> | 135:176b8275d35d | 1795 | * @retval None |
<> | 135:176b8275d35d | 1796 | */ |
<> | 135:176b8275d35d | 1797 | __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) |
<> | 135:176b8275d35d | 1798 | { |
<> | 135:176b8275d35d | 1799 | MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); |
<> | 135:176b8275d35d | 1800 | } |
<> | 135:176b8275d35d | 1801 | |
<> | 135:176b8275d35d | 1802 | /** |
<> | 135:176b8275d35d | 1803 | * @brief Set the trigger of the capture/compare DMA request. |
<> | 135:176b8275d35d | 1804 | * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger |
<> | 135:176b8275d35d | 1805 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1806 | * @param DMAReqTrigger This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1807 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
<> | 135:176b8275d35d | 1808 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
<> | 135:176b8275d35d | 1809 | * @retval None |
<> | 135:176b8275d35d | 1810 | */ |
<> | 135:176b8275d35d | 1811 | __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) |
<> | 135:176b8275d35d | 1812 | { |
<> | 135:176b8275d35d | 1813 | MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); |
<> | 135:176b8275d35d | 1814 | } |
<> | 135:176b8275d35d | 1815 | |
<> | 135:176b8275d35d | 1816 | /** |
<> | 135:176b8275d35d | 1817 | * @brief Get actual trigger of the capture/compare DMA request. |
<> | 135:176b8275d35d | 1818 | * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger |
<> | 135:176b8275d35d | 1819 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1820 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 1821 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
<> | 135:176b8275d35d | 1822 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
<> | 135:176b8275d35d | 1823 | */ |
<> | 135:176b8275d35d | 1824 | __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 1825 | { |
<> | 135:176b8275d35d | 1826 | return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); |
<> | 135:176b8275d35d | 1827 | } |
<> | 135:176b8275d35d | 1828 | |
<> | 135:176b8275d35d | 1829 | /** |
<> | 135:176b8275d35d | 1830 | * @brief Set the lock level to freeze the |
<> | 135:176b8275d35d | 1831 | * configuration of several capture/compare parameters. |
<> | 135:176b8275d35d | 1832 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 1833 | * the lock mechanism is supported by a timer instance. |
<> | 135:176b8275d35d | 1834 | * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel |
<> | 135:176b8275d35d | 1835 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1836 | * @param LockLevel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1837 | * @arg @ref LL_TIM_LOCKLEVEL_OFF |
<> | 135:176b8275d35d | 1838 | * @arg @ref LL_TIM_LOCKLEVEL_1 |
<> | 135:176b8275d35d | 1839 | * @arg @ref LL_TIM_LOCKLEVEL_2 |
<> | 135:176b8275d35d | 1840 | * @arg @ref LL_TIM_LOCKLEVEL_3 |
<> | 135:176b8275d35d | 1841 | * @retval None |
<> | 135:176b8275d35d | 1842 | */ |
<> | 135:176b8275d35d | 1843 | __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) |
<> | 135:176b8275d35d | 1844 | { |
<> | 135:176b8275d35d | 1845 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); |
<> | 135:176b8275d35d | 1846 | } |
<> | 135:176b8275d35d | 1847 | |
<> | 135:176b8275d35d | 1848 | /** |
<> | 135:176b8275d35d | 1849 | * @brief Enable capture/compare channels. |
<> | 135:176b8275d35d | 1850 | * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n |
<> | 135:176b8275d35d | 1851 | * CCER CC1NE LL_TIM_CC_EnableChannel\n |
<> | 135:176b8275d35d | 1852 | * CCER CC2E LL_TIM_CC_EnableChannel\n |
<> | 135:176b8275d35d | 1853 | * CCER CC2NE LL_TIM_CC_EnableChannel\n |
<> | 135:176b8275d35d | 1854 | * CCER CC3E LL_TIM_CC_EnableChannel\n |
<> | 135:176b8275d35d | 1855 | * CCER CC3NE LL_TIM_CC_EnableChannel\n |
<> | 135:176b8275d35d | 1856 | * CCER CC4E LL_TIM_CC_EnableChannel\n |
<> | 135:176b8275d35d | 1857 | * CCER CC5E LL_TIM_CC_EnableChannel\n |
<> | 135:176b8275d35d | 1858 | * CCER CC6E LL_TIM_CC_EnableChannel |
<> | 135:176b8275d35d | 1859 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1860 | * @param Channels This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 1861 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 1862 | * @arg @ref LL_TIM_CHANNEL_CH1N |
<> | 135:176b8275d35d | 1863 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 1864 | * @arg @ref LL_TIM_CHANNEL_CH2N |
<> | 135:176b8275d35d | 1865 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 1866 | * @arg @ref LL_TIM_CHANNEL_CH3N |
<> | 135:176b8275d35d | 1867 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 1868 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 1869 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 1870 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 1871 | * @retval None |
<> | 135:176b8275d35d | 1872 | */ |
<> | 135:176b8275d35d | 1873 | __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
<> | 135:176b8275d35d | 1874 | { |
<> | 135:176b8275d35d | 1875 | SET_BIT(TIMx->CCER, Channels); |
<> | 135:176b8275d35d | 1876 | } |
<> | 135:176b8275d35d | 1877 | |
<> | 135:176b8275d35d | 1878 | /** |
<> | 135:176b8275d35d | 1879 | * @brief Disable capture/compare channels. |
<> | 135:176b8275d35d | 1880 | * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n |
<> | 135:176b8275d35d | 1881 | * CCER CC1NE LL_TIM_CC_DisableChannel\n |
<> | 135:176b8275d35d | 1882 | * CCER CC2E LL_TIM_CC_DisableChannel\n |
<> | 135:176b8275d35d | 1883 | * CCER CC2NE LL_TIM_CC_DisableChannel\n |
<> | 135:176b8275d35d | 1884 | * CCER CC3E LL_TIM_CC_DisableChannel\n |
<> | 135:176b8275d35d | 1885 | * CCER CC3NE LL_TIM_CC_DisableChannel\n |
<> | 135:176b8275d35d | 1886 | * CCER CC4E LL_TIM_CC_DisableChannel\n |
<> | 135:176b8275d35d | 1887 | * CCER CC5E LL_TIM_CC_DisableChannel\n |
<> | 135:176b8275d35d | 1888 | * CCER CC6E LL_TIM_CC_DisableChannel |
<> | 135:176b8275d35d | 1889 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1890 | * @param Channels This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 1891 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 1892 | * @arg @ref LL_TIM_CHANNEL_CH1N |
<> | 135:176b8275d35d | 1893 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 1894 | * @arg @ref LL_TIM_CHANNEL_CH2N |
<> | 135:176b8275d35d | 1895 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 1896 | * @arg @ref LL_TIM_CHANNEL_CH3N |
<> | 135:176b8275d35d | 1897 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 1898 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 1899 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 1900 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 1901 | * @retval None |
<> | 135:176b8275d35d | 1902 | */ |
<> | 135:176b8275d35d | 1903 | __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
<> | 135:176b8275d35d | 1904 | { |
<> | 135:176b8275d35d | 1905 | CLEAR_BIT(TIMx->CCER, Channels); |
<> | 135:176b8275d35d | 1906 | } |
<> | 135:176b8275d35d | 1907 | |
<> | 135:176b8275d35d | 1908 | /** |
<> | 135:176b8275d35d | 1909 | * @brief Indicate whether channel(s) is(are) enabled. |
<> | 135:176b8275d35d | 1910 | * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n |
<> | 135:176b8275d35d | 1911 | * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n |
<> | 135:176b8275d35d | 1912 | * CCER CC2E LL_TIM_CC_IsEnabledChannel\n |
<> | 135:176b8275d35d | 1913 | * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n |
<> | 135:176b8275d35d | 1914 | * CCER CC3E LL_TIM_CC_IsEnabledChannel\n |
<> | 135:176b8275d35d | 1915 | * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n |
<> | 135:176b8275d35d | 1916 | * CCER CC4E LL_TIM_CC_IsEnabledChannel\n |
<> | 135:176b8275d35d | 1917 | * CCER CC5E LL_TIM_CC_IsEnabledChannel\n |
<> | 135:176b8275d35d | 1918 | * CCER CC6E LL_TIM_CC_IsEnabledChannel |
<> | 135:176b8275d35d | 1919 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1920 | * @param Channels This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 1921 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 1922 | * @arg @ref LL_TIM_CHANNEL_CH1N |
<> | 135:176b8275d35d | 1923 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 1924 | * @arg @ref LL_TIM_CHANNEL_CH2N |
<> | 135:176b8275d35d | 1925 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 1926 | * @arg @ref LL_TIM_CHANNEL_CH3N |
<> | 135:176b8275d35d | 1927 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 1928 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 1929 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 1930 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 1931 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 1932 | */ |
<> | 135:176b8275d35d | 1933 | __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
<> | 135:176b8275d35d | 1934 | { |
<> | 135:176b8275d35d | 1935 | return (READ_BIT(TIMx->CCER, Channels) == (Channels)); |
<> | 135:176b8275d35d | 1936 | } |
<> | 135:176b8275d35d | 1937 | |
<> | 135:176b8275d35d | 1938 | /** |
<> | 135:176b8275d35d | 1939 | * @} |
<> | 135:176b8275d35d | 1940 | */ |
<> | 135:176b8275d35d | 1941 | |
<> | 135:176b8275d35d | 1942 | /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration |
<> | 135:176b8275d35d | 1943 | * @{ |
<> | 135:176b8275d35d | 1944 | */ |
<> | 135:176b8275d35d | 1945 | /** |
<> | 135:176b8275d35d | 1946 | * @brief Configure an output channel. |
<> | 135:176b8275d35d | 1947 | * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1948 | * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1949 | * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1950 | * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1951 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 1952 | * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1953 | * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1954 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 1955 | * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1956 | * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1957 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 1958 | * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1959 | * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1960 | * @endif |
<> | 135:176b8275d35d | 1961 | * CCER CC1P LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1962 | * CCER CC2P LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1963 | * CCER CC3P LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1964 | * CCER CC4P LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1965 | * CCER CC5P LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1966 | * CCER CC6P LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1967 | * CR2 OIS1 LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1968 | * CR2 OIS2 LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1969 | * CR2 OIS3 LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1970 | * CR2 OIS4 LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1971 | * CR2 OIS5 LL_TIM_OC_ConfigOutput\n |
<> | 135:176b8275d35d | 1972 | * CR2 OIS6 LL_TIM_OC_ConfigOutput |
<> | 135:176b8275d35d | 1973 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 1974 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 1975 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 1976 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 1977 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 1978 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 1979 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 1980 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 1981 | * @param Configuration This parameter must be a combination of all the following values: |
<> | 135:176b8275d35d | 1982 | * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW |
<> | 135:176b8275d35d | 1983 | * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH |
<> | 135:176b8275d35d | 1984 | * @note CH3 CH4 CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 1985 | * @retval None |
<> | 135:176b8275d35d | 1986 | */ |
<> | 135:176b8275d35d | 1987 | __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
<> | 135:176b8275d35d | 1988 | { |
<> | 135:176b8275d35d | 1989 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 1990 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 1991 | CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); |
<> | 135:176b8275d35d | 1992 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), |
<> | 135:176b8275d35d | 1993 | (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); |
<> | 135:176b8275d35d | 1994 | MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), |
<> | 135:176b8275d35d | 1995 | (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); |
<> | 135:176b8275d35d | 1996 | } |
<> | 135:176b8275d35d | 1997 | |
<> | 135:176b8275d35d | 1998 | /** |
<> | 135:176b8275d35d | 1999 | * @brief Define the behavior of the output reference signal OCxREF from which |
<> | 135:176b8275d35d | 2000 | * OCx and OCxN (when relevant) are derived. |
<> | 135:176b8275d35d | 2001 | * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n |
<> | 135:176b8275d35d | 2002 | * CCMR1 OC2M LL_TIM_OC_SetMode\n |
<> | 135:176b8275d35d | 2003 | * CCMR2 OC3M LL_TIM_OC_SetMode\n |
<> | 135:176b8275d35d | 2004 | * CCMR2 OC4M LL_TIM_OC_SetMode\n |
<> | 135:176b8275d35d | 2005 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2006 | * CCMR3 OC5M LL_TIM_OC_SetMode\n |
<> | 135:176b8275d35d | 2007 | * CCMR3 OC6M LL_TIM_OC_SetMode |
<> | 135:176b8275d35d | 2008 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2009 | * CCMR3 OC5M LL_TIM_OC_SetMode\n |
<> | 135:176b8275d35d | 2010 | * CCMR3 OC6M LL_TIM_OC_SetMode |
<> | 135:176b8275d35d | 2011 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2012 | * CCMR3 OC5M LL_TIM_OC_SetMode\n |
<> | 135:176b8275d35d | 2013 | * CCMR3 OC6M LL_TIM_OC_SetMode |
<> | 135:176b8275d35d | 2014 | * @endif |
<> | 135:176b8275d35d | 2015 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2016 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2017 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2018 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2019 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2020 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2021 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2022 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2023 | * @param Mode This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2024 | * @arg @ref LL_TIM_OCMODE_FROZEN |
<> | 135:176b8275d35d | 2025 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
<> | 135:176b8275d35d | 2026 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
<> | 135:176b8275d35d | 2027 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
<> | 135:176b8275d35d | 2028 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
<> | 135:176b8275d35d | 2029 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
<> | 135:176b8275d35d | 2030 | * @arg @ref LL_TIM_OCMODE_PWM1 |
<> | 135:176b8275d35d | 2031 | * @arg @ref LL_TIM_OCMODE_PWM2 |
<> | 135:176b8275d35d | 2032 | * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 |
<> | 135:176b8275d35d | 2033 | * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 |
<> | 135:176b8275d35d | 2034 | * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 |
<> | 135:176b8275d35d | 2035 | * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 |
<> | 135:176b8275d35d | 2036 | * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 |
<> | 135:176b8275d35d | 2037 | * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 |
<> | 135:176b8275d35d | 2038 | * @note The following OC modes are not available on all F3 devices : |
<> | 135:176b8275d35d | 2039 | * - LL_TIM_OCMODE_RETRIG_OPM1 |
<> | 135:176b8275d35d | 2040 | * - LL_TIM_OCMODE_RETRIG_OPM2 |
<> | 135:176b8275d35d | 2041 | * - LL_TIM_OCMODE_COMBINED_PWM1 |
<> | 135:176b8275d35d | 2042 | * - LL_TIM_OCMODE_COMBINED_PWM2 |
<> | 135:176b8275d35d | 2043 | * - LL_TIM_OCMODE_ASSYMETRIC_PWM1 |
<> | 135:176b8275d35d | 2044 | * - LL_TIM_OCMODE_ASSYMETRIC_PWM2 |
<> | 135:176b8275d35d | 2045 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2046 | * @retval None |
<> | 135:176b8275d35d | 2047 | */ |
<> | 135:176b8275d35d | 2048 | __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) |
<> | 135:176b8275d35d | 2049 | { |
<> | 135:176b8275d35d | 2050 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2051 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2052 | MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); |
<> | 135:176b8275d35d | 2053 | } |
<> | 135:176b8275d35d | 2054 | |
<> | 135:176b8275d35d | 2055 | /** |
<> | 135:176b8275d35d | 2056 | * @brief Get the output compare mode of an output channel. |
<> | 135:176b8275d35d | 2057 | * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n |
<> | 135:176b8275d35d | 2058 | * CCMR1 OC2M LL_TIM_OC_GetMode\n |
<> | 135:176b8275d35d | 2059 | * CCMR2 OC3M LL_TIM_OC_GetMode\n |
<> | 135:176b8275d35d | 2060 | * CCMR2 OC4M LL_TIM_OC_GetMode\n |
<> | 135:176b8275d35d | 2061 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2062 | * CCMR3 OC5M LL_TIM_OC_GetMode\n |
<> | 135:176b8275d35d | 2063 | * CCMR3 OC6M LL_TIM_OC_GetMode |
<> | 135:176b8275d35d | 2064 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2065 | * CCMR3 OC5M LL_TIM_OC_GetMode\n |
<> | 135:176b8275d35d | 2066 | * CCMR3 OC6M LL_TIM_OC_GetMode |
<> | 135:176b8275d35d | 2067 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2068 | * CCMR3 OC5M LL_TIM_OC_GetMode\n |
<> | 135:176b8275d35d | 2069 | * CCMR3 OC6M LL_TIM_OC_GetMode |
<> | 135:176b8275d35d | 2070 | * @endif |
<> | 135:176b8275d35d | 2071 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2072 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2073 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2074 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2075 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2076 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2077 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2078 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2079 | * @note The following OC modes are not available on all F3 devices : |
<> | 135:176b8275d35d | 2080 | * - LL_TIM_OCMODE_RETRIG_OPM1 |
<> | 135:176b8275d35d | 2081 | * - LL_TIM_OCMODE_RETRIG_OPM2 |
<> | 135:176b8275d35d | 2082 | * - LL_TIM_OCMODE_COMBINED_PWM1 |
<> | 135:176b8275d35d | 2083 | * - LL_TIM_OCMODE_COMBINED_PWM2 |
<> | 135:176b8275d35d | 2084 | * - LL_TIM_OCMODE_ASSYMETRIC_PWM1 |
<> | 135:176b8275d35d | 2085 | * - LL_TIM_OCMODE_ASSYMETRIC_PWM2 |
<> | 135:176b8275d35d | 2086 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2087 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 2088 | * @arg @ref LL_TIM_OCMODE_FROZEN |
<> | 135:176b8275d35d | 2089 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
<> | 135:176b8275d35d | 2090 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
<> | 135:176b8275d35d | 2091 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
<> | 135:176b8275d35d | 2092 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
<> | 135:176b8275d35d | 2093 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
<> | 135:176b8275d35d | 2094 | * @arg @ref LL_TIM_OCMODE_PWM1 |
<> | 135:176b8275d35d | 2095 | * @arg @ref LL_TIM_OCMODE_PWM2 |
<> | 135:176b8275d35d | 2096 | * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 |
<> | 135:176b8275d35d | 2097 | * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 |
<> | 135:176b8275d35d | 2098 | * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 |
<> | 135:176b8275d35d | 2099 | * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 |
<> | 135:176b8275d35d | 2100 | * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 |
<> | 135:176b8275d35d | 2101 | * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 |
<> | 135:176b8275d35d | 2102 | */ |
<> | 135:176b8275d35d | 2103 | __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2104 | { |
<> | 135:176b8275d35d | 2105 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2106 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2107 | return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); |
<> | 135:176b8275d35d | 2108 | } |
<> | 135:176b8275d35d | 2109 | |
<> | 135:176b8275d35d | 2110 | /** |
<> | 135:176b8275d35d | 2111 | * @brief Set the polarity of an output channel. |
<> | 135:176b8275d35d | 2112 | * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n |
<> | 135:176b8275d35d | 2113 | * CCER CC1NP LL_TIM_OC_SetPolarity\n |
<> | 135:176b8275d35d | 2114 | * CCER CC2P LL_TIM_OC_SetPolarity\n |
<> | 135:176b8275d35d | 2115 | * CCER CC2NP LL_TIM_OC_SetPolarity\n |
<> | 135:176b8275d35d | 2116 | * CCER CC3P LL_TIM_OC_SetPolarity\n |
<> | 135:176b8275d35d | 2117 | * CCER CC3NP LL_TIM_OC_SetPolarity\n |
<> | 135:176b8275d35d | 2118 | * CCER CC4P LL_TIM_OC_SetPolarity\n |
<> | 135:176b8275d35d | 2119 | * CCER CC5P LL_TIM_OC_SetPolarity\n |
<> | 135:176b8275d35d | 2120 | * CCER CC6P LL_TIM_OC_SetPolarity |
<> | 135:176b8275d35d | 2121 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2122 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2123 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2124 | * @arg @ref LL_TIM_CHANNEL_CH1N |
<> | 135:176b8275d35d | 2125 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2126 | * @arg @ref LL_TIM_CHANNEL_CH2N |
<> | 135:176b8275d35d | 2127 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2128 | * @arg @ref LL_TIM_CHANNEL_CH3N |
<> | 135:176b8275d35d | 2129 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2130 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2131 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2132 | * @param Polarity This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2133 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
<> | 135:176b8275d35d | 2134 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
<> | 135:176b8275d35d | 2135 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2136 | * @retval None |
<> | 135:176b8275d35d | 2137 | */ |
<> | 135:176b8275d35d | 2138 | __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) |
<> | 135:176b8275d35d | 2139 | { |
<> | 135:176b8275d35d | 2140 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2141 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); |
<> | 135:176b8275d35d | 2142 | } |
<> | 135:176b8275d35d | 2143 | |
<> | 135:176b8275d35d | 2144 | /** |
<> | 135:176b8275d35d | 2145 | * @brief Get the polarity of an output channel. |
<> | 135:176b8275d35d | 2146 | * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n |
<> | 135:176b8275d35d | 2147 | * CCER CC1NP LL_TIM_OC_GetPolarity\n |
<> | 135:176b8275d35d | 2148 | * CCER CC2P LL_TIM_OC_GetPolarity\n |
<> | 135:176b8275d35d | 2149 | * CCER CC2NP LL_TIM_OC_GetPolarity\n |
<> | 135:176b8275d35d | 2150 | * CCER CC3P LL_TIM_OC_GetPolarity\n |
<> | 135:176b8275d35d | 2151 | * CCER CC3NP LL_TIM_OC_GetPolarity\n |
<> | 135:176b8275d35d | 2152 | * CCER CC4P LL_TIM_OC_GetPolarity\n |
<> | 135:176b8275d35d | 2153 | * CCER CC5P LL_TIM_OC_GetPolarity\n |
<> | 135:176b8275d35d | 2154 | * CCER CC6P LL_TIM_OC_GetPolarity |
<> | 135:176b8275d35d | 2155 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2156 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2157 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2158 | * @arg @ref LL_TIM_CHANNEL_CH1N |
<> | 135:176b8275d35d | 2159 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2160 | * @arg @ref LL_TIM_CHANNEL_CH2N |
<> | 135:176b8275d35d | 2161 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2162 | * @arg @ref LL_TIM_CHANNEL_CH3N |
<> | 135:176b8275d35d | 2163 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2164 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2165 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2166 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2167 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 2168 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
<> | 135:176b8275d35d | 2169 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
<> | 135:176b8275d35d | 2170 | */ |
<> | 135:176b8275d35d | 2171 | __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2172 | { |
<> | 135:176b8275d35d | 2173 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2174 | return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); |
<> | 135:176b8275d35d | 2175 | } |
<> | 135:176b8275d35d | 2176 | |
<> | 135:176b8275d35d | 2177 | /** |
<> | 135:176b8275d35d | 2178 | * @brief Set the IDLE state of an output channel |
<> | 135:176b8275d35d | 2179 | * @note This function is significant only for the timer instances |
<> | 135:176b8275d35d | 2180 | * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) |
<> | 135:176b8275d35d | 2181 | * can be used to check whether or not a timer instance provides |
<> | 135:176b8275d35d | 2182 | * a break input. |
<> | 135:176b8275d35d | 2183 | * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n |
<> | 135:176b8275d35d | 2184 | * CR2 OIS2N LL_TIM_OC_SetIdleState\n |
<> | 135:176b8275d35d | 2185 | * CR2 OIS2 LL_TIM_OC_SetIdleState\n |
<> | 135:176b8275d35d | 2186 | * CR2 OIS2N LL_TIM_OC_SetIdleState\n |
<> | 135:176b8275d35d | 2187 | * CR2 OIS3 LL_TIM_OC_SetIdleState\n |
<> | 135:176b8275d35d | 2188 | * CR2 OIS3N LL_TIM_OC_SetIdleState\n |
<> | 135:176b8275d35d | 2189 | * CR2 OIS4 LL_TIM_OC_SetIdleState\n |
<> | 135:176b8275d35d | 2190 | * CR2 OIS5 LL_TIM_OC_SetIdleState\n |
<> | 135:176b8275d35d | 2191 | * CR2 OIS6 LL_TIM_OC_SetIdleState |
<> | 135:176b8275d35d | 2192 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2193 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2194 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2195 | * @arg @ref LL_TIM_CHANNEL_CH1N |
<> | 135:176b8275d35d | 2196 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2197 | * @arg @ref LL_TIM_CHANNEL_CH2N |
<> | 135:176b8275d35d | 2198 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2199 | * @arg @ref LL_TIM_CHANNEL_CH3N |
<> | 135:176b8275d35d | 2200 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2201 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2202 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2203 | * @param IdleState This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2204 | * @arg @ref LL_TIM_OCIDLESTATE_LOW |
<> | 135:176b8275d35d | 2205 | * @arg @ref LL_TIM_OCIDLESTATE_HIGH |
<> | 135:176b8275d35d | 2206 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2207 | * @retval None |
<> | 135:176b8275d35d | 2208 | */ |
<> | 135:176b8275d35d | 2209 | __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) |
<> | 135:176b8275d35d | 2210 | { |
<> | 135:176b8275d35d | 2211 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2212 | MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); |
<> | 135:176b8275d35d | 2213 | } |
<> | 135:176b8275d35d | 2214 | |
<> | 135:176b8275d35d | 2215 | /** |
<> | 135:176b8275d35d | 2216 | * @brief Get the IDLE state of an output channel |
<> | 135:176b8275d35d | 2217 | * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n |
<> | 135:176b8275d35d | 2218 | * CR2 OIS2N LL_TIM_OC_GetIdleState\n |
<> | 135:176b8275d35d | 2219 | * CR2 OIS2 LL_TIM_OC_GetIdleState\n |
<> | 135:176b8275d35d | 2220 | * CR2 OIS2N LL_TIM_OC_GetIdleState\n |
<> | 135:176b8275d35d | 2221 | * CR2 OIS3 LL_TIM_OC_GetIdleState\n |
<> | 135:176b8275d35d | 2222 | * CR2 OIS3N LL_TIM_OC_GetIdleState\n |
<> | 135:176b8275d35d | 2223 | * CR2 OIS4 LL_TIM_OC_GetIdleState\n |
<> | 135:176b8275d35d | 2224 | * CR2 OIS5 LL_TIM_OC_GetIdleState\n |
<> | 135:176b8275d35d | 2225 | * CR2 OIS6 LL_TIM_OC_GetIdleState |
<> | 135:176b8275d35d | 2226 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2227 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2228 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2229 | * @arg @ref LL_TIM_CHANNEL_CH1N |
<> | 135:176b8275d35d | 2230 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2231 | * @arg @ref LL_TIM_CHANNEL_CH2N |
<> | 135:176b8275d35d | 2232 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2233 | * @arg @ref LL_TIM_CHANNEL_CH3N |
<> | 135:176b8275d35d | 2234 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2235 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2236 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2237 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2238 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 2239 | * @arg @ref LL_TIM_OCIDLESTATE_LOW |
<> | 135:176b8275d35d | 2240 | * @arg @ref LL_TIM_OCIDLESTATE_HIGH |
<> | 135:176b8275d35d | 2241 | */ |
<> | 135:176b8275d35d | 2242 | __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2243 | { |
<> | 135:176b8275d35d | 2244 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2245 | return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); |
<> | 135:176b8275d35d | 2246 | } |
<> | 135:176b8275d35d | 2247 | |
<> | 135:176b8275d35d | 2248 | /** |
<> | 135:176b8275d35d | 2249 | * @brief Enable fast mode for the output channel. |
<> | 135:176b8275d35d | 2250 | * @note Acts only if the channel is configured in PWM1 or PWM2 mode. |
<> | 135:176b8275d35d | 2251 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n |
<> | 135:176b8275d35d | 2252 | * CCMR1 OC2FE LL_TIM_OC_EnableFast\n |
<> | 135:176b8275d35d | 2253 | * CCMR2 OC3FE LL_TIM_OC_EnableFast\n |
<> | 135:176b8275d35d | 2254 | * CCMR2 OC4FE LL_TIM_OC_EnableFast\n |
<> | 135:176b8275d35d | 2255 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2256 | * CCMR3 OC5FE LL_TIM_OC_EnableFast\n |
<> | 135:176b8275d35d | 2257 | * CCMR3 OC6FE LL_TIM_OC_EnableFast |
<> | 135:176b8275d35d | 2258 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2259 | * CCMR3 OC5FE LL_TIM_OC_EnableFast\n |
<> | 135:176b8275d35d | 2260 | * CCMR3 OC6FE LL_TIM_OC_EnableFast |
<> | 135:176b8275d35d | 2261 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2262 | * CCMR3 OC5FE LL_TIM_OC_EnableFast\n |
<> | 135:176b8275d35d | 2263 | * CCMR3 OC6FE LL_TIM_OC_EnableFast |
<> | 135:176b8275d35d | 2264 | * @endif |
<> | 135:176b8275d35d | 2265 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2266 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2267 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2268 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2269 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2270 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2271 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2272 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2273 | * @note OC5FE and OC6FE are not available for all F3 devices |
<> | 135:176b8275d35d | 2274 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2275 | * @retval None |
<> | 135:176b8275d35d | 2276 | */ |
<> | 135:176b8275d35d | 2277 | __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2278 | { |
<> | 135:176b8275d35d | 2279 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2280 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2281 | SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
<> | 135:176b8275d35d | 2282 | |
<> | 135:176b8275d35d | 2283 | } |
<> | 135:176b8275d35d | 2284 | |
<> | 135:176b8275d35d | 2285 | /** |
<> | 135:176b8275d35d | 2286 | * @brief Disable fast mode for the output channel. |
<> | 135:176b8275d35d | 2287 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n |
<> | 135:176b8275d35d | 2288 | * CCMR1 OC2FE LL_TIM_OC_DisableFast\n |
<> | 135:176b8275d35d | 2289 | * CCMR2 OC3FE LL_TIM_OC_DisableFast\n |
<> | 135:176b8275d35d | 2290 | * CCMR2 OC4FE LL_TIM_OC_DisableFast\n |
<> | 135:176b8275d35d | 2291 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2292 | * CCMR3 OC5FE LL_TIM_OC_DisableFast\n |
<> | 135:176b8275d35d | 2293 | * CCMR3 OC6FE LL_TIM_OC_DisableFast |
<> | 135:176b8275d35d | 2294 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2295 | * CCMR3 OC5FE LL_TIM_OC_DisableFast\n |
<> | 135:176b8275d35d | 2296 | * CCMR3 OC6FE LL_TIM_OC_DisableFast |
<> | 135:176b8275d35d | 2297 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2298 | * CCMR3 OC5FE LL_TIM_OC_DisableFast\n |
<> | 135:176b8275d35d | 2299 | * CCMR3 OC6FE LL_TIM_OC_DisableFast |
<> | 135:176b8275d35d | 2300 | * @endif |
<> | 135:176b8275d35d | 2301 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2302 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2303 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2304 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2305 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2306 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2307 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2308 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2309 | * @note OC5FE and OC6FE are not available for all F3 devices |
<> | 135:176b8275d35d | 2310 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2311 | * @retval None |
<> | 135:176b8275d35d | 2312 | */ |
<> | 135:176b8275d35d | 2313 | __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2314 | { |
<> | 135:176b8275d35d | 2315 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2316 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2317 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
<> | 135:176b8275d35d | 2318 | |
<> | 135:176b8275d35d | 2319 | } |
<> | 135:176b8275d35d | 2320 | |
<> | 135:176b8275d35d | 2321 | /** |
<> | 135:176b8275d35d | 2322 | * @brief Indicates whether fast mode is enabled for the output channel. |
<> | 135:176b8275d35d | 2323 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n |
<> | 135:176b8275d35d | 2324 | * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n |
<> | 135:176b8275d35d | 2325 | * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n |
<> | 135:176b8275d35d | 2326 | * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n |
<> | 135:176b8275d35d | 2327 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2328 | * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n |
<> | 135:176b8275d35d | 2329 | * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast |
<> | 135:176b8275d35d | 2330 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2331 | * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n |
<> | 135:176b8275d35d | 2332 | * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast |
<> | 135:176b8275d35d | 2333 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2334 | * CCMR3 OC5FE LL_TIM_OC_DisableFast\n |
<> | 135:176b8275d35d | 2335 | * CCMR3 OC6FE LL_TIM_OC_DisableFast |
<> | 135:176b8275d35d | 2336 | * @endif |
<> | 135:176b8275d35d | 2337 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2338 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2339 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2340 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2341 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2342 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2343 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2344 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2345 | * @note OC5FE and OC6FE are not available for all F3 devices |
<> | 135:176b8275d35d | 2346 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2347 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2348 | */ |
<> | 135:176b8275d35d | 2349 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2350 | { |
<> | 135:176b8275d35d | 2351 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2352 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2353 | register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; |
<> | 135:176b8275d35d | 2354 | return (READ_BIT(*pReg, bitfield) == bitfield); |
<> | 135:176b8275d35d | 2355 | } |
<> | 135:176b8275d35d | 2356 | |
<> | 135:176b8275d35d | 2357 | /** |
<> | 135:176b8275d35d | 2358 | * @brief Enable compare register (TIMx_CCRx) preload for the output channel. |
<> | 135:176b8275d35d | 2359 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n |
<> | 135:176b8275d35d | 2360 | * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n |
<> | 135:176b8275d35d | 2361 | * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n |
<> | 135:176b8275d35d | 2362 | * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n |
<> | 135:176b8275d35d | 2363 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2364 | * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n |
<> | 135:176b8275d35d | 2365 | * CCMR3 OC6PE LL_TIM_OC_EnablePreload |
<> | 135:176b8275d35d | 2366 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2367 | * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n |
<> | 135:176b8275d35d | 2368 | * CCMR3 OC6PE LL_TIM_OC_EnablePreload |
<> | 135:176b8275d35d | 2369 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2370 | * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n |
<> | 135:176b8275d35d | 2371 | * CCMR3 OC6PE LL_TIM_OC_EnablePreload |
<> | 135:176b8275d35d | 2372 | * @endif |
<> | 135:176b8275d35d | 2373 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2374 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2375 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2376 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2377 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2378 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2379 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2380 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2381 | * @note OC5PE and OC6PE are not available for all F3 devices |
<> | 135:176b8275d35d | 2382 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2383 | * @retval None |
<> | 135:176b8275d35d | 2384 | */ |
<> | 135:176b8275d35d | 2385 | __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2386 | { |
<> | 135:176b8275d35d | 2387 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2388 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2389 | SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
<> | 135:176b8275d35d | 2390 | } |
<> | 135:176b8275d35d | 2391 | |
<> | 135:176b8275d35d | 2392 | /** |
<> | 135:176b8275d35d | 2393 | * @brief Disable compare register (TIMx_CCRx) preload for the output channel. |
<> | 135:176b8275d35d | 2394 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n |
<> | 135:176b8275d35d | 2395 | * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n |
<> | 135:176b8275d35d | 2396 | * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n |
<> | 135:176b8275d35d | 2397 | * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n |
<> | 135:176b8275d35d | 2398 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2399 | * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n |
<> | 135:176b8275d35d | 2400 | * CCMR3 OC6PE LL_TIM_OC_DisablePreload |
<> | 135:176b8275d35d | 2401 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2402 | * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n |
<> | 135:176b8275d35d | 2403 | * CCMR3 OC6PE LL_TIM_OC_DisablePreload |
<> | 135:176b8275d35d | 2404 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2405 | * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n |
<> | 135:176b8275d35d | 2406 | * CCMR3 OC6PE LL_TIM_OC_DisablePreload |
<> | 135:176b8275d35d | 2407 | * @endif |
<> | 135:176b8275d35d | 2408 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2409 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2410 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2411 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2412 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2413 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2414 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2415 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2416 | * @note OC5PE and OC6PE are not available for all F3 devices |
<> | 135:176b8275d35d | 2417 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2418 | * @retval None |
<> | 135:176b8275d35d | 2419 | */ |
<> | 135:176b8275d35d | 2420 | __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2421 | { |
<> | 135:176b8275d35d | 2422 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2423 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2424 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
<> | 135:176b8275d35d | 2425 | } |
<> | 135:176b8275d35d | 2426 | |
<> | 135:176b8275d35d | 2427 | /** |
<> | 135:176b8275d35d | 2428 | * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. |
<> | 135:176b8275d35d | 2429 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n |
<> | 135:176b8275d35d | 2430 | * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n |
<> | 135:176b8275d35d | 2431 | * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n |
<> | 135:176b8275d35d | 2432 | * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n |
<> | 135:176b8275d35d | 2433 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2434 | * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n |
<> | 135:176b8275d35d | 2435 | * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload |
<> | 135:176b8275d35d | 2436 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2437 | * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n |
<> | 135:176b8275d35d | 2438 | * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload |
<> | 135:176b8275d35d | 2439 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2440 | * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n |
<> | 135:176b8275d35d | 2441 | * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload |
<> | 135:176b8275d35d | 2442 | * @endif |
<> | 135:176b8275d35d | 2443 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2444 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2445 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2446 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2447 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2448 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2449 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2450 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2451 | * @note OC5PE and OC6PE are not available for all F3 devices |
<> | 135:176b8275d35d | 2452 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2453 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2454 | */ |
<> | 135:176b8275d35d | 2455 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2456 | { |
<> | 135:176b8275d35d | 2457 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2458 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2459 | register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; |
<> | 135:176b8275d35d | 2460 | return (READ_BIT(*pReg, bitfield) == bitfield); |
<> | 135:176b8275d35d | 2461 | } |
<> | 135:176b8275d35d | 2462 | |
<> | 135:176b8275d35d | 2463 | /** |
<> | 135:176b8275d35d | 2464 | * @brief Enable clearing the output channel on an external event. |
<> | 135:176b8275d35d | 2465 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
<> | 135:176b8275d35d | 2466 | * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
<> | 135:176b8275d35d | 2467 | * or not a timer instance can clear the OCxREF signal on an external event. |
<> | 135:176b8275d35d | 2468 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n |
<> | 135:176b8275d35d | 2469 | * CCMR1 OC2CE LL_TIM_OC_EnableClear\n |
<> | 135:176b8275d35d | 2470 | * CCMR2 OC3CE LL_TIM_OC_EnableClear\n |
<> | 135:176b8275d35d | 2471 | * CCMR2 OC4CE LL_TIM_OC_EnableClear\n |
<> | 135:176b8275d35d | 2472 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2473 | * CCMR3 OC5CE LL_TIM_OC_EnableClear\n |
<> | 135:176b8275d35d | 2474 | * CCMR3 OC6CE LL_TIM_OC_EnableClear |
<> | 135:176b8275d35d | 2475 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2476 | * CCMR3 OC5CE LL_TIM_OC_EnableClear\n |
<> | 135:176b8275d35d | 2477 | * CCMR3 OC6CE LL_TIM_OC_EnableClear |
<> | 135:176b8275d35d | 2478 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2479 | * CCMR3 OC5CE LL_TIM_OC_EnableClear\n |
<> | 135:176b8275d35d | 2480 | * CCMR3 OC6CE LL_TIM_OC_EnableClear |
<> | 135:176b8275d35d | 2481 | * @endif |
<> | 135:176b8275d35d | 2482 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2483 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2484 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2485 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2486 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2487 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2488 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2489 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2490 | * @note OC5CE and OC6CE are not available for all F3 devices |
<> | 135:176b8275d35d | 2491 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2492 | * @retval None |
<> | 135:176b8275d35d | 2493 | */ |
<> | 135:176b8275d35d | 2494 | __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2495 | { |
<> | 135:176b8275d35d | 2496 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2497 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2498 | SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
<> | 135:176b8275d35d | 2499 | } |
<> | 135:176b8275d35d | 2500 | |
<> | 135:176b8275d35d | 2501 | /** |
<> | 135:176b8275d35d | 2502 | * @brief Disable clearing the output channel on an external event. |
<> | 135:176b8275d35d | 2503 | * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
<> | 135:176b8275d35d | 2504 | * or not a timer instance can clear the OCxREF signal on an external event. |
<> | 135:176b8275d35d | 2505 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n |
<> | 135:176b8275d35d | 2506 | * CCMR1 OC2CE LL_TIM_OC_DisableClear\n |
<> | 135:176b8275d35d | 2507 | * CCMR2 OC3CE LL_TIM_OC_DisableClear\n |
<> | 135:176b8275d35d | 2508 | * CCMR2 OC4CE LL_TIM_OC_DisableClear\n |
<> | 135:176b8275d35d | 2509 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2510 | * CCMR3 OC5CE LL_TIM_OC_DisableClear\n |
<> | 135:176b8275d35d | 2511 | * CCMR3 OC6CE LL_TIM_OC_DisableClear |
<> | 135:176b8275d35d | 2512 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2513 | * CCMR3 OC5CE LL_TIM_OC_DisableClear\n |
<> | 135:176b8275d35d | 2514 | * CCMR3 OC6CE LL_TIM_OC_DisableClear |
<> | 135:176b8275d35d | 2515 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2516 | * CCMR3 OC5CE LL_TIM_OC_DisableClear\n |
<> | 135:176b8275d35d | 2517 | * CCMR3 OC6CE LL_TIM_OC_DisableClear |
<> | 135:176b8275d35d | 2518 | * @endif |
<> | 135:176b8275d35d | 2519 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2520 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2521 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2522 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2523 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2524 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2525 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2526 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2527 | * @note OC5CE and OC6CE are not available for all F3 devices |
<> | 135:176b8275d35d | 2528 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2529 | * @retval None |
<> | 135:176b8275d35d | 2530 | */ |
<> | 135:176b8275d35d | 2531 | __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2532 | { |
<> | 135:176b8275d35d | 2533 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2534 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2535 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
<> | 135:176b8275d35d | 2536 | } |
<> | 135:176b8275d35d | 2537 | |
<> | 135:176b8275d35d | 2538 | /** |
<> | 135:176b8275d35d | 2539 | * @brief Indicates clearing the output channel on an external event is enabled for the output channel. |
<> | 135:176b8275d35d | 2540 | * @note This function enables clearing the output channel on an external event. |
<> | 135:176b8275d35d | 2541 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
<> | 135:176b8275d35d | 2542 | * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
<> | 135:176b8275d35d | 2543 | * or not a timer instance can clear the OCxREF signal on an external event. |
<> | 135:176b8275d35d | 2544 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n |
<> | 135:176b8275d35d | 2545 | * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n |
<> | 135:176b8275d35d | 2546 | * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n |
<> | 135:176b8275d35d | 2547 | * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n |
<> | 135:176b8275d35d | 2548 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2549 | * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n |
<> | 135:176b8275d35d | 2550 | * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear |
<> | 135:176b8275d35d | 2551 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2552 | * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n |
<> | 135:176b8275d35d | 2553 | * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear |
<> | 135:176b8275d35d | 2554 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2555 | * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n |
<> | 135:176b8275d35d | 2556 | * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear |
<> | 135:176b8275d35d | 2557 | * @endif |
<> | 135:176b8275d35d | 2558 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2559 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2560 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2561 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2562 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2563 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2564 | * @arg @ref LL_TIM_CHANNEL_CH5 |
<> | 135:176b8275d35d | 2565 | * @arg @ref LL_TIM_CHANNEL_CH6 |
<> | 135:176b8275d35d | 2566 | * @note OC5CE and OC6CE are not available for all F3 devices |
<> | 135:176b8275d35d | 2567 | * @note CH5 and CH6 channels are not available for all F3 devices |
<> | 135:176b8275d35d | 2568 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 2569 | */ |
<> | 135:176b8275d35d | 2570 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2571 | { |
<> | 135:176b8275d35d | 2572 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2573 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2574 | register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; |
<> | 135:176b8275d35d | 2575 | return (READ_BIT(*pReg, bitfield) == bitfield); |
<> | 135:176b8275d35d | 2576 | } |
<> | 135:176b8275d35d | 2577 | |
<> | 135:176b8275d35d | 2578 | /** |
<> | 135:176b8275d35d | 2579 | * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals). |
<> | 135:176b8275d35d | 2580 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 2581 | * dead-time insertion feature is supported by a timer instance. |
<> | 135:176b8275d35d | 2582 | * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter |
<> | 135:176b8275d35d | 2583 | * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime |
<> | 135:176b8275d35d | 2584 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2585 | * @param DeadTime between Min_Data=0 and Max_Data=255 |
<> | 135:176b8275d35d | 2586 | * @retval None |
<> | 135:176b8275d35d | 2587 | */ |
<> | 135:176b8275d35d | 2588 | __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) |
<> | 135:176b8275d35d | 2589 | { |
<> | 135:176b8275d35d | 2590 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); |
<> | 135:176b8275d35d | 2591 | } |
<> | 135:176b8275d35d | 2592 | |
<> | 135:176b8275d35d | 2593 | /** |
<> | 135:176b8275d35d | 2594 | * @brief Set compare value for output channel 1 (TIMx_CCR1). |
<> | 135:176b8275d35d | 2595 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
<> | 135:176b8275d35d | 2596 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 2597 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 2598 | * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 2599 | * output channel 1 is supported by a timer instance. |
<> | 135:176b8275d35d | 2600 | * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 |
<> | 135:176b8275d35d | 2601 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2602 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
<> | 135:176b8275d35d | 2603 | * @retval None |
<> | 135:176b8275d35d | 2604 | */ |
<> | 135:176b8275d35d | 2605 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) |
<> | 135:176b8275d35d | 2606 | { |
<> | 135:176b8275d35d | 2607 | WRITE_REG(TIMx->CCR1, CompareValue); |
<> | 135:176b8275d35d | 2608 | } |
<> | 135:176b8275d35d | 2609 | |
<> | 135:176b8275d35d | 2610 | /** |
<> | 135:176b8275d35d | 2611 | * @brief Set compare value for output channel 2 (TIMx_CCR2). |
<> | 135:176b8275d35d | 2612 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
<> | 135:176b8275d35d | 2613 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 2614 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 2615 | * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 2616 | * output channel 2 is supported by a timer instance. |
<> | 135:176b8275d35d | 2617 | * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 |
<> | 135:176b8275d35d | 2618 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2619 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
<> | 135:176b8275d35d | 2620 | * @retval None |
<> | 135:176b8275d35d | 2621 | */ |
<> | 135:176b8275d35d | 2622 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) |
<> | 135:176b8275d35d | 2623 | { |
<> | 135:176b8275d35d | 2624 | WRITE_REG(TIMx->CCR2, CompareValue); |
<> | 135:176b8275d35d | 2625 | } |
<> | 135:176b8275d35d | 2626 | |
<> | 135:176b8275d35d | 2627 | /** |
<> | 135:176b8275d35d | 2628 | * @brief Set compare value for output channel 3 (TIMx_CCR3). |
<> | 135:176b8275d35d | 2629 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
<> | 135:176b8275d35d | 2630 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 2631 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 2632 | * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 2633 | * output channel is supported by a timer instance. |
<> | 135:176b8275d35d | 2634 | * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 |
<> | 135:176b8275d35d | 2635 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2636 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
<> | 135:176b8275d35d | 2637 | * @retval None |
<> | 135:176b8275d35d | 2638 | */ |
<> | 135:176b8275d35d | 2639 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) |
<> | 135:176b8275d35d | 2640 | { |
<> | 135:176b8275d35d | 2641 | WRITE_REG(TIMx->CCR3, CompareValue); |
<> | 135:176b8275d35d | 2642 | } |
<> | 135:176b8275d35d | 2643 | |
<> | 135:176b8275d35d | 2644 | /** |
<> | 135:176b8275d35d | 2645 | * @brief Set compare value for output channel 4 (TIMx_CCR4). |
<> | 135:176b8275d35d | 2646 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
<> | 135:176b8275d35d | 2647 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 2648 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 2649 | * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 2650 | * output channel 4 is supported by a timer instance. |
<> | 135:176b8275d35d | 2651 | * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 |
<> | 135:176b8275d35d | 2652 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2653 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
<> | 135:176b8275d35d | 2654 | * @retval None |
<> | 135:176b8275d35d | 2655 | */ |
<> | 135:176b8275d35d | 2656 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) |
<> | 135:176b8275d35d | 2657 | { |
<> | 135:176b8275d35d | 2658 | WRITE_REG(TIMx->CCR4, CompareValue); |
<> | 135:176b8275d35d | 2659 | } |
<> | 135:176b8275d35d | 2660 | |
<> | 135:176b8275d35d | 2661 | #if defined(TIM_CCR5_CCR5) |
<> | 135:176b8275d35d | 2662 | /** |
<> | 135:176b8275d35d | 2663 | * @brief Set compare value for output channel 5 (TIMx_CCR5). |
<> | 135:176b8275d35d | 2664 | * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 2665 | * output channel 5 is supported by a timer instance. |
<> | 135:176b8275d35d | 2666 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2667 | * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 |
<> | 135:176b8275d35d | 2668 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2669 | * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 |
<> | 135:176b8275d35d | 2670 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2671 | * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 |
<> | 135:176b8275d35d | 2672 | * @endif |
<> | 135:176b8275d35d | 2673 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2674 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
<> | 135:176b8275d35d | 2675 | * @note CH5 channel is not available for all F3 devices |
<> | 135:176b8275d35d | 2676 | * @retval None |
<> | 135:176b8275d35d | 2677 | */ |
<> | 135:176b8275d35d | 2678 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) |
<> | 135:176b8275d35d | 2679 | { |
<> | 135:176b8275d35d | 2680 | WRITE_REG(TIMx->CCR5, CompareValue); |
<> | 135:176b8275d35d | 2681 | } |
<> | 135:176b8275d35d | 2682 | |
<> | 135:176b8275d35d | 2683 | #endif /* TIM_CCR5_CCR5 */ |
<> | 135:176b8275d35d | 2684 | #if defined(TIM_CCR6_CCR6) |
<> | 135:176b8275d35d | 2685 | /** |
<> | 135:176b8275d35d | 2686 | * @brief Set compare value for output channel 6 (TIMx_CCR6). |
<> | 135:176b8275d35d | 2687 | * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 2688 | * output channel 6 is supported by a timer instance. |
<> | 135:176b8275d35d | 2689 | * @if STM32F344x8 |
<> | 135:176b8275d35d | 2690 | * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 |
<> | 135:176b8275d35d | 2691 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2692 | * CCR6 CCR6 LL_TIM_OC_SetCompareCH6 |
<> | 135:176b8275d35d | 2693 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2694 | * CCR6 CCR6 LL_TIM_OC_SetCompareCH6 |
<> | 135:176b8275d35d | 2695 | * @endif |
<> | 135:176b8275d35d | 2696 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2697 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
<> | 135:176b8275d35d | 2698 | * @note CH6 channel is not available for all F3 devices |
<> | 135:176b8275d35d | 2699 | * @retval None |
<> | 135:176b8275d35d | 2700 | */ |
<> | 135:176b8275d35d | 2701 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) |
<> | 135:176b8275d35d | 2702 | { |
<> | 135:176b8275d35d | 2703 | WRITE_REG(TIMx->CCR6, CompareValue); |
<> | 135:176b8275d35d | 2704 | } |
<> | 135:176b8275d35d | 2705 | |
<> | 135:176b8275d35d | 2706 | #endif /* TIM_CCR6_CCR6 */ |
<> | 135:176b8275d35d | 2707 | /** |
<> | 135:176b8275d35d | 2708 | * @brief Get compare value (TIMx_CCR1) set for output channel 1. |
<> | 135:176b8275d35d | 2709 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
<> | 135:176b8275d35d | 2710 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 2711 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 2712 | * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 2713 | * output channel 1 is supported by a timer instance. |
<> | 135:176b8275d35d | 2714 | * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 |
<> | 135:176b8275d35d | 2715 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2716 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 2717 | */ |
<> | 135:176b8275d35d | 2718 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 2719 | { |
<> | 135:176b8275d35d | 2720 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
<> | 135:176b8275d35d | 2721 | } |
<> | 135:176b8275d35d | 2722 | |
<> | 135:176b8275d35d | 2723 | /** |
<> | 135:176b8275d35d | 2724 | * @brief Get compare value (TIMx_CCR2) set for output channel 2. |
<> | 135:176b8275d35d | 2725 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
<> | 135:176b8275d35d | 2726 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 2727 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 2728 | * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 2729 | * output channel 2 is supported by a timer instance. |
<> | 135:176b8275d35d | 2730 | * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 |
<> | 135:176b8275d35d | 2731 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2732 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 2733 | */ |
<> | 135:176b8275d35d | 2734 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 2735 | { |
<> | 135:176b8275d35d | 2736 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
<> | 135:176b8275d35d | 2737 | } |
<> | 135:176b8275d35d | 2738 | |
<> | 135:176b8275d35d | 2739 | /** |
<> | 135:176b8275d35d | 2740 | * @brief Get compare value (TIMx_CCR3) set for output channel 3. |
<> | 135:176b8275d35d | 2741 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
<> | 135:176b8275d35d | 2742 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 2743 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 2744 | * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 2745 | * output channel 3 is supported by a timer instance. |
<> | 135:176b8275d35d | 2746 | * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 |
<> | 135:176b8275d35d | 2747 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2748 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 2749 | */ |
<> | 135:176b8275d35d | 2750 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 2751 | { |
<> | 135:176b8275d35d | 2752 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
<> | 135:176b8275d35d | 2753 | } |
<> | 135:176b8275d35d | 2754 | |
<> | 135:176b8275d35d | 2755 | /** |
<> | 135:176b8275d35d | 2756 | * @brief Get compare value (TIMx_CCR4) set for output channel 4. |
<> | 135:176b8275d35d | 2757 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
<> | 135:176b8275d35d | 2758 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 2759 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 2760 | * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 2761 | * output channel 4 is supported by a timer instance. |
<> | 135:176b8275d35d | 2762 | * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 |
<> | 135:176b8275d35d | 2763 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2764 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 2765 | */ |
<> | 135:176b8275d35d | 2766 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 2767 | { |
<> | 135:176b8275d35d | 2768 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
<> | 135:176b8275d35d | 2769 | } |
<> | 135:176b8275d35d | 2770 | |
<> | 135:176b8275d35d | 2771 | #if defined(TIM_CCR5_CCR5) |
<> | 135:176b8275d35d | 2772 | /** |
<> | 135:176b8275d35d | 2773 | * @brief Get compare value (TIMx_CCR5) set for output channel 5. |
<> | 135:176b8275d35d | 2774 | * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 2775 | * output channel 5 is supported by a timer instance. |
<> | 135:176b8275d35d | 2776 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2777 | * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 |
<> | 135:176b8275d35d | 2778 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2779 | * CCR5 CCR5 LL_TIM_OC_GetCompareCH5 |
<> | 135:176b8275d35d | 2780 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2781 | * CCR5 CCR5 LL_TIM_OC_GetCompareCH5 |
<> | 135:176b8275d35d | 2782 | * @endif |
<> | 135:176b8275d35d | 2783 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2784 | * @note CH5 channel is not available for all F3 devices |
<> | 135:176b8275d35d | 2785 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 2786 | */ |
<> | 135:176b8275d35d | 2787 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 2788 | { |
<> | 135:176b8275d35d | 2789 | return (uint32_t)(READ_REG(TIMx->CCR5)); |
<> | 135:176b8275d35d | 2790 | } |
<> | 135:176b8275d35d | 2791 | |
<> | 135:176b8275d35d | 2792 | #endif /* TIM_CCR5_CCR5 */ |
<> | 135:176b8275d35d | 2793 | #if defined(TIM_CCR6_CCR6) |
<> | 135:176b8275d35d | 2794 | /** |
<> | 135:176b8275d35d | 2795 | * @brief Get compare value (TIMx_CCR6) set for output channel 6. |
<> | 135:176b8275d35d | 2796 | * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 2797 | * output channel 6 is supported by a timer instance. |
<> | 135:176b8275d35d | 2798 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2799 | * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 |
<> | 135:176b8275d35d | 2800 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2801 | * CCR6 CCR6 LL_TIM_OC_GetCompareCH6 |
<> | 135:176b8275d35d | 2802 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2803 | * CCR6 CCR6 LL_TIM_OC_GetCompareCH6 |
<> | 135:176b8275d35d | 2804 | * @endif |
<> | 135:176b8275d35d | 2805 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2806 | * @note CH6 channel is not available for all F3 devices |
<> | 135:176b8275d35d | 2807 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 2808 | */ |
<> | 135:176b8275d35d | 2809 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 2810 | { |
<> | 135:176b8275d35d | 2811 | return (uint32_t)(READ_REG(TIMx->CCR6)); |
<> | 135:176b8275d35d | 2812 | } |
<> | 135:176b8275d35d | 2813 | |
<> | 135:176b8275d35d | 2814 | #endif /* TIM_CCR6_CCR6 */ |
<> | 135:176b8275d35d | 2815 | #if defined(TIM_CCR5_CCR5) |
<> | 135:176b8275d35d | 2816 | /** |
<> | 135:176b8275d35d | 2817 | * @brief Select on which reference signal the OC5REF is combined to. |
<> | 135:176b8275d35d | 2818 | * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 2819 | * whether or not a timer instance supports the combined 3-phase PWM mode. |
<> | 135:176b8275d35d | 2820 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 2821 | * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n |
<> | 135:176b8275d35d | 2822 | * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n |
<> | 135:176b8275d35d | 2823 | * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels |
<> | 135:176b8275d35d | 2824 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 2825 | * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n |
<> | 135:176b8275d35d | 2826 | * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n |
<> | 135:176b8275d35d | 2827 | * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels |
<> | 135:176b8275d35d | 2828 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 2829 | * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n |
<> | 135:176b8275d35d | 2830 | * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n |
<> | 135:176b8275d35d | 2831 | * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels |
<> | 135:176b8275d35d | 2832 | * @endif |
<> | 135:176b8275d35d | 2833 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2834 | * @param GroupCH5 This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2835 | * @arg @ref LL_TIM_GROUPCH5_NONE |
<> | 135:176b8275d35d | 2836 | * @arg @ref LL_TIM_GROUPCH5_OC1REFC |
<> | 135:176b8275d35d | 2837 | * @arg @ref LL_TIM_GROUPCH5_OC2REFC |
<> | 135:176b8275d35d | 2838 | * @arg @ref LL_TIM_GROUPCH5_OC3REFC |
<> | 135:176b8275d35d | 2839 | * @note CH5 channel is not available for all F3 devices |
<> | 135:176b8275d35d | 2840 | * @retval None |
<> | 135:176b8275d35d | 2841 | */ |
<> | 135:176b8275d35d | 2842 | __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) |
<> | 135:176b8275d35d | 2843 | { |
<> | 135:176b8275d35d | 2844 | MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5); |
<> | 135:176b8275d35d | 2845 | } |
<> | 135:176b8275d35d | 2846 | |
<> | 135:176b8275d35d | 2847 | #endif /* TIM_CCR5_CCR5 */ |
<> | 135:176b8275d35d | 2848 | /** |
<> | 135:176b8275d35d | 2849 | * @} |
<> | 135:176b8275d35d | 2850 | */ |
<> | 135:176b8275d35d | 2851 | |
<> | 135:176b8275d35d | 2852 | /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration |
<> | 135:176b8275d35d | 2853 | * @{ |
<> | 135:176b8275d35d | 2854 | */ |
<> | 135:176b8275d35d | 2855 | /** |
<> | 135:176b8275d35d | 2856 | * @brief Configure input channel. |
<> | 135:176b8275d35d | 2857 | * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2858 | * CCMR1 IC1PSC LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2859 | * CCMR1 IC1F LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2860 | * CCMR1 CC2S LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2861 | * CCMR1 IC2PSC LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2862 | * CCMR1 IC2F LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2863 | * CCMR2 CC3S LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2864 | * CCMR2 IC3PSC LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2865 | * CCMR2 IC3F LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2866 | * CCMR2 CC4S LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2867 | * CCMR2 IC4PSC LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2868 | * CCMR2 IC4F LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2869 | * CCER CC1P LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2870 | * CCER CC1NP LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2871 | * CCER CC2P LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2872 | * CCER CC2NP LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2873 | * CCER CC3P LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2874 | * CCER CC3NP LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2875 | * CCER CC4P LL_TIM_IC_Config\n |
<> | 135:176b8275d35d | 2876 | * CCER CC4NP LL_TIM_IC_Config |
<> | 135:176b8275d35d | 2877 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2878 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2879 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2880 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2881 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2882 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2883 | * @param Configuration This parameter must be a combination of all the following values: |
<> | 135:176b8275d35d | 2884 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC |
<> | 135:176b8275d35d | 2885 | * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 |
<> | 135:176b8275d35d | 2886 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 |
<> | 135:176b8275d35d | 2887 | * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE |
<> | 135:176b8275d35d | 2888 | * @retval None |
<> | 135:176b8275d35d | 2889 | */ |
<> | 135:176b8275d35d | 2890 | __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
<> | 135:176b8275d35d | 2891 | { |
<> | 135:176b8275d35d | 2892 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2893 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2894 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), |
<> | 135:176b8275d35d | 2895 | ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); |
<> | 135:176b8275d35d | 2896 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
<> | 135:176b8275d35d | 2897 | (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); |
<> | 135:176b8275d35d | 2898 | } |
<> | 135:176b8275d35d | 2899 | |
<> | 135:176b8275d35d | 2900 | /** |
<> | 135:176b8275d35d | 2901 | * @brief Set the active input. |
<> | 135:176b8275d35d | 2902 | * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n |
<> | 135:176b8275d35d | 2903 | * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n |
<> | 135:176b8275d35d | 2904 | * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n |
<> | 135:176b8275d35d | 2905 | * CCMR2 CC4S LL_TIM_IC_SetActiveInput |
<> | 135:176b8275d35d | 2906 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2907 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2908 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2909 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2910 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2911 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2912 | * @param ICActiveInput This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2913 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
<> | 135:176b8275d35d | 2914 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
<> | 135:176b8275d35d | 2915 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
<> | 135:176b8275d35d | 2916 | * @retval None |
<> | 135:176b8275d35d | 2917 | */ |
<> | 135:176b8275d35d | 2918 | __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) |
<> | 135:176b8275d35d | 2919 | { |
<> | 135:176b8275d35d | 2920 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2921 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2922 | MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
<> | 135:176b8275d35d | 2923 | } |
<> | 135:176b8275d35d | 2924 | |
<> | 135:176b8275d35d | 2925 | /** |
<> | 135:176b8275d35d | 2926 | * @brief Get the current active input. |
<> | 135:176b8275d35d | 2927 | * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n |
<> | 135:176b8275d35d | 2928 | * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n |
<> | 135:176b8275d35d | 2929 | * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n |
<> | 135:176b8275d35d | 2930 | * CCMR2 CC4S LL_TIM_IC_GetActiveInput |
<> | 135:176b8275d35d | 2931 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2932 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2933 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2934 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2935 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2936 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2937 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 2938 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
<> | 135:176b8275d35d | 2939 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
<> | 135:176b8275d35d | 2940 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
<> | 135:176b8275d35d | 2941 | */ |
<> | 135:176b8275d35d | 2942 | __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2943 | { |
<> | 135:176b8275d35d | 2944 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2945 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2946 | return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
<> | 135:176b8275d35d | 2947 | } |
<> | 135:176b8275d35d | 2948 | |
<> | 135:176b8275d35d | 2949 | /** |
<> | 135:176b8275d35d | 2950 | * @brief Set the prescaler of input channel. |
<> | 135:176b8275d35d | 2951 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n |
<> | 135:176b8275d35d | 2952 | * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n |
<> | 135:176b8275d35d | 2953 | * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n |
<> | 135:176b8275d35d | 2954 | * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler |
<> | 135:176b8275d35d | 2955 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2956 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2957 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2958 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2959 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2960 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2961 | * @param ICPrescaler This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2962 | * @arg @ref LL_TIM_ICPSC_DIV1 |
<> | 135:176b8275d35d | 2963 | * @arg @ref LL_TIM_ICPSC_DIV2 |
<> | 135:176b8275d35d | 2964 | * @arg @ref LL_TIM_ICPSC_DIV4 |
<> | 135:176b8275d35d | 2965 | * @arg @ref LL_TIM_ICPSC_DIV8 |
<> | 135:176b8275d35d | 2966 | * @retval None |
<> | 135:176b8275d35d | 2967 | */ |
<> | 135:176b8275d35d | 2968 | __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) |
<> | 135:176b8275d35d | 2969 | { |
<> | 135:176b8275d35d | 2970 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2971 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2972 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
<> | 135:176b8275d35d | 2973 | } |
<> | 135:176b8275d35d | 2974 | |
<> | 135:176b8275d35d | 2975 | /** |
<> | 135:176b8275d35d | 2976 | * @brief Get the current prescaler value acting on an input channel. |
<> | 135:176b8275d35d | 2977 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n |
<> | 135:176b8275d35d | 2978 | * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n |
<> | 135:176b8275d35d | 2979 | * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n |
<> | 135:176b8275d35d | 2980 | * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler |
<> | 135:176b8275d35d | 2981 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 2982 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 2983 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 2984 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 2985 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 2986 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 2987 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 2988 | * @arg @ref LL_TIM_ICPSC_DIV1 |
<> | 135:176b8275d35d | 2989 | * @arg @ref LL_TIM_ICPSC_DIV2 |
<> | 135:176b8275d35d | 2990 | * @arg @ref LL_TIM_ICPSC_DIV4 |
<> | 135:176b8275d35d | 2991 | * @arg @ref LL_TIM_ICPSC_DIV8 |
<> | 135:176b8275d35d | 2992 | */ |
<> | 135:176b8275d35d | 2993 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 2994 | { |
<> | 135:176b8275d35d | 2995 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 2996 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 2997 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
<> | 135:176b8275d35d | 2998 | } |
<> | 135:176b8275d35d | 2999 | |
<> | 135:176b8275d35d | 3000 | /** |
<> | 135:176b8275d35d | 3001 | * @brief Set the input filter duration. |
<> | 135:176b8275d35d | 3002 | * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n |
<> | 135:176b8275d35d | 3003 | * CCMR1 IC2F LL_TIM_IC_SetFilter\n |
<> | 135:176b8275d35d | 3004 | * CCMR2 IC3F LL_TIM_IC_SetFilter\n |
<> | 135:176b8275d35d | 3005 | * CCMR2 IC4F LL_TIM_IC_SetFilter |
<> | 135:176b8275d35d | 3006 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3007 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3008 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 3009 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 3010 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 3011 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 3012 | * @param ICFilter This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3013 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
<> | 135:176b8275d35d | 3014 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
<> | 135:176b8275d35d | 3015 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
<> | 135:176b8275d35d | 3016 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
<> | 135:176b8275d35d | 3017 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
<> | 135:176b8275d35d | 3018 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
<> | 135:176b8275d35d | 3019 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
<> | 135:176b8275d35d | 3020 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
<> | 135:176b8275d35d | 3021 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
<> | 135:176b8275d35d | 3022 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
<> | 135:176b8275d35d | 3023 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
<> | 135:176b8275d35d | 3024 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
<> | 135:176b8275d35d | 3025 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
<> | 135:176b8275d35d | 3026 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
<> | 135:176b8275d35d | 3027 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
<> | 135:176b8275d35d | 3028 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
<> | 135:176b8275d35d | 3029 | * @retval None |
<> | 135:176b8275d35d | 3030 | */ |
<> | 135:176b8275d35d | 3031 | __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) |
<> | 135:176b8275d35d | 3032 | { |
<> | 135:176b8275d35d | 3033 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 3034 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 3035 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
<> | 135:176b8275d35d | 3036 | } |
<> | 135:176b8275d35d | 3037 | |
<> | 135:176b8275d35d | 3038 | /** |
<> | 135:176b8275d35d | 3039 | * @brief Get the input filter duration. |
<> | 135:176b8275d35d | 3040 | * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n |
<> | 135:176b8275d35d | 3041 | * CCMR1 IC2F LL_TIM_IC_GetFilter\n |
<> | 135:176b8275d35d | 3042 | * CCMR2 IC3F LL_TIM_IC_GetFilter\n |
<> | 135:176b8275d35d | 3043 | * CCMR2 IC4F LL_TIM_IC_GetFilter |
<> | 135:176b8275d35d | 3044 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3045 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3046 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 3047 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 3048 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 3049 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 3050 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 3051 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
<> | 135:176b8275d35d | 3052 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
<> | 135:176b8275d35d | 3053 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
<> | 135:176b8275d35d | 3054 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
<> | 135:176b8275d35d | 3055 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
<> | 135:176b8275d35d | 3056 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
<> | 135:176b8275d35d | 3057 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
<> | 135:176b8275d35d | 3058 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
<> | 135:176b8275d35d | 3059 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
<> | 135:176b8275d35d | 3060 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
<> | 135:176b8275d35d | 3061 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
<> | 135:176b8275d35d | 3062 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
<> | 135:176b8275d35d | 3063 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
<> | 135:176b8275d35d | 3064 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
<> | 135:176b8275d35d | 3065 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
<> | 135:176b8275d35d | 3066 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
<> | 135:176b8275d35d | 3067 | */ |
<> | 135:176b8275d35d | 3068 | __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 3069 | { |
<> | 135:176b8275d35d | 3070 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 3071 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
<> | 135:176b8275d35d | 3072 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
<> | 135:176b8275d35d | 3073 | } |
<> | 135:176b8275d35d | 3074 | |
<> | 135:176b8275d35d | 3075 | /** |
<> | 135:176b8275d35d | 3076 | * @brief Set the input channel polarity. |
<> | 135:176b8275d35d | 3077 | * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n |
<> | 135:176b8275d35d | 3078 | * CCER CC1NP LL_TIM_IC_SetPolarity\n |
<> | 135:176b8275d35d | 3079 | * CCER CC2P LL_TIM_IC_SetPolarity\n |
<> | 135:176b8275d35d | 3080 | * CCER CC2NP LL_TIM_IC_SetPolarity\n |
<> | 135:176b8275d35d | 3081 | * CCER CC3P LL_TIM_IC_SetPolarity\n |
<> | 135:176b8275d35d | 3082 | * CCER CC3NP LL_TIM_IC_SetPolarity\n |
<> | 135:176b8275d35d | 3083 | * CCER CC4P LL_TIM_IC_SetPolarity\n |
<> | 135:176b8275d35d | 3084 | * CCER CC4NP LL_TIM_IC_SetPolarity |
<> | 135:176b8275d35d | 3085 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3086 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3087 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 3088 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 3089 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 3090 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 3091 | * @param ICPolarity This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3092 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
<> | 135:176b8275d35d | 3093 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
<> | 135:176b8275d35d | 3094 | * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE |
<> | 135:176b8275d35d | 3095 | * @retval None |
<> | 135:176b8275d35d | 3096 | */ |
<> | 135:176b8275d35d | 3097 | __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) |
<> | 135:176b8275d35d | 3098 | { |
<> | 135:176b8275d35d | 3099 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 3100 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
<> | 135:176b8275d35d | 3101 | ICPolarity << SHIFT_TAB_CCxP[iChannel]); |
<> | 135:176b8275d35d | 3102 | } |
<> | 135:176b8275d35d | 3103 | |
<> | 135:176b8275d35d | 3104 | /** |
<> | 135:176b8275d35d | 3105 | * @brief Get the current input channel polarity. |
<> | 135:176b8275d35d | 3106 | * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n |
<> | 135:176b8275d35d | 3107 | * CCER CC1NP LL_TIM_IC_GetPolarity\n |
<> | 135:176b8275d35d | 3108 | * CCER CC2P LL_TIM_IC_GetPolarity\n |
<> | 135:176b8275d35d | 3109 | * CCER CC2NP LL_TIM_IC_GetPolarity\n |
<> | 135:176b8275d35d | 3110 | * CCER CC3P LL_TIM_IC_GetPolarity\n |
<> | 135:176b8275d35d | 3111 | * CCER CC3NP LL_TIM_IC_GetPolarity\n |
<> | 135:176b8275d35d | 3112 | * CCER CC4P LL_TIM_IC_GetPolarity\n |
<> | 135:176b8275d35d | 3113 | * CCER CC4NP LL_TIM_IC_GetPolarity |
<> | 135:176b8275d35d | 3114 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3115 | * @param Channel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3116 | * @arg @ref LL_TIM_CHANNEL_CH1 |
<> | 135:176b8275d35d | 3117 | * @arg @ref LL_TIM_CHANNEL_CH2 |
<> | 135:176b8275d35d | 3118 | * @arg @ref LL_TIM_CHANNEL_CH3 |
<> | 135:176b8275d35d | 3119 | * @arg @ref LL_TIM_CHANNEL_CH4 |
<> | 135:176b8275d35d | 3120 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 3121 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
<> | 135:176b8275d35d | 3122 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
<> | 135:176b8275d35d | 3123 | * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE |
<> | 135:176b8275d35d | 3124 | */ |
<> | 135:176b8275d35d | 3125 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) |
<> | 135:176b8275d35d | 3126 | { |
<> | 135:176b8275d35d | 3127 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
<> | 135:176b8275d35d | 3128 | return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> |
<> | 135:176b8275d35d | 3129 | SHIFT_TAB_CCxP[iChannel]); |
<> | 135:176b8275d35d | 3130 | } |
<> | 135:176b8275d35d | 3131 | |
<> | 135:176b8275d35d | 3132 | /** |
<> | 135:176b8275d35d | 3133 | * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). |
<> | 135:176b8275d35d | 3134 | * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3135 | * a timer instance provides an XOR input. |
<> | 135:176b8275d35d | 3136 | * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination |
<> | 135:176b8275d35d | 3137 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3138 | * @retval None |
<> | 135:176b8275d35d | 3139 | */ |
<> | 135:176b8275d35d | 3140 | __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3141 | { |
<> | 135:176b8275d35d | 3142 | SET_BIT(TIMx->CR2, TIM_CR2_TI1S); |
<> | 135:176b8275d35d | 3143 | } |
<> | 135:176b8275d35d | 3144 | |
<> | 135:176b8275d35d | 3145 | /** |
<> | 135:176b8275d35d | 3146 | * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. |
<> | 135:176b8275d35d | 3147 | * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3148 | * a timer instance provides an XOR input. |
<> | 135:176b8275d35d | 3149 | * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination |
<> | 135:176b8275d35d | 3150 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3151 | * @retval None |
<> | 135:176b8275d35d | 3152 | */ |
<> | 135:176b8275d35d | 3153 | __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3154 | { |
<> | 135:176b8275d35d | 3155 | CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); |
<> | 135:176b8275d35d | 3156 | } |
<> | 135:176b8275d35d | 3157 | |
<> | 135:176b8275d35d | 3158 | /** |
<> | 135:176b8275d35d | 3159 | * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. |
<> | 135:176b8275d35d | 3160 | * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3161 | * a timer instance provides an XOR input. |
<> | 135:176b8275d35d | 3162 | * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination |
<> | 135:176b8275d35d | 3163 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3164 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 3165 | */ |
<> | 135:176b8275d35d | 3166 | __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3167 | { |
<> | 135:176b8275d35d | 3168 | return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)); |
<> | 135:176b8275d35d | 3169 | } |
<> | 135:176b8275d35d | 3170 | |
<> | 135:176b8275d35d | 3171 | /** |
<> | 135:176b8275d35d | 3172 | * @brief Get captured value for input channel 1. |
<> | 135:176b8275d35d | 3173 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
<> | 135:176b8275d35d | 3174 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 3175 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 3176 | * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3177 | * input channel 1 is supported by a timer instance. |
<> | 135:176b8275d35d | 3178 | * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 |
<> | 135:176b8275d35d | 3179 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3180 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 3181 | */ |
<> | 135:176b8275d35d | 3182 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3183 | { |
<> | 135:176b8275d35d | 3184 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
<> | 135:176b8275d35d | 3185 | } |
<> | 135:176b8275d35d | 3186 | |
<> | 135:176b8275d35d | 3187 | /** |
<> | 135:176b8275d35d | 3188 | * @brief Get captured value for input channel 2. |
<> | 135:176b8275d35d | 3189 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
<> | 135:176b8275d35d | 3190 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 3191 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 3192 | * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3193 | * input channel 2 is supported by a timer instance. |
<> | 135:176b8275d35d | 3194 | * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 |
<> | 135:176b8275d35d | 3195 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3196 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 3197 | */ |
<> | 135:176b8275d35d | 3198 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3199 | { |
<> | 135:176b8275d35d | 3200 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
<> | 135:176b8275d35d | 3201 | } |
<> | 135:176b8275d35d | 3202 | |
<> | 135:176b8275d35d | 3203 | /** |
<> | 135:176b8275d35d | 3204 | * @brief Get captured value for input channel 3. |
<> | 135:176b8275d35d | 3205 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
<> | 135:176b8275d35d | 3206 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 3207 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 3208 | * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3209 | * input channel 3 is supported by a timer instance. |
<> | 135:176b8275d35d | 3210 | * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 |
<> | 135:176b8275d35d | 3211 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3212 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 3213 | */ |
<> | 135:176b8275d35d | 3214 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3215 | { |
<> | 135:176b8275d35d | 3216 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
<> | 135:176b8275d35d | 3217 | } |
<> | 135:176b8275d35d | 3218 | |
<> | 135:176b8275d35d | 3219 | /** |
<> | 135:176b8275d35d | 3220 | * @brief Get captured value for input channel 4. |
<> | 135:176b8275d35d | 3221 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
<> | 135:176b8275d35d | 3222 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 3223 | * whether or not a timer instance supports a 32 bits counter. |
<> | 135:176b8275d35d | 3224 | * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3225 | * input channel 4 is supported by a timer instance. |
<> | 135:176b8275d35d | 3226 | * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 |
<> | 135:176b8275d35d | 3227 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3228 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
<> | 135:176b8275d35d | 3229 | */ |
<> | 135:176b8275d35d | 3230 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3231 | { |
<> | 135:176b8275d35d | 3232 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
<> | 135:176b8275d35d | 3233 | } |
<> | 135:176b8275d35d | 3234 | |
<> | 135:176b8275d35d | 3235 | /** |
<> | 135:176b8275d35d | 3236 | * @} |
<> | 135:176b8275d35d | 3237 | */ |
<> | 135:176b8275d35d | 3238 | |
<> | 135:176b8275d35d | 3239 | /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection |
<> | 135:176b8275d35d | 3240 | * @{ |
<> | 135:176b8275d35d | 3241 | */ |
<> | 135:176b8275d35d | 3242 | /** |
<> | 135:176b8275d35d | 3243 | * @brief Enable external clock mode 2. |
<> | 135:176b8275d35d | 3244 | * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. |
<> | 135:176b8275d35d | 3245 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 3246 | * whether or not a timer instance supports external clock mode2. |
<> | 135:176b8275d35d | 3247 | * @rmtoll SMCR ECE LL_TIM_EnableExternalClock |
<> | 135:176b8275d35d | 3248 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3249 | * @retval None |
<> | 135:176b8275d35d | 3250 | */ |
<> | 135:176b8275d35d | 3251 | __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3252 | { |
<> | 135:176b8275d35d | 3253 | SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
<> | 135:176b8275d35d | 3254 | } |
<> | 135:176b8275d35d | 3255 | |
<> | 135:176b8275d35d | 3256 | /** |
<> | 135:176b8275d35d | 3257 | * @brief Disable external clock mode 2. |
<> | 135:176b8275d35d | 3258 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 3259 | * whether or not a timer instance supports external clock mode2. |
<> | 135:176b8275d35d | 3260 | * @rmtoll SMCR ECE LL_TIM_DisableExternalClock |
<> | 135:176b8275d35d | 3261 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3262 | * @retval None |
<> | 135:176b8275d35d | 3263 | */ |
<> | 135:176b8275d35d | 3264 | __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3265 | { |
<> | 135:176b8275d35d | 3266 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
<> | 135:176b8275d35d | 3267 | } |
<> | 135:176b8275d35d | 3268 | |
<> | 135:176b8275d35d | 3269 | /** |
<> | 135:176b8275d35d | 3270 | * @brief Indicate whether external clock mode 2 is enabled. |
<> | 135:176b8275d35d | 3271 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 3272 | * whether or not a timer instance supports external clock mode2. |
<> | 135:176b8275d35d | 3273 | * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock |
<> | 135:176b8275d35d | 3274 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3275 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 3276 | */ |
<> | 135:176b8275d35d | 3277 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3278 | { |
<> | 135:176b8275d35d | 3279 | return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)); |
<> | 135:176b8275d35d | 3280 | } |
<> | 135:176b8275d35d | 3281 | |
<> | 135:176b8275d35d | 3282 | /** |
<> | 135:176b8275d35d | 3283 | * @brief Set the clock source of the counter clock. |
<> | 135:176b8275d35d | 3284 | * @note when selected clock source is external clock mode 1, the timer input |
<> | 135:176b8275d35d | 3285 | * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() |
<> | 135:176b8275d35d | 3286 | * function. This timer input must be configured by calling |
<> | 135:176b8275d35d | 3287 | * the @ref LL_TIM_IC_Config() function. |
<> | 135:176b8275d35d | 3288 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 3289 | * whether or not a timer instance supports external clock mode1. |
<> | 135:176b8275d35d | 3290 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 3291 | * whether or not a timer instance supports external clock mode2. |
<> | 135:176b8275d35d | 3292 | * @rmtoll SMCR SMS LL_TIM_SetClockSource\n |
<> | 135:176b8275d35d | 3293 | * SMCR ECE LL_TIM_SetClockSource |
<> | 135:176b8275d35d | 3294 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3295 | * @param ClockSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3296 | * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL |
<> | 135:176b8275d35d | 3297 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 |
<> | 135:176b8275d35d | 3298 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 |
<> | 135:176b8275d35d | 3299 | * @retval None |
<> | 135:176b8275d35d | 3300 | */ |
<> | 135:176b8275d35d | 3301 | __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) |
<> | 135:176b8275d35d | 3302 | { |
<> | 135:176b8275d35d | 3303 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); |
<> | 135:176b8275d35d | 3304 | } |
<> | 135:176b8275d35d | 3305 | |
<> | 135:176b8275d35d | 3306 | /** |
<> | 135:176b8275d35d | 3307 | * @brief Set the encoder interface mode. |
<> | 135:176b8275d35d | 3308 | * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 3309 | * whether or not a timer instance supports the encoder mode. |
<> | 135:176b8275d35d | 3310 | * @rmtoll SMCR SMS LL_TIM_SetEncoderMode |
<> | 135:176b8275d35d | 3311 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3312 | * @param EncoderMode This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3313 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 |
<> | 135:176b8275d35d | 3314 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 |
<> | 135:176b8275d35d | 3315 | * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 |
<> | 135:176b8275d35d | 3316 | * @retval None |
<> | 135:176b8275d35d | 3317 | */ |
<> | 135:176b8275d35d | 3318 | __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) |
<> | 135:176b8275d35d | 3319 | { |
<> | 135:176b8275d35d | 3320 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); |
<> | 135:176b8275d35d | 3321 | } |
<> | 135:176b8275d35d | 3322 | |
<> | 135:176b8275d35d | 3323 | /** |
<> | 135:176b8275d35d | 3324 | * @} |
<> | 135:176b8275d35d | 3325 | */ |
<> | 135:176b8275d35d | 3326 | |
<> | 135:176b8275d35d | 3327 | /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration |
<> | 135:176b8275d35d | 3328 | * @{ |
<> | 135:176b8275d35d | 3329 | */ |
<> | 135:176b8275d35d | 3330 | /** |
<> | 135:176b8275d35d | 3331 | * @brief Set the trigger output (TRGO) used for timer synchronization . |
<> | 135:176b8275d35d | 3332 | * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 3333 | * whether or not a timer instance can operate as a master timer. |
<> | 135:176b8275d35d | 3334 | * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput |
<> | 135:176b8275d35d | 3335 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3336 | * @param TimerSynchronization This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3337 | * @arg @ref LL_TIM_TRGO_RESET |
<> | 135:176b8275d35d | 3338 | * @arg @ref LL_TIM_TRGO_ENABLE |
<> | 135:176b8275d35d | 3339 | * @arg @ref LL_TIM_TRGO_UPDATE |
<> | 135:176b8275d35d | 3340 | * @arg @ref LL_TIM_TRGO_CC1IF |
<> | 135:176b8275d35d | 3341 | * @arg @ref LL_TIM_TRGO_OC1REF |
<> | 135:176b8275d35d | 3342 | * @arg @ref LL_TIM_TRGO_OC2REF |
<> | 135:176b8275d35d | 3343 | * @arg @ref LL_TIM_TRGO_OC3REF |
<> | 135:176b8275d35d | 3344 | * @arg @ref LL_TIM_TRGO_OC4REF |
<> | 135:176b8275d35d | 3345 | * @retval None |
<> | 135:176b8275d35d | 3346 | */ |
<> | 135:176b8275d35d | 3347 | __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) |
<> | 135:176b8275d35d | 3348 | { |
<> | 135:176b8275d35d | 3349 | MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); |
<> | 135:176b8275d35d | 3350 | } |
<> | 135:176b8275d35d | 3351 | |
<> | 135:176b8275d35d | 3352 | #if defined(TIM_CR2_MMS2) |
<> | 135:176b8275d35d | 3353 | /** |
<> | 135:176b8275d35d | 3354 | * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . |
<> | 135:176b8275d35d | 3355 | * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check |
<> | 135:176b8275d35d | 3356 | * whether or not a timer instance can be used for ADC synchronization. |
<> | 135:176b8275d35d | 3357 | * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 |
<> | 135:176b8275d35d | 3358 | * @param TIMx Timer Instance |
<> | 135:176b8275d35d | 3359 | * @param ADCSynchronization This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3360 | * @arg @ref LL_TIM_TRGO2_RESET |
<> | 135:176b8275d35d | 3361 | * @arg @ref LL_TIM_TRGO2_ENABLE |
<> | 135:176b8275d35d | 3362 | * @arg @ref LL_TIM_TRGO2_UPDATE |
<> | 135:176b8275d35d | 3363 | * @arg @ref LL_TIM_TRGO2_CC1F |
<> | 135:176b8275d35d | 3364 | * @arg @ref LL_TIM_TRGO2_OC1 |
<> | 135:176b8275d35d | 3365 | * @arg @ref LL_TIM_TRGO2_OC2 |
<> | 135:176b8275d35d | 3366 | * @arg @ref LL_TIM_TRGO2_OC3 |
<> | 135:176b8275d35d | 3367 | * @arg @ref LL_TIM_TRGO2_OC4 |
<> | 135:176b8275d35d | 3368 | * @arg @ref LL_TIM_TRGO2_OC5 |
<> | 135:176b8275d35d | 3369 | * @arg @ref LL_TIM_TRGO2_OC6 |
<> | 135:176b8275d35d | 3370 | * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING |
<> | 135:176b8275d35d | 3371 | * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING |
<> | 135:176b8275d35d | 3372 | * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING |
<> | 135:176b8275d35d | 3373 | * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING |
<> | 135:176b8275d35d | 3374 | * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING |
<> | 135:176b8275d35d | 3375 | * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING |
<> | 135:176b8275d35d | 3376 | * @note OC5 and OC6 are not available for all F3 devices |
<> | 135:176b8275d35d | 3377 | * @retval None |
<> | 135:176b8275d35d | 3378 | */ |
<> | 135:176b8275d35d | 3379 | __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) |
<> | 135:176b8275d35d | 3380 | { |
<> | 135:176b8275d35d | 3381 | MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); |
<> | 135:176b8275d35d | 3382 | } |
<> | 135:176b8275d35d | 3383 | |
<> | 135:176b8275d35d | 3384 | #endif /* TIM_CR2_MMS2 */ |
<> | 135:176b8275d35d | 3385 | /** |
<> | 135:176b8275d35d | 3386 | * @brief Set the synchronization mode of a slave timer. |
<> | 135:176b8275d35d | 3387 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3388 | * a timer instance can operate as a slave timer. |
<> | 135:176b8275d35d | 3389 | * @rmtoll SMCR SMS LL_TIM_SetSlaveMode |
<> | 135:176b8275d35d | 3390 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3391 | * @param SlaveMode This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3392 | * @arg @ref LL_TIM_SLAVEMODE_DISABLED |
<> | 135:176b8275d35d | 3393 | * @arg @ref LL_TIM_SLAVEMODE_RESET |
<> | 135:176b8275d35d | 3394 | * @arg @ref LL_TIM_SLAVEMODE_GATED |
<> | 135:176b8275d35d | 3395 | * @arg @ref LL_TIM_SLAVEMODE_TRIGGER |
<> | 135:176b8275d35d | 3396 | * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER |
<> | 135:176b8275d35d | 3397 | * @retval None |
<> | 135:176b8275d35d | 3398 | */ |
<> | 135:176b8275d35d | 3399 | __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) |
<> | 135:176b8275d35d | 3400 | { |
<> | 135:176b8275d35d | 3401 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); |
<> | 135:176b8275d35d | 3402 | } |
<> | 135:176b8275d35d | 3403 | |
<> | 135:176b8275d35d | 3404 | /** |
<> | 135:176b8275d35d | 3405 | * @brief Set the selects the trigger input to be used to synchronize the counter. |
<> | 135:176b8275d35d | 3406 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3407 | * a timer instance can operate as a slave timer. |
<> | 135:176b8275d35d | 3408 | * @rmtoll SMCR TS LL_TIM_SetTriggerInput |
<> | 135:176b8275d35d | 3409 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3410 | * @param TriggerInput This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3411 | * @arg @ref LL_TIM_TS_ITR0 |
<> | 135:176b8275d35d | 3412 | * @arg @ref LL_TIM_TS_ITR1 |
<> | 135:176b8275d35d | 3413 | * @arg @ref LL_TIM_TS_ITR2 |
<> | 135:176b8275d35d | 3414 | * @arg @ref LL_TIM_TS_ITR3 |
<> | 135:176b8275d35d | 3415 | * @arg @ref LL_TIM_TS_TI1F_ED |
<> | 135:176b8275d35d | 3416 | * @arg @ref LL_TIM_TS_TI1FP1 |
<> | 135:176b8275d35d | 3417 | * @arg @ref LL_TIM_TS_TI2FP2 |
<> | 135:176b8275d35d | 3418 | * @arg @ref LL_TIM_TS_ETRF |
<> | 135:176b8275d35d | 3419 | * @retval None |
<> | 135:176b8275d35d | 3420 | */ |
<> | 135:176b8275d35d | 3421 | __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) |
<> | 135:176b8275d35d | 3422 | { |
<> | 135:176b8275d35d | 3423 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); |
<> | 135:176b8275d35d | 3424 | } |
<> | 135:176b8275d35d | 3425 | |
<> | 135:176b8275d35d | 3426 | /** |
<> | 135:176b8275d35d | 3427 | * @brief Enable the Master/Slave mode. |
<> | 135:176b8275d35d | 3428 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3429 | * a timer instance can operate as a slave timer. |
<> | 135:176b8275d35d | 3430 | * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode |
<> | 135:176b8275d35d | 3431 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3432 | * @retval None |
<> | 135:176b8275d35d | 3433 | */ |
<> | 135:176b8275d35d | 3434 | __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3435 | { |
<> | 135:176b8275d35d | 3436 | SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
<> | 135:176b8275d35d | 3437 | } |
<> | 135:176b8275d35d | 3438 | |
<> | 135:176b8275d35d | 3439 | /** |
<> | 135:176b8275d35d | 3440 | * @brief Disable the Master/Slave mode. |
<> | 135:176b8275d35d | 3441 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3442 | * a timer instance can operate as a slave timer. |
<> | 135:176b8275d35d | 3443 | * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode |
<> | 135:176b8275d35d | 3444 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3445 | * @retval None |
<> | 135:176b8275d35d | 3446 | */ |
<> | 135:176b8275d35d | 3447 | __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3448 | { |
<> | 135:176b8275d35d | 3449 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
<> | 135:176b8275d35d | 3450 | } |
<> | 135:176b8275d35d | 3451 | |
<> | 135:176b8275d35d | 3452 | /** |
<> | 135:176b8275d35d | 3453 | * @brief Indicates whether the Master/Slave mode is enabled. |
<> | 135:176b8275d35d | 3454 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3455 | * a timer instance can operate as a slave timer. |
<> | 135:176b8275d35d | 3456 | * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode |
<> | 135:176b8275d35d | 3457 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3458 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 3459 | */ |
<> | 135:176b8275d35d | 3460 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3461 | { |
<> | 135:176b8275d35d | 3462 | return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)); |
<> | 135:176b8275d35d | 3463 | } |
<> | 135:176b8275d35d | 3464 | |
<> | 135:176b8275d35d | 3465 | /** |
<> | 135:176b8275d35d | 3466 | * @brief Configure the external trigger (ETR) input. |
<> | 135:176b8275d35d | 3467 | * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3468 | * a timer instance provides an external trigger input. |
<> | 135:176b8275d35d | 3469 | * @rmtoll SMCR ETP LL_TIM_ConfigETR\n |
<> | 135:176b8275d35d | 3470 | * SMCR ETPS LL_TIM_ConfigETR\n |
<> | 135:176b8275d35d | 3471 | * SMCR ETF LL_TIM_ConfigETR |
<> | 135:176b8275d35d | 3472 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3473 | * @param ETRPolarity This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3474 | * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED |
<> | 135:176b8275d35d | 3475 | * @arg @ref LL_TIM_ETR_POLARITY_INVERTED |
<> | 135:176b8275d35d | 3476 | * @param ETRPrescaler This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3477 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 |
<> | 135:176b8275d35d | 3478 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 |
<> | 135:176b8275d35d | 3479 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 |
<> | 135:176b8275d35d | 3480 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 |
<> | 135:176b8275d35d | 3481 | * @param ETRFilter This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3482 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1 |
<> | 135:176b8275d35d | 3483 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 |
<> | 135:176b8275d35d | 3484 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 |
<> | 135:176b8275d35d | 3485 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 |
<> | 135:176b8275d35d | 3486 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 |
<> | 135:176b8275d35d | 3487 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 |
<> | 135:176b8275d35d | 3488 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 |
<> | 135:176b8275d35d | 3489 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 |
<> | 135:176b8275d35d | 3490 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 |
<> | 135:176b8275d35d | 3491 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 |
<> | 135:176b8275d35d | 3492 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 |
<> | 135:176b8275d35d | 3493 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 |
<> | 135:176b8275d35d | 3494 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 |
<> | 135:176b8275d35d | 3495 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 |
<> | 135:176b8275d35d | 3496 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 |
<> | 135:176b8275d35d | 3497 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 |
<> | 135:176b8275d35d | 3498 | * @retval None |
<> | 135:176b8275d35d | 3499 | */ |
<> | 135:176b8275d35d | 3500 | __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, |
<> | 135:176b8275d35d | 3501 | uint32_t ETRFilter) |
<> | 135:176b8275d35d | 3502 | { |
<> | 135:176b8275d35d | 3503 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); |
<> | 135:176b8275d35d | 3504 | } |
<> | 135:176b8275d35d | 3505 | |
<> | 135:176b8275d35d | 3506 | /** |
<> | 135:176b8275d35d | 3507 | * @} |
<> | 135:176b8275d35d | 3508 | */ |
<> | 135:176b8275d35d | 3509 | |
<> | 135:176b8275d35d | 3510 | /** @defgroup TIM_LL_EF_Break_Function Break function configuration |
<> | 135:176b8275d35d | 3511 | * @{ |
<> | 135:176b8275d35d | 3512 | */ |
<> | 135:176b8275d35d | 3513 | /** |
<> | 135:176b8275d35d | 3514 | * @brief Enable the break function. |
<> | 135:176b8275d35d | 3515 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3516 | * a timer instance provides a break input. |
<> | 135:176b8275d35d | 3517 | * @rmtoll BDTR BKE LL_TIM_EnableBRK |
<> | 135:176b8275d35d | 3518 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3519 | * @retval None |
<> | 135:176b8275d35d | 3520 | */ |
<> | 135:176b8275d35d | 3521 | __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3522 | { |
<> | 135:176b8275d35d | 3523 | SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); |
<> | 135:176b8275d35d | 3524 | } |
<> | 135:176b8275d35d | 3525 | |
<> | 135:176b8275d35d | 3526 | /** |
<> | 135:176b8275d35d | 3527 | * @brief Disable the break function. |
<> | 135:176b8275d35d | 3528 | * @rmtoll BDTR BKE LL_TIM_DisableBRK |
<> | 135:176b8275d35d | 3529 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3530 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3531 | * a timer instance provides a break input. |
<> | 135:176b8275d35d | 3532 | * @retval None |
<> | 135:176b8275d35d | 3533 | */ |
<> | 135:176b8275d35d | 3534 | __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3535 | { |
<> | 135:176b8275d35d | 3536 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); |
<> | 135:176b8275d35d | 3537 | } |
<> | 135:176b8275d35d | 3538 | |
<> | 135:176b8275d35d | 3539 | #if defined(TIM_BDTR_BKF) |
<> | 135:176b8275d35d | 3540 | /** |
<> | 135:176b8275d35d | 3541 | * @brief Configure the break input. |
<> | 135:176b8275d35d | 3542 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3543 | * a timer instance provides a break input. |
<> | 135:176b8275d35d | 3544 | * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n |
<> | 135:176b8275d35d | 3545 | * BDTR BKF LL_TIM_ConfigBRK |
<> | 135:176b8275d35d | 3546 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3547 | * @param BreakPolarity This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3548 | * @arg @ref LL_TIM_BREAK_POLARITY_LOW |
<> | 135:176b8275d35d | 3549 | * @arg @ref LL_TIM_BREAK_POLARITY_HIGH |
<> | 135:176b8275d35d | 3550 | * @param BreakFilter This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3551 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 |
<> | 135:176b8275d35d | 3552 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 |
<> | 135:176b8275d35d | 3553 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 |
<> | 135:176b8275d35d | 3554 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 |
<> | 135:176b8275d35d | 3555 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 |
<> | 135:176b8275d35d | 3556 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 |
<> | 135:176b8275d35d | 3557 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 |
<> | 135:176b8275d35d | 3558 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 |
<> | 135:176b8275d35d | 3559 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 |
<> | 135:176b8275d35d | 3560 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 |
<> | 135:176b8275d35d | 3561 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 |
<> | 135:176b8275d35d | 3562 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 |
<> | 135:176b8275d35d | 3563 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 |
<> | 135:176b8275d35d | 3564 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 |
<> | 135:176b8275d35d | 3565 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 |
<> | 135:176b8275d35d | 3566 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 |
<> | 135:176b8275d35d | 3567 | * @retval None |
<> | 135:176b8275d35d | 3568 | */ |
<> | 135:176b8275d35d | 3569 | __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter) |
<> | 135:176b8275d35d | 3570 | { |
<> | 135:176b8275d35d | 3571 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); |
<> | 135:176b8275d35d | 3572 | } |
<> | 135:176b8275d35d | 3573 | |
<> | 135:176b8275d35d | 3574 | #else |
<> | 135:176b8275d35d | 3575 | /** |
<> | 135:176b8275d35d | 3576 | * @brief Configure the break input. |
<> | 135:176b8275d35d | 3577 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3578 | * a timer instance provides a break input. |
<> | 135:176b8275d35d | 3579 | * @rmtoll BDTR BKP LL_TIM_ConfigBRK |
<> | 135:176b8275d35d | 3580 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3581 | * @param BreakPolarity This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3582 | * @arg @ref LL_TIM_BREAK_POLARITY_LOW |
<> | 135:176b8275d35d | 3583 | * @arg @ref LL_TIM_BREAK_POLARITY_HIGH |
<> | 135:176b8275d35d | 3584 | * @retval None |
<> | 135:176b8275d35d | 3585 | */ |
<> | 135:176b8275d35d | 3586 | __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) |
<> | 135:176b8275d35d | 3587 | { |
<> | 135:176b8275d35d | 3588 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); |
<> | 135:176b8275d35d | 3589 | } |
<> | 135:176b8275d35d | 3590 | |
<> | 135:176b8275d35d | 3591 | #endif /* TIM_BDTR_BKF */ |
<> | 135:176b8275d35d | 3592 | #if defined(TIM_BDTR_BK2E) |
<> | 135:176b8275d35d | 3593 | /** |
<> | 135:176b8275d35d | 3594 | * @brief Enable the break 2 function. |
<> | 135:176b8275d35d | 3595 | * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3596 | * a timer instance provides a second break input. |
<> | 135:176b8275d35d | 3597 | * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 |
<> | 135:176b8275d35d | 3598 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3599 | * @retval None |
<> | 135:176b8275d35d | 3600 | */ |
<> | 135:176b8275d35d | 3601 | __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3602 | { |
<> | 135:176b8275d35d | 3603 | SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); |
<> | 135:176b8275d35d | 3604 | } |
<> | 135:176b8275d35d | 3605 | |
<> | 135:176b8275d35d | 3606 | /** |
<> | 135:176b8275d35d | 3607 | * @brief Disable the break 2 function. |
<> | 135:176b8275d35d | 3608 | * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3609 | * a timer instance provides a second break input. |
<> | 135:176b8275d35d | 3610 | * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 |
<> | 135:176b8275d35d | 3611 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3612 | * @retval None |
<> | 135:176b8275d35d | 3613 | */ |
<> | 135:176b8275d35d | 3614 | __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3615 | { |
<> | 135:176b8275d35d | 3616 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); |
<> | 135:176b8275d35d | 3617 | } |
<> | 135:176b8275d35d | 3618 | |
<> | 135:176b8275d35d | 3619 | /** |
<> | 135:176b8275d35d | 3620 | * @brief Configure the break 2 input. |
<> | 135:176b8275d35d | 3621 | * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3622 | * a timer instance provides a second break input. |
<> | 135:176b8275d35d | 3623 | * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n |
<> | 135:176b8275d35d | 3624 | * BDTR BK2F LL_TIM_ConfigBRK2 |
<> | 135:176b8275d35d | 3625 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3626 | * @param Break2Polarity This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3627 | * @arg @ref LL_TIM_BREAK2_POLARITY_LOW |
<> | 135:176b8275d35d | 3628 | * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH |
<> | 135:176b8275d35d | 3629 | * @param Break2Filter This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3630 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 |
<> | 135:176b8275d35d | 3631 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 |
<> | 135:176b8275d35d | 3632 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 |
<> | 135:176b8275d35d | 3633 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 |
<> | 135:176b8275d35d | 3634 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 |
<> | 135:176b8275d35d | 3635 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 |
<> | 135:176b8275d35d | 3636 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 |
<> | 135:176b8275d35d | 3637 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 |
<> | 135:176b8275d35d | 3638 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 |
<> | 135:176b8275d35d | 3639 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 |
<> | 135:176b8275d35d | 3640 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 |
<> | 135:176b8275d35d | 3641 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 |
<> | 135:176b8275d35d | 3642 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 |
<> | 135:176b8275d35d | 3643 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 |
<> | 135:176b8275d35d | 3644 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 |
<> | 135:176b8275d35d | 3645 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 |
<> | 135:176b8275d35d | 3646 | * @retval None |
<> | 135:176b8275d35d | 3647 | */ |
<> | 135:176b8275d35d | 3648 | __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) |
<> | 135:176b8275d35d | 3649 | { |
<> | 135:176b8275d35d | 3650 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); |
<> | 135:176b8275d35d | 3651 | } |
<> | 135:176b8275d35d | 3652 | |
<> | 135:176b8275d35d | 3653 | #endif /* TIM_BDTR_BK2E */ |
<> | 135:176b8275d35d | 3654 | /** |
<> | 135:176b8275d35d | 3655 | * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. |
<> | 135:176b8275d35d | 3656 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3657 | * a timer instance provides a break input. |
<> | 135:176b8275d35d | 3658 | * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n |
<> | 135:176b8275d35d | 3659 | * BDTR OSSR LL_TIM_SetOffStates |
<> | 135:176b8275d35d | 3660 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3661 | * @param OffStateIdle This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3662 | * @arg @ref LL_TIM_OSSI_DISABLE |
<> | 135:176b8275d35d | 3663 | * @arg @ref LL_TIM_OSSI_ENABLE |
<> | 135:176b8275d35d | 3664 | * @param OffStateRun This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3665 | * @arg @ref LL_TIM_OSSR_DISABLE |
<> | 135:176b8275d35d | 3666 | * @arg @ref LL_TIM_OSSR_ENABLE |
<> | 135:176b8275d35d | 3667 | * @retval None |
<> | 135:176b8275d35d | 3668 | */ |
<> | 135:176b8275d35d | 3669 | __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) |
<> | 135:176b8275d35d | 3670 | { |
<> | 135:176b8275d35d | 3671 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); |
<> | 135:176b8275d35d | 3672 | } |
<> | 135:176b8275d35d | 3673 | |
<> | 135:176b8275d35d | 3674 | /** |
<> | 135:176b8275d35d | 3675 | * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). |
<> | 135:176b8275d35d | 3676 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3677 | * a timer instance provides a break input. |
<> | 135:176b8275d35d | 3678 | * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput |
<> | 135:176b8275d35d | 3679 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3680 | * @retval None |
<> | 135:176b8275d35d | 3681 | */ |
<> | 135:176b8275d35d | 3682 | __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3683 | { |
<> | 135:176b8275d35d | 3684 | SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); |
<> | 135:176b8275d35d | 3685 | } |
<> | 135:176b8275d35d | 3686 | |
<> | 135:176b8275d35d | 3687 | /** |
<> | 135:176b8275d35d | 3688 | * @brief Disable automatic output (MOE can be set only by software). |
<> | 135:176b8275d35d | 3689 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3690 | * a timer instance provides a break input. |
<> | 135:176b8275d35d | 3691 | * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput |
<> | 135:176b8275d35d | 3692 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3693 | * @retval None |
<> | 135:176b8275d35d | 3694 | */ |
<> | 135:176b8275d35d | 3695 | __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3696 | { |
<> | 135:176b8275d35d | 3697 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); |
<> | 135:176b8275d35d | 3698 | } |
<> | 135:176b8275d35d | 3699 | |
<> | 135:176b8275d35d | 3700 | /** |
<> | 135:176b8275d35d | 3701 | * @brief Indicate whether automatic output is enabled. |
<> | 135:176b8275d35d | 3702 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3703 | * a timer instance provides a break input. |
<> | 135:176b8275d35d | 3704 | * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput |
<> | 135:176b8275d35d | 3705 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3706 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 3707 | */ |
<> | 135:176b8275d35d | 3708 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3709 | { |
<> | 135:176b8275d35d | 3710 | return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)); |
<> | 135:176b8275d35d | 3711 | } |
<> | 135:176b8275d35d | 3712 | |
<> | 135:176b8275d35d | 3713 | /** |
<> | 135:176b8275d35d | 3714 | * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). |
<> | 135:176b8275d35d | 3715 | * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by |
<> | 135:176b8275d35d | 3716 | * software and is reset in case of break or break2 event |
<> | 135:176b8275d35d | 3717 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3718 | * a timer instance provides a break input. |
<> | 135:176b8275d35d | 3719 | * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs |
<> | 135:176b8275d35d | 3720 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3721 | * @retval None |
<> | 135:176b8275d35d | 3722 | */ |
<> | 135:176b8275d35d | 3723 | __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3724 | { |
<> | 135:176b8275d35d | 3725 | SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); |
<> | 135:176b8275d35d | 3726 | } |
<> | 135:176b8275d35d | 3727 | |
<> | 135:176b8275d35d | 3728 | /** |
<> | 135:176b8275d35d | 3729 | * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). |
<> | 135:176b8275d35d | 3730 | * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by |
<> | 135:176b8275d35d | 3731 | * software and is reset in case of break or break2 event. |
<> | 135:176b8275d35d | 3732 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3733 | * a timer instance provides a break input. |
<> | 135:176b8275d35d | 3734 | * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs |
<> | 135:176b8275d35d | 3735 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3736 | * @retval None |
<> | 135:176b8275d35d | 3737 | */ |
<> | 135:176b8275d35d | 3738 | __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3739 | { |
<> | 135:176b8275d35d | 3740 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); |
<> | 135:176b8275d35d | 3741 | } |
<> | 135:176b8275d35d | 3742 | |
<> | 135:176b8275d35d | 3743 | /** |
<> | 135:176b8275d35d | 3744 | * @brief Indicates whether outputs are enabled. |
<> | 135:176b8275d35d | 3745 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3746 | * a timer instance provides a break input. |
<> | 135:176b8275d35d | 3747 | * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs |
<> | 135:176b8275d35d | 3748 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3749 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 3750 | */ |
<> | 135:176b8275d35d | 3751 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3752 | { |
<> | 135:176b8275d35d | 3753 | return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)); |
<> | 135:176b8275d35d | 3754 | } |
<> | 135:176b8275d35d | 3755 | |
<> | 135:176b8275d35d | 3756 | /** |
<> | 135:176b8275d35d | 3757 | * @} |
<> | 135:176b8275d35d | 3758 | */ |
<> | 135:176b8275d35d | 3759 | |
<> | 135:176b8275d35d | 3760 | /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration |
<> | 135:176b8275d35d | 3761 | * @{ |
<> | 135:176b8275d35d | 3762 | */ |
<> | 135:176b8275d35d | 3763 | /** |
<> | 135:176b8275d35d | 3764 | * @brief Configures the timer DMA burst feature. |
<> | 135:176b8275d35d | 3765 | * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or |
<> | 135:176b8275d35d | 3766 | * not a timer instance supports the DMA burst mode. |
<> | 135:176b8275d35d | 3767 | * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n |
<> | 135:176b8275d35d | 3768 | * DCR DBA LL_TIM_ConfigDMABurst |
<> | 135:176b8275d35d | 3769 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3770 | * @param DMABurstBaseAddress This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3771 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 |
<> | 135:176b8275d35d | 3772 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 |
<> | 135:176b8275d35d | 3773 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR |
<> | 135:176b8275d35d | 3774 | * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER |
<> | 135:176b8275d35d | 3775 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SR |
<> | 135:176b8275d35d | 3776 | * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR |
<> | 135:176b8275d35d | 3777 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 |
<> | 135:176b8275d35d | 3778 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 |
<> | 135:176b8275d35d | 3779 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER |
<> | 135:176b8275d35d | 3780 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT |
<> | 135:176b8275d35d | 3781 | * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC |
<> | 135:176b8275d35d | 3782 | * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR |
<> | 135:176b8275d35d | 3783 | * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR |
<> | 135:176b8275d35d | 3784 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 |
<> | 135:176b8275d35d | 3785 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 |
<> | 135:176b8275d35d | 3786 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 |
<> | 135:176b8275d35d | 3787 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 |
<> | 135:176b8275d35d | 3788 | * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR |
<> | 135:176b8275d35d | 3789 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 (*) |
<> | 135:176b8275d35d | 3790 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 (*) |
<> | 135:176b8275d35d | 3791 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 (*) |
<> | 135:176b8275d35d | 3792 | * (*) value not defined in all devices |
<> | 135:176b8275d35d | 3793 | * @arg @ref LL_TIM_DMABURST_BASEADDR_OR |
<> | 135:176b8275d35d | 3794 | * @param DMABurstLength This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3795 | * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER |
<> | 135:176b8275d35d | 3796 | * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS |
<> | 135:176b8275d35d | 3797 | * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS |
<> | 135:176b8275d35d | 3798 | * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS |
<> | 135:176b8275d35d | 3799 | * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS |
<> | 135:176b8275d35d | 3800 | * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS |
<> | 135:176b8275d35d | 3801 | * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS |
<> | 135:176b8275d35d | 3802 | * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS |
<> | 135:176b8275d35d | 3803 | * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS |
<> | 135:176b8275d35d | 3804 | * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS |
<> | 135:176b8275d35d | 3805 | * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS |
<> | 135:176b8275d35d | 3806 | * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS |
<> | 135:176b8275d35d | 3807 | * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS |
<> | 135:176b8275d35d | 3808 | * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS |
<> | 135:176b8275d35d | 3809 | * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS |
<> | 135:176b8275d35d | 3810 | * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS |
<> | 135:176b8275d35d | 3811 | * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS |
<> | 135:176b8275d35d | 3812 | * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS |
<> | 135:176b8275d35d | 3813 | * @retval None |
<> | 135:176b8275d35d | 3814 | */ |
<> | 135:176b8275d35d | 3815 | __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) |
<> | 135:176b8275d35d | 3816 | { |
<> | 135:176b8275d35d | 3817 | MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); |
<> | 135:176b8275d35d | 3818 | } |
<> | 135:176b8275d35d | 3819 | |
<> | 135:176b8275d35d | 3820 | /** |
<> | 135:176b8275d35d | 3821 | * @} |
<> | 135:176b8275d35d | 3822 | */ |
<> | 135:176b8275d35d | 3823 | |
<> | 135:176b8275d35d | 3824 | /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping |
<> | 135:176b8275d35d | 3825 | * @{ |
<> | 135:176b8275d35d | 3826 | */ |
<> | 135:176b8275d35d | 3827 | /** |
<> | 135:176b8275d35d | 3828 | * @brief Remap TIM inputs (input channel, internal/external triggers). |
<> | 135:176b8275d35d | 3829 | * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not |
<> | 135:176b8275d35d | 3830 | * a some timer inputs can be remapped. |
<> | 135:176b8275d35d | 3831 | * @if STM32F334x8 |
<> | 135:176b8275d35d | 3832 | * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n |
<> | 135:176b8275d35d | 3833 | * TIM16_OR TI1_RMP LL_TIM_SetRemap\n |
<> | 135:176b8275d35d | 3834 | * @elseif STM32F302x8 |
<> | 135:176b8275d35d | 3835 | * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n |
<> | 135:176b8275d35d | 3836 | * TIM16_OR TI1_RMP LL_TIM_SetRemap\n |
<> | 135:176b8275d35d | 3837 | * @elseif STM32F303xC |
<> | 135:176b8275d35d | 3838 | * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n |
<> | 135:176b8275d35d | 3839 | * TIM8_OR ETR_RMP LL_TIM_SetRemap\n |
<> | 135:176b8275d35d | 3840 | * TIM20_OR ETR_RMP LL_TIM_SetRemap\n |
<> | 135:176b8275d35d | 3841 | * @elseif STM32F373xC |
<> | 135:176b8275d35d | 3842 | * @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap |
<> | 135:176b8275d35d | 3843 | * @endif |
<> | 135:176b8275d35d | 3844 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3845 | * @param Remap Remap params depends on the TIMx. Description available only |
<> | 135:176b8275d35d | 3846 | * in CHM version of the User Manual (not in .pdf). |
<> | 135:176b8275d35d | 3847 | * Otherwise see Reference Manual description of OR registers. |
<> | 135:176b8275d35d | 3848 | * |
<> | 135:176b8275d35d | 3849 | * Below description summarizes "Timer Instance" and "Remap" param combinations: |
<> | 135:176b8275d35d | 3850 | * |
<> | 135:176b8275d35d | 3851 | * TIM1: any combination of ETR_RMP where (**) |
<> | 135:176b8275d35d | 3852 | * |
<> | 135:176b8275d35d | 3853 | * . . ETR_RMP can be one of the following values |
<> | 135:176b8275d35d | 3854 | * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC |
<> | 135:176b8275d35d | 3855 | * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (*) |
<> | 135:176b8275d35d | 3856 | * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (*) |
<> | 135:176b8275d35d | 3857 | * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (*) |
<> | 135:176b8275d35d | 3858 | * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_NC (*) |
<> | 135:176b8275d35d | 3859 | * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (*) |
<> | 135:176b8275d35d | 3860 | * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (*) |
<> | 135:176b8275d35d | 3861 | * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (*) |
<> | 135:176b8275d35d | 3862 | * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC (*) |
<> | 135:176b8275d35d | 3863 | * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (*) |
<> | 135:176b8275d35d | 3864 | * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (*) |
<> | 135:176b8275d35d | 3865 | * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (*) |
<> | 135:176b8275d35d | 3866 | * |
<> | 135:176b8275d35d | 3867 | * TIM8: any combination of ETR_RMP where (**) |
<> | 135:176b8275d35d | 3868 | * |
<> | 135:176b8275d35d | 3869 | * . . ETR_RMP can be one of the following values |
<> | 135:176b8275d35d | 3870 | * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC (*) |
<> | 135:176b8275d35d | 3871 | * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (*) |
<> | 135:176b8275d35d | 3872 | * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (*) |
<> | 135:176b8275d35d | 3873 | * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (*) |
<> | 135:176b8275d35d | 3874 | * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC (*) |
<> | 135:176b8275d35d | 3875 | * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (*) |
<> | 135:176b8275d35d | 3876 | * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (*) |
<> | 135:176b8275d35d | 3877 | * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (*) |
<> | 135:176b8275d35d | 3878 | * |
<> | 135:176b8275d35d | 3879 | * TIM14: any combination of TI1_RMP where (**) |
<> | 135:176b8275d35d | 3880 | * |
<> | 135:176b8275d35d | 3881 | * . . TI1_RMP can be one of the following values |
<> | 135:176b8275d35d | 3882 | * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO (*) |
<> | 135:176b8275d35d | 3883 | * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK (*) |
<> | 135:176b8275d35d | 3884 | * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE (*) |
<> | 135:176b8275d35d | 3885 | * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO (*) |
<> | 135:176b8275d35d | 3886 | * |
<> | 135:176b8275d35d | 3887 | * TIM16: any combination of TI1_RMP where (**) |
<> | 135:176b8275d35d | 3888 | * |
<> | 135:176b8275d35d | 3889 | * . . TI1_RMP can be one of the following values |
<> | 135:176b8275d35d | 3890 | * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO (*) |
<> | 135:176b8275d35d | 3891 | * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI (*) |
<> | 135:176b8275d35d | 3892 | * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE (*) |
<> | 135:176b8275d35d | 3893 | * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC (*) |
<> | 135:176b8275d35d | 3894 | * |
<> | 135:176b8275d35d | 3895 | * TIM20: any combination of ETR_RMP where (**) |
<> | 135:176b8275d35d | 3896 | * |
<> | 135:176b8275d35d | 3897 | * . . ETR_RMP can be one of the following values |
<> | 135:176b8275d35d | 3898 | * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_NC (*) |
<> | 135:176b8275d35d | 3899 | * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (*) |
<> | 135:176b8275d35d | 3900 | * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (*) |
<> | 135:176b8275d35d | 3901 | * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (*) |
<> | 135:176b8275d35d | 3902 | * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_NC (*) |
<> | 135:176b8275d35d | 3903 | * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (*) |
<> | 135:176b8275d35d | 3904 | * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (*) |
<> | 135:176b8275d35d | 3905 | * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (*) |
<> | 135:176b8275d35d | 3906 | * |
<> | 135:176b8275d35d | 3907 | * (*) Value not defined in all devices. \n |
<> | 135:176b8275d35d | 3908 | * (**) Register not available in all devices. |
<> | 135:176b8275d35d | 3909 | * @retval None |
<> | 135:176b8275d35d | 3910 | */ |
<> | 135:176b8275d35d | 3911 | __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) |
<> | 135:176b8275d35d | 3912 | { |
<> | 135:176b8275d35d | 3913 | MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); |
<> | 135:176b8275d35d | 3914 | } |
<> | 135:176b8275d35d | 3915 | |
<> | 135:176b8275d35d | 3916 | /** |
<> | 135:176b8275d35d | 3917 | * @} |
<> | 135:176b8275d35d | 3918 | */ |
<> | 135:176b8275d35d | 3919 | |
<> | 135:176b8275d35d | 3920 | #if defined(TIM_SMCR_OCCS) |
<> | 135:176b8275d35d | 3921 | /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management |
<> | 135:176b8275d35d | 3922 | * @{ |
<> | 135:176b8275d35d | 3923 | */ |
<> | 135:176b8275d35d | 3924 | /** |
<> | 135:176b8275d35d | 3925 | * @brief Set the OCREF clear input source |
<> | 135:176b8275d35d | 3926 | * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT |
<> | 135:176b8275d35d | 3927 | * @note This function can only be used in Output compare and PWM modes. |
<> | 135:176b8275d35d | 3928 | * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource |
<> | 135:176b8275d35d | 3929 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3930 | * @param OCRefClearInputSource This parameter can be one of the following values: |
<> | 135:176b8275d35d | 3931 | * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR |
<> | 135:176b8275d35d | 3932 | * @arg @ref LL_TIM_OCREF_CLR_INT_ETR |
<> | 135:176b8275d35d | 3933 | * @retval None |
<> | 135:176b8275d35d | 3934 | */ |
<> | 135:176b8275d35d | 3935 | __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) |
<> | 135:176b8275d35d | 3936 | { |
<> | 135:176b8275d35d | 3937 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); |
<> | 135:176b8275d35d | 3938 | } |
<> | 135:176b8275d35d | 3939 | /** |
<> | 135:176b8275d35d | 3940 | * @} |
<> | 135:176b8275d35d | 3941 | */ |
<> | 135:176b8275d35d | 3942 | #endif /* TIM_SMCR_OCCS */ |
<> | 135:176b8275d35d | 3943 | |
<> | 135:176b8275d35d | 3944 | /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management |
<> | 135:176b8275d35d | 3945 | * @{ |
<> | 135:176b8275d35d | 3946 | */ |
<> | 135:176b8275d35d | 3947 | /** |
<> | 135:176b8275d35d | 3948 | * @brief Clear the update interrupt flag (UIF). |
<> | 135:176b8275d35d | 3949 | * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE |
<> | 135:176b8275d35d | 3950 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3951 | * @retval None |
<> | 135:176b8275d35d | 3952 | */ |
<> | 135:176b8275d35d | 3953 | __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3954 | { |
<> | 135:176b8275d35d | 3955 | WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); |
<> | 135:176b8275d35d | 3956 | } |
<> | 135:176b8275d35d | 3957 | |
<> | 135:176b8275d35d | 3958 | /** |
<> | 135:176b8275d35d | 3959 | * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). |
<> | 135:176b8275d35d | 3960 | * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE |
<> | 135:176b8275d35d | 3961 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3962 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 3963 | */ |
<> | 135:176b8275d35d | 3964 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3965 | { |
<> | 135:176b8275d35d | 3966 | return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); |
<> | 135:176b8275d35d | 3967 | } |
<> | 135:176b8275d35d | 3968 | |
<> | 135:176b8275d35d | 3969 | /** |
<> | 135:176b8275d35d | 3970 | * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). |
<> | 135:176b8275d35d | 3971 | * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 |
<> | 135:176b8275d35d | 3972 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3973 | * @retval None |
<> | 135:176b8275d35d | 3974 | */ |
<> | 135:176b8275d35d | 3975 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3976 | { |
<> | 135:176b8275d35d | 3977 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); |
<> | 135:176b8275d35d | 3978 | } |
<> | 135:176b8275d35d | 3979 | |
<> | 135:176b8275d35d | 3980 | /** |
<> | 135:176b8275d35d | 3981 | * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). |
<> | 135:176b8275d35d | 3982 | * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 |
<> | 135:176b8275d35d | 3983 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3984 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 3985 | */ |
<> | 135:176b8275d35d | 3986 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3987 | { |
<> | 135:176b8275d35d | 3988 | return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)); |
<> | 135:176b8275d35d | 3989 | } |
<> | 135:176b8275d35d | 3990 | |
<> | 135:176b8275d35d | 3991 | /** |
<> | 135:176b8275d35d | 3992 | * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). |
<> | 135:176b8275d35d | 3993 | * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 |
<> | 135:176b8275d35d | 3994 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 3995 | * @retval None |
<> | 135:176b8275d35d | 3996 | */ |
<> | 135:176b8275d35d | 3997 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 3998 | { |
<> | 135:176b8275d35d | 3999 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); |
<> | 135:176b8275d35d | 4000 | } |
<> | 135:176b8275d35d | 4001 | |
<> | 135:176b8275d35d | 4002 | /** |
<> | 135:176b8275d35d | 4003 | * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). |
<> | 135:176b8275d35d | 4004 | * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 |
<> | 135:176b8275d35d | 4005 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4006 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4007 | */ |
<> | 135:176b8275d35d | 4008 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4009 | { |
<> | 135:176b8275d35d | 4010 | return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)); |
<> | 135:176b8275d35d | 4011 | } |
<> | 135:176b8275d35d | 4012 | |
<> | 135:176b8275d35d | 4013 | /** |
<> | 135:176b8275d35d | 4014 | * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). |
<> | 135:176b8275d35d | 4015 | * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 |
<> | 135:176b8275d35d | 4016 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4017 | * @retval None |
<> | 135:176b8275d35d | 4018 | */ |
<> | 135:176b8275d35d | 4019 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4020 | { |
<> | 135:176b8275d35d | 4021 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); |
<> | 135:176b8275d35d | 4022 | } |
<> | 135:176b8275d35d | 4023 | |
<> | 135:176b8275d35d | 4024 | /** |
<> | 135:176b8275d35d | 4025 | * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). |
<> | 135:176b8275d35d | 4026 | * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 |
<> | 135:176b8275d35d | 4027 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4028 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4029 | */ |
<> | 135:176b8275d35d | 4030 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4031 | { |
<> | 135:176b8275d35d | 4032 | return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)); |
<> | 135:176b8275d35d | 4033 | } |
<> | 135:176b8275d35d | 4034 | |
<> | 135:176b8275d35d | 4035 | /** |
<> | 135:176b8275d35d | 4036 | * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). |
<> | 135:176b8275d35d | 4037 | * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 |
<> | 135:176b8275d35d | 4038 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4039 | * @retval None |
<> | 135:176b8275d35d | 4040 | */ |
<> | 135:176b8275d35d | 4041 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4042 | { |
<> | 135:176b8275d35d | 4043 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); |
<> | 135:176b8275d35d | 4044 | } |
<> | 135:176b8275d35d | 4045 | |
<> | 135:176b8275d35d | 4046 | /** |
<> | 135:176b8275d35d | 4047 | * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). |
<> | 135:176b8275d35d | 4048 | * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 |
<> | 135:176b8275d35d | 4049 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4050 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4051 | */ |
<> | 135:176b8275d35d | 4052 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4053 | { |
<> | 135:176b8275d35d | 4054 | return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)); |
<> | 135:176b8275d35d | 4055 | } |
<> | 135:176b8275d35d | 4056 | |
<> | 135:176b8275d35d | 4057 | #if defined (TIM_SR_CC5IF) |
<> | 135:176b8275d35d | 4058 | /** |
<> | 135:176b8275d35d | 4059 | * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). |
<> | 135:176b8275d35d | 4060 | * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 |
<> | 135:176b8275d35d | 4061 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4062 | * @retval None |
<> | 135:176b8275d35d | 4063 | */ |
<> | 135:176b8275d35d | 4064 | __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4065 | { |
<> | 135:176b8275d35d | 4066 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); |
<> | 135:176b8275d35d | 4067 | } |
<> | 135:176b8275d35d | 4068 | |
<> | 135:176b8275d35d | 4069 | /** |
<> | 135:176b8275d35d | 4070 | * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). |
<> | 135:176b8275d35d | 4071 | * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 |
<> | 135:176b8275d35d | 4072 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4073 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4074 | */ |
<> | 135:176b8275d35d | 4075 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4076 | { |
<> | 135:176b8275d35d | 4077 | return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)); |
<> | 135:176b8275d35d | 4078 | } |
<> | 135:176b8275d35d | 4079 | |
<> | 135:176b8275d35d | 4080 | #endif /* TIM_SR_CC5IF */ |
<> | 135:176b8275d35d | 4081 | #if defined (TIM_SR_CC6IF) |
<> | 135:176b8275d35d | 4082 | /** |
<> | 135:176b8275d35d | 4083 | * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). |
<> | 135:176b8275d35d | 4084 | * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 |
<> | 135:176b8275d35d | 4085 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4086 | * @retval None |
<> | 135:176b8275d35d | 4087 | */ |
<> | 135:176b8275d35d | 4088 | __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4089 | { |
<> | 135:176b8275d35d | 4090 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); |
<> | 135:176b8275d35d | 4091 | } |
<> | 135:176b8275d35d | 4092 | |
<> | 135:176b8275d35d | 4093 | /** |
<> | 135:176b8275d35d | 4094 | * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). |
<> | 135:176b8275d35d | 4095 | * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 |
<> | 135:176b8275d35d | 4096 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4097 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4098 | */ |
<> | 135:176b8275d35d | 4099 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4100 | { |
<> | 135:176b8275d35d | 4101 | return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)); |
<> | 135:176b8275d35d | 4102 | } |
<> | 135:176b8275d35d | 4103 | |
<> | 135:176b8275d35d | 4104 | #endif /* TIM_SR_CC6IF */ |
<> | 135:176b8275d35d | 4105 | /** |
<> | 135:176b8275d35d | 4106 | * @brief Clear the commutation interrupt flag (COMIF). |
<> | 135:176b8275d35d | 4107 | * @rmtoll SR COMIF LL_TIM_ClearFlag_COM |
<> | 135:176b8275d35d | 4108 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4109 | * @retval None |
<> | 135:176b8275d35d | 4110 | */ |
<> | 135:176b8275d35d | 4111 | __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4112 | { |
<> | 135:176b8275d35d | 4113 | WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); |
<> | 135:176b8275d35d | 4114 | } |
<> | 135:176b8275d35d | 4115 | |
<> | 135:176b8275d35d | 4116 | /** |
<> | 135:176b8275d35d | 4117 | * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). |
<> | 135:176b8275d35d | 4118 | * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM |
<> | 135:176b8275d35d | 4119 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4120 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4121 | */ |
<> | 135:176b8275d35d | 4122 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4123 | { |
<> | 135:176b8275d35d | 4124 | return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)); |
<> | 135:176b8275d35d | 4125 | } |
<> | 135:176b8275d35d | 4126 | |
<> | 135:176b8275d35d | 4127 | /** |
<> | 135:176b8275d35d | 4128 | * @brief Clear the trigger interrupt flag (TIF). |
<> | 135:176b8275d35d | 4129 | * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG |
<> | 135:176b8275d35d | 4130 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4131 | * @retval None |
<> | 135:176b8275d35d | 4132 | */ |
<> | 135:176b8275d35d | 4133 | __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4134 | { |
<> | 135:176b8275d35d | 4135 | WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); |
<> | 135:176b8275d35d | 4136 | } |
<> | 135:176b8275d35d | 4137 | |
<> | 135:176b8275d35d | 4138 | /** |
<> | 135:176b8275d35d | 4139 | * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). |
<> | 135:176b8275d35d | 4140 | * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG |
<> | 135:176b8275d35d | 4141 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4142 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4143 | */ |
<> | 135:176b8275d35d | 4144 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4145 | { |
<> | 135:176b8275d35d | 4146 | return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)); |
<> | 135:176b8275d35d | 4147 | } |
<> | 135:176b8275d35d | 4148 | |
<> | 135:176b8275d35d | 4149 | /** |
<> | 135:176b8275d35d | 4150 | * @brief Clear the break interrupt flag (BIF). |
<> | 135:176b8275d35d | 4151 | * @rmtoll SR BIF LL_TIM_ClearFlag_BRK |
<> | 135:176b8275d35d | 4152 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4153 | * @retval None |
<> | 135:176b8275d35d | 4154 | */ |
<> | 135:176b8275d35d | 4155 | __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4156 | { |
<> | 135:176b8275d35d | 4157 | WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); |
<> | 135:176b8275d35d | 4158 | } |
<> | 135:176b8275d35d | 4159 | |
<> | 135:176b8275d35d | 4160 | /** |
<> | 135:176b8275d35d | 4161 | * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). |
<> | 135:176b8275d35d | 4162 | * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK |
<> | 135:176b8275d35d | 4163 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4164 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4165 | */ |
<> | 135:176b8275d35d | 4166 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4167 | { |
<> | 135:176b8275d35d | 4168 | return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)); |
<> | 135:176b8275d35d | 4169 | } |
<> | 135:176b8275d35d | 4170 | |
<> | 135:176b8275d35d | 4171 | #if defined(TIM_SR_B2IF) |
<> | 135:176b8275d35d | 4172 | /** |
<> | 135:176b8275d35d | 4173 | * @brief Clear the break 2 interrupt flag (B2IF). |
<> | 135:176b8275d35d | 4174 | * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 |
<> | 135:176b8275d35d | 4175 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4176 | * @retval None |
<> | 135:176b8275d35d | 4177 | */ |
<> | 135:176b8275d35d | 4178 | __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4179 | { |
<> | 135:176b8275d35d | 4180 | WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); |
<> | 135:176b8275d35d | 4181 | } |
<> | 135:176b8275d35d | 4182 | |
<> | 135:176b8275d35d | 4183 | /** |
<> | 135:176b8275d35d | 4184 | * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). |
<> | 135:176b8275d35d | 4185 | * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 |
<> | 135:176b8275d35d | 4186 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4187 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4188 | */ |
<> | 135:176b8275d35d | 4189 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4190 | { |
<> | 135:176b8275d35d | 4191 | return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)); |
<> | 135:176b8275d35d | 4192 | } |
<> | 135:176b8275d35d | 4193 | |
<> | 135:176b8275d35d | 4194 | #endif /* TIM_SR_B2IF */ |
<> | 135:176b8275d35d | 4195 | /** |
<> | 135:176b8275d35d | 4196 | * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). |
<> | 135:176b8275d35d | 4197 | * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR |
<> | 135:176b8275d35d | 4198 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4199 | * @retval None |
<> | 135:176b8275d35d | 4200 | */ |
<> | 135:176b8275d35d | 4201 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4202 | { |
<> | 135:176b8275d35d | 4203 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); |
<> | 135:176b8275d35d | 4204 | } |
<> | 135:176b8275d35d | 4205 | |
<> | 135:176b8275d35d | 4206 | /** |
<> | 135:176b8275d35d | 4207 | * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). |
<> | 135:176b8275d35d | 4208 | * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR |
<> | 135:176b8275d35d | 4209 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4210 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4211 | */ |
<> | 135:176b8275d35d | 4212 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4213 | { |
<> | 135:176b8275d35d | 4214 | return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)); |
<> | 135:176b8275d35d | 4215 | } |
<> | 135:176b8275d35d | 4216 | |
<> | 135:176b8275d35d | 4217 | /** |
<> | 135:176b8275d35d | 4218 | * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). |
<> | 135:176b8275d35d | 4219 | * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR |
<> | 135:176b8275d35d | 4220 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4221 | * @retval None |
<> | 135:176b8275d35d | 4222 | */ |
<> | 135:176b8275d35d | 4223 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4224 | { |
<> | 135:176b8275d35d | 4225 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); |
<> | 135:176b8275d35d | 4226 | } |
<> | 135:176b8275d35d | 4227 | |
<> | 135:176b8275d35d | 4228 | /** |
<> | 135:176b8275d35d | 4229 | * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). |
<> | 135:176b8275d35d | 4230 | * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR |
<> | 135:176b8275d35d | 4231 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4232 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4233 | */ |
<> | 135:176b8275d35d | 4234 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4235 | { |
<> | 135:176b8275d35d | 4236 | return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)); |
<> | 135:176b8275d35d | 4237 | } |
<> | 135:176b8275d35d | 4238 | |
<> | 135:176b8275d35d | 4239 | /** |
<> | 135:176b8275d35d | 4240 | * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). |
<> | 135:176b8275d35d | 4241 | * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR |
<> | 135:176b8275d35d | 4242 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4243 | * @retval None |
<> | 135:176b8275d35d | 4244 | */ |
<> | 135:176b8275d35d | 4245 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4246 | { |
<> | 135:176b8275d35d | 4247 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); |
<> | 135:176b8275d35d | 4248 | } |
<> | 135:176b8275d35d | 4249 | |
<> | 135:176b8275d35d | 4250 | /** |
<> | 135:176b8275d35d | 4251 | * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). |
<> | 135:176b8275d35d | 4252 | * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR |
<> | 135:176b8275d35d | 4253 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4254 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4255 | */ |
<> | 135:176b8275d35d | 4256 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4257 | { |
<> | 135:176b8275d35d | 4258 | return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)); |
<> | 135:176b8275d35d | 4259 | } |
<> | 135:176b8275d35d | 4260 | |
<> | 135:176b8275d35d | 4261 | /** |
<> | 135:176b8275d35d | 4262 | * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). |
<> | 135:176b8275d35d | 4263 | * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR |
<> | 135:176b8275d35d | 4264 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4265 | * @retval None |
<> | 135:176b8275d35d | 4266 | */ |
<> | 135:176b8275d35d | 4267 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4268 | { |
<> | 135:176b8275d35d | 4269 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); |
<> | 135:176b8275d35d | 4270 | } |
<> | 135:176b8275d35d | 4271 | |
<> | 135:176b8275d35d | 4272 | /** |
<> | 135:176b8275d35d | 4273 | * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). |
<> | 135:176b8275d35d | 4274 | * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR |
<> | 135:176b8275d35d | 4275 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4276 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4277 | */ |
<> | 135:176b8275d35d | 4278 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4279 | { |
<> | 135:176b8275d35d | 4280 | return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)); |
<> | 135:176b8275d35d | 4281 | } |
<> | 135:176b8275d35d | 4282 | |
<> | 135:176b8275d35d | 4283 | /** |
<> | 135:176b8275d35d | 4284 | * @} |
<> | 135:176b8275d35d | 4285 | */ |
<> | 135:176b8275d35d | 4286 | |
<> | 135:176b8275d35d | 4287 | /** @defgroup TIM_LL_EF_IT_Management IT-Management |
<> | 135:176b8275d35d | 4288 | * @{ |
<> | 135:176b8275d35d | 4289 | */ |
<> | 135:176b8275d35d | 4290 | /** |
<> | 135:176b8275d35d | 4291 | * @brief Enable update interrupt (UIE). |
<> | 135:176b8275d35d | 4292 | * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE |
<> | 135:176b8275d35d | 4293 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4294 | * @retval None |
<> | 135:176b8275d35d | 4295 | */ |
<> | 135:176b8275d35d | 4296 | __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4297 | { |
<> | 135:176b8275d35d | 4298 | SET_BIT(TIMx->DIER, TIM_DIER_UIE); |
<> | 135:176b8275d35d | 4299 | } |
<> | 135:176b8275d35d | 4300 | |
<> | 135:176b8275d35d | 4301 | /** |
<> | 135:176b8275d35d | 4302 | * @brief Disable update interrupt (UIE). |
<> | 135:176b8275d35d | 4303 | * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE |
<> | 135:176b8275d35d | 4304 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4305 | * @retval None |
<> | 135:176b8275d35d | 4306 | */ |
<> | 135:176b8275d35d | 4307 | __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4308 | { |
<> | 135:176b8275d35d | 4309 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); |
<> | 135:176b8275d35d | 4310 | } |
<> | 135:176b8275d35d | 4311 | |
<> | 135:176b8275d35d | 4312 | /** |
<> | 135:176b8275d35d | 4313 | * @brief Indicates whether the update interrupt (UIE) is enabled. |
<> | 135:176b8275d35d | 4314 | * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE |
<> | 135:176b8275d35d | 4315 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4316 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4317 | */ |
<> | 135:176b8275d35d | 4318 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4319 | { |
<> | 135:176b8275d35d | 4320 | return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)); |
<> | 135:176b8275d35d | 4321 | } |
<> | 135:176b8275d35d | 4322 | |
<> | 135:176b8275d35d | 4323 | /** |
<> | 135:176b8275d35d | 4324 | * @brief Enable capture/compare 1 interrupt (CC1IE). |
<> | 135:176b8275d35d | 4325 | * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 |
<> | 135:176b8275d35d | 4326 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4327 | * @retval None |
<> | 135:176b8275d35d | 4328 | */ |
<> | 135:176b8275d35d | 4329 | __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4330 | { |
<> | 135:176b8275d35d | 4331 | SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
<> | 135:176b8275d35d | 4332 | } |
<> | 135:176b8275d35d | 4333 | |
<> | 135:176b8275d35d | 4334 | /** |
<> | 135:176b8275d35d | 4335 | * @brief Disable capture/compare 1 interrupt (CC1IE). |
<> | 135:176b8275d35d | 4336 | * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 |
<> | 135:176b8275d35d | 4337 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4338 | * @retval None |
<> | 135:176b8275d35d | 4339 | */ |
<> | 135:176b8275d35d | 4340 | __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4341 | { |
<> | 135:176b8275d35d | 4342 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
<> | 135:176b8275d35d | 4343 | } |
<> | 135:176b8275d35d | 4344 | |
<> | 135:176b8275d35d | 4345 | /** |
<> | 135:176b8275d35d | 4346 | * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. |
<> | 135:176b8275d35d | 4347 | * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 |
<> | 135:176b8275d35d | 4348 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4349 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4350 | */ |
<> | 135:176b8275d35d | 4351 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4352 | { |
<> | 135:176b8275d35d | 4353 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)); |
<> | 135:176b8275d35d | 4354 | } |
<> | 135:176b8275d35d | 4355 | |
<> | 135:176b8275d35d | 4356 | /** |
<> | 135:176b8275d35d | 4357 | * @brief Enable capture/compare 2 interrupt (CC2IE). |
<> | 135:176b8275d35d | 4358 | * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 |
<> | 135:176b8275d35d | 4359 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4360 | * @retval None |
<> | 135:176b8275d35d | 4361 | */ |
<> | 135:176b8275d35d | 4362 | __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4363 | { |
<> | 135:176b8275d35d | 4364 | SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
<> | 135:176b8275d35d | 4365 | } |
<> | 135:176b8275d35d | 4366 | |
<> | 135:176b8275d35d | 4367 | /** |
<> | 135:176b8275d35d | 4368 | * @brief Disable capture/compare 2 interrupt (CC2IE). |
<> | 135:176b8275d35d | 4369 | * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 |
<> | 135:176b8275d35d | 4370 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4371 | * @retval None |
<> | 135:176b8275d35d | 4372 | */ |
<> | 135:176b8275d35d | 4373 | __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4374 | { |
<> | 135:176b8275d35d | 4375 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
<> | 135:176b8275d35d | 4376 | } |
<> | 135:176b8275d35d | 4377 | |
<> | 135:176b8275d35d | 4378 | /** |
<> | 135:176b8275d35d | 4379 | * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. |
<> | 135:176b8275d35d | 4380 | * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 |
<> | 135:176b8275d35d | 4381 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4382 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4383 | */ |
<> | 135:176b8275d35d | 4384 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4385 | { |
<> | 135:176b8275d35d | 4386 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)); |
<> | 135:176b8275d35d | 4387 | } |
<> | 135:176b8275d35d | 4388 | |
<> | 135:176b8275d35d | 4389 | /** |
<> | 135:176b8275d35d | 4390 | * @brief Enable capture/compare 3 interrupt (CC3IE). |
<> | 135:176b8275d35d | 4391 | * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 |
<> | 135:176b8275d35d | 4392 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4393 | * @retval None |
<> | 135:176b8275d35d | 4394 | */ |
<> | 135:176b8275d35d | 4395 | __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4396 | { |
<> | 135:176b8275d35d | 4397 | SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
<> | 135:176b8275d35d | 4398 | } |
<> | 135:176b8275d35d | 4399 | |
<> | 135:176b8275d35d | 4400 | /** |
<> | 135:176b8275d35d | 4401 | * @brief Disable capture/compare 3 interrupt (CC3IE). |
<> | 135:176b8275d35d | 4402 | * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 |
<> | 135:176b8275d35d | 4403 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4404 | * @retval None |
<> | 135:176b8275d35d | 4405 | */ |
<> | 135:176b8275d35d | 4406 | __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4407 | { |
<> | 135:176b8275d35d | 4408 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
<> | 135:176b8275d35d | 4409 | } |
<> | 135:176b8275d35d | 4410 | |
<> | 135:176b8275d35d | 4411 | /** |
<> | 135:176b8275d35d | 4412 | * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. |
<> | 135:176b8275d35d | 4413 | * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 |
<> | 135:176b8275d35d | 4414 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4415 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4416 | */ |
<> | 135:176b8275d35d | 4417 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4418 | { |
<> | 135:176b8275d35d | 4419 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)); |
<> | 135:176b8275d35d | 4420 | } |
<> | 135:176b8275d35d | 4421 | |
<> | 135:176b8275d35d | 4422 | /** |
<> | 135:176b8275d35d | 4423 | * @brief Enable capture/compare 4 interrupt (CC4IE). |
<> | 135:176b8275d35d | 4424 | * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 |
<> | 135:176b8275d35d | 4425 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4426 | * @retval None |
<> | 135:176b8275d35d | 4427 | */ |
<> | 135:176b8275d35d | 4428 | __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4429 | { |
<> | 135:176b8275d35d | 4430 | SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
<> | 135:176b8275d35d | 4431 | } |
<> | 135:176b8275d35d | 4432 | |
<> | 135:176b8275d35d | 4433 | /** |
<> | 135:176b8275d35d | 4434 | * @brief Disable capture/compare 4 interrupt (CC4IE). |
<> | 135:176b8275d35d | 4435 | * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 |
<> | 135:176b8275d35d | 4436 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4437 | * @retval None |
<> | 135:176b8275d35d | 4438 | */ |
<> | 135:176b8275d35d | 4439 | __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4440 | { |
<> | 135:176b8275d35d | 4441 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
<> | 135:176b8275d35d | 4442 | } |
<> | 135:176b8275d35d | 4443 | |
<> | 135:176b8275d35d | 4444 | /** |
<> | 135:176b8275d35d | 4445 | * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. |
<> | 135:176b8275d35d | 4446 | * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 |
<> | 135:176b8275d35d | 4447 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4448 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4449 | */ |
<> | 135:176b8275d35d | 4450 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4451 | { |
<> | 135:176b8275d35d | 4452 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)); |
<> | 135:176b8275d35d | 4453 | } |
<> | 135:176b8275d35d | 4454 | |
<> | 135:176b8275d35d | 4455 | /** |
<> | 135:176b8275d35d | 4456 | * @brief Enable commutation interrupt (COMIE). |
<> | 135:176b8275d35d | 4457 | * @rmtoll DIER COMIE LL_TIM_EnableIT_COM |
<> | 135:176b8275d35d | 4458 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4459 | * @retval None |
<> | 135:176b8275d35d | 4460 | */ |
<> | 135:176b8275d35d | 4461 | __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4462 | { |
<> | 135:176b8275d35d | 4463 | SET_BIT(TIMx->DIER, TIM_DIER_COMIE); |
<> | 135:176b8275d35d | 4464 | } |
<> | 135:176b8275d35d | 4465 | |
<> | 135:176b8275d35d | 4466 | /** |
<> | 135:176b8275d35d | 4467 | * @brief Disable commutation interrupt (COMIE). |
<> | 135:176b8275d35d | 4468 | * @rmtoll DIER COMIE LL_TIM_DisableIT_COM |
<> | 135:176b8275d35d | 4469 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4470 | * @retval None |
<> | 135:176b8275d35d | 4471 | */ |
<> | 135:176b8275d35d | 4472 | __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4473 | { |
<> | 135:176b8275d35d | 4474 | CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); |
<> | 135:176b8275d35d | 4475 | } |
<> | 135:176b8275d35d | 4476 | |
<> | 135:176b8275d35d | 4477 | /** |
<> | 135:176b8275d35d | 4478 | * @brief Indicates whether the commutation interrupt (COMIE) is enabled. |
<> | 135:176b8275d35d | 4479 | * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM |
<> | 135:176b8275d35d | 4480 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4481 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4482 | */ |
<> | 135:176b8275d35d | 4483 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4484 | { |
<> | 135:176b8275d35d | 4485 | return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)); |
<> | 135:176b8275d35d | 4486 | } |
<> | 135:176b8275d35d | 4487 | |
<> | 135:176b8275d35d | 4488 | /** |
<> | 135:176b8275d35d | 4489 | * @brief Enable trigger interrupt (TIE). |
<> | 135:176b8275d35d | 4490 | * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG |
<> | 135:176b8275d35d | 4491 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4492 | * @retval None |
<> | 135:176b8275d35d | 4493 | */ |
<> | 135:176b8275d35d | 4494 | __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4495 | { |
<> | 135:176b8275d35d | 4496 | SET_BIT(TIMx->DIER, TIM_DIER_TIE); |
<> | 135:176b8275d35d | 4497 | } |
<> | 135:176b8275d35d | 4498 | |
<> | 135:176b8275d35d | 4499 | /** |
<> | 135:176b8275d35d | 4500 | * @brief Disable trigger interrupt (TIE). |
<> | 135:176b8275d35d | 4501 | * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG |
<> | 135:176b8275d35d | 4502 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4503 | * @retval None |
<> | 135:176b8275d35d | 4504 | */ |
<> | 135:176b8275d35d | 4505 | __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4506 | { |
<> | 135:176b8275d35d | 4507 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); |
<> | 135:176b8275d35d | 4508 | } |
<> | 135:176b8275d35d | 4509 | |
<> | 135:176b8275d35d | 4510 | /** |
<> | 135:176b8275d35d | 4511 | * @brief Indicates whether the trigger interrupt (TIE) is enabled. |
<> | 135:176b8275d35d | 4512 | * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG |
<> | 135:176b8275d35d | 4513 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4514 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4515 | */ |
<> | 135:176b8275d35d | 4516 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4517 | { |
<> | 135:176b8275d35d | 4518 | return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)); |
<> | 135:176b8275d35d | 4519 | } |
<> | 135:176b8275d35d | 4520 | |
<> | 135:176b8275d35d | 4521 | /** |
<> | 135:176b8275d35d | 4522 | * @brief Enable break interrupt (BIE). |
<> | 135:176b8275d35d | 4523 | * @rmtoll DIER BIE LL_TIM_EnableIT_BRK |
<> | 135:176b8275d35d | 4524 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4525 | * @retval None |
<> | 135:176b8275d35d | 4526 | */ |
<> | 135:176b8275d35d | 4527 | __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4528 | { |
<> | 135:176b8275d35d | 4529 | SET_BIT(TIMx->DIER, TIM_DIER_BIE); |
<> | 135:176b8275d35d | 4530 | } |
<> | 135:176b8275d35d | 4531 | |
<> | 135:176b8275d35d | 4532 | /** |
<> | 135:176b8275d35d | 4533 | * @brief Disable break interrupt (BIE). |
<> | 135:176b8275d35d | 4534 | * @rmtoll DIER BIE LL_TIM_DisableIT_BRK |
<> | 135:176b8275d35d | 4535 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4536 | * @retval None |
<> | 135:176b8275d35d | 4537 | */ |
<> | 135:176b8275d35d | 4538 | __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4539 | { |
<> | 135:176b8275d35d | 4540 | CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); |
<> | 135:176b8275d35d | 4541 | } |
<> | 135:176b8275d35d | 4542 | |
<> | 135:176b8275d35d | 4543 | /** |
<> | 135:176b8275d35d | 4544 | * @brief Indicates whether the break interrupt (BIE) is enabled. |
<> | 135:176b8275d35d | 4545 | * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK |
<> | 135:176b8275d35d | 4546 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4547 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4548 | */ |
<> | 135:176b8275d35d | 4549 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4550 | { |
<> | 135:176b8275d35d | 4551 | return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)); |
<> | 135:176b8275d35d | 4552 | } |
<> | 135:176b8275d35d | 4553 | |
<> | 135:176b8275d35d | 4554 | /** |
<> | 135:176b8275d35d | 4555 | * @} |
<> | 135:176b8275d35d | 4556 | */ |
<> | 135:176b8275d35d | 4557 | |
<> | 135:176b8275d35d | 4558 | /** @defgroup TIM_LL_EF_DMA_Management DMA-Management |
<> | 135:176b8275d35d | 4559 | * @{ |
<> | 135:176b8275d35d | 4560 | */ |
<> | 135:176b8275d35d | 4561 | /** |
<> | 135:176b8275d35d | 4562 | * @brief Enable update DMA request (UDE). |
<> | 135:176b8275d35d | 4563 | * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE |
<> | 135:176b8275d35d | 4564 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4565 | * @retval None |
<> | 135:176b8275d35d | 4566 | */ |
<> | 135:176b8275d35d | 4567 | __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4568 | { |
<> | 135:176b8275d35d | 4569 | SET_BIT(TIMx->DIER, TIM_DIER_UDE); |
<> | 135:176b8275d35d | 4570 | } |
<> | 135:176b8275d35d | 4571 | |
<> | 135:176b8275d35d | 4572 | /** |
<> | 135:176b8275d35d | 4573 | * @brief Disable update DMA request (UDE). |
<> | 135:176b8275d35d | 4574 | * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE |
<> | 135:176b8275d35d | 4575 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4576 | * @retval None |
<> | 135:176b8275d35d | 4577 | */ |
<> | 135:176b8275d35d | 4578 | __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4579 | { |
<> | 135:176b8275d35d | 4580 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); |
<> | 135:176b8275d35d | 4581 | } |
<> | 135:176b8275d35d | 4582 | |
<> | 135:176b8275d35d | 4583 | /** |
<> | 135:176b8275d35d | 4584 | * @brief Indicates whether the update DMA request (UDE) is enabled. |
<> | 135:176b8275d35d | 4585 | * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE |
<> | 135:176b8275d35d | 4586 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4587 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4588 | */ |
<> | 135:176b8275d35d | 4589 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4590 | { |
<> | 135:176b8275d35d | 4591 | return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)); |
<> | 135:176b8275d35d | 4592 | } |
<> | 135:176b8275d35d | 4593 | |
<> | 135:176b8275d35d | 4594 | /** |
<> | 135:176b8275d35d | 4595 | * @brief Enable capture/compare 1 DMA request (CC1DE). |
<> | 135:176b8275d35d | 4596 | * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 |
<> | 135:176b8275d35d | 4597 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4598 | * @retval None |
<> | 135:176b8275d35d | 4599 | */ |
<> | 135:176b8275d35d | 4600 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4601 | { |
<> | 135:176b8275d35d | 4602 | SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
<> | 135:176b8275d35d | 4603 | } |
<> | 135:176b8275d35d | 4604 | |
<> | 135:176b8275d35d | 4605 | /** |
<> | 135:176b8275d35d | 4606 | * @brief Disable capture/compare 1 DMA request (CC1DE). |
<> | 135:176b8275d35d | 4607 | * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 |
<> | 135:176b8275d35d | 4608 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4609 | * @retval None |
<> | 135:176b8275d35d | 4610 | */ |
<> | 135:176b8275d35d | 4611 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4612 | { |
<> | 135:176b8275d35d | 4613 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
<> | 135:176b8275d35d | 4614 | } |
<> | 135:176b8275d35d | 4615 | |
<> | 135:176b8275d35d | 4616 | /** |
<> | 135:176b8275d35d | 4617 | * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. |
<> | 135:176b8275d35d | 4618 | * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 |
<> | 135:176b8275d35d | 4619 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4620 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4621 | */ |
<> | 135:176b8275d35d | 4622 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4623 | { |
<> | 135:176b8275d35d | 4624 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)); |
<> | 135:176b8275d35d | 4625 | } |
<> | 135:176b8275d35d | 4626 | |
<> | 135:176b8275d35d | 4627 | /** |
<> | 135:176b8275d35d | 4628 | * @brief Enable capture/compare 2 DMA request (CC2DE). |
<> | 135:176b8275d35d | 4629 | * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 |
<> | 135:176b8275d35d | 4630 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4631 | * @retval None |
<> | 135:176b8275d35d | 4632 | */ |
<> | 135:176b8275d35d | 4633 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4634 | { |
<> | 135:176b8275d35d | 4635 | SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
<> | 135:176b8275d35d | 4636 | } |
<> | 135:176b8275d35d | 4637 | |
<> | 135:176b8275d35d | 4638 | /** |
<> | 135:176b8275d35d | 4639 | * @brief Disable capture/compare 2 DMA request (CC2DE). |
<> | 135:176b8275d35d | 4640 | * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 |
<> | 135:176b8275d35d | 4641 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4642 | * @retval None |
<> | 135:176b8275d35d | 4643 | */ |
<> | 135:176b8275d35d | 4644 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4645 | { |
<> | 135:176b8275d35d | 4646 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
<> | 135:176b8275d35d | 4647 | } |
<> | 135:176b8275d35d | 4648 | |
<> | 135:176b8275d35d | 4649 | /** |
<> | 135:176b8275d35d | 4650 | * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. |
<> | 135:176b8275d35d | 4651 | * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 |
<> | 135:176b8275d35d | 4652 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4653 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4654 | */ |
<> | 135:176b8275d35d | 4655 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4656 | { |
<> | 135:176b8275d35d | 4657 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)); |
<> | 135:176b8275d35d | 4658 | } |
<> | 135:176b8275d35d | 4659 | |
<> | 135:176b8275d35d | 4660 | /** |
<> | 135:176b8275d35d | 4661 | * @brief Enable capture/compare 3 DMA request (CC3DE). |
<> | 135:176b8275d35d | 4662 | * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 |
<> | 135:176b8275d35d | 4663 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4664 | * @retval None |
<> | 135:176b8275d35d | 4665 | */ |
<> | 135:176b8275d35d | 4666 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4667 | { |
<> | 135:176b8275d35d | 4668 | SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
<> | 135:176b8275d35d | 4669 | } |
<> | 135:176b8275d35d | 4670 | |
<> | 135:176b8275d35d | 4671 | /** |
<> | 135:176b8275d35d | 4672 | * @brief Disable capture/compare 3 DMA request (CC3DE). |
<> | 135:176b8275d35d | 4673 | * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 |
<> | 135:176b8275d35d | 4674 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4675 | * @retval None |
<> | 135:176b8275d35d | 4676 | */ |
<> | 135:176b8275d35d | 4677 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4678 | { |
<> | 135:176b8275d35d | 4679 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
<> | 135:176b8275d35d | 4680 | } |
<> | 135:176b8275d35d | 4681 | |
<> | 135:176b8275d35d | 4682 | /** |
<> | 135:176b8275d35d | 4683 | * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. |
<> | 135:176b8275d35d | 4684 | * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 |
<> | 135:176b8275d35d | 4685 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4686 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4687 | */ |
<> | 135:176b8275d35d | 4688 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4689 | { |
<> | 135:176b8275d35d | 4690 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)); |
<> | 135:176b8275d35d | 4691 | } |
<> | 135:176b8275d35d | 4692 | |
<> | 135:176b8275d35d | 4693 | /** |
<> | 135:176b8275d35d | 4694 | * @brief Enable capture/compare 4 DMA request (CC4DE). |
<> | 135:176b8275d35d | 4695 | * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 |
<> | 135:176b8275d35d | 4696 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4697 | * @retval None |
<> | 135:176b8275d35d | 4698 | */ |
<> | 135:176b8275d35d | 4699 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4700 | { |
<> | 135:176b8275d35d | 4701 | SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
<> | 135:176b8275d35d | 4702 | } |
<> | 135:176b8275d35d | 4703 | |
<> | 135:176b8275d35d | 4704 | /** |
<> | 135:176b8275d35d | 4705 | * @brief Disable capture/compare 4 DMA request (CC4DE). |
<> | 135:176b8275d35d | 4706 | * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 |
<> | 135:176b8275d35d | 4707 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4708 | * @retval None |
<> | 135:176b8275d35d | 4709 | */ |
<> | 135:176b8275d35d | 4710 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4711 | { |
<> | 135:176b8275d35d | 4712 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
<> | 135:176b8275d35d | 4713 | } |
<> | 135:176b8275d35d | 4714 | |
<> | 135:176b8275d35d | 4715 | /** |
<> | 135:176b8275d35d | 4716 | * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. |
<> | 135:176b8275d35d | 4717 | * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 |
<> | 135:176b8275d35d | 4718 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4719 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4720 | */ |
<> | 135:176b8275d35d | 4721 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4722 | { |
<> | 135:176b8275d35d | 4723 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)); |
<> | 135:176b8275d35d | 4724 | } |
<> | 135:176b8275d35d | 4725 | |
<> | 135:176b8275d35d | 4726 | /** |
<> | 135:176b8275d35d | 4727 | * @brief Enable commutation DMA request (COMDE). |
<> | 135:176b8275d35d | 4728 | * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM |
<> | 135:176b8275d35d | 4729 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4730 | * @retval None |
<> | 135:176b8275d35d | 4731 | */ |
<> | 135:176b8275d35d | 4732 | __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4733 | { |
<> | 135:176b8275d35d | 4734 | SET_BIT(TIMx->DIER, TIM_DIER_COMDE); |
<> | 135:176b8275d35d | 4735 | } |
<> | 135:176b8275d35d | 4736 | |
<> | 135:176b8275d35d | 4737 | /** |
<> | 135:176b8275d35d | 4738 | * @brief Disable commutation DMA request (COMDE). |
<> | 135:176b8275d35d | 4739 | * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM |
<> | 135:176b8275d35d | 4740 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4741 | * @retval None |
<> | 135:176b8275d35d | 4742 | */ |
<> | 135:176b8275d35d | 4743 | __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4744 | { |
<> | 135:176b8275d35d | 4745 | CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); |
<> | 135:176b8275d35d | 4746 | } |
<> | 135:176b8275d35d | 4747 | |
<> | 135:176b8275d35d | 4748 | /** |
<> | 135:176b8275d35d | 4749 | * @brief Indicates whether the commutation DMA request (COMDE) is enabled. |
<> | 135:176b8275d35d | 4750 | * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM |
<> | 135:176b8275d35d | 4751 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4752 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4753 | */ |
<> | 135:176b8275d35d | 4754 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4755 | { |
<> | 135:176b8275d35d | 4756 | return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)); |
<> | 135:176b8275d35d | 4757 | } |
<> | 135:176b8275d35d | 4758 | |
<> | 135:176b8275d35d | 4759 | /** |
<> | 135:176b8275d35d | 4760 | * @brief Enable trigger interrupt (TDE). |
<> | 135:176b8275d35d | 4761 | * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG |
<> | 135:176b8275d35d | 4762 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4763 | * @retval None |
<> | 135:176b8275d35d | 4764 | */ |
<> | 135:176b8275d35d | 4765 | __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4766 | { |
<> | 135:176b8275d35d | 4767 | SET_BIT(TIMx->DIER, TIM_DIER_TDE); |
<> | 135:176b8275d35d | 4768 | } |
<> | 135:176b8275d35d | 4769 | |
<> | 135:176b8275d35d | 4770 | /** |
<> | 135:176b8275d35d | 4771 | * @brief Disable trigger interrupt (TDE). |
<> | 135:176b8275d35d | 4772 | * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG |
<> | 135:176b8275d35d | 4773 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4774 | * @retval None |
<> | 135:176b8275d35d | 4775 | */ |
<> | 135:176b8275d35d | 4776 | __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4777 | { |
<> | 135:176b8275d35d | 4778 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); |
<> | 135:176b8275d35d | 4779 | } |
<> | 135:176b8275d35d | 4780 | |
<> | 135:176b8275d35d | 4781 | /** |
<> | 135:176b8275d35d | 4782 | * @brief Indicates whether the trigger interrupt (TDE) is enabled. |
<> | 135:176b8275d35d | 4783 | * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG |
<> | 135:176b8275d35d | 4784 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4785 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 4786 | */ |
<> | 135:176b8275d35d | 4787 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4788 | { |
<> | 135:176b8275d35d | 4789 | return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)); |
<> | 135:176b8275d35d | 4790 | } |
<> | 135:176b8275d35d | 4791 | |
<> | 135:176b8275d35d | 4792 | /** |
<> | 135:176b8275d35d | 4793 | * @} |
<> | 135:176b8275d35d | 4794 | */ |
<> | 135:176b8275d35d | 4795 | |
<> | 135:176b8275d35d | 4796 | /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management |
<> | 135:176b8275d35d | 4797 | * @{ |
<> | 135:176b8275d35d | 4798 | */ |
<> | 135:176b8275d35d | 4799 | /** |
<> | 135:176b8275d35d | 4800 | * @brief Generate an update event. |
<> | 135:176b8275d35d | 4801 | * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE |
<> | 135:176b8275d35d | 4802 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4803 | * @retval None |
<> | 135:176b8275d35d | 4804 | */ |
<> | 135:176b8275d35d | 4805 | __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4806 | { |
<> | 135:176b8275d35d | 4807 | SET_BIT(TIMx->EGR, TIM_EGR_UG); |
<> | 135:176b8275d35d | 4808 | } |
<> | 135:176b8275d35d | 4809 | |
<> | 135:176b8275d35d | 4810 | /** |
<> | 135:176b8275d35d | 4811 | * @brief Generate Capture/Compare 1 event. |
<> | 135:176b8275d35d | 4812 | * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 |
<> | 135:176b8275d35d | 4813 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4814 | * @retval None |
<> | 135:176b8275d35d | 4815 | */ |
<> | 135:176b8275d35d | 4816 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4817 | { |
<> | 135:176b8275d35d | 4818 | SET_BIT(TIMx->EGR, TIM_EGR_CC1G); |
<> | 135:176b8275d35d | 4819 | } |
<> | 135:176b8275d35d | 4820 | |
<> | 135:176b8275d35d | 4821 | /** |
<> | 135:176b8275d35d | 4822 | * @brief Generate Capture/Compare 2 event. |
<> | 135:176b8275d35d | 4823 | * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 |
<> | 135:176b8275d35d | 4824 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4825 | * @retval None |
<> | 135:176b8275d35d | 4826 | */ |
<> | 135:176b8275d35d | 4827 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4828 | { |
<> | 135:176b8275d35d | 4829 | SET_BIT(TIMx->EGR, TIM_EGR_CC2G); |
<> | 135:176b8275d35d | 4830 | } |
<> | 135:176b8275d35d | 4831 | |
<> | 135:176b8275d35d | 4832 | /** |
<> | 135:176b8275d35d | 4833 | * @brief Generate Capture/Compare 3 event. |
<> | 135:176b8275d35d | 4834 | * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 |
<> | 135:176b8275d35d | 4835 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4836 | * @retval None |
<> | 135:176b8275d35d | 4837 | */ |
<> | 135:176b8275d35d | 4838 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4839 | { |
<> | 135:176b8275d35d | 4840 | SET_BIT(TIMx->EGR, TIM_EGR_CC3G); |
<> | 135:176b8275d35d | 4841 | } |
<> | 135:176b8275d35d | 4842 | |
<> | 135:176b8275d35d | 4843 | /** |
<> | 135:176b8275d35d | 4844 | * @brief Generate Capture/Compare 4 event. |
<> | 135:176b8275d35d | 4845 | * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 |
<> | 135:176b8275d35d | 4846 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4847 | * @retval None |
<> | 135:176b8275d35d | 4848 | */ |
<> | 135:176b8275d35d | 4849 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4850 | { |
<> | 135:176b8275d35d | 4851 | SET_BIT(TIMx->EGR, TIM_EGR_CC4G); |
<> | 135:176b8275d35d | 4852 | } |
<> | 135:176b8275d35d | 4853 | |
<> | 135:176b8275d35d | 4854 | /** |
<> | 135:176b8275d35d | 4855 | * @brief Generate commutation event. |
<> | 135:176b8275d35d | 4856 | * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM |
<> | 135:176b8275d35d | 4857 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4858 | * @retval None |
<> | 135:176b8275d35d | 4859 | */ |
<> | 135:176b8275d35d | 4860 | __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4861 | { |
<> | 135:176b8275d35d | 4862 | SET_BIT(TIMx->EGR, TIM_EGR_COMG); |
<> | 135:176b8275d35d | 4863 | } |
<> | 135:176b8275d35d | 4864 | |
<> | 135:176b8275d35d | 4865 | /** |
<> | 135:176b8275d35d | 4866 | * @brief Generate trigger event. |
<> | 135:176b8275d35d | 4867 | * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG |
<> | 135:176b8275d35d | 4868 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4869 | * @retval None |
<> | 135:176b8275d35d | 4870 | */ |
<> | 135:176b8275d35d | 4871 | __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4872 | { |
<> | 135:176b8275d35d | 4873 | SET_BIT(TIMx->EGR, TIM_EGR_TG); |
<> | 135:176b8275d35d | 4874 | } |
<> | 135:176b8275d35d | 4875 | |
<> | 135:176b8275d35d | 4876 | /** |
<> | 135:176b8275d35d | 4877 | * @brief Generate break event. |
<> | 135:176b8275d35d | 4878 | * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK |
<> | 135:176b8275d35d | 4879 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4880 | * @retval None |
<> | 135:176b8275d35d | 4881 | */ |
<> | 135:176b8275d35d | 4882 | __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4883 | { |
<> | 135:176b8275d35d | 4884 | SET_BIT(TIMx->EGR, TIM_EGR_BG); |
<> | 135:176b8275d35d | 4885 | } |
<> | 135:176b8275d35d | 4886 | |
<> | 135:176b8275d35d | 4887 | #if defined(TIM_EGR_B2G) |
<> | 135:176b8275d35d | 4888 | /** |
<> | 135:176b8275d35d | 4889 | * @brief Generate break 2 event. |
<> | 135:176b8275d35d | 4890 | * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 |
<> | 135:176b8275d35d | 4891 | * @param TIMx Timer instance |
<> | 135:176b8275d35d | 4892 | * @retval None |
<> | 135:176b8275d35d | 4893 | */ |
<> | 135:176b8275d35d | 4894 | __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) |
<> | 135:176b8275d35d | 4895 | { |
<> | 135:176b8275d35d | 4896 | SET_BIT(TIMx->EGR, TIM_EGR_B2G); |
<> | 135:176b8275d35d | 4897 | } |
<> | 135:176b8275d35d | 4898 | |
<> | 135:176b8275d35d | 4899 | #endif /* TIM_EGR_B2G */ |
<> | 135:176b8275d35d | 4900 | /** |
<> | 135:176b8275d35d | 4901 | * @} |
<> | 135:176b8275d35d | 4902 | */ |
<> | 135:176b8275d35d | 4903 | |
<> | 135:176b8275d35d | 4904 | #if defined(USE_FULL_LL_DRIVER) |
<> | 135:176b8275d35d | 4905 | /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions |
<> | 135:176b8275d35d | 4906 | * @{ |
<> | 135:176b8275d35d | 4907 | */ |
<> | 135:176b8275d35d | 4908 | |
<> | 135:176b8275d35d | 4909 | ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); |
<> | 135:176b8275d35d | 4910 | void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); |
<> | 135:176b8275d35d | 4911 | ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); |
<> | 135:176b8275d35d | 4912 | void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
<> | 135:176b8275d35d | 4913 | ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
<> | 135:176b8275d35d | 4914 | void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
<> | 135:176b8275d35d | 4915 | ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); |
<> | 135:176b8275d35d | 4916 | void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
<> | 135:176b8275d35d | 4917 | ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
<> | 135:176b8275d35d | 4918 | void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); |
<> | 135:176b8275d35d | 4919 | ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); |
<> | 135:176b8275d35d | 4920 | void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); |
<> | 135:176b8275d35d | 4921 | ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); |
<> | 135:176b8275d35d | 4922 | /** |
<> | 135:176b8275d35d | 4923 | * @} |
<> | 135:176b8275d35d | 4924 | */ |
<> | 135:176b8275d35d | 4925 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 135:176b8275d35d | 4926 | |
<> | 135:176b8275d35d | 4927 | /** |
<> | 135:176b8275d35d | 4928 | * @} |
<> | 135:176b8275d35d | 4929 | */ |
<> | 135:176b8275d35d | 4930 | |
<> | 135:176b8275d35d | 4931 | /** |
<> | 135:176b8275d35d | 4932 | * @} |
<> | 135:176b8275d35d | 4933 | */ |
<> | 135:176b8275d35d | 4934 | |
<> | 135:176b8275d35d | 4935 | #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */ |
<> | 135:176b8275d35d | 4936 | |
<> | 135:176b8275d35d | 4937 | /** |
<> | 135:176b8275d35d | 4938 | * @} |
<> | 135:176b8275d35d | 4939 | */ |
<> | 135:176b8275d35d | 4940 | |
<> | 135:176b8275d35d | 4941 | #ifdef __cplusplus |
<> | 135:176b8275d35d | 4942 | } |
<> | 135:176b8275d35d | 4943 | #endif |
<> | 135:176b8275d35d | 4944 | |
<> | 135:176b8275d35d | 4945 | #endif /* __STM32F3xx_LL_TIM_H */ |
<> | 135:176b8275d35d | 4946 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |