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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_wwdg.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
134:ad3be0349dc5
Child:
160:5571c4ff569f
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 134:ad3be0349dc5 1 /**
<> 134:ad3be0349dc5 2 ******************************************************************************
<> 134:ad3be0349dc5 3 * @file stm32f0xx_ll_wwdg.h
<> 134:ad3be0349dc5 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.4.0
<> 134:ad3be0349dc5 6 * @date 27-May-2016
<> 134:ad3be0349dc5 7 * @brief Header file of WWDG LL module.
<> 134:ad3be0349dc5 8 ******************************************************************************
<> 134:ad3be0349dc5 9 * @attention
<> 134:ad3be0349dc5 10 *
<> 134:ad3be0349dc5 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 134:ad3be0349dc5 12 *
<> 134:ad3be0349dc5 13 * Redistribution and use in source and binary forms, with or without modification,
<> 134:ad3be0349dc5 14 * are permitted provided that the following conditions are met:
<> 134:ad3be0349dc5 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 134:ad3be0349dc5 16 * this list of conditions and the following disclaimer.
<> 134:ad3be0349dc5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 134:ad3be0349dc5 18 * this list of conditions and the following disclaimer in the documentation
<> 134:ad3be0349dc5 19 * and/or other materials provided with the distribution.
<> 134:ad3be0349dc5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 134:ad3be0349dc5 21 * may be used to endorse or promote products derived from this software
<> 134:ad3be0349dc5 22 * without specific prior written permission.
<> 134:ad3be0349dc5 23 *
<> 134:ad3be0349dc5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 134:ad3be0349dc5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 134:ad3be0349dc5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 134:ad3be0349dc5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 134:ad3be0349dc5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 134:ad3be0349dc5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 134:ad3be0349dc5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 134:ad3be0349dc5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 134:ad3be0349dc5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 134:ad3be0349dc5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 134:ad3be0349dc5 34 *
<> 134:ad3be0349dc5 35 ******************************************************************************
<> 134:ad3be0349dc5 36 */
<> 134:ad3be0349dc5 37
<> 134:ad3be0349dc5 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 134:ad3be0349dc5 39 #ifndef __STM32F0xx_LL_WWDG_H
<> 134:ad3be0349dc5 40 #define __STM32F0xx_LL_WWDG_H
<> 134:ad3be0349dc5 41
<> 134:ad3be0349dc5 42 #ifdef __cplusplus
<> 134:ad3be0349dc5 43 extern "C" {
<> 134:ad3be0349dc5 44 #endif
<> 134:ad3be0349dc5 45
<> 134:ad3be0349dc5 46 /* Includes ------------------------------------------------------------------*/
<> 134:ad3be0349dc5 47 #include "stm32f0xx.h"
<> 134:ad3be0349dc5 48
<> 134:ad3be0349dc5 49 /** @addtogroup STM32F0xx_LL_Driver
<> 134:ad3be0349dc5 50 * @{
<> 134:ad3be0349dc5 51 */
<> 134:ad3be0349dc5 52
<> 134:ad3be0349dc5 53 #if defined (WWDG)
<> 134:ad3be0349dc5 54
<> 134:ad3be0349dc5 55 /** @defgroup WWDG_LL WWDG
<> 134:ad3be0349dc5 56 * @{
<> 134:ad3be0349dc5 57 */
<> 134:ad3be0349dc5 58
<> 134:ad3be0349dc5 59 /* Private types -------------------------------------------------------------*/
<> 134:ad3be0349dc5 60 /* Private variables ---------------------------------------------------------*/
<> 134:ad3be0349dc5 61
<> 134:ad3be0349dc5 62 /* Private constants ---------------------------------------------------------*/
<> 134:ad3be0349dc5 63
<> 134:ad3be0349dc5 64 /* Private macros ------------------------------------------------------------*/
<> 134:ad3be0349dc5 65
<> 134:ad3be0349dc5 66 /* Exported types ------------------------------------------------------------*/
<> 134:ad3be0349dc5 67 /* Exported constants --------------------------------------------------------*/
<> 134:ad3be0349dc5 68 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
<> 134:ad3be0349dc5 69 * @{
<> 134:ad3be0349dc5 70 */
<> 134:ad3be0349dc5 71
<> 134:ad3be0349dc5 72
<> 134:ad3be0349dc5 73 /** @defgroup WWDG_LL_EC_IT IT Defines
<> 134:ad3be0349dc5 74 * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
<> 134:ad3be0349dc5 75 * @{
<> 134:ad3be0349dc5 76 */
<> 134:ad3be0349dc5 77 #define LL_WWDG_CFR_EWI WWDG_CFR_EWI
<> 134:ad3be0349dc5 78 /**
<> 134:ad3be0349dc5 79 * @}
<> 134:ad3be0349dc5 80 */
<> 134:ad3be0349dc5 81
<> 134:ad3be0349dc5 82 /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
<> 134:ad3be0349dc5 83 * @{
<> 134:ad3be0349dc5 84 */
<> 134:ad3be0349dc5 85 #define LL_WWDG_PRESCALER_1 (uint32_t)0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
<> 134:ad3be0349dc5 86 #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
<> 134:ad3be0349dc5 87 #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
<> 134:ad3be0349dc5 88 #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
<> 134:ad3be0349dc5 89 /**
<> 134:ad3be0349dc5 90 * @}
<> 134:ad3be0349dc5 91 */
<> 134:ad3be0349dc5 92
<> 134:ad3be0349dc5 93 /**
<> 134:ad3be0349dc5 94 * @}
<> 134:ad3be0349dc5 95 */
<> 134:ad3be0349dc5 96
<> 134:ad3be0349dc5 97 /* Exported macro ------------------------------------------------------------*/
<> 134:ad3be0349dc5 98 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
<> 134:ad3be0349dc5 99 * @{
<> 134:ad3be0349dc5 100 */
<> 134:ad3be0349dc5 101 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
<> 134:ad3be0349dc5 102 * @{
<> 134:ad3be0349dc5 103 */
<> 134:ad3be0349dc5 104 /**
<> 134:ad3be0349dc5 105 * @brief Write a value in WWDG register
<> 134:ad3be0349dc5 106 * @param __INSTANCE__ WWDG Instance
<> 134:ad3be0349dc5 107 * @param __REG__ Register to be written
<> 134:ad3be0349dc5 108 * @param __VALUE__ Value to be written in the register
<> 134:ad3be0349dc5 109 * @retval None
<> 134:ad3be0349dc5 110 */
<> 134:ad3be0349dc5 111 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 134:ad3be0349dc5 112
<> 134:ad3be0349dc5 113 /**
<> 134:ad3be0349dc5 114 * @brief Read a value in WWDG register
<> 134:ad3be0349dc5 115 * @param __INSTANCE__ WWDG Instance
<> 134:ad3be0349dc5 116 * @param __REG__ Register to be read
<> 134:ad3be0349dc5 117 * @retval Register value
<> 134:ad3be0349dc5 118 */
<> 134:ad3be0349dc5 119 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 134:ad3be0349dc5 120 /**
<> 134:ad3be0349dc5 121 * @}
<> 134:ad3be0349dc5 122 */
<> 134:ad3be0349dc5 123
<> 134:ad3be0349dc5 124
<> 134:ad3be0349dc5 125 /**
<> 134:ad3be0349dc5 126 * @}
<> 134:ad3be0349dc5 127 */
<> 134:ad3be0349dc5 128
<> 134:ad3be0349dc5 129 /* Exported functions --------------------------------------------------------*/
<> 134:ad3be0349dc5 130 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
<> 134:ad3be0349dc5 131 * @{
<> 134:ad3be0349dc5 132 */
<> 134:ad3be0349dc5 133
<> 134:ad3be0349dc5 134 /** @defgroup WWDG_LL_EF_Configuration Configuration
<> 134:ad3be0349dc5 135 * @{
<> 134:ad3be0349dc5 136 */
<> 134:ad3be0349dc5 137 /**
<> 134:ad3be0349dc5 138 * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
<> 134:ad3be0349dc5 139 * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
<> 134:ad3be0349dc5 140 * then it cannot be disabled again except by a reset.
<> 134:ad3be0349dc5 141 * This bit is set by software and only cleared by hardware after a reset.
<> 134:ad3be0349dc5 142 * When WDGA = 1, the watchdog can generate a reset.
<> 134:ad3be0349dc5 143 * @rmtoll CR WDGA LL_WWDG_Enable
<> 134:ad3be0349dc5 144 * @param WWDGx WWDG Instance
<> 134:ad3be0349dc5 145 * @retval None
<> 134:ad3be0349dc5 146 */
<> 134:ad3be0349dc5 147 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
<> 134:ad3be0349dc5 148 {
<> 134:ad3be0349dc5 149 SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
<> 134:ad3be0349dc5 150 }
<> 134:ad3be0349dc5 151
<> 134:ad3be0349dc5 152 /**
<> 134:ad3be0349dc5 153 * @brief Checks if Window Watchdog is enabled
<> 134:ad3be0349dc5 154 * @rmtoll CR WDGA LL_WWDG_IsEnabled
<> 134:ad3be0349dc5 155 * @param WWDGx WWDG Instance
<> 134:ad3be0349dc5 156 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 157 */
<> 134:ad3be0349dc5 158 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
<> 134:ad3be0349dc5 159 {
<> 134:ad3be0349dc5 160 return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
<> 134:ad3be0349dc5 161 }
<> 134:ad3be0349dc5 162
<> 134:ad3be0349dc5 163 /**
<> 134:ad3be0349dc5 164 * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
<> 134:ad3be0349dc5 165 * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
<> 134:ad3be0349dc5 166 * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
<> 134:ad3be0349dc5 167 * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
<> 134:ad3be0349dc5 168 * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
<> 134:ad3be0349dc5 169 * @rmtoll CR T LL_WWDG_SetCounter
<> 134:ad3be0349dc5 170 * @param WWDGx WWDG Instance
<> 134:ad3be0349dc5 171 * @param Counter 0..0x7F (7 bit counter value)
<> 134:ad3be0349dc5 172 * @retval None
<> 134:ad3be0349dc5 173 */
<> 134:ad3be0349dc5 174 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
<> 134:ad3be0349dc5 175 {
<> 134:ad3be0349dc5 176 MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
<> 134:ad3be0349dc5 177 }
<> 134:ad3be0349dc5 178
<> 134:ad3be0349dc5 179 /**
<> 134:ad3be0349dc5 180 * @brief Return current Watchdog Counter Value (7 bits counter value)
<> 134:ad3be0349dc5 181 * @rmtoll CR T LL_WWDG_GetCounter
<> 134:ad3be0349dc5 182 * @param WWDGx WWDG Instance
<> 134:ad3be0349dc5 183 * @retval 7 bit Watchdog Counter value
<> 134:ad3be0349dc5 184 */
<> 134:ad3be0349dc5 185 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
<> 134:ad3be0349dc5 186 {
<> 134:ad3be0349dc5 187 return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
<> 134:ad3be0349dc5 188 }
<> 134:ad3be0349dc5 189
<> 134:ad3be0349dc5 190 /**
<> 134:ad3be0349dc5 191 * @brief Set the time base of the prescaler (WDGTB).
<> 134:ad3be0349dc5 192 * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
<> 134:ad3be0349dc5 193 * is decremented every (4096 x 2expWDGTB) PCLK cycles
<> 134:ad3be0349dc5 194 * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
<> 134:ad3be0349dc5 195 * @param WWDGx WWDG Instance
<> 134:ad3be0349dc5 196 * @param Prescaler This parameter can be one of the following values:
<> 134:ad3be0349dc5 197 * @arg @ref LL_WWDG_PRESCALER_1
<> 134:ad3be0349dc5 198 * @arg @ref LL_WWDG_PRESCALER_2
<> 134:ad3be0349dc5 199 * @arg @ref LL_WWDG_PRESCALER_4
<> 134:ad3be0349dc5 200 * @arg @ref LL_WWDG_PRESCALER_8
<> 134:ad3be0349dc5 201 * @retval None
<> 134:ad3be0349dc5 202 */
<> 134:ad3be0349dc5 203 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
<> 134:ad3be0349dc5 204 {
<> 134:ad3be0349dc5 205 MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
<> 134:ad3be0349dc5 206 }
<> 134:ad3be0349dc5 207
<> 134:ad3be0349dc5 208 /**
<> 134:ad3be0349dc5 209 * @brief Return current Watchdog Prescaler Value
<> 134:ad3be0349dc5 210 * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
<> 134:ad3be0349dc5 211 * @param WWDGx WWDG Instance
<> 134:ad3be0349dc5 212 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 213 * @arg @ref LL_WWDG_PRESCALER_1
<> 134:ad3be0349dc5 214 * @arg @ref LL_WWDG_PRESCALER_2
<> 134:ad3be0349dc5 215 * @arg @ref LL_WWDG_PRESCALER_4
<> 134:ad3be0349dc5 216 * @arg @ref LL_WWDG_PRESCALER_8
<> 134:ad3be0349dc5 217 */
<> 134:ad3be0349dc5 218 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
<> 134:ad3be0349dc5 219 {
<> 134:ad3be0349dc5 220 return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
<> 134:ad3be0349dc5 221 }
<> 134:ad3be0349dc5 222
<> 134:ad3be0349dc5 223 /**
<> 134:ad3be0349dc5 224 * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
<> 134:ad3be0349dc5 225 * @note This window value defines when write in the WWDG_CR register
<> 134:ad3be0349dc5 226 * to program Watchdog counter is allowed.
<> 134:ad3be0349dc5 227 * Watchdog counter value update must occur only when the counter value
<> 134:ad3be0349dc5 228 * is lower than the Watchdog window register value.
<> 134:ad3be0349dc5 229 * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
<> 134:ad3be0349dc5 230 * (in the control register) is refreshed before the downcounter has reached
<> 134:ad3be0349dc5 231 * the watchdog window register value.
<> 134:ad3be0349dc5 232 * Physically is possible to set the Window lower then 0x40 but it is not recommended.
<> 134:ad3be0349dc5 233 * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
<> 134:ad3be0349dc5 234 * @rmtoll CFR W LL_WWDG_SetWindow
<> 134:ad3be0349dc5 235 * @param WWDGx WWDG Instance
<> 134:ad3be0349dc5 236 * @param Window 0x00..0x7F (7 bit Window value)
<> 134:ad3be0349dc5 237 * @retval None
<> 134:ad3be0349dc5 238 */
<> 134:ad3be0349dc5 239 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
<> 134:ad3be0349dc5 240 {
<> 134:ad3be0349dc5 241 MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
<> 134:ad3be0349dc5 242 }
<> 134:ad3be0349dc5 243
<> 134:ad3be0349dc5 244 /**
<> 134:ad3be0349dc5 245 * @brief Return current Watchdog Window Value (7 bits value)
<> 134:ad3be0349dc5 246 * @rmtoll CFR W LL_WWDG_GetWindow
<> 134:ad3be0349dc5 247 * @param WWDGx WWDG Instance
<> 134:ad3be0349dc5 248 * @retval 7 bit Watchdog Window value
<> 134:ad3be0349dc5 249 */
<> 134:ad3be0349dc5 250 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
<> 134:ad3be0349dc5 251 {
<> 134:ad3be0349dc5 252 return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
<> 134:ad3be0349dc5 253 }
<> 134:ad3be0349dc5 254
<> 134:ad3be0349dc5 255 /**
<> 134:ad3be0349dc5 256 * @}
<> 134:ad3be0349dc5 257 */
<> 134:ad3be0349dc5 258
<> 134:ad3be0349dc5 259 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
<> 134:ad3be0349dc5 260 * @{
<> 134:ad3be0349dc5 261 */
<> 134:ad3be0349dc5 262 /**
<> 134:ad3be0349dc5 263 * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
<> 134:ad3be0349dc5 264 * @note This bit is set by hardware when the counter has reached the value 0x40.
<> 134:ad3be0349dc5 265 * It must be cleared by software by writing 0.
<> 134:ad3be0349dc5 266 * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
<> 134:ad3be0349dc5 267 * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
<> 134:ad3be0349dc5 268 * @param WWDGx WWDG Instance
<> 134:ad3be0349dc5 269 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 270 */
<> 134:ad3be0349dc5 271 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
<> 134:ad3be0349dc5 272 {
<> 134:ad3be0349dc5 273 return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
<> 134:ad3be0349dc5 274 }
<> 134:ad3be0349dc5 275
<> 134:ad3be0349dc5 276 /**
<> 134:ad3be0349dc5 277 * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
<> 134:ad3be0349dc5 278 * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
<> 134:ad3be0349dc5 279 * @param WWDGx WWDG Instance
<> 134:ad3be0349dc5 280 * @retval None
<> 134:ad3be0349dc5 281 */
<> 134:ad3be0349dc5 282 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
<> 134:ad3be0349dc5 283 {
<> 134:ad3be0349dc5 284 WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
<> 134:ad3be0349dc5 285 }
<> 134:ad3be0349dc5 286
<> 134:ad3be0349dc5 287 /**
<> 134:ad3be0349dc5 288 * @}
<> 134:ad3be0349dc5 289 */
<> 134:ad3be0349dc5 290
<> 134:ad3be0349dc5 291 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
<> 134:ad3be0349dc5 292 * @{
<> 134:ad3be0349dc5 293 */
<> 134:ad3be0349dc5 294 /**
<> 134:ad3be0349dc5 295 * @brief Enable the Early Wakeup Interrupt.
<> 134:ad3be0349dc5 296 * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
<> 134:ad3be0349dc5 297 * This interrupt is only cleared by hardware after a reset
<> 134:ad3be0349dc5 298 * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
<> 134:ad3be0349dc5 299 * @param WWDGx WWDG Instance
<> 134:ad3be0349dc5 300 * @retval None
<> 134:ad3be0349dc5 301 */
<> 134:ad3be0349dc5 302 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
<> 134:ad3be0349dc5 303 {
<> 134:ad3be0349dc5 304 SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
<> 134:ad3be0349dc5 305 }
<> 134:ad3be0349dc5 306
<> 134:ad3be0349dc5 307 /**
<> 134:ad3be0349dc5 308 * @brief Check if Early Wakeup Interrupt is enabled
<> 134:ad3be0349dc5 309 * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
<> 134:ad3be0349dc5 310 * @param WWDGx WWDG Instance
<> 134:ad3be0349dc5 311 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 312 */
<> 134:ad3be0349dc5 313 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
<> 134:ad3be0349dc5 314 {
<> 134:ad3be0349dc5 315 return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
<> 134:ad3be0349dc5 316 }
<> 134:ad3be0349dc5 317
<> 134:ad3be0349dc5 318 /**
<> 134:ad3be0349dc5 319 * @}
<> 134:ad3be0349dc5 320 */
<> 134:ad3be0349dc5 321
<> 134:ad3be0349dc5 322 /**
<> 134:ad3be0349dc5 323 * @}
<> 134:ad3be0349dc5 324 */
<> 134:ad3be0349dc5 325
<> 134:ad3be0349dc5 326 /**
<> 134:ad3be0349dc5 327 * @}
<> 134:ad3be0349dc5 328 */
<> 134:ad3be0349dc5 329
<> 134:ad3be0349dc5 330 #endif /* WWDG */
<> 134:ad3be0349dc5 331
<> 134:ad3be0349dc5 332 /**
<> 134:ad3be0349dc5 333 * @}
<> 134:ad3be0349dc5 334 */
<> 134:ad3be0349dc5 335
<> 134:ad3be0349dc5 336 #ifdef __cplusplus
<> 134:ad3be0349dc5 337 }
<> 134:ad3be0349dc5 338 #endif
<> 134:ad3be0349dc5 339
<> 134:ad3be0349dc5 340 #endif /* __STM32F0xx_LL_WWDG_H */
<> 134:ad3be0349dc5 341
<> 134:ad3be0349dc5 342 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/