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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Parent:: 134:ad3be0349dc5
Child:: 160:5571c4ff569f

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	134:ad3be0349dc5	1	/**
<>	134:ad3be0349dc5	2	******************************************************************************
<>	134:ad3be0349dc5	3	* @file stm32f0xx_ll_tim.h
<>	134:ad3be0349dc5	4	* @author MCD Application Team
<>	134:ad3be0349dc5	5	* @version V1.4.0
<>	134:ad3be0349dc5	6	* @date 27-May-2016
<>	134:ad3be0349dc5	7	* @brief Header file of TIM LL module.
<>	134:ad3be0349dc5	8	******************************************************************************
<>	134:ad3be0349dc5	9	* @attention
<>	134:ad3be0349dc5	10	*
<>	134:ad3be0349dc5	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	134:ad3be0349dc5	12	*
<>	134:ad3be0349dc5	13	* Redistribution and use in source and binary forms, with or without modification,
<>	134:ad3be0349dc5	14	* are permitted provided that the following conditions are met:
<>	134:ad3be0349dc5	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	134:ad3be0349dc5	16	* this list of conditions and the following disclaimer.
<>	134:ad3be0349dc5	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	134:ad3be0349dc5	18	* this list of conditions and the following disclaimer in the documentation
<>	134:ad3be0349dc5	19	* and/or other materials provided with the distribution.
<>	134:ad3be0349dc5	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	134:ad3be0349dc5	21	* may be used to endorse or promote products derived from this software
<>	134:ad3be0349dc5	22	* without specific prior written permission.
<>	134:ad3be0349dc5	23	*
<>	134:ad3be0349dc5	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	134:ad3be0349dc5	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	134:ad3be0349dc5	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	134:ad3be0349dc5	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	134:ad3be0349dc5	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	134:ad3be0349dc5	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	134:ad3be0349dc5	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	134:ad3be0349dc5	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	134:ad3be0349dc5	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	134:ad3be0349dc5	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	134:ad3be0349dc5	34	*
<>	134:ad3be0349dc5	35	******************************************************************************
<>	134:ad3be0349dc5	36	*/
<>	134:ad3be0349dc5	37
<>	134:ad3be0349dc5	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	134:ad3be0349dc5	39	#ifndef __STM32F0xx_LL_TIM_H
<>	134:ad3be0349dc5	40	#define __STM32F0xx_LL_TIM_H
<>	134:ad3be0349dc5	41
<>	134:ad3be0349dc5	42	#ifdef __cplusplus
<>	134:ad3be0349dc5	43	extern "C" {
<>	134:ad3be0349dc5	44	#endif
<>	134:ad3be0349dc5	45
<>	134:ad3be0349dc5	46	/* Includes ------------------------------------------------------------------*/
<>	134:ad3be0349dc5	47	#include "stm32f0xx.h"
<>	134:ad3be0349dc5	48
<>	134:ad3be0349dc5	49	/** @addtogroup STM32F0xx_LL_Driver
<>	134:ad3be0349dc5	50	* @{
<>	134:ad3be0349dc5	51	*/
<>	134:ad3be0349dc5	52
<>	134:ad3be0349dc5	53	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM6) \|\| defined (TIM7)
<>	134:ad3be0349dc5	54
<>	134:ad3be0349dc5	55	/** @defgroup TIM_LL TIM
<>	134:ad3be0349dc5	56	* @{
<>	134:ad3be0349dc5	57	*/
<>	134:ad3be0349dc5	58
<>	134:ad3be0349dc5	59	/* Private types -------------------------------------------------------------*/
<>	134:ad3be0349dc5	60	/* Private variables ---------------------------------------------------------*/
<>	134:ad3be0349dc5	61	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
<>	134:ad3be0349dc5	62	* @{
<>	134:ad3be0349dc5	63	*/
<>	134:ad3be0349dc5	64	static const uint8_t OFFSET_TAB_CCMRx[] =
<>	134:ad3be0349dc5	65	{
<>	134:ad3be0349dc5	66	0x00U, /* 0: TIMx_CH1 */
<>	134:ad3be0349dc5	67	0x00U, /* 1: TIMx_CH1N */
<>	134:ad3be0349dc5	68	0x00U, /* 2: TIMx_CH2 */
<>	134:ad3be0349dc5	69	0x00U, /* 3: TIMx_CH2N */
<>	134:ad3be0349dc5	70	0x04U, /* 4: TIMx_CH3 */
<>	134:ad3be0349dc5	71	0x04U, /* 5: TIMx_CH3N */
<>	134:ad3be0349dc5	72	0x04U /* 6: TIMx_CH4 */
<>	134:ad3be0349dc5	73	};
<>	134:ad3be0349dc5	74
<>	134:ad3be0349dc5	75	static const uint8_t SHIFT_TAB_OCxx[] =
<>	134:ad3be0349dc5	76	{
<>	134:ad3be0349dc5	77	0U, /* 0: OC1M, OC1FE, OC1PE */
<>	134:ad3be0349dc5	78	0U, /* 1: - NA */
<>	134:ad3be0349dc5	79	8U, /* 2: OC2M, OC2FE, OC2PE */
<>	134:ad3be0349dc5	80	0U, /* 3: - NA */
<>	134:ad3be0349dc5	81	0U, /* 4: OC3M, OC3FE, OC3PE */
<>	134:ad3be0349dc5	82	0U, /* 5: - NA */
<>	134:ad3be0349dc5	83	8U /* 6: OC4M, OC4FE, OC4PE */
<>	134:ad3be0349dc5	84	};
<>	134:ad3be0349dc5	85
<>	134:ad3be0349dc5	86	static const uint8_t SHIFT_TAB_ICxx[] =
<>	134:ad3be0349dc5	87	{
<>	134:ad3be0349dc5	88	0U, /* 0: CC1S, IC1PSC, IC1F */
<>	134:ad3be0349dc5	89	0U, /* 1: - NA */
<>	134:ad3be0349dc5	90	8U, /* 2: CC2S, IC2PSC, IC2F */
<>	134:ad3be0349dc5	91	0U, /* 3: - NA */
<>	134:ad3be0349dc5	92	0U, /* 4: CC3S, IC3PSC, IC3F */
<>	134:ad3be0349dc5	93	0U, /* 5: - NA */
<>	134:ad3be0349dc5	94	8U /* 6: CC4S, IC4PSC, IC4F */
<>	134:ad3be0349dc5	95	};
<>	134:ad3be0349dc5	96
<>	134:ad3be0349dc5	97	static const uint8_t SHIFT_TAB_CCxP[] =
<>	134:ad3be0349dc5	98	{
<>	134:ad3be0349dc5	99	0U, /* 0: CC1P */
<>	134:ad3be0349dc5	100	2U, /* 1: CC1NP */
<>	134:ad3be0349dc5	101	4U, /* 2: CC2P */
<>	134:ad3be0349dc5	102	6U, /* 3: CC2NP */
<>	134:ad3be0349dc5	103	8U, /* 4: CC3P */
<>	134:ad3be0349dc5	104	10U, /* 5: CC3NP */
<>	134:ad3be0349dc5	105	12U /* 6: CC4P */
<>	134:ad3be0349dc5	106	};
<>	134:ad3be0349dc5	107
<>	134:ad3be0349dc5	108	static const uint8_t SHIFT_TAB_OISx[] =
<>	134:ad3be0349dc5	109	{
<>	134:ad3be0349dc5	110	0U, /* 0: OIS1 */
<>	134:ad3be0349dc5	111	1U, /* 1: OIS1N */
<>	134:ad3be0349dc5	112	2U, /* 2: OIS2 */
<>	134:ad3be0349dc5	113	3U, /* 3: OIS2N */
<>	134:ad3be0349dc5	114	4U, /* 4: OIS3 */
<>	134:ad3be0349dc5	115	5U, /* 5: OIS3N */
<>	134:ad3be0349dc5	116	6U /* 6: OIS4 */
<>	134:ad3be0349dc5	117	};
<>	134:ad3be0349dc5	118	/**
<>	134:ad3be0349dc5	119	* @}
<>	134:ad3be0349dc5	120	*/
<>	134:ad3be0349dc5	121
<>	134:ad3be0349dc5	122
<>	134:ad3be0349dc5	123	/* Private constants ---------------------------------------------------------*/
<>	134:ad3be0349dc5	124	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
<>	134:ad3be0349dc5	125	* @{
<>	134:ad3be0349dc5	126	*/
<>	134:ad3be0349dc5	127
<>	134:ad3be0349dc5	128
<>	134:ad3be0349dc5	129	#define TIMx_OR_RMP_SHIFT ((uint32_t)16U)
<>	134:ad3be0349dc5	130	#define TIMx_OR_RMP_MASK ((uint32_t)0x0000FFFFU)
<>	134:ad3be0349dc5	131	#define TIM14_OR_RMP_MASK ((uint32_t)(TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT))
<>	134:ad3be0349dc5	132
<>	134:ad3be0349dc5	133	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
<>	134:ad3be0349dc5	134	#define DT_DELAY_1 ((uint8_t)0x7FU)
<>	134:ad3be0349dc5	135	#define DT_DELAY_2 ((uint8_t)0x3FU)
<>	134:ad3be0349dc5	136	#define DT_DELAY_3 ((uint8_t)0x1FU)
<>	134:ad3be0349dc5	137	#define DT_DELAY_4 ((uint8_t)0x1FU)
<>	134:ad3be0349dc5	138
<>	134:ad3be0349dc5	139	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
<>	134:ad3be0349dc5	140	#define DT_RANGE_1 ((uint8_t)0x00U)
<>	134:ad3be0349dc5	141	#define DT_RANGE_2 ((uint8_t)0x80U)
<>	134:ad3be0349dc5	142	#define DT_RANGE_3 ((uint8_t)0xC0U)
<>	134:ad3be0349dc5	143	#define DT_RANGE_4 ((uint8_t)0xE0U)
<>	134:ad3be0349dc5	144
<>	134:ad3be0349dc5	145
<>	134:ad3be0349dc5	146	/**
<>	134:ad3be0349dc5	147	* @}
<>	134:ad3be0349dc5	148	*/
<>	134:ad3be0349dc5	149
<>	134:ad3be0349dc5	150
<>	134:ad3be0349dc5	151	/* Private macros ------------------------------------------------------------*/
<>	134:ad3be0349dc5	152	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
<>	134:ad3be0349dc5	153	* @{
<>	134:ad3be0349dc5	154	*/
<>	134:ad3be0349dc5	155	/** @brief Convert channel id into channel index.
<>	134:ad3be0349dc5	156	* @param __CHANNEL__ This parameter can be one of the following values:
<>	134:ad3be0349dc5	157	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	158	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	134:ad3be0349dc5	159	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	160	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	134:ad3be0349dc5	161	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	162	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	134:ad3be0349dc5	163	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	164	* @retval none
<>	134:ad3be0349dc5	165	*/
<>	134:ad3be0349dc5	166	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
<>	134:ad3be0349dc5	167	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
<>	134:ad3be0349dc5	168	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
<>	134:ad3be0349dc5	169	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
<>	134:ad3be0349dc5	170	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
<>	134:ad3be0349dc5	171	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
<>	134:ad3be0349dc5	172	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
<>	134:ad3be0349dc5	173
<>	134:ad3be0349dc5	174	/** @brief Calculate the deadtime sampling period(in ps).
<>	134:ad3be0349dc5	175	* @param __TIMCLK__ timer input clock frequency (in Hz).
<>	134:ad3be0349dc5	176	* @param __CKD__ This parameter can be one of the following values:
<>	134:ad3be0349dc5	177	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	134:ad3be0349dc5	178	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	134:ad3be0349dc5	179	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	134:ad3be0349dc5	180	* @retval none
<>	134:ad3be0349dc5	181	*/
<>	134:ad3be0349dc5	182	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
<>	134:ad3be0349dc5	183	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
<>	134:ad3be0349dc5	184	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
<>	134:ad3be0349dc5	185	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
<>	134:ad3be0349dc5	186	/**
<>	134:ad3be0349dc5	187	* @}
<>	134:ad3be0349dc5	188	*/
<>	134:ad3be0349dc5	189
<>	134:ad3be0349dc5	190
<>	134:ad3be0349dc5	191	/* Exported types ------------------------------------------------------------*/
<>	134:ad3be0349dc5	192	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	193	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
<>	134:ad3be0349dc5	194	* @{
<>	134:ad3be0349dc5	195	*/
<>	134:ad3be0349dc5	196
<>	134:ad3be0349dc5	197	/**
<>	134:ad3be0349dc5	198	* @brief TIM Time Base configuration structure definition.
<>	134:ad3be0349dc5	199	*/
<>	134:ad3be0349dc5	200	typedef struct
<>	134:ad3be0349dc5	201	{
<>	134:ad3be0349dc5	202	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<>	134:ad3be0349dc5	203	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	134:ad3be0349dc5	204
<>	134:ad3be0349dc5	205	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
<>	134:ad3be0349dc5	206
<>	134:ad3be0349dc5	207	uint32_t CounterMode; /*!< Specifies the counter mode.
<>	134:ad3be0349dc5	208	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
<>	134:ad3be0349dc5	209
<>	134:ad3be0349dc5	210	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
<>	134:ad3be0349dc5	211
<>	134:ad3be0349dc5	212	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
<>	134:ad3be0349dc5	213	Auto-Reload Register at the next update event.
<>	134:ad3be0349dc5	214	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	134:ad3be0349dc5	215	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
<>	134:ad3be0349dc5	216
<>	134:ad3be0349dc5	217	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
<>	134:ad3be0349dc5	218
<>	134:ad3be0349dc5	219	uint32_t ClockDivision; /*!< Specifies the clock division.
<>	134:ad3be0349dc5	220	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
<>	134:ad3be0349dc5	221
<>	134:ad3be0349dc5	222	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
<>	134:ad3be0349dc5	223
<>	134:ad3be0349dc5	224	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
<>	134:ad3be0349dc5	225	reaches zero, an update event is generated and counting restarts
<>	134:ad3be0349dc5	226	from the RCR value (N).
<>	134:ad3be0349dc5	227	This means in PWM mode that (N+1) corresponds to:
<>	134:ad3be0349dc5	228	- the number of PWM periods in edge-aligned mode
<>	134:ad3be0349dc5	229	- the number of half PWM period in center-aligned mode
<>	134:ad3be0349dc5	230	This parameter must be a number between 0x00 and 0xFF.
<>	134:ad3be0349dc5	231
<>	134:ad3be0349dc5	232	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
<>	134:ad3be0349dc5	233	} LL_TIM_InitTypeDef;
<>	134:ad3be0349dc5	234
<>	134:ad3be0349dc5	235	/**
<>	134:ad3be0349dc5	236	* @brief TIM Output Compare configuration structure definition.
<>	134:ad3be0349dc5	237	*/
<>	134:ad3be0349dc5	238	typedef struct
<>	134:ad3be0349dc5	239	{
<>	134:ad3be0349dc5	240	uint32_t OCMode; /*!< Specifies the output mode.
<>	134:ad3be0349dc5	241	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
<>	134:ad3be0349dc5	242
<>	134:ad3be0349dc5	243	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
<>	134:ad3be0349dc5	244
<>	134:ad3be0349dc5	245	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
<>	134:ad3be0349dc5	246	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
<>	134:ad3be0349dc5	247
<>	134:ad3be0349dc5	248	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
<>	134:ad3be0349dc5	249
<>	134:ad3be0349dc5	250	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
<>	134:ad3be0349dc5	251	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
<>	134:ad3be0349dc5	252
<>	134:ad3be0349dc5	253	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
<>	134:ad3be0349dc5	254
<>	134:ad3be0349dc5	255	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
<>	134:ad3be0349dc5	256	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	134:ad3be0349dc5	257
<>	134:ad3be0349dc5	258	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
<>	134:ad3be0349dc5	259
<>	134:ad3be0349dc5	260	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	134:ad3be0349dc5	261	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
<>	134:ad3be0349dc5	262
<>	134:ad3be0349dc5	263	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
<>	134:ad3be0349dc5	264
<>	134:ad3be0349dc5	265	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<>	134:ad3be0349dc5	266	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
<>	134:ad3be0349dc5	267
<>	134:ad3be0349dc5	268	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
<>	134:ad3be0349dc5	269
<>	134:ad3be0349dc5	270	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	134:ad3be0349dc5	271	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
<>	134:ad3be0349dc5	272
<>	134:ad3be0349dc5	273	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
<>	134:ad3be0349dc5	274
<>	134:ad3be0349dc5	275	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	134:ad3be0349dc5	276	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
<>	134:ad3be0349dc5	277
<>	134:ad3be0349dc5	278	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
<>	134:ad3be0349dc5	279	} LL_TIM_OC_InitTypeDef;
<>	134:ad3be0349dc5	280
<>	134:ad3be0349dc5	281	/**
<>	134:ad3be0349dc5	282	* @brief TIM Input Capture configuration structure definition.
<>	134:ad3be0349dc5	283	*/
<>	134:ad3be0349dc5	284
<>	134:ad3be0349dc5	285	typedef struct
<>	134:ad3be0349dc5	286	{
<>	134:ad3be0349dc5	287
<>	134:ad3be0349dc5	288	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	134:ad3be0349dc5	289	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	134:ad3be0349dc5	290
<>	134:ad3be0349dc5	291	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	134:ad3be0349dc5	292
<>	134:ad3be0349dc5	293	uint32_t ICActiveInput; /*!< Specifies the input.
<>	134:ad3be0349dc5	294	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	134:ad3be0349dc5	295
<>	134:ad3be0349dc5	296	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	134:ad3be0349dc5	297
<>	134:ad3be0349dc5	298	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<>	134:ad3be0349dc5	299	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	134:ad3be0349dc5	300
<>	134:ad3be0349dc5	301	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	134:ad3be0349dc5	302
<>	134:ad3be0349dc5	303	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	134:ad3be0349dc5	304	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	134:ad3be0349dc5	305
<>	134:ad3be0349dc5	306	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	134:ad3be0349dc5	307	} LL_TIM_IC_InitTypeDef;
<>	134:ad3be0349dc5	308
<>	134:ad3be0349dc5	309
<>	134:ad3be0349dc5	310	/**
<>	134:ad3be0349dc5	311	* @brief TIM Encoder interface configuration structure definition.
<>	134:ad3be0349dc5	312	*/
<>	134:ad3be0349dc5	313	typedef struct
<>	134:ad3be0349dc5	314	{
<>	134:ad3be0349dc5	315	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
<>	134:ad3be0349dc5	316	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
<>	134:ad3be0349dc5	317
<>	134:ad3be0349dc5	318	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
<>	134:ad3be0349dc5	319
<>	134:ad3be0349dc5	320	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
<>	134:ad3be0349dc5	321	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	134:ad3be0349dc5	322
<>	134:ad3be0349dc5	323	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	134:ad3be0349dc5	324
<>	134:ad3be0349dc5	325	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
<>	134:ad3be0349dc5	326	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	134:ad3be0349dc5	327
<>	134:ad3be0349dc5	328	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	134:ad3be0349dc5	329
<>	134:ad3be0349dc5	330	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
<>	134:ad3be0349dc5	331	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	134:ad3be0349dc5	332
<>	134:ad3be0349dc5	333	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	134:ad3be0349dc5	334
<>	134:ad3be0349dc5	335	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
<>	134:ad3be0349dc5	336	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	134:ad3be0349dc5	337
<>	134:ad3be0349dc5	338	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	134:ad3be0349dc5	339
<>	134:ad3be0349dc5	340	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
<>	134:ad3be0349dc5	341	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	134:ad3be0349dc5	342
<>	134:ad3be0349dc5	343	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	134:ad3be0349dc5	344
<>	134:ad3be0349dc5	345	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
<>	134:ad3be0349dc5	346	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	134:ad3be0349dc5	347
<>	134:ad3be0349dc5	348	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	134:ad3be0349dc5	349
<>	134:ad3be0349dc5	350	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
<>	134:ad3be0349dc5	351	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	134:ad3be0349dc5	352
<>	134:ad3be0349dc5	353	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	134:ad3be0349dc5	354
<>	134:ad3be0349dc5	355	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
<>	134:ad3be0349dc5	356	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	134:ad3be0349dc5	357
<>	134:ad3be0349dc5	358	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	134:ad3be0349dc5	359
<>	134:ad3be0349dc5	360	} LL_TIM_ENCODER_InitTypeDef;
<>	134:ad3be0349dc5	361
<>	134:ad3be0349dc5	362	/**
<>	134:ad3be0349dc5	363	* @brief TIM Hall sensor interface configuration structure definition.
<>	134:ad3be0349dc5	364	*/
<>	134:ad3be0349dc5	365	typedef struct
<>	134:ad3be0349dc5	366	{
<>	134:ad3be0349dc5	367
<>	134:ad3be0349dc5	368	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
<>	134:ad3be0349dc5	369	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	134:ad3be0349dc5	370
<>	134:ad3be0349dc5	371	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	134:ad3be0349dc5	372
<>	134:ad3be0349dc5	373	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
<>	134:ad3be0349dc5	374	Prescaler must be set to get a maximum counter period longer than the
<>	134:ad3be0349dc5	375	time interval between 2 consecutive changes on the Hall inputs.
<>	134:ad3be0349dc5	376	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	134:ad3be0349dc5	377
<>	134:ad3be0349dc5	378	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	134:ad3be0349dc5	379
<>	134:ad3be0349dc5	380	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
<>	134:ad3be0349dc5	381	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	134:ad3be0349dc5	382
<>	134:ad3be0349dc5	383	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	134:ad3be0349dc5	384
<>	134:ad3be0349dc5	385	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
<>	134:ad3be0349dc5	386	A positive pulse (TRGO event) is generated with a programmable delay every time
<>	134:ad3be0349dc5	387	a change occurs on the Hall inputs.
<>	134:ad3be0349dc5	388	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
<>	134:ad3be0349dc5	389
<>	134:ad3be0349dc5	390	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
<>	134:ad3be0349dc5	391	} LL_TIM_HALLSENSOR_InitTypeDef;
<>	134:ad3be0349dc5	392
<>	134:ad3be0349dc5	393	/**
<>	134:ad3be0349dc5	394	* @}
<>	134:ad3be0349dc5	395	*/
<>	134:ad3be0349dc5	396	#endif /* USE_FULL_LL_DRIVER */
<>	134:ad3be0349dc5	397
<>	134:ad3be0349dc5	398	/* Exported constants --------------------------------------------------------*/
<>	134:ad3be0349dc5	399	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
<>	134:ad3be0349dc5	400	* @{
<>	134:ad3be0349dc5	401	*/
<>	134:ad3be0349dc5	402
<>	134:ad3be0349dc5	403	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
<>	134:ad3be0349dc5	404	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
<>	134:ad3be0349dc5	405	* @{
<>	134:ad3be0349dc5	406	*/
<>	134:ad3be0349dc5	407	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
<>	134:ad3be0349dc5	408	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
<>	134:ad3be0349dc5	409	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
<>	134:ad3be0349dc5	410	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
<>	134:ad3be0349dc5	411	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
<>	134:ad3be0349dc5	412	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
<>	134:ad3be0349dc5	413	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
<>	134:ad3be0349dc5	414	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
<>	134:ad3be0349dc5	415	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
<>	134:ad3be0349dc5	416	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
<>	134:ad3be0349dc5	417	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
<>	134:ad3be0349dc5	418	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
<>	134:ad3be0349dc5	419	/**
<>	134:ad3be0349dc5	420	* @}
<>	134:ad3be0349dc5	421	*/
<>	134:ad3be0349dc5	422
<>	134:ad3be0349dc5	423	/** @defgroup TIM_LL_EC_IT IT Defines
<>	134:ad3be0349dc5	424	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
<>	134:ad3be0349dc5	425	* @{
<>	134:ad3be0349dc5	426	*/
<>	134:ad3be0349dc5	427	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
<>	134:ad3be0349dc5	428	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
<>	134:ad3be0349dc5	429	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
<>	134:ad3be0349dc5	430	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
<>	134:ad3be0349dc5	431	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
<>	134:ad3be0349dc5	432	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
<>	134:ad3be0349dc5	433	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
<>	134:ad3be0349dc5	434	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
<>	134:ad3be0349dc5	435	/**
<>	134:ad3be0349dc5	436	* @}
<>	134:ad3be0349dc5	437	*/
<>	134:ad3be0349dc5	438
<>	134:ad3be0349dc5	439	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
<>	134:ad3be0349dc5	440	* @{
<>	134:ad3be0349dc5	441	*/
<>	134:ad3be0349dc5	442	#define LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U) /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
<>	134:ad3be0349dc5	443	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
<>	134:ad3be0349dc5	444	/**
<>	134:ad3be0349dc5	445	* @}
<>	134:ad3be0349dc5	446	*/
<>	134:ad3be0349dc5	447
<>	134:ad3be0349dc5	448	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
<>	134:ad3be0349dc5	449	* @{
<>	134:ad3be0349dc5	450	*/
<>	134:ad3be0349dc5	451	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
<>	134:ad3be0349dc5	452	#define LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U) /!< Counter stops counting at the next update event /
<>	134:ad3be0349dc5	453	/**
<>	134:ad3be0349dc5	454	* @}
<>	134:ad3be0349dc5	455	*/
<>	134:ad3be0349dc5	456
<>	134:ad3be0349dc5	457	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
<>	134:ad3be0349dc5	458	* @{
<>	134:ad3be0349dc5	459	*/
<>	134:ad3be0349dc5	460	#define LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U) /!<Counter used as upcounter /
<>	134:ad3be0349dc5	461	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
<>	134:ad3be0349dc5	462	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
<>	134:ad3be0349dc5	463	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
<>	134:ad3be0349dc5	464	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
<>	134:ad3be0349dc5	465	/**
<>	134:ad3be0349dc5	466	* @}
<>	134:ad3be0349dc5	467	*/
<>	134:ad3be0349dc5	468
<>	134:ad3be0349dc5	469	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
<>	134:ad3be0349dc5	470	* @{
<>	134:ad3be0349dc5	471	*/
<>	134:ad3be0349dc5	472	#define LL_TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U) /!< tDTS=tCK_INT /
<>	134:ad3be0349dc5	473	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
<>	134:ad3be0349dc5	474	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
<>	134:ad3be0349dc5	475	/**
<>	134:ad3be0349dc5	476	* @}
<>	134:ad3be0349dc5	477	*/
<>	134:ad3be0349dc5	478
<>	134:ad3be0349dc5	479	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
<>	134:ad3be0349dc5	480	* @{
<>	134:ad3be0349dc5	481	*/
<>	134:ad3be0349dc5	482	#define LL_TIM_COUNTERDIRECTION_UP ((uint32_t)0x00000000U) /!< Timer counter counts up /
<>	134:ad3be0349dc5	483	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
<>	134:ad3be0349dc5	484	/**
<>	134:ad3be0349dc5	485	* @}
<>	134:ad3be0349dc5	486	*/
<>	134:ad3be0349dc5	487
<>	134:ad3be0349dc5	488	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
<>	134:ad3be0349dc5	489	* @{
<>	134:ad3be0349dc5	490	*/
<>	134:ad3be0349dc5	491	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY ((uint32_t)0x00000000U) /!< Capture/compare control bits are updated by setting the COMG bit only /
<>	134:ad3be0349dc5	492	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
<>	134:ad3be0349dc5	493	/**
<>	134:ad3be0349dc5	494	* @}
<>	134:ad3be0349dc5	495	*/
<>	134:ad3be0349dc5	496
<>	134:ad3be0349dc5	497	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
<>	134:ad3be0349dc5	498	* @{
<>	134:ad3be0349dc5	499	*/
<>	134:ad3be0349dc5	500	#define LL_TIM_CCDMAREQUEST_CC ((uint32_t)0x00000000U) /!< CCx DMA request sent when CCx event occurs /
<>	134:ad3be0349dc5	501	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
<>	134:ad3be0349dc5	502	/**
<>	134:ad3be0349dc5	503	* @}
<>	134:ad3be0349dc5	504	*/
<>	134:ad3be0349dc5	505
<>	134:ad3be0349dc5	506	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
<>	134:ad3be0349dc5	507	* @{
<>	134:ad3be0349dc5	508	*/
<>	134:ad3be0349dc5	509	#define LL_TIM_LOCKLEVEL_OFF ((uint32_t)0x00000000U) /!< LOCK OFF - No bit is write protected /
<>	134:ad3be0349dc5	510	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
<>	134:ad3be0349dc5	511	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
<>	134:ad3be0349dc5	512	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
<>	134:ad3be0349dc5	513	/**
<>	134:ad3be0349dc5	514	* @}
<>	134:ad3be0349dc5	515	*/
<>	134:ad3be0349dc5	516
<>	134:ad3be0349dc5	517	/** @defgroup TIM_LL_EC_CHANNEL Channel
<>	134:ad3be0349dc5	518	* @{
<>	134:ad3be0349dc5	519	*/
<>	134:ad3be0349dc5	520	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
<>	134:ad3be0349dc5	521	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
<>	134:ad3be0349dc5	522	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
<>	134:ad3be0349dc5	523	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
<>	134:ad3be0349dc5	524	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
<>	134:ad3be0349dc5	525	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
<>	134:ad3be0349dc5	526	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
<>	134:ad3be0349dc5	527	/**
<>	134:ad3be0349dc5	528	* @}
<>	134:ad3be0349dc5	529	*/
<>	134:ad3be0349dc5	530
<>	134:ad3be0349dc5	531	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	532	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
<>	134:ad3be0349dc5	533	* @{
<>	134:ad3be0349dc5	534	*/
<>	134:ad3be0349dc5	535	#define LL_TIM_OCSTATE_DISABLE ((uint32_t)0x00000000U) /!< OCx is not active /
<>	134:ad3be0349dc5	536	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
<>	134:ad3be0349dc5	537	/**
<>	134:ad3be0349dc5	538	* @}
<>	134:ad3be0349dc5	539	*/
<>	134:ad3be0349dc5	540	#endif /* USE_FULL_LL_DRIVER */
<>	134:ad3be0349dc5	541
<>	134:ad3be0349dc5	542	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
<>	134:ad3be0349dc5	543	* @{
<>	134:ad3be0349dc5	544	*/
<>	134:ad3be0349dc5	545	#define LL_TIM_OCMODE_FROZEN ((uint32_t)0x00000000U) /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
<>	134:ad3be0349dc5	546	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
<>	134:ad3be0349dc5	547	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
<>	134:ad3be0349dc5	548	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
<>	134:ad3be0349dc5	549	#define LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) /!<OCyREF is forced low/
<>	134:ad3be0349dc5	550	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
<>	134:ad3be0349dc5	551	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
<>	134:ad3be0349dc5	552	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
<>	134:ad3be0349dc5	553	/**
<>	134:ad3be0349dc5	554	* @}
<>	134:ad3be0349dc5	555	*/
<>	134:ad3be0349dc5	556
<>	134:ad3be0349dc5	557	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
<>	134:ad3be0349dc5	558	* @{
<>	134:ad3be0349dc5	559	*/
<>	134:ad3be0349dc5	560	#define LL_TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U) /!< OCxactive high/
<>	134:ad3be0349dc5	561	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
<>	134:ad3be0349dc5	562	/**
<>	134:ad3be0349dc5	563	* @}
<>	134:ad3be0349dc5	564	*/
<>	134:ad3be0349dc5	565
<>	134:ad3be0349dc5	566	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
<>	134:ad3be0349dc5	567	* @{
<>	134:ad3be0349dc5	568	*/
<>	134:ad3be0349dc5	569	#define LL_TIM_OCIDLESTATE_LOW ((uint32_t)0x00000000U) /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
<>	134:ad3be0349dc5	570	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
<>	134:ad3be0349dc5	571	/**
<>	134:ad3be0349dc5	572	* @}
<>	134:ad3be0349dc5	573	*/
<>	134:ad3be0349dc5	574
<>	134:ad3be0349dc5	575
<>	134:ad3be0349dc5	576	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
<>	134:ad3be0349dc5	577	* @{
<>	134:ad3be0349dc5	578	*/
<>	134:ad3be0349dc5	579	#define LL_TIM_ACTIVEINPUT_DIRECTTI (uint32_t)(TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
<>	134:ad3be0349dc5	580	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (uint32_t)(TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
<>	134:ad3be0349dc5	581	#define LL_TIM_ACTIVEINPUT_TRC (uint32_t)(TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
<>	134:ad3be0349dc5	582	/**
<>	134:ad3be0349dc5	583	* @}
<>	134:ad3be0349dc5	584	*/
<>	134:ad3be0349dc5	585
<>	134:ad3be0349dc5	586	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
<>	134:ad3be0349dc5	587	* @{
<>	134:ad3be0349dc5	588	*/
<>	134:ad3be0349dc5	589	#define LL_TIM_ICPSC_DIV1 ((uint32_t)0x00000000U) /!< No prescaler, capture is done each time an edge is detected on the capture input /
<>	134:ad3be0349dc5	590	#define LL_TIM_ICPSC_DIV2 (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
<>	134:ad3be0349dc5	591	#define LL_TIM_ICPSC_DIV4 (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
<>	134:ad3be0349dc5	592	#define LL_TIM_ICPSC_DIV8 (uint32_t)(TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
<>	134:ad3be0349dc5	593	/**
<>	134:ad3be0349dc5	594	* @}
<>	134:ad3be0349dc5	595	*/
<>	134:ad3be0349dc5	596
<>	134:ad3be0349dc5	597	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
<>	134:ad3be0349dc5	598	* @{
<>	134:ad3be0349dc5	599	*/
<>	134:ad3be0349dc5	600	#define LL_TIM_IC_FILTER_FDIV1 ((uint32_t)0x00000000U) /!< No filter, sampling is done at fDTS /
<>	134:ad3be0349dc5	601	#define LL_TIM_IC_FILTER_FDIV1_N2 (uint32_t)(TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
<>	134:ad3be0349dc5	602	#define LL_TIM_IC_FILTER_FDIV1_N4 (uint32_t)(TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
<>	134:ad3be0349dc5	603	#define LL_TIM_IC_FILTER_FDIV1_N8 (uint32_t)((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
<>	134:ad3be0349dc5	604	#define LL_TIM_IC_FILTER_FDIV2_N6 (uint32_t)(TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
<>	134:ad3be0349dc5	605	#define LL_TIM_IC_FILTER_FDIV2_N8 (uint32_t)((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
<>	134:ad3be0349dc5	606	#define LL_TIM_IC_FILTER_FDIV4_N6 (uint32_t)((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
<>	134:ad3be0349dc5	607	#define LL_TIM_IC_FILTER_FDIV4_N8 (uint32_t)((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
<>	134:ad3be0349dc5	608	#define LL_TIM_IC_FILTER_FDIV8_N6 (uint32_t)(TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
<>	134:ad3be0349dc5	609	#define LL_TIM_IC_FILTER_FDIV8_N8 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
<>	134:ad3be0349dc5	610	#define LL_TIM_IC_FILTER_FDIV16_N5 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
<>	134:ad3be0349dc5	611	#define LL_TIM_IC_FILTER_FDIV16_N6 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
<>	134:ad3be0349dc5	612	#define LL_TIM_IC_FILTER_FDIV16_N8 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
<>	134:ad3be0349dc5	613	#define LL_TIM_IC_FILTER_FDIV32_N5 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
<>	134:ad3be0349dc5	614	#define LL_TIM_IC_FILTER_FDIV32_N6 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
<>	134:ad3be0349dc5	615	#define LL_TIM_IC_FILTER_FDIV32_N8 (uint32_t)(TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
<>	134:ad3be0349dc5	616	/**
<>	134:ad3be0349dc5	617	* @}
<>	134:ad3be0349dc5	618	*/
<>	134:ad3be0349dc5	619
<>	134:ad3be0349dc5	620	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
<>	134:ad3be0349dc5	621	* @{
<>	134:ad3be0349dc5	622	*/
<>	134:ad3be0349dc5	623	#define LL_TIM_IC_POLARITY_RISING ((uint32_t)0x00000000U) /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
<>	134:ad3be0349dc5	624	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
<>	134:ad3be0349dc5	625	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
<>	134:ad3be0349dc5	626	/**
<>	134:ad3be0349dc5	627	* @}
<>	134:ad3be0349dc5	628	*/
<>	134:ad3be0349dc5	629
<>	134:ad3be0349dc5	630	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
<>	134:ad3be0349dc5	631	* @{
<>	134:ad3be0349dc5	632	*/
<>	134:ad3be0349dc5	633	#define LL_TIM_CLOCKSOURCE_INTERNAL ((uint32_t)0x00000000U) /!< The timer is clocked by the internal clock provided from the RCC /
<>	134:ad3be0349dc5	634	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0 ) /!< Counter counts at each rising or falling edge on a selected inpu t/
<>	134:ad3be0349dc5	635	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
<>	134:ad3be0349dc5	636	/**
<>	134:ad3be0349dc5	637	* @}
<>	134:ad3be0349dc5	638	*/
<>	134:ad3be0349dc5	639
<>	134:ad3be0349dc5	640	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
<>	134:ad3be0349dc5	641	* @{
<>	134:ad3be0349dc5	642	*/
<>	134:ad3be0349dc5	643	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
<>	134:ad3be0349dc5	644	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
<>	134:ad3be0349dc5	645	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
<>	134:ad3be0349dc5	646	/**
<>	134:ad3be0349dc5	647	* @}
<>	134:ad3be0349dc5	648	*/
<>	134:ad3be0349dc5	649
<>	134:ad3be0349dc5	650	/** @defgroup TIM_LL_EC_TRGO Trigger Output
<>	134:ad3be0349dc5	651	* @{
<>	134:ad3be0349dc5	652	*/
<>	134:ad3be0349dc5	653	#define LL_TIM_TRGO_RESET ((uint32_t)0x00000000U) /!< UG bit from the TIMx_EGR register is used as trigger output /
<>	134:ad3be0349dc5	654	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
<>	134:ad3be0349dc5	655	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
<>	134:ad3be0349dc5	656	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
<>	134:ad3be0349dc5	657	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
<>	134:ad3be0349dc5	658	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
<>	134:ad3be0349dc5	659	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
<>	134:ad3be0349dc5	660	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
<>	134:ad3be0349dc5	661	/**
<>	134:ad3be0349dc5	662	* @}
<>	134:ad3be0349dc5	663	*/
<>	134:ad3be0349dc5	664
<>	134:ad3be0349dc5	665
<>	134:ad3be0349dc5	666	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
<>	134:ad3be0349dc5	667	* @{
<>	134:ad3be0349dc5	668	*/
<>	134:ad3be0349dc5	669	#define LL_TIM_SLAVEMODE_DISABLED ((uint32_t)0x00000000U) /!< Slave mode disabled /
<>	134:ad3be0349dc5	670	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
<>	134:ad3be0349dc5	671	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
<>	134:ad3be0349dc5	672	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
<>	134:ad3be0349dc5	673	/**
<>	134:ad3be0349dc5	674	* @}
<>	134:ad3be0349dc5	675	*/
<>	134:ad3be0349dc5	676
<>	134:ad3be0349dc5	677	/** @defgroup TIM_LL_EC_TS Trigger Selection
<>	134:ad3be0349dc5	678	* @{
<>	134:ad3be0349dc5	679	*/
<>	134:ad3be0349dc5	680	#define LL_TIM_TS_ITR0 ((uint32_t)0x00000000U) /!< Internal Trigger 0 (ITR0) is used as trigger input /
<>	134:ad3be0349dc5	681	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
<>	134:ad3be0349dc5	682	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
<>	134:ad3be0349dc5	683	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
<>	134:ad3be0349dc5	684	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
<>	134:ad3be0349dc5	685	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
<>	134:ad3be0349dc5	686	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
<>	134:ad3be0349dc5	687	#define LL_TIM_TS_ETRF TIM_SMCR_TS /!< Filtered external Trigger (ETRF) is used as trigger input /
<>	134:ad3be0349dc5	688	/**
<>	134:ad3be0349dc5	689	* @}
<>	134:ad3be0349dc5	690	*/
<>	134:ad3be0349dc5	691
<>	134:ad3be0349dc5	692	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
<>	134:ad3be0349dc5	693	* @{
<>	134:ad3be0349dc5	694	*/
<>	134:ad3be0349dc5	695	#define LL_TIM_ETR_POLARITY_NONINVERTED ((uint32_t)0x00000000U) /!< ETR is non-inverted, active at high level or rising edge /
<>	134:ad3be0349dc5	696	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
<>	134:ad3be0349dc5	697	/**
<>	134:ad3be0349dc5	698	* @}
<>	134:ad3be0349dc5	699	*/
<>	134:ad3be0349dc5	700
<>	134:ad3be0349dc5	701	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
<>	134:ad3be0349dc5	702	* @{
<>	134:ad3be0349dc5	703	*/
<>	134:ad3be0349dc5	704	#define LL_TIM_ETR_PRESCALER_DIV1 ((uint32_t)0x00000000U) /!< ETR prescaler OFF /
<>	134:ad3be0349dc5	705	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
<>	134:ad3be0349dc5	706	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
<>	134:ad3be0349dc5	707	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
<>	134:ad3be0349dc5	708	/**
<>	134:ad3be0349dc5	709	* @}
<>	134:ad3be0349dc5	710	*/
<>	134:ad3be0349dc5	711
<>	134:ad3be0349dc5	712	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
<>	134:ad3be0349dc5	713	* @{
<>	134:ad3be0349dc5	714	*/
<>	134:ad3be0349dc5	715	#define LL_TIM_ETR_FILTER_FDIV1 ((uint32_t)0x00000000U) /!< No filter, sampling is done at fDTS /
<>	134:ad3be0349dc5	716	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
<>	134:ad3be0349dc5	717	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
<>	134:ad3be0349dc5	718	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
<>	134:ad3be0349dc5	719	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
<>	134:ad3be0349dc5	720	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
<>	134:ad3be0349dc5	721	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 ) /!< fSAMPLING=fDTS/4, N=6 /
<>	134:ad3be0349dc5	722	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
<>	134:ad3be0349dc5	723	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
<>	134:ad3be0349dc5	724	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
<>	134:ad3be0349dc5	725	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 ) /!< fSAMPLING=fDTS/16, N=6 /
<>	134:ad3be0349dc5	726	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
<>	134:ad3be0349dc5	727	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 ) /!< fSAMPLING=fDTS/16, N=5 /
<>	134:ad3be0349dc5	728	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
<>	134:ad3be0349dc5	729	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
<>	134:ad3be0349dc5	730	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
<>	134:ad3be0349dc5	731	/**
<>	134:ad3be0349dc5	732	* @}
<>	134:ad3be0349dc5	733	*/
<>	134:ad3be0349dc5	734
<>	134:ad3be0349dc5	735
<>	134:ad3be0349dc5	736	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
<>	134:ad3be0349dc5	737	* @{
<>	134:ad3be0349dc5	738	*/
<>	134:ad3be0349dc5	739	#define LL_TIM_BREAK_POLARITY_LOW ((uint32_t)0x00000000U) /!< Break input BRK is active low /
<>	134:ad3be0349dc5	740	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
<>	134:ad3be0349dc5	741	/**
<>	134:ad3be0349dc5	742	* @}
<>	134:ad3be0349dc5	743	*/
<>	134:ad3be0349dc5	744
<>	134:ad3be0349dc5	745
<>	134:ad3be0349dc5	746
<>	134:ad3be0349dc5	747
<>	134:ad3be0349dc5	748	/** @defgroup TIM_LL_EC_OSSI OSSI
<>	134:ad3be0349dc5	749	* @{
<>	134:ad3be0349dc5	750	*/
<>	134:ad3be0349dc5	751	#define LL_TIM_OSSI_DISABLE ((uint32_t)0x00000000U) /!< When inactive, OCx/OCxN outputs are disabled /
<>	134:ad3be0349dc5	752	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
<>	134:ad3be0349dc5	753	/**
<>	134:ad3be0349dc5	754	* @}
<>	134:ad3be0349dc5	755	*/
<>	134:ad3be0349dc5	756
<>	134:ad3be0349dc5	757	/** @defgroup TIM_LL_EC_OSSR OSSR
<>	134:ad3be0349dc5	758	* @{
<>	134:ad3be0349dc5	759	*/
<>	134:ad3be0349dc5	760	#define LL_TIM_OSSR_DISABLE ((uint32_t)0x00000000U) /!< When inactive, OCx/OCxN outputs are disabled /
<>	134:ad3be0349dc5	761	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
<>	134:ad3be0349dc5	762	/**
<>	134:ad3be0349dc5	763	* @}
<>	134:ad3be0349dc5	764	*/
<>	134:ad3be0349dc5	765
<>	134:ad3be0349dc5	766
<>	134:ad3be0349dc5	767	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
<>	134:ad3be0349dc5	768	* @{
<>	134:ad3be0349dc5	769	*/
<>	134:ad3be0349dc5	770	#define LL_TIM_DMABURST_BASEADDR_CR1 ((uint32_t)0x00000000U) /!< TIMx_CR1 register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	771	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	772	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	773	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	774	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	775	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	776	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	777	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	778	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	779	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	780	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	781	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	782	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	783	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	784	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	785	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	786	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	787	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
<>	134:ad3be0349dc5	788
<>	134:ad3be0349dc5	789
<>	134:ad3be0349dc5	790	/**
<>	134:ad3be0349dc5	791	* @}
<>	134:ad3be0349dc5	792	*/
<>	134:ad3be0349dc5	793
<>	134:ad3be0349dc5	794	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
<>	134:ad3be0349dc5	795	* @{
<>	134:ad3be0349dc5	796	*/
<>	134:ad3be0349dc5	797	#define LL_TIM_DMABURST_LENGTH_1TRANSFER ((uint32_t)0x00000000U) /!< Transfer is done to 1 register starting from the DMA burst base address /
<>	134:ad3be0349dc5	798	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	799	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	800	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	801	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	802	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	803	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	804	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	805	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	806	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	807	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	808	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	809	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	810	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	811	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	812	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	813	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	814	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
<>	134:ad3be0349dc5	815	/**
<>	134:ad3be0349dc5	816	* @}
<>	134:ad3be0349dc5	817	*/
<>	134:ad3be0349dc5	818
<>	134:ad3be0349dc5	819
<>	134:ad3be0349dc5	820	#define LL_TIM_TIM14_TI1_RMP_GPIO ((uint32_t)0x00000000U \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to Ored GPIO /
<>	134:ad3be0349dc5	821	#define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to RTC clock /
<>	134:ad3be0349dc5	822	#define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to HSE/32 clock /
<>	134:ad3be0349dc5	823	#define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 \| TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to MCO /
<>	134:ad3be0349dc5	824
<>	134:ad3be0349dc5	825
<>	134:ad3be0349dc5	826	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
<>	134:ad3be0349dc5	827	* @{
<>	134:ad3be0349dc5	828	*/
<>	134:ad3be0349dc5	829	#define LL_TIM_OCREF_CLR_INT_OCREF_CLR ((uint32_t)0x00000000U ) /!< OCREF_CLR_INT is connected to the OCREF_CLR input /
<>	134:ad3be0349dc5	830	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
<>	134:ad3be0349dc5	831	/**
<>	134:ad3be0349dc5	832	* @}
<>	134:ad3be0349dc5	833	*/
<>	134:ad3be0349dc5	834
<>	134:ad3be0349dc5	835
<>	134:ad3be0349dc5	836	/**
<>	134:ad3be0349dc5	837	* @}
<>	134:ad3be0349dc5	838	*/
<>	134:ad3be0349dc5	839
<>	134:ad3be0349dc5	840	/* Exported macro ------------------------------------------------------------*/
<>	134:ad3be0349dc5	841	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
<>	134:ad3be0349dc5	842	* @{
<>	134:ad3be0349dc5	843	*/
<>	134:ad3be0349dc5	844
<>	134:ad3be0349dc5	845	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
<>	134:ad3be0349dc5	846	* @{
<>	134:ad3be0349dc5	847	*/
<>	134:ad3be0349dc5	848	/**
<>	134:ad3be0349dc5	849	* @brief Write a value in TIM register.
<>	134:ad3be0349dc5	850	* @param __INSTANCE__ TIM Instance
<>	134:ad3be0349dc5	851	* @param __REG__ Register to be written
<>	134:ad3be0349dc5	852	* @param __VALUE__ Value to be written in the register
<>	134:ad3be0349dc5	853	* @retval None
<>	134:ad3be0349dc5	854	*/
<>	134:ad3be0349dc5	855	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	134:ad3be0349dc5	856
<>	134:ad3be0349dc5	857	/**
<>	134:ad3be0349dc5	858	* @brief Read a value in TIM register.
<>	134:ad3be0349dc5	859	* @param __INSTANCE__ TIM Instance
<>	134:ad3be0349dc5	860	* @param __REG__ Register to be read
<>	134:ad3be0349dc5	861	* @retval Register value
<>	134:ad3be0349dc5	862	*/
<>	134:ad3be0349dc5	863	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	134:ad3be0349dc5	864	/**
<>	134:ad3be0349dc5	865	* @}
<>	134:ad3be0349dc5	866	*/
<>	134:ad3be0349dc5	867
<>	134:ad3be0349dc5	868	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
<>	134:ad3be0349dc5	869	* @{
<>	134:ad3be0349dc5	870	*/
<>	134:ad3be0349dc5	871
<>	134:ad3be0349dc5	872	/**
<>	134:ad3be0349dc5	873	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
<>	134:ad3be0349dc5	874	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
<>	134:ad3be0349dc5	875	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	134:ad3be0349dc5	876	* @param __CKD__ This parameter can be one of the following values:
<>	134:ad3be0349dc5	877	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	134:ad3be0349dc5	878	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	134:ad3be0349dc5	879	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	134:ad3be0349dc5	880	* @param __DT__ deadtime duration (in ns)
<>	134:ad3be0349dc5	881	* @retval DTG[0:7]
<>	134:ad3be0349dc5	882	*/
<>	134:ad3be0349dc5	883	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
<>	134:ad3be0349dc5	884	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
<>	134:ad3be0349dc5	885	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
<>	134:ad3be0349dc5	886	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
<>	134:ad3be0349dc5	887	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
<>	134:ad3be0349dc5	888	0U)
<>	134:ad3be0349dc5	889
<>	134:ad3be0349dc5	890	/**
<>	134:ad3be0349dc5	891	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
<>	134:ad3be0349dc5	892	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
<>	134:ad3be0349dc5	893	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	134:ad3be0349dc5	894	* @param __CNTCLK__ counter clock frequency (in Hz)
<>	134:ad3be0349dc5	895	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
<>	134:ad3be0349dc5	896	*/
<>	134:ad3be0349dc5	897	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
<>	134:ad3be0349dc5	898	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
<>	134:ad3be0349dc5	899
<>	134:ad3be0349dc5	900	/**
<>	134:ad3be0349dc5	901	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
<>	134:ad3be0349dc5	902	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
<>	134:ad3be0349dc5	903	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	134:ad3be0349dc5	904	* @param __PSC__ prescaler
<>	134:ad3be0349dc5	905	* @param __FREQ__ output signal frequency (in Hz)
<>	134:ad3be0349dc5	906	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<>	134:ad3be0349dc5	907	*/
<>	134:ad3be0349dc5	908	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
<>	134:ad3be0349dc5	909	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
<>	134:ad3be0349dc5	910
<>	134:ad3be0349dc5	911	/**
<>	134:ad3be0349dc5	912	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
<>	134:ad3be0349dc5	913	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
<>	134:ad3be0349dc5	914	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	134:ad3be0349dc5	915	* @param __PSC__ prescaler
<>	134:ad3be0349dc5	916	* @param __DELAY__ timer output compare active/inactive delay (in us)
<>	134:ad3be0349dc5	917	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
<>	134:ad3be0349dc5	918	*/
<>	134:ad3be0349dc5	919	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
<>	134:ad3be0349dc5	920	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
<>	134:ad3be0349dc5	921	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
<>	134:ad3be0349dc5	922
<>	134:ad3be0349dc5	923	/**
<>	134:ad3be0349dc5	924	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
<>	134:ad3be0349dc5	925	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
<>	134:ad3be0349dc5	926	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	134:ad3be0349dc5	927	* @param __PSC__ prescaler
<>	134:ad3be0349dc5	928	* @param __DELAY__ timer output compare active/inactive delay (in us)
<>	134:ad3be0349dc5	929	* @param __PULSE__ pulse duration (in us)
<>	134:ad3be0349dc5	930	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<>	134:ad3be0349dc5	931	*/
<>	134:ad3be0349dc5	932	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
<>	134:ad3be0349dc5	933	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
<>	134:ad3be0349dc5	934	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
<>	134:ad3be0349dc5	935
<>	134:ad3be0349dc5	936	/**
<>	134:ad3be0349dc5	937	* @brief HELPER macro retrieving the ratio of the input capture prescaler
<>	134:ad3be0349dc5	938	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
<>	134:ad3be0349dc5	939	* @param __ICPSC__ This parameter can be one of the following values:
<>	134:ad3be0349dc5	940	* @arg @ref LL_TIM_ICPSC_DIV1
<>	134:ad3be0349dc5	941	* @arg @ref LL_TIM_ICPSC_DIV2
<>	134:ad3be0349dc5	942	* @arg @ref LL_TIM_ICPSC_DIV4
<>	134:ad3be0349dc5	943	* @arg @ref LL_TIM_ICPSC_DIV8
<>	134:ad3be0349dc5	944	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
<>	134:ad3be0349dc5	945	*/
<>	134:ad3be0349dc5	946	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
<>	134:ad3be0349dc5	947	((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
<>	134:ad3be0349dc5	948
<>	134:ad3be0349dc5	949
<>	134:ad3be0349dc5	950	/**
<>	134:ad3be0349dc5	951	* @}
<>	134:ad3be0349dc5	952	*/
<>	134:ad3be0349dc5	953
<>	134:ad3be0349dc5	954
<>	134:ad3be0349dc5	955	/**
<>	134:ad3be0349dc5	956	* @}
<>	134:ad3be0349dc5	957	*/
<>	134:ad3be0349dc5	958
<>	134:ad3be0349dc5	959	/* Exported functions --------------------------------------------------------*/
<>	134:ad3be0349dc5	960	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
<>	134:ad3be0349dc5	961	* @{
<>	134:ad3be0349dc5	962	*/
<>	134:ad3be0349dc5	963
<>	134:ad3be0349dc5	964	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
<>	134:ad3be0349dc5	965	* @{
<>	134:ad3be0349dc5	966	*/
<>	134:ad3be0349dc5	967	/**
<>	134:ad3be0349dc5	968	* @brief Enable timer counter.
<>	134:ad3be0349dc5	969	* @rmtoll CR1 CEN LL_TIM_EnableCounter
<>	134:ad3be0349dc5	970	* @param TIMx Timer instance
<>	134:ad3be0349dc5	971	* @retval None
<>	134:ad3be0349dc5	972	*/
<>	134:ad3be0349dc5	973	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	974	{
<>	134:ad3be0349dc5	975	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
<>	134:ad3be0349dc5	976	}
<>	134:ad3be0349dc5	977
<>	134:ad3be0349dc5	978	/**
<>	134:ad3be0349dc5	979	* @brief Disable timer counter.
<>	134:ad3be0349dc5	980	* @rmtoll CR1 CEN LL_TIM_DisableCounter
<>	134:ad3be0349dc5	981	* @param TIMx Timer instance
<>	134:ad3be0349dc5	982	* @retval None
<>	134:ad3be0349dc5	983	*/
<>	134:ad3be0349dc5	984	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	985	{
<>	134:ad3be0349dc5	986	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
<>	134:ad3be0349dc5	987	}
<>	134:ad3be0349dc5	988
<>	134:ad3be0349dc5	989	/**
<>	134:ad3be0349dc5	990	* @brief Indicates whether the timer counter is enabled.
<>	134:ad3be0349dc5	991	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
<>	134:ad3be0349dc5	992	* @param TIMx Timer instance
<>	134:ad3be0349dc5	993	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	994	*/
<>	134:ad3be0349dc5	995	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	996	{
<>	134:ad3be0349dc5	997	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
<>	134:ad3be0349dc5	998	}
<>	134:ad3be0349dc5	999
<>	134:ad3be0349dc5	1000	/**
<>	134:ad3be0349dc5	1001	* @brief Enable update event generation.
<>	134:ad3be0349dc5	1002	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
<>	134:ad3be0349dc5	1003	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1004	* @retval None
<>	134:ad3be0349dc5	1005	*/
<>	134:ad3be0349dc5	1006	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1007	{
<>	134:ad3be0349dc5	1008	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
<>	134:ad3be0349dc5	1009	}
<>	134:ad3be0349dc5	1010
<>	134:ad3be0349dc5	1011	/**
<>	134:ad3be0349dc5	1012	* @brief Disable update event generation.
<>	134:ad3be0349dc5	1013	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
<>	134:ad3be0349dc5	1014	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1015	* @retval None
<>	134:ad3be0349dc5	1016	*/
<>	134:ad3be0349dc5	1017	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1018	{
<>	134:ad3be0349dc5	1019	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
<>	134:ad3be0349dc5	1020	}
<>	134:ad3be0349dc5	1021
<>	134:ad3be0349dc5	1022	/**
<>	134:ad3be0349dc5	1023	* @brief Indicates whether update event generation is enabled.
<>	134:ad3be0349dc5	1024	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
<>	134:ad3be0349dc5	1025	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1026	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1027	*/
<>	134:ad3be0349dc5	1028	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1029	{
<>	134:ad3be0349dc5	1030	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
<>	134:ad3be0349dc5	1031	}
<>	134:ad3be0349dc5	1032
<>	134:ad3be0349dc5	1033	/**
<>	134:ad3be0349dc5	1034	* @brief Set update event source
<>	134:ad3be0349dc5	1035	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
<>	134:ad3be0349dc5	1036	* generate an update interrupt or DMA request if enabled:
<>	134:ad3be0349dc5	1037	* - Counter overflow/underflow
<>	134:ad3be0349dc5	1038	* - Setting the UG bit
<>	134:ad3be0349dc5	1039	* - Update generation through the slave mode controller
<>	134:ad3be0349dc5	1040	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
<>	134:ad3be0349dc5	1041	* overflow/underflow generates an update interrupt or DMA request if enabled.
<>	134:ad3be0349dc5	1042	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
<>	134:ad3be0349dc5	1043	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1044	* @param UpdateSource This parameter can be one of the following values:
<>	134:ad3be0349dc5	1045	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<>	134:ad3be0349dc5	1046	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<>	134:ad3be0349dc5	1047	* @retval None
<>	134:ad3be0349dc5	1048	*/
<>	134:ad3be0349dc5	1049	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
<>	134:ad3be0349dc5	1050	{
<>	134:ad3be0349dc5	1051	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
<>	134:ad3be0349dc5	1052	}
<>	134:ad3be0349dc5	1053
<>	134:ad3be0349dc5	1054	/**
<>	134:ad3be0349dc5	1055	* @brief Get actual event update source
<>	134:ad3be0349dc5	1056	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
<>	134:ad3be0349dc5	1057	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1058	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1059	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<>	134:ad3be0349dc5	1060	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<>	134:ad3be0349dc5	1061	*/
<>	134:ad3be0349dc5	1062	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1063	{
<>	134:ad3be0349dc5	1064	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
<>	134:ad3be0349dc5	1065	}
<>	134:ad3be0349dc5	1066
<>	134:ad3be0349dc5	1067	/**
<>	134:ad3be0349dc5	1068	* @brief Set one pulse mode (one shot v.s. repetitive).
<>	134:ad3be0349dc5	1069	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
<>	134:ad3be0349dc5	1070	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1071	* @param OnePulseMode This parameter can be one of the following values:
<>	134:ad3be0349dc5	1072	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<>	134:ad3be0349dc5	1073	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<>	134:ad3be0349dc5	1074	* @retval None
<>	134:ad3be0349dc5	1075	*/
<>	134:ad3be0349dc5	1076	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
<>	134:ad3be0349dc5	1077	{
<>	134:ad3be0349dc5	1078	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
<>	134:ad3be0349dc5	1079	}
<>	134:ad3be0349dc5	1080
<>	134:ad3be0349dc5	1081	/**
<>	134:ad3be0349dc5	1082	* @brief Get actual one pulse mode.
<>	134:ad3be0349dc5	1083	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
<>	134:ad3be0349dc5	1084	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1085	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1086	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<>	134:ad3be0349dc5	1087	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<>	134:ad3be0349dc5	1088	*/
<>	134:ad3be0349dc5	1089	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1090	{
<>	134:ad3be0349dc5	1091	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
<>	134:ad3be0349dc5	1092	}
<>	134:ad3be0349dc5	1093
<>	134:ad3be0349dc5	1094	/**
<>	134:ad3be0349dc5	1095	* @brief Set the timer counter counting mode.
<>	134:ad3be0349dc5	1096	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<>	134:ad3be0349dc5	1097	* check whether or not the counter mode selection feature is supported
<>	134:ad3be0349dc5	1098	* by a timer instance.
<>	134:ad3be0349dc5	1099	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
<>	134:ad3be0349dc5	1100	* CR1 CMS LL_TIM_SetCounterMode
<>	134:ad3be0349dc5	1101	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1102	* @param CounterMode This parameter can be one of the following values:
<>	134:ad3be0349dc5	1103	* @arg @ref LL_TIM_COUNTERMODE_UP
<>	134:ad3be0349dc5	1104	* @arg @ref LL_TIM_COUNTERMODE_DOWN
<>	134:ad3be0349dc5	1105	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<>	134:ad3be0349dc5	1106	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<>	134:ad3be0349dc5	1107	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<>	134:ad3be0349dc5	1108	* @retval None
<>	134:ad3be0349dc5	1109	*/
<>	134:ad3be0349dc5	1110	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
<>	134:ad3be0349dc5	1111	{
<>	134:ad3be0349dc5	1112	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
<>	134:ad3be0349dc5	1113	}
<>	134:ad3be0349dc5	1114
<>	134:ad3be0349dc5	1115	/**
<>	134:ad3be0349dc5	1116	* @brief Get actual counter mode.
<>	134:ad3be0349dc5	1117	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<>	134:ad3be0349dc5	1118	* check whether or not the counter mode selection feature is supported
<>	134:ad3be0349dc5	1119	* by a timer instance.
<>	134:ad3be0349dc5	1120	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
<>	134:ad3be0349dc5	1121	* CR1 CMS LL_TIM_GetCounterMode
<>	134:ad3be0349dc5	1122	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1123	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1124	* @arg @ref LL_TIM_COUNTERMODE_UP
<>	134:ad3be0349dc5	1125	* @arg @ref LL_TIM_COUNTERMODE_DOWN
<>	134:ad3be0349dc5	1126	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<>	134:ad3be0349dc5	1127	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<>	134:ad3be0349dc5	1128	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<>	134:ad3be0349dc5	1129	*/
<>	134:ad3be0349dc5	1130	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1131	{
<>	134:ad3be0349dc5	1132	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
<>	134:ad3be0349dc5	1133	}
<>	134:ad3be0349dc5	1134
<>	134:ad3be0349dc5	1135	/**
<>	134:ad3be0349dc5	1136	* @brief Enable auto-reload (ARR) preload.
<>	134:ad3be0349dc5	1137	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
<>	134:ad3be0349dc5	1138	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1139	* @retval None
<>	134:ad3be0349dc5	1140	*/
<>	134:ad3be0349dc5	1141	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1142	{
<>	134:ad3be0349dc5	1143	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
<>	134:ad3be0349dc5	1144	}
<>	134:ad3be0349dc5	1145
<>	134:ad3be0349dc5	1146	/**
<>	134:ad3be0349dc5	1147	* @brief Disable auto-reload (ARR) preload.
<>	134:ad3be0349dc5	1148	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
<>	134:ad3be0349dc5	1149	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1150	* @retval None
<>	134:ad3be0349dc5	1151	*/
<>	134:ad3be0349dc5	1152	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1153	{
<>	134:ad3be0349dc5	1154	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
<>	134:ad3be0349dc5	1155	}
<>	134:ad3be0349dc5	1156
<>	134:ad3be0349dc5	1157	/**
<>	134:ad3be0349dc5	1158	* @brief Indicates whether auto-reload (ARR) preload is enabled.
<>	134:ad3be0349dc5	1159	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
<>	134:ad3be0349dc5	1160	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1161	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1162	*/
<>	134:ad3be0349dc5	1163	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1164	{
<>	134:ad3be0349dc5	1165	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
<>	134:ad3be0349dc5	1166	}
<>	134:ad3be0349dc5	1167
<>	134:ad3be0349dc5	1168	/**
<>	134:ad3be0349dc5	1169	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<>	134:ad3be0349dc5	1170	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1171	* whether or not the clock division feature is supported by the timer
<>	134:ad3be0349dc5	1172	* instance.
<>	134:ad3be0349dc5	1173	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
<>	134:ad3be0349dc5	1174	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1175	* @param ClockDivision This parameter can be one of the following values:
<>	134:ad3be0349dc5	1176	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	134:ad3be0349dc5	1177	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	134:ad3be0349dc5	1178	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	134:ad3be0349dc5	1179	* @retval None
<>	134:ad3be0349dc5	1180	*/
<>	134:ad3be0349dc5	1181	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
<>	134:ad3be0349dc5	1182	{
<>	134:ad3be0349dc5	1183	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
<>	134:ad3be0349dc5	1184	}
<>	134:ad3be0349dc5	1185
<>	134:ad3be0349dc5	1186	/**
<>	134:ad3be0349dc5	1187	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<>	134:ad3be0349dc5	1188	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1189	* whether or not the clock division feature is supported by the timer
<>	134:ad3be0349dc5	1190	* instance.
<>	134:ad3be0349dc5	1191	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
<>	134:ad3be0349dc5	1192	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1193	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1194	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	134:ad3be0349dc5	1195	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	134:ad3be0349dc5	1196	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	134:ad3be0349dc5	1197	*/
<>	134:ad3be0349dc5	1198	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1199	{
<>	134:ad3be0349dc5	1200	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
<>	134:ad3be0349dc5	1201	}
<>	134:ad3be0349dc5	1202
<>	134:ad3be0349dc5	1203	/**
<>	134:ad3be0349dc5	1204	* @brief Set the counter value.
<>	134:ad3be0349dc5	1205	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1206	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	1207	* @rmtoll CNT CNT LL_TIM_SetCounter
<>	134:ad3be0349dc5	1208	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1209	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<>	134:ad3be0349dc5	1210	* @retval None
<>	134:ad3be0349dc5	1211	*/
<>	134:ad3be0349dc5	1212	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
<>	134:ad3be0349dc5	1213	{
<>	134:ad3be0349dc5	1214	WRITE_REG(TIMx->CNT, Counter);
<>	134:ad3be0349dc5	1215	}
<>	134:ad3be0349dc5	1216
<>	134:ad3be0349dc5	1217	/**
<>	134:ad3be0349dc5	1218	* @brief Get the counter value.
<>	134:ad3be0349dc5	1219	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1220	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	1221	* @rmtoll CNT CNT LL_TIM_GetCounter
<>	134:ad3be0349dc5	1222	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1223	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<>	134:ad3be0349dc5	1224	*/
<>	134:ad3be0349dc5	1225	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1226	{
<>	134:ad3be0349dc5	1227	return (uint32_t)(READ_REG(TIMx->CNT));
<>	134:ad3be0349dc5	1228	}
<>	134:ad3be0349dc5	1229
<>	134:ad3be0349dc5	1230	/**
<>	134:ad3be0349dc5	1231	* @brief Get the current direction of the counter
<>	134:ad3be0349dc5	1232	* @rmtoll CR1 DIR LL_TIM_GetDirection
<>	134:ad3be0349dc5	1233	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1234	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1235	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
<>	134:ad3be0349dc5	1236	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
<>	134:ad3be0349dc5	1237	*/
<>	134:ad3be0349dc5	1238	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1239	{
<>	134:ad3be0349dc5	1240	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
<>	134:ad3be0349dc5	1241	}
<>	134:ad3be0349dc5	1242
<>	134:ad3be0349dc5	1243	/**
<>	134:ad3be0349dc5	1244	* @brief Set the prescaler value.
<>	134:ad3be0349dc5	1245	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
<>	134:ad3be0349dc5	1246	* @note The prescaler can be changed on the fly as this control register is buffered. The new
<>	134:ad3be0349dc5	1247	* prescaler ratio is taken into account at the next update event.
<>	134:ad3be0349dc5	1248	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
<>	134:ad3be0349dc5	1249	* @rmtoll PSC PSC LL_TIM_SetPrescaler
<>	134:ad3be0349dc5	1250	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1251	* @param Prescaler between Min_Data=0 and Max_Data=65535
<>	134:ad3be0349dc5	1252	* @retval None
<>	134:ad3be0349dc5	1253	*/
<>	134:ad3be0349dc5	1254	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
<>	134:ad3be0349dc5	1255	{
<>	134:ad3be0349dc5	1256	WRITE_REG(TIMx->PSC, Prescaler);
<>	134:ad3be0349dc5	1257	}
<>	134:ad3be0349dc5	1258
<>	134:ad3be0349dc5	1259	/**
<>	134:ad3be0349dc5	1260	* @brief Get the prescaler value.
<>	134:ad3be0349dc5	1261	* @rmtoll PSC PSC LL_TIM_GetPrescaler
<>	134:ad3be0349dc5	1262	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1263	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
<>	134:ad3be0349dc5	1264	*/
<>	134:ad3be0349dc5	1265	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1266	{
<>	134:ad3be0349dc5	1267	return (uint32_t)(READ_REG(TIMx->PSC));
<>	134:ad3be0349dc5	1268	}
<>	134:ad3be0349dc5	1269
<>	134:ad3be0349dc5	1270	/**
<>	134:ad3be0349dc5	1271	* @brief Set the auto-reload value.
<>	134:ad3be0349dc5	1272	* @note The counter is blocked while the auto-reload value is null.
<>	134:ad3be0349dc5	1273	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1274	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	1275	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
<>	134:ad3be0349dc5	1276	* @rmtoll ARR ARR LL_TIM_SetAutoReload
<>	134:ad3be0349dc5	1277	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1278	* @param AutoReload between Min_Data=0 and Max_Data=65535
<>	134:ad3be0349dc5	1279	* @retval None
<>	134:ad3be0349dc5	1280	*/
<>	134:ad3be0349dc5	1281	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
<>	134:ad3be0349dc5	1282	{
<>	134:ad3be0349dc5	1283	WRITE_REG(TIMx->ARR, AutoReload);
<>	134:ad3be0349dc5	1284	}
<>	134:ad3be0349dc5	1285
<>	134:ad3be0349dc5	1286	/**
<>	134:ad3be0349dc5	1287	* @brief Get the auto-reload value.
<>	134:ad3be0349dc5	1288	* @rmtoll ARR ARR LL_TIM_GetAutoReload
<>	134:ad3be0349dc5	1289	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1290	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	1291	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1292	* @retval Auto-reload value
<>	134:ad3be0349dc5	1293	*/
<>	134:ad3be0349dc5	1294	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1295	{
<>	134:ad3be0349dc5	1296	return (uint32_t)(READ_REG(TIMx->ARR));
<>	134:ad3be0349dc5	1297	}
<>	134:ad3be0349dc5	1298
<>	134:ad3be0349dc5	1299	/**
<>	134:ad3be0349dc5	1300	* @brief Set the repetition counter value.
<>	134:ad3be0349dc5	1301	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1302	* whether or not a timer instance supports a repetition counter.
<>	134:ad3be0349dc5	1303	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
<>	134:ad3be0349dc5	1304	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1305	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
<>	134:ad3be0349dc5	1306	* @retval None
<>	134:ad3be0349dc5	1307	*/
<>	134:ad3be0349dc5	1308	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
<>	134:ad3be0349dc5	1309	{
<>	134:ad3be0349dc5	1310	WRITE_REG(TIMx->RCR, RepetitionCounter);
<>	134:ad3be0349dc5	1311	}
<>	134:ad3be0349dc5	1312
<>	134:ad3be0349dc5	1313	/**
<>	134:ad3be0349dc5	1314	* @brief Get the repetition counter value.
<>	134:ad3be0349dc5	1315	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1316	* whether or not a timer instance supports a repetition counter.
<>	134:ad3be0349dc5	1317	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
<>	134:ad3be0349dc5	1318	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1319	* @retval Repetition counter value
<>	134:ad3be0349dc5	1320	*/
<>	134:ad3be0349dc5	1321	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1322	{
<>	134:ad3be0349dc5	1323	return (uint32_t)(READ_REG(TIMx->RCR));
<>	134:ad3be0349dc5	1324	}
<>	134:ad3be0349dc5	1325
<>	134:ad3be0349dc5	1326	/**
<>	134:ad3be0349dc5	1327	* @}
<>	134:ad3be0349dc5	1328	*/
<>	134:ad3be0349dc5	1329
<>	134:ad3be0349dc5	1330	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
<>	134:ad3be0349dc5	1331	* @{
<>	134:ad3be0349dc5	1332	*/
<>	134:ad3be0349dc5	1333	/**
<>	134:ad3be0349dc5	1334	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
<>	134:ad3be0349dc5	1335	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
<>	134:ad3be0349dc5	1336	* they are updated only when a commutation event (COM) occurs.
<>	134:ad3be0349dc5	1337	* @note Only on channels that have a complementary output.
<>	134:ad3be0349dc5	1338	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1339	* whether or not a timer instance is able to generate a commutation event.
<>	134:ad3be0349dc5	1340	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
<>	134:ad3be0349dc5	1341	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1342	* @retval None
<>	134:ad3be0349dc5	1343	*/
<>	134:ad3be0349dc5	1344	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1345	{
<>	134:ad3be0349dc5	1346	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
<>	134:ad3be0349dc5	1347	}
<>	134:ad3be0349dc5	1348
<>	134:ad3be0349dc5	1349	/**
<>	134:ad3be0349dc5	1350	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
<>	134:ad3be0349dc5	1351	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1352	* whether or not a timer instance is able to generate a commutation event.
<>	134:ad3be0349dc5	1353	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
<>	134:ad3be0349dc5	1354	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1355	* @retval None
<>	134:ad3be0349dc5	1356	*/
<>	134:ad3be0349dc5	1357	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1358	{
<>	134:ad3be0349dc5	1359	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
<>	134:ad3be0349dc5	1360	}
<>	134:ad3be0349dc5	1361
<>	134:ad3be0349dc5	1362	/**
<>	134:ad3be0349dc5	1363	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
<>	134:ad3be0349dc5	1364	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1365	* whether or not a timer instance is able to generate a commutation event.
<>	134:ad3be0349dc5	1366	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
<>	134:ad3be0349dc5	1367	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1368	* @param CCUpdateSource This parameter can be one of the following values:
<>	134:ad3be0349dc5	1369	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
<>	134:ad3be0349dc5	1370	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
<>	134:ad3be0349dc5	1371	* @retval None
<>	134:ad3be0349dc5	1372	*/
<>	134:ad3be0349dc5	1373	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
<>	134:ad3be0349dc5	1374	{
<>	134:ad3be0349dc5	1375	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
<>	134:ad3be0349dc5	1376	}
<>	134:ad3be0349dc5	1377
<>	134:ad3be0349dc5	1378	/**
<>	134:ad3be0349dc5	1379	* @brief Set the trigger of the capture/compare DMA request.
<>	134:ad3be0349dc5	1380	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
<>	134:ad3be0349dc5	1381	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1382	* @param DMAReqTrigger This parameter can be one of the following values:
<>	134:ad3be0349dc5	1383	* @arg @ref LL_TIM_CCDMAREQUEST_CC
<>	134:ad3be0349dc5	1384	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<>	134:ad3be0349dc5	1385	* @retval None
<>	134:ad3be0349dc5	1386	*/
<>	134:ad3be0349dc5	1387	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
<>	134:ad3be0349dc5	1388	{
<>	134:ad3be0349dc5	1389	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
<>	134:ad3be0349dc5	1390	}
<>	134:ad3be0349dc5	1391
<>	134:ad3be0349dc5	1392	/**
<>	134:ad3be0349dc5	1393	* @brief Get actual trigger of the capture/compare DMA request.
<>	134:ad3be0349dc5	1394	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
<>	134:ad3be0349dc5	1395	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1396	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1397	* @arg @ref LL_TIM_CCDMAREQUEST_CC
<>	134:ad3be0349dc5	1398	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<>	134:ad3be0349dc5	1399	*/
<>	134:ad3be0349dc5	1400	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	1401	{
<>	134:ad3be0349dc5	1402	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
<>	134:ad3be0349dc5	1403	}
<>	134:ad3be0349dc5	1404
<>	134:ad3be0349dc5	1405	/**
<>	134:ad3be0349dc5	1406	* @brief Set the lock level to freeze the
<>	134:ad3be0349dc5	1407	* configuration of several capture/compare parameters.
<>	134:ad3be0349dc5	1408	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	1409	* the lock mechanism is supported by a timer instance.
<>	134:ad3be0349dc5	1410	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
<>	134:ad3be0349dc5	1411	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1412	* @param LockLevel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1413	* @arg @ref LL_TIM_LOCKLEVEL_OFF
<>	134:ad3be0349dc5	1414	* @arg @ref LL_TIM_LOCKLEVEL_1
<>	134:ad3be0349dc5	1415	* @arg @ref LL_TIM_LOCKLEVEL_2
<>	134:ad3be0349dc5	1416	* @arg @ref LL_TIM_LOCKLEVEL_3
<>	134:ad3be0349dc5	1417	* @retval None
<>	134:ad3be0349dc5	1418	*/
<>	134:ad3be0349dc5	1419	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
<>	134:ad3be0349dc5	1420	{
<>	134:ad3be0349dc5	1421	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
<>	134:ad3be0349dc5	1422	}
<>	134:ad3be0349dc5	1423
<>	134:ad3be0349dc5	1424	/**
<>	134:ad3be0349dc5	1425	* @brief Enable capture/compare channels.
<>	134:ad3be0349dc5	1426	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
<>	134:ad3be0349dc5	1427	* CCER CC1NE LL_TIM_CC_EnableChannel\n
<>	134:ad3be0349dc5	1428	* CCER CC2E LL_TIM_CC_EnableChannel\n
<>	134:ad3be0349dc5	1429	* CCER CC2NE LL_TIM_CC_EnableChannel\n
<>	134:ad3be0349dc5	1430	* CCER CC3E LL_TIM_CC_EnableChannel\n
<>	134:ad3be0349dc5	1431	* CCER CC3NE LL_TIM_CC_EnableChannel\n
<>	134:ad3be0349dc5	1432	* CCER CC4E LL_TIM_CC_EnableChannel
<>	134:ad3be0349dc5	1433	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1434	* @param Channels This parameter can be a combination of the following values:
<>	134:ad3be0349dc5	1435	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1436	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	134:ad3be0349dc5	1437	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1438	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	134:ad3be0349dc5	1439	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1440	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	134:ad3be0349dc5	1441	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1442	* @retval None
<>	134:ad3be0349dc5	1443	*/
<>	134:ad3be0349dc5	1444	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	134:ad3be0349dc5	1445	{
<>	134:ad3be0349dc5	1446	SET_BIT(TIMx->CCER, Channels);
<>	134:ad3be0349dc5	1447	}
<>	134:ad3be0349dc5	1448
<>	134:ad3be0349dc5	1449	/**
<>	134:ad3be0349dc5	1450	* @brief Disable capture/compare channels.
<>	134:ad3be0349dc5	1451	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
<>	134:ad3be0349dc5	1452	* CCER CC1NE LL_TIM_CC_DisableChannel\n
<>	134:ad3be0349dc5	1453	* CCER CC2E LL_TIM_CC_DisableChannel\n
<>	134:ad3be0349dc5	1454	* CCER CC2NE LL_TIM_CC_DisableChannel\n
<>	134:ad3be0349dc5	1455	* CCER CC3E LL_TIM_CC_DisableChannel\n
<>	134:ad3be0349dc5	1456	* CCER CC3NE LL_TIM_CC_DisableChannel\n
<>	134:ad3be0349dc5	1457	* CCER CC4E LL_TIM_CC_DisableChannel
<>	134:ad3be0349dc5	1458	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1459	* @param Channels This parameter can be a combination of the following values:
<>	134:ad3be0349dc5	1460	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1461	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	134:ad3be0349dc5	1462	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1463	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	134:ad3be0349dc5	1464	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1465	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	134:ad3be0349dc5	1466	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1467	* @retval None
<>	134:ad3be0349dc5	1468	*/
<>	134:ad3be0349dc5	1469	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	134:ad3be0349dc5	1470	{
<>	134:ad3be0349dc5	1471	CLEAR_BIT(TIMx->CCER, Channels);
<>	134:ad3be0349dc5	1472	}
<>	134:ad3be0349dc5	1473
<>	134:ad3be0349dc5	1474	/**
<>	134:ad3be0349dc5	1475	* @brief Indicate whether channel(s) is(are) enabled.
<>	134:ad3be0349dc5	1476	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
<>	134:ad3be0349dc5	1477	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
<>	134:ad3be0349dc5	1478	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
<>	134:ad3be0349dc5	1479	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
<>	134:ad3be0349dc5	1480	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
<>	134:ad3be0349dc5	1481	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
<>	134:ad3be0349dc5	1482	* CCER CC4E LL_TIM_CC_IsEnabledChannel
<>	134:ad3be0349dc5	1483	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1484	* @param Channels This parameter can be a combination of the following values:
<>	134:ad3be0349dc5	1485	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1486	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	134:ad3be0349dc5	1487	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1488	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	134:ad3be0349dc5	1489	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1490	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	134:ad3be0349dc5	1491	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1492	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1493	*/
<>	134:ad3be0349dc5	1494	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	134:ad3be0349dc5	1495	{
<>	134:ad3be0349dc5	1496	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
<>	134:ad3be0349dc5	1497	}
<>	134:ad3be0349dc5	1498
<>	134:ad3be0349dc5	1499	/**
<>	134:ad3be0349dc5	1500	* @}
<>	134:ad3be0349dc5	1501	*/
<>	134:ad3be0349dc5	1502
<>	134:ad3be0349dc5	1503	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
<>	134:ad3be0349dc5	1504	* @{
<>	134:ad3be0349dc5	1505	*/
<>	134:ad3be0349dc5	1506	/**
<>	134:ad3be0349dc5	1507	* @brief Configure an output channel.
<>	134:ad3be0349dc5	1508	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
<>	134:ad3be0349dc5	1509	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
<>	134:ad3be0349dc5	1510	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
<>	134:ad3be0349dc5	1511	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
<>	134:ad3be0349dc5	1512	* CCER CC1P LL_TIM_OC_ConfigOutput\n
<>	134:ad3be0349dc5	1513	* CCER CC2P LL_TIM_OC_ConfigOutput\n
<>	134:ad3be0349dc5	1514	* CCER CC3P LL_TIM_OC_ConfigOutput\n
<>	134:ad3be0349dc5	1515	* CCER CC4P LL_TIM_OC_ConfigOutput\n
<>	134:ad3be0349dc5	1516	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
<>	134:ad3be0349dc5	1517	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
<>	134:ad3be0349dc5	1518	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
<>	134:ad3be0349dc5	1519	* CR2 OIS4 LL_TIM_OC_ConfigOutput
<>	134:ad3be0349dc5	1520	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1521	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1522	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1523	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1524	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1525	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1526	* @param Configuration This parameter must be a combination of all the following values:
<>	134:ad3be0349dc5	1527	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
<>	134:ad3be0349dc5	1528	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
<>	134:ad3be0349dc5	1529	* @retval None
<>	134:ad3be0349dc5	1530	*/
<>	134:ad3be0349dc5	1531	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
<>	134:ad3be0349dc5	1532	{
<>	134:ad3be0349dc5	1533	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1534	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	1535	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
<>	134:ad3be0349dc5	1536	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
<>	134:ad3be0349dc5	1537	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
<>	134:ad3be0349dc5	1538	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
<>	134:ad3be0349dc5	1539	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
<>	134:ad3be0349dc5	1540	}
<>	134:ad3be0349dc5	1541
<>	134:ad3be0349dc5	1542	/**
<>	134:ad3be0349dc5	1543	* @brief Define the behavior of the output reference signal OCxREF from which
<>	134:ad3be0349dc5	1544	* OCx and OCxN (when relevant) are derived.
<>	134:ad3be0349dc5	1545	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
<>	134:ad3be0349dc5	1546	* CCMR1 OC2M LL_TIM_OC_SetMode\n
<>	134:ad3be0349dc5	1547	* CCMR2 OC3M LL_TIM_OC_SetMode\n
<>	134:ad3be0349dc5	1548	* CCMR2 OC4M LL_TIM_OC_SetMode
<>	134:ad3be0349dc5	1549	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1550	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1551	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1552	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1553	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1554	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1555	* @param Mode This parameter can be one of the following values:
<>	134:ad3be0349dc5	1556	* @arg @ref LL_TIM_OCMODE_FROZEN
<>	134:ad3be0349dc5	1557	* @arg @ref LL_TIM_OCMODE_ACTIVE
<>	134:ad3be0349dc5	1558	* @arg @ref LL_TIM_OCMODE_INACTIVE
<>	134:ad3be0349dc5	1559	* @arg @ref LL_TIM_OCMODE_TOGGLE
<>	134:ad3be0349dc5	1560	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<>	134:ad3be0349dc5	1561	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<>	134:ad3be0349dc5	1562	* @arg @ref LL_TIM_OCMODE_PWM1
<>	134:ad3be0349dc5	1563	* @arg @ref LL_TIM_OCMODE_PWM2
<>	134:ad3be0349dc5	1564	* @retval None
<>	134:ad3be0349dc5	1565	*/
<>	134:ad3be0349dc5	1566	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
<>	134:ad3be0349dc5	1567	{
<>	134:ad3be0349dc5	1568	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1569	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	1570	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
<>	134:ad3be0349dc5	1571	}
<>	134:ad3be0349dc5	1572
<>	134:ad3be0349dc5	1573	/**
<>	134:ad3be0349dc5	1574	* @brief Get the output compare mode of an output channel.
<>	134:ad3be0349dc5	1575	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
<>	134:ad3be0349dc5	1576	* CCMR1 OC2M LL_TIM_OC_GetMode\n
<>	134:ad3be0349dc5	1577	* CCMR2 OC3M LL_TIM_OC_GetMode\n
<>	134:ad3be0349dc5	1578	* CCMR2 OC4M LL_TIM_OC_GetMode
<>	134:ad3be0349dc5	1579	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1580	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1581	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1582	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1583	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1584	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1585	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1586	* @arg @ref LL_TIM_OCMODE_FROZEN
<>	134:ad3be0349dc5	1587	* @arg @ref LL_TIM_OCMODE_ACTIVE
<>	134:ad3be0349dc5	1588	* @arg @ref LL_TIM_OCMODE_INACTIVE
<>	134:ad3be0349dc5	1589	* @arg @ref LL_TIM_OCMODE_TOGGLE
<>	134:ad3be0349dc5	1590	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<>	134:ad3be0349dc5	1591	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<>	134:ad3be0349dc5	1592	* @arg @ref LL_TIM_OCMODE_PWM1
<>	134:ad3be0349dc5	1593	* @arg @ref LL_TIM_OCMODE_PWM2
<>	134:ad3be0349dc5	1594	*/
<>	134:ad3be0349dc5	1595	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	1596	{
<>	134:ad3be0349dc5	1597	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1598	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	1599	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
<>	134:ad3be0349dc5	1600	}
<>	134:ad3be0349dc5	1601
<>	134:ad3be0349dc5	1602	/**
<>	134:ad3be0349dc5	1603	* @brief Set the polarity of an output channel.
<>	134:ad3be0349dc5	1604	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
<>	134:ad3be0349dc5	1605	* CCER CC1NP LL_TIM_OC_SetPolarity\n
<>	134:ad3be0349dc5	1606	* CCER CC2P LL_TIM_OC_SetPolarity\n
<>	134:ad3be0349dc5	1607	* CCER CC2NP LL_TIM_OC_SetPolarity\n
<>	134:ad3be0349dc5	1608	* CCER CC3P LL_TIM_OC_SetPolarity\n
<>	134:ad3be0349dc5	1609	* CCER CC3NP LL_TIM_OC_SetPolarity\n
<>	134:ad3be0349dc5	1610	* CCER CC4P LL_TIM_OC_SetPolarity
<>	134:ad3be0349dc5	1611	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1612	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1613	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1614	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	134:ad3be0349dc5	1615	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1616	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	134:ad3be0349dc5	1617	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1618	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	134:ad3be0349dc5	1619	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1620	* @param Polarity This parameter can be one of the following values:
<>	134:ad3be0349dc5	1621	* @arg @ref LL_TIM_OCPOLARITY_HIGH
<>	134:ad3be0349dc5	1622	* @arg @ref LL_TIM_OCPOLARITY_LOW
<>	134:ad3be0349dc5	1623	* @retval None
<>	134:ad3be0349dc5	1624	*/
<>	134:ad3be0349dc5	1625	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
<>	134:ad3be0349dc5	1626	{
<>	134:ad3be0349dc5	1627	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1628	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
<>	134:ad3be0349dc5	1629	}
<>	134:ad3be0349dc5	1630
<>	134:ad3be0349dc5	1631	/**
<>	134:ad3be0349dc5	1632	* @brief Get the polarity of an output channel.
<>	134:ad3be0349dc5	1633	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
<>	134:ad3be0349dc5	1634	* CCER CC1NP LL_TIM_OC_GetPolarity\n
<>	134:ad3be0349dc5	1635	* CCER CC2P LL_TIM_OC_GetPolarity\n
<>	134:ad3be0349dc5	1636	* CCER CC2NP LL_TIM_OC_GetPolarity\n
<>	134:ad3be0349dc5	1637	* CCER CC3P LL_TIM_OC_GetPolarity\n
<>	134:ad3be0349dc5	1638	* CCER CC3NP LL_TIM_OC_GetPolarity\n
<>	134:ad3be0349dc5	1639	* CCER CC4P LL_TIM_OC_GetPolarity
<>	134:ad3be0349dc5	1640	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1641	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1642	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1643	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	134:ad3be0349dc5	1644	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1645	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	134:ad3be0349dc5	1646	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1647	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	134:ad3be0349dc5	1648	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1649	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1650	* @arg @ref LL_TIM_OCPOLARITY_HIGH
<>	134:ad3be0349dc5	1651	* @arg @ref LL_TIM_OCPOLARITY_LOW
<>	134:ad3be0349dc5	1652	*/
<>	134:ad3be0349dc5	1653	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	1654	{
<>	134:ad3be0349dc5	1655	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1656	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
<>	134:ad3be0349dc5	1657	}
<>	134:ad3be0349dc5	1658
<>	134:ad3be0349dc5	1659	/**
<>	134:ad3be0349dc5	1660	* @brief Set the IDLE state of an output channel
<>	134:ad3be0349dc5	1661	* @note This function is significant only for the timer instances
<>	134:ad3be0349dc5	1662	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
<>	134:ad3be0349dc5	1663	* can be used to check whether or not a timer instance provides
<>	134:ad3be0349dc5	1664	* a break input.
<>	134:ad3be0349dc5	1665	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
<>	134:ad3be0349dc5	1666	* CR2 OIS1N LL_TIM_OC_SetIdleState\n
<>	134:ad3be0349dc5	1667	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
<>	134:ad3be0349dc5	1668	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
<>	134:ad3be0349dc5	1669	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
<>	134:ad3be0349dc5	1670	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
<>	134:ad3be0349dc5	1671	* CR2 OIS4 LL_TIM_OC_SetIdleState
<>	134:ad3be0349dc5	1672	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1673	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1674	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1675	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	134:ad3be0349dc5	1676	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1677	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	134:ad3be0349dc5	1678	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1679	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	134:ad3be0349dc5	1680	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1681	* @param IdleState This parameter can be one of the following values:
<>	134:ad3be0349dc5	1682	* @arg @ref LL_TIM_OCIDLESTATE_LOW
<>	134:ad3be0349dc5	1683	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
<>	134:ad3be0349dc5	1684	* @retval None
<>	134:ad3be0349dc5	1685	*/
<>	134:ad3be0349dc5	1686	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
<>	134:ad3be0349dc5	1687	{
<>	134:ad3be0349dc5	1688	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1689	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
<>	134:ad3be0349dc5	1690	}
<>	134:ad3be0349dc5	1691
<>	134:ad3be0349dc5	1692	/**
<>	134:ad3be0349dc5	1693	* @brief Get the IDLE state of an output channel
<>	134:ad3be0349dc5	1694	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
<>	134:ad3be0349dc5	1695	* CR2 OIS1N LL_TIM_OC_GetIdleState\n
<>	134:ad3be0349dc5	1696	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
<>	134:ad3be0349dc5	1697	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
<>	134:ad3be0349dc5	1698	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
<>	134:ad3be0349dc5	1699	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
<>	134:ad3be0349dc5	1700	* CR2 OIS4 LL_TIM_OC_GetIdleState
<>	134:ad3be0349dc5	1701	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1702	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1703	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1704	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	134:ad3be0349dc5	1705	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1706	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	134:ad3be0349dc5	1707	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1708	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	134:ad3be0349dc5	1709	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1710	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1711	* @arg @ref LL_TIM_OCIDLESTATE_LOW
<>	134:ad3be0349dc5	1712	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
<>	134:ad3be0349dc5	1713	*/
<>	134:ad3be0349dc5	1714	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	1715	{
<>	134:ad3be0349dc5	1716	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1717	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
<>	134:ad3be0349dc5	1718	}
<>	134:ad3be0349dc5	1719
<>	134:ad3be0349dc5	1720	/**
<>	134:ad3be0349dc5	1721	* @brief Enable fast mode for the output channel.
<>	134:ad3be0349dc5	1722	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
<>	134:ad3be0349dc5	1723	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
<>	134:ad3be0349dc5	1724	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
<>	134:ad3be0349dc5	1725	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
<>	134:ad3be0349dc5	1726	* CCMR2 OC4FE LL_TIM_OC_EnableFast
<>	134:ad3be0349dc5	1727	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1728	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1729	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1730	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1731	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1732	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1733	* @retval None
<>	134:ad3be0349dc5	1734	*/
<>	134:ad3be0349dc5	1735	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	1736	{
<>	134:ad3be0349dc5	1737	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1738	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	1739	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<>	134:ad3be0349dc5	1740
<>	134:ad3be0349dc5	1741	}
<>	134:ad3be0349dc5	1742
<>	134:ad3be0349dc5	1743	/**
<>	134:ad3be0349dc5	1744	* @brief Disable fast mode for the output channel.
<>	134:ad3be0349dc5	1745	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
<>	134:ad3be0349dc5	1746	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
<>	134:ad3be0349dc5	1747	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
<>	134:ad3be0349dc5	1748	* CCMR2 OC4FE LL_TIM_OC_DisableFast
<>	134:ad3be0349dc5	1749	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1750	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1751	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1752	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1753	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1754	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1755	* @retval None
<>	134:ad3be0349dc5	1756	*/
<>	134:ad3be0349dc5	1757	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	1758	{
<>	134:ad3be0349dc5	1759	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1760	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	1761	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<>	134:ad3be0349dc5	1762
<>	134:ad3be0349dc5	1763	}
<>	134:ad3be0349dc5	1764
<>	134:ad3be0349dc5	1765	/**
<>	134:ad3be0349dc5	1766	* @brief Indicates whether fast mode is enabled for the output channel.
<>	134:ad3be0349dc5	1767	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
<>	134:ad3be0349dc5	1768	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
<>	134:ad3be0349dc5	1769	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
<>	134:ad3be0349dc5	1770	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
<>	134:ad3be0349dc5	1771	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1772	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1773	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1774	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1775	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1776	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1777	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1778	*/
<>	134:ad3be0349dc5	1779	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	1780	{
<>	134:ad3be0349dc5	1781	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1782	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	1783	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
<>	134:ad3be0349dc5	1784	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	134:ad3be0349dc5	1785	}
<>	134:ad3be0349dc5	1786
<>	134:ad3be0349dc5	1787	/**
<>	134:ad3be0349dc5	1788	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
<>	134:ad3be0349dc5	1789	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
<>	134:ad3be0349dc5	1790	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
<>	134:ad3be0349dc5	1791	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
<>	134:ad3be0349dc5	1792	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
<>	134:ad3be0349dc5	1793	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1794	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1795	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1796	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1797	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1798	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1799	* @retval None
<>	134:ad3be0349dc5	1800	*/
<>	134:ad3be0349dc5	1801	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	1802	{
<>	134:ad3be0349dc5	1803	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1804	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	1805	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<>	134:ad3be0349dc5	1806	}
<>	134:ad3be0349dc5	1807
<>	134:ad3be0349dc5	1808	/**
<>	134:ad3be0349dc5	1809	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
<>	134:ad3be0349dc5	1810	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
<>	134:ad3be0349dc5	1811	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
<>	134:ad3be0349dc5	1812	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
<>	134:ad3be0349dc5	1813	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
<>	134:ad3be0349dc5	1814	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1815	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1816	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1817	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1818	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1819	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1820	* @retval None
<>	134:ad3be0349dc5	1821	*/
<>	134:ad3be0349dc5	1822	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	1823	{
<>	134:ad3be0349dc5	1824	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1825	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	1826	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<>	134:ad3be0349dc5	1827	}
<>	134:ad3be0349dc5	1828
<>	134:ad3be0349dc5	1829	/**
<>	134:ad3be0349dc5	1830	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
<>	134:ad3be0349dc5	1831	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
<>	134:ad3be0349dc5	1832	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
<>	134:ad3be0349dc5	1833	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
<>	134:ad3be0349dc5	1834	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
<>	134:ad3be0349dc5	1835	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1836	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1837	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1838	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1839	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1840	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1841	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1842	*/
<>	134:ad3be0349dc5	1843	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	1844	{
<>	134:ad3be0349dc5	1845	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1846	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	1847	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
<>	134:ad3be0349dc5	1848	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	134:ad3be0349dc5	1849	}
<>	134:ad3be0349dc5	1850
<>	134:ad3be0349dc5	1851	/**
<>	134:ad3be0349dc5	1852	* @brief Enable clearing the output channel on an external event.
<>	134:ad3be0349dc5	1853	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<>	134:ad3be0349dc5	1854	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	134:ad3be0349dc5	1855	* or not a timer instance can clear the OCxREF signal on an external event.
<>	134:ad3be0349dc5	1856	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
<>	134:ad3be0349dc5	1857	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
<>	134:ad3be0349dc5	1858	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
<>	134:ad3be0349dc5	1859	* CCMR2 OC4CE LL_TIM_OC_EnableClear
<>	134:ad3be0349dc5	1860	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1861	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1862	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1863	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1864	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1865	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1866	* @retval None
<>	134:ad3be0349dc5	1867	*/
<>	134:ad3be0349dc5	1868	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	1869	{
<>	134:ad3be0349dc5	1870	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1871	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	1872	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<>	134:ad3be0349dc5	1873	}
<>	134:ad3be0349dc5	1874
<>	134:ad3be0349dc5	1875	/**
<>	134:ad3be0349dc5	1876	* @brief Disable clearing the output channel on an external event.
<>	134:ad3be0349dc5	1877	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	134:ad3be0349dc5	1878	* or not a timer instance can clear the OCxREF signal on an external event.
<>	134:ad3be0349dc5	1879	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
<>	134:ad3be0349dc5	1880	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
<>	134:ad3be0349dc5	1881	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
<>	134:ad3be0349dc5	1882	* CCMR2 OC4CE LL_TIM_OC_DisableClear
<>	134:ad3be0349dc5	1883	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1884	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1885	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1886	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1887	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1888	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1889	* @retval None
<>	134:ad3be0349dc5	1890	*/
<>	134:ad3be0349dc5	1891	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	1892	{
<>	134:ad3be0349dc5	1893	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1894	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	1895	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<>	134:ad3be0349dc5	1896	}
<>	134:ad3be0349dc5	1897
<>	134:ad3be0349dc5	1898	/**
<>	134:ad3be0349dc5	1899	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
<>	134:ad3be0349dc5	1900	* @note This function enables clearing the output channel on an external event.
<>	134:ad3be0349dc5	1901	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<>	134:ad3be0349dc5	1902	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	134:ad3be0349dc5	1903	* or not a timer instance can clear the OCxREF signal on an external event.
<>	134:ad3be0349dc5	1904	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
<>	134:ad3be0349dc5	1905	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
<>	134:ad3be0349dc5	1906	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
<>	134:ad3be0349dc5	1907	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
<>	134:ad3be0349dc5	1908	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1909	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1910	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	1911	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	1912	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	1913	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	1914	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1915	*/
<>	134:ad3be0349dc5	1916	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	1917	{
<>	134:ad3be0349dc5	1918	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	1919	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	1920	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
<>	134:ad3be0349dc5	1921	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	134:ad3be0349dc5	1922	}
<>	134:ad3be0349dc5	1923
<>	134:ad3be0349dc5	1924	/**
<>	134:ad3be0349dc5	1925	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
<>	134:ad3be0349dc5	1926	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	1927	* dead-time insertion feature is supported by a timer instance.
<>	134:ad3be0349dc5	1928	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
<>	134:ad3be0349dc5	1929	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
<>	134:ad3be0349dc5	1930	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1931	* @param DeadTime between Min_Data=0 and Max_Data=255
<>	134:ad3be0349dc5	1932	* @retval None
<>	134:ad3be0349dc5	1933	*/
<>	134:ad3be0349dc5	1934	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
<>	134:ad3be0349dc5	1935	{
<>	134:ad3be0349dc5	1936	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
<>	134:ad3be0349dc5	1937	}
<>	134:ad3be0349dc5	1938
<>	134:ad3be0349dc5	1939	/**
<>	134:ad3be0349dc5	1940	* @brief Set compare value for output channel 1 (TIMx_CCR1).
<>	134:ad3be0349dc5	1941	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	134:ad3be0349dc5	1942	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1943	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	1944	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	1945	* output channel 1 is supported by a timer instance.
<>	134:ad3be0349dc5	1946	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
<>	134:ad3be0349dc5	1947	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1948	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	134:ad3be0349dc5	1949	* @retval None
<>	134:ad3be0349dc5	1950	*/
<>	134:ad3be0349dc5	1951	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	134:ad3be0349dc5	1952	{
<>	134:ad3be0349dc5	1953	WRITE_REG(TIMx->CCR1, CompareValue);
<>	134:ad3be0349dc5	1954	}
<>	134:ad3be0349dc5	1955
<>	134:ad3be0349dc5	1956	/**
<>	134:ad3be0349dc5	1957	* @brief Set compare value for output channel 2 (TIMx_CCR2).
<>	134:ad3be0349dc5	1958	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	134:ad3be0349dc5	1959	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1960	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	1961	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	1962	* output channel 2 is supported by a timer instance.
<>	134:ad3be0349dc5	1963	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
<>	134:ad3be0349dc5	1964	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1965	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	134:ad3be0349dc5	1966	* @retval None
<>	134:ad3be0349dc5	1967	*/
<>	134:ad3be0349dc5	1968	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	134:ad3be0349dc5	1969	{
<>	134:ad3be0349dc5	1970	WRITE_REG(TIMx->CCR2, CompareValue);
<>	134:ad3be0349dc5	1971	}
<>	134:ad3be0349dc5	1972
<>	134:ad3be0349dc5	1973	/**
<>	134:ad3be0349dc5	1974	* @brief Set compare value for output channel 3 (TIMx_CCR3).
<>	134:ad3be0349dc5	1975	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	134:ad3be0349dc5	1976	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1977	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	1978	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	1979	* output channel is supported by a timer instance.
<>	134:ad3be0349dc5	1980	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
<>	134:ad3be0349dc5	1981	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1982	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	134:ad3be0349dc5	1983	* @retval None
<>	134:ad3be0349dc5	1984	*/
<>	134:ad3be0349dc5	1985	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	134:ad3be0349dc5	1986	{
<>	134:ad3be0349dc5	1987	WRITE_REG(TIMx->CCR3, CompareValue);
<>	134:ad3be0349dc5	1988	}
<>	134:ad3be0349dc5	1989
<>	134:ad3be0349dc5	1990	/**
<>	134:ad3be0349dc5	1991	* @brief Set compare value for output channel 4 (TIMx_CCR4).
<>	134:ad3be0349dc5	1992	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	134:ad3be0349dc5	1993	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	1994	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	1995	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	1996	* output channel 4 is supported by a timer instance.
<>	134:ad3be0349dc5	1997	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
<>	134:ad3be0349dc5	1998	* @param TIMx Timer instance
<>	134:ad3be0349dc5	1999	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	134:ad3be0349dc5	2000	* @retval None
<>	134:ad3be0349dc5	2001	*/
<>	134:ad3be0349dc5	2002	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	134:ad3be0349dc5	2003	{
<>	134:ad3be0349dc5	2004	WRITE_REG(TIMx->CCR4, CompareValue);
<>	134:ad3be0349dc5	2005	}
<>	134:ad3be0349dc5	2006
<>	134:ad3be0349dc5	2007	/**
<>	134:ad3be0349dc5	2008	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
<>	134:ad3be0349dc5	2009	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	134:ad3be0349dc5	2010	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2011	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	2012	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2013	* output channel 1 is supported by a timer instance.
<>	134:ad3be0349dc5	2014	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
<>	134:ad3be0349dc5	2015	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2016	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	134:ad3be0349dc5	2017	*/
<>	134:ad3be0349dc5	2018	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2019	{
<>	134:ad3be0349dc5	2020	return (uint32_t)(READ_REG(TIMx->CCR1));
<>	134:ad3be0349dc5	2021	}
<>	134:ad3be0349dc5	2022
<>	134:ad3be0349dc5	2023	/**
<>	134:ad3be0349dc5	2024	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
<>	134:ad3be0349dc5	2025	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	134:ad3be0349dc5	2026	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2027	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	2028	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2029	* output channel 2 is supported by a timer instance.
<>	134:ad3be0349dc5	2030	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
<>	134:ad3be0349dc5	2031	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2032	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	134:ad3be0349dc5	2033	*/
<>	134:ad3be0349dc5	2034	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2035	{
<>	134:ad3be0349dc5	2036	return (uint32_t)(READ_REG(TIMx->CCR2));
<>	134:ad3be0349dc5	2037	}
<>	134:ad3be0349dc5	2038
<>	134:ad3be0349dc5	2039	/**
<>	134:ad3be0349dc5	2040	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
<>	134:ad3be0349dc5	2041	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	134:ad3be0349dc5	2042	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2043	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	2044	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2045	* output channel 3 is supported by a timer instance.
<>	134:ad3be0349dc5	2046	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
<>	134:ad3be0349dc5	2047	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2048	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	134:ad3be0349dc5	2049	*/
<>	134:ad3be0349dc5	2050	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2051	{
<>	134:ad3be0349dc5	2052	return (uint32_t)(READ_REG(TIMx->CCR3));
<>	134:ad3be0349dc5	2053	}
<>	134:ad3be0349dc5	2054
<>	134:ad3be0349dc5	2055	/**
<>	134:ad3be0349dc5	2056	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
<>	134:ad3be0349dc5	2057	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	134:ad3be0349dc5	2058	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2059	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	2060	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2061	* output channel 4 is supported by a timer instance.
<>	134:ad3be0349dc5	2062	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
<>	134:ad3be0349dc5	2063	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2064	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	134:ad3be0349dc5	2065	*/
<>	134:ad3be0349dc5	2066	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2067	{
<>	134:ad3be0349dc5	2068	return (uint32_t)(READ_REG(TIMx->CCR4));
<>	134:ad3be0349dc5	2069	}
<>	134:ad3be0349dc5	2070
<>	134:ad3be0349dc5	2071	/**
<>	134:ad3be0349dc5	2072	* @}
<>	134:ad3be0349dc5	2073	*/
<>	134:ad3be0349dc5	2074
<>	134:ad3be0349dc5	2075	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
<>	134:ad3be0349dc5	2076	* @{
<>	134:ad3be0349dc5	2077	*/
<>	134:ad3be0349dc5	2078	/**
<>	134:ad3be0349dc5	2079	* @brief Configure input channel.
<>	134:ad3be0349dc5	2080	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2081	* CCMR1 IC1PSC LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2082	* CCMR1 IC1F LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2083	* CCMR1 CC2S LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2084	* CCMR1 IC2PSC LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2085	* CCMR1 IC2F LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2086	* CCMR2 CC3S LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2087	* CCMR2 IC3PSC LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2088	* CCMR2 IC3F LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2089	* CCMR2 CC4S LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2090	* CCMR2 IC4PSC LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2091	* CCMR2 IC4F LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2092	* CCER CC1P LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2093	* CCER CC1NP LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2094	* CCER CC2P LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2095	* CCER CC2NP LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2096	* CCER CC3P LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2097	* CCER CC3NP LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2098	* CCER CC4P LL_TIM_IC_Config\n
<>	134:ad3be0349dc5	2099	* CCER CC4NP LL_TIM_IC_Config
<>	134:ad3be0349dc5	2100	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2101	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	2102	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	2103	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	2104	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	2105	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	2106	* @param Configuration This parameter must be a combination of all the following values:
<>	134:ad3be0349dc5	2107	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
<>	134:ad3be0349dc5	2108	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
<>	134:ad3be0349dc5	2109	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	134:ad3be0349dc5	2110	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	134:ad3be0349dc5	2111	* @retval None
<>	134:ad3be0349dc5	2112	*/
<>	134:ad3be0349dc5	2113	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
<>	134:ad3be0349dc5	2114	{
<>	134:ad3be0349dc5	2115	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	2116	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	2117	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
<>	134:ad3be0349dc5	2118	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
<>	134:ad3be0349dc5	2119	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
<>	134:ad3be0349dc5	2120	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
<>	134:ad3be0349dc5	2121	}
<>	134:ad3be0349dc5	2122
<>	134:ad3be0349dc5	2123	/**
<>	134:ad3be0349dc5	2124	* @brief Set the active input.
<>	134:ad3be0349dc5	2125	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
<>	134:ad3be0349dc5	2126	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
<>	134:ad3be0349dc5	2127	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
<>	134:ad3be0349dc5	2128	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
<>	134:ad3be0349dc5	2129	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2130	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	2131	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	2132	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	2133	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	2134	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	2135	* @param ICActiveInput This parameter can be one of the following values:
<>	134:ad3be0349dc5	2136	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<>	134:ad3be0349dc5	2137	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<>	134:ad3be0349dc5	2138	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
<>	134:ad3be0349dc5	2139	* @retval None
<>	134:ad3be0349dc5	2140	*/
<>	134:ad3be0349dc5	2141	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
<>	134:ad3be0349dc5	2142	{
<>	134:ad3be0349dc5	2143	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	2144	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	2145	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	134:ad3be0349dc5	2146	}
<>	134:ad3be0349dc5	2147
<>	134:ad3be0349dc5	2148	/**
<>	134:ad3be0349dc5	2149	* @brief Get the current active input.
<>	134:ad3be0349dc5	2150	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
<>	134:ad3be0349dc5	2151	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
<>	134:ad3be0349dc5	2152	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
<>	134:ad3be0349dc5	2153	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
<>	134:ad3be0349dc5	2154	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2155	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	2156	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	2157	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	2158	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	2159	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	2160	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	2161	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<>	134:ad3be0349dc5	2162	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<>	134:ad3be0349dc5	2163	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
<>	134:ad3be0349dc5	2164	*/
<>	134:ad3be0349dc5	2165	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	2166	{
<>	134:ad3be0349dc5	2167	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	2168	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	2169	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	134:ad3be0349dc5	2170	}
<>	134:ad3be0349dc5	2171
<>	134:ad3be0349dc5	2172	/**
<>	134:ad3be0349dc5	2173	* @brief Set the prescaler of input channel.
<>	134:ad3be0349dc5	2174	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
<>	134:ad3be0349dc5	2175	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
<>	134:ad3be0349dc5	2176	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
<>	134:ad3be0349dc5	2177	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
<>	134:ad3be0349dc5	2178	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2179	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	2180	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	2181	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	2182	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	2183	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	2184	* @param ICPrescaler This parameter can be one of the following values:
<>	134:ad3be0349dc5	2185	* @arg @ref LL_TIM_ICPSC_DIV1
<>	134:ad3be0349dc5	2186	* @arg @ref LL_TIM_ICPSC_DIV2
<>	134:ad3be0349dc5	2187	* @arg @ref LL_TIM_ICPSC_DIV4
<>	134:ad3be0349dc5	2188	* @arg @ref LL_TIM_ICPSC_DIV8
<>	134:ad3be0349dc5	2189	* @retval None
<>	134:ad3be0349dc5	2190	*/
<>	134:ad3be0349dc5	2191	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
<>	134:ad3be0349dc5	2192	{
<>	134:ad3be0349dc5	2193	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	2194	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	2195	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	134:ad3be0349dc5	2196	}
<>	134:ad3be0349dc5	2197
<>	134:ad3be0349dc5	2198	/**
<>	134:ad3be0349dc5	2199	* @brief Get the current prescaler value acting on an input channel.
<>	134:ad3be0349dc5	2200	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
<>	134:ad3be0349dc5	2201	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
<>	134:ad3be0349dc5	2202	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
<>	134:ad3be0349dc5	2203	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
<>	134:ad3be0349dc5	2204	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2205	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	2206	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	2207	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	2208	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	2209	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	2210	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	2211	* @arg @ref LL_TIM_ICPSC_DIV1
<>	134:ad3be0349dc5	2212	* @arg @ref LL_TIM_ICPSC_DIV2
<>	134:ad3be0349dc5	2213	* @arg @ref LL_TIM_ICPSC_DIV4
<>	134:ad3be0349dc5	2214	* @arg @ref LL_TIM_ICPSC_DIV8
<>	134:ad3be0349dc5	2215	*/
<>	134:ad3be0349dc5	2216	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	2217	{
<>	134:ad3be0349dc5	2218	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	2219	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	2220	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	134:ad3be0349dc5	2221	}
<>	134:ad3be0349dc5	2222
<>	134:ad3be0349dc5	2223	/**
<>	134:ad3be0349dc5	2224	* @brief Set the input filter duration.
<>	134:ad3be0349dc5	2225	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
<>	134:ad3be0349dc5	2226	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
<>	134:ad3be0349dc5	2227	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
<>	134:ad3be0349dc5	2228	* CCMR2 IC4F LL_TIM_IC_SetFilter
<>	134:ad3be0349dc5	2229	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2230	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	2231	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	2232	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	2233	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	2234	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	2235	* @param ICFilter This parameter can be one of the following values:
<>	134:ad3be0349dc5	2236	* @arg @ref LL_TIM_IC_FILTER_FDIV1
<>	134:ad3be0349dc5	2237	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<>	134:ad3be0349dc5	2238	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<>	134:ad3be0349dc5	2239	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<>	134:ad3be0349dc5	2240	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<>	134:ad3be0349dc5	2241	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<>	134:ad3be0349dc5	2242	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<>	134:ad3be0349dc5	2243	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<>	134:ad3be0349dc5	2244	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<>	134:ad3be0349dc5	2245	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<>	134:ad3be0349dc5	2246	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<>	134:ad3be0349dc5	2247	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<>	134:ad3be0349dc5	2248	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<>	134:ad3be0349dc5	2249	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<>	134:ad3be0349dc5	2250	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<>	134:ad3be0349dc5	2251	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	134:ad3be0349dc5	2252	* @retval None
<>	134:ad3be0349dc5	2253	*/
<>	134:ad3be0349dc5	2254	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
<>	134:ad3be0349dc5	2255	{
<>	134:ad3be0349dc5	2256	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	2257	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	2258	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	134:ad3be0349dc5	2259	}
<>	134:ad3be0349dc5	2260
<>	134:ad3be0349dc5	2261	/**
<>	134:ad3be0349dc5	2262	* @brief Get the input filter duration.
<>	134:ad3be0349dc5	2263	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
<>	134:ad3be0349dc5	2264	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
<>	134:ad3be0349dc5	2265	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
<>	134:ad3be0349dc5	2266	* CCMR2 IC4F LL_TIM_IC_GetFilter
<>	134:ad3be0349dc5	2267	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2268	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	2269	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	2270	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	2271	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	2272	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	2273	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	2274	* @arg @ref LL_TIM_IC_FILTER_FDIV1
<>	134:ad3be0349dc5	2275	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<>	134:ad3be0349dc5	2276	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<>	134:ad3be0349dc5	2277	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<>	134:ad3be0349dc5	2278	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<>	134:ad3be0349dc5	2279	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<>	134:ad3be0349dc5	2280	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<>	134:ad3be0349dc5	2281	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<>	134:ad3be0349dc5	2282	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<>	134:ad3be0349dc5	2283	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<>	134:ad3be0349dc5	2284	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<>	134:ad3be0349dc5	2285	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<>	134:ad3be0349dc5	2286	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<>	134:ad3be0349dc5	2287	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<>	134:ad3be0349dc5	2288	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<>	134:ad3be0349dc5	2289	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	134:ad3be0349dc5	2290	*/
<>	134:ad3be0349dc5	2291	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	2292	{
<>	134:ad3be0349dc5	2293	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	2294	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	134:ad3be0349dc5	2295	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	134:ad3be0349dc5	2296	}
<>	134:ad3be0349dc5	2297
<>	134:ad3be0349dc5	2298	/**
<>	134:ad3be0349dc5	2299	* @brief Set the input channel polarity.
<>	134:ad3be0349dc5	2300	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
<>	134:ad3be0349dc5	2301	* CCER CC1NP LL_TIM_IC_SetPolarity\n
<>	134:ad3be0349dc5	2302	* CCER CC2P LL_TIM_IC_SetPolarity\n
<>	134:ad3be0349dc5	2303	* CCER CC2NP LL_TIM_IC_SetPolarity\n
<>	134:ad3be0349dc5	2304	* CCER CC3P LL_TIM_IC_SetPolarity\n
<>	134:ad3be0349dc5	2305	* CCER CC3NP LL_TIM_IC_SetPolarity\n
<>	134:ad3be0349dc5	2306	* CCER CC4P LL_TIM_IC_SetPolarity\n
<>	134:ad3be0349dc5	2307	* CCER CC4NP LL_TIM_IC_SetPolarity
<>	134:ad3be0349dc5	2308	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2309	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	2310	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	2311	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	2312	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	2313	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	2314	* @param ICPolarity This parameter can be one of the following values:
<>	134:ad3be0349dc5	2315	* @arg @ref LL_TIM_IC_POLARITY_RISING
<>	134:ad3be0349dc5	2316	* @arg @ref LL_TIM_IC_POLARITY_FALLING
<>	134:ad3be0349dc5	2317	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	134:ad3be0349dc5	2318	* @retval None
<>	134:ad3be0349dc5	2319	*/
<>	134:ad3be0349dc5	2320	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
<>	134:ad3be0349dc5	2321	{
<>	134:ad3be0349dc5	2322	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	2323	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
<>	134:ad3be0349dc5	2324	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
<>	134:ad3be0349dc5	2325	}
<>	134:ad3be0349dc5	2326
<>	134:ad3be0349dc5	2327	/**
<>	134:ad3be0349dc5	2328	* @brief Get the current input channel polarity.
<>	134:ad3be0349dc5	2329	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
<>	134:ad3be0349dc5	2330	* CCER CC1NP LL_TIM_IC_GetPolarity\n
<>	134:ad3be0349dc5	2331	* CCER CC2P LL_TIM_IC_GetPolarity\n
<>	134:ad3be0349dc5	2332	* CCER CC2NP LL_TIM_IC_GetPolarity\n
<>	134:ad3be0349dc5	2333	* CCER CC3P LL_TIM_IC_GetPolarity\n
<>	134:ad3be0349dc5	2334	* CCER CC3NP LL_TIM_IC_GetPolarity\n
<>	134:ad3be0349dc5	2335	* CCER CC4P LL_TIM_IC_GetPolarity\n
<>	134:ad3be0349dc5	2336	* CCER CC4NP LL_TIM_IC_GetPolarity
<>	134:ad3be0349dc5	2337	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2338	* @param Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	2339	* @arg @ref LL_TIM_CHANNEL_CH1
<>	134:ad3be0349dc5	2340	* @arg @ref LL_TIM_CHANNEL_CH2
<>	134:ad3be0349dc5	2341	* @arg @ref LL_TIM_CHANNEL_CH3
<>	134:ad3be0349dc5	2342	* @arg @ref LL_TIM_CHANNEL_CH4
<>	134:ad3be0349dc5	2343	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	2344	* @arg @ref LL_TIM_IC_POLARITY_RISING
<>	134:ad3be0349dc5	2345	* @arg @ref LL_TIM_IC_POLARITY_FALLING
<>	134:ad3be0349dc5	2346	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	134:ad3be0349dc5	2347	*/
<>	134:ad3be0349dc5	2348	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
<>	134:ad3be0349dc5	2349	{
<>	134:ad3be0349dc5	2350	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	134:ad3be0349dc5	2351	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
<>	134:ad3be0349dc5	2352	SHIFT_TAB_CCxP[iChannel]);
<>	134:ad3be0349dc5	2353	}
<>	134:ad3be0349dc5	2354
<>	134:ad3be0349dc5	2355	/**
<>	134:ad3be0349dc5	2356	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
<>	134:ad3be0349dc5	2357	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2358	* a timer instance provides an XOR input.
<>	134:ad3be0349dc5	2359	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
<>	134:ad3be0349dc5	2360	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2361	* @retval None
<>	134:ad3be0349dc5	2362	*/
<>	134:ad3be0349dc5	2363	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2364	{
<>	134:ad3be0349dc5	2365	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
<>	134:ad3be0349dc5	2366	}
<>	134:ad3be0349dc5	2367
<>	134:ad3be0349dc5	2368	/**
<>	134:ad3be0349dc5	2369	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
<>	134:ad3be0349dc5	2370	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2371	* a timer instance provides an XOR input.
<>	134:ad3be0349dc5	2372	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
<>	134:ad3be0349dc5	2373	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2374	* @retval None
<>	134:ad3be0349dc5	2375	*/
<>	134:ad3be0349dc5	2376	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2377	{
<>	134:ad3be0349dc5	2378	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
<>	134:ad3be0349dc5	2379	}
<>	134:ad3be0349dc5	2380
<>	134:ad3be0349dc5	2381	/**
<>	134:ad3be0349dc5	2382	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
<>	134:ad3be0349dc5	2383	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2384	* a timer instance provides an XOR input.
<>	134:ad3be0349dc5	2385	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
<>	134:ad3be0349dc5	2386	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2387	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2388	*/
<>	134:ad3be0349dc5	2389	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2390	{
<>	134:ad3be0349dc5	2391	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
<>	134:ad3be0349dc5	2392	}
<>	134:ad3be0349dc5	2393
<>	134:ad3be0349dc5	2394	/**
<>	134:ad3be0349dc5	2395	* @brief Get captured value for input channel 1.
<>	134:ad3be0349dc5	2396	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	134:ad3be0349dc5	2397	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2398	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	2399	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2400	* input channel 1 is supported by a timer instance.
<>	134:ad3be0349dc5	2401	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
<>	134:ad3be0349dc5	2402	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2403	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	134:ad3be0349dc5	2404	*/
<>	134:ad3be0349dc5	2405	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2406	{
<>	134:ad3be0349dc5	2407	return (uint32_t)(READ_REG(TIMx->CCR1));
<>	134:ad3be0349dc5	2408	}
<>	134:ad3be0349dc5	2409
<>	134:ad3be0349dc5	2410	/**
<>	134:ad3be0349dc5	2411	* @brief Get captured value for input channel 2.
<>	134:ad3be0349dc5	2412	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	134:ad3be0349dc5	2413	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2414	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	2415	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2416	* input channel 2 is supported by a timer instance.
<>	134:ad3be0349dc5	2417	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
<>	134:ad3be0349dc5	2418	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2419	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	134:ad3be0349dc5	2420	*/
<>	134:ad3be0349dc5	2421	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2422	{
<>	134:ad3be0349dc5	2423	return (uint32_t)(READ_REG(TIMx->CCR2));
<>	134:ad3be0349dc5	2424	}
<>	134:ad3be0349dc5	2425
<>	134:ad3be0349dc5	2426	/**
<>	134:ad3be0349dc5	2427	* @brief Get captured value for input channel 3.
<>	134:ad3be0349dc5	2428	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	134:ad3be0349dc5	2429	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2430	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	2431	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2432	* input channel 3 is supported by a timer instance.
<>	134:ad3be0349dc5	2433	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
<>	134:ad3be0349dc5	2434	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2435	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	134:ad3be0349dc5	2436	*/
<>	134:ad3be0349dc5	2437	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2438	{
<>	134:ad3be0349dc5	2439	return (uint32_t)(READ_REG(TIMx->CCR3));
<>	134:ad3be0349dc5	2440	}
<>	134:ad3be0349dc5	2441
<>	134:ad3be0349dc5	2442	/**
<>	134:ad3be0349dc5	2443	* @brief Get captured value for input channel 4.
<>	134:ad3be0349dc5	2444	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	134:ad3be0349dc5	2445	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2446	* whether or not a timer instance supports a 32 bits counter.
<>	134:ad3be0349dc5	2447	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2448	* input channel 4 is supported by a timer instance.
<>	134:ad3be0349dc5	2449	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
<>	134:ad3be0349dc5	2450	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2451	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	134:ad3be0349dc5	2452	*/
<>	134:ad3be0349dc5	2453	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2454	{
<>	134:ad3be0349dc5	2455	return (uint32_t)(READ_REG(TIMx->CCR4));
<>	134:ad3be0349dc5	2456	}
<>	134:ad3be0349dc5	2457
<>	134:ad3be0349dc5	2458	/**
<>	134:ad3be0349dc5	2459	* @}
<>	134:ad3be0349dc5	2460	*/
<>	134:ad3be0349dc5	2461
<>	134:ad3be0349dc5	2462	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
<>	134:ad3be0349dc5	2463	* @{
<>	134:ad3be0349dc5	2464	*/
<>	134:ad3be0349dc5	2465	/**
<>	134:ad3be0349dc5	2466	* @brief Enable external clock mode 2.
<>	134:ad3be0349dc5	2467	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
<>	134:ad3be0349dc5	2468	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2469	* whether or not a timer instance supports external clock mode2.
<>	134:ad3be0349dc5	2470	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
<>	134:ad3be0349dc5	2471	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2472	* @retval None
<>	134:ad3be0349dc5	2473	*/
<>	134:ad3be0349dc5	2474	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2475	{
<>	134:ad3be0349dc5	2476	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<>	134:ad3be0349dc5	2477	}
<>	134:ad3be0349dc5	2478
<>	134:ad3be0349dc5	2479	/**
<>	134:ad3be0349dc5	2480	* @brief Disable external clock mode 2.
<>	134:ad3be0349dc5	2481	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2482	* whether or not a timer instance supports external clock mode2.
<>	134:ad3be0349dc5	2483	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
<>	134:ad3be0349dc5	2484	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2485	* @retval None
<>	134:ad3be0349dc5	2486	*/
<>	134:ad3be0349dc5	2487	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2488	{
<>	134:ad3be0349dc5	2489	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<>	134:ad3be0349dc5	2490	}
<>	134:ad3be0349dc5	2491
<>	134:ad3be0349dc5	2492	/**
<>	134:ad3be0349dc5	2493	* @brief Indicate whether external clock mode 2 is enabled.
<>	134:ad3be0349dc5	2494	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2495	* whether or not a timer instance supports external clock mode2.
<>	134:ad3be0349dc5	2496	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
<>	134:ad3be0349dc5	2497	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2498	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2499	*/
<>	134:ad3be0349dc5	2500	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2501	{
<>	134:ad3be0349dc5	2502	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
<>	134:ad3be0349dc5	2503	}
<>	134:ad3be0349dc5	2504
<>	134:ad3be0349dc5	2505	/**
<>	134:ad3be0349dc5	2506	* @brief Set the clock source of the counter clock.
<>	134:ad3be0349dc5	2507	* @note when selected clock source is external clock mode 1, the timer input
<>	134:ad3be0349dc5	2508	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
<>	134:ad3be0349dc5	2509	* function. This timer input must be configured by calling
<>	134:ad3be0349dc5	2510	* the @ref LL_TIM_IC_Config() function.
<>	134:ad3be0349dc5	2511	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2512	* whether or not a timer instance supports external clock mode1.
<>	134:ad3be0349dc5	2513	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2514	* whether or not a timer instance supports external clock mode2.
<>	134:ad3be0349dc5	2515	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
<>	134:ad3be0349dc5	2516	* SMCR ECE LL_TIM_SetClockSource
<>	134:ad3be0349dc5	2517	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2518	* @param ClockSource This parameter can be one of the following values:
<>	134:ad3be0349dc5	2519	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
<>	134:ad3be0349dc5	2520	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
<>	134:ad3be0349dc5	2521	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
<>	134:ad3be0349dc5	2522	* @retval None
<>	134:ad3be0349dc5	2523	*/
<>	134:ad3be0349dc5	2524	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
<>	134:ad3be0349dc5	2525	{
<>	134:ad3be0349dc5	2526	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
<>	134:ad3be0349dc5	2527	}
<>	134:ad3be0349dc5	2528
<>	134:ad3be0349dc5	2529	/**
<>	134:ad3be0349dc5	2530	* @brief Set the encoder interface mode.
<>	134:ad3be0349dc5	2531	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2532	* whether or not a timer instance supports the encoder mode.
<>	134:ad3be0349dc5	2533	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
<>	134:ad3be0349dc5	2534	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2535	* @param EncoderMode This parameter can be one of the following values:
<>	134:ad3be0349dc5	2536	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
<>	134:ad3be0349dc5	2537	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
<>	134:ad3be0349dc5	2538	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
<>	134:ad3be0349dc5	2539	* @retval None
<>	134:ad3be0349dc5	2540	*/
<>	134:ad3be0349dc5	2541	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
<>	134:ad3be0349dc5	2542	{
<>	134:ad3be0349dc5	2543	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
<>	134:ad3be0349dc5	2544	}
<>	134:ad3be0349dc5	2545
<>	134:ad3be0349dc5	2546	/**
<>	134:ad3be0349dc5	2547	* @}
<>	134:ad3be0349dc5	2548	*/
<>	134:ad3be0349dc5	2549
<>	134:ad3be0349dc5	2550	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
<>	134:ad3be0349dc5	2551	* @{
<>	134:ad3be0349dc5	2552	*/
<>	134:ad3be0349dc5	2553	/**
<>	134:ad3be0349dc5	2554	* @brief Set the trigger output (TRGO) used for timer synchronization .
<>	134:ad3be0349dc5	2555	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
<>	134:ad3be0349dc5	2556	* whether or not a timer instance can operate as a master timer.
<>	134:ad3be0349dc5	2557	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
<>	134:ad3be0349dc5	2558	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2559	* @param TimerSynchronization This parameter can be one of the following values:
<>	134:ad3be0349dc5	2560	* @arg @ref LL_TIM_TRGO_RESET
<>	134:ad3be0349dc5	2561	* @arg @ref LL_TIM_TRGO_ENABLE
<>	134:ad3be0349dc5	2562	* @arg @ref LL_TIM_TRGO_UPDATE
<>	134:ad3be0349dc5	2563	* @arg @ref LL_TIM_TRGO_CC1IF
<>	134:ad3be0349dc5	2564	* @arg @ref LL_TIM_TRGO_OC1REF
<>	134:ad3be0349dc5	2565	* @arg @ref LL_TIM_TRGO_OC2REF
<>	134:ad3be0349dc5	2566	* @arg @ref LL_TIM_TRGO_OC3REF
<>	134:ad3be0349dc5	2567	* @arg @ref LL_TIM_TRGO_OC4REF
<>	134:ad3be0349dc5	2568	* @retval None
<>	134:ad3be0349dc5	2569	*/
<>	134:ad3be0349dc5	2570	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
<>	134:ad3be0349dc5	2571	{
<>	134:ad3be0349dc5	2572	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
<>	134:ad3be0349dc5	2573	}
<>	134:ad3be0349dc5	2574
<>	134:ad3be0349dc5	2575	/**
<>	134:ad3be0349dc5	2576	* @brief Set the synchronization mode of a slave timer.
<>	134:ad3be0349dc5	2577	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2578	* a timer instance can operate as a slave timer.
<>	134:ad3be0349dc5	2579	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
<>	134:ad3be0349dc5	2580	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2581	* @param SlaveMode This parameter can be one of the following values:
<>	134:ad3be0349dc5	2582	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
<>	134:ad3be0349dc5	2583	* @arg @ref LL_TIM_SLAVEMODE_RESET
<>	134:ad3be0349dc5	2584	* @arg @ref LL_TIM_SLAVEMODE_GATED
<>	134:ad3be0349dc5	2585	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
<>	134:ad3be0349dc5	2586	* @retval None
<>	134:ad3be0349dc5	2587	*/
<>	134:ad3be0349dc5	2588	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
<>	134:ad3be0349dc5	2589	{
<>	134:ad3be0349dc5	2590	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
<>	134:ad3be0349dc5	2591	}
<>	134:ad3be0349dc5	2592
<>	134:ad3be0349dc5	2593	/**
<>	134:ad3be0349dc5	2594	* @brief Set the selects the trigger input to be used to synchronize the counter.
<>	134:ad3be0349dc5	2595	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2596	* a timer instance can operate as a slave timer.
<>	134:ad3be0349dc5	2597	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
<>	134:ad3be0349dc5	2598	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2599	* @param TriggerInput This parameter can be one of the following values:
<>	134:ad3be0349dc5	2600	* @arg @ref LL_TIM_TS_ITR0
<>	134:ad3be0349dc5	2601	* @arg @ref LL_TIM_TS_ITR1
<>	134:ad3be0349dc5	2602	* @arg @ref LL_TIM_TS_ITR2
<>	134:ad3be0349dc5	2603	* @arg @ref LL_TIM_TS_ITR3
<>	134:ad3be0349dc5	2604	* @arg @ref LL_TIM_TS_TI1F_ED
<>	134:ad3be0349dc5	2605	* @arg @ref LL_TIM_TS_TI1FP1
<>	134:ad3be0349dc5	2606	* @arg @ref LL_TIM_TS_TI2FP2
<>	134:ad3be0349dc5	2607	* @arg @ref LL_TIM_TS_ETRF
<>	134:ad3be0349dc5	2608	* @retval None
<>	134:ad3be0349dc5	2609	*/
<>	134:ad3be0349dc5	2610	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
<>	134:ad3be0349dc5	2611	{
<>	134:ad3be0349dc5	2612	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
<>	134:ad3be0349dc5	2613	}
<>	134:ad3be0349dc5	2614
<>	134:ad3be0349dc5	2615	/**
<>	134:ad3be0349dc5	2616	* @brief Enable the Master/Slave mode.
<>	134:ad3be0349dc5	2617	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2618	* a timer instance can operate as a slave timer.
<>	134:ad3be0349dc5	2619	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
<>	134:ad3be0349dc5	2620	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2621	* @retval None
<>	134:ad3be0349dc5	2622	*/
<>	134:ad3be0349dc5	2623	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2624	{
<>	134:ad3be0349dc5	2625	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<>	134:ad3be0349dc5	2626	}
<>	134:ad3be0349dc5	2627
<>	134:ad3be0349dc5	2628	/**
<>	134:ad3be0349dc5	2629	* @brief Disable the Master/Slave mode.
<>	134:ad3be0349dc5	2630	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2631	* a timer instance can operate as a slave timer.
<>	134:ad3be0349dc5	2632	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
<>	134:ad3be0349dc5	2633	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2634	* @retval None
<>	134:ad3be0349dc5	2635	*/
<>	134:ad3be0349dc5	2636	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2637	{
<>	134:ad3be0349dc5	2638	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<>	134:ad3be0349dc5	2639	}
<>	134:ad3be0349dc5	2640
<>	134:ad3be0349dc5	2641	/**
<>	134:ad3be0349dc5	2642	* @brief Indicates whether the Master/Slave mode is enabled.
<>	134:ad3be0349dc5	2643	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2644	* a timer instance can operate as a slave timer.
<>	134:ad3be0349dc5	2645	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
<>	134:ad3be0349dc5	2646	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2647	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2648	*/
<>	134:ad3be0349dc5	2649	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2650	{
<>	134:ad3be0349dc5	2651	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
<>	134:ad3be0349dc5	2652	}
<>	134:ad3be0349dc5	2653
<>	134:ad3be0349dc5	2654	/**
<>	134:ad3be0349dc5	2655	* @brief Configure the external trigger (ETR) input.
<>	134:ad3be0349dc5	2656	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2657	* a timer instance provides an external trigger input.
<>	134:ad3be0349dc5	2658	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
<>	134:ad3be0349dc5	2659	* SMCR ETPS LL_TIM_ConfigETR\n
<>	134:ad3be0349dc5	2660	* SMCR ETF LL_TIM_ConfigETR
<>	134:ad3be0349dc5	2661	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2662	* @param ETRPolarity This parameter can be one of the following values:
<>	134:ad3be0349dc5	2663	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
<>	134:ad3be0349dc5	2664	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
<>	134:ad3be0349dc5	2665	* @param ETRPrescaler This parameter can be one of the following values:
<>	134:ad3be0349dc5	2666	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
<>	134:ad3be0349dc5	2667	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
<>	134:ad3be0349dc5	2668	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
<>	134:ad3be0349dc5	2669	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
<>	134:ad3be0349dc5	2670	* @param ETRFilter This parameter can be one of the following values:
<>	134:ad3be0349dc5	2671	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
<>	134:ad3be0349dc5	2672	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
<>	134:ad3be0349dc5	2673	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
<>	134:ad3be0349dc5	2674	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
<>	134:ad3be0349dc5	2675	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
<>	134:ad3be0349dc5	2676	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
<>	134:ad3be0349dc5	2677	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
<>	134:ad3be0349dc5	2678	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
<>	134:ad3be0349dc5	2679	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
<>	134:ad3be0349dc5	2680	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
<>	134:ad3be0349dc5	2681	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
<>	134:ad3be0349dc5	2682	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
<>	134:ad3be0349dc5	2683	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
<>	134:ad3be0349dc5	2684	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
<>	134:ad3be0349dc5	2685	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
<>	134:ad3be0349dc5	2686	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
<>	134:ad3be0349dc5	2687	* @retval None
<>	134:ad3be0349dc5	2688	*/
<>	134:ad3be0349dc5	2689	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
<>	134:ad3be0349dc5	2690	uint32_t ETRFilter)
<>	134:ad3be0349dc5	2691	{
<>	134:ad3be0349dc5	2692	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
<>	134:ad3be0349dc5	2693	}
<>	134:ad3be0349dc5	2694
<>	134:ad3be0349dc5	2695	/**
<>	134:ad3be0349dc5	2696	* @}
<>	134:ad3be0349dc5	2697	*/
<>	134:ad3be0349dc5	2698
<>	134:ad3be0349dc5	2699	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
<>	134:ad3be0349dc5	2700	* @{
<>	134:ad3be0349dc5	2701	*/
<>	134:ad3be0349dc5	2702	/**
<>	134:ad3be0349dc5	2703	* @brief Enable the break function.
<>	134:ad3be0349dc5	2704	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2705	* a timer instance provides a break input.
<>	134:ad3be0349dc5	2706	* @rmtoll BDTR BKE LL_TIM_EnableBRK
<>	134:ad3be0349dc5	2707	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2708	* @retval None
<>	134:ad3be0349dc5	2709	*/
<>	134:ad3be0349dc5	2710	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2711	{
<>	134:ad3be0349dc5	2712	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
<>	134:ad3be0349dc5	2713	}
<>	134:ad3be0349dc5	2714
<>	134:ad3be0349dc5	2715	/**
<>	134:ad3be0349dc5	2716	* @brief Disable the break function.
<>	134:ad3be0349dc5	2717	* @rmtoll BDTR BKE LL_TIM_DisableBRK
<>	134:ad3be0349dc5	2718	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2719	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2720	* a timer instance provides a break input.
<>	134:ad3be0349dc5	2721	* @retval None
<>	134:ad3be0349dc5	2722	*/
<>	134:ad3be0349dc5	2723	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2724	{
<>	134:ad3be0349dc5	2725	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
<>	134:ad3be0349dc5	2726	}
<>	134:ad3be0349dc5	2727
<>	134:ad3be0349dc5	2728	/**
<>	134:ad3be0349dc5	2729	* @brief Configure the break input.
<>	134:ad3be0349dc5	2730	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2731	* a timer instance provides a break input.
<>	134:ad3be0349dc5	2732	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
<>	134:ad3be0349dc5	2733	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2734	* @param BreakPolarity This parameter can be one of the following values:
<>	134:ad3be0349dc5	2735	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
<>	134:ad3be0349dc5	2736	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
<>	134:ad3be0349dc5	2737	* @retval None
<>	134:ad3be0349dc5	2738	*/
<>	134:ad3be0349dc5	2739	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
<>	134:ad3be0349dc5	2740	{
<>	134:ad3be0349dc5	2741	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
<>	134:ad3be0349dc5	2742	}
<>	134:ad3be0349dc5	2743
<>	134:ad3be0349dc5	2744	/**
<>	134:ad3be0349dc5	2745	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
<>	134:ad3be0349dc5	2746	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2747	* a timer instance provides a break input.
<>	134:ad3be0349dc5	2748	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
<>	134:ad3be0349dc5	2749	* BDTR OSSR LL_TIM_SetOffStates
<>	134:ad3be0349dc5	2750	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2751	* @param OffStateIdle This parameter can be one of the following values:
<>	134:ad3be0349dc5	2752	* @arg @ref LL_TIM_OSSI_DISABLE
<>	134:ad3be0349dc5	2753	* @arg @ref LL_TIM_OSSI_ENABLE
<>	134:ad3be0349dc5	2754	* @param OffStateRun This parameter can be one of the following values:
<>	134:ad3be0349dc5	2755	* @arg @ref LL_TIM_OSSR_DISABLE
<>	134:ad3be0349dc5	2756	* @arg @ref LL_TIM_OSSR_ENABLE
<>	134:ad3be0349dc5	2757	* @retval None
<>	134:ad3be0349dc5	2758	*/
<>	134:ad3be0349dc5	2759	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
<>	134:ad3be0349dc5	2760	{
<>	134:ad3be0349dc5	2761	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
<>	134:ad3be0349dc5	2762	}
<>	134:ad3be0349dc5	2763
<>	134:ad3be0349dc5	2764	/**
<>	134:ad3be0349dc5	2765	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
<>	134:ad3be0349dc5	2766	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2767	* a timer instance provides a break input.
<>	134:ad3be0349dc5	2768	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
<>	134:ad3be0349dc5	2769	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2770	* @retval None
<>	134:ad3be0349dc5	2771	*/
<>	134:ad3be0349dc5	2772	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2773	{
<>	134:ad3be0349dc5	2774	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
<>	134:ad3be0349dc5	2775	}
<>	134:ad3be0349dc5	2776
<>	134:ad3be0349dc5	2777	/**
<>	134:ad3be0349dc5	2778	* @brief Disable automatic output (MOE can be set only by software).
<>	134:ad3be0349dc5	2779	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2780	* a timer instance provides a break input.
<>	134:ad3be0349dc5	2781	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
<>	134:ad3be0349dc5	2782	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2783	* @retval None
<>	134:ad3be0349dc5	2784	*/
<>	134:ad3be0349dc5	2785	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2786	{
<>	134:ad3be0349dc5	2787	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
<>	134:ad3be0349dc5	2788	}
<>	134:ad3be0349dc5	2789
<>	134:ad3be0349dc5	2790	/**
<>	134:ad3be0349dc5	2791	* @brief Indicate whether automatic output is enabled.
<>	134:ad3be0349dc5	2792	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2793	* a timer instance provides a break input.
<>	134:ad3be0349dc5	2794	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
<>	134:ad3be0349dc5	2795	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2796	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2797	*/
<>	134:ad3be0349dc5	2798	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2799	{
<>	134:ad3be0349dc5	2800	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
<>	134:ad3be0349dc5	2801	}
<>	134:ad3be0349dc5	2802
<>	134:ad3be0349dc5	2803	/**
<>	134:ad3be0349dc5	2804	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
<>	134:ad3be0349dc5	2805	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
<>	134:ad3be0349dc5	2806	* software and is reset in case of break or break2 event
<>	134:ad3be0349dc5	2807	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2808	* a timer instance provides a break input.
<>	134:ad3be0349dc5	2809	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
<>	134:ad3be0349dc5	2810	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2811	* @retval None
<>	134:ad3be0349dc5	2812	*/
<>	134:ad3be0349dc5	2813	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2814	{
<>	134:ad3be0349dc5	2815	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
<>	134:ad3be0349dc5	2816	}
<>	134:ad3be0349dc5	2817
<>	134:ad3be0349dc5	2818	/**
<>	134:ad3be0349dc5	2819	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
<>	134:ad3be0349dc5	2820	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
<>	134:ad3be0349dc5	2821	* software and is reset in case of break or break2 event.
<>	134:ad3be0349dc5	2822	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2823	* a timer instance provides a break input.
<>	134:ad3be0349dc5	2824	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
<>	134:ad3be0349dc5	2825	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2826	* @retval None
<>	134:ad3be0349dc5	2827	*/
<>	134:ad3be0349dc5	2828	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2829	{
<>	134:ad3be0349dc5	2830	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
<>	134:ad3be0349dc5	2831	}
<>	134:ad3be0349dc5	2832
<>	134:ad3be0349dc5	2833	/**
<>	134:ad3be0349dc5	2834	* @brief Indicates whether outputs are enabled.
<>	134:ad3be0349dc5	2835	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2836	* a timer instance provides a break input.
<>	134:ad3be0349dc5	2837	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
<>	134:ad3be0349dc5	2838	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2839	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2840	*/
<>	134:ad3be0349dc5	2841	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2842	{
<>	134:ad3be0349dc5	2843	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
<>	134:ad3be0349dc5	2844	}
<>	134:ad3be0349dc5	2845
<>	134:ad3be0349dc5	2846	/**
<>	134:ad3be0349dc5	2847	* @}
<>	134:ad3be0349dc5	2848	*/
<>	134:ad3be0349dc5	2849
<>	134:ad3be0349dc5	2850	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
<>	134:ad3be0349dc5	2851	* @{
<>	134:ad3be0349dc5	2852	*/
<>	134:ad3be0349dc5	2853	/**
<>	134:ad3be0349dc5	2854	* @brief Configures the timer DMA burst feature.
<>	134:ad3be0349dc5	2855	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
<>	134:ad3be0349dc5	2856	* not a timer instance supports the DMA burst mode.
<>	134:ad3be0349dc5	2857	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
<>	134:ad3be0349dc5	2858	* DCR DBA LL_TIM_ConfigDMABurst
<>	134:ad3be0349dc5	2859	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2860	* @param DMABurstBaseAddress This parameter can be one of the following values:
<>	134:ad3be0349dc5	2861	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
<>	134:ad3be0349dc5	2862	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
<>	134:ad3be0349dc5	2863	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
<>	134:ad3be0349dc5	2864	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
<>	134:ad3be0349dc5	2865	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
<>	134:ad3be0349dc5	2866	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
<>	134:ad3be0349dc5	2867	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
<>	134:ad3be0349dc5	2868	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
<>	134:ad3be0349dc5	2869	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
<>	134:ad3be0349dc5	2870	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
<>	134:ad3be0349dc5	2871	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
<>	134:ad3be0349dc5	2872	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
<>	134:ad3be0349dc5	2873	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
<>	134:ad3be0349dc5	2874	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
<>	134:ad3be0349dc5	2875	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
<>	134:ad3be0349dc5	2876	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
<>	134:ad3be0349dc5	2877	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
<>	134:ad3be0349dc5	2878	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
<>	134:ad3be0349dc5	2879	* @param DMABurstLength This parameter can be one of the following values:
<>	134:ad3be0349dc5	2880	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
<>	134:ad3be0349dc5	2881	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
<>	134:ad3be0349dc5	2882	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
<>	134:ad3be0349dc5	2883	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
<>	134:ad3be0349dc5	2884	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
<>	134:ad3be0349dc5	2885	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
<>	134:ad3be0349dc5	2886	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
<>	134:ad3be0349dc5	2887	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
<>	134:ad3be0349dc5	2888	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
<>	134:ad3be0349dc5	2889	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
<>	134:ad3be0349dc5	2890	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
<>	134:ad3be0349dc5	2891	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
<>	134:ad3be0349dc5	2892	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
<>	134:ad3be0349dc5	2893	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
<>	134:ad3be0349dc5	2894	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
<>	134:ad3be0349dc5	2895	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
<>	134:ad3be0349dc5	2896	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
<>	134:ad3be0349dc5	2897	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
<>	134:ad3be0349dc5	2898	* @retval None
<>	134:ad3be0349dc5	2899	*/
<>	134:ad3be0349dc5	2900	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
<>	134:ad3be0349dc5	2901	{
<>	134:ad3be0349dc5	2902	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
<>	134:ad3be0349dc5	2903	}
<>	134:ad3be0349dc5	2904
<>	134:ad3be0349dc5	2905	/**
<>	134:ad3be0349dc5	2906	* @}
<>	134:ad3be0349dc5	2907	*/
<>	134:ad3be0349dc5	2908
<>	134:ad3be0349dc5	2909	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
<>	134:ad3be0349dc5	2910	* @{
<>	134:ad3be0349dc5	2911	*/
<>	134:ad3be0349dc5	2912	/**
<>	134:ad3be0349dc5	2913	* @brief Remap TIM inputs (input channel, internal/external triggers).
<>	134:ad3be0349dc5	2914	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
<>	134:ad3be0349dc5	2915	* a some timer inputs can be remapped.
<>	134:ad3be0349dc5	2916	* @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
<>	134:ad3be0349dc5	2917	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2918	* @param Remap This parameter can be one of the following values:
<>	134:ad3be0349dc5	2919	* @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
<>	134:ad3be0349dc5	2920	* @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
<>	134:ad3be0349dc5	2921	* @arg @ref LL_TIM_TIM14_TI1_RMP_HSE
<>	134:ad3be0349dc5	2922	* @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
<>	134:ad3be0349dc5	2923	*
<>	134:ad3be0349dc5	2924	* @retval None
<>	134:ad3be0349dc5	2925	*/
<>	134:ad3be0349dc5	2926	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
<>	134:ad3be0349dc5	2927	{
<>	134:ad3be0349dc5	2928	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
<>	134:ad3be0349dc5	2929	}
<>	134:ad3be0349dc5	2930
<>	134:ad3be0349dc5	2931	/**
<>	134:ad3be0349dc5	2932	* @}
<>	134:ad3be0349dc5	2933	*/
<>	134:ad3be0349dc5	2934
<>	134:ad3be0349dc5	2935	#if defined(TIM_SMCR_OCCS)
<>	134:ad3be0349dc5	2936	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
<>	134:ad3be0349dc5	2937	* @{
<>	134:ad3be0349dc5	2938	*/
<>	134:ad3be0349dc5	2939	/**
<>	134:ad3be0349dc5	2940	* @brief Set the OCREF clear source
<>	134:ad3be0349dc5	2941	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
<>	134:ad3be0349dc5	2942	* @note This function can only be used in Output compare and PWM modes.
<>	134:ad3be0349dc5	2943	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
<>	134:ad3be0349dc5	2944	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2945	* @param OCRefClearInputSource This parameter can be one of the following values:
<>	134:ad3be0349dc5	2946	* @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
<>	134:ad3be0349dc5	2947	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
<>	134:ad3be0349dc5	2948	* @retval None
<>	134:ad3be0349dc5	2949	*/
<>	134:ad3be0349dc5	2950	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
<>	134:ad3be0349dc5	2951	{
<>	134:ad3be0349dc5	2952	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
<>	134:ad3be0349dc5	2953	}
<>	134:ad3be0349dc5	2954	/**
<>	134:ad3be0349dc5	2955	* @}
<>	134:ad3be0349dc5	2956	*/
<>	134:ad3be0349dc5	2957
<>	134:ad3be0349dc5	2958	#endif /* TIM_SMCR_OCCS */
<>	134:ad3be0349dc5	2959	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
<>	134:ad3be0349dc5	2960	* @{
<>	134:ad3be0349dc5	2961	*/
<>	134:ad3be0349dc5	2962	/**
<>	134:ad3be0349dc5	2963	* @brief Clear the update interrupt flag (UIF).
<>	134:ad3be0349dc5	2964	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
<>	134:ad3be0349dc5	2965	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2966	* @retval None
<>	134:ad3be0349dc5	2967	*/
<>	134:ad3be0349dc5	2968	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2969	{
<>	134:ad3be0349dc5	2970	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
<>	134:ad3be0349dc5	2971	}
<>	134:ad3be0349dc5	2972
<>	134:ad3be0349dc5	2973	/**
<>	134:ad3be0349dc5	2974	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
<>	134:ad3be0349dc5	2975	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
<>	134:ad3be0349dc5	2976	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2977	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2978	*/
<>	134:ad3be0349dc5	2979	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2980	{
<>	134:ad3be0349dc5	2981	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
<>	134:ad3be0349dc5	2982	}
<>	134:ad3be0349dc5	2983
<>	134:ad3be0349dc5	2984	/**
<>	134:ad3be0349dc5	2985	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
<>	134:ad3be0349dc5	2986	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
<>	134:ad3be0349dc5	2987	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2988	* @retval None
<>	134:ad3be0349dc5	2989	*/
<>	134:ad3be0349dc5	2990	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	2991	{
<>	134:ad3be0349dc5	2992	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
<>	134:ad3be0349dc5	2993	}
<>	134:ad3be0349dc5	2994
<>	134:ad3be0349dc5	2995	/**
<>	134:ad3be0349dc5	2996	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
<>	134:ad3be0349dc5	2997	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
<>	134:ad3be0349dc5	2998	* @param TIMx Timer instance
<>	134:ad3be0349dc5	2999	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3000	*/
<>	134:ad3be0349dc5	3001	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3002	{
<>	134:ad3be0349dc5	3003	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
<>	134:ad3be0349dc5	3004	}
<>	134:ad3be0349dc5	3005
<>	134:ad3be0349dc5	3006	/**
<>	134:ad3be0349dc5	3007	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
<>	134:ad3be0349dc5	3008	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
<>	134:ad3be0349dc5	3009	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3010	* @retval None
<>	134:ad3be0349dc5	3011	*/
<>	134:ad3be0349dc5	3012	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3013	{
<>	134:ad3be0349dc5	3014	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
<>	134:ad3be0349dc5	3015	}
<>	134:ad3be0349dc5	3016
<>	134:ad3be0349dc5	3017	/**
<>	134:ad3be0349dc5	3018	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
<>	134:ad3be0349dc5	3019	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
<>	134:ad3be0349dc5	3020	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3021	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3022	*/
<>	134:ad3be0349dc5	3023	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3024	{
<>	134:ad3be0349dc5	3025	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
<>	134:ad3be0349dc5	3026	}
<>	134:ad3be0349dc5	3027
<>	134:ad3be0349dc5	3028	/**
<>	134:ad3be0349dc5	3029	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
<>	134:ad3be0349dc5	3030	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
<>	134:ad3be0349dc5	3031	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3032	* @retval None
<>	134:ad3be0349dc5	3033	*/
<>	134:ad3be0349dc5	3034	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3035	{
<>	134:ad3be0349dc5	3036	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
<>	134:ad3be0349dc5	3037	}
<>	134:ad3be0349dc5	3038
<>	134:ad3be0349dc5	3039	/**
<>	134:ad3be0349dc5	3040	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
<>	134:ad3be0349dc5	3041	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
<>	134:ad3be0349dc5	3042	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3043	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3044	*/
<>	134:ad3be0349dc5	3045	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3046	{
<>	134:ad3be0349dc5	3047	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
<>	134:ad3be0349dc5	3048	}
<>	134:ad3be0349dc5	3049
<>	134:ad3be0349dc5	3050	/**
<>	134:ad3be0349dc5	3051	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
<>	134:ad3be0349dc5	3052	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
<>	134:ad3be0349dc5	3053	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3054	* @retval None
<>	134:ad3be0349dc5	3055	*/
<>	134:ad3be0349dc5	3056	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3057	{
<>	134:ad3be0349dc5	3058	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
<>	134:ad3be0349dc5	3059	}
<>	134:ad3be0349dc5	3060
<>	134:ad3be0349dc5	3061	/**
<>	134:ad3be0349dc5	3062	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
<>	134:ad3be0349dc5	3063	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
<>	134:ad3be0349dc5	3064	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3065	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3066	*/
<>	134:ad3be0349dc5	3067	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3068	{
<>	134:ad3be0349dc5	3069	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
<>	134:ad3be0349dc5	3070	}
<>	134:ad3be0349dc5	3071
<>	134:ad3be0349dc5	3072	/**
<>	134:ad3be0349dc5	3073	* @brief Clear the commutation interrupt flag (COMIF).
<>	134:ad3be0349dc5	3074	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
<>	134:ad3be0349dc5	3075	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3076	* @retval None
<>	134:ad3be0349dc5	3077	*/
<>	134:ad3be0349dc5	3078	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3079	{
<>	134:ad3be0349dc5	3080	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
<>	134:ad3be0349dc5	3081	}
<>	134:ad3be0349dc5	3082
<>	134:ad3be0349dc5	3083	/**
<>	134:ad3be0349dc5	3084	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
<>	134:ad3be0349dc5	3085	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
<>	134:ad3be0349dc5	3086	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3087	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3088	*/
<>	134:ad3be0349dc5	3089	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3090	{
<>	134:ad3be0349dc5	3091	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
<>	134:ad3be0349dc5	3092	}
<>	134:ad3be0349dc5	3093
<>	134:ad3be0349dc5	3094	/**
<>	134:ad3be0349dc5	3095	* @brief Clear the trigger interrupt flag (TIF).
<>	134:ad3be0349dc5	3096	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
<>	134:ad3be0349dc5	3097	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3098	* @retval None
<>	134:ad3be0349dc5	3099	*/
<>	134:ad3be0349dc5	3100	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3101	{
<>	134:ad3be0349dc5	3102	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
<>	134:ad3be0349dc5	3103	}
<>	134:ad3be0349dc5	3104
<>	134:ad3be0349dc5	3105	/**
<>	134:ad3be0349dc5	3106	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
<>	134:ad3be0349dc5	3107	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
<>	134:ad3be0349dc5	3108	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3109	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3110	*/
<>	134:ad3be0349dc5	3111	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3112	{
<>	134:ad3be0349dc5	3113	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
<>	134:ad3be0349dc5	3114	}
<>	134:ad3be0349dc5	3115
<>	134:ad3be0349dc5	3116	/**
<>	134:ad3be0349dc5	3117	* @brief Clear the break interrupt flag (BIF).
<>	134:ad3be0349dc5	3118	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
<>	134:ad3be0349dc5	3119	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3120	* @retval None
<>	134:ad3be0349dc5	3121	*/
<>	134:ad3be0349dc5	3122	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3123	{
<>	134:ad3be0349dc5	3124	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
<>	134:ad3be0349dc5	3125	}
<>	134:ad3be0349dc5	3126
<>	134:ad3be0349dc5	3127	/**
<>	134:ad3be0349dc5	3128	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
<>	134:ad3be0349dc5	3129	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
<>	134:ad3be0349dc5	3130	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3131	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3132	*/
<>	134:ad3be0349dc5	3133	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3134	{
<>	134:ad3be0349dc5	3135	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
<>	134:ad3be0349dc5	3136	}
<>	134:ad3be0349dc5	3137
<>	134:ad3be0349dc5	3138	/**
<>	134:ad3be0349dc5	3139	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
<>	134:ad3be0349dc5	3140	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
<>	134:ad3be0349dc5	3141	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3142	* @retval None
<>	134:ad3be0349dc5	3143	*/
<>	134:ad3be0349dc5	3144	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3145	{
<>	134:ad3be0349dc5	3146	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
<>	134:ad3be0349dc5	3147	}
<>	134:ad3be0349dc5	3148
<>	134:ad3be0349dc5	3149	/**
<>	134:ad3be0349dc5	3150	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
<>	134:ad3be0349dc5	3151	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
<>	134:ad3be0349dc5	3152	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3153	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3154	*/
<>	134:ad3be0349dc5	3155	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3156	{
<>	134:ad3be0349dc5	3157	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
<>	134:ad3be0349dc5	3158	}
<>	134:ad3be0349dc5	3159
<>	134:ad3be0349dc5	3160	/**
<>	134:ad3be0349dc5	3161	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
<>	134:ad3be0349dc5	3162	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
<>	134:ad3be0349dc5	3163	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3164	* @retval None
<>	134:ad3be0349dc5	3165	*/
<>	134:ad3be0349dc5	3166	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3167	{
<>	134:ad3be0349dc5	3168	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
<>	134:ad3be0349dc5	3169	}
<>	134:ad3be0349dc5	3170
<>	134:ad3be0349dc5	3171	/**
<>	134:ad3be0349dc5	3172	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
<>	134:ad3be0349dc5	3173	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
<>	134:ad3be0349dc5	3174	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3175	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3176	*/
<>	134:ad3be0349dc5	3177	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3178	{
<>	134:ad3be0349dc5	3179	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
<>	134:ad3be0349dc5	3180	}
<>	134:ad3be0349dc5	3181
<>	134:ad3be0349dc5	3182	/**
<>	134:ad3be0349dc5	3183	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
<>	134:ad3be0349dc5	3184	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
<>	134:ad3be0349dc5	3185	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3186	* @retval None
<>	134:ad3be0349dc5	3187	*/
<>	134:ad3be0349dc5	3188	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3189	{
<>	134:ad3be0349dc5	3190	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
<>	134:ad3be0349dc5	3191	}
<>	134:ad3be0349dc5	3192
<>	134:ad3be0349dc5	3193	/**
<>	134:ad3be0349dc5	3194	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
<>	134:ad3be0349dc5	3195	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
<>	134:ad3be0349dc5	3196	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3197	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3198	*/
<>	134:ad3be0349dc5	3199	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3200	{
<>	134:ad3be0349dc5	3201	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
<>	134:ad3be0349dc5	3202	}
<>	134:ad3be0349dc5	3203
<>	134:ad3be0349dc5	3204	/**
<>	134:ad3be0349dc5	3205	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
<>	134:ad3be0349dc5	3206	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
<>	134:ad3be0349dc5	3207	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3208	* @retval None
<>	134:ad3be0349dc5	3209	*/
<>	134:ad3be0349dc5	3210	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3211	{
<>	134:ad3be0349dc5	3212	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
<>	134:ad3be0349dc5	3213	}
<>	134:ad3be0349dc5	3214
<>	134:ad3be0349dc5	3215	/**
<>	134:ad3be0349dc5	3216	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
<>	134:ad3be0349dc5	3217	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
<>	134:ad3be0349dc5	3218	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3219	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3220	*/
<>	134:ad3be0349dc5	3221	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3222	{
<>	134:ad3be0349dc5	3223	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
<>	134:ad3be0349dc5	3224	}
<>	134:ad3be0349dc5	3225
<>	134:ad3be0349dc5	3226	/**
<>	134:ad3be0349dc5	3227	* @}
<>	134:ad3be0349dc5	3228	*/
<>	134:ad3be0349dc5	3229
<>	134:ad3be0349dc5	3230	/** @defgroup TIM_LL_EF_IT_Management IT-Management
<>	134:ad3be0349dc5	3231	* @{
<>	134:ad3be0349dc5	3232	*/
<>	134:ad3be0349dc5	3233	/**
<>	134:ad3be0349dc5	3234	* @brief Enable update interrupt (UIE).
<>	134:ad3be0349dc5	3235	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
<>	134:ad3be0349dc5	3236	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3237	* @retval None
<>	134:ad3be0349dc5	3238	*/
<>	134:ad3be0349dc5	3239	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3240	{
<>	134:ad3be0349dc5	3241	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
<>	134:ad3be0349dc5	3242	}
<>	134:ad3be0349dc5	3243
<>	134:ad3be0349dc5	3244	/**
<>	134:ad3be0349dc5	3245	* @brief Disable update interrupt (UIE).
<>	134:ad3be0349dc5	3246	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
<>	134:ad3be0349dc5	3247	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3248	* @retval None
<>	134:ad3be0349dc5	3249	*/
<>	134:ad3be0349dc5	3250	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3251	{
<>	134:ad3be0349dc5	3252	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
<>	134:ad3be0349dc5	3253	}
<>	134:ad3be0349dc5	3254
<>	134:ad3be0349dc5	3255	/**
<>	134:ad3be0349dc5	3256	* @brief Indicates whether the update interrupt (UIE) is enabled.
<>	134:ad3be0349dc5	3257	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
<>	134:ad3be0349dc5	3258	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3259	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3260	*/
<>	134:ad3be0349dc5	3261	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3262	{
<>	134:ad3be0349dc5	3263	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
<>	134:ad3be0349dc5	3264	}
<>	134:ad3be0349dc5	3265
<>	134:ad3be0349dc5	3266	/**
<>	134:ad3be0349dc5	3267	* @brief Enable capture/compare 1 interrupt (CC1IE).
<>	134:ad3be0349dc5	3268	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
<>	134:ad3be0349dc5	3269	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3270	* @retval None
<>	134:ad3be0349dc5	3271	*/
<>	134:ad3be0349dc5	3272	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3273	{
<>	134:ad3be0349dc5	3274	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<>	134:ad3be0349dc5	3275	}
<>	134:ad3be0349dc5	3276
<>	134:ad3be0349dc5	3277	/**
<>	134:ad3be0349dc5	3278	* @brief Disable capture/compare 1 interrupt (CC1IE).
<>	134:ad3be0349dc5	3279	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
<>	134:ad3be0349dc5	3280	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3281	* @retval None
<>	134:ad3be0349dc5	3282	*/
<>	134:ad3be0349dc5	3283	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3284	{
<>	134:ad3be0349dc5	3285	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<>	134:ad3be0349dc5	3286	}
<>	134:ad3be0349dc5	3287
<>	134:ad3be0349dc5	3288	/**
<>	134:ad3be0349dc5	3289	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
<>	134:ad3be0349dc5	3290	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
<>	134:ad3be0349dc5	3291	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3292	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3293	*/
<>	134:ad3be0349dc5	3294	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3295	{
<>	134:ad3be0349dc5	3296	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
<>	134:ad3be0349dc5	3297	}
<>	134:ad3be0349dc5	3298
<>	134:ad3be0349dc5	3299	/**
<>	134:ad3be0349dc5	3300	* @brief Enable capture/compare 2 interrupt (CC2IE).
<>	134:ad3be0349dc5	3301	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
<>	134:ad3be0349dc5	3302	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3303	* @retval None
<>	134:ad3be0349dc5	3304	*/
<>	134:ad3be0349dc5	3305	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3306	{
<>	134:ad3be0349dc5	3307	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<>	134:ad3be0349dc5	3308	}
<>	134:ad3be0349dc5	3309
<>	134:ad3be0349dc5	3310	/**
<>	134:ad3be0349dc5	3311	* @brief Disable capture/compare 2 interrupt (CC2IE).
<>	134:ad3be0349dc5	3312	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
<>	134:ad3be0349dc5	3313	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3314	* @retval None
<>	134:ad3be0349dc5	3315	*/
<>	134:ad3be0349dc5	3316	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3317	{
<>	134:ad3be0349dc5	3318	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<>	134:ad3be0349dc5	3319	}
<>	134:ad3be0349dc5	3320
<>	134:ad3be0349dc5	3321	/**
<>	134:ad3be0349dc5	3322	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
<>	134:ad3be0349dc5	3323	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
<>	134:ad3be0349dc5	3324	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3325	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3326	*/
<>	134:ad3be0349dc5	3327	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3328	{
<>	134:ad3be0349dc5	3329	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
<>	134:ad3be0349dc5	3330	}
<>	134:ad3be0349dc5	3331
<>	134:ad3be0349dc5	3332	/**
<>	134:ad3be0349dc5	3333	* @brief Enable capture/compare 3 interrupt (CC3IE).
<>	134:ad3be0349dc5	3334	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
<>	134:ad3be0349dc5	3335	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3336	* @retval None
<>	134:ad3be0349dc5	3337	*/
<>	134:ad3be0349dc5	3338	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3339	{
<>	134:ad3be0349dc5	3340	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<>	134:ad3be0349dc5	3341	}
<>	134:ad3be0349dc5	3342
<>	134:ad3be0349dc5	3343	/**
<>	134:ad3be0349dc5	3344	* @brief Disable capture/compare 3 interrupt (CC3IE).
<>	134:ad3be0349dc5	3345	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
<>	134:ad3be0349dc5	3346	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3347	* @retval None
<>	134:ad3be0349dc5	3348	*/
<>	134:ad3be0349dc5	3349	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3350	{
<>	134:ad3be0349dc5	3351	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<>	134:ad3be0349dc5	3352	}
<>	134:ad3be0349dc5	3353
<>	134:ad3be0349dc5	3354	/**
<>	134:ad3be0349dc5	3355	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
<>	134:ad3be0349dc5	3356	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
<>	134:ad3be0349dc5	3357	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3358	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3359	*/
<>	134:ad3be0349dc5	3360	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3361	{
<>	134:ad3be0349dc5	3362	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
<>	134:ad3be0349dc5	3363	}
<>	134:ad3be0349dc5	3364
<>	134:ad3be0349dc5	3365	/**
<>	134:ad3be0349dc5	3366	* @brief Enable capture/compare 4 interrupt (CC4IE).
<>	134:ad3be0349dc5	3367	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
<>	134:ad3be0349dc5	3368	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3369	* @retval None
<>	134:ad3be0349dc5	3370	*/
<>	134:ad3be0349dc5	3371	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3372	{
<>	134:ad3be0349dc5	3373	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<>	134:ad3be0349dc5	3374	}
<>	134:ad3be0349dc5	3375
<>	134:ad3be0349dc5	3376	/**
<>	134:ad3be0349dc5	3377	* @brief Disable capture/compare 4 interrupt (CC4IE).
<>	134:ad3be0349dc5	3378	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
<>	134:ad3be0349dc5	3379	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3380	* @retval None
<>	134:ad3be0349dc5	3381	*/
<>	134:ad3be0349dc5	3382	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3383	{
<>	134:ad3be0349dc5	3384	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<>	134:ad3be0349dc5	3385	}
<>	134:ad3be0349dc5	3386
<>	134:ad3be0349dc5	3387	/**
<>	134:ad3be0349dc5	3388	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
<>	134:ad3be0349dc5	3389	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
<>	134:ad3be0349dc5	3390	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3391	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3392	*/
<>	134:ad3be0349dc5	3393	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3394	{
<>	134:ad3be0349dc5	3395	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
<>	134:ad3be0349dc5	3396	}
<>	134:ad3be0349dc5	3397
<>	134:ad3be0349dc5	3398	/**
<>	134:ad3be0349dc5	3399	* @brief Enable commutation interrupt (COMIE).
<>	134:ad3be0349dc5	3400	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
<>	134:ad3be0349dc5	3401	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3402	* @retval None
<>	134:ad3be0349dc5	3403	*/
<>	134:ad3be0349dc5	3404	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3405	{
<>	134:ad3be0349dc5	3406	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
<>	134:ad3be0349dc5	3407	}
<>	134:ad3be0349dc5	3408
<>	134:ad3be0349dc5	3409	/**
<>	134:ad3be0349dc5	3410	* @brief Disable commutation interrupt (COMIE).
<>	134:ad3be0349dc5	3411	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
<>	134:ad3be0349dc5	3412	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3413	* @retval None
<>	134:ad3be0349dc5	3414	*/
<>	134:ad3be0349dc5	3415	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3416	{
<>	134:ad3be0349dc5	3417	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
<>	134:ad3be0349dc5	3418	}
<>	134:ad3be0349dc5	3419
<>	134:ad3be0349dc5	3420	/**
<>	134:ad3be0349dc5	3421	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
<>	134:ad3be0349dc5	3422	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
<>	134:ad3be0349dc5	3423	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3424	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3425	*/
<>	134:ad3be0349dc5	3426	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3427	{
<>	134:ad3be0349dc5	3428	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
<>	134:ad3be0349dc5	3429	}
<>	134:ad3be0349dc5	3430
<>	134:ad3be0349dc5	3431	/**
<>	134:ad3be0349dc5	3432	* @brief Enable trigger interrupt (TIE).
<>	134:ad3be0349dc5	3433	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
<>	134:ad3be0349dc5	3434	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3435	* @retval None
<>	134:ad3be0349dc5	3436	*/
<>	134:ad3be0349dc5	3437	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3438	{
<>	134:ad3be0349dc5	3439	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
<>	134:ad3be0349dc5	3440	}
<>	134:ad3be0349dc5	3441
<>	134:ad3be0349dc5	3442	/**
<>	134:ad3be0349dc5	3443	* @brief Disable trigger interrupt (TIE).
<>	134:ad3be0349dc5	3444	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
<>	134:ad3be0349dc5	3445	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3446	* @retval None
<>	134:ad3be0349dc5	3447	*/
<>	134:ad3be0349dc5	3448	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3449	{
<>	134:ad3be0349dc5	3450	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
<>	134:ad3be0349dc5	3451	}
<>	134:ad3be0349dc5	3452
<>	134:ad3be0349dc5	3453	/**
<>	134:ad3be0349dc5	3454	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
<>	134:ad3be0349dc5	3455	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
<>	134:ad3be0349dc5	3456	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3457	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3458	*/
<>	134:ad3be0349dc5	3459	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3460	{
<>	134:ad3be0349dc5	3461	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
<>	134:ad3be0349dc5	3462	}
<>	134:ad3be0349dc5	3463
<>	134:ad3be0349dc5	3464	/**
<>	134:ad3be0349dc5	3465	* @brief Enable break interrupt (BIE).
<>	134:ad3be0349dc5	3466	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
<>	134:ad3be0349dc5	3467	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3468	* @retval None
<>	134:ad3be0349dc5	3469	*/
<>	134:ad3be0349dc5	3470	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3471	{
<>	134:ad3be0349dc5	3472	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
<>	134:ad3be0349dc5	3473	}
<>	134:ad3be0349dc5	3474
<>	134:ad3be0349dc5	3475	/**
<>	134:ad3be0349dc5	3476	* @brief Disable break interrupt (BIE).
<>	134:ad3be0349dc5	3477	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
<>	134:ad3be0349dc5	3478	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3479	* @retval None
<>	134:ad3be0349dc5	3480	*/
<>	134:ad3be0349dc5	3481	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3482	{
<>	134:ad3be0349dc5	3483	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
<>	134:ad3be0349dc5	3484	}
<>	134:ad3be0349dc5	3485
<>	134:ad3be0349dc5	3486	/**
<>	134:ad3be0349dc5	3487	* @brief Indicates whether the break interrupt (BIE) is enabled.
<>	134:ad3be0349dc5	3488	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
<>	134:ad3be0349dc5	3489	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3490	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3491	*/
<>	134:ad3be0349dc5	3492	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3493	{
<>	134:ad3be0349dc5	3494	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
<>	134:ad3be0349dc5	3495	}
<>	134:ad3be0349dc5	3496
<>	134:ad3be0349dc5	3497	/**
<>	134:ad3be0349dc5	3498	* @}
<>	134:ad3be0349dc5	3499	*/
<>	134:ad3be0349dc5	3500
<>	134:ad3be0349dc5	3501	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
<>	134:ad3be0349dc5	3502	* @{
<>	134:ad3be0349dc5	3503	*/
<>	134:ad3be0349dc5	3504	/**
<>	134:ad3be0349dc5	3505	* @brief Enable update DMA request (UDE).
<>	134:ad3be0349dc5	3506	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
<>	134:ad3be0349dc5	3507	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3508	* @retval None
<>	134:ad3be0349dc5	3509	*/
<>	134:ad3be0349dc5	3510	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3511	{
<>	134:ad3be0349dc5	3512	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
<>	134:ad3be0349dc5	3513	}
<>	134:ad3be0349dc5	3514
<>	134:ad3be0349dc5	3515	/**
<>	134:ad3be0349dc5	3516	* @brief Disable update DMA request (UDE).
<>	134:ad3be0349dc5	3517	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
<>	134:ad3be0349dc5	3518	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3519	* @retval None
<>	134:ad3be0349dc5	3520	*/
<>	134:ad3be0349dc5	3521	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3522	{
<>	134:ad3be0349dc5	3523	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
<>	134:ad3be0349dc5	3524	}
<>	134:ad3be0349dc5	3525
<>	134:ad3be0349dc5	3526	/**
<>	134:ad3be0349dc5	3527	* @brief Indicates whether the update DMA request (UDE) is enabled.
<>	134:ad3be0349dc5	3528	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
<>	134:ad3be0349dc5	3529	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3530	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3531	*/
<>	134:ad3be0349dc5	3532	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3533	{
<>	134:ad3be0349dc5	3534	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
<>	134:ad3be0349dc5	3535	}
<>	134:ad3be0349dc5	3536
<>	134:ad3be0349dc5	3537	/**
<>	134:ad3be0349dc5	3538	* @brief Enable capture/compare 1 DMA request (CC1DE).
<>	134:ad3be0349dc5	3539	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
<>	134:ad3be0349dc5	3540	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3541	* @retval None
<>	134:ad3be0349dc5	3542	*/
<>	134:ad3be0349dc5	3543	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3544	{
<>	134:ad3be0349dc5	3545	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<>	134:ad3be0349dc5	3546	}
<>	134:ad3be0349dc5	3547
<>	134:ad3be0349dc5	3548	/**
<>	134:ad3be0349dc5	3549	* @brief Disable capture/compare 1 DMA request (CC1DE).
<>	134:ad3be0349dc5	3550	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
<>	134:ad3be0349dc5	3551	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3552	* @retval None
<>	134:ad3be0349dc5	3553	*/
<>	134:ad3be0349dc5	3554	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3555	{
<>	134:ad3be0349dc5	3556	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<>	134:ad3be0349dc5	3557	}
<>	134:ad3be0349dc5	3558
<>	134:ad3be0349dc5	3559	/**
<>	134:ad3be0349dc5	3560	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
<>	134:ad3be0349dc5	3561	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
<>	134:ad3be0349dc5	3562	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3563	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3564	*/
<>	134:ad3be0349dc5	3565	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3566	{
<>	134:ad3be0349dc5	3567	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
<>	134:ad3be0349dc5	3568	}
<>	134:ad3be0349dc5	3569
<>	134:ad3be0349dc5	3570	/**
<>	134:ad3be0349dc5	3571	* @brief Enable capture/compare 2 DMA request (CC2DE).
<>	134:ad3be0349dc5	3572	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
<>	134:ad3be0349dc5	3573	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3574	* @retval None
<>	134:ad3be0349dc5	3575	*/
<>	134:ad3be0349dc5	3576	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3577	{
<>	134:ad3be0349dc5	3578	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<>	134:ad3be0349dc5	3579	}
<>	134:ad3be0349dc5	3580
<>	134:ad3be0349dc5	3581	/**
<>	134:ad3be0349dc5	3582	* @brief Disable capture/compare 2 DMA request (CC2DE).
<>	134:ad3be0349dc5	3583	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
<>	134:ad3be0349dc5	3584	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3585	* @retval None
<>	134:ad3be0349dc5	3586	*/
<>	134:ad3be0349dc5	3587	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3588	{
<>	134:ad3be0349dc5	3589	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<>	134:ad3be0349dc5	3590	}
<>	134:ad3be0349dc5	3591
<>	134:ad3be0349dc5	3592	/**
<>	134:ad3be0349dc5	3593	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
<>	134:ad3be0349dc5	3594	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
<>	134:ad3be0349dc5	3595	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3596	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3597	*/
<>	134:ad3be0349dc5	3598	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3599	{
<>	134:ad3be0349dc5	3600	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
<>	134:ad3be0349dc5	3601	}
<>	134:ad3be0349dc5	3602
<>	134:ad3be0349dc5	3603	/**
<>	134:ad3be0349dc5	3604	* @brief Enable capture/compare 3 DMA request (CC3DE).
<>	134:ad3be0349dc5	3605	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
<>	134:ad3be0349dc5	3606	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3607	* @retval None
<>	134:ad3be0349dc5	3608	*/
<>	134:ad3be0349dc5	3609	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3610	{
<>	134:ad3be0349dc5	3611	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<>	134:ad3be0349dc5	3612	}
<>	134:ad3be0349dc5	3613
<>	134:ad3be0349dc5	3614	/**
<>	134:ad3be0349dc5	3615	* @brief Disable capture/compare 3 DMA request (CC3DE).
<>	134:ad3be0349dc5	3616	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
<>	134:ad3be0349dc5	3617	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3618	* @retval None
<>	134:ad3be0349dc5	3619	*/
<>	134:ad3be0349dc5	3620	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3621	{
<>	134:ad3be0349dc5	3622	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<>	134:ad3be0349dc5	3623	}
<>	134:ad3be0349dc5	3624
<>	134:ad3be0349dc5	3625	/**
<>	134:ad3be0349dc5	3626	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
<>	134:ad3be0349dc5	3627	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
<>	134:ad3be0349dc5	3628	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3629	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3630	*/
<>	134:ad3be0349dc5	3631	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3632	{
<>	134:ad3be0349dc5	3633	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
<>	134:ad3be0349dc5	3634	}
<>	134:ad3be0349dc5	3635
<>	134:ad3be0349dc5	3636	/**
<>	134:ad3be0349dc5	3637	* @brief Enable capture/compare 4 DMA request (CC4DE).
<>	134:ad3be0349dc5	3638	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
<>	134:ad3be0349dc5	3639	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3640	* @retval None
<>	134:ad3be0349dc5	3641	*/
<>	134:ad3be0349dc5	3642	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3643	{
<>	134:ad3be0349dc5	3644	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<>	134:ad3be0349dc5	3645	}
<>	134:ad3be0349dc5	3646
<>	134:ad3be0349dc5	3647	/**
<>	134:ad3be0349dc5	3648	* @brief Disable capture/compare 4 DMA request (CC4DE).
<>	134:ad3be0349dc5	3649	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
<>	134:ad3be0349dc5	3650	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3651	* @retval None
<>	134:ad3be0349dc5	3652	*/
<>	134:ad3be0349dc5	3653	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3654	{
<>	134:ad3be0349dc5	3655	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<>	134:ad3be0349dc5	3656	}
<>	134:ad3be0349dc5	3657
<>	134:ad3be0349dc5	3658	/**
<>	134:ad3be0349dc5	3659	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
<>	134:ad3be0349dc5	3660	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
<>	134:ad3be0349dc5	3661	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3662	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3663	*/
<>	134:ad3be0349dc5	3664	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3665	{
<>	134:ad3be0349dc5	3666	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
<>	134:ad3be0349dc5	3667	}
<>	134:ad3be0349dc5	3668
<>	134:ad3be0349dc5	3669	/**
<>	134:ad3be0349dc5	3670	* @brief Enable commutation DMA request (COMDE).
<>	134:ad3be0349dc5	3671	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
<>	134:ad3be0349dc5	3672	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3673	* @retval None
<>	134:ad3be0349dc5	3674	*/
<>	134:ad3be0349dc5	3675	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3676	{
<>	134:ad3be0349dc5	3677	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
<>	134:ad3be0349dc5	3678	}
<>	134:ad3be0349dc5	3679
<>	134:ad3be0349dc5	3680	/**
<>	134:ad3be0349dc5	3681	* @brief Disable commutation DMA request (COMDE).
<>	134:ad3be0349dc5	3682	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
<>	134:ad3be0349dc5	3683	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3684	* @retval None
<>	134:ad3be0349dc5	3685	*/
<>	134:ad3be0349dc5	3686	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3687	{
<>	134:ad3be0349dc5	3688	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
<>	134:ad3be0349dc5	3689	}
<>	134:ad3be0349dc5	3690
<>	134:ad3be0349dc5	3691	/**
<>	134:ad3be0349dc5	3692	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
<>	134:ad3be0349dc5	3693	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
<>	134:ad3be0349dc5	3694	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3695	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3696	*/
<>	134:ad3be0349dc5	3697	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3698	{
<>	134:ad3be0349dc5	3699	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
<>	134:ad3be0349dc5	3700	}
<>	134:ad3be0349dc5	3701
<>	134:ad3be0349dc5	3702	/**
<>	134:ad3be0349dc5	3703	* @brief Enable trigger interrupt (TDE).
<>	134:ad3be0349dc5	3704	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
<>	134:ad3be0349dc5	3705	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3706	* @retval None
<>	134:ad3be0349dc5	3707	*/
<>	134:ad3be0349dc5	3708	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3709	{
<>	134:ad3be0349dc5	3710	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
<>	134:ad3be0349dc5	3711	}
<>	134:ad3be0349dc5	3712
<>	134:ad3be0349dc5	3713	/**
<>	134:ad3be0349dc5	3714	* @brief Disable trigger interrupt (TDE).
<>	134:ad3be0349dc5	3715	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
<>	134:ad3be0349dc5	3716	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3717	* @retval None
<>	134:ad3be0349dc5	3718	*/
<>	134:ad3be0349dc5	3719	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3720	{
<>	134:ad3be0349dc5	3721	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
<>	134:ad3be0349dc5	3722	}
<>	134:ad3be0349dc5	3723
<>	134:ad3be0349dc5	3724	/**
<>	134:ad3be0349dc5	3725	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
<>	134:ad3be0349dc5	3726	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
<>	134:ad3be0349dc5	3727	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3728	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	3729	*/
<>	134:ad3be0349dc5	3730	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3731	{
<>	134:ad3be0349dc5	3732	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
<>	134:ad3be0349dc5	3733	}
<>	134:ad3be0349dc5	3734
<>	134:ad3be0349dc5	3735	/**
<>	134:ad3be0349dc5	3736	* @}
<>	134:ad3be0349dc5	3737	*/
<>	134:ad3be0349dc5	3738
<>	134:ad3be0349dc5	3739	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
<>	134:ad3be0349dc5	3740	* @{
<>	134:ad3be0349dc5	3741	*/
<>	134:ad3be0349dc5	3742	/**
<>	134:ad3be0349dc5	3743	* @brief Generate an update event.
<>	134:ad3be0349dc5	3744	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
<>	134:ad3be0349dc5	3745	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3746	* @retval None
<>	134:ad3be0349dc5	3747	*/
<>	134:ad3be0349dc5	3748	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3749	{
<>	134:ad3be0349dc5	3750	SET_BIT(TIMx->EGR, TIM_EGR_UG);
<>	134:ad3be0349dc5	3751	}
<>	134:ad3be0349dc5	3752
<>	134:ad3be0349dc5	3753	/**
<>	134:ad3be0349dc5	3754	* @brief Generate Capture/Compare 1 event.
<>	134:ad3be0349dc5	3755	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
<>	134:ad3be0349dc5	3756	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3757	* @retval None
<>	134:ad3be0349dc5	3758	*/
<>	134:ad3be0349dc5	3759	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3760	{
<>	134:ad3be0349dc5	3761	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
<>	134:ad3be0349dc5	3762	}
<>	134:ad3be0349dc5	3763
<>	134:ad3be0349dc5	3764	/**
<>	134:ad3be0349dc5	3765	* @brief Generate Capture/Compare 2 event.
<>	134:ad3be0349dc5	3766	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
<>	134:ad3be0349dc5	3767	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3768	* @retval None
<>	134:ad3be0349dc5	3769	*/
<>	134:ad3be0349dc5	3770	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3771	{
<>	134:ad3be0349dc5	3772	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
<>	134:ad3be0349dc5	3773	}
<>	134:ad3be0349dc5	3774
<>	134:ad3be0349dc5	3775	/**
<>	134:ad3be0349dc5	3776	* @brief Generate Capture/Compare 3 event.
<>	134:ad3be0349dc5	3777	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
<>	134:ad3be0349dc5	3778	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3779	* @retval None
<>	134:ad3be0349dc5	3780	*/
<>	134:ad3be0349dc5	3781	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3782	{
<>	134:ad3be0349dc5	3783	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
<>	134:ad3be0349dc5	3784	}
<>	134:ad3be0349dc5	3785
<>	134:ad3be0349dc5	3786	/**
<>	134:ad3be0349dc5	3787	* @brief Generate Capture/Compare 4 event.
<>	134:ad3be0349dc5	3788	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
<>	134:ad3be0349dc5	3789	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3790	* @retval None
<>	134:ad3be0349dc5	3791	*/
<>	134:ad3be0349dc5	3792	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3793	{
<>	134:ad3be0349dc5	3794	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
<>	134:ad3be0349dc5	3795	}
<>	134:ad3be0349dc5	3796
<>	134:ad3be0349dc5	3797	/**
<>	134:ad3be0349dc5	3798	* @brief Generate commutation event.
<>	134:ad3be0349dc5	3799	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
<>	134:ad3be0349dc5	3800	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3801	* @retval None
<>	134:ad3be0349dc5	3802	*/
<>	134:ad3be0349dc5	3803	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3804	{
<>	134:ad3be0349dc5	3805	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
<>	134:ad3be0349dc5	3806	}
<>	134:ad3be0349dc5	3807
<>	134:ad3be0349dc5	3808	/**
<>	134:ad3be0349dc5	3809	* @brief Generate trigger event.
<>	134:ad3be0349dc5	3810	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
<>	134:ad3be0349dc5	3811	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3812	* @retval None
<>	134:ad3be0349dc5	3813	*/
<>	134:ad3be0349dc5	3814	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3815	{
<>	134:ad3be0349dc5	3816	SET_BIT(TIMx->EGR, TIM_EGR_TG);
<>	134:ad3be0349dc5	3817	}
<>	134:ad3be0349dc5	3818
<>	134:ad3be0349dc5	3819	/**
<>	134:ad3be0349dc5	3820	* @brief Generate break event.
<>	134:ad3be0349dc5	3821	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
<>	134:ad3be0349dc5	3822	* @param TIMx Timer instance
<>	134:ad3be0349dc5	3823	* @retval None
<>	134:ad3be0349dc5	3824	*/
<>	134:ad3be0349dc5	3825	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
<>	134:ad3be0349dc5	3826	{
<>	134:ad3be0349dc5	3827	SET_BIT(TIMx->EGR, TIM_EGR_BG);
<>	134:ad3be0349dc5	3828	}
<>	134:ad3be0349dc5	3829
<>	134:ad3be0349dc5	3830	/**
<>	134:ad3be0349dc5	3831	* @}
<>	134:ad3be0349dc5	3832	*/
<>	134:ad3be0349dc5	3833
<>	134:ad3be0349dc5	3834	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	3835	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
<>	134:ad3be0349dc5	3836	* @{
<>	134:ad3be0349dc5	3837	*/
<>	134:ad3be0349dc5	3838
<>	134:ad3be0349dc5	3839	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
<>	134:ad3be0349dc5	3840	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
<>	134:ad3be0349dc5	3841	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
<>	134:ad3be0349dc5	3842	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
<>	134:ad3be0349dc5	3843	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
<>	134:ad3be0349dc5	3844	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
<>	134:ad3be0349dc5	3845	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
<>	134:ad3be0349dc5	3846	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
<>	134:ad3be0349dc5	3847	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
<>	134:ad3be0349dc5	3848	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
<>	134:ad3be0349dc5	3849	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
<>	134:ad3be0349dc5	3850	/**
<>	134:ad3be0349dc5	3851	* @}
<>	134:ad3be0349dc5	3852	*/
<>	134:ad3be0349dc5	3853	#endif /* USE_FULL_LL_DRIVER */
<>	134:ad3be0349dc5	3854
<>	134:ad3be0349dc5	3855	/**
<>	134:ad3be0349dc5	3856	* @}
<>	134:ad3be0349dc5	3857	*/
<>	134:ad3be0349dc5	3858
<>	134:ad3be0349dc5	3859	/**
<>	134:ad3be0349dc5	3860	* @}
<>	134:ad3be0349dc5	3861	*/
<>	134:ad3be0349dc5	3862
<>	134:ad3be0349dc5	3863	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM6 \|\| TIM7 */
<>	134:ad3be0349dc5	3864
<>	134:ad3be0349dc5	3865	/**
<>	134:ad3be0349dc5	3866	* @}
<>	134:ad3be0349dc5	3867	*/
<>	134:ad3be0349dc5	3868
<>	134:ad3be0349dc5	3869	#ifdef __cplusplus
<>	134:ad3be0349dc5	3870	}
<>	134:ad3be0349dc5	3871	#endif
<>	134:ad3be0349dc5	3872
<>	134:ad3be0349dc5	3873	#endif /* __STM32F0xx_LL_TIM_H */
<>	134:ad3be0349dc5	3874
<>	134:ad3be0349dc5	3875	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/