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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_system.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Parent:: 134:ad3be0349dc5
Child:: 160:5571c4ff569f

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	134:ad3be0349dc5	1	/**
<>	134:ad3be0349dc5	2	******************************************************************************
<>	134:ad3be0349dc5	3	* @file stm32f0xx_ll_system.h
<>	134:ad3be0349dc5	4	* @author MCD Application Team
<>	134:ad3be0349dc5	5	* @version V1.4.0
<>	134:ad3be0349dc5	6	* @date 27-May-2016
<>	134:ad3be0349dc5	7	* @brief Header file of SYSTEM LL module.
<>	134:ad3be0349dc5	8	@verbatim
<>	134:ad3be0349dc5	9	==============================================================================
<>	134:ad3be0349dc5	10	##### How to use this driver #####
<>	134:ad3be0349dc5	11	==============================================================================
<>	134:ad3be0349dc5	12	[..]
<>	134:ad3be0349dc5	13	The LL SYSTEM driver contains a set of generic APIs that can be
<>	134:ad3be0349dc5	14	used by user:
<>	134:ad3be0349dc5	15	(+) Some of the FLASH features need to be handled in the SYSTEM file.
<>	134:ad3be0349dc5	16	(+) Access to DBGCMU registers
<>	134:ad3be0349dc5	17	(+) Access to SYSCFG registers
<>	134:ad3be0349dc5	18
<>	134:ad3be0349dc5	19	@endverbatim
<>	134:ad3be0349dc5	20	******************************************************************************
<>	134:ad3be0349dc5	21	* @attention
<>	134:ad3be0349dc5	22	*
<>	134:ad3be0349dc5	23	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	134:ad3be0349dc5	24	*
<>	134:ad3be0349dc5	25	* Redistribution and use in source and binary forms, with or without modification,
<>	134:ad3be0349dc5	26	* are permitted provided that the following conditions are met:
<>	134:ad3be0349dc5	27	* 1. Redistributions of source code must retain the above copyright notice,
<>	134:ad3be0349dc5	28	* this list of conditions and the following disclaimer.
<>	134:ad3be0349dc5	29	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	134:ad3be0349dc5	30	* this list of conditions and the following disclaimer in the documentation
<>	134:ad3be0349dc5	31	* and/or other materials provided with the distribution.
<>	134:ad3be0349dc5	32	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	134:ad3be0349dc5	33	* may be used to endorse or promote products derived from this software
<>	134:ad3be0349dc5	34	* without specific prior written permission.
<>	134:ad3be0349dc5	35	*
<>	134:ad3be0349dc5	36	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	134:ad3be0349dc5	37	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	134:ad3be0349dc5	38	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	134:ad3be0349dc5	39	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	134:ad3be0349dc5	40	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	134:ad3be0349dc5	41	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	134:ad3be0349dc5	42	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	134:ad3be0349dc5	43	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	134:ad3be0349dc5	44	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	134:ad3be0349dc5	45	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	134:ad3be0349dc5	46	*
<>	134:ad3be0349dc5	47	******************************************************************************
<>	134:ad3be0349dc5	48	*/
<>	134:ad3be0349dc5	49
<>	134:ad3be0349dc5	50	/* Define to prevent recursive inclusion -------------------------------------*/
<>	134:ad3be0349dc5	51	#ifndef __STM32F0xx_LL_SYSTEM_H
<>	134:ad3be0349dc5	52	#define __STM32F0xx_LL_SYSTEM_H
<>	134:ad3be0349dc5	53
<>	134:ad3be0349dc5	54	#ifdef __cplusplus
<>	134:ad3be0349dc5	55	extern "C" {
<>	134:ad3be0349dc5	56	#endif
<>	134:ad3be0349dc5	57
<>	134:ad3be0349dc5	58	/* Includes ------------------------------------------------------------------*/
<>	134:ad3be0349dc5	59	#include "stm32f0xx.h"
<>	134:ad3be0349dc5	60
<>	134:ad3be0349dc5	61	/** @addtogroup STM32F0xx_LL_Driver
<>	134:ad3be0349dc5	62	* @{
<>	134:ad3be0349dc5	63	*/
<>	134:ad3be0349dc5	64
<>	134:ad3be0349dc5	65	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU)
<>	134:ad3be0349dc5	66
<>	134:ad3be0349dc5	67	/** @defgroup SYSTEM_LL SYSTEM
<>	134:ad3be0349dc5	68	* @{
<>	134:ad3be0349dc5	69	*/
<>	134:ad3be0349dc5	70
<>	134:ad3be0349dc5	71	/* Private types -------------------------------------------------------------*/
<>	134:ad3be0349dc5	72	/* Private variables ---------------------------------------------------------*/
<>	134:ad3be0349dc5	73
<>	134:ad3be0349dc5	74	/* Private constants ---------------------------------------------------------*/
<>	134:ad3be0349dc5	75	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
<>	134:ad3be0349dc5	76	* @{
<>	134:ad3be0349dc5	77	*/
<>	134:ad3be0349dc5	78
<>	134:ad3be0349dc5	79	/* Defines used for position in the register */
<>	134:ad3be0349dc5	80	#define DBGMCU_REVID_POSITION (uint32_t)16U
<>	134:ad3be0349dc5	81
<>	134:ad3be0349dc5	82	/**
<>	134:ad3be0349dc5	83	* @}
<>	134:ad3be0349dc5	84	*/
<>	134:ad3be0349dc5	85
<>	134:ad3be0349dc5	86	/* Private macros ------------------------------------------------------------*/
<>	134:ad3be0349dc5	87
<>	134:ad3be0349dc5	88	/* Exported types ------------------------------------------------------------*/
<>	134:ad3be0349dc5	89	/* Exported constants --------------------------------------------------------*/
<>	134:ad3be0349dc5	90	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
<>	134:ad3be0349dc5	91	* @{
<>	134:ad3be0349dc5	92	*/
<>	134:ad3be0349dc5	93
<>	134:ad3be0349dc5	94	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Remap
<>	134:ad3be0349dc5	95	* @{
<>	134:ad3be0349dc5	96	*/
<>	134:ad3be0349dc5	97	#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /!< Main Flash memory mapped at 0x00000000 /
<>	134:ad3be0349dc5	98	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
<>	134:ad3be0349dc5	99	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 \| SYSCFG_CFGR1_MEM_MODE_0) /!< Embedded SRAM mapped at 0x00000000 /
<>	134:ad3be0349dc5	100	/**
<>	134:ad3be0349dc5	101	* @}
<>	134:ad3be0349dc5	102	*/
<>	134:ad3be0349dc5	103
<>	134:ad3be0349dc5	104	#if defined(SYSCFG_CFGR1_IR_MOD)
<>	134:ad3be0349dc5	105	/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation
<>	134:ad3be0349dc5	106	* @{
<>	134:ad3be0349dc5	107	*/
<>	134:ad3be0349dc5	108	#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /!< Timer16 is selected as IR Modulation enveloppe source /
<>	134:ad3be0349dc5	109	#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /!< USART1 is selected as IR Modulation enveloppe source /
<>	134:ad3be0349dc5	110	#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /!< USART4 is selected as IR Modulation enveloppe source /
<>	134:ad3be0349dc5	111	/**
<>	134:ad3be0349dc5	112	* @}
<>	134:ad3be0349dc5	113	*/
<>	134:ad3be0349dc5	114
<>	134:ad3be0349dc5	115	#endif /* SYSCFG_CFGR1_IR_MOD */
<>	134:ad3be0349dc5	116
<>	134:ad3be0349dc5	117	#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART3_DMA_RMP)
<>	134:ad3be0349dc5	118	/** @defgroup SYSTEM_LL_EC_USART1TX_RMP SYSCFG USART DMA Remap
<>	134:ad3be0349dc5	119	* @{
<>	134:ad3be0349dc5	120	*/
<>	134:ad3be0349dc5	121	#if defined (SYSCFG_CFGR1_USART1TX_DMA_RMP)
<>	134:ad3be0349dc5	122	#define LL_SYSCFG_USART1TX_RMP_DMA1CH2 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART1_TX DMA request mapped on DMA channel 2U /
<>	134:ad3be0349dc5	123	#define LL_SYSCFG_USART1TX_RMP_DMA1CH4 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART1TX_DMA_RMP) /!< USART1_TX DMA request mapped on DMA channel 4U /
<>	134:ad3be0349dc5	124	#endif /SYSCFG_CFGR1_USART1TX_DMA_RMP/
<>	134:ad3be0349dc5	125	#if defined (SYSCFG_CFGR1_USART1RX_DMA_RMP)
<>	134:ad3be0349dc5	126	#define LL_SYSCFG_USART1RX_RMP_DMA1CH3 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART1_RX DMA request mapped on DMA channel 3U /
<>	134:ad3be0349dc5	127	#define LL_SYSCFG_USART1RX_RMP_DMA1CH5 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART1RX_DMA_RMP) /!< USART1_RX DMA request mapped on DMA channel 5 /
<>	134:ad3be0349dc5	128	#endif /SYSCFG_CFGR1_USART1RX_DMA_RMP/
<>	134:ad3be0349dc5	129	#if defined (SYSCFG_CFGR1_USART2_DMA_RMP)
<>	134:ad3be0349dc5	130	#define LL_SYSCFG_USART2_RMP_DMA1CH54 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4U respectively /
<>	134:ad3be0349dc5	131	#define LL_SYSCFG_USART2_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART2_DMA_RMP) /!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively /
<>	134:ad3be0349dc5	132	#endif /SYSCFG_CFGR1_USART2_DMA_RMP/
<>	134:ad3be0349dc5	133	#if defined (SYSCFG_CFGR1_USART3_DMA_RMP)
<>	134:ad3be0349dc5	134	#define LL_SYSCFG_USART3_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively /
<>	134:ad3be0349dc5	135	#define LL_SYSCFG_USART3_RMP_DMA1CH32 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART3_DMA_RMP) /!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 3U and 2U respectively /
<>	134:ad3be0349dc5	136	#endif /* SYSCFG_CFGR1_USART3_DMA_RMP */
<>	134:ad3be0349dc5	137	/**
<>	134:ad3be0349dc5	138	* @}
<>	134:ad3be0349dc5	139	*/
<>	134:ad3be0349dc5	140	#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP \|\| SYSCFG_CFGR1_USART1RX_DMA_RMP \|\| SYSCFG_CFGR1_USART2_DMA_RMP \|\| SYSCFG_CFGR1_USART3_DMA_RMP */
<>	134:ad3be0349dc5	141
<>	134:ad3be0349dc5	142	#if defined (SYSCFG_CFGR1_SPI2_DMA_RMP)
<>	134:ad3be0349dc5	143	/** @defgroup SYSTEM_LL_EC_SPI2_RMP_DMA1 SYSCFG SPI2 DMA Remap
<>	134:ad3be0349dc5	144	* @{
<>	134:ad3be0349dc5	145	*/
<>	134:ad3be0349dc5	146	#define LL_SYSCFG_SPI2_RMP_DMA1_CH45 (uint32_t)0x00000000U /!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4U and 5 respectively /
<>	134:ad3be0349dc5	147	#define LL_SYSCFG_SPI2_RMP_DMA1_CH67 SYSCFG_CFGR1_SPI2_DMA_RMP /!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively /
<>	134:ad3be0349dc5	148	/**
<>	134:ad3be0349dc5	149	* @}
<>	134:ad3be0349dc5	150	*/
<>	134:ad3be0349dc5	151
<>	134:ad3be0349dc5	152	#endif /SYSCFG_CFGR1_SPI2_DMA_RMP/
<>	134:ad3be0349dc5	153
<>	134:ad3be0349dc5	154	#if defined (SYSCFG_CFGR1_I2C1_DMA_RMP)
<>	134:ad3be0349dc5	155	/** @defgroup SYSTEM_LL_EC_I2C1_RMP_DMA1 SYSCFG I2C1 DMA Remap
<>	134:ad3be0349dc5	156	* @{
<>	134:ad3be0349dc5	157	*/
<>	134:ad3be0349dc5	158	#define LL_SYSCFG_I2C1_RMP_DMA1_CH32 (uint32_t)0x00000000U /!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3U and 2U respectively /
<>	134:ad3be0349dc5	159	#define LL_SYSCFG_I2C1_RMP_DMA1_CH76 SYSCFG_CFGR1_I2C1_DMA_RMP /!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively /
<>	134:ad3be0349dc5	160	/**
<>	134:ad3be0349dc5	161	* @}
<>	134:ad3be0349dc5	162	*/
<>	134:ad3be0349dc5	163
<>	134:ad3be0349dc5	164	#endif /SYSCFG_CFGR1_I2C1_DMA_RMP/
<>	134:ad3be0349dc5	165
<>	134:ad3be0349dc5	166	#if defined(SYSCFG_CFGR1_ADC_DMA_RMP)
<>	134:ad3be0349dc5	167	/** @defgroup SYSTEM_LL_EC_ADC1_RMP_DMA1 SYSCFG ADC1 DMA Remap
<>	134:ad3be0349dc5	168	* @{
<>	134:ad3be0349dc5	169	*/
<>	134:ad3be0349dc5	170	#define LL_SYSCFG_ADC1_RMP_DMA1_CH1 (uint32_t)0x00000000U /!< ADC DMA request mapped on DMA channel 1U /
<>	134:ad3be0349dc5	171	#define LL_SYSCFG_ADC1_RMP_DMA1_CH2 SYSCFG_CFGR1_ADC_DMA_RMP /!< ADC DMA request mapped on DMA channel 2U /
<>	134:ad3be0349dc5	172	/**
<>	134:ad3be0349dc5	173	* @}
<>	134:ad3be0349dc5	174	*/
<>	134:ad3be0349dc5	175
<>	134:ad3be0349dc5	176	#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */
<>	134:ad3be0349dc5	177
<>	134:ad3be0349dc5	178	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM17_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM1_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM3_DMA_RMP)
<>	134:ad3be0349dc5	179	/** @defgroup SYSTEM_LL_EC_TIM16_RMP_DMA1 SYSCFG TIM DMA Remap
<>	134:ad3be0349dc5	180	* @{
<>	134:ad3be0349dc5	181	*/
<>	134:ad3be0349dc5	182	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP)
<>	134:ad3be0349dc5	183	#if defined (SYSCFG_CFGR1_TIM16_DMA_RMP2)
<>	134:ad3be0349dc5	184	#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 (((SYSCFG_CFGR1_TIM16_DMA_RMP \| SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) \| (uint32_t)0x00000000U) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 /
<>	134:ad3be0349dc5	185	#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 (((SYSCFG_CFGR1_TIM16_DMA_RMP \| SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 /
<>	134:ad3be0349dc5	186	#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP2 >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP2) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6 /
<>	134:ad3be0349dc5	187	#else
<>	134:ad3be0349dc5	188	#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 /
<>	134:ad3be0349dc5	189	#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 /
<>	134:ad3be0349dc5	190	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP2 */
<>	134:ad3be0349dc5	191	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP */
<>	134:ad3be0349dc5	192	#if defined(SYSCFG_CFGR1_TIM17_DMA_RMP)
<>	134:ad3be0349dc5	193	#if defined (SYSCFG_CFGR1_TIM17_DMA_RMP2)
<>	134:ad3be0349dc5	194	#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 (((SYSCFG_CFGR1_TIM17_DMA_RMP \| SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) \| (uint32_t)0x00000000U) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 /
<>	134:ad3be0349dc5	195	#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 (((SYSCFG_CFGR1_TIM17_DMA_RMP \| SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 /
<>	134:ad3be0349dc5	196	#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP2 >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP2) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7 /
<>	134:ad3be0349dc5	197	#else
<>	134:ad3be0349dc5	198	#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 /
<>	134:ad3be0349dc5	199	#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 /
<>	134:ad3be0349dc5	200	#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP2 */
<>	134:ad3be0349dc5	201	#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP */
<>	134:ad3be0349dc5	202	#if defined (SYSCFG_CFGR1_TIM1_DMA_RMP)
<>	134:ad3be0349dc5	203	#define LL_SYSCFG_TIM1_RMP_DMA1_CH234 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMAchannel 2, 3 and 4 respectively /
<>	134:ad3be0349dc5	204	#define LL_SYSCFG_TIM1_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM1_DMA_RMP) /!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 /
<>	134:ad3be0349dc5	205	#endif /SYSCFG_CFGR1_TIM1_DMA_RMP/
<>	134:ad3be0349dc5	206	#if defined (SYSCFG_CFGR1_TIM2_DMA_RMP)
<>	134:ad3be0349dc5	207	#define LL_SYSCFG_TIM2_RMP_DMA1_CH34 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively /
<>	134:ad3be0349dc5	208	#define LL_SYSCFG_TIM2_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM2_DMA_RMP) /!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 /
<>	134:ad3be0349dc5	209	#endif /SYSCFG_CFGR1_TIM2_DMA_RMP/
<>	134:ad3be0349dc5	210	#if defined (SYSCFG_CFGR1_TIM3_DMA_RMP)
<>	134:ad3be0349dc5	211	#define LL_SYSCFG_TIM3_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 /
<>	134:ad3be0349dc5	212	#define LL_SYSCFG_TIM3_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM3_DMA_RMP) /!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 /
<>	134:ad3be0349dc5	213	#endif /SYSCFG_CFGR1_TIM3_DMA_RMP/
<>	134:ad3be0349dc5	214	/**
<>	134:ad3be0349dc5	215	* @}
<>	134:ad3be0349dc5	216	*/
<>	134:ad3be0349dc5	217
<>	134:ad3be0349dc5	218	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP \|\| SYSCFG_CFGR1_TIM17_DMA_RMP \|\| SYSCFG_CFGR1_TIM1_DMA_RMP \|\| SYSCFG_CFGR1_TIM2_DMA_RMP \|\| SYSCFG_CFGR1_TIM3_DMA_RMP */
<>	134:ad3be0349dc5	219
<>	134:ad3be0349dc5	220	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
<>	134:ad3be0349dc5	221	* @{
<>	134:ad3be0349dc5	222	*/
<>	134:ad3be0349dc5	223	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /!< I2C PB6 Fast mode plus /
<>	134:ad3be0349dc5	224	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /!< I2C PB7 Fast mode plus /
<>	134:ad3be0349dc5	225	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /!< I2C PB8 Fast mode plus /
<>	134:ad3be0349dc5	226	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /!< I2C PB9 Fast mode plus /
<>	134:ad3be0349dc5	227	#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1)
<>	134:ad3be0349dc5	228	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 /
<>	134:ad3be0349dc5	229	#endif /SYSCFG_CFGR1_I2C_FMP_I2C1/
<>	134:ad3be0349dc5	230	#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2)
<>	134:ad3be0349dc5	231	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /!< Enable I2C2 Fast mode plus /
<>	134:ad3be0349dc5	232	#endif /SYSCFG_CFGR1_I2C_FMP_I2C2/
<>	134:ad3be0349dc5	233	#if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
<>	134:ad3be0349dc5	234	#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /!< Enable Fast Mode Plus on PA9 /
<>	134:ad3be0349dc5	235	#endif /SYSCFG_CFGR1_I2C_FMP_PA9/
<>	134:ad3be0349dc5	236	#if defined(SYSCFG_CFGR1_I2C_FMP_PA10)
<>	134:ad3be0349dc5	237	#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /!< Enable Fast Mode Plus on PA10 /
<>	134:ad3be0349dc5	238	#endif /SYSCFG_CFGR1_I2C_FMP_PA10/
<>	134:ad3be0349dc5	239	/**
<>	134:ad3be0349dc5	240	* @}
<>	134:ad3be0349dc5	241	*/
<>	134:ad3be0349dc5	242
<>	134:ad3be0349dc5	243	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
<>	134:ad3be0349dc5	244	* @{
<>	134:ad3be0349dc5	245	*/
<>	134:ad3be0349dc5	246	#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /!< EXTI PORT A /
<>	134:ad3be0349dc5	247	#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /!< EXTI PORT B /
<>	134:ad3be0349dc5	248	#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /!< EXTI PORT C /
<>	134:ad3be0349dc5	249	#if defined(GPIOD_BASE)
<>	134:ad3be0349dc5	250	#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /!< EXTI PORT D /
<>	134:ad3be0349dc5	251	#endif /GPIOD_BASE/
<>	134:ad3be0349dc5	252	#if defined(GPIOE_BASE)
<>	134:ad3be0349dc5	253	#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /!< EXTI PORT E /
<>	134:ad3be0349dc5	254	#endif /GPIOE_BASE/
<>	134:ad3be0349dc5	255	#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /!< EXTI PORT F /
<>	134:ad3be0349dc5	256	/**
<>	134:ad3be0349dc5	257	* @}
<>	134:ad3be0349dc5	258	*/
<>	134:ad3be0349dc5	259
<>	134:ad3be0349dc5	260	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
<>	134:ad3be0349dc5	261	* @{
<>	134:ad3be0349dc5	262	*/
<>	134:ad3be0349dc5	263	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U \| 0U) /!< EXTI_POSITION_0 \| EXTICR[0] /
<>	134:ad3be0349dc5	264	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U \| 0U) /!< EXTI_POSITION_4 \| EXTICR[0] /
<>	134:ad3be0349dc5	265	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U \| 0U) /!< EXTI_POSITION_8 \| EXTICR[0] /
<>	134:ad3be0349dc5	266	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U \| 0U) /!< EXTI_POSITION_12 \| EXTICR[0] /
<>	134:ad3be0349dc5	267	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U \| 1U) /!< EXTI_POSITION_0 \| EXTICR[1] /
<>	134:ad3be0349dc5	268	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U \| 1U) /!< EXTI_POSITION_4 \| EXTICR[1] /
<>	134:ad3be0349dc5	269	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U \| 1U) /!< EXTI_POSITION_8 \| EXTICR[1] /
<>	134:ad3be0349dc5	270	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U \| 1U) /!< EXTI_POSITION_12 \| EXTICR[1] /
<>	134:ad3be0349dc5	271	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U \| 2U) /!< EXTI_POSITION_0 \| EXTICR[2] /
<>	134:ad3be0349dc5	272	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U \| 2U) /!< EXTI_POSITION_4 \| EXTICR[2] /
<>	134:ad3be0349dc5	273	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U \| 2U) /!< EXTI_POSITION_8 \| EXTICR[2] /
<>	134:ad3be0349dc5	274	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U \| 2U) /!< EXTI_POSITION_12 \| EXTICR[2] /
<>	134:ad3be0349dc5	275	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U \| 3U) /!< EXTI_POSITION_0 \| EXTICR[3] /
<>	134:ad3be0349dc5	276	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U \| 3U) /!< EXTI_POSITION_4 \| EXTICR[3] /
<>	134:ad3be0349dc5	277	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U \| 3U) /!< EXTI_POSITION_8 \| EXTICR[3] /
<>	134:ad3be0349dc5	278	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U \| 3U) /!< EXTI_POSITION_12 \| EXTICR[3] /
<>	134:ad3be0349dc5	279	/**
<>	134:ad3be0349dc5	280	* @}
<>	134:ad3be0349dc5	281	*/
<>	134:ad3be0349dc5	282
<>	134:ad3be0349dc5	283	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
<>	134:ad3be0349dc5	284	* @{
<>	134:ad3be0349dc5	285	*/
<>	134:ad3be0349dc5	286	#if defined(SYSCFG_CFGR2_PVD_LOCK)
<>	134:ad3be0349dc5	287	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection
<>	134:ad3be0349dc5	288	with TIM1/15/16U/17 Break Input and also
<>	134:ad3be0349dc5	289	the PVDE and PLS bits of the Power Control Interface */
<>	134:ad3be0349dc5	290	#endif /SYSCFG_CFGR2_PVD_LOCK/
<>	134:ad3be0349dc5	291	#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal
<>	134:ad3be0349dc5	292	with Break Input of TIM1/15/16/17 */
<>	134:ad3be0349dc5	293	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of
<>	134:ad3be0349dc5	294	CortexM0 with Break Input of TIM1/15/16/17 */
<>	134:ad3be0349dc5	295	/**
<>	134:ad3be0349dc5	296	* @}
<>	134:ad3be0349dc5	297	*/
<>	134:ad3be0349dc5	298
<>	134:ad3be0349dc5	299	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
<>	134:ad3be0349dc5	300	* @{
<>	134:ad3be0349dc5	301	*/
<>	134:ad3be0349dc5	302	#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<>	134:ad3be0349dc5	303	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /!< TIM2 counter stopped when core is halted /
<>	134:ad3be0349dc5	304	#endif /DBGMCU_APB1_FZ_DBG_TIM2_STOP/
<>	134:ad3be0349dc5	305	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /!< TIM3 counter stopped when core is halted /
<>	134:ad3be0349dc5	306	#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<>	134:ad3be0349dc5	307	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /!< TIM6 counter stopped when core is halted /
<>	134:ad3be0349dc5	308	#endif /DBGMCU_APB1_FZ_DBG_TIM6_STOP/
<>	134:ad3be0349dc5	309	#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<>	134:ad3be0349dc5	310	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /!< TIM7 counter stopped when core is halted /
<>	134:ad3be0349dc5	311	#endif /DBGMCU_APB1_FZ_DBG_TIM7_STOP/
<>	134:ad3be0349dc5	312	#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /!< TIM14 counter stopped when core is halted /
<>	134:ad3be0349dc5	313	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /!< RTC Calendar frozen when core is halted /
<>	134:ad3be0349dc5	314	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /!< Debug Window Watchdog stopped when Core is halted /
<>	134:ad3be0349dc5	315	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /!< Debug Independent Watchdog stopped when Core is halted /
<>	134:ad3be0349dc5	316	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /!< I2C1 SMBUS timeout mode stopped when Core is halted /
<>	134:ad3be0349dc5	317	#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
<>	134:ad3be0349dc5	318	#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /!< CAN debug stopped when Core is halted /
<>	134:ad3be0349dc5	319	#endif /DBGMCU_APB1_FZ_DBG_CAN_STOP/
<>	134:ad3be0349dc5	320	/**
<>	134:ad3be0349dc5	321	* @}
<>	134:ad3be0349dc5	322	*/
<>	134:ad3be0349dc5	323
<>	134:ad3be0349dc5	324	/** @defgroup SYSTEM_LL_EC_APB1 GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
<>	134:ad3be0349dc5	325	* @{
<>	134:ad3be0349dc5	326	*/
<>	134:ad3be0349dc5	327	#define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /!< TIM1 counter stopped when core is halted /
<>	134:ad3be0349dc5	328	#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
<>	134:ad3be0349dc5	329	#define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /!< TIM15 counter stopped when core is halted /
<>	134:ad3be0349dc5	330	#endif /DBGMCU_APB2_FZ_DBG_TIM15_STOP/
<>	134:ad3be0349dc5	331	#define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /!< TIM16 counter stopped when core is halted /
<>	134:ad3be0349dc5	332	#define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /!< TIM17 counter stopped when core is halted /
<>	134:ad3be0349dc5	333	/**
<>	134:ad3be0349dc5	334	* @}
<>	134:ad3be0349dc5	335	*/
<>	134:ad3be0349dc5	336
<>	134:ad3be0349dc5	337	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
<>	134:ad3be0349dc5	338	* @{
<>	134:ad3be0349dc5	339	*/
<>	134:ad3be0349dc5	340	#define LL_FLASH_LATENCY_0 ((uint32_t)0x00000000U) /!< FLASH Zero Latency cycle /
<>	134:ad3be0349dc5	341	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /!< FLASH One Latency cycle /
<>	134:ad3be0349dc5	342	/**
<>	134:ad3be0349dc5	343	* @}
<>	134:ad3be0349dc5	344	*/
<>	134:ad3be0349dc5	345
<>	134:ad3be0349dc5	346	/**
<>	134:ad3be0349dc5	347	* @}
<>	134:ad3be0349dc5	348	*/
<>	134:ad3be0349dc5	349
<>	134:ad3be0349dc5	350	/* Exported macro ------------------------------------------------------------*/
<>	134:ad3be0349dc5	351
<>	134:ad3be0349dc5	352	/* Exported functions --------------------------------------------------------*/
<>	134:ad3be0349dc5	353	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
<>	134:ad3be0349dc5	354	* @{
<>	134:ad3be0349dc5	355	*/
<>	134:ad3be0349dc5	356
<>	134:ad3be0349dc5	357	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
<>	134:ad3be0349dc5	358	* @{
<>	134:ad3be0349dc5	359	*/
<>	134:ad3be0349dc5	360
<>	134:ad3be0349dc5	361	/**
<>	134:ad3be0349dc5	362	* @brief Set memory mapping at address 0x00000000
<>	134:ad3be0349dc5	363	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
<>	134:ad3be0349dc5	364	* @param Memory This parameter can be one of the following values:
<>	134:ad3be0349dc5	365	* @arg @ref LL_SYSCFG_REMAP_FLASH
<>	134:ad3be0349dc5	366	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
<>	134:ad3be0349dc5	367	* @arg @ref LL_SYSCFG_REMAP_SRAM
<>	134:ad3be0349dc5	368	* @retval None
<>	134:ad3be0349dc5	369	*/
<>	134:ad3be0349dc5	370	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
<>	134:ad3be0349dc5	371	{
<>	134:ad3be0349dc5	372	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
<>	134:ad3be0349dc5	373	}
<>	134:ad3be0349dc5	374
<>	134:ad3be0349dc5	375	/**
<>	134:ad3be0349dc5	376	* @brief Get memory mapping at address 0x00000000
<>	134:ad3be0349dc5	377	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
<>	134:ad3be0349dc5	378	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	379	* @arg @ref LL_SYSCFG_REMAP_FLASH
<>	134:ad3be0349dc5	380	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
<>	134:ad3be0349dc5	381	* @arg @ref LL_SYSCFG_REMAP_SRAM
<>	134:ad3be0349dc5	382	*/
<>	134:ad3be0349dc5	383	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
<>	134:ad3be0349dc5	384	{
<>	134:ad3be0349dc5	385	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
<>	134:ad3be0349dc5	386	}
<>	134:ad3be0349dc5	387
<>	134:ad3be0349dc5	388	#if defined(SYSCFG_CFGR1_IR_MOD)
<>	134:ad3be0349dc5	389	/**
<>	134:ad3be0349dc5	390	* @brief Set IR Modulation Envelope signal source.
<>	134:ad3be0349dc5	391	* @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal
<>	134:ad3be0349dc5	392	* @param Source This parameter can be one of the following values:
<>	134:ad3be0349dc5	393	* @arg @ref LL_SYSCFG_IR_MOD_TIM16
<>	134:ad3be0349dc5	394	* @arg @ref LL_SYSCFG_IR_MOD_USART1
<>	134:ad3be0349dc5	395	* @arg @ref LL_SYSCFG_IR_MOD_USART4
<>	134:ad3be0349dc5	396	* @retval None
<>	134:ad3be0349dc5	397	*/
<>	134:ad3be0349dc5	398	__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)
<>	134:ad3be0349dc5	399	{
<>	134:ad3be0349dc5	400	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source);
<>	134:ad3be0349dc5	401	}
<>	134:ad3be0349dc5	402
<>	134:ad3be0349dc5	403	/**
<>	134:ad3be0349dc5	404	* @brief Get IR Modulation Envelope signal source.
<>	134:ad3be0349dc5	405	* @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal
<>	134:ad3be0349dc5	406	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	407	* @arg @ref LL_SYSCFG_IR_MOD_TIM16
<>	134:ad3be0349dc5	408	* @arg @ref LL_SYSCFG_IR_MOD_USART1
<>	134:ad3be0349dc5	409	* @arg @ref LL_SYSCFG_IR_MOD_USART4
<>	134:ad3be0349dc5	410	*/
<>	134:ad3be0349dc5	411	__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void)
<>	134:ad3be0349dc5	412	{
<>	134:ad3be0349dc5	413	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD));
<>	134:ad3be0349dc5	414	}
<>	134:ad3be0349dc5	415	#endif /* SYSCFG_CFGR1_IR_MOD */
<>	134:ad3be0349dc5	416
<>	134:ad3be0349dc5	417	#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART3_DMA_RMP)
<>	134:ad3be0349dc5	418	/**
<>	134:ad3be0349dc5	419	* @brief Set DMA request remapping bits for USART
<>	134:ad3be0349dc5	420	* @rmtoll SYSCFG_CFGR1 USART1TX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
<>	134:ad3be0349dc5	421	* SYSCFG_CFGR1 USART1RX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
<>	134:ad3be0349dc5	422	* SYSCFG_CFGR1 USART2_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
<>	134:ad3be0349dc5	423	* SYSCFG_CFGR1 USART3_DMA_RMP LL_SYSCFG_SetRemapDMA_USART
<>	134:ad3be0349dc5	424	* @param Remap This parameter can be one of the following values:
<>	134:ad3be0349dc5	425	* @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH2 (*)
<>	134:ad3be0349dc5	426	* @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH4 (*)
<>	134:ad3be0349dc5	427	* @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH3 (*)
<>	134:ad3be0349dc5	428	* @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH5 (*)
<>	134:ad3be0349dc5	429	* @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH54 (*)
<>	134:ad3be0349dc5	430	* @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH67 (*)
<>	134:ad3be0349dc5	431	* @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH67 (*)
<>	134:ad3be0349dc5	432	* @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH32 (*)
<>	134:ad3be0349dc5	433	*
<>	134:ad3be0349dc5	434	* (*) value not defined in all devices.
<>	134:ad3be0349dc5	435	* @retval None
<>	134:ad3be0349dc5	436	*/
<>	134:ad3be0349dc5	437	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap)
<>	134:ad3be0349dc5	438	{
<>	134:ad3be0349dc5	439	MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U));
<>	134:ad3be0349dc5	440	}
<>	134:ad3be0349dc5	441	#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP \|\| SYSCFG_CFGR1_USART1RX_DMA_RMP \|\| SYSCFG_CFGR1_USART2_DMA_RMP \|\| SYSCFG_CFGR1_USART3_DMA_RMP */
<>	134:ad3be0349dc5	442
<>	134:ad3be0349dc5	443	#if defined(SYSCFG_CFGR1_SPI2_DMA_RMP)
<>	134:ad3be0349dc5	444	/**
<>	134:ad3be0349dc5	445	* @brief Set DMA request remapping bits for SPI
<>	134:ad3be0349dc5	446	* @rmtoll SYSCFG_CFGR1 SPI2_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
<>	134:ad3be0349dc5	447	* @param Remap This parameter can be one of the following values:
<>	134:ad3be0349dc5	448	* @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH45
<>	134:ad3be0349dc5	449	* @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH67
<>	134:ad3be0349dc5	450	* @retval None
<>	134:ad3be0349dc5	451	*/
<>	134:ad3be0349dc5	452	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
<>	134:ad3be0349dc5	453	{
<>	134:ad3be0349dc5	454	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_SPI2_DMA_RMP, Remap);
<>	134:ad3be0349dc5	455	}
<>	134:ad3be0349dc5	456	#endif /* SYSCFG_CFGR1_SPI2_DMA_RMP */
<>	134:ad3be0349dc5	457
<>	134:ad3be0349dc5	458	#if defined(SYSCFG_CFGR1_I2C1_DMA_RMP)
<>	134:ad3be0349dc5	459	/**
<>	134:ad3be0349dc5	460	* @brief Set DMA request remapping bits for I2C
<>	134:ad3be0349dc5	461	* @rmtoll SYSCFG_CFGR1 I2C1_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
<>	134:ad3be0349dc5	462	* @param Remap This parameter can be one of the following values:
<>	134:ad3be0349dc5	463	* @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH32
<>	134:ad3be0349dc5	464	* @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH76
<>	134:ad3be0349dc5	465	* @retval None
<>	134:ad3be0349dc5	466	*/
<>	134:ad3be0349dc5	467	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
<>	134:ad3be0349dc5	468	{
<>	134:ad3be0349dc5	469	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_I2C1_DMA_RMP, Remap);
<>	134:ad3be0349dc5	470	}
<>	134:ad3be0349dc5	471	#endif /* SYSCFG_CFGR1_I2C1_DMA_RMP */
<>	134:ad3be0349dc5	472
<>	134:ad3be0349dc5	473	#if defined(SYSCFG_CFGR1_ADC_DMA_RMP)
<>	134:ad3be0349dc5	474	/**
<>	134:ad3be0349dc5	475	* @brief Set DMA request remapping bits for ADC
<>	134:ad3be0349dc5	476	* @rmtoll SYSCFG_CFGR1 ADC_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
<>	134:ad3be0349dc5	477	* @param Remap This parameter can be one of the following values:
<>	134:ad3be0349dc5	478	* @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH1
<>	134:ad3be0349dc5	479	* @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH2
<>	134:ad3be0349dc5	480	* @retval None
<>	134:ad3be0349dc5	481	*/
<>	134:ad3be0349dc5	482	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
<>	134:ad3be0349dc5	483	{
<>	134:ad3be0349dc5	484	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ADC_DMA_RMP, Remap);
<>	134:ad3be0349dc5	485	}
<>	134:ad3be0349dc5	486	#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */
<>	134:ad3be0349dc5	487
<>	134:ad3be0349dc5	488	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM17_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM1_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM3_DMA_RMP)
<>	134:ad3be0349dc5	489	/**
<>	134:ad3be0349dc5	490	* @brief Set DMA request remapping bits for TIM
<>	134:ad3be0349dc5	491	* @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<>	134:ad3be0349dc5	492	* SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<>	134:ad3be0349dc5	493	* SYSCFG_CFGR1 TIM16_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n
<>	134:ad3be0349dc5	494	* SYSCFG_CFGR1 TIM17_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n
<>	134:ad3be0349dc5	495	* SYSCFG_CFGR1 TIM1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<>	134:ad3be0349dc5	496	* SYSCFG_CFGR1 TIM2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
<>	134:ad3be0349dc5	497	* SYSCFG_CFGR1 TIM3_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
<>	134:ad3be0349dc5	498	* @param Remap This parameter can be one of the following values:
<>	134:ad3be0349dc5	499	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 (*)
<>	134:ad3be0349dc5	500	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH4 (*)
<>	134:ad3be0349dc5	501	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 (*)
<>	134:ad3be0349dc5	502	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 (*)
<>	134:ad3be0349dc5	503	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH2 (*)
<>	134:ad3be0349dc5	504	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 (*)
<>	134:ad3be0349dc5	505	* @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH234 (*)
<>	134:ad3be0349dc5	506	* @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH6 (*)
<>	134:ad3be0349dc5	507	* @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH34 (*)
<>	134:ad3be0349dc5	508	* @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH7 (*)
<>	134:ad3be0349dc5	509	* @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH4 (*)
<>	134:ad3be0349dc5	510	* @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH6 (*)
<>	134:ad3be0349dc5	511	*
<>	134:ad3be0349dc5	512	* (*) value not defined in all devices.
<>	134:ad3be0349dc5	513	* @retval None
<>	134:ad3be0349dc5	514	*/
<>	134:ad3be0349dc5	515	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
<>	134:ad3be0349dc5	516	{
<>	134:ad3be0349dc5	517	MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U));
<>	134:ad3be0349dc5	518	}
<>	134:ad3be0349dc5	519	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP \|\| SYSCFG_CFGR1_TIM17_DMA_RMP \|\| SYSCFG_CFGR1_TIM1_DMA_RMP \|\| SYSCFG_CFGR1_TIM2_DMA_RMP \|\| SYSCFG_CFGR1_TIM3_DMA_RMP */
<>	134:ad3be0349dc5	520
<>	134:ad3be0349dc5	521	#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
<>	134:ad3be0349dc5	522	/**
<>	134:ad3be0349dc5	523	* @brief Enable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either
<>	134:ad3be0349dc5	524	* PA9/10 or PA11/12 pin pair on small pin-count packages)
<>	134:ad3be0349dc5	525	* @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_EnablePinRemap
<>	134:ad3be0349dc5	526	* @retval None
<>	134:ad3be0349dc5	527	*/
<>	134:ad3be0349dc5	528	__STATIC_INLINE void LL_SYSCFG_EnablePinRemap(void)
<>	134:ad3be0349dc5	529	{
<>	134:ad3be0349dc5	530	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP);
<>	134:ad3be0349dc5	531	}
<>	134:ad3be0349dc5	532
<>	134:ad3be0349dc5	533	/**
<>	134:ad3be0349dc5	534	* @brief Disable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either
<>	134:ad3be0349dc5	535	* PA9/10 or PA11/12 pin pair on small pin-count packages)
<>	134:ad3be0349dc5	536	* @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_DisablePinRemap
<>	134:ad3be0349dc5	537	* @retval None
<>	134:ad3be0349dc5	538	*/
<>	134:ad3be0349dc5	539	__STATIC_INLINE void LL_SYSCFG_DisablePinRemap(void)
<>	134:ad3be0349dc5	540	{
<>	134:ad3be0349dc5	541	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP);
<>	134:ad3be0349dc5	542	}
<>	134:ad3be0349dc5	543	#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
<>	134:ad3be0349dc5	544
<>	134:ad3be0349dc5	545	/**
<>	134:ad3be0349dc5	546	* @brief Enable the I2C fast mode plus driving capability.
<>	134:ad3be0349dc5	547	* @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n
<>	134:ad3be0349dc5	548	* SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n
<>	134:ad3be0349dc5	549	* SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n
<>	134:ad3be0349dc5	550	* SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n
<>	134:ad3be0349dc5	551	* SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n
<>	134:ad3be0349dc5	552	* SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n
<>	134:ad3be0349dc5	553	* SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n
<>	134:ad3be0349dc5	554	* SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus
<>	134:ad3be0349dc5	555	* @param ConfigFastModePlus This parameter can be a combination of the following values:
<>	134:ad3be0349dc5	556	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
<>	134:ad3be0349dc5	557	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
<>	134:ad3be0349dc5	558	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
<>	134:ad3be0349dc5	559	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
<>	134:ad3be0349dc5	560	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
<>	134:ad3be0349dc5	561	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
<>	134:ad3be0349dc5	562	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
<>	134:ad3be0349dc5	563	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
<>	134:ad3be0349dc5	564	*
<>	134:ad3be0349dc5	565	* (*) value not defined in all devices
<>	134:ad3be0349dc5	566	* @retval None
<>	134:ad3be0349dc5	567	*/
<>	134:ad3be0349dc5	568	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
<>	134:ad3be0349dc5	569	{
<>	134:ad3be0349dc5	570	SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
<>	134:ad3be0349dc5	571	}
<>	134:ad3be0349dc5	572
<>	134:ad3be0349dc5	573	/**
<>	134:ad3be0349dc5	574	* @brief Disable the I2C fast mode plus driving capability.
<>	134:ad3be0349dc5	575	* @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n
<>	134:ad3be0349dc5	576	* SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n
<>	134:ad3be0349dc5	577	* SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n
<>	134:ad3be0349dc5	578	* SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n
<>	134:ad3be0349dc5	579	* SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n
<>	134:ad3be0349dc5	580	* SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n
<>	134:ad3be0349dc5	581	* SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n
<>	134:ad3be0349dc5	582	* SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus
<>	134:ad3be0349dc5	583	* @param ConfigFastModePlus This parameter can be a combination of the following values:
<>	134:ad3be0349dc5	584	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
<>	134:ad3be0349dc5	585	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
<>	134:ad3be0349dc5	586	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
<>	134:ad3be0349dc5	587	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
<>	134:ad3be0349dc5	588	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
<>	134:ad3be0349dc5	589	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
<>	134:ad3be0349dc5	590	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
<>	134:ad3be0349dc5	591	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
<>	134:ad3be0349dc5	592	*
<>	134:ad3be0349dc5	593	* (*) value not defined in all devices
<>	134:ad3be0349dc5	594	* @retval None
<>	134:ad3be0349dc5	595	*/
<>	134:ad3be0349dc5	596	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
<>	134:ad3be0349dc5	597	{
<>	134:ad3be0349dc5	598	CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
<>	134:ad3be0349dc5	599	}
<>	134:ad3be0349dc5	600
<>	134:ad3be0349dc5	601	/**
<>	134:ad3be0349dc5	602	* @brief Configure source input for the EXTI external interrupt.
<>	134:ad3be0349dc5	603	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	604	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	605	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	606	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	607	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	608	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	609	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	610	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	611	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	612	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	613	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	614	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	615	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	616	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	617	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	618	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
<>	134:ad3be0349dc5	619	* @param Port This parameter can be one of the following values:
<>	134:ad3be0349dc5	620	* @arg @ref LL_SYSCFG_EXTI_PORTA
<>	134:ad3be0349dc5	621	* @arg @ref LL_SYSCFG_EXTI_PORTB
<>	134:ad3be0349dc5	622	* @arg @ref LL_SYSCFG_EXTI_PORTC
<>	134:ad3be0349dc5	623	* @arg @ref LL_SYSCFG_EXTI_PORTD (*)
<>	134:ad3be0349dc5	624	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
<>	134:ad3be0349dc5	625	* @arg @ref LL_SYSCFG_EXTI_PORTF
<>	134:ad3be0349dc5	626	*
<>	134:ad3be0349dc5	627	* (*) value not defined in all devices
<>	134:ad3be0349dc5	628	* @param Line This parameter can be one of the following values:
<>	134:ad3be0349dc5	629	* @arg @ref LL_SYSCFG_EXTI_LINE0
<>	134:ad3be0349dc5	630	* @arg @ref LL_SYSCFG_EXTI_LINE1
<>	134:ad3be0349dc5	631	* @arg @ref LL_SYSCFG_EXTI_LINE2
<>	134:ad3be0349dc5	632	* @arg @ref LL_SYSCFG_EXTI_LINE3
<>	134:ad3be0349dc5	633	* @arg @ref LL_SYSCFG_EXTI_LINE4
<>	134:ad3be0349dc5	634	* @arg @ref LL_SYSCFG_EXTI_LINE5
<>	134:ad3be0349dc5	635	* @arg @ref LL_SYSCFG_EXTI_LINE6
<>	134:ad3be0349dc5	636	* @arg @ref LL_SYSCFG_EXTI_LINE7
<>	134:ad3be0349dc5	637	* @arg @ref LL_SYSCFG_EXTI_LINE8
<>	134:ad3be0349dc5	638	* @arg @ref LL_SYSCFG_EXTI_LINE9
<>	134:ad3be0349dc5	639	* @arg @ref LL_SYSCFG_EXTI_LINE10
<>	134:ad3be0349dc5	640	* @arg @ref LL_SYSCFG_EXTI_LINE11
<>	134:ad3be0349dc5	641	* @arg @ref LL_SYSCFG_EXTI_LINE12
<>	134:ad3be0349dc5	642	* @arg @ref LL_SYSCFG_EXTI_LINE13
<>	134:ad3be0349dc5	643	* @arg @ref LL_SYSCFG_EXTI_LINE14
<>	134:ad3be0349dc5	644	* @arg @ref LL_SYSCFG_EXTI_LINE15
<>	134:ad3be0349dc5	645	* @retval None
<>	134:ad3be0349dc5	646	*/
<>	134:ad3be0349dc5	647	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
<>	134:ad3be0349dc5	648	{
<>	134:ad3be0349dc5	649	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], SYSCFG_EXTICR1_EXTI0 << (Line >> 16), Port << (Line >> 16));
<>	134:ad3be0349dc5	650	}
<>	134:ad3be0349dc5	651
<>	134:ad3be0349dc5	652	/**
<>	134:ad3be0349dc5	653	* @brief Get the configured defined for specific EXTI Line
<>	134:ad3be0349dc5	654	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	655	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	656	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	657	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	658	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	659	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	660	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	661	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	662	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	663	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	664	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	665	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	666	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	667	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	668	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
<>	134:ad3be0349dc5	669	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
<>	134:ad3be0349dc5	670	* @param Line This parameter can be one of the following values:
<>	134:ad3be0349dc5	671	* @arg @ref LL_SYSCFG_EXTI_LINE0
<>	134:ad3be0349dc5	672	* @arg @ref LL_SYSCFG_EXTI_LINE1
<>	134:ad3be0349dc5	673	* @arg @ref LL_SYSCFG_EXTI_LINE2
<>	134:ad3be0349dc5	674	* @arg @ref LL_SYSCFG_EXTI_LINE3
<>	134:ad3be0349dc5	675	* @arg @ref LL_SYSCFG_EXTI_LINE4
<>	134:ad3be0349dc5	676	* @arg @ref LL_SYSCFG_EXTI_LINE5
<>	134:ad3be0349dc5	677	* @arg @ref LL_SYSCFG_EXTI_LINE6
<>	134:ad3be0349dc5	678	* @arg @ref LL_SYSCFG_EXTI_LINE7
<>	134:ad3be0349dc5	679	* @arg @ref LL_SYSCFG_EXTI_LINE8
<>	134:ad3be0349dc5	680	* @arg @ref LL_SYSCFG_EXTI_LINE9
<>	134:ad3be0349dc5	681	* @arg @ref LL_SYSCFG_EXTI_LINE10
<>	134:ad3be0349dc5	682	* @arg @ref LL_SYSCFG_EXTI_LINE11
<>	134:ad3be0349dc5	683	* @arg @ref LL_SYSCFG_EXTI_LINE12
<>	134:ad3be0349dc5	684	* @arg @ref LL_SYSCFG_EXTI_LINE13
<>	134:ad3be0349dc5	685	* @arg @ref LL_SYSCFG_EXTI_LINE14
<>	134:ad3be0349dc5	686	* @arg @ref LL_SYSCFG_EXTI_LINE15
<>	134:ad3be0349dc5	687	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	688	* @arg @ref LL_SYSCFG_EXTI_PORTA
<>	134:ad3be0349dc5	689	* @arg @ref LL_SYSCFG_EXTI_PORTB
<>	134:ad3be0349dc5	690	* @arg @ref LL_SYSCFG_EXTI_PORTC
<>	134:ad3be0349dc5	691	* @arg @ref LL_SYSCFG_EXTI_PORTD (*)
<>	134:ad3be0349dc5	692	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
<>	134:ad3be0349dc5	693	* @arg @ref LL_SYSCFG_EXTI_PORTF
<>	134:ad3be0349dc5	694	*
<>	134:ad3be0349dc5	695	* (*) value not defined in all devices
<>	134:ad3be0349dc5	696	*/
<>	134:ad3be0349dc5	697	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
<>	134:ad3be0349dc5	698	{
<>	134:ad3be0349dc5	699	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16))) >> (Line >> 16));
<>	134:ad3be0349dc5	700	}
<>	134:ad3be0349dc5	701
<>	134:ad3be0349dc5	702	#if defined(SYSCFG_ITLINE0_SR_EWDG)
<>	134:ad3be0349dc5	703	/**
<>	134:ad3be0349dc5	704	* @brief Check if Window watchdog interrupt occurred or not.
<>	134:ad3be0349dc5	705	* @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG
<>	134:ad3be0349dc5	706	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	707	*/
<>	134:ad3be0349dc5	708	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void)
<>	134:ad3be0349dc5	709	{
<>	134:ad3be0349dc5	710	return (READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG));
<>	134:ad3be0349dc5	711	}
<>	134:ad3be0349dc5	712	#endif /* SYSCFG_ITLINE0_SR_EWDG */
<>	134:ad3be0349dc5	713
<>	134:ad3be0349dc5	714	#if defined(SYSCFG_ITLINE1_SR_PVDOUT)
<>	134:ad3be0349dc5	715	/**
<>	134:ad3be0349dc5	716	* @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16).
<>	134:ad3be0349dc5	717	* @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT
<>	134:ad3be0349dc5	718	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	719	*/
<>	134:ad3be0349dc5	720	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void)
<>	134:ad3be0349dc5	721	{
<>	134:ad3be0349dc5	722	return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT));
<>	134:ad3be0349dc5	723	}
<>	134:ad3be0349dc5	724	#endif /* SYSCFG_ITLINE1_SR_PVDOUT */
<>	134:ad3be0349dc5	725
<>	134:ad3be0349dc5	726	#if defined(SYSCFG_ITLINE1_SR_VDDIO2)
<>	134:ad3be0349dc5	727	/**
<>	134:ad3be0349dc5	728	* @brief Check if VDDIO2 supply monitoring interrupt occurred or not (EXTI line 31).
<>	134:ad3be0349dc5	729	* @rmtoll SYSCFG_ITLINE1 SR_VDDIO2 LL_SYSCFG_IsActiveFlag_VDDIO2
<>	134:ad3be0349dc5	730	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	731	*/
<>	134:ad3be0349dc5	732	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VDDIO2(void)
<>	134:ad3be0349dc5	733	{
<>	134:ad3be0349dc5	734	return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_VDDIO2) == (SYSCFG_ITLINE1_SR_VDDIO2));
<>	134:ad3be0349dc5	735	}
<>	134:ad3be0349dc5	736	#endif /* SYSCFG_ITLINE1_SR_VDDIO2 */
<>	134:ad3be0349dc5	737
<>	134:ad3be0349dc5	738	#if defined(SYSCFG_ITLINE2_SR_RTC_WAKEUP)
<>	134:ad3be0349dc5	739	/**
<>	134:ad3be0349dc5	740	* @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 20).
<>	134:ad3be0349dc5	741	* @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP
<>	134:ad3be0349dc5	742	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	743	*/
<>	134:ad3be0349dc5	744	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void)
<>	134:ad3be0349dc5	745	{
<>	134:ad3be0349dc5	746	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_WAKEUP) == (SYSCFG_ITLINE2_SR_RTC_WAKEUP));
<>	134:ad3be0349dc5	747	}
<>	134:ad3be0349dc5	748	#endif /* SYSCFG_ITLINE2_SR_RTC_WAKEUP */
<>	134:ad3be0349dc5	749
<>	134:ad3be0349dc5	750	#if defined(SYSCFG_ITLINE2_SR_RTC_TSTAMP)
<>	134:ad3be0349dc5	751	/**
<>	134:ad3be0349dc5	752	* @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 19).
<>	134:ad3be0349dc5	753	* @rmtoll SYSCFG_ITLINE2 SR_RTC_TSTAMP LL_SYSCFG_IsActiveFlag_RTC_TSTAMP
<>	134:ad3be0349dc5	754	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	755	*/
<>	134:ad3be0349dc5	756	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void)
<>	134:ad3be0349dc5	757	{
<>	134:ad3be0349dc5	758	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_TSTAMP) == (SYSCFG_ITLINE2_SR_RTC_TSTAMP));
<>	134:ad3be0349dc5	759	}
<>	134:ad3be0349dc5	760	#endif /* SYSCFG_ITLINE2_SR_RTC_TSTAMP */
<>	134:ad3be0349dc5	761
<>	134:ad3be0349dc5	762	#if defined(SYSCFG_ITLINE2_SR_RTC_ALRA)
<>	134:ad3be0349dc5	763	/**
<>	134:ad3be0349dc5	764	* @brief Check if RTC Alarm interrupt occurred or not (EXTI line 17).
<>	134:ad3be0349dc5	765	* @rmtoll SYSCFG_ITLINE2 SR_RTC_ALRA LL_SYSCFG_IsActiveFlag_RTC_ALRA
<>	134:ad3be0349dc5	766	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	767	*/
<>	134:ad3be0349dc5	768	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_ALRA(void)
<>	134:ad3be0349dc5	769	{
<>	134:ad3be0349dc5	770	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_ALRA) == (SYSCFG_ITLINE2_SR_RTC_ALRA));
<>	134:ad3be0349dc5	771	}
<>	134:ad3be0349dc5	772	#endif /* SYSCFG_ITLINE2_SR_RTC_ALRA */
<>	134:ad3be0349dc5	773
<>	134:ad3be0349dc5	774	#if defined(SYSCFG_ITLINE3_SR_FLASH_ITF)
<>	134:ad3be0349dc5	775	/**
<>	134:ad3be0349dc5	776	* @brief Check if Flash interface interrupt occurred or not.
<>	134:ad3be0349dc5	777	* @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF
<>	134:ad3be0349dc5	778	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	779	*/
<>	134:ad3be0349dc5	780	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)
<>	134:ad3be0349dc5	781	{
<>	134:ad3be0349dc5	782	return (READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF));
<>	134:ad3be0349dc5	783	}
<>	134:ad3be0349dc5	784	#endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */
<>	134:ad3be0349dc5	785
<>	134:ad3be0349dc5	786	#if defined(SYSCFG_ITLINE4_SR_CRS)
<>	134:ad3be0349dc5	787	/**
<>	134:ad3be0349dc5	788	* @brief Check if Clock recovery system interrupt occurred or not.
<>	134:ad3be0349dc5	789	* @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS
<>	134:ad3be0349dc5	790	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	791	*/
<>	134:ad3be0349dc5	792	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void)
<>	134:ad3be0349dc5	793	{
<>	134:ad3be0349dc5	794	return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS));
<>	134:ad3be0349dc5	795	}
<>	134:ad3be0349dc5	796	#endif /* SYSCFG_ITLINE4_SR_CRS */
<>	134:ad3be0349dc5	797
<>	134:ad3be0349dc5	798	#if defined(SYSCFG_ITLINE4_SR_CLK_CTRL)
<>	134:ad3be0349dc5	799	/**
<>	134:ad3be0349dc5	800	* @brief Check if Reset and clock control interrupt occurred or not.
<>	134:ad3be0349dc5	801	* @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL
<>	134:ad3be0349dc5	802	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	803	*/
<>	134:ad3be0349dc5	804	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)
<>	134:ad3be0349dc5	805	{
<>	134:ad3be0349dc5	806	return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL));
<>	134:ad3be0349dc5	807	}
<>	134:ad3be0349dc5	808	#endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */
<>	134:ad3be0349dc5	809
<>	134:ad3be0349dc5	810	#if defined(SYSCFG_ITLINE5_SR_EXTI0)
<>	134:ad3be0349dc5	811	/**
<>	134:ad3be0349dc5	812	* @brief Check if EXTI line 0 interrupt occurred or not.
<>	134:ad3be0349dc5	813	* @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0
<>	134:ad3be0349dc5	814	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	815	*/
<>	134:ad3be0349dc5	816	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void)
<>	134:ad3be0349dc5	817	{
<>	134:ad3be0349dc5	818	return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0));
<>	134:ad3be0349dc5	819	}
<>	134:ad3be0349dc5	820	#endif /* SYSCFG_ITLINE5_SR_EXTI0 */
<>	134:ad3be0349dc5	821
<>	134:ad3be0349dc5	822	#if defined(SYSCFG_ITLINE5_SR_EXTI1)
<>	134:ad3be0349dc5	823	/**
<>	134:ad3be0349dc5	824	* @brief Check if EXTI line 1 interrupt occurred or not.
<>	134:ad3be0349dc5	825	* @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1
<>	134:ad3be0349dc5	826	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	827	*/
<>	134:ad3be0349dc5	828	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void)
<>	134:ad3be0349dc5	829	{
<>	134:ad3be0349dc5	830	return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1));
<>	134:ad3be0349dc5	831	}
<>	134:ad3be0349dc5	832	#endif /* SYSCFG_ITLINE5_SR_EXTI1 */
<>	134:ad3be0349dc5	833
<>	134:ad3be0349dc5	834	#if defined(SYSCFG_ITLINE6_SR_EXTI2)
<>	134:ad3be0349dc5	835	/**
<>	134:ad3be0349dc5	836	* @brief Check if EXTI line 2 interrupt occurred or not.
<>	134:ad3be0349dc5	837	* @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2
<>	134:ad3be0349dc5	838	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	839	*/
<>	134:ad3be0349dc5	840	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void)
<>	134:ad3be0349dc5	841	{
<>	134:ad3be0349dc5	842	return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2));
<>	134:ad3be0349dc5	843	}
<>	134:ad3be0349dc5	844	#endif /* SYSCFG_ITLINE6_SR_EXTI2 */
<>	134:ad3be0349dc5	845
<>	134:ad3be0349dc5	846	#if defined(SYSCFG_ITLINE6_SR_EXTI3)
<>	134:ad3be0349dc5	847	/**
<>	134:ad3be0349dc5	848	* @brief Check if EXTI line 3 interrupt occurred or not.
<>	134:ad3be0349dc5	849	* @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3
<>	134:ad3be0349dc5	850	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	851	*/
<>	134:ad3be0349dc5	852	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void)
<>	134:ad3be0349dc5	853	{
<>	134:ad3be0349dc5	854	return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3));
<>	134:ad3be0349dc5	855	}
<>	134:ad3be0349dc5	856	#endif /* SYSCFG_ITLINE6_SR_EXTI3 */
<>	134:ad3be0349dc5	857
<>	134:ad3be0349dc5	858	#if defined(SYSCFG_ITLINE7_SR_EXTI4)
<>	134:ad3be0349dc5	859	/**
<>	134:ad3be0349dc5	860	* @brief Check if EXTI line 4 interrupt occurred or not.
<>	134:ad3be0349dc5	861	* @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4
<>	134:ad3be0349dc5	862	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	863	*/
<>	134:ad3be0349dc5	864	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void)
<>	134:ad3be0349dc5	865	{
<>	134:ad3be0349dc5	866	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4));
<>	134:ad3be0349dc5	867	}
<>	134:ad3be0349dc5	868	#endif /* SYSCFG_ITLINE7_SR_EXTI4 */
<>	134:ad3be0349dc5	869
<>	134:ad3be0349dc5	870	#if defined(SYSCFG_ITLINE7_SR_EXTI5)
<>	134:ad3be0349dc5	871	/**
<>	134:ad3be0349dc5	872	* @brief Check if EXTI line 5 interrupt occurred or not.
<>	134:ad3be0349dc5	873	* @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5
<>	134:ad3be0349dc5	874	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	875	*/
<>	134:ad3be0349dc5	876	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void)
<>	134:ad3be0349dc5	877	{
<>	134:ad3be0349dc5	878	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5));
<>	134:ad3be0349dc5	879	}
<>	134:ad3be0349dc5	880	#endif /* SYSCFG_ITLINE7_SR_EXTI5 */
<>	134:ad3be0349dc5	881
<>	134:ad3be0349dc5	882	#if defined(SYSCFG_ITLINE7_SR_EXTI6)
<>	134:ad3be0349dc5	883	/**
<>	134:ad3be0349dc5	884	* @brief Check if EXTI line 6 interrupt occurred or not.
<>	134:ad3be0349dc5	885	* @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6
<>	134:ad3be0349dc5	886	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	887	*/
<>	134:ad3be0349dc5	888	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void)
<>	134:ad3be0349dc5	889	{
<>	134:ad3be0349dc5	890	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6));
<>	134:ad3be0349dc5	891	}
<>	134:ad3be0349dc5	892	#endif /* SYSCFG_ITLINE7_SR_EXTI6 */
<>	134:ad3be0349dc5	893
<>	134:ad3be0349dc5	894	#if defined(SYSCFG_ITLINE7_SR_EXTI7)
<>	134:ad3be0349dc5	895	/**
<>	134:ad3be0349dc5	896	* @brief Check if EXTI line 7 interrupt occurred or not.
<>	134:ad3be0349dc5	897	* @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7
<>	134:ad3be0349dc5	898	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	899	*/
<>	134:ad3be0349dc5	900	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void)
<>	134:ad3be0349dc5	901	{
<>	134:ad3be0349dc5	902	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7));
<>	134:ad3be0349dc5	903	}
<>	134:ad3be0349dc5	904	#endif /* SYSCFG_ITLINE7_SR_EXTI7 */
<>	134:ad3be0349dc5	905
<>	134:ad3be0349dc5	906	#if defined(SYSCFG_ITLINE7_SR_EXTI8)
<>	134:ad3be0349dc5	907	/**
<>	134:ad3be0349dc5	908	* @brief Check if EXTI line 8 interrupt occurred or not.
<>	134:ad3be0349dc5	909	* @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8
<>	134:ad3be0349dc5	910	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	911	*/
<>	134:ad3be0349dc5	912	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void)
<>	134:ad3be0349dc5	913	{
<>	134:ad3be0349dc5	914	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8));
<>	134:ad3be0349dc5	915	}
<>	134:ad3be0349dc5	916	#endif /* SYSCFG_ITLINE7_SR_EXTI8 */
<>	134:ad3be0349dc5	917
<>	134:ad3be0349dc5	918	#if defined(SYSCFG_ITLINE7_SR_EXTI9)
<>	134:ad3be0349dc5	919	/**
<>	134:ad3be0349dc5	920	* @brief Check if EXTI line 9 interrupt occurred or not.
<>	134:ad3be0349dc5	921	* @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9
<>	134:ad3be0349dc5	922	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	923	*/
<>	134:ad3be0349dc5	924	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void)
<>	134:ad3be0349dc5	925	{
<>	134:ad3be0349dc5	926	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9));
<>	134:ad3be0349dc5	927	}
<>	134:ad3be0349dc5	928	#endif /* SYSCFG_ITLINE7_SR_EXTI9 */
<>	134:ad3be0349dc5	929
<>	134:ad3be0349dc5	930	#if defined(SYSCFG_ITLINE7_SR_EXTI10)
<>	134:ad3be0349dc5	931	/**
<>	134:ad3be0349dc5	932	* @brief Check if EXTI line 10 interrupt occurred or not.
<>	134:ad3be0349dc5	933	* @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10
<>	134:ad3be0349dc5	934	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	935	*/
<>	134:ad3be0349dc5	936	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void)
<>	134:ad3be0349dc5	937	{
<>	134:ad3be0349dc5	938	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10));
<>	134:ad3be0349dc5	939	}
<>	134:ad3be0349dc5	940	#endif /* SYSCFG_ITLINE7_SR_EXTI10 */
<>	134:ad3be0349dc5	941
<>	134:ad3be0349dc5	942	#if defined(SYSCFG_ITLINE7_SR_EXTI11)
<>	134:ad3be0349dc5	943	/**
<>	134:ad3be0349dc5	944	* @brief Check if EXTI line 11 interrupt occurred or not.
<>	134:ad3be0349dc5	945	* @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11
<>	134:ad3be0349dc5	946	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	947	*/
<>	134:ad3be0349dc5	948	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void)
<>	134:ad3be0349dc5	949	{
<>	134:ad3be0349dc5	950	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11));
<>	134:ad3be0349dc5	951	}
<>	134:ad3be0349dc5	952	#endif /* SYSCFG_ITLINE7_SR_EXTI11 */
<>	134:ad3be0349dc5	953
<>	134:ad3be0349dc5	954	#if defined(SYSCFG_ITLINE7_SR_EXTI12)
<>	134:ad3be0349dc5	955	/**
<>	134:ad3be0349dc5	956	* @brief Check if EXTI line 12 interrupt occurred or not.
<>	134:ad3be0349dc5	957	* @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12
<>	134:ad3be0349dc5	958	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	959	*/
<>	134:ad3be0349dc5	960	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void)
<>	134:ad3be0349dc5	961	{
<>	134:ad3be0349dc5	962	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12));
<>	134:ad3be0349dc5	963	}
<>	134:ad3be0349dc5	964	#endif /* SYSCFG_ITLINE7_SR_EXTI12 */
<>	134:ad3be0349dc5	965
<>	134:ad3be0349dc5	966	#if defined(SYSCFG_ITLINE7_SR_EXTI13)
<>	134:ad3be0349dc5	967	/**
<>	134:ad3be0349dc5	968	* @brief Check if EXTI line 13 interrupt occurred or not.
<>	134:ad3be0349dc5	969	* @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13
<>	134:ad3be0349dc5	970	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	971	*/
<>	134:ad3be0349dc5	972	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void)
<>	134:ad3be0349dc5	973	{
<>	134:ad3be0349dc5	974	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13));
<>	134:ad3be0349dc5	975	}
<>	134:ad3be0349dc5	976	#endif /* SYSCFG_ITLINE7_SR_EXTI13 */
<>	134:ad3be0349dc5	977
<>	134:ad3be0349dc5	978	#if defined(SYSCFG_ITLINE7_SR_EXTI14)
<>	134:ad3be0349dc5	979	/**
<>	134:ad3be0349dc5	980	* @brief Check if EXTI line 14 interrupt occurred or not.
<>	134:ad3be0349dc5	981	* @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14
<>	134:ad3be0349dc5	982	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	983	*/
<>	134:ad3be0349dc5	984	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void)
<>	134:ad3be0349dc5	985	{
<>	134:ad3be0349dc5	986	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14));
<>	134:ad3be0349dc5	987	}
<>	134:ad3be0349dc5	988	#endif /* SYSCFG_ITLINE7_SR_EXTI14 */
<>	134:ad3be0349dc5	989
<>	134:ad3be0349dc5	990	#if defined(SYSCFG_ITLINE7_SR_EXTI15)
<>	134:ad3be0349dc5	991	/**
<>	134:ad3be0349dc5	992	* @brief Check if EXTI line 15 interrupt occurred or not.
<>	134:ad3be0349dc5	993	* @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15
<>	134:ad3be0349dc5	994	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	995	*/
<>	134:ad3be0349dc5	996	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void)
<>	134:ad3be0349dc5	997	{
<>	134:ad3be0349dc5	998	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15));
<>	134:ad3be0349dc5	999	}
<>	134:ad3be0349dc5	1000	#endif /* SYSCFG_ITLINE7_SR_EXTI15 */
<>	134:ad3be0349dc5	1001
<>	134:ad3be0349dc5	1002	#if defined(SYSCFG_ITLINE8_SR_TSC_EOA)
<>	134:ad3be0349dc5	1003	/**
<>	134:ad3be0349dc5	1004	* @brief Check if Touch sensing controller end of acquisition interrupt occurred or not.
<>	134:ad3be0349dc5	1005	* @rmtoll SYSCFG_ITLINE8 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA
<>	134:ad3be0349dc5	1006	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1007	*/
<>	134:ad3be0349dc5	1008	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void)
<>	134:ad3be0349dc5	1009	{
<>	134:ad3be0349dc5	1010	return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_EOA) == (SYSCFG_ITLINE8_SR_TSC_EOA));
<>	134:ad3be0349dc5	1011	}
<>	134:ad3be0349dc5	1012	#endif /* SYSCFG_ITLINE8_SR_TSC_EOA */
<>	134:ad3be0349dc5	1013
<>	134:ad3be0349dc5	1014	#if defined(SYSCFG_ITLINE8_SR_TSC_MCE)
<>	134:ad3be0349dc5	1015	/**
<>	134:ad3be0349dc5	1016	* @brief Check if Touch sensing controller max counterror interrupt occurred or not.
<>	134:ad3be0349dc5	1017	* @rmtoll SYSCFG_ITLINE8 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE
<>	134:ad3be0349dc5	1018	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1019	*/
<>	134:ad3be0349dc5	1020	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void)
<>	134:ad3be0349dc5	1021	{
<>	134:ad3be0349dc5	1022	return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_MCE) == (SYSCFG_ITLINE8_SR_TSC_MCE));
<>	134:ad3be0349dc5	1023	}
<>	134:ad3be0349dc5	1024	#endif /* SYSCFG_ITLINE8_SR_TSC_MCE */
<>	134:ad3be0349dc5	1025
<>	134:ad3be0349dc5	1026	#if defined(SYSCFG_ITLINE9_SR_DMA1_CH1)
<>	134:ad3be0349dc5	1027	/**
<>	134:ad3be0349dc5	1028	* @brief Check if DMA1 channel 1 interrupt occurred or not.
<>	134:ad3be0349dc5	1029	* @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1
<>	134:ad3be0349dc5	1030	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1031	*/
<>	134:ad3be0349dc5	1032	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)
<>	134:ad3be0349dc5	1033	{
<>	134:ad3be0349dc5	1034	return (READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1));
<>	134:ad3be0349dc5	1035	}
<>	134:ad3be0349dc5	1036	#endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */
<>	134:ad3be0349dc5	1037
<>	134:ad3be0349dc5	1038	#if defined(SYSCFG_ITLINE10_SR_DMA1_CH2)
<>	134:ad3be0349dc5	1039	/**
<>	134:ad3be0349dc5	1040	* @brief Check if DMA1 channel 2 interrupt occurred or not.
<>	134:ad3be0349dc5	1041	* @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2
<>	134:ad3be0349dc5	1042	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1043	*/
<>	134:ad3be0349dc5	1044	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)
<>	134:ad3be0349dc5	1045	{
<>	134:ad3be0349dc5	1046	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2));
<>	134:ad3be0349dc5	1047	}
<>	134:ad3be0349dc5	1048	#endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */
<>	134:ad3be0349dc5	1049
<>	134:ad3be0349dc5	1050	#if defined(SYSCFG_ITLINE10_SR_DMA1_CH3)
<>	134:ad3be0349dc5	1051	/**
<>	134:ad3be0349dc5	1052	* @brief Check if DMA1 channel 3 interrupt occurred or not.
<>	134:ad3be0349dc5	1053	* @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3
<>	134:ad3be0349dc5	1054	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1055	*/
<>	134:ad3be0349dc5	1056	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)
<>	134:ad3be0349dc5	1057	{
<>	134:ad3be0349dc5	1058	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3));
<>	134:ad3be0349dc5	1059	}
<>	134:ad3be0349dc5	1060	#endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */
<>	134:ad3be0349dc5	1061
<>	134:ad3be0349dc5	1062	#if defined(SYSCFG_ITLINE10_SR_DMA2_CH1)
<>	134:ad3be0349dc5	1063	/**
<>	134:ad3be0349dc5	1064	* @brief Check if DMA2 channel 1 interrupt occurred or not.
<>	134:ad3be0349dc5	1065	* @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1
<>	134:ad3be0349dc5	1066	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1067	*/
<>	134:ad3be0349dc5	1068	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void)
<>	134:ad3be0349dc5	1069	{
<>	134:ad3be0349dc5	1070	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH1) == (SYSCFG_ITLINE10_SR_DMA2_CH1));
<>	134:ad3be0349dc5	1071	}
<>	134:ad3be0349dc5	1072	#endif /* SYSCFG_ITLINE10_SR_DMA2_CH1 */
<>	134:ad3be0349dc5	1073
<>	134:ad3be0349dc5	1074	#if defined(SYSCFG_ITLINE10_SR_DMA2_CH2)
<>	134:ad3be0349dc5	1075	/**
<>	134:ad3be0349dc5	1076	* @brief Check if DMA2 channel 2 interrupt occurred or not.
<>	134:ad3be0349dc5	1077	* @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2
<>	134:ad3be0349dc5	1078	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1079	*/
<>	134:ad3be0349dc5	1080	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void)
<>	134:ad3be0349dc5	1081	{
<>	134:ad3be0349dc5	1082	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH2) == (SYSCFG_ITLINE10_SR_DMA2_CH2));
<>	134:ad3be0349dc5	1083	}
<>	134:ad3be0349dc5	1084	#endif /* SYSCFG_ITLINE10_SR_DMA2_CH2 */
<>	134:ad3be0349dc5	1085
<>	134:ad3be0349dc5	1086	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4)
<>	134:ad3be0349dc5	1087	/**
<>	134:ad3be0349dc5	1088	* @brief Check if DMA1 channel 4 interrupt occurred or not.
<>	134:ad3be0349dc5	1089	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4
<>	134:ad3be0349dc5	1090	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1091	*/
<>	134:ad3be0349dc5	1092	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)
<>	134:ad3be0349dc5	1093	{
<>	134:ad3be0349dc5	1094	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4));
<>	134:ad3be0349dc5	1095	}
<>	134:ad3be0349dc5	1096	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */
<>	134:ad3be0349dc5	1097
<>	134:ad3be0349dc5	1098	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
<>	134:ad3be0349dc5	1099	/**
<>	134:ad3be0349dc5	1100	* @brief Check if DMA1 channel 5 interrupt occurred or not.
<>	134:ad3be0349dc5	1101	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5
<>	134:ad3be0349dc5	1102	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1103	*/
<>	134:ad3be0349dc5	1104	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)
<>	134:ad3be0349dc5	1105	{
<>	134:ad3be0349dc5	1106	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5));
<>	134:ad3be0349dc5	1107	}
<>	134:ad3be0349dc5	1108	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */
<>	134:ad3be0349dc5	1109
<>	134:ad3be0349dc5	1110	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6)
<>	134:ad3be0349dc5	1111	/**
<>	134:ad3be0349dc5	1112	* @brief Check if DMA1 channel 6 interrupt occurred or not.
<>	134:ad3be0349dc5	1113	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6
<>	134:ad3be0349dc5	1114	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1115	*/
<>	134:ad3be0349dc5	1116	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void)
<>	134:ad3be0349dc5	1117	{
<>	134:ad3be0349dc5	1118	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6));
<>	134:ad3be0349dc5	1119	}
<>	134:ad3be0349dc5	1120	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */
<>	134:ad3be0349dc5	1121
<>	134:ad3be0349dc5	1122	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7)
<>	134:ad3be0349dc5	1123	/**
<>	134:ad3be0349dc5	1124	* @brief Check if DMA1 channel 7 interrupt occurred or not.
<>	134:ad3be0349dc5	1125	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7
<>	134:ad3be0349dc5	1126	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1127	*/
<>	134:ad3be0349dc5	1128	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void)
<>	134:ad3be0349dc5	1129	{
<>	134:ad3be0349dc5	1130	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7));
<>	134:ad3be0349dc5	1131	}
<>	134:ad3be0349dc5	1132	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */
<>	134:ad3be0349dc5	1133
<>	134:ad3be0349dc5	1134	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH3)
<>	134:ad3be0349dc5	1135	/**
<>	134:ad3be0349dc5	1136	* @brief Check if DMA2 channel 3 interrupt occurred or not.
<>	134:ad3be0349dc5	1137	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3
<>	134:ad3be0349dc5	1138	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1139	*/
<>	134:ad3be0349dc5	1140	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void)
<>	134:ad3be0349dc5	1141	{
<>	134:ad3be0349dc5	1142	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3));
<>	134:ad3be0349dc5	1143	}
<>	134:ad3be0349dc5	1144	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */
<>	134:ad3be0349dc5	1145
<>	134:ad3be0349dc5	1146	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH4)
<>	134:ad3be0349dc5	1147	/**
<>	134:ad3be0349dc5	1148	* @brief Check if DMA2 channel 4 interrupt occurred or not.
<>	134:ad3be0349dc5	1149	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4
<>	134:ad3be0349dc5	1150	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1151	*/
<>	134:ad3be0349dc5	1152	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void)
<>	134:ad3be0349dc5	1153	{
<>	134:ad3be0349dc5	1154	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4));
<>	134:ad3be0349dc5	1155	}
<>	134:ad3be0349dc5	1156	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */
<>	134:ad3be0349dc5	1157
<>	134:ad3be0349dc5	1158	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH5)
<>	134:ad3be0349dc5	1159	/**
<>	134:ad3be0349dc5	1160	* @brief Check if DMA2 channel 5 interrupt occurred or not.
<>	134:ad3be0349dc5	1161	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5
<>	134:ad3be0349dc5	1162	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1163	*/
<>	134:ad3be0349dc5	1164	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void)
<>	134:ad3be0349dc5	1165	{
<>	134:ad3be0349dc5	1166	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5));
<>	134:ad3be0349dc5	1167	}
<>	134:ad3be0349dc5	1168	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */
<>	134:ad3be0349dc5	1169
<>	134:ad3be0349dc5	1170	#if defined(SYSCFG_ITLINE12_SR_ADC)
<>	134:ad3be0349dc5	1171	/**
<>	134:ad3be0349dc5	1172	* @brief Check if ADC interrupt occurred or not.
<>	134:ad3be0349dc5	1173	* @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC
<>	134:ad3be0349dc5	1174	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1175	*/
<>	134:ad3be0349dc5	1176	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void)
<>	134:ad3be0349dc5	1177	{
<>	134:ad3be0349dc5	1178	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC));
<>	134:ad3be0349dc5	1179	}
<>	134:ad3be0349dc5	1180	#endif /* SYSCFG_ITLINE12_SR_ADC */
<>	134:ad3be0349dc5	1181
<>	134:ad3be0349dc5	1182	#if defined(SYSCFG_ITLINE12_SR_COMP1)
<>	134:ad3be0349dc5	1183	/**
<>	134:ad3be0349dc5	1184	* @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21).
<>	134:ad3be0349dc5	1185	* @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1
<>	134:ad3be0349dc5	1186	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1187	*/
<>	134:ad3be0349dc5	1188	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void)
<>	134:ad3be0349dc5	1189	{
<>	134:ad3be0349dc5	1190	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1));
<>	134:ad3be0349dc5	1191	}
<>	134:ad3be0349dc5	1192	#endif /* SYSCFG_ITLINE12_SR_COMP1 */
<>	134:ad3be0349dc5	1193
<>	134:ad3be0349dc5	1194	#if defined(SYSCFG_ITLINE12_SR_COMP2)
<>	134:ad3be0349dc5	1195	/**
<>	134:ad3be0349dc5	1196	* @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22).
<>	134:ad3be0349dc5	1197	* @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2
<>	134:ad3be0349dc5	1198	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1199	*/
<>	134:ad3be0349dc5	1200	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void)
<>	134:ad3be0349dc5	1201	{
<>	134:ad3be0349dc5	1202	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2));
<>	134:ad3be0349dc5	1203	}
<>	134:ad3be0349dc5	1204	#endif /* SYSCFG_ITLINE12_SR_COMP2 */
<>	134:ad3be0349dc5	1205
<>	134:ad3be0349dc5	1206	#if defined(SYSCFG_ITLINE13_SR_TIM1_BRK)
<>	134:ad3be0349dc5	1207	/**
<>	134:ad3be0349dc5	1208	* @brief Check if Timer 1 break interrupt occurred or not.
<>	134:ad3be0349dc5	1209	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK
<>	134:ad3be0349dc5	1210	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1211	*/
<>	134:ad3be0349dc5	1212	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)
<>	134:ad3be0349dc5	1213	{
<>	134:ad3be0349dc5	1214	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK));
<>	134:ad3be0349dc5	1215	}
<>	134:ad3be0349dc5	1216	#endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */
<>	134:ad3be0349dc5	1217
<>	134:ad3be0349dc5	1218	#if defined(SYSCFG_ITLINE13_SR_TIM1_UPD)
<>	134:ad3be0349dc5	1219	/**
<>	134:ad3be0349dc5	1220	* @brief Check if Timer 1 update interrupt occurred or not.
<>	134:ad3be0349dc5	1221	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD
<>	134:ad3be0349dc5	1222	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1223	*/
<>	134:ad3be0349dc5	1224	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)
<>	134:ad3be0349dc5	1225	{
<>	134:ad3be0349dc5	1226	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD));
<>	134:ad3be0349dc5	1227	}
<>	134:ad3be0349dc5	1228	#endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */
<>	134:ad3be0349dc5	1229
<>	134:ad3be0349dc5	1230	#if defined(SYSCFG_ITLINE13_SR_TIM1_TRG)
<>	134:ad3be0349dc5	1231	/**
<>	134:ad3be0349dc5	1232	* @brief Check if Timer 1 trigger interrupt occurred or not.
<>	134:ad3be0349dc5	1233	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG
<>	134:ad3be0349dc5	1234	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1235	*/
<>	134:ad3be0349dc5	1236	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)
<>	134:ad3be0349dc5	1237	{
<>	134:ad3be0349dc5	1238	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG));
<>	134:ad3be0349dc5	1239	}
<>	134:ad3be0349dc5	1240	#endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */
<>	134:ad3be0349dc5	1241
<>	134:ad3be0349dc5	1242	#if defined(SYSCFG_ITLINE13_SR_TIM1_CCU)
<>	134:ad3be0349dc5	1243	/**
<>	134:ad3be0349dc5	1244	* @brief Check if Timer 1 commutation interrupt occurred or not.
<>	134:ad3be0349dc5	1245	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU
<>	134:ad3be0349dc5	1246	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1247	*/
<>	134:ad3be0349dc5	1248	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)
<>	134:ad3be0349dc5	1249	{
<>	134:ad3be0349dc5	1250	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU));
<>	134:ad3be0349dc5	1251	}
<>	134:ad3be0349dc5	1252	#endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */
<>	134:ad3be0349dc5	1253
<>	134:ad3be0349dc5	1254	#if defined(SYSCFG_ITLINE14_SR_TIM1_CC)
<>	134:ad3be0349dc5	1255	/**
<>	134:ad3be0349dc5	1256	* @brief Check if Timer 1 capture compare interrupt occurred or not.
<>	134:ad3be0349dc5	1257	* @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC
<>	134:ad3be0349dc5	1258	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1259	*/
<>	134:ad3be0349dc5	1260	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void)
<>	134:ad3be0349dc5	1261	{
<>	134:ad3be0349dc5	1262	return (READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC));
<>	134:ad3be0349dc5	1263	}
<>	134:ad3be0349dc5	1264	#endif /* SYSCFG_ITLINE14_SR_TIM1_CC */
<>	134:ad3be0349dc5	1265
<>	134:ad3be0349dc5	1266	#if defined(SYSCFG_ITLINE15_SR_TIM2_GLB)
<>	134:ad3be0349dc5	1267	/**
<>	134:ad3be0349dc5	1268	* @brief Check if Timer 2 interrupt occurred or not.
<>	134:ad3be0349dc5	1269	* @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2
<>	134:ad3be0349dc5	1270	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1271	*/
<>	134:ad3be0349dc5	1272	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void)
<>	134:ad3be0349dc5	1273	{
<>	134:ad3be0349dc5	1274	return (READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB));
<>	134:ad3be0349dc5	1275	}
<>	134:ad3be0349dc5	1276	#endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */
<>	134:ad3be0349dc5	1277
<>	134:ad3be0349dc5	1278	#if defined(SYSCFG_ITLINE16_SR_TIM3_GLB)
<>	134:ad3be0349dc5	1279	/**
<>	134:ad3be0349dc5	1280	* @brief Check if Timer 3 interrupt occurred or not.
<>	134:ad3be0349dc5	1281	* @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3
<>	134:ad3be0349dc5	1282	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1283	*/
<>	134:ad3be0349dc5	1284	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void)
<>	134:ad3be0349dc5	1285	{
<>	134:ad3be0349dc5	1286	return (READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB));
<>	134:ad3be0349dc5	1287	}
<>	134:ad3be0349dc5	1288	#endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */
<>	134:ad3be0349dc5	1289
<>	134:ad3be0349dc5	1290	#if defined(SYSCFG_ITLINE17_SR_DAC)
<>	134:ad3be0349dc5	1291	/**
<>	134:ad3be0349dc5	1292	* @brief Check if DAC underrun interrupt occurred or not.
<>	134:ad3be0349dc5	1293	* @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC
<>	134:ad3be0349dc5	1294	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1295	*/
<>	134:ad3be0349dc5	1296	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void)
<>	134:ad3be0349dc5	1297	{
<>	134:ad3be0349dc5	1298	return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC));
<>	134:ad3be0349dc5	1299	}
<>	134:ad3be0349dc5	1300	#endif /* SYSCFG_ITLINE17_SR_DAC */
<>	134:ad3be0349dc5	1301
<>	134:ad3be0349dc5	1302	#if defined(SYSCFG_ITLINE17_SR_TIM6_GLB)
<>	134:ad3be0349dc5	1303	/**
<>	134:ad3be0349dc5	1304	* @brief Check if Timer 6 interrupt occurred or not.
<>	134:ad3be0349dc5	1305	* @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6
<>	134:ad3be0349dc5	1306	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1307	*/
<>	134:ad3be0349dc5	1308	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void)
<>	134:ad3be0349dc5	1309	{
<>	134:ad3be0349dc5	1310	return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB));
<>	134:ad3be0349dc5	1311	}
<>	134:ad3be0349dc5	1312	#endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */
<>	134:ad3be0349dc5	1313
<>	134:ad3be0349dc5	1314	#if defined(SYSCFG_ITLINE18_SR_TIM7_GLB)
<>	134:ad3be0349dc5	1315	/**
<>	134:ad3be0349dc5	1316	* @brief Check if Timer 7 interrupt occurred or not.
<>	134:ad3be0349dc5	1317	* @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7
<>	134:ad3be0349dc5	1318	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1319	*/
<>	134:ad3be0349dc5	1320	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void)
<>	134:ad3be0349dc5	1321	{
<>	134:ad3be0349dc5	1322	return (READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB));
<>	134:ad3be0349dc5	1323	}
<>	134:ad3be0349dc5	1324	#endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */
<>	134:ad3be0349dc5	1325
<>	134:ad3be0349dc5	1326	#if defined(SYSCFG_ITLINE19_SR_TIM14_GLB)
<>	134:ad3be0349dc5	1327	/**
<>	134:ad3be0349dc5	1328	* @brief Check if Timer 14 interrupt occurred or not.
<>	134:ad3be0349dc5	1329	* @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14
<>	134:ad3be0349dc5	1330	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1331	*/
<>	134:ad3be0349dc5	1332	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void)
<>	134:ad3be0349dc5	1333	{
<>	134:ad3be0349dc5	1334	return (READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB));
<>	134:ad3be0349dc5	1335	}
<>	134:ad3be0349dc5	1336	#endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */
<>	134:ad3be0349dc5	1337
<>	134:ad3be0349dc5	1338	#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB)
<>	134:ad3be0349dc5	1339	/**
<>	134:ad3be0349dc5	1340	* @brief Check if Timer 15 interrupt occurred or not.
<>	134:ad3be0349dc5	1341	* @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15
<>	134:ad3be0349dc5	1342	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1343	*/
<>	134:ad3be0349dc5	1344	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void)
<>	134:ad3be0349dc5	1345	{
<>	134:ad3be0349dc5	1346	return (READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB));
<>	134:ad3be0349dc5	1347	}
<>	134:ad3be0349dc5	1348	#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */
<>	134:ad3be0349dc5	1349
<>	134:ad3be0349dc5	1350	#if defined(SYSCFG_ITLINE21_SR_TIM16_GLB)
<>	134:ad3be0349dc5	1351	/**
<>	134:ad3be0349dc5	1352	* @brief Check if Timer 16 interrupt occurred or not.
<>	134:ad3be0349dc5	1353	* @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16
<>	134:ad3be0349dc5	1354	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1355	*/
<>	134:ad3be0349dc5	1356	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void)
<>	134:ad3be0349dc5	1357	{
<>	134:ad3be0349dc5	1358	return (READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB));
<>	134:ad3be0349dc5	1359	}
<>	134:ad3be0349dc5	1360	#endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */
<>	134:ad3be0349dc5	1361
<>	134:ad3be0349dc5	1362	#if defined(SYSCFG_ITLINE22_SR_TIM17_GLB)
<>	134:ad3be0349dc5	1363	/**
<>	134:ad3be0349dc5	1364	* @brief Check if Timer 17 interrupt occurred or not.
<>	134:ad3be0349dc5	1365	* @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17
<>	134:ad3be0349dc5	1366	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1367	*/
<>	134:ad3be0349dc5	1368	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void)
<>	134:ad3be0349dc5	1369	{
<>	134:ad3be0349dc5	1370	return (READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB));
<>	134:ad3be0349dc5	1371	}
<>	134:ad3be0349dc5	1372	#endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */
<>	134:ad3be0349dc5	1373
<>	134:ad3be0349dc5	1374	#if defined(SYSCFG_ITLINE23_SR_I2C1_GLB)
<>	134:ad3be0349dc5	1375	/**
<>	134:ad3be0349dc5	1376	* @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23.
<>	134:ad3be0349dc5	1377	* @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1
<>	134:ad3be0349dc5	1378	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1379	*/
<>	134:ad3be0349dc5	1380	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void)
<>	134:ad3be0349dc5	1381	{
<>	134:ad3be0349dc5	1382	return (READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB));
<>	134:ad3be0349dc5	1383	}
<>	134:ad3be0349dc5	1384	#endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */
<>	134:ad3be0349dc5	1385
<>	134:ad3be0349dc5	1386	#if defined(SYSCFG_ITLINE24_SR_I2C2_GLB)
<>	134:ad3be0349dc5	1387	/**
<>	134:ad3be0349dc5	1388	* @brief Check if I2C2 interrupt occurred or not.
<>	134:ad3be0349dc5	1389	* @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2
<>	134:ad3be0349dc5	1390	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1391	*/
<>	134:ad3be0349dc5	1392	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void)
<>	134:ad3be0349dc5	1393	{
<>	134:ad3be0349dc5	1394	return (READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB));
<>	134:ad3be0349dc5	1395	}
<>	134:ad3be0349dc5	1396	#endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */
<>	134:ad3be0349dc5	1397
<>	134:ad3be0349dc5	1398	#if defined(SYSCFG_ITLINE25_SR_SPI1)
<>	134:ad3be0349dc5	1399	/**
<>	134:ad3be0349dc5	1400	* @brief Check if SPI1 interrupt occurred or not.
<>	134:ad3be0349dc5	1401	* @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1
<>	134:ad3be0349dc5	1402	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1403	*/
<>	134:ad3be0349dc5	1404	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void)
<>	134:ad3be0349dc5	1405	{
<>	134:ad3be0349dc5	1406	return (READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1));
<>	134:ad3be0349dc5	1407	}
<>	134:ad3be0349dc5	1408	#endif /* SYSCFG_ITLINE25_SR_SPI1 */
<>	134:ad3be0349dc5	1409
<>	134:ad3be0349dc5	1410	#if defined(SYSCFG_ITLINE26_SR_SPI2)
<>	134:ad3be0349dc5	1411	/**
<>	134:ad3be0349dc5	1412	* @brief Check if SPI2 interrupt occurred or not.
<>	134:ad3be0349dc5	1413	* @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2
<>	134:ad3be0349dc5	1414	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1415	*/
<>	134:ad3be0349dc5	1416	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void)
<>	134:ad3be0349dc5	1417	{
<>	134:ad3be0349dc5	1418	return (READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2));
<>	134:ad3be0349dc5	1419	}
<>	134:ad3be0349dc5	1420	#endif /* SYSCFG_ITLINE26_SR_SPI2 */
<>	134:ad3be0349dc5	1421
<>	134:ad3be0349dc5	1422	#if defined(SYSCFG_ITLINE27_SR_USART1_GLB)
<>	134:ad3be0349dc5	1423	/**
<>	134:ad3be0349dc5	1424	* @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25.
<>	134:ad3be0349dc5	1425	* @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1
<>	134:ad3be0349dc5	1426	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1427	*/
<>	134:ad3be0349dc5	1428	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void)
<>	134:ad3be0349dc5	1429	{
<>	134:ad3be0349dc5	1430	return (READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB));
<>	134:ad3be0349dc5	1431	}
<>	134:ad3be0349dc5	1432	#endif /* SYSCFG_ITLINE27_SR_USART1_GLB */
<>	134:ad3be0349dc5	1433
<>	134:ad3be0349dc5	1434	#if defined(SYSCFG_ITLINE28_SR_USART2_GLB)
<>	134:ad3be0349dc5	1435	/**
<>	134:ad3be0349dc5	1436	* @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26.
<>	134:ad3be0349dc5	1437	* @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2
<>	134:ad3be0349dc5	1438	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1439	*/
<>	134:ad3be0349dc5	1440	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void)
<>	134:ad3be0349dc5	1441	{
<>	134:ad3be0349dc5	1442	return (READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB));
<>	134:ad3be0349dc5	1443	}
<>	134:ad3be0349dc5	1444	#endif /* SYSCFG_ITLINE28_SR_USART2_GLB */
<>	134:ad3be0349dc5	1445
<>	134:ad3be0349dc5	1446	#if defined(SYSCFG_ITLINE29_SR_USART3_GLB)
<>	134:ad3be0349dc5	1447	/**
<>	134:ad3be0349dc5	1448	* @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28.
<>	134:ad3be0349dc5	1449	* @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3
<>	134:ad3be0349dc5	1450	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1451	*/
<>	134:ad3be0349dc5	1452	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void)
<>	134:ad3be0349dc5	1453	{
<>	134:ad3be0349dc5	1454	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB));
<>	134:ad3be0349dc5	1455	}
<>	134:ad3be0349dc5	1456	#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */
<>	134:ad3be0349dc5	1457
<>	134:ad3be0349dc5	1458	#if defined(SYSCFG_ITLINE29_SR_USART4_GLB)
<>	134:ad3be0349dc5	1459	/**
<>	134:ad3be0349dc5	1460	* @brief Check if USART4 interrupt occurred or not.
<>	134:ad3be0349dc5	1461	* @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4
<>	134:ad3be0349dc5	1462	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1463	*/
<>	134:ad3be0349dc5	1464	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void)
<>	134:ad3be0349dc5	1465	{
<>	134:ad3be0349dc5	1466	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB));
<>	134:ad3be0349dc5	1467	}
<>	134:ad3be0349dc5	1468	#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */
<>	134:ad3be0349dc5	1469
<>	134:ad3be0349dc5	1470	#if defined(SYSCFG_ITLINE29_SR_USART5_GLB)
<>	134:ad3be0349dc5	1471	/**
<>	134:ad3be0349dc5	1472	* @brief Check if USART5 interrupt occurred or not.
<>	134:ad3be0349dc5	1473	* @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5
<>	134:ad3be0349dc5	1474	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1475	*/
<>	134:ad3be0349dc5	1476	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void)
<>	134:ad3be0349dc5	1477	{
<>	134:ad3be0349dc5	1478	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB));
<>	134:ad3be0349dc5	1479	}
<>	134:ad3be0349dc5	1480	#endif /* SYSCFG_ITLINE29_SR_USART5_GLB */
<>	134:ad3be0349dc5	1481
<>	134:ad3be0349dc5	1482	#if defined(SYSCFG_ITLINE29_SR_USART6_GLB)
<>	134:ad3be0349dc5	1483	/**
<>	134:ad3be0349dc5	1484	* @brief Check if USART6 interrupt occurred or not.
<>	134:ad3be0349dc5	1485	* @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6
<>	134:ad3be0349dc5	1486	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1487	*/
<>	134:ad3be0349dc5	1488	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void)
<>	134:ad3be0349dc5	1489	{
<>	134:ad3be0349dc5	1490	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB));
<>	134:ad3be0349dc5	1491	}
<>	134:ad3be0349dc5	1492	#endif /* SYSCFG_ITLINE29_SR_USART6_GLB */
<>	134:ad3be0349dc5	1493
<>	134:ad3be0349dc5	1494	#if defined(SYSCFG_ITLINE29_SR_USART7_GLB)
<>	134:ad3be0349dc5	1495	/**
<>	134:ad3be0349dc5	1496	* @brief Check if USART7 interrupt occurred or not.
<>	134:ad3be0349dc5	1497	* @rmtoll SYSCFG_ITLINE29 SR_USART7_GLB LL_SYSCFG_IsActiveFlag_USART7
<>	134:ad3be0349dc5	1498	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1499	*/
<>	134:ad3be0349dc5	1500	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART7(void)
<>	134:ad3be0349dc5	1501	{
<>	134:ad3be0349dc5	1502	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART7_GLB) == (SYSCFG_ITLINE29_SR_USART7_GLB));
<>	134:ad3be0349dc5	1503	}
<>	134:ad3be0349dc5	1504	#endif /* SYSCFG_ITLINE29_SR_USART7_GLB */
<>	134:ad3be0349dc5	1505
<>	134:ad3be0349dc5	1506	#if defined(SYSCFG_ITLINE29_SR_USART8_GLB)
<>	134:ad3be0349dc5	1507	/**
<>	134:ad3be0349dc5	1508	* @brief Check if USART8 interrupt occurred or not.
<>	134:ad3be0349dc5	1509	* @rmtoll SYSCFG_ITLINE29 SR_USART8_GLB LL_SYSCFG_IsActiveFlag_USART8
<>	134:ad3be0349dc5	1510	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1511	*/
<>	134:ad3be0349dc5	1512	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART8(void)
<>	134:ad3be0349dc5	1513	{
<>	134:ad3be0349dc5	1514	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART8_GLB) == (SYSCFG_ITLINE29_SR_USART8_GLB));
<>	134:ad3be0349dc5	1515	}
<>	134:ad3be0349dc5	1516	#endif /* SYSCFG_ITLINE29_SR_USART8_GLB */
<>	134:ad3be0349dc5	1517
<>	134:ad3be0349dc5	1518	#if defined(SYSCFG_ITLINE30_SR_CAN)
<>	134:ad3be0349dc5	1519	/**
<>	134:ad3be0349dc5	1520	* @brief Check if CAN interrupt occurred or not.
<>	134:ad3be0349dc5	1521	* @rmtoll SYSCFG_ITLINE30 SR_CAN LL_SYSCFG_IsActiveFlag_CAN
<>	134:ad3be0349dc5	1522	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1523	*/
<>	134:ad3be0349dc5	1524	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CAN(void)
<>	134:ad3be0349dc5	1525	{
<>	134:ad3be0349dc5	1526	return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CAN) == (SYSCFG_ITLINE30_SR_CAN));
<>	134:ad3be0349dc5	1527	}
<>	134:ad3be0349dc5	1528	#endif /* SYSCFG_ITLINE30_SR_CAN */
<>	134:ad3be0349dc5	1529
<>	134:ad3be0349dc5	1530	#if defined(SYSCFG_ITLINE30_SR_CEC)
<>	134:ad3be0349dc5	1531	/**
<>	134:ad3be0349dc5	1532	* @brief Check if CEC interrupt occurred or not, combined with EXTI line 27.
<>	134:ad3be0349dc5	1533	* @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC
<>	134:ad3be0349dc5	1534	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1535	*/
<>	134:ad3be0349dc5	1536	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void)
<>	134:ad3be0349dc5	1537	{
<>	134:ad3be0349dc5	1538	return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC));
<>	134:ad3be0349dc5	1539	}
<>	134:ad3be0349dc5	1540	#endif /* SYSCFG_ITLINE30_SR_CEC */
<>	134:ad3be0349dc5	1541
<>	134:ad3be0349dc5	1542	/**
<>	134:ad3be0349dc5	1543	* @brief Set connections to TIMx Break inputs
<>	134:ad3be0349dc5	1544	* @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
<>	134:ad3be0349dc5	1545	* SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
<>	134:ad3be0349dc5	1546	* SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
<>	134:ad3be0349dc5	1547	* @param Break This parameter can be a combination of the following values:
<>	134:ad3be0349dc5	1548	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
<>	134:ad3be0349dc5	1549	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
<>	134:ad3be0349dc5	1550	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
<>	134:ad3be0349dc5	1551	*
<>	134:ad3be0349dc5	1552	* (*) value not defined in all devices
<>	134:ad3be0349dc5	1553	* @retval None
<>	134:ad3be0349dc5	1554	*/
<>	134:ad3be0349dc5	1555	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
<>	134:ad3be0349dc5	1556	{
<>	134:ad3be0349dc5	1557	#if defined(SYSCFG_CFGR2_PVD_LOCK)
<>	134:ad3be0349dc5	1558	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK \| SYSCFG_CFGR2_PVD_LOCK, Break);
<>	134:ad3be0349dc5	1559	#else
<>	134:ad3be0349dc5	1560	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break);
<>	134:ad3be0349dc5	1561	#endif /SYSCFG_CFGR2_PVD_LOCK/
<>	134:ad3be0349dc5	1562	}
<>	134:ad3be0349dc5	1563
<>	134:ad3be0349dc5	1564	/**
<>	134:ad3be0349dc5	1565	* @brief Get connections to TIMx Break inputs
<>	134:ad3be0349dc5	1566	* @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
<>	134:ad3be0349dc5	1567	* SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
<>	134:ad3be0349dc5	1568	* SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
<>	134:ad3be0349dc5	1569	* @retval Returned value can be can be a combination of the following values:
<>	134:ad3be0349dc5	1570	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
<>	134:ad3be0349dc5	1571	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
<>	134:ad3be0349dc5	1572	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
<>	134:ad3be0349dc5	1573	*
<>	134:ad3be0349dc5	1574	* (*) value not defined in all devices
<>	134:ad3be0349dc5	1575	*/
<>	134:ad3be0349dc5	1576	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
<>	134:ad3be0349dc5	1577	{
<>	134:ad3be0349dc5	1578	#if defined(SYSCFG_CFGR2_PVD_LOCK)
<>	134:ad3be0349dc5	1579	return (uint32_t)(READ_BIT(SYSCFG->CFGR2,
<>	134:ad3be0349dc5	1580	SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK \| SYSCFG_CFGR2_PVD_LOCK));
<>	134:ad3be0349dc5	1581	#else
<>	134:ad3be0349dc5	1582	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK));
<>	134:ad3be0349dc5	1583	#endif /SYSCFG_CFGR2_PVD_LOCK/
<>	134:ad3be0349dc5	1584	}
<>	134:ad3be0349dc5	1585
<>	134:ad3be0349dc5	1586	/**
<>	134:ad3be0349dc5	1587	* @brief Check if SRAM parity error detected
<>	134:ad3be0349dc5	1588	* @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_IsActiveFlag_SP
<>	134:ad3be0349dc5	1589	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1590	*/
<>	134:ad3be0349dc5	1591	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
<>	134:ad3be0349dc5	1592	{
<>	134:ad3be0349dc5	1593	return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF));
<>	134:ad3be0349dc5	1594	}
<>	134:ad3be0349dc5	1595
<>	134:ad3be0349dc5	1596	/**
<>	134:ad3be0349dc5	1597	* @brief Clear SRAM parity error flag
<>	134:ad3be0349dc5	1598	* @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_ClearFlag_SP
<>	134:ad3be0349dc5	1599	* @retval None
<>	134:ad3be0349dc5	1600	*/
<>	134:ad3be0349dc5	1601	__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
<>	134:ad3be0349dc5	1602	{
<>	134:ad3be0349dc5	1603	SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF);
<>	134:ad3be0349dc5	1604	}
<>	134:ad3be0349dc5	1605
<>	134:ad3be0349dc5	1606	/**
<>	134:ad3be0349dc5	1607	* @}
<>	134:ad3be0349dc5	1608	*/
<>	134:ad3be0349dc5	1609
<>	134:ad3be0349dc5	1610	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
<>	134:ad3be0349dc5	1611	* @{
<>	134:ad3be0349dc5	1612	*/
<>	134:ad3be0349dc5	1613
<>	134:ad3be0349dc5	1614	/**
<>	134:ad3be0349dc5	1615	* @brief Return the device identifier
<>	134:ad3be0349dc5	1616	* @note For STM32F03x devices, the device ID is 0x444
<>	134:ad3be0349dc5	1617	* @note For STM32F04x devices, the device ID is 0x445.
<>	134:ad3be0349dc5	1618	* @note For STM32F05x devices, the device ID is 0x440
<>	134:ad3be0349dc5	1619	* @note For STM32F07x devices, the device ID is 0x448
<>	134:ad3be0349dc5	1620	* @note For STM32F09x devices, the device ID is 0x442
<>	134:ad3be0349dc5	1621	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
<>	134:ad3be0349dc5	1622	* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
<>	134:ad3be0349dc5	1623	*/
<>	134:ad3be0349dc5	1624	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
<>	134:ad3be0349dc5	1625	{
<>	134:ad3be0349dc5	1626	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
<>	134:ad3be0349dc5	1627	}
<>	134:ad3be0349dc5	1628
<>	134:ad3be0349dc5	1629	/**
<>	134:ad3be0349dc5	1630	* @brief Return the device revision identifier
<>	134:ad3be0349dc5	1631	* @note This field indicates the revision of the device.
<>	134:ad3be0349dc5	1632	For example, it is read as 0x1000 for Revision 1.0.
<>	134:ad3be0349dc5	1633	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
<>	134:ad3be0349dc5	1634	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
<>	134:ad3be0349dc5	1635	*/
<>	134:ad3be0349dc5	1636	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
<>	134:ad3be0349dc5	1637	{
<>	134:ad3be0349dc5	1638	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION);
<>	134:ad3be0349dc5	1639	}
<>	134:ad3be0349dc5	1640
<>	134:ad3be0349dc5	1641	/**
<>	134:ad3be0349dc5	1642	* @brief Enable the Debug Module during STOP mode
<>	134:ad3be0349dc5	1643	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
<>	134:ad3be0349dc5	1644	* @retval None
<>	134:ad3be0349dc5	1645	*/
<>	134:ad3be0349dc5	1646	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
<>	134:ad3be0349dc5	1647	{
<>	134:ad3be0349dc5	1648	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
<>	134:ad3be0349dc5	1649	}
<>	134:ad3be0349dc5	1650
<>	134:ad3be0349dc5	1651	/**
<>	134:ad3be0349dc5	1652	* @brief Disable the Debug Module during STOP mode
<>	134:ad3be0349dc5	1653	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
<>	134:ad3be0349dc5	1654	* @retval None
<>	134:ad3be0349dc5	1655	*/
<>	134:ad3be0349dc5	1656	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
<>	134:ad3be0349dc5	1657	{
<>	134:ad3be0349dc5	1658	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
<>	134:ad3be0349dc5	1659	}
<>	134:ad3be0349dc5	1660
<>	134:ad3be0349dc5	1661	/**
<>	134:ad3be0349dc5	1662	* @brief Enable the Debug Module during STANDBY mode
<>	134:ad3be0349dc5	1663	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
<>	134:ad3be0349dc5	1664	* @retval None
<>	134:ad3be0349dc5	1665	*/
<>	134:ad3be0349dc5	1666	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
<>	134:ad3be0349dc5	1667	{
<>	134:ad3be0349dc5	1668	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
<>	134:ad3be0349dc5	1669	}
<>	134:ad3be0349dc5	1670
<>	134:ad3be0349dc5	1671	/**
<>	134:ad3be0349dc5	1672	* @brief Disable the Debug Module during STANDBY mode
<>	134:ad3be0349dc5	1673	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
<>	134:ad3be0349dc5	1674	* @retval None
<>	134:ad3be0349dc5	1675	*/
<>	134:ad3be0349dc5	1676	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
<>	134:ad3be0349dc5	1677	{
<>	134:ad3be0349dc5	1678	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
<>	134:ad3be0349dc5	1679	}
<>	134:ad3be0349dc5	1680
<>	134:ad3be0349dc5	1681	/**
<>	134:ad3be0349dc5	1682	* @brief Freeze APB1 peripherals (group1 peripherals)
<>	134:ad3be0349dc5	1683	* @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	134:ad3be0349dc5	1684	* DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	134:ad3be0349dc5	1685	* DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	134:ad3be0349dc5	1686	* DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	134:ad3be0349dc5	1687	* DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	134:ad3be0349dc5	1688	* DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	134:ad3be0349dc5	1689	* DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	134:ad3be0349dc5	1690	* DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	134:ad3be0349dc5	1691	* DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<>	134:ad3be0349dc5	1692	* DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
<>	134:ad3be0349dc5	1693	* @param Periphs This parameter can be a combination of the following values:
<>	134:ad3be0349dc5	1694	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
<>	134:ad3be0349dc5	1695	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
<>	134:ad3be0349dc5	1696	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
<>	134:ad3be0349dc5	1697	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
<>	134:ad3be0349dc5	1698	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
<>	134:ad3be0349dc5	1699	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
<>	134:ad3be0349dc5	1700	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
<>	134:ad3be0349dc5	1701	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
<>	134:ad3be0349dc5	1702	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
<>	134:ad3be0349dc5	1703	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
<>	134:ad3be0349dc5	1704	*
<>	134:ad3be0349dc5	1705	* (*) value not defined in all devices
<>	134:ad3be0349dc5	1706	* @retval None
<>	134:ad3be0349dc5	1707	*/
<>	134:ad3be0349dc5	1708	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
<>	134:ad3be0349dc5	1709	{
<>	134:ad3be0349dc5	1710	SET_BIT(DBGMCU->APB1FZ, Periphs);
<>	134:ad3be0349dc5	1711	}
<>	134:ad3be0349dc5	1712
<>	134:ad3be0349dc5	1713	/**
<>	134:ad3be0349dc5	1714	* @brief Unfreeze APB1 peripherals (group1 peripherals)
<>	134:ad3be0349dc5	1715	* @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	134:ad3be0349dc5	1716	* DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	134:ad3be0349dc5	1717	* DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	134:ad3be0349dc5	1718	* DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	134:ad3be0349dc5	1719	* DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	134:ad3be0349dc5	1720	* DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	134:ad3be0349dc5	1721	* DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	134:ad3be0349dc5	1722	* DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	134:ad3be0349dc5	1723	* DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<>	134:ad3be0349dc5	1724	* DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
<>	134:ad3be0349dc5	1725	* @param Periphs This parameter can be a combination of the following values:
<>	134:ad3be0349dc5	1726	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
<>	134:ad3be0349dc5	1727	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
<>	134:ad3be0349dc5	1728	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
<>	134:ad3be0349dc5	1729	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
<>	134:ad3be0349dc5	1730	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
<>	134:ad3be0349dc5	1731	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
<>	134:ad3be0349dc5	1732	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
<>	134:ad3be0349dc5	1733	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
<>	134:ad3be0349dc5	1734	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
<>	134:ad3be0349dc5	1735	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
<>	134:ad3be0349dc5	1736	*
<>	134:ad3be0349dc5	1737	* (*) value not defined in all devices
<>	134:ad3be0349dc5	1738	* @retval None
<>	134:ad3be0349dc5	1739	*/
<>	134:ad3be0349dc5	1740	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
<>	134:ad3be0349dc5	1741	{
<>	134:ad3be0349dc5	1742	CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
<>	134:ad3be0349dc5	1743	}
<>	134:ad3be0349dc5	1744
<>	134:ad3be0349dc5	1745	/**
<>	134:ad3be0349dc5	1746	* @brief Freeze APB1 peripherals (group2 peripherals)
<>	134:ad3be0349dc5	1747	* @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
<>	134:ad3be0349dc5	1748	* DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
<>	134:ad3be0349dc5	1749	* DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
<>	134:ad3be0349dc5	1750	* DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
<>	134:ad3be0349dc5	1751	* @param Periphs This parameter can be a combination of the following values:
<>	134:ad3be0349dc5	1752	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
<>	134:ad3be0349dc5	1753	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*)
<>	134:ad3be0349dc5	1754	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
<>	134:ad3be0349dc5	1755	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
<>	134:ad3be0349dc5	1756	*
<>	134:ad3be0349dc5	1757	* (*) value not defined in all devices
<>	134:ad3be0349dc5	1758	* @retval None
<>	134:ad3be0349dc5	1759	*/
<>	134:ad3be0349dc5	1760	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
<>	134:ad3be0349dc5	1761	{
<>	134:ad3be0349dc5	1762	SET_BIT(DBGMCU->APB2FZ, Periphs);
<>	134:ad3be0349dc5	1763	}
<>	134:ad3be0349dc5	1764
<>	134:ad3be0349dc5	1765	/**
<>	134:ad3be0349dc5	1766	* @brief Unfreeze APB1 peripherals (group2 peripherals)
<>	134:ad3be0349dc5	1767	* @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
<>	134:ad3be0349dc5	1768	* DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
<>	134:ad3be0349dc5	1769	* DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
<>	134:ad3be0349dc5	1770	* DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
<>	134:ad3be0349dc5	1771	* @param Periphs This parameter can be a combination of the following values:
<>	134:ad3be0349dc5	1772	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
<>	134:ad3be0349dc5	1773	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*)
<>	134:ad3be0349dc5	1774	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
<>	134:ad3be0349dc5	1775	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
<>	134:ad3be0349dc5	1776	*
<>	134:ad3be0349dc5	1777	* (*) value not defined in all devices
<>	134:ad3be0349dc5	1778	* @retval None
<>	134:ad3be0349dc5	1779	*/
<>	134:ad3be0349dc5	1780	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
<>	134:ad3be0349dc5	1781	{
<>	134:ad3be0349dc5	1782	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
<>	134:ad3be0349dc5	1783	}
<>	134:ad3be0349dc5	1784	/**
<>	134:ad3be0349dc5	1785	* @}
<>	134:ad3be0349dc5	1786	*/
<>	134:ad3be0349dc5	1787
<>	134:ad3be0349dc5	1788	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
<>	134:ad3be0349dc5	1789	* @{
<>	134:ad3be0349dc5	1790	*/
<>	134:ad3be0349dc5	1791
<>	134:ad3be0349dc5	1792	/**
<>	134:ad3be0349dc5	1793	* @brief Set FLASH Latency
<>	134:ad3be0349dc5	1794	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
<>	134:ad3be0349dc5	1795	* @param Latency This parameter can be one of the following values:
<>	134:ad3be0349dc5	1796	* @arg @ref LL_FLASH_LATENCY_0
<>	134:ad3be0349dc5	1797	* @arg @ref LL_FLASH_LATENCY_1
<>	134:ad3be0349dc5	1798	* @retval None
<>	134:ad3be0349dc5	1799	*/
<>	134:ad3be0349dc5	1800	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
<>	134:ad3be0349dc5	1801	{
<>	134:ad3be0349dc5	1802	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
<>	134:ad3be0349dc5	1803	}
<>	134:ad3be0349dc5	1804
<>	134:ad3be0349dc5	1805	/**
<>	134:ad3be0349dc5	1806	* @brief Get FLASH Latency
<>	134:ad3be0349dc5	1807	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
<>	134:ad3be0349dc5	1808	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1809	* @arg @ref LL_FLASH_LATENCY_0
<>	134:ad3be0349dc5	1810	* @arg @ref LL_FLASH_LATENCY_1
<>	134:ad3be0349dc5	1811	*/
<>	134:ad3be0349dc5	1812	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
<>	134:ad3be0349dc5	1813	{
<>	134:ad3be0349dc5	1814	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
<>	134:ad3be0349dc5	1815	}
<>	134:ad3be0349dc5	1816
<>	134:ad3be0349dc5	1817	/**
<>	134:ad3be0349dc5	1818	* @brief Enable Prefetch
<>	134:ad3be0349dc5	1819	* @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
<>	134:ad3be0349dc5	1820	* @retval None
<>	134:ad3be0349dc5	1821	*/
<>	134:ad3be0349dc5	1822	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
<>	134:ad3be0349dc5	1823	{
<>	134:ad3be0349dc5	1824	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
<>	134:ad3be0349dc5	1825	}
<>	134:ad3be0349dc5	1826
<>	134:ad3be0349dc5	1827	/**
<>	134:ad3be0349dc5	1828	* @brief Disable Prefetch
<>	134:ad3be0349dc5	1829	* @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
<>	134:ad3be0349dc5	1830	* @retval None
<>	134:ad3be0349dc5	1831	*/
<>	134:ad3be0349dc5	1832	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
<>	134:ad3be0349dc5	1833	{
<>	134:ad3be0349dc5	1834	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
<>	134:ad3be0349dc5	1835	}
<>	134:ad3be0349dc5	1836
<>	134:ad3be0349dc5	1837	/**
<>	134:ad3be0349dc5	1838	* @brief Check if Prefetch buffer is enabled
<>	134:ad3be0349dc5	1839	* @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
<>	134:ad3be0349dc5	1840	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1841	*/
<>	134:ad3be0349dc5	1842	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
<>	134:ad3be0349dc5	1843	{
<>	134:ad3be0349dc5	1844	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
<>	134:ad3be0349dc5	1845	}
<>	134:ad3be0349dc5	1846
<>	134:ad3be0349dc5	1847
<>	134:ad3be0349dc5	1848
<>	134:ad3be0349dc5	1849	/**
<>	134:ad3be0349dc5	1850	* @}
<>	134:ad3be0349dc5	1851	*/
<>	134:ad3be0349dc5	1852
<>	134:ad3be0349dc5	1853	/**
<>	134:ad3be0349dc5	1854	* @}
<>	134:ad3be0349dc5	1855	*/
<>	134:ad3be0349dc5	1856
<>	134:ad3be0349dc5	1857	/**
<>	134:ad3be0349dc5	1858	* @}
<>	134:ad3be0349dc5	1859	*/
<>	134:ad3be0349dc5	1860
<>	134:ad3be0349dc5	1861	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) */
<>	134:ad3be0349dc5	1862
<>	134:ad3be0349dc5	1863	/**
<>	134:ad3be0349dc5	1864	* @}
<>	134:ad3be0349dc5	1865	*/
<>	134:ad3be0349dc5	1866
<>	134:ad3be0349dc5	1867	#ifdef __cplusplus
<>	134:ad3be0349dc5	1868	}
<>	134:ad3be0349dc5	1869	#endif
<>	134:ad3be0349dc5	1870
<>	134:ad3be0349dc5	1871	#endif /* __STM32F0xx_LL_SYSTEM_H */
<>	134:ad3be0349dc5	1872
<>	134:ad3be0349dc5	1873	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/