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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
134:ad3be0349dc5
Child:
160:5571c4ff569f
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 134:ad3be0349dc5 1 /**
<> 134:ad3be0349dc5 2 ******************************************************************************
<> 134:ad3be0349dc5 3 * @file stm32f0xx_ll_dma.h
<> 134:ad3be0349dc5 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.4.0
<> 134:ad3be0349dc5 6 * @date 27-May-2016
<> 134:ad3be0349dc5 7 * @brief Header file of DMA LL module.
<> 134:ad3be0349dc5 8 ******************************************************************************
<> 134:ad3be0349dc5 9 * @attention
<> 134:ad3be0349dc5 10 *
<> 134:ad3be0349dc5 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 134:ad3be0349dc5 12 *
<> 134:ad3be0349dc5 13 * Redistribution and use in source and binary forms, with or without modification,
<> 134:ad3be0349dc5 14 * are permitted provided that the following conditions are met:
<> 134:ad3be0349dc5 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 134:ad3be0349dc5 16 * this list of conditions and the following disclaimer.
<> 134:ad3be0349dc5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 134:ad3be0349dc5 18 * this list of conditions and the following disclaimer in the documentation
<> 134:ad3be0349dc5 19 * and/or other materials provided with the distribution.
<> 134:ad3be0349dc5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 134:ad3be0349dc5 21 * may be used to endorse or promote products derived from this software
<> 134:ad3be0349dc5 22 * without specific prior written permission.
<> 134:ad3be0349dc5 23 *
<> 134:ad3be0349dc5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 134:ad3be0349dc5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 134:ad3be0349dc5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 134:ad3be0349dc5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 134:ad3be0349dc5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 134:ad3be0349dc5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 134:ad3be0349dc5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 134:ad3be0349dc5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 134:ad3be0349dc5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 134:ad3be0349dc5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 134:ad3be0349dc5 34 *
<> 134:ad3be0349dc5 35 ******************************************************************************
<> 134:ad3be0349dc5 36 */
<> 134:ad3be0349dc5 37
<> 134:ad3be0349dc5 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 134:ad3be0349dc5 39 #ifndef __STM32F0xx_LL_DMA_H
<> 134:ad3be0349dc5 40 #define __STM32F0xx_LL_DMA_H
<> 134:ad3be0349dc5 41
<> 134:ad3be0349dc5 42 #ifdef __cplusplus
<> 134:ad3be0349dc5 43 extern "C" {
<> 134:ad3be0349dc5 44 #endif
<> 134:ad3be0349dc5 45
<> 134:ad3be0349dc5 46 /* Includes ------------------------------------------------------------------*/
<> 134:ad3be0349dc5 47 #include "stm32f0xx.h"
<> 134:ad3be0349dc5 48
<> 134:ad3be0349dc5 49 /** @addtogroup STM32F0xx_LL_Driver
<> 134:ad3be0349dc5 50 * @{
<> 134:ad3be0349dc5 51 */
<> 134:ad3be0349dc5 52
<> 134:ad3be0349dc5 53 #if defined (DMA1) || defined (DMA2)
<> 134:ad3be0349dc5 54
<> 134:ad3be0349dc5 55 /** @defgroup DMA_LL DMA
<> 134:ad3be0349dc5 56 * @{
<> 134:ad3be0349dc5 57 */
<> 134:ad3be0349dc5 58
<> 134:ad3be0349dc5 59 /* Private types -------------------------------------------------------------*/
<> 134:ad3be0349dc5 60 /* Private variables ---------------------------------------------------------*/
<> 134:ad3be0349dc5 61 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
<> 134:ad3be0349dc5 62 * @{
<> 134:ad3be0349dc5 63 */
<> 134:ad3be0349dc5 64 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
<> 134:ad3be0349dc5 65 static const uint8_t CHANNEL_OFFSET_TAB[] =
<> 134:ad3be0349dc5 66 {
<> 134:ad3be0349dc5 67 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
<> 134:ad3be0349dc5 68 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
<> 134:ad3be0349dc5 69 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
<> 134:ad3be0349dc5 70 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
<> 134:ad3be0349dc5 71 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
<> 134:ad3be0349dc5 72 #if defined(DMA1_Channel6)
<> 134:ad3be0349dc5 73 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
<> 134:ad3be0349dc5 74 #endif /*DMA1_Channel6*/
<> 134:ad3be0349dc5 75 #if defined(DMA1_Channel7)
<> 134:ad3be0349dc5 76 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
<> 134:ad3be0349dc5 77 #endif /*DMA1_Channel7*/
<> 134:ad3be0349dc5 78 };
<> 134:ad3be0349dc5 79 /**
<> 134:ad3be0349dc5 80 * @}
<> 134:ad3be0349dc5 81 */
<> 134:ad3be0349dc5 82
<> 134:ad3be0349dc5 83 /* Private constants ---------------------------------------------------------*/
<> 134:ad3be0349dc5 84 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
<> 134:ad3be0349dc5 85 * @{
<> 134:ad3be0349dc5 86 */
<> 134:ad3be0349dc5 87 /* Define used to get CSELR register offset */
<> 134:ad3be0349dc5 88 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
<> 134:ad3be0349dc5 89
<> 134:ad3be0349dc5 90 /* Defines used for the bit position in the register and perform offsets */
<> 134:ad3be0349dc5 91 #define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U)
<> 134:ad3be0349dc5 92 /**
<> 134:ad3be0349dc5 93 * @}
<> 134:ad3be0349dc5 94 */
<> 134:ad3be0349dc5 95
<> 134:ad3be0349dc5 96 /* Private macros ------------------------------------------------------------*/
<> 134:ad3be0349dc5 97 #if defined(USE_FULL_LL_DRIVER)
<> 134:ad3be0349dc5 98 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
<> 134:ad3be0349dc5 99 * @{
<> 134:ad3be0349dc5 100 */
<> 134:ad3be0349dc5 101 /**
<> 134:ad3be0349dc5 102 * @}
<> 134:ad3be0349dc5 103 */
<> 134:ad3be0349dc5 104 #endif /*USE_FULL_LL_DRIVER*/
<> 134:ad3be0349dc5 105
<> 134:ad3be0349dc5 106 /* Exported types ------------------------------------------------------------*/
<> 134:ad3be0349dc5 107 #if defined(USE_FULL_LL_DRIVER)
<> 134:ad3be0349dc5 108 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
<> 134:ad3be0349dc5 109 * @{
<> 134:ad3be0349dc5 110 */
<> 134:ad3be0349dc5 111 typedef struct
<> 134:ad3be0349dc5 112 {
<> 134:ad3be0349dc5 113 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
<> 134:ad3be0349dc5 114 or as Source base address in case of memory to memory transfer direction.
<> 134:ad3be0349dc5 115
<> 134:ad3be0349dc5 116 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<> 134:ad3be0349dc5 117
<> 134:ad3be0349dc5 118 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
<> 134:ad3be0349dc5 119 or as Destination base address in case of memory to memory transfer direction.
<> 134:ad3be0349dc5 120
<> 134:ad3be0349dc5 121 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
<> 134:ad3be0349dc5 122
<> 134:ad3be0349dc5 123 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<> 134:ad3be0349dc5 124 from memory to memory or from peripheral to memory.
<> 134:ad3be0349dc5 125 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
<> 134:ad3be0349dc5 126
<> 134:ad3be0349dc5 127 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
<> 134:ad3be0349dc5 128
<> 134:ad3be0349dc5 129 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
<> 134:ad3be0349dc5 130 This parameter can be a value of @ref DMA_LL_EC_MODE
<> 134:ad3be0349dc5 131 @note: The circular buffer mode cannot be used if the memory to memory
<> 134:ad3be0349dc5 132 data transfer direction is configured on the selected Channel
<> 134:ad3be0349dc5 133
<> 134:ad3be0349dc5 134 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
<> 134:ad3be0349dc5 135
<> 134:ad3be0349dc5 136 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
<> 134:ad3be0349dc5 137 is incremented or not.
<> 134:ad3be0349dc5 138 This parameter can be a value of @ref DMA_LL_EC_PERIPH
<> 134:ad3be0349dc5 139
<> 134:ad3be0349dc5 140 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
<> 134:ad3be0349dc5 141
<> 134:ad3be0349dc5 142 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
<> 134:ad3be0349dc5 143 is incremented or not.
<> 134:ad3be0349dc5 144 This parameter can be a value of @ref DMA_LL_EC_MEMORY
<> 134:ad3be0349dc5 145
<> 134:ad3be0349dc5 146 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
<> 134:ad3be0349dc5 147
<> 134:ad3be0349dc5 148 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
<> 134:ad3be0349dc5 149 in case of memory to memory transfer direction.
<> 134:ad3be0349dc5 150 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
<> 134:ad3be0349dc5 151
<> 134:ad3be0349dc5 152 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
<> 134:ad3be0349dc5 153
<> 134:ad3be0349dc5 154 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
<> 134:ad3be0349dc5 155 in case of memory to memory transfer direction.
<> 134:ad3be0349dc5 156 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
<> 134:ad3be0349dc5 157
<> 134:ad3be0349dc5 158 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
<> 134:ad3be0349dc5 159
<> 134:ad3be0349dc5 160 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
<> 134:ad3be0349dc5 161 The data unit is equal to the source buffer configuration set in PeripheralSize
<> 134:ad3be0349dc5 162 or MemorySize parameters depending in the transfer direction.
<> 134:ad3be0349dc5 163 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
<> 134:ad3be0349dc5 164
<> 134:ad3be0349dc5 165 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
<> 134:ad3be0349dc5 166 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 134:ad3be0349dc5 167
<> 134:ad3be0349dc5 168 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
<> 134:ad3be0349dc5 169 This parameter can be a value of @ref DMA_LL_EC_REQUEST
<> 134:ad3be0349dc5 170
<> 134:ad3be0349dc5 171 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
<> 134:ad3be0349dc5 172 #endif
<> 134:ad3be0349dc5 173
<> 134:ad3be0349dc5 174 uint32_t Priority; /*!< Specifies the channel priority level.
<> 134:ad3be0349dc5 175 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
<> 134:ad3be0349dc5 176
<> 134:ad3be0349dc5 177 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
<> 134:ad3be0349dc5 178
<> 134:ad3be0349dc5 179 } LL_DMA_InitTypeDef;
<> 134:ad3be0349dc5 180 /**
<> 134:ad3be0349dc5 181 * @}
<> 134:ad3be0349dc5 182 */
<> 134:ad3be0349dc5 183 #endif /*USE_FULL_LL_DRIVER*/
<> 134:ad3be0349dc5 184
<> 134:ad3be0349dc5 185 /* Exported constants --------------------------------------------------------*/
<> 134:ad3be0349dc5 186 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
<> 134:ad3be0349dc5 187 * @{
<> 134:ad3be0349dc5 188 */
<> 134:ad3be0349dc5 189 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
<> 134:ad3be0349dc5 190 * @brief Flags defines which can be used with LL_DMA_WriteReg function
<> 134:ad3be0349dc5 191 * @{
<> 134:ad3be0349dc5 192 */
<> 134:ad3be0349dc5 193 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
<> 134:ad3be0349dc5 194 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
<> 134:ad3be0349dc5 195 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
<> 134:ad3be0349dc5 196 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
<> 134:ad3be0349dc5 197 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
<> 134:ad3be0349dc5 198 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
<> 134:ad3be0349dc5 199 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
<> 134:ad3be0349dc5 200 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
<> 134:ad3be0349dc5 201 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
<> 134:ad3be0349dc5 202 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
<> 134:ad3be0349dc5 203 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
<> 134:ad3be0349dc5 204 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
<> 134:ad3be0349dc5 205 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
<> 134:ad3be0349dc5 206 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
<> 134:ad3be0349dc5 207 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
<> 134:ad3be0349dc5 208 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
<> 134:ad3be0349dc5 209 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
<> 134:ad3be0349dc5 210 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
<> 134:ad3be0349dc5 211 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
<> 134:ad3be0349dc5 212 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
<> 134:ad3be0349dc5 213 #if defined(DMA1_Channel6)
<> 134:ad3be0349dc5 214 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
<> 134:ad3be0349dc5 215 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
<> 134:ad3be0349dc5 216 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
<> 134:ad3be0349dc5 217 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
<> 134:ad3be0349dc5 218 #endif
<> 134:ad3be0349dc5 219 #if defined(DMA1_Channel7)
<> 134:ad3be0349dc5 220 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
<> 134:ad3be0349dc5 221 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
<> 134:ad3be0349dc5 222 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
<> 134:ad3be0349dc5 223 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
<> 134:ad3be0349dc5 224 #endif
<> 134:ad3be0349dc5 225 /**
<> 134:ad3be0349dc5 226 * @}
<> 134:ad3be0349dc5 227 */
<> 134:ad3be0349dc5 228
<> 134:ad3be0349dc5 229 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
<> 134:ad3be0349dc5 230 * @brief Flags defines which can be used with LL_DMA_ReadReg function
<> 134:ad3be0349dc5 231 * @{
<> 134:ad3be0349dc5 232 */
<> 134:ad3be0349dc5 233 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
<> 134:ad3be0349dc5 234 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
<> 134:ad3be0349dc5 235 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
<> 134:ad3be0349dc5 236 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
<> 134:ad3be0349dc5 237 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
<> 134:ad3be0349dc5 238 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
<> 134:ad3be0349dc5 239 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
<> 134:ad3be0349dc5 240 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
<> 134:ad3be0349dc5 241 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
<> 134:ad3be0349dc5 242 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
<> 134:ad3be0349dc5 243 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
<> 134:ad3be0349dc5 244 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
<> 134:ad3be0349dc5 245 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
<> 134:ad3be0349dc5 246 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
<> 134:ad3be0349dc5 247 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
<> 134:ad3be0349dc5 248 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
<> 134:ad3be0349dc5 249 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
<> 134:ad3be0349dc5 250 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
<> 134:ad3be0349dc5 251 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
<> 134:ad3be0349dc5 252 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
<> 134:ad3be0349dc5 253 #if defined(DMA1_Channel6)
<> 134:ad3be0349dc5 254 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
<> 134:ad3be0349dc5 255 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
<> 134:ad3be0349dc5 256 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
<> 134:ad3be0349dc5 257 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
<> 134:ad3be0349dc5 258 #endif
<> 134:ad3be0349dc5 259 #if defined(DMA1_Channel7)
<> 134:ad3be0349dc5 260 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
<> 134:ad3be0349dc5 261 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
<> 134:ad3be0349dc5 262 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
<> 134:ad3be0349dc5 263 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
<> 134:ad3be0349dc5 264 #endif
<> 134:ad3be0349dc5 265 /**
<> 134:ad3be0349dc5 266 * @}
<> 134:ad3be0349dc5 267 */
<> 134:ad3be0349dc5 268
<> 134:ad3be0349dc5 269 /** @defgroup DMA_LL_EC_IT IT Defines
<> 134:ad3be0349dc5 270 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
<> 134:ad3be0349dc5 271 * @{
<> 134:ad3be0349dc5 272 */
<> 134:ad3be0349dc5 273 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
<> 134:ad3be0349dc5 274 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
<> 134:ad3be0349dc5 275 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
<> 134:ad3be0349dc5 276 /**
<> 134:ad3be0349dc5 277 * @}
<> 134:ad3be0349dc5 278 */
<> 134:ad3be0349dc5 279
<> 134:ad3be0349dc5 280 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
<> 134:ad3be0349dc5 281 * @{
<> 134:ad3be0349dc5 282 */
<> 134:ad3be0349dc5 283 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /*!< DMA Channel 1 */
<> 134:ad3be0349dc5 284 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /*!< DMA Channel 2 */
<> 134:ad3be0349dc5 285 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /*!< DMA Channel 3 */
<> 134:ad3be0349dc5 286 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /*!< DMA Channel 4 */
<> 134:ad3be0349dc5 287 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /*!< DMA Channel 5 */
<> 134:ad3be0349dc5 288 #if defined(DMA1_Channel6)
<> 134:ad3be0349dc5 289 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /*!< DMA Channel 6 */
<> 134:ad3be0349dc5 290 #endif
<> 134:ad3be0349dc5 291 #if defined(DMA1_Channel7)
<> 134:ad3be0349dc5 292 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /*!< DMA Channel 7 */
<> 134:ad3be0349dc5 293 #endif
<> 134:ad3be0349dc5 294 #if defined(USE_FULL_LL_DRIVER)
<> 134:ad3be0349dc5 295 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
<> 134:ad3be0349dc5 296 #endif /*USE_FULL_LL_DRIVER*/
<> 134:ad3be0349dc5 297 /**
<> 134:ad3be0349dc5 298 * @}
<> 134:ad3be0349dc5 299 */
<> 134:ad3be0349dc5 300
<> 134:ad3be0349dc5 301 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
<> 134:ad3be0349dc5 302 * @{
<> 134:ad3be0349dc5 303 */
<> 134:ad3be0349dc5 304 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
<> 134:ad3be0349dc5 305 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
<> 134:ad3be0349dc5 306 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
<> 134:ad3be0349dc5 307 /**
<> 134:ad3be0349dc5 308 * @}
<> 134:ad3be0349dc5 309 */
<> 134:ad3be0349dc5 310
<> 134:ad3be0349dc5 311 /** @defgroup DMA_LL_EC_MODE Transfer mode
<> 134:ad3be0349dc5 312 * @{
<> 134:ad3be0349dc5 313 */
<> 134:ad3be0349dc5 314 #define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */
<> 134:ad3be0349dc5 315 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
<> 134:ad3be0349dc5 316 /**
<> 134:ad3be0349dc5 317 * @}
<> 134:ad3be0349dc5 318 */
<> 134:ad3be0349dc5 319
<> 134:ad3be0349dc5 320 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
<> 134:ad3be0349dc5 321 * @{
<> 134:ad3be0349dc5 322 */
<> 134:ad3be0349dc5 323 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
<> 134:ad3be0349dc5 324 #define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */
<> 134:ad3be0349dc5 325 /**
<> 134:ad3be0349dc5 326 * @}
<> 134:ad3be0349dc5 327 */
<> 134:ad3be0349dc5 328
<> 134:ad3be0349dc5 329 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
<> 134:ad3be0349dc5 330 * @{
<> 134:ad3be0349dc5 331 */
<> 134:ad3be0349dc5 332 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
<> 134:ad3be0349dc5 333 #define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */
<> 134:ad3be0349dc5 334 /**
<> 134:ad3be0349dc5 335 * @}
<> 134:ad3be0349dc5 336 */
<> 134:ad3be0349dc5 337
<> 134:ad3be0349dc5 338 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
<> 134:ad3be0349dc5 339 * @{
<> 134:ad3be0349dc5 340 */
<> 134:ad3be0349dc5 341 #define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */
<> 134:ad3be0349dc5 342 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
<> 134:ad3be0349dc5 343 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
<> 134:ad3be0349dc5 344 /**
<> 134:ad3be0349dc5 345 * @}
<> 134:ad3be0349dc5 346 */
<> 134:ad3be0349dc5 347
<> 134:ad3be0349dc5 348 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
<> 134:ad3be0349dc5 349 * @{
<> 134:ad3be0349dc5 350 */
<> 134:ad3be0349dc5 351 #define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */
<> 134:ad3be0349dc5 352 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
<> 134:ad3be0349dc5 353 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
<> 134:ad3be0349dc5 354 /**
<> 134:ad3be0349dc5 355 * @}
<> 134:ad3be0349dc5 356 */
<> 134:ad3be0349dc5 357
<> 134:ad3be0349dc5 358 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
<> 134:ad3be0349dc5 359 * @{
<> 134:ad3be0349dc5 360 */
<> 134:ad3be0349dc5 361 #define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */
<> 134:ad3be0349dc5 362 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
<> 134:ad3be0349dc5 363 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
<> 134:ad3be0349dc5 364 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
<> 134:ad3be0349dc5 365 /**
<> 134:ad3be0349dc5 366 * @}
<> 134:ad3be0349dc5 367 */
<> 134:ad3be0349dc5 368
<> 134:ad3be0349dc5 369 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 134:ad3be0349dc5 370 /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
<> 134:ad3be0349dc5 371 * @{
<> 134:ad3be0349dc5 372 */
<> 134:ad3be0349dc5 373 #define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U) /*!< DMA peripheral request 0 */
<> 134:ad3be0349dc5 374 #define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U) /*!< DMA peripheral request 1 */
<> 134:ad3be0349dc5 375 #define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U) /*!< DMA peripheral request 2 */
<> 134:ad3be0349dc5 376 #define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U) /*!< DMA peripheral request 3 */
<> 134:ad3be0349dc5 377 #define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U) /*!< DMA peripheral request 4 */
<> 134:ad3be0349dc5 378 #define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U) /*!< DMA peripheral request 5 */
<> 134:ad3be0349dc5 379 #define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U) /*!< DMA peripheral request 6 */
<> 134:ad3be0349dc5 380 #define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U) /*!< DMA peripheral request 7 */
<> 134:ad3be0349dc5 381 #define LL_DMA_REQUEST_8 ((uint32_t)0x00000008U) /*!< DMA peripheral request 8 */
<> 134:ad3be0349dc5 382 #define LL_DMA_REQUEST_9 ((uint32_t)0x00000009U) /*!< DMA peripheral request 9 */
<> 134:ad3be0349dc5 383 #define LL_DMA_REQUEST_10 ((uint32_t)0x0000000AU) /*!< DMA peripheral request 10 */
<> 134:ad3be0349dc5 384 #define LL_DMA_REQUEST_11 ((uint32_t)0x0000000BU) /*!< DMA peripheral request 11 */
<> 134:ad3be0349dc5 385 #define LL_DMA_REQUEST_12 ((uint32_t)0x0000000CU) /*!< DMA peripheral request 12 */
<> 134:ad3be0349dc5 386 #define LL_DMA_REQUEST_13 ((uint32_t)0x0000000DU) /*!< DMA peripheral request 13 */
<> 134:ad3be0349dc5 387 #define LL_DMA_REQUEST_14 ((uint32_t)0x0000000EU) /*!< DMA peripheral request 14 */
<> 134:ad3be0349dc5 388 #define LL_DMA_REQUEST_15 ((uint32_t)0x0000000FU) /*!< DMA peripheral request 15 */
<> 134:ad3be0349dc5 389 /**
<> 134:ad3be0349dc5 390 * @}
<> 134:ad3be0349dc5 391 */
<> 134:ad3be0349dc5 392 #endif
<> 134:ad3be0349dc5 393
<> 134:ad3be0349dc5 394 /**
<> 134:ad3be0349dc5 395 * @}
<> 134:ad3be0349dc5 396 */
<> 134:ad3be0349dc5 397
<> 134:ad3be0349dc5 398 /* Exported macro ------------------------------------------------------------*/
<> 134:ad3be0349dc5 399 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
<> 134:ad3be0349dc5 400 * @{
<> 134:ad3be0349dc5 401 */
<> 134:ad3be0349dc5 402
<> 134:ad3be0349dc5 403 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
<> 134:ad3be0349dc5 404 * @{
<> 134:ad3be0349dc5 405 */
<> 134:ad3be0349dc5 406 /**
<> 134:ad3be0349dc5 407 * @brief Write a value in DMA register
<> 134:ad3be0349dc5 408 * @param __INSTANCE__ DMA Instance
<> 134:ad3be0349dc5 409 * @param __REG__ Register to be written
<> 134:ad3be0349dc5 410 * @param __VALUE__ Value to be written in the register
<> 134:ad3be0349dc5 411 * @retval None
<> 134:ad3be0349dc5 412 */
<> 134:ad3be0349dc5 413 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 134:ad3be0349dc5 414
<> 134:ad3be0349dc5 415 /**
<> 134:ad3be0349dc5 416 * @brief Read a value in DMA register
<> 134:ad3be0349dc5 417 * @param __INSTANCE__ DMA Instance
<> 134:ad3be0349dc5 418 * @param __REG__ Register to be read
<> 134:ad3be0349dc5 419 * @retval Register value
<> 134:ad3be0349dc5 420 */
<> 134:ad3be0349dc5 421 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 134:ad3be0349dc5 422 /**
<> 134:ad3be0349dc5 423 * @}
<> 134:ad3be0349dc5 424 */
<> 134:ad3be0349dc5 425
<> 134:ad3be0349dc5 426 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
<> 134:ad3be0349dc5 427 * @{
<> 134:ad3be0349dc5 428 */
<> 134:ad3be0349dc5 429 /**
<> 134:ad3be0349dc5 430 * @brief Convert DMAx_Channely into DMAx
<> 134:ad3be0349dc5 431 * @param __CHANNEL_INSTANCE__ DMAx_Channely
<> 134:ad3be0349dc5 432 * @retval DMAx
<> 134:ad3be0349dc5 433 */
<> 134:ad3be0349dc5 434 #if defined(DMA2)
<> 134:ad3be0349dc5 435 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
<> 134:ad3be0349dc5 436 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
<> 134:ad3be0349dc5 437 #else
<> 134:ad3be0349dc5 438 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
<> 134:ad3be0349dc5 439 #endif
<> 134:ad3be0349dc5 440
<> 134:ad3be0349dc5 441 /**
<> 134:ad3be0349dc5 442 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
<> 134:ad3be0349dc5 443 * @param __CHANNEL_INSTANCE__ DMAx_Channely
<> 134:ad3be0349dc5 444 * @retval LL_DMA_CHANNEL_y
<> 134:ad3be0349dc5 445 */
<> 134:ad3be0349dc5 446 #if defined (DMA2)
<> 134:ad3be0349dc5 447 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<> 134:ad3be0349dc5 448 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 134:ad3be0349dc5 449 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 134:ad3be0349dc5 450 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 134:ad3be0349dc5 451 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 134:ad3be0349dc5 452 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 134:ad3be0349dc5 453 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 134:ad3be0349dc5 454 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 134:ad3be0349dc5 455 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 134:ad3be0349dc5 456 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 134:ad3be0349dc5 457 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 134:ad3be0349dc5 458 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 134:ad3be0349dc5 459 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<> 134:ad3be0349dc5 460 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
<> 134:ad3be0349dc5 461 LL_DMA_CHANNEL_7)
<> 134:ad3be0349dc5 462 #else
<> 134:ad3be0349dc5 463 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 134:ad3be0349dc5 464 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 134:ad3be0349dc5 465 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 134:ad3be0349dc5 466 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 134:ad3be0349dc5 467 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 134:ad3be0349dc5 468 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 134:ad3be0349dc5 469 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 134:ad3be0349dc5 470 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 134:ad3be0349dc5 471 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 134:ad3be0349dc5 472 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 134:ad3be0349dc5 473 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 134:ad3be0349dc5 474 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<> 134:ad3be0349dc5 475 LL_DMA_CHANNEL_7)
<> 134:ad3be0349dc5 476 #endif
<> 134:ad3be0349dc5 477 #else
<> 134:ad3be0349dc5 478 #if defined (DMA1_Channel6) && defined (DMA1_Channel7)
<> 134:ad3be0349dc5 479 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 134:ad3be0349dc5 480 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 134:ad3be0349dc5 481 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 134:ad3be0349dc5 482 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 134:ad3be0349dc5 483 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 134:ad3be0349dc5 484 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 134:ad3be0349dc5 485 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
<> 134:ad3be0349dc5 486 LL_DMA_CHANNEL_7)
<> 134:ad3be0349dc5 487 #elif defined (DMA1_Channel6)
<> 134:ad3be0349dc5 488 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 134:ad3be0349dc5 489 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 134:ad3be0349dc5 490 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 134:ad3be0349dc5 491 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 134:ad3be0349dc5 492 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 134:ad3be0349dc5 493 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
<> 134:ad3be0349dc5 494 LL_DMA_CHANNEL_6)
<> 134:ad3be0349dc5 495 #else
<> 134:ad3be0349dc5 496 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
<> 134:ad3be0349dc5 497 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
<> 134:ad3be0349dc5 498 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
<> 134:ad3be0349dc5 499 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
<> 134:ad3be0349dc5 500 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
<> 134:ad3be0349dc5 501 LL_DMA_CHANNEL_5)
<> 134:ad3be0349dc5 502 #endif /* DMA1_Channel6 && DMA1_Channel7 */
<> 134:ad3be0349dc5 503 #endif
<> 134:ad3be0349dc5 504
<> 134:ad3be0349dc5 505 /**
<> 134:ad3be0349dc5 506 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
<> 134:ad3be0349dc5 507 * @param __DMA_INSTANCE__ DMAx
<> 134:ad3be0349dc5 508 * @param __CHANNEL__ LL_DMA_CHANNEL_y
<> 134:ad3be0349dc5 509 * @retval DMAx_Channely
<> 134:ad3be0349dc5 510 */
<> 134:ad3be0349dc5 511 #if defined (DMA2)
<> 134:ad3be0349dc5 512 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<> 134:ad3be0349dc5 513 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 134:ad3be0349dc5 514 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 134:ad3be0349dc5 515 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<> 134:ad3be0349dc5 516 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 134:ad3be0349dc5 517 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<> 134:ad3be0349dc5 518 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 134:ad3be0349dc5 519 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<> 134:ad3be0349dc5 520 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 134:ad3be0349dc5 521 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<> 134:ad3be0349dc5 522 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<> 134:ad3be0349dc5 523 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<> 134:ad3be0349dc5 524 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<> 134:ad3be0349dc5 525 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
<> 134:ad3be0349dc5 526 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
<> 134:ad3be0349dc5 527 DMA2_Channel7)
<> 134:ad3be0349dc5 528 #else
<> 134:ad3be0349dc5 529 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 134:ad3be0349dc5 530 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 134:ad3be0349dc5 531 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
<> 134:ad3be0349dc5 532 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 134:ad3be0349dc5 533 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
<> 134:ad3be0349dc5 534 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 134:ad3be0349dc5 535 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
<> 134:ad3be0349dc5 536 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 134:ad3be0349dc5 537 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
<> 134:ad3be0349dc5 538 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<> 134:ad3be0349dc5 539 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
<> 134:ad3be0349dc5 540 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<> 134:ad3be0349dc5 541 DMA1_Channel7)
<> 134:ad3be0349dc5 542 #endif
<> 134:ad3be0349dc5 543 #else
<> 134:ad3be0349dc5 544 #if defined (DMA1_Channel6) && defined (DMA1_Channel7)
<> 134:ad3be0349dc5 545 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 134:ad3be0349dc5 546 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 134:ad3be0349dc5 547 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 134:ad3be0349dc5 548 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 134:ad3be0349dc5 549 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 134:ad3be0349dc5 550 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<> 134:ad3be0349dc5 551 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
<> 134:ad3be0349dc5 552 DMA1_Channel7)
<> 134:ad3be0349dc5 553 #elif defined (DMA1_Channel6)
<> 134:ad3be0349dc5 554 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 134:ad3be0349dc5 555 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 134:ad3be0349dc5 556 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 134:ad3be0349dc5 557 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 134:ad3be0349dc5 558 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 134:ad3be0349dc5 559 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
<> 134:ad3be0349dc5 560 DMA1_Channel6)
<> 134:ad3be0349dc5 561 #else
<> 134:ad3be0349dc5 562 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
<> 134:ad3be0349dc5 563 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
<> 134:ad3be0349dc5 564 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
<> 134:ad3be0349dc5 565 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
<> 134:ad3be0349dc5 566 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
<> 134:ad3be0349dc5 567 DMA1_Channel5)
<> 134:ad3be0349dc5 568 #endif /* DMA1_Channel6 && DMA1_Channel7 */
<> 134:ad3be0349dc5 569 #endif
<> 134:ad3be0349dc5 570
<> 134:ad3be0349dc5 571 /**
<> 134:ad3be0349dc5 572 * @}
<> 134:ad3be0349dc5 573 */
<> 134:ad3be0349dc5 574
<> 134:ad3be0349dc5 575 /**
<> 134:ad3be0349dc5 576 * @}
<> 134:ad3be0349dc5 577 */
<> 134:ad3be0349dc5 578
<> 134:ad3be0349dc5 579 /* Exported functions --------------------------------------------------------*/
<> 134:ad3be0349dc5 580 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
<> 134:ad3be0349dc5 581 * @{
<> 134:ad3be0349dc5 582 */
<> 134:ad3be0349dc5 583
<> 134:ad3be0349dc5 584 /** @defgroup DMA_LL_EF_Configuration Configuration
<> 134:ad3be0349dc5 585 * @{
<> 134:ad3be0349dc5 586 */
<> 134:ad3be0349dc5 587 /**
<> 134:ad3be0349dc5 588 * @brief Enable DMA channel.
<> 134:ad3be0349dc5 589 * @rmtoll CCR EN LL_DMA_EnableChannel
<> 134:ad3be0349dc5 590 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 591 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 592 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 593 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 594 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 595 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 596 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 597 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 598 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 599 * @retval None
<> 134:ad3be0349dc5 600 */
<> 134:ad3be0349dc5 601 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 602 {
<> 134:ad3be0349dc5 603 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<> 134:ad3be0349dc5 604 }
<> 134:ad3be0349dc5 605
<> 134:ad3be0349dc5 606 /**
<> 134:ad3be0349dc5 607 * @brief Disable DMA channel.
<> 134:ad3be0349dc5 608 * @rmtoll CCR EN LL_DMA_DisableChannel
<> 134:ad3be0349dc5 609 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 610 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 611 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 612 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 613 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 614 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 615 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 616 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 617 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 618 * @retval None
<> 134:ad3be0349dc5 619 */
<> 134:ad3be0349dc5 620 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 621 {
<> 134:ad3be0349dc5 622 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
<> 134:ad3be0349dc5 623 }
<> 134:ad3be0349dc5 624
<> 134:ad3be0349dc5 625 /**
<> 134:ad3be0349dc5 626 * @brief Check if DMA channel is enabled or disabled.
<> 134:ad3be0349dc5 627 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
<> 134:ad3be0349dc5 628 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 629 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 630 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 631 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 632 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 633 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 634 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 635 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 636 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 637 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 638 */
<> 134:ad3be0349dc5 639 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 640 {
<> 134:ad3be0349dc5 641 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 134:ad3be0349dc5 642 DMA_CCR_EN) == (DMA_CCR_EN));
<> 134:ad3be0349dc5 643 }
<> 134:ad3be0349dc5 644
<> 134:ad3be0349dc5 645 /**
<> 134:ad3be0349dc5 646 * @brief Configure all parameters link to DMA transfer.
<> 134:ad3be0349dc5 647 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
<> 134:ad3be0349dc5 648 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
<> 134:ad3be0349dc5 649 * CCR CIRC LL_DMA_ConfigTransfer\n
<> 134:ad3be0349dc5 650 * CCR PINC LL_DMA_ConfigTransfer\n
<> 134:ad3be0349dc5 651 * CCR MINC LL_DMA_ConfigTransfer\n
<> 134:ad3be0349dc5 652 * CCR PSIZE LL_DMA_ConfigTransfer\n
<> 134:ad3be0349dc5 653 * CCR MSIZE LL_DMA_ConfigTransfer\n
<> 134:ad3be0349dc5 654 * CCR PL LL_DMA_ConfigTransfer
<> 134:ad3be0349dc5 655 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 656 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 657 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 658 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 659 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 660 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 661 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 662 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 663 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 664 * @param Configuration This parameter must be a combination of all the following values:
<> 134:ad3be0349dc5 665 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<> 134:ad3be0349dc5 666 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
<> 134:ad3be0349dc5 667 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
<> 134:ad3be0349dc5 668 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
<> 134:ad3be0349dc5 669 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
<> 134:ad3be0349dc5 670 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
<> 134:ad3be0349dc5 671 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
<> 134:ad3be0349dc5 672 * @retval None
<> 134:ad3be0349dc5 673 */
<> 134:ad3be0349dc5 674 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
<> 134:ad3be0349dc5 675 {
<> 134:ad3be0349dc5 676 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 134:ad3be0349dc5 677 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
<> 134:ad3be0349dc5 678 Configuration);
<> 134:ad3be0349dc5 679 }
<> 134:ad3be0349dc5 680
<> 134:ad3be0349dc5 681 /**
<> 134:ad3be0349dc5 682 * @brief Set Data transfer direction (read from peripheral or from memory).
<> 134:ad3be0349dc5 683 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
<> 134:ad3be0349dc5 684 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
<> 134:ad3be0349dc5 685 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 686 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 687 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 688 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 689 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 690 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 691 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 692 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 693 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 694 * @param Direction This parameter can be one of the following values:
<> 134:ad3be0349dc5 695 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<> 134:ad3be0349dc5 696 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<> 134:ad3be0349dc5 697 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<> 134:ad3be0349dc5 698 * @retval None
<> 134:ad3be0349dc5 699 */
<> 134:ad3be0349dc5 700 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
<> 134:ad3be0349dc5 701 {
<> 134:ad3be0349dc5 702 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 134:ad3be0349dc5 703 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
<> 134:ad3be0349dc5 704 }
<> 134:ad3be0349dc5 705
<> 134:ad3be0349dc5 706 /**
<> 134:ad3be0349dc5 707 * @brief Get Data transfer direction (read from peripheral or from memory).
<> 134:ad3be0349dc5 708 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
<> 134:ad3be0349dc5 709 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
<> 134:ad3be0349dc5 710 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 711 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 712 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 713 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 714 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 715 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 716 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 717 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 718 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 719 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 720 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<> 134:ad3be0349dc5 721 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<> 134:ad3be0349dc5 722 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<> 134:ad3be0349dc5 723 */
<> 134:ad3be0349dc5 724 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 725 {
<> 134:ad3be0349dc5 726 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 134:ad3be0349dc5 727 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
<> 134:ad3be0349dc5 728 }
<> 134:ad3be0349dc5 729
<> 134:ad3be0349dc5 730 /**
<> 134:ad3be0349dc5 731 * @brief Set DMA mode circular or normal.
<> 134:ad3be0349dc5 732 * @note The circular buffer mode cannot be used if the memory-to-memory
<> 134:ad3be0349dc5 733 * data transfer is configured on the selected Channel.
<> 134:ad3be0349dc5 734 * @rmtoll CCR CIRC LL_DMA_SetMode
<> 134:ad3be0349dc5 735 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 736 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 737 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 738 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 739 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 740 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 741 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 742 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 743 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 744 * @param Mode This parameter can be one of the following values:
<> 134:ad3be0349dc5 745 * @arg @ref LL_DMA_MODE_NORMAL
<> 134:ad3be0349dc5 746 * @arg @ref LL_DMA_MODE_CIRCULAR
<> 134:ad3be0349dc5 747 * @retval None
<> 134:ad3be0349dc5 748 */
<> 134:ad3be0349dc5 749 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
<> 134:ad3be0349dc5 750 {
<> 134:ad3be0349dc5 751 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
<> 134:ad3be0349dc5 752 Mode);
<> 134:ad3be0349dc5 753 }
<> 134:ad3be0349dc5 754
<> 134:ad3be0349dc5 755 /**
<> 134:ad3be0349dc5 756 * @brief Get DMA mode circular or normal.
<> 134:ad3be0349dc5 757 * @rmtoll CCR CIRC LL_DMA_GetMode
<> 134:ad3be0349dc5 758 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 759 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 760 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 761 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 762 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 763 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 764 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 765 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 766 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 767 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 768 * @arg @ref LL_DMA_MODE_NORMAL
<> 134:ad3be0349dc5 769 * @arg @ref LL_DMA_MODE_CIRCULAR
<> 134:ad3be0349dc5 770 */
<> 134:ad3be0349dc5 771 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 772 {
<> 134:ad3be0349dc5 773 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 134:ad3be0349dc5 774 DMA_CCR_CIRC));
<> 134:ad3be0349dc5 775 }
<> 134:ad3be0349dc5 776
<> 134:ad3be0349dc5 777 /**
<> 134:ad3be0349dc5 778 * @brief Set Peripheral increment mode.
<> 134:ad3be0349dc5 779 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
<> 134:ad3be0349dc5 780 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 781 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 782 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 783 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 784 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 785 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 786 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 787 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 788 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 789 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
<> 134:ad3be0349dc5 790 * @arg @ref LL_DMA_PERIPH_INCREMENT
<> 134:ad3be0349dc5 791 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
<> 134:ad3be0349dc5 792 * @retval None
<> 134:ad3be0349dc5 793 */
<> 134:ad3be0349dc5 794 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
<> 134:ad3be0349dc5 795 {
<> 134:ad3be0349dc5 796 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
<> 134:ad3be0349dc5 797 PeriphOrM2MSrcIncMode);
<> 134:ad3be0349dc5 798 }
<> 134:ad3be0349dc5 799
<> 134:ad3be0349dc5 800 /**
<> 134:ad3be0349dc5 801 * @brief Get Peripheral increment mode.
<> 134:ad3be0349dc5 802 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
<> 134:ad3be0349dc5 803 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 804 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 805 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 806 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 807 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 808 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 809 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 810 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 811 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 812 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 813 * @arg @ref LL_DMA_PERIPH_INCREMENT
<> 134:ad3be0349dc5 814 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
<> 134:ad3be0349dc5 815 */
<> 134:ad3be0349dc5 816 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 817 {
<> 134:ad3be0349dc5 818 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 134:ad3be0349dc5 819 DMA_CCR_PINC));
<> 134:ad3be0349dc5 820 }
<> 134:ad3be0349dc5 821
<> 134:ad3be0349dc5 822 /**
<> 134:ad3be0349dc5 823 * @brief Set Memory increment mode.
<> 134:ad3be0349dc5 824 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
<> 134:ad3be0349dc5 825 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 826 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 827 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 828 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 829 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 830 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 831 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 832 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 833 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 834 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
<> 134:ad3be0349dc5 835 * @arg @ref LL_DMA_MEMORY_INCREMENT
<> 134:ad3be0349dc5 836 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
<> 134:ad3be0349dc5 837 * @retval None
<> 134:ad3be0349dc5 838 */
<> 134:ad3be0349dc5 839 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
<> 134:ad3be0349dc5 840 {
<> 134:ad3be0349dc5 841 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
<> 134:ad3be0349dc5 842 MemoryOrM2MDstIncMode);
<> 134:ad3be0349dc5 843 }
<> 134:ad3be0349dc5 844
<> 134:ad3be0349dc5 845 /**
<> 134:ad3be0349dc5 846 * @brief Get Memory increment mode.
<> 134:ad3be0349dc5 847 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
<> 134:ad3be0349dc5 848 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 849 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 850 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 851 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 852 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 853 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 854 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 855 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 856 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 857 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 858 * @arg @ref LL_DMA_MEMORY_INCREMENT
<> 134:ad3be0349dc5 859 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
<> 134:ad3be0349dc5 860 */
<> 134:ad3be0349dc5 861 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 862 {
<> 134:ad3be0349dc5 863 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 134:ad3be0349dc5 864 DMA_CCR_MINC));
<> 134:ad3be0349dc5 865 }
<> 134:ad3be0349dc5 866
<> 134:ad3be0349dc5 867 /**
<> 134:ad3be0349dc5 868 * @brief Set Peripheral size.
<> 134:ad3be0349dc5 869 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
<> 134:ad3be0349dc5 870 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 871 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 872 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 873 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 874 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 875 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 876 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 877 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 878 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 879 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
<> 134:ad3be0349dc5 880 * @arg @ref LL_DMA_PDATAALIGN_BYTE
<> 134:ad3be0349dc5 881 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<> 134:ad3be0349dc5 882 * @arg @ref LL_DMA_PDATAALIGN_WORD
<> 134:ad3be0349dc5 883 * @retval None
<> 134:ad3be0349dc5 884 */
<> 134:ad3be0349dc5 885 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
<> 134:ad3be0349dc5 886 {
<> 134:ad3be0349dc5 887 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
<> 134:ad3be0349dc5 888 PeriphOrM2MSrcDataSize);
<> 134:ad3be0349dc5 889 }
<> 134:ad3be0349dc5 890
<> 134:ad3be0349dc5 891 /**
<> 134:ad3be0349dc5 892 * @brief Get Peripheral size.
<> 134:ad3be0349dc5 893 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
<> 134:ad3be0349dc5 894 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 895 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 896 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 897 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 898 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 899 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 900 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 901 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 902 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 903 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 904 * @arg @ref LL_DMA_PDATAALIGN_BYTE
<> 134:ad3be0349dc5 905 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
<> 134:ad3be0349dc5 906 * @arg @ref LL_DMA_PDATAALIGN_WORD
<> 134:ad3be0349dc5 907 */
<> 134:ad3be0349dc5 908 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 909 {
<> 134:ad3be0349dc5 910 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 134:ad3be0349dc5 911 DMA_CCR_PSIZE));
<> 134:ad3be0349dc5 912 }
<> 134:ad3be0349dc5 913
<> 134:ad3be0349dc5 914 /**
<> 134:ad3be0349dc5 915 * @brief Set Memory size.
<> 134:ad3be0349dc5 916 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
<> 134:ad3be0349dc5 917 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 918 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 919 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 920 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 921 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 922 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 923 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 924 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 925 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 926 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
<> 134:ad3be0349dc5 927 * @arg @ref LL_DMA_MDATAALIGN_BYTE
<> 134:ad3be0349dc5 928 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<> 134:ad3be0349dc5 929 * @arg @ref LL_DMA_MDATAALIGN_WORD
<> 134:ad3be0349dc5 930 * @retval None
<> 134:ad3be0349dc5 931 */
<> 134:ad3be0349dc5 932 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
<> 134:ad3be0349dc5 933 {
<> 134:ad3be0349dc5 934 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
<> 134:ad3be0349dc5 935 MemoryOrM2MDstDataSize);
<> 134:ad3be0349dc5 936 }
<> 134:ad3be0349dc5 937
<> 134:ad3be0349dc5 938 /**
<> 134:ad3be0349dc5 939 * @brief Get Memory size.
<> 134:ad3be0349dc5 940 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
<> 134:ad3be0349dc5 941 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 942 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 943 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 944 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 945 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 946 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 947 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 948 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 949 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 950 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 951 * @arg @ref LL_DMA_MDATAALIGN_BYTE
<> 134:ad3be0349dc5 952 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
<> 134:ad3be0349dc5 953 * @arg @ref LL_DMA_MDATAALIGN_WORD
<> 134:ad3be0349dc5 954 */
<> 134:ad3be0349dc5 955 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 956 {
<> 134:ad3be0349dc5 957 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 134:ad3be0349dc5 958 DMA_CCR_MSIZE));
<> 134:ad3be0349dc5 959 }
<> 134:ad3be0349dc5 960
<> 134:ad3be0349dc5 961 /**
<> 134:ad3be0349dc5 962 * @brief Set Channel priority level.
<> 134:ad3be0349dc5 963 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
<> 134:ad3be0349dc5 964 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 965 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 966 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 967 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 968 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 969 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 970 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 971 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 972 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 973 * @param Priority This parameter can be one of the following values:
<> 134:ad3be0349dc5 974 * @arg @ref LL_DMA_PRIORITY_LOW
<> 134:ad3be0349dc5 975 * @arg @ref LL_DMA_PRIORITY_MEDIUM
<> 134:ad3be0349dc5 976 * @arg @ref LL_DMA_PRIORITY_HIGH
<> 134:ad3be0349dc5 977 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
<> 134:ad3be0349dc5 978 * @retval None
<> 134:ad3be0349dc5 979 */
<> 134:ad3be0349dc5 980 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
<> 134:ad3be0349dc5 981 {
<> 134:ad3be0349dc5 982 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
<> 134:ad3be0349dc5 983 Priority);
<> 134:ad3be0349dc5 984 }
<> 134:ad3be0349dc5 985
<> 134:ad3be0349dc5 986 /**
<> 134:ad3be0349dc5 987 * @brief Get Channel priority level.
<> 134:ad3be0349dc5 988 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
<> 134:ad3be0349dc5 989 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 990 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 991 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 992 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 993 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 994 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 995 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 996 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 997 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 998 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 999 * @arg @ref LL_DMA_PRIORITY_LOW
<> 134:ad3be0349dc5 1000 * @arg @ref LL_DMA_PRIORITY_MEDIUM
<> 134:ad3be0349dc5 1001 * @arg @ref LL_DMA_PRIORITY_HIGH
<> 134:ad3be0349dc5 1002 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
<> 134:ad3be0349dc5 1003 */
<> 134:ad3be0349dc5 1004 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 1005 {
<> 134:ad3be0349dc5 1006 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 134:ad3be0349dc5 1007 DMA_CCR_PL));
<> 134:ad3be0349dc5 1008 }
<> 134:ad3be0349dc5 1009
<> 134:ad3be0349dc5 1010 /**
<> 134:ad3be0349dc5 1011 * @brief Set Number of data to transfer.
<> 134:ad3be0349dc5 1012 * @note This action has no effect if
<> 134:ad3be0349dc5 1013 * channel is enabled.
<> 134:ad3be0349dc5 1014 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
<> 134:ad3be0349dc5 1015 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1016 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 1017 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 1018 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 1019 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 1020 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 1021 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 1022 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 1023 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 1024 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
<> 134:ad3be0349dc5 1025 * @retval None
<> 134:ad3be0349dc5 1026 */
<> 134:ad3be0349dc5 1027 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
<> 134:ad3be0349dc5 1028 {
<> 134:ad3be0349dc5 1029 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<> 134:ad3be0349dc5 1030 DMA_CNDTR_NDT, NbData);
<> 134:ad3be0349dc5 1031 }
<> 134:ad3be0349dc5 1032
<> 134:ad3be0349dc5 1033 /**
<> 134:ad3be0349dc5 1034 * @brief Get Number of data to transfer.
<> 134:ad3be0349dc5 1035 * @note Once the channel is enabled, the return value indicate the
<> 134:ad3be0349dc5 1036 * remaining bytes to be transmitted.
<> 134:ad3be0349dc5 1037 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
<> 134:ad3be0349dc5 1038 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1039 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 1040 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 1041 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 1042 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 1043 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 1044 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 1045 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 1046 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 1047 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 134:ad3be0349dc5 1048 */
<> 134:ad3be0349dc5 1049 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 1050 {
<> 134:ad3be0349dc5 1051 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
<> 134:ad3be0349dc5 1052 DMA_CNDTR_NDT));
<> 134:ad3be0349dc5 1053 }
<> 134:ad3be0349dc5 1054
<> 134:ad3be0349dc5 1055 /**
<> 134:ad3be0349dc5 1056 * @brief Configure the Source and Destination addresses.
<> 134:ad3be0349dc5 1057 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
<> 134:ad3be0349dc5 1058 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
<> 134:ad3be0349dc5 1059 * CMAR MA LL_DMA_ConfigAddresses
<> 134:ad3be0349dc5 1060 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1061 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 1062 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 1063 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 1064 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 1065 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 1066 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 1067 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 1068 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 1069 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 134:ad3be0349dc5 1070 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 134:ad3be0349dc5 1071 * @param Direction This parameter can be one of the following values:
<> 134:ad3be0349dc5 1072 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
<> 134:ad3be0349dc5 1073 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
<> 134:ad3be0349dc5 1074 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
<> 134:ad3be0349dc5 1075 * @retval None
<> 134:ad3be0349dc5 1076 */
<> 134:ad3be0349dc5 1077 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
<> 134:ad3be0349dc5 1078 uint32_t DstAddress, uint32_t Direction)
<> 134:ad3be0349dc5 1079 {
<> 134:ad3be0349dc5 1080 /* Direction Memory to Periph */
<> 134:ad3be0349dc5 1081 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
<> 134:ad3be0349dc5 1082 {
<> 134:ad3be0349dc5 1083 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<> 134:ad3be0349dc5 1084 SrcAddress);
<> 134:ad3be0349dc5 1085 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<> 134:ad3be0349dc5 1086 DstAddress);
<> 134:ad3be0349dc5 1087 }
<> 134:ad3be0349dc5 1088 /* Direction Periph to Memory and Memory to Memory */
<> 134:ad3be0349dc5 1089 else
<> 134:ad3be0349dc5 1090 {
<> 134:ad3be0349dc5 1091 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<> 134:ad3be0349dc5 1092 SrcAddress);
<> 134:ad3be0349dc5 1093 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<> 134:ad3be0349dc5 1094 DstAddress);
<> 134:ad3be0349dc5 1095 }
<> 134:ad3be0349dc5 1096 }
<> 134:ad3be0349dc5 1097
<> 134:ad3be0349dc5 1098 /**
<> 134:ad3be0349dc5 1099 * @brief Set the Memory address.
<> 134:ad3be0349dc5 1100 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<> 134:ad3be0349dc5 1101 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
<> 134:ad3be0349dc5 1102 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1103 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 1104 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 1105 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 1106 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 1107 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 1108 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 1109 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 1110 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 1111 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 134:ad3be0349dc5 1112 * @retval None
<> 134:ad3be0349dc5 1113 */
<> 134:ad3be0349dc5 1114 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<> 134:ad3be0349dc5 1115 {
<> 134:ad3be0349dc5 1116 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<> 134:ad3be0349dc5 1117 MemoryAddress);
<> 134:ad3be0349dc5 1118 }
<> 134:ad3be0349dc5 1119
<> 134:ad3be0349dc5 1120 /**
<> 134:ad3be0349dc5 1121 * @brief Set the Peripheral address.
<> 134:ad3be0349dc5 1122 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<> 134:ad3be0349dc5 1123 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
<> 134:ad3be0349dc5 1124 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1125 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 1126 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 1127 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 1128 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 1129 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 1130 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 1131 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 1132 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 1133 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 134:ad3be0349dc5 1134 * @retval None
<> 134:ad3be0349dc5 1135 */
<> 134:ad3be0349dc5 1136 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
<> 134:ad3be0349dc5 1137 {
<> 134:ad3be0349dc5 1138 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<> 134:ad3be0349dc5 1139 PeriphAddress);
<> 134:ad3be0349dc5 1140 }
<> 134:ad3be0349dc5 1141
<> 134:ad3be0349dc5 1142 /**
<> 134:ad3be0349dc5 1143 * @brief Get Memory address.
<> 134:ad3be0349dc5 1144 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<> 134:ad3be0349dc5 1145 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
<> 134:ad3be0349dc5 1146 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1147 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 1148 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 1149 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 1150 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 1151 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 1152 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 1153 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 1154 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 1155 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 134:ad3be0349dc5 1156 */
<> 134:ad3be0349dc5 1157 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 1158 {
<> 134:ad3be0349dc5 1159 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
<> 134:ad3be0349dc5 1160 DMA_CMAR_MA));
<> 134:ad3be0349dc5 1161 }
<> 134:ad3be0349dc5 1162
<> 134:ad3be0349dc5 1163 /**
<> 134:ad3be0349dc5 1164 * @brief Get Peripheral address.
<> 134:ad3be0349dc5 1165 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
<> 134:ad3be0349dc5 1166 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
<> 134:ad3be0349dc5 1167 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1168 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 1169 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 1170 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 1171 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 1172 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 1173 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 1174 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 1175 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 1176 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 134:ad3be0349dc5 1177 */
<> 134:ad3be0349dc5 1178 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 1179 {
<> 134:ad3be0349dc5 1180 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
<> 134:ad3be0349dc5 1181 DMA_CPAR_PA));
<> 134:ad3be0349dc5 1182 }
<> 134:ad3be0349dc5 1183
<> 134:ad3be0349dc5 1184 /**
<> 134:ad3be0349dc5 1185 * @brief Set the Memory to Memory Source address.
<> 134:ad3be0349dc5 1186 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<> 134:ad3be0349dc5 1187 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
<> 134:ad3be0349dc5 1188 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1189 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 1190 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 1191 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 1192 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 1193 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 1194 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 1195 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 1196 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 1197 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 134:ad3be0349dc5 1198 * @retval None
<> 134:ad3be0349dc5 1199 */
<> 134:ad3be0349dc5 1200 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<> 134:ad3be0349dc5 1201 {
<> 134:ad3be0349dc5 1202 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
<> 134:ad3be0349dc5 1203 MemoryAddress);
<> 134:ad3be0349dc5 1204 }
<> 134:ad3be0349dc5 1205
<> 134:ad3be0349dc5 1206 /**
<> 134:ad3be0349dc5 1207 * @brief Set the Memory to Memory Destination address.
<> 134:ad3be0349dc5 1208 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<> 134:ad3be0349dc5 1209 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
<> 134:ad3be0349dc5 1210 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1211 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 1212 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 1213 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 1214 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 1215 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 1216 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 1217 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 1218 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 1219 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 134:ad3be0349dc5 1220 * @retval None
<> 134:ad3be0349dc5 1221 */
<> 134:ad3be0349dc5 1222 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
<> 134:ad3be0349dc5 1223 {
<> 134:ad3be0349dc5 1224 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
<> 134:ad3be0349dc5 1225 MemoryAddress);
<> 134:ad3be0349dc5 1226 }
<> 134:ad3be0349dc5 1227
<> 134:ad3be0349dc5 1228 /**
<> 134:ad3be0349dc5 1229 * @brief Get the Memory to Memory Source address.
<> 134:ad3be0349dc5 1230 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<> 134:ad3be0349dc5 1231 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
<> 134:ad3be0349dc5 1232 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1233 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 1234 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 1235 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 1236 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 1237 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 1238 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 1239 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 1240 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 1241 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 134:ad3be0349dc5 1242 */
<> 134:ad3be0349dc5 1243 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 1244 {
<> 134:ad3be0349dc5 1245 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
<> 134:ad3be0349dc5 1246 DMA_CPAR_PA));
<> 134:ad3be0349dc5 1247 }
<> 134:ad3be0349dc5 1248
<> 134:ad3be0349dc5 1249 /**
<> 134:ad3be0349dc5 1250 * @brief Get the Memory to Memory Destination address.
<> 134:ad3be0349dc5 1251 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
<> 134:ad3be0349dc5 1252 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
<> 134:ad3be0349dc5 1253 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1254 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 1255 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 1256 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 1257 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 1258 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 1259 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 1260 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 1261 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 1262 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
<> 134:ad3be0349dc5 1263 */
<> 134:ad3be0349dc5 1264 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 1265 {
<> 134:ad3be0349dc5 1266 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
<> 134:ad3be0349dc5 1267 DMA_CMAR_MA));
<> 134:ad3be0349dc5 1268 }
<> 134:ad3be0349dc5 1269
<> 134:ad3be0349dc5 1270 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 134:ad3be0349dc5 1271 /**
<> 134:ad3be0349dc5 1272 * @brief Set DMA request for DMA instance on Channel x.
<> 134:ad3be0349dc5 1273 * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
<> 134:ad3be0349dc5 1274 * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
<> 134:ad3be0349dc5 1275 * CSELR C2S LL_DMA_SetPeriphRequest\n
<> 134:ad3be0349dc5 1276 * CSELR C3S LL_DMA_SetPeriphRequest\n
<> 134:ad3be0349dc5 1277 * CSELR C4S LL_DMA_SetPeriphRequest\n
<> 134:ad3be0349dc5 1278 * CSELR C5S LL_DMA_SetPeriphRequest\n
<> 134:ad3be0349dc5 1279 * CSELR C6S LL_DMA_SetPeriphRequest\n
<> 134:ad3be0349dc5 1280 * CSELR C7S LL_DMA_SetPeriphRequest
<> 134:ad3be0349dc5 1281 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1282 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 1283 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 1284 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 1285 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 1286 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 1287 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 1288 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 1289 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 1290 * @param PeriphRequest This parameter can be one of the following values:
<> 134:ad3be0349dc5 1291 * @arg @ref LL_DMA_REQUEST_0
<> 134:ad3be0349dc5 1292 * @arg @ref LL_DMA_REQUEST_1
<> 134:ad3be0349dc5 1293 * @arg @ref LL_DMA_REQUEST_2
<> 134:ad3be0349dc5 1294 * @arg @ref LL_DMA_REQUEST_3
<> 134:ad3be0349dc5 1295 * @arg @ref LL_DMA_REQUEST_4
<> 134:ad3be0349dc5 1296 * @arg @ref LL_DMA_REQUEST_5
<> 134:ad3be0349dc5 1297 * @arg @ref LL_DMA_REQUEST_6
<> 134:ad3be0349dc5 1298 * @arg @ref LL_DMA_REQUEST_7
<> 134:ad3be0349dc5 1299 * @arg @ref LL_DMA_REQUEST_8
<> 134:ad3be0349dc5 1300 * @arg @ref LL_DMA_REQUEST_9
<> 134:ad3be0349dc5 1301 * @arg @ref LL_DMA_REQUEST_10
<> 134:ad3be0349dc5 1302 * @arg @ref LL_DMA_REQUEST_11
<> 134:ad3be0349dc5 1303 * @arg @ref LL_DMA_REQUEST_12
<> 134:ad3be0349dc5 1304 * @arg @ref LL_DMA_REQUEST_13
<> 134:ad3be0349dc5 1305 * @arg @ref LL_DMA_REQUEST_14
<> 134:ad3be0349dc5 1306 * @arg @ref LL_DMA_REQUEST_15
<> 134:ad3be0349dc5 1307 * @retval None
<> 134:ad3be0349dc5 1308 */
<> 134:ad3be0349dc5 1309 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
<> 134:ad3be0349dc5 1310 {
<> 134:ad3be0349dc5 1311 MODIFY_REG(DMAx->CSELR,
<> 134:ad3be0349dc5 1312 DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
<> 134:ad3be0349dc5 1313 }
<> 134:ad3be0349dc5 1314
<> 134:ad3be0349dc5 1315 /**
<> 134:ad3be0349dc5 1316 * @brief Get DMA request for DMA instance on Channel x.
<> 134:ad3be0349dc5 1317 * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
<> 134:ad3be0349dc5 1318 * CSELR C2S LL_DMA_GetPeriphRequest\n
<> 134:ad3be0349dc5 1319 * CSELR C3S LL_DMA_GetPeriphRequest\n
<> 134:ad3be0349dc5 1320 * CSELR C4S LL_DMA_GetPeriphRequest\n
<> 134:ad3be0349dc5 1321 * CSELR C5S LL_DMA_GetPeriphRequest\n
<> 134:ad3be0349dc5 1322 * CSELR C6S LL_DMA_GetPeriphRequest\n
<> 134:ad3be0349dc5 1323 * CSELR C7S LL_DMA_GetPeriphRequest
<> 134:ad3be0349dc5 1324 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1325 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 1326 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 1327 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 1328 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 1329 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 1330 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 1331 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 1332 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 1333 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1334 * @arg @ref LL_DMA_REQUEST_0
<> 134:ad3be0349dc5 1335 * @arg @ref LL_DMA_REQUEST_1
<> 134:ad3be0349dc5 1336 * @arg @ref LL_DMA_REQUEST_2
<> 134:ad3be0349dc5 1337 * @arg @ref LL_DMA_REQUEST_3
<> 134:ad3be0349dc5 1338 * @arg @ref LL_DMA_REQUEST_4
<> 134:ad3be0349dc5 1339 * @arg @ref LL_DMA_REQUEST_5
<> 134:ad3be0349dc5 1340 * @arg @ref LL_DMA_REQUEST_6
<> 134:ad3be0349dc5 1341 * @arg @ref LL_DMA_REQUEST_7
<> 134:ad3be0349dc5 1342 * @arg @ref LL_DMA_REQUEST_8
<> 134:ad3be0349dc5 1343 * @arg @ref LL_DMA_REQUEST_9
<> 134:ad3be0349dc5 1344 * @arg @ref LL_DMA_REQUEST_10
<> 134:ad3be0349dc5 1345 * @arg @ref LL_DMA_REQUEST_11
<> 134:ad3be0349dc5 1346 * @arg @ref LL_DMA_REQUEST_12
<> 134:ad3be0349dc5 1347 * @arg @ref LL_DMA_REQUEST_13
<> 134:ad3be0349dc5 1348 * @arg @ref LL_DMA_REQUEST_14
<> 134:ad3be0349dc5 1349 * @arg @ref LL_DMA_REQUEST_15
<> 134:ad3be0349dc5 1350 */
<> 134:ad3be0349dc5 1351 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 1352 {
<> 134:ad3be0349dc5 1353 return (READ_BIT(DMAx->CSELR,
<> 134:ad3be0349dc5 1354 DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
<> 134:ad3be0349dc5 1355 }
<> 134:ad3be0349dc5 1356 #endif
<> 134:ad3be0349dc5 1357
<> 134:ad3be0349dc5 1358 /**
<> 134:ad3be0349dc5 1359 * @}
<> 134:ad3be0349dc5 1360 */
<> 134:ad3be0349dc5 1361
<> 134:ad3be0349dc5 1362 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
<> 134:ad3be0349dc5 1363 * @{
<> 134:ad3be0349dc5 1364 */
<> 134:ad3be0349dc5 1365
<> 134:ad3be0349dc5 1366 /**
<> 134:ad3be0349dc5 1367 * @brief Get Channel 1 global interrupt flag.
<> 134:ad3be0349dc5 1368 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
<> 134:ad3be0349dc5 1369 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1370 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1371 */
<> 134:ad3be0349dc5 1372 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1373 {
<> 134:ad3be0349dc5 1374 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
<> 134:ad3be0349dc5 1375 }
<> 134:ad3be0349dc5 1376
<> 134:ad3be0349dc5 1377 /**
<> 134:ad3be0349dc5 1378 * @brief Get Channel 2 global interrupt flag.
<> 134:ad3be0349dc5 1379 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
<> 134:ad3be0349dc5 1380 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1381 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1382 */
<> 134:ad3be0349dc5 1383 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1384 {
<> 134:ad3be0349dc5 1385 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
<> 134:ad3be0349dc5 1386 }
<> 134:ad3be0349dc5 1387
<> 134:ad3be0349dc5 1388 /**
<> 134:ad3be0349dc5 1389 * @brief Get Channel 3 global interrupt flag.
<> 134:ad3be0349dc5 1390 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
<> 134:ad3be0349dc5 1391 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1392 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1393 */
<> 134:ad3be0349dc5 1394 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1395 {
<> 134:ad3be0349dc5 1396 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
<> 134:ad3be0349dc5 1397 }
<> 134:ad3be0349dc5 1398
<> 134:ad3be0349dc5 1399 /**
<> 134:ad3be0349dc5 1400 * @brief Get Channel 4 global interrupt flag.
<> 134:ad3be0349dc5 1401 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
<> 134:ad3be0349dc5 1402 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1403 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1404 */
<> 134:ad3be0349dc5 1405 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1406 {
<> 134:ad3be0349dc5 1407 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
<> 134:ad3be0349dc5 1408 }
<> 134:ad3be0349dc5 1409
<> 134:ad3be0349dc5 1410 /**
<> 134:ad3be0349dc5 1411 * @brief Get Channel 5 global interrupt flag.
<> 134:ad3be0349dc5 1412 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
<> 134:ad3be0349dc5 1413 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1414 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1415 */
<> 134:ad3be0349dc5 1416 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1417 {
<> 134:ad3be0349dc5 1418 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
<> 134:ad3be0349dc5 1419 }
<> 134:ad3be0349dc5 1420
<> 134:ad3be0349dc5 1421 #if defined(DMA1_Channel6)
<> 134:ad3be0349dc5 1422 /**
<> 134:ad3be0349dc5 1423 * @brief Get Channel 6 global interrupt flag.
<> 134:ad3be0349dc5 1424 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
<> 134:ad3be0349dc5 1425 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1426 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1427 */
<> 134:ad3be0349dc5 1428 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1429 {
<> 134:ad3be0349dc5 1430 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
<> 134:ad3be0349dc5 1431 }
<> 134:ad3be0349dc5 1432 #endif
<> 134:ad3be0349dc5 1433
<> 134:ad3be0349dc5 1434 #if defined(DMA1_Channel7)
<> 134:ad3be0349dc5 1435 /**
<> 134:ad3be0349dc5 1436 * @brief Get Channel 7 global interrupt flag.
<> 134:ad3be0349dc5 1437 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
<> 134:ad3be0349dc5 1438 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1439 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1440 */
<> 134:ad3be0349dc5 1441 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1442 {
<> 134:ad3be0349dc5 1443 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
<> 134:ad3be0349dc5 1444 }
<> 134:ad3be0349dc5 1445 #endif
<> 134:ad3be0349dc5 1446
<> 134:ad3be0349dc5 1447 /**
<> 134:ad3be0349dc5 1448 * @brief Get Channel 1 transfer complete flag.
<> 134:ad3be0349dc5 1449 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
<> 134:ad3be0349dc5 1450 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1451 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1452 */
<> 134:ad3be0349dc5 1453 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1454 {
<> 134:ad3be0349dc5 1455 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
<> 134:ad3be0349dc5 1456 }
<> 134:ad3be0349dc5 1457
<> 134:ad3be0349dc5 1458 /**
<> 134:ad3be0349dc5 1459 * @brief Get Channel 2 transfer complete flag.
<> 134:ad3be0349dc5 1460 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
<> 134:ad3be0349dc5 1461 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1462 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1463 */
<> 134:ad3be0349dc5 1464 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1465 {
<> 134:ad3be0349dc5 1466 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
<> 134:ad3be0349dc5 1467 }
<> 134:ad3be0349dc5 1468
<> 134:ad3be0349dc5 1469 /**
<> 134:ad3be0349dc5 1470 * @brief Get Channel 3 transfer complete flag.
<> 134:ad3be0349dc5 1471 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
<> 134:ad3be0349dc5 1472 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1473 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1474 */
<> 134:ad3be0349dc5 1475 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1476 {
<> 134:ad3be0349dc5 1477 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
<> 134:ad3be0349dc5 1478 }
<> 134:ad3be0349dc5 1479
<> 134:ad3be0349dc5 1480 /**
<> 134:ad3be0349dc5 1481 * @brief Get Channel 4 transfer complete flag.
<> 134:ad3be0349dc5 1482 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
<> 134:ad3be0349dc5 1483 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1484 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1485 */
<> 134:ad3be0349dc5 1486 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1487 {
<> 134:ad3be0349dc5 1488 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
<> 134:ad3be0349dc5 1489 }
<> 134:ad3be0349dc5 1490
<> 134:ad3be0349dc5 1491 /**
<> 134:ad3be0349dc5 1492 * @brief Get Channel 5 transfer complete flag.
<> 134:ad3be0349dc5 1493 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
<> 134:ad3be0349dc5 1494 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1495 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1496 */
<> 134:ad3be0349dc5 1497 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1498 {
<> 134:ad3be0349dc5 1499 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
<> 134:ad3be0349dc5 1500 }
<> 134:ad3be0349dc5 1501
<> 134:ad3be0349dc5 1502 #if defined(DMA1_Channel6)
<> 134:ad3be0349dc5 1503 /**
<> 134:ad3be0349dc5 1504 * @brief Get Channel 6 transfer complete flag.
<> 134:ad3be0349dc5 1505 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
<> 134:ad3be0349dc5 1506 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1507 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1508 */
<> 134:ad3be0349dc5 1509 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1510 {
<> 134:ad3be0349dc5 1511 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
<> 134:ad3be0349dc5 1512 }
<> 134:ad3be0349dc5 1513 #endif
<> 134:ad3be0349dc5 1514
<> 134:ad3be0349dc5 1515 #if defined(DMA1_Channel7)
<> 134:ad3be0349dc5 1516 /**
<> 134:ad3be0349dc5 1517 * @brief Get Channel 7 transfer complete flag.
<> 134:ad3be0349dc5 1518 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
<> 134:ad3be0349dc5 1519 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1520 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1521 */
<> 134:ad3be0349dc5 1522 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1523 {
<> 134:ad3be0349dc5 1524 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
<> 134:ad3be0349dc5 1525 }
<> 134:ad3be0349dc5 1526 #endif
<> 134:ad3be0349dc5 1527
<> 134:ad3be0349dc5 1528 /**
<> 134:ad3be0349dc5 1529 * @brief Get Channel 1 half transfer flag.
<> 134:ad3be0349dc5 1530 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
<> 134:ad3be0349dc5 1531 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1532 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1533 */
<> 134:ad3be0349dc5 1534 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1535 {
<> 134:ad3be0349dc5 1536 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
<> 134:ad3be0349dc5 1537 }
<> 134:ad3be0349dc5 1538
<> 134:ad3be0349dc5 1539 /**
<> 134:ad3be0349dc5 1540 * @brief Get Channel 2 half transfer flag.
<> 134:ad3be0349dc5 1541 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
<> 134:ad3be0349dc5 1542 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1543 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1544 */
<> 134:ad3be0349dc5 1545 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1546 {
<> 134:ad3be0349dc5 1547 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
<> 134:ad3be0349dc5 1548 }
<> 134:ad3be0349dc5 1549
<> 134:ad3be0349dc5 1550 /**
<> 134:ad3be0349dc5 1551 * @brief Get Channel 3 half transfer flag.
<> 134:ad3be0349dc5 1552 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
<> 134:ad3be0349dc5 1553 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1554 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1555 */
<> 134:ad3be0349dc5 1556 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1557 {
<> 134:ad3be0349dc5 1558 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
<> 134:ad3be0349dc5 1559 }
<> 134:ad3be0349dc5 1560
<> 134:ad3be0349dc5 1561 /**
<> 134:ad3be0349dc5 1562 * @brief Get Channel 4 half transfer flag.
<> 134:ad3be0349dc5 1563 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
<> 134:ad3be0349dc5 1564 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1565 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1566 */
<> 134:ad3be0349dc5 1567 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1568 {
<> 134:ad3be0349dc5 1569 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
<> 134:ad3be0349dc5 1570 }
<> 134:ad3be0349dc5 1571
<> 134:ad3be0349dc5 1572 /**
<> 134:ad3be0349dc5 1573 * @brief Get Channel 5 half transfer flag.
<> 134:ad3be0349dc5 1574 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
<> 134:ad3be0349dc5 1575 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1576 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1577 */
<> 134:ad3be0349dc5 1578 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1579 {
<> 134:ad3be0349dc5 1580 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
<> 134:ad3be0349dc5 1581 }
<> 134:ad3be0349dc5 1582
<> 134:ad3be0349dc5 1583 #if defined(DMA1_Channel6)
<> 134:ad3be0349dc5 1584 /**
<> 134:ad3be0349dc5 1585 * @brief Get Channel 6 half transfer flag.
<> 134:ad3be0349dc5 1586 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
<> 134:ad3be0349dc5 1587 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1588 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1589 */
<> 134:ad3be0349dc5 1590 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1591 {
<> 134:ad3be0349dc5 1592 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
<> 134:ad3be0349dc5 1593 }
<> 134:ad3be0349dc5 1594 #endif
<> 134:ad3be0349dc5 1595
<> 134:ad3be0349dc5 1596 #if defined(DMA1_Channel7)
<> 134:ad3be0349dc5 1597 /**
<> 134:ad3be0349dc5 1598 * @brief Get Channel 7 half transfer flag.
<> 134:ad3be0349dc5 1599 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
<> 134:ad3be0349dc5 1600 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1601 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1602 */
<> 134:ad3be0349dc5 1603 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1604 {
<> 134:ad3be0349dc5 1605 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
<> 134:ad3be0349dc5 1606 }
<> 134:ad3be0349dc5 1607 #endif
<> 134:ad3be0349dc5 1608
<> 134:ad3be0349dc5 1609 /**
<> 134:ad3be0349dc5 1610 * @brief Get Channel 1 transfer error flag.
<> 134:ad3be0349dc5 1611 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
<> 134:ad3be0349dc5 1612 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1613 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1614 */
<> 134:ad3be0349dc5 1615 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1616 {
<> 134:ad3be0349dc5 1617 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
<> 134:ad3be0349dc5 1618 }
<> 134:ad3be0349dc5 1619
<> 134:ad3be0349dc5 1620 /**
<> 134:ad3be0349dc5 1621 * @brief Get Channel 2 transfer error flag.
<> 134:ad3be0349dc5 1622 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
<> 134:ad3be0349dc5 1623 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1624 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1625 */
<> 134:ad3be0349dc5 1626 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1627 {
<> 134:ad3be0349dc5 1628 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
<> 134:ad3be0349dc5 1629 }
<> 134:ad3be0349dc5 1630
<> 134:ad3be0349dc5 1631 /**
<> 134:ad3be0349dc5 1632 * @brief Get Channel 3 transfer error flag.
<> 134:ad3be0349dc5 1633 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
<> 134:ad3be0349dc5 1634 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1635 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1636 */
<> 134:ad3be0349dc5 1637 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1638 {
<> 134:ad3be0349dc5 1639 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
<> 134:ad3be0349dc5 1640 }
<> 134:ad3be0349dc5 1641
<> 134:ad3be0349dc5 1642 /**
<> 134:ad3be0349dc5 1643 * @brief Get Channel 4 transfer error flag.
<> 134:ad3be0349dc5 1644 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
<> 134:ad3be0349dc5 1645 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1646 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1647 */
<> 134:ad3be0349dc5 1648 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1649 {
<> 134:ad3be0349dc5 1650 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
<> 134:ad3be0349dc5 1651 }
<> 134:ad3be0349dc5 1652
<> 134:ad3be0349dc5 1653 /**
<> 134:ad3be0349dc5 1654 * @brief Get Channel 5 transfer error flag.
<> 134:ad3be0349dc5 1655 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
<> 134:ad3be0349dc5 1656 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1657 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1658 */
<> 134:ad3be0349dc5 1659 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1660 {
<> 134:ad3be0349dc5 1661 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
<> 134:ad3be0349dc5 1662 }
<> 134:ad3be0349dc5 1663
<> 134:ad3be0349dc5 1664 #if defined(DMA1_Channel6)
<> 134:ad3be0349dc5 1665 /**
<> 134:ad3be0349dc5 1666 * @brief Get Channel 6 transfer error flag.
<> 134:ad3be0349dc5 1667 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
<> 134:ad3be0349dc5 1668 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1669 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1670 */
<> 134:ad3be0349dc5 1671 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1672 {
<> 134:ad3be0349dc5 1673 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
<> 134:ad3be0349dc5 1674 }
<> 134:ad3be0349dc5 1675 #endif
<> 134:ad3be0349dc5 1676
<> 134:ad3be0349dc5 1677 #if defined(DMA1_Channel7)
<> 134:ad3be0349dc5 1678 /**
<> 134:ad3be0349dc5 1679 * @brief Get Channel 7 transfer error flag.
<> 134:ad3be0349dc5 1680 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
<> 134:ad3be0349dc5 1681 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1682 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 1683 */
<> 134:ad3be0349dc5 1684 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1685 {
<> 134:ad3be0349dc5 1686 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
<> 134:ad3be0349dc5 1687 }
<> 134:ad3be0349dc5 1688 #endif
<> 134:ad3be0349dc5 1689
<> 134:ad3be0349dc5 1690 /**
<> 134:ad3be0349dc5 1691 * @brief Clear Channel 1 global interrupt flag.
<> 134:ad3be0349dc5 1692 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
<> 134:ad3be0349dc5 1693 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1694 * @retval None
<> 134:ad3be0349dc5 1695 */
<> 134:ad3be0349dc5 1696 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1697 {
<> 134:ad3be0349dc5 1698 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
<> 134:ad3be0349dc5 1699 }
<> 134:ad3be0349dc5 1700
<> 134:ad3be0349dc5 1701 /**
<> 134:ad3be0349dc5 1702 * @brief Clear Channel 2 global interrupt flag.
<> 134:ad3be0349dc5 1703 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
<> 134:ad3be0349dc5 1704 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1705 * @retval None
<> 134:ad3be0349dc5 1706 */
<> 134:ad3be0349dc5 1707 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1708 {
<> 134:ad3be0349dc5 1709 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
<> 134:ad3be0349dc5 1710 }
<> 134:ad3be0349dc5 1711
<> 134:ad3be0349dc5 1712 /**
<> 134:ad3be0349dc5 1713 * @brief Clear Channel 3 global interrupt flag.
<> 134:ad3be0349dc5 1714 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
<> 134:ad3be0349dc5 1715 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1716 * @retval None
<> 134:ad3be0349dc5 1717 */
<> 134:ad3be0349dc5 1718 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1719 {
<> 134:ad3be0349dc5 1720 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
<> 134:ad3be0349dc5 1721 }
<> 134:ad3be0349dc5 1722
<> 134:ad3be0349dc5 1723 /**
<> 134:ad3be0349dc5 1724 * @brief Clear Channel 4 global interrupt flag.
<> 134:ad3be0349dc5 1725 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
<> 134:ad3be0349dc5 1726 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1727 * @retval None
<> 134:ad3be0349dc5 1728 */
<> 134:ad3be0349dc5 1729 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1730 {
<> 134:ad3be0349dc5 1731 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
<> 134:ad3be0349dc5 1732 }
<> 134:ad3be0349dc5 1733
<> 134:ad3be0349dc5 1734 /**
<> 134:ad3be0349dc5 1735 * @brief Clear Channel 5 global interrupt flag.
<> 134:ad3be0349dc5 1736 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
<> 134:ad3be0349dc5 1737 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1738 * @retval None
<> 134:ad3be0349dc5 1739 */
<> 134:ad3be0349dc5 1740 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1741 {
<> 134:ad3be0349dc5 1742 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
<> 134:ad3be0349dc5 1743 }
<> 134:ad3be0349dc5 1744
<> 134:ad3be0349dc5 1745 #if defined(DMA1_Channel6)
<> 134:ad3be0349dc5 1746 /**
<> 134:ad3be0349dc5 1747 * @brief Clear Channel 6 global interrupt flag.
<> 134:ad3be0349dc5 1748 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
<> 134:ad3be0349dc5 1749 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1750 * @retval None
<> 134:ad3be0349dc5 1751 */
<> 134:ad3be0349dc5 1752 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1753 {
<> 134:ad3be0349dc5 1754 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
<> 134:ad3be0349dc5 1755 }
<> 134:ad3be0349dc5 1756 #endif
<> 134:ad3be0349dc5 1757
<> 134:ad3be0349dc5 1758 #if defined(DMA1_Channel7)
<> 134:ad3be0349dc5 1759 /**
<> 134:ad3be0349dc5 1760 * @brief Clear Channel 7 global interrupt flag.
<> 134:ad3be0349dc5 1761 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
<> 134:ad3be0349dc5 1762 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1763 * @retval None
<> 134:ad3be0349dc5 1764 */
<> 134:ad3be0349dc5 1765 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1766 {
<> 134:ad3be0349dc5 1767 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
<> 134:ad3be0349dc5 1768 }
<> 134:ad3be0349dc5 1769 #endif
<> 134:ad3be0349dc5 1770
<> 134:ad3be0349dc5 1771 /**
<> 134:ad3be0349dc5 1772 * @brief Clear Channel 1 transfer complete flag.
<> 134:ad3be0349dc5 1773 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
<> 134:ad3be0349dc5 1774 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1775 * @retval None
<> 134:ad3be0349dc5 1776 */
<> 134:ad3be0349dc5 1777 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1778 {
<> 134:ad3be0349dc5 1779 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
<> 134:ad3be0349dc5 1780 }
<> 134:ad3be0349dc5 1781
<> 134:ad3be0349dc5 1782 /**
<> 134:ad3be0349dc5 1783 * @brief Clear Channel 2 transfer complete flag.
<> 134:ad3be0349dc5 1784 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
<> 134:ad3be0349dc5 1785 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1786 * @retval None
<> 134:ad3be0349dc5 1787 */
<> 134:ad3be0349dc5 1788 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1789 {
<> 134:ad3be0349dc5 1790 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
<> 134:ad3be0349dc5 1791 }
<> 134:ad3be0349dc5 1792
<> 134:ad3be0349dc5 1793 /**
<> 134:ad3be0349dc5 1794 * @brief Clear Channel 3 transfer complete flag.
<> 134:ad3be0349dc5 1795 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
<> 134:ad3be0349dc5 1796 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1797 * @retval None
<> 134:ad3be0349dc5 1798 */
<> 134:ad3be0349dc5 1799 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1800 {
<> 134:ad3be0349dc5 1801 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
<> 134:ad3be0349dc5 1802 }
<> 134:ad3be0349dc5 1803
<> 134:ad3be0349dc5 1804 /**
<> 134:ad3be0349dc5 1805 * @brief Clear Channel 4 transfer complete flag.
<> 134:ad3be0349dc5 1806 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
<> 134:ad3be0349dc5 1807 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1808 * @retval None
<> 134:ad3be0349dc5 1809 */
<> 134:ad3be0349dc5 1810 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1811 {
<> 134:ad3be0349dc5 1812 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
<> 134:ad3be0349dc5 1813 }
<> 134:ad3be0349dc5 1814
<> 134:ad3be0349dc5 1815 /**
<> 134:ad3be0349dc5 1816 * @brief Clear Channel 5 transfer complete flag.
<> 134:ad3be0349dc5 1817 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
<> 134:ad3be0349dc5 1818 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1819 * @retval None
<> 134:ad3be0349dc5 1820 */
<> 134:ad3be0349dc5 1821 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1822 {
<> 134:ad3be0349dc5 1823 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
<> 134:ad3be0349dc5 1824 }
<> 134:ad3be0349dc5 1825
<> 134:ad3be0349dc5 1826 #if defined(DMA1_Channel6)
<> 134:ad3be0349dc5 1827 /**
<> 134:ad3be0349dc5 1828 * @brief Clear Channel 6 transfer complete flag.
<> 134:ad3be0349dc5 1829 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
<> 134:ad3be0349dc5 1830 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1831 * @retval None
<> 134:ad3be0349dc5 1832 */
<> 134:ad3be0349dc5 1833 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1834 {
<> 134:ad3be0349dc5 1835 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
<> 134:ad3be0349dc5 1836 }
<> 134:ad3be0349dc5 1837 #endif
<> 134:ad3be0349dc5 1838
<> 134:ad3be0349dc5 1839 #if defined(DMA1_Channel7)
<> 134:ad3be0349dc5 1840 /**
<> 134:ad3be0349dc5 1841 * @brief Clear Channel 7 transfer complete flag.
<> 134:ad3be0349dc5 1842 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
<> 134:ad3be0349dc5 1843 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1844 * @retval None
<> 134:ad3be0349dc5 1845 */
<> 134:ad3be0349dc5 1846 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1847 {
<> 134:ad3be0349dc5 1848 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
<> 134:ad3be0349dc5 1849 }
<> 134:ad3be0349dc5 1850 #endif
<> 134:ad3be0349dc5 1851
<> 134:ad3be0349dc5 1852 /**
<> 134:ad3be0349dc5 1853 * @brief Clear Channel 1 half transfer flag.
<> 134:ad3be0349dc5 1854 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
<> 134:ad3be0349dc5 1855 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1856 * @retval None
<> 134:ad3be0349dc5 1857 */
<> 134:ad3be0349dc5 1858 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1859 {
<> 134:ad3be0349dc5 1860 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
<> 134:ad3be0349dc5 1861 }
<> 134:ad3be0349dc5 1862
<> 134:ad3be0349dc5 1863 /**
<> 134:ad3be0349dc5 1864 * @brief Clear Channel 2 half transfer flag.
<> 134:ad3be0349dc5 1865 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
<> 134:ad3be0349dc5 1866 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1867 * @retval None
<> 134:ad3be0349dc5 1868 */
<> 134:ad3be0349dc5 1869 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1870 {
<> 134:ad3be0349dc5 1871 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
<> 134:ad3be0349dc5 1872 }
<> 134:ad3be0349dc5 1873
<> 134:ad3be0349dc5 1874 /**
<> 134:ad3be0349dc5 1875 * @brief Clear Channel 3 half transfer flag.
<> 134:ad3be0349dc5 1876 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
<> 134:ad3be0349dc5 1877 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1878 * @retval None
<> 134:ad3be0349dc5 1879 */
<> 134:ad3be0349dc5 1880 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1881 {
<> 134:ad3be0349dc5 1882 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
<> 134:ad3be0349dc5 1883 }
<> 134:ad3be0349dc5 1884
<> 134:ad3be0349dc5 1885 /**
<> 134:ad3be0349dc5 1886 * @brief Clear Channel 4 half transfer flag.
<> 134:ad3be0349dc5 1887 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
<> 134:ad3be0349dc5 1888 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1889 * @retval None
<> 134:ad3be0349dc5 1890 */
<> 134:ad3be0349dc5 1891 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1892 {
<> 134:ad3be0349dc5 1893 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
<> 134:ad3be0349dc5 1894 }
<> 134:ad3be0349dc5 1895
<> 134:ad3be0349dc5 1896 /**
<> 134:ad3be0349dc5 1897 * @brief Clear Channel 5 half transfer flag.
<> 134:ad3be0349dc5 1898 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
<> 134:ad3be0349dc5 1899 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1900 * @retval None
<> 134:ad3be0349dc5 1901 */
<> 134:ad3be0349dc5 1902 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1903 {
<> 134:ad3be0349dc5 1904 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
<> 134:ad3be0349dc5 1905 }
<> 134:ad3be0349dc5 1906
<> 134:ad3be0349dc5 1907 #if defined(DMA1_Channel6)
<> 134:ad3be0349dc5 1908 /**
<> 134:ad3be0349dc5 1909 * @brief Clear Channel 6 half transfer flag.
<> 134:ad3be0349dc5 1910 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
<> 134:ad3be0349dc5 1911 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1912 * @retval None
<> 134:ad3be0349dc5 1913 */
<> 134:ad3be0349dc5 1914 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1915 {
<> 134:ad3be0349dc5 1916 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
<> 134:ad3be0349dc5 1917 }
<> 134:ad3be0349dc5 1918 #endif
<> 134:ad3be0349dc5 1919
<> 134:ad3be0349dc5 1920 #if defined(DMA1_Channel7)
<> 134:ad3be0349dc5 1921 /**
<> 134:ad3be0349dc5 1922 * @brief Clear Channel 7 half transfer flag.
<> 134:ad3be0349dc5 1923 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
<> 134:ad3be0349dc5 1924 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1925 * @retval None
<> 134:ad3be0349dc5 1926 */
<> 134:ad3be0349dc5 1927 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1928 {
<> 134:ad3be0349dc5 1929 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
<> 134:ad3be0349dc5 1930 }
<> 134:ad3be0349dc5 1931 #endif
<> 134:ad3be0349dc5 1932
<> 134:ad3be0349dc5 1933 /**
<> 134:ad3be0349dc5 1934 * @brief Clear Channel 1 transfer error flag.
<> 134:ad3be0349dc5 1935 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
<> 134:ad3be0349dc5 1936 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1937 * @retval None
<> 134:ad3be0349dc5 1938 */
<> 134:ad3be0349dc5 1939 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1940 {
<> 134:ad3be0349dc5 1941 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
<> 134:ad3be0349dc5 1942 }
<> 134:ad3be0349dc5 1943
<> 134:ad3be0349dc5 1944 /**
<> 134:ad3be0349dc5 1945 * @brief Clear Channel 2 transfer error flag.
<> 134:ad3be0349dc5 1946 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
<> 134:ad3be0349dc5 1947 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1948 * @retval None
<> 134:ad3be0349dc5 1949 */
<> 134:ad3be0349dc5 1950 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1951 {
<> 134:ad3be0349dc5 1952 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
<> 134:ad3be0349dc5 1953 }
<> 134:ad3be0349dc5 1954
<> 134:ad3be0349dc5 1955 /**
<> 134:ad3be0349dc5 1956 * @brief Clear Channel 3 transfer error flag.
<> 134:ad3be0349dc5 1957 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
<> 134:ad3be0349dc5 1958 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1959 * @retval None
<> 134:ad3be0349dc5 1960 */
<> 134:ad3be0349dc5 1961 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1962 {
<> 134:ad3be0349dc5 1963 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
<> 134:ad3be0349dc5 1964 }
<> 134:ad3be0349dc5 1965
<> 134:ad3be0349dc5 1966 /**
<> 134:ad3be0349dc5 1967 * @brief Clear Channel 4 transfer error flag.
<> 134:ad3be0349dc5 1968 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
<> 134:ad3be0349dc5 1969 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1970 * @retval None
<> 134:ad3be0349dc5 1971 */
<> 134:ad3be0349dc5 1972 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1973 {
<> 134:ad3be0349dc5 1974 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
<> 134:ad3be0349dc5 1975 }
<> 134:ad3be0349dc5 1976
<> 134:ad3be0349dc5 1977 /**
<> 134:ad3be0349dc5 1978 * @brief Clear Channel 5 transfer error flag.
<> 134:ad3be0349dc5 1979 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
<> 134:ad3be0349dc5 1980 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1981 * @retval None
<> 134:ad3be0349dc5 1982 */
<> 134:ad3be0349dc5 1983 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1984 {
<> 134:ad3be0349dc5 1985 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
<> 134:ad3be0349dc5 1986 }
<> 134:ad3be0349dc5 1987
<> 134:ad3be0349dc5 1988 #if defined(DMA1_Channel6)
<> 134:ad3be0349dc5 1989 /**
<> 134:ad3be0349dc5 1990 * @brief Clear Channel 6 transfer error flag.
<> 134:ad3be0349dc5 1991 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
<> 134:ad3be0349dc5 1992 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 1993 * @retval None
<> 134:ad3be0349dc5 1994 */
<> 134:ad3be0349dc5 1995 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 1996 {
<> 134:ad3be0349dc5 1997 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
<> 134:ad3be0349dc5 1998 }
<> 134:ad3be0349dc5 1999 #endif
<> 134:ad3be0349dc5 2000
<> 134:ad3be0349dc5 2001 #if defined(DMA1_Channel7)
<> 134:ad3be0349dc5 2002 /**
<> 134:ad3be0349dc5 2003 * @brief Clear Channel 7 transfer error flag.
<> 134:ad3be0349dc5 2004 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
<> 134:ad3be0349dc5 2005 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 2006 * @retval None
<> 134:ad3be0349dc5 2007 */
<> 134:ad3be0349dc5 2008 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
<> 134:ad3be0349dc5 2009 {
<> 134:ad3be0349dc5 2010 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
<> 134:ad3be0349dc5 2011 }
<> 134:ad3be0349dc5 2012 #endif
<> 134:ad3be0349dc5 2013
<> 134:ad3be0349dc5 2014 /**
<> 134:ad3be0349dc5 2015 * @}
<> 134:ad3be0349dc5 2016 */
<> 134:ad3be0349dc5 2017
<> 134:ad3be0349dc5 2018 /** @defgroup DMA_LL_EF_IT_Management IT_Management
<> 134:ad3be0349dc5 2019 * @{
<> 134:ad3be0349dc5 2020 */
<> 134:ad3be0349dc5 2021 /**
<> 134:ad3be0349dc5 2022 * @brief Enable Transfer complete interrupt.
<> 134:ad3be0349dc5 2023 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
<> 134:ad3be0349dc5 2024 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 2025 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 2026 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 2027 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 2028 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 2029 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 2030 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 2031 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 2032 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 2033 * @retval None
<> 134:ad3be0349dc5 2034 */
<> 134:ad3be0349dc5 2035 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 2036 {
<> 134:ad3be0349dc5 2037 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<> 134:ad3be0349dc5 2038 }
<> 134:ad3be0349dc5 2039
<> 134:ad3be0349dc5 2040 /**
<> 134:ad3be0349dc5 2041 * @brief Enable Half transfer interrupt.
<> 134:ad3be0349dc5 2042 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
<> 134:ad3be0349dc5 2043 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 2044 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 2045 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 2046 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 2047 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 2048 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 2049 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 2050 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 2051 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 2052 * @retval None
<> 134:ad3be0349dc5 2053 */
<> 134:ad3be0349dc5 2054 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 2055 {
<> 134:ad3be0349dc5 2056 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<> 134:ad3be0349dc5 2057 }
<> 134:ad3be0349dc5 2058
<> 134:ad3be0349dc5 2059 /**
<> 134:ad3be0349dc5 2060 * @brief Enable Transfer error interrupt.
<> 134:ad3be0349dc5 2061 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
<> 134:ad3be0349dc5 2062 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 2063 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 2064 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 2065 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 2066 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 2067 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 2068 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 2069 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 2070 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 2071 * @retval None
<> 134:ad3be0349dc5 2072 */
<> 134:ad3be0349dc5 2073 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 2074 {
<> 134:ad3be0349dc5 2075 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<> 134:ad3be0349dc5 2076 }
<> 134:ad3be0349dc5 2077
<> 134:ad3be0349dc5 2078 /**
<> 134:ad3be0349dc5 2079 * @brief Disable Transfer complete interrupt.
<> 134:ad3be0349dc5 2080 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
<> 134:ad3be0349dc5 2081 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 2082 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 2083 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 2084 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 2085 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 2086 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 2087 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 2088 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 2089 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 2090 * @retval None
<> 134:ad3be0349dc5 2091 */
<> 134:ad3be0349dc5 2092 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 2093 {
<> 134:ad3be0349dc5 2094 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
<> 134:ad3be0349dc5 2095 }
<> 134:ad3be0349dc5 2096
<> 134:ad3be0349dc5 2097 /**
<> 134:ad3be0349dc5 2098 * @brief Disable Half transfer interrupt.
<> 134:ad3be0349dc5 2099 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
<> 134:ad3be0349dc5 2100 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 2101 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 2102 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 2103 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 2104 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 2105 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 2106 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 2107 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 2108 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 2109 * @retval None
<> 134:ad3be0349dc5 2110 */
<> 134:ad3be0349dc5 2111 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 2112 {
<> 134:ad3be0349dc5 2113 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
<> 134:ad3be0349dc5 2114 }
<> 134:ad3be0349dc5 2115
<> 134:ad3be0349dc5 2116 /**
<> 134:ad3be0349dc5 2117 * @brief Disable Transfer error interrupt.
<> 134:ad3be0349dc5 2118 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
<> 134:ad3be0349dc5 2119 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 2120 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 2121 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 2122 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 2123 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 2124 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 2125 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 2126 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 2127 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 2128 * @retval None
<> 134:ad3be0349dc5 2129 */
<> 134:ad3be0349dc5 2130 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 2131 {
<> 134:ad3be0349dc5 2132 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
<> 134:ad3be0349dc5 2133 }
<> 134:ad3be0349dc5 2134
<> 134:ad3be0349dc5 2135 /**
<> 134:ad3be0349dc5 2136 * @brief Check if Transfer complete Interrupt is enabled.
<> 134:ad3be0349dc5 2137 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
<> 134:ad3be0349dc5 2138 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 2139 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 2140 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 2141 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 2142 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 2143 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 2144 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 2145 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 2146 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 2147 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 2148 */
<> 134:ad3be0349dc5 2149 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 2150 {
<> 134:ad3be0349dc5 2151 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 134:ad3be0349dc5 2152 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
<> 134:ad3be0349dc5 2153 }
<> 134:ad3be0349dc5 2154
<> 134:ad3be0349dc5 2155 /**
<> 134:ad3be0349dc5 2156 * @brief Check if Half transfer Interrupt is enabled.
<> 134:ad3be0349dc5 2157 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
<> 134:ad3be0349dc5 2158 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 2159 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 2160 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 2161 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 2162 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 2163 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 2164 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 2165 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 2166 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 2167 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 2168 */
<> 134:ad3be0349dc5 2169 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 2170 {
<> 134:ad3be0349dc5 2171 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 134:ad3be0349dc5 2172 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
<> 134:ad3be0349dc5 2173 }
<> 134:ad3be0349dc5 2174
<> 134:ad3be0349dc5 2175 /**
<> 134:ad3be0349dc5 2176 * @brief Check if Transfer error Interrupt is enabled.
<> 134:ad3be0349dc5 2177 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
<> 134:ad3be0349dc5 2178 * @param DMAx DMAx Instance
<> 134:ad3be0349dc5 2179 * @param Channel This parameter can be one of the following values:
<> 134:ad3be0349dc5 2180 * @arg @ref LL_DMA_CHANNEL_1
<> 134:ad3be0349dc5 2181 * @arg @ref LL_DMA_CHANNEL_2
<> 134:ad3be0349dc5 2182 * @arg @ref LL_DMA_CHANNEL_3
<> 134:ad3be0349dc5 2183 * @arg @ref LL_DMA_CHANNEL_4
<> 134:ad3be0349dc5 2184 * @arg @ref LL_DMA_CHANNEL_5
<> 134:ad3be0349dc5 2185 * @arg @ref LL_DMA_CHANNEL_6
<> 134:ad3be0349dc5 2186 * @arg @ref LL_DMA_CHANNEL_7
<> 134:ad3be0349dc5 2187 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 2188 */
<> 134:ad3be0349dc5 2189 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
<> 134:ad3be0349dc5 2190 {
<> 134:ad3be0349dc5 2191 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
<> 134:ad3be0349dc5 2192 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
<> 134:ad3be0349dc5 2193 }
<> 134:ad3be0349dc5 2194
<> 134:ad3be0349dc5 2195 /**
<> 134:ad3be0349dc5 2196 * @}
<> 134:ad3be0349dc5 2197 */
<> 134:ad3be0349dc5 2198
<> 134:ad3be0349dc5 2199 #if defined(USE_FULL_LL_DRIVER)
<> 134:ad3be0349dc5 2200 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
<> 134:ad3be0349dc5 2201 * @{
<> 134:ad3be0349dc5 2202 */
<> 134:ad3be0349dc5 2203
<> 134:ad3be0349dc5 2204 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
<> 134:ad3be0349dc5 2205 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
<> 134:ad3be0349dc5 2206 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
<> 134:ad3be0349dc5 2207
<> 134:ad3be0349dc5 2208 /**
<> 134:ad3be0349dc5 2209 * @}
<> 134:ad3be0349dc5 2210 */
<> 134:ad3be0349dc5 2211 #endif /* USE_FULL_LL_DRIVER */
<> 134:ad3be0349dc5 2212
<> 134:ad3be0349dc5 2213 /**
<> 134:ad3be0349dc5 2214 * @}
<> 134:ad3be0349dc5 2215 */
<> 134:ad3be0349dc5 2216
<> 134:ad3be0349dc5 2217 /**
<> 134:ad3be0349dc5 2218 * @}
<> 134:ad3be0349dc5 2219 */
<> 134:ad3be0349dc5 2220
<> 134:ad3be0349dc5 2221 #endif /* DMA1 || DMA2 */
<> 134:ad3be0349dc5 2222
<> 134:ad3be0349dc5 2223 /**
<> 134:ad3be0349dc5 2224 * @}
<> 134:ad3be0349dc5 2225 */
<> 134:ad3be0349dc5 2226
<> 134:ad3be0349dc5 2227 #ifdef __cplusplus
<> 134:ad3be0349dc5 2228 }
<> 134:ad3be0349dc5 2229 #endif
<> 134:ad3be0349dc5 2230
<> 134:ad3be0349dc5 2231 #endif /* __STM32F0xx_LL_DMA_H */
<> 134:ad3be0349dc5 2232
<> 134:ad3be0349dc5 2233 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/