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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
134:ad3be0349dc5
Child:
160:5571c4ff569f
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 134:ad3be0349dc5 1 /**
<> 134:ad3be0349dc5 2 ******************************************************************************
<> 134:ad3be0349dc5 3 * @file stm32f0xx_ll_crs.h
<> 134:ad3be0349dc5 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.4.0
<> 134:ad3be0349dc5 6 * @date 27-May-2016
<> 134:ad3be0349dc5 7 * @brief Header file of CRS LL module.
<> 134:ad3be0349dc5 8 ******************************************************************************
<> 134:ad3be0349dc5 9 * @attention
<> 134:ad3be0349dc5 10 *
<> 134:ad3be0349dc5 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 134:ad3be0349dc5 12 *
<> 134:ad3be0349dc5 13 * Redistribution and use in source and binary forms, with or without modification,
<> 134:ad3be0349dc5 14 * are permitted provided that the following conditions are met:
<> 134:ad3be0349dc5 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 134:ad3be0349dc5 16 * this list of conditions and the following disclaimer.
<> 134:ad3be0349dc5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 134:ad3be0349dc5 18 * this list of conditions and the following disclaimer in the documentation
<> 134:ad3be0349dc5 19 * and/or other materials provided with the distribution.
<> 134:ad3be0349dc5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 134:ad3be0349dc5 21 * may be used to endorse or promote products derived from this software
<> 134:ad3be0349dc5 22 * without specific prior written permission.
<> 134:ad3be0349dc5 23 *
<> 134:ad3be0349dc5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 134:ad3be0349dc5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 134:ad3be0349dc5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 134:ad3be0349dc5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 134:ad3be0349dc5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 134:ad3be0349dc5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 134:ad3be0349dc5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 134:ad3be0349dc5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 134:ad3be0349dc5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 134:ad3be0349dc5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 134:ad3be0349dc5 34 *
<> 134:ad3be0349dc5 35 ******************************************************************************
<> 134:ad3be0349dc5 36 */
<> 134:ad3be0349dc5 37
<> 134:ad3be0349dc5 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 134:ad3be0349dc5 39 #ifndef __STM32F0xx_LL_CRS_H
<> 134:ad3be0349dc5 40 #define __STM32F0xx_LL_CRS_H
<> 134:ad3be0349dc5 41
<> 134:ad3be0349dc5 42 #ifdef __cplusplus
<> 134:ad3be0349dc5 43 extern "C" {
<> 134:ad3be0349dc5 44 #endif
<> 134:ad3be0349dc5 45
<> 134:ad3be0349dc5 46 /* Includes ------------------------------------------------------------------*/
<> 134:ad3be0349dc5 47 #include "stm32f0xx.h"
<> 134:ad3be0349dc5 48
<> 134:ad3be0349dc5 49 /** @addtogroup STM32F0xx_LL_Driver
<> 134:ad3be0349dc5 50 * @{
<> 134:ad3be0349dc5 51 */
<> 134:ad3be0349dc5 52
<> 134:ad3be0349dc5 53 #if defined(CRS)
<> 134:ad3be0349dc5 54
<> 134:ad3be0349dc5 55 /** @defgroup CRS_LL CRS
<> 134:ad3be0349dc5 56 * @{
<> 134:ad3be0349dc5 57 */
<> 134:ad3be0349dc5 58
<> 134:ad3be0349dc5 59 /* Private types -------------------------------------------------------------*/
<> 134:ad3be0349dc5 60 /* Private variables ---------------------------------------------------------*/
<> 134:ad3be0349dc5 61
<> 134:ad3be0349dc5 62 /* Private constants ---------------------------------------------------------*/
<> 134:ad3be0349dc5 63 /** @defgroup CRS_LL_Private_Constants CRS Private Constants
<> 134:ad3be0349dc5 64 * @{
<> 134:ad3be0349dc5 65 */
<> 134:ad3be0349dc5 66
<> 134:ad3be0349dc5 67 /* Defines used for the bit position in the register and perform offsets*/
<> 134:ad3be0349dc5 68 #define CRS_POSITION_TRIM (uint32_t)8U /* bit position in CR reg */
<> 134:ad3be0349dc5 69 #define CRS_POSITION_FECAP (uint32_t)16U /* bit position in ISR reg */
<> 134:ad3be0349dc5 70 #define CRS_POSITION_RELOAD (uint32_t)0U /* bit position in CFGR reg */
<> 134:ad3be0349dc5 71 #define CRS_POSITION_FELIM (uint32_t)16U /* bit position in CFGR reg */
<> 134:ad3be0349dc5 72
<> 134:ad3be0349dc5 73
<> 134:ad3be0349dc5 74 /**
<> 134:ad3be0349dc5 75 * @}
<> 134:ad3be0349dc5 76 */
<> 134:ad3be0349dc5 77
<> 134:ad3be0349dc5 78 /* Private macros ------------------------------------------------------------*/
<> 134:ad3be0349dc5 79
<> 134:ad3be0349dc5 80 /* Exported types ------------------------------------------------------------*/
<> 134:ad3be0349dc5 81 /* Exported constants --------------------------------------------------------*/
<> 134:ad3be0349dc5 82 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
<> 134:ad3be0349dc5 83 * @{
<> 134:ad3be0349dc5 84 */
<> 134:ad3be0349dc5 85
<> 134:ad3be0349dc5 86 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
<> 134:ad3be0349dc5 87 * @brief Flags defines which can be used with LL_CRS_ReadReg function
<> 134:ad3be0349dc5 88 * @{
<> 134:ad3be0349dc5 89 */
<> 134:ad3be0349dc5 90 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
<> 134:ad3be0349dc5 91 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
<> 134:ad3be0349dc5 92 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
<> 134:ad3be0349dc5 93 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
<> 134:ad3be0349dc5 94 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
<> 134:ad3be0349dc5 95 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
<> 134:ad3be0349dc5 96 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
<> 134:ad3be0349dc5 97 /**
<> 134:ad3be0349dc5 98 * @}
<> 134:ad3be0349dc5 99 */
<> 134:ad3be0349dc5 100
<> 134:ad3be0349dc5 101 /** @defgroup CRS_LL_EC_IT IT Defines
<> 134:ad3be0349dc5 102 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
<> 134:ad3be0349dc5 103 * @{
<> 134:ad3be0349dc5 104 */
<> 134:ad3be0349dc5 105 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
<> 134:ad3be0349dc5 106 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
<> 134:ad3be0349dc5 107 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
<> 134:ad3be0349dc5 108 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
<> 134:ad3be0349dc5 109 /**
<> 134:ad3be0349dc5 110 * @}
<> 134:ad3be0349dc5 111 */
<> 134:ad3be0349dc5 112
<> 134:ad3be0349dc5 113 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
<> 134:ad3be0349dc5 114 * @{
<> 134:ad3be0349dc5 115 */
<> 134:ad3be0349dc5 116 #define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
<> 134:ad3be0349dc5 117 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
<> 134:ad3be0349dc5 118 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
<> 134:ad3be0349dc5 119 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
<> 134:ad3be0349dc5 120 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
<> 134:ad3be0349dc5 121 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
<> 134:ad3be0349dc5 122 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
<> 134:ad3be0349dc5 123 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
<> 134:ad3be0349dc5 124 /**
<> 134:ad3be0349dc5 125 * @}
<> 134:ad3be0349dc5 126 */
<> 134:ad3be0349dc5 127
<> 134:ad3be0349dc5 128 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
<> 134:ad3be0349dc5 129 * @{
<> 134:ad3be0349dc5 130 */
<> 134:ad3be0349dc5 131 #define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */
<> 134:ad3be0349dc5 132 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
<> 134:ad3be0349dc5 133 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
<> 134:ad3be0349dc5 134 /**
<> 134:ad3be0349dc5 135 * @}
<> 134:ad3be0349dc5 136 */
<> 134:ad3be0349dc5 137
<> 134:ad3be0349dc5 138 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
<> 134:ad3be0349dc5 139 * @{
<> 134:ad3be0349dc5 140 */
<> 134:ad3be0349dc5 141 #define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
<> 134:ad3be0349dc5 142 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
<> 134:ad3be0349dc5 143 /**
<> 134:ad3be0349dc5 144 * @}
<> 134:ad3be0349dc5 145 */
<> 134:ad3be0349dc5 146
<> 134:ad3be0349dc5 147 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
<> 134:ad3be0349dc5 148 * @{
<> 134:ad3be0349dc5 149 */
<> 134:ad3be0349dc5 150 #define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
<> 134:ad3be0349dc5 151 #define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
<> 134:ad3be0349dc5 152 /**
<> 134:ad3be0349dc5 153 * @}
<> 134:ad3be0349dc5 154 */
<> 134:ad3be0349dc5 155
<> 134:ad3be0349dc5 156 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
<> 134:ad3be0349dc5 157 * @{
<> 134:ad3be0349dc5 158 */
<> 134:ad3be0349dc5 159 /**
<> 134:ad3be0349dc5 160 * @brief Reset value of the RELOAD field
<> 134:ad3be0349dc5 161 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
<> 134:ad3be0349dc5 162 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
<> 134:ad3be0349dc5 163 */
<> 134:ad3be0349dc5 164 #define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
<> 134:ad3be0349dc5 165
<> 134:ad3be0349dc5 166 /**
<> 134:ad3be0349dc5 167 * @brief Reset value of Frequency error limit.
<> 134:ad3be0349dc5 168 */
<> 134:ad3be0349dc5 169 #define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
<> 134:ad3be0349dc5 170
<> 134:ad3be0349dc5 171 /**
<> 134:ad3be0349dc5 172 * @brief Reset value of the HSI48 Calibration field
<> 134:ad3be0349dc5 173 * @note The default value is 32, which corresponds to the middle of the trimming interval.
<> 134:ad3be0349dc5 174 * The trimming step is around 67 kHz between two consecutive TRIM steps.
<> 134:ad3be0349dc5 175 * A higher TRIM value corresponds to a higher output frequency
<> 134:ad3be0349dc5 176 */
<> 134:ad3be0349dc5 177 #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U)
<> 134:ad3be0349dc5 178 /**
<> 134:ad3be0349dc5 179 * @}
<> 134:ad3be0349dc5 180 */
<> 134:ad3be0349dc5 181
<> 134:ad3be0349dc5 182 /**
<> 134:ad3be0349dc5 183 * @}
<> 134:ad3be0349dc5 184 */
<> 134:ad3be0349dc5 185
<> 134:ad3be0349dc5 186 /* Exported macro ------------------------------------------------------------*/
<> 134:ad3be0349dc5 187 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
<> 134:ad3be0349dc5 188 * @{
<> 134:ad3be0349dc5 189 */
<> 134:ad3be0349dc5 190
<> 134:ad3be0349dc5 191 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
<> 134:ad3be0349dc5 192 * @{
<> 134:ad3be0349dc5 193 */
<> 134:ad3be0349dc5 194
<> 134:ad3be0349dc5 195 /**
<> 134:ad3be0349dc5 196 * @brief Write a value in CRS register
<> 134:ad3be0349dc5 197 * @param __INSTANCE__ CRS Instance
<> 134:ad3be0349dc5 198 * @param __REG__ Register to be written
<> 134:ad3be0349dc5 199 * @param __VALUE__ Value to be written in the register
<> 134:ad3be0349dc5 200 * @retval None
<> 134:ad3be0349dc5 201 */
<> 134:ad3be0349dc5 202 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 134:ad3be0349dc5 203
<> 134:ad3be0349dc5 204 /**
<> 134:ad3be0349dc5 205 * @brief Read a value in CRS register
<> 134:ad3be0349dc5 206 * @param __INSTANCE__ CRS Instance
<> 134:ad3be0349dc5 207 * @param __REG__ Register to be read
<> 134:ad3be0349dc5 208 * @retval Register value
<> 134:ad3be0349dc5 209 */
<> 134:ad3be0349dc5 210 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 134:ad3be0349dc5 211 /**
<> 134:ad3be0349dc5 212 * @}
<> 134:ad3be0349dc5 213 */
<> 134:ad3be0349dc5 214
<> 134:ad3be0349dc5 215 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
<> 134:ad3be0349dc5 216 * @{
<> 134:ad3be0349dc5 217 */
<> 134:ad3be0349dc5 218
<> 134:ad3be0349dc5 219 /**
<> 134:ad3be0349dc5 220 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
<> 134:ad3be0349dc5 221 * @note The RELOAD value should be selected according to the ratio between
<> 134:ad3be0349dc5 222 * the target frequency and the frequency of the synchronization source after
<> 134:ad3be0349dc5 223 * prescaling. It is then decreased by one in order to reach the expected
<> 134:ad3be0349dc5 224 * synchronization on the zero value. The formula is the following:
<> 134:ad3be0349dc5 225 * RELOAD = (fTARGET / fSYNC) -1
<> 134:ad3be0349dc5 226 * @param __FTARGET__ Target frequency (value in Hz)
<> 134:ad3be0349dc5 227 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
<> 134:ad3be0349dc5 228 * @retval Reload value (in Hz)
<> 134:ad3be0349dc5 229 */
<> 134:ad3be0349dc5 230 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
<> 134:ad3be0349dc5 231
<> 134:ad3be0349dc5 232 /**
<> 134:ad3be0349dc5 233 * @}
<> 134:ad3be0349dc5 234 */
<> 134:ad3be0349dc5 235
<> 134:ad3be0349dc5 236 /**
<> 134:ad3be0349dc5 237 * @}
<> 134:ad3be0349dc5 238 */
<> 134:ad3be0349dc5 239
<> 134:ad3be0349dc5 240 /* Exported functions --------------------------------------------------------*/
<> 134:ad3be0349dc5 241 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
<> 134:ad3be0349dc5 242 * @{
<> 134:ad3be0349dc5 243 */
<> 134:ad3be0349dc5 244
<> 134:ad3be0349dc5 245 /** @defgroup CRS_LL_EF_Configuration Configuration
<> 134:ad3be0349dc5 246 * @{
<> 134:ad3be0349dc5 247 */
<> 134:ad3be0349dc5 248
<> 134:ad3be0349dc5 249 /**
<> 134:ad3be0349dc5 250 * @brief Enable Frequency error counter
<> 134:ad3be0349dc5 251 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
<> 134:ad3be0349dc5 252 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
<> 134:ad3be0349dc5 253 * @retval None
<> 134:ad3be0349dc5 254 */
<> 134:ad3be0349dc5 255 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
<> 134:ad3be0349dc5 256 {
<> 134:ad3be0349dc5 257 SET_BIT(CRS->CR, CRS_CR_CEN);
<> 134:ad3be0349dc5 258 }
<> 134:ad3be0349dc5 259
<> 134:ad3be0349dc5 260 /**
<> 134:ad3be0349dc5 261 * @brief Disable Frequency error counter
<> 134:ad3be0349dc5 262 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
<> 134:ad3be0349dc5 263 * @retval None
<> 134:ad3be0349dc5 264 */
<> 134:ad3be0349dc5 265 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
<> 134:ad3be0349dc5 266 {
<> 134:ad3be0349dc5 267 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
<> 134:ad3be0349dc5 268 }
<> 134:ad3be0349dc5 269
<> 134:ad3be0349dc5 270 /**
<> 134:ad3be0349dc5 271 * @brief Check if Frequency error counter is enabled or not
<> 134:ad3be0349dc5 272 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
<> 134:ad3be0349dc5 273 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 274 */
<> 134:ad3be0349dc5 275 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
<> 134:ad3be0349dc5 276 {
<> 134:ad3be0349dc5 277 return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
<> 134:ad3be0349dc5 278 }
<> 134:ad3be0349dc5 279
<> 134:ad3be0349dc5 280 /**
<> 134:ad3be0349dc5 281 * @brief Enable Automatic trimming counter
<> 134:ad3be0349dc5 282 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
<> 134:ad3be0349dc5 283 * @retval None
<> 134:ad3be0349dc5 284 */
<> 134:ad3be0349dc5 285 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
<> 134:ad3be0349dc5 286 {
<> 134:ad3be0349dc5 287 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
<> 134:ad3be0349dc5 288 }
<> 134:ad3be0349dc5 289
<> 134:ad3be0349dc5 290 /**
<> 134:ad3be0349dc5 291 * @brief Disable Automatic trimming counter
<> 134:ad3be0349dc5 292 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
<> 134:ad3be0349dc5 293 * @retval None
<> 134:ad3be0349dc5 294 */
<> 134:ad3be0349dc5 295 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
<> 134:ad3be0349dc5 296 {
<> 134:ad3be0349dc5 297 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
<> 134:ad3be0349dc5 298 }
<> 134:ad3be0349dc5 299
<> 134:ad3be0349dc5 300 /**
<> 134:ad3be0349dc5 301 * @brief Check if Automatic trimming is enabled or not
<> 134:ad3be0349dc5 302 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
<> 134:ad3be0349dc5 303 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 304 */
<> 134:ad3be0349dc5 305 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
<> 134:ad3be0349dc5 306 {
<> 134:ad3be0349dc5 307 return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
<> 134:ad3be0349dc5 308 }
<> 134:ad3be0349dc5 309
<> 134:ad3be0349dc5 310 /**
<> 134:ad3be0349dc5 311 * @brief Set HSI48 oscillator smooth trimming
<> 134:ad3be0349dc5 312 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
<> 134:ad3be0349dc5 313 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
<> 134:ad3be0349dc5 314 * @param Value a number between Min_Data = 0 and Max_Data = 63
<> 134:ad3be0349dc5 315 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
<> 134:ad3be0349dc5 316 * @retval None
<> 134:ad3be0349dc5 317 */
<> 134:ad3be0349dc5 318 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
<> 134:ad3be0349dc5 319 {
<> 134:ad3be0349dc5 320 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
<> 134:ad3be0349dc5 321 }
<> 134:ad3be0349dc5 322
<> 134:ad3be0349dc5 323 /**
<> 134:ad3be0349dc5 324 * @brief Get HSI48 oscillator smooth trimming
<> 134:ad3be0349dc5 325 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
<> 134:ad3be0349dc5 326 * @retval a number between Min_Data = 0 and Max_Data = 63
<> 134:ad3be0349dc5 327 */
<> 134:ad3be0349dc5 328 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
<> 134:ad3be0349dc5 329 {
<> 134:ad3be0349dc5 330 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
<> 134:ad3be0349dc5 331 }
<> 134:ad3be0349dc5 332
<> 134:ad3be0349dc5 333 /**
<> 134:ad3be0349dc5 334 * @brief Set counter reload value
<> 134:ad3be0349dc5 335 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
<> 134:ad3be0349dc5 336 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
<> 134:ad3be0349dc5 337 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
<> 134:ad3be0349dc5 338 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
<> 134:ad3be0349dc5 339 * @retval None
<> 134:ad3be0349dc5 340 */
<> 134:ad3be0349dc5 341 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
<> 134:ad3be0349dc5 342 {
<> 134:ad3be0349dc5 343 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
<> 134:ad3be0349dc5 344 }
<> 134:ad3be0349dc5 345
<> 134:ad3be0349dc5 346 /**
<> 134:ad3be0349dc5 347 * @brief Get counter reload value
<> 134:ad3be0349dc5 348 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
<> 134:ad3be0349dc5 349 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
<> 134:ad3be0349dc5 350 */
<> 134:ad3be0349dc5 351 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
<> 134:ad3be0349dc5 352 {
<> 134:ad3be0349dc5 353 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
<> 134:ad3be0349dc5 354 }
<> 134:ad3be0349dc5 355
<> 134:ad3be0349dc5 356 /**
<> 134:ad3be0349dc5 357 * @brief Set frequency error limit
<> 134:ad3be0349dc5 358 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
<> 134:ad3be0349dc5 359 * @param Value a number between Min_Data = 0 and Max_Data = 255
<> 134:ad3be0349dc5 360 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
<> 134:ad3be0349dc5 361 * @retval None
<> 134:ad3be0349dc5 362 */
<> 134:ad3be0349dc5 363 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
<> 134:ad3be0349dc5 364 {
<> 134:ad3be0349dc5 365 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
<> 134:ad3be0349dc5 366 }
<> 134:ad3be0349dc5 367
<> 134:ad3be0349dc5 368 /**
<> 134:ad3be0349dc5 369 * @brief Get frequency error limit
<> 134:ad3be0349dc5 370 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
<> 134:ad3be0349dc5 371 * @retval A number between Min_Data = 0 and Max_Data = 255
<> 134:ad3be0349dc5 372 */
<> 134:ad3be0349dc5 373 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
<> 134:ad3be0349dc5 374 {
<> 134:ad3be0349dc5 375 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
<> 134:ad3be0349dc5 376 }
<> 134:ad3be0349dc5 377
<> 134:ad3be0349dc5 378 /**
<> 134:ad3be0349dc5 379 * @brief Set division factor for SYNC signal
<> 134:ad3be0349dc5 380 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
<> 134:ad3be0349dc5 381 * @param Divider This parameter can be one of the following values:
<> 134:ad3be0349dc5 382 * @arg @ref LL_CRS_SYNC_DIV_1
<> 134:ad3be0349dc5 383 * @arg @ref LL_CRS_SYNC_DIV_2
<> 134:ad3be0349dc5 384 * @arg @ref LL_CRS_SYNC_DIV_4
<> 134:ad3be0349dc5 385 * @arg @ref LL_CRS_SYNC_DIV_8
<> 134:ad3be0349dc5 386 * @arg @ref LL_CRS_SYNC_DIV_16
<> 134:ad3be0349dc5 387 * @arg @ref LL_CRS_SYNC_DIV_32
<> 134:ad3be0349dc5 388 * @arg @ref LL_CRS_SYNC_DIV_64
<> 134:ad3be0349dc5 389 * @arg @ref LL_CRS_SYNC_DIV_128
<> 134:ad3be0349dc5 390 * @retval None
<> 134:ad3be0349dc5 391 */
<> 134:ad3be0349dc5 392 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
<> 134:ad3be0349dc5 393 {
<> 134:ad3be0349dc5 394 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
<> 134:ad3be0349dc5 395 }
<> 134:ad3be0349dc5 396
<> 134:ad3be0349dc5 397 /**
<> 134:ad3be0349dc5 398 * @brief Get division factor for SYNC signal
<> 134:ad3be0349dc5 399 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
<> 134:ad3be0349dc5 400 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 401 * @arg @ref LL_CRS_SYNC_DIV_1
<> 134:ad3be0349dc5 402 * @arg @ref LL_CRS_SYNC_DIV_2
<> 134:ad3be0349dc5 403 * @arg @ref LL_CRS_SYNC_DIV_4
<> 134:ad3be0349dc5 404 * @arg @ref LL_CRS_SYNC_DIV_8
<> 134:ad3be0349dc5 405 * @arg @ref LL_CRS_SYNC_DIV_16
<> 134:ad3be0349dc5 406 * @arg @ref LL_CRS_SYNC_DIV_32
<> 134:ad3be0349dc5 407 * @arg @ref LL_CRS_SYNC_DIV_64
<> 134:ad3be0349dc5 408 * @arg @ref LL_CRS_SYNC_DIV_128
<> 134:ad3be0349dc5 409 */
<> 134:ad3be0349dc5 410 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
<> 134:ad3be0349dc5 411 {
<> 134:ad3be0349dc5 412 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
<> 134:ad3be0349dc5 413 }
<> 134:ad3be0349dc5 414
<> 134:ad3be0349dc5 415 /**
<> 134:ad3be0349dc5 416 * @brief Set SYNC signal source
<> 134:ad3be0349dc5 417 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
<> 134:ad3be0349dc5 418 * @param Source This parameter can be one of the following values:
<> 134:ad3be0349dc5 419 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
<> 134:ad3be0349dc5 420 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
<> 134:ad3be0349dc5 421 * @arg @ref LL_CRS_SYNC_SOURCE_USB
<> 134:ad3be0349dc5 422 * @retval None
<> 134:ad3be0349dc5 423 */
<> 134:ad3be0349dc5 424 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
<> 134:ad3be0349dc5 425 {
<> 134:ad3be0349dc5 426 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
<> 134:ad3be0349dc5 427 }
<> 134:ad3be0349dc5 428
<> 134:ad3be0349dc5 429 /**
<> 134:ad3be0349dc5 430 * @brief Get SYNC signal source
<> 134:ad3be0349dc5 431 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
<> 134:ad3be0349dc5 432 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 433 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
<> 134:ad3be0349dc5 434 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
<> 134:ad3be0349dc5 435 * @arg @ref LL_CRS_SYNC_SOURCE_USB
<> 134:ad3be0349dc5 436 */
<> 134:ad3be0349dc5 437 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
<> 134:ad3be0349dc5 438 {
<> 134:ad3be0349dc5 439 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
<> 134:ad3be0349dc5 440 }
<> 134:ad3be0349dc5 441
<> 134:ad3be0349dc5 442 /**
<> 134:ad3be0349dc5 443 * @brief Set input polarity for the SYNC signal source
<> 134:ad3be0349dc5 444 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
<> 134:ad3be0349dc5 445 * @param Polarity This parameter can be one of the following values:
<> 134:ad3be0349dc5 446 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
<> 134:ad3be0349dc5 447 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
<> 134:ad3be0349dc5 448 * @retval None
<> 134:ad3be0349dc5 449 */
<> 134:ad3be0349dc5 450 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
<> 134:ad3be0349dc5 451 {
<> 134:ad3be0349dc5 452 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
<> 134:ad3be0349dc5 453 }
<> 134:ad3be0349dc5 454
<> 134:ad3be0349dc5 455 /**
<> 134:ad3be0349dc5 456 * @brief Get input polarity for the SYNC signal source
<> 134:ad3be0349dc5 457 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
<> 134:ad3be0349dc5 458 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 459 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
<> 134:ad3be0349dc5 460 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
<> 134:ad3be0349dc5 461 */
<> 134:ad3be0349dc5 462 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
<> 134:ad3be0349dc5 463 {
<> 134:ad3be0349dc5 464 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
<> 134:ad3be0349dc5 465 }
<> 134:ad3be0349dc5 466
<> 134:ad3be0349dc5 467 /**
<> 134:ad3be0349dc5 468 * @brief Configure CRS for the synchronization
<> 134:ad3be0349dc5 469 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
<> 134:ad3be0349dc5 470 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
<> 134:ad3be0349dc5 471 * CFGR FELIM LL_CRS_ConfigSynchronization\n
<> 134:ad3be0349dc5 472 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
<> 134:ad3be0349dc5 473 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
<> 134:ad3be0349dc5 474 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
<> 134:ad3be0349dc5 475 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
<> 134:ad3be0349dc5 476 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
<> 134:ad3be0349dc5 477 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
<> 134:ad3be0349dc5 478 * @param Settings This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 479 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
<> 134:ad3be0349dc5 480 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
<> 134:ad3be0349dc5 481 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
<> 134:ad3be0349dc5 482 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
<> 134:ad3be0349dc5 483 * @retval None
<> 134:ad3be0349dc5 484 */
<> 134:ad3be0349dc5 485 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
<> 134:ad3be0349dc5 486 {
<> 134:ad3be0349dc5 487 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
<> 134:ad3be0349dc5 488 MODIFY_REG(CRS->CFGR,
<> 134:ad3be0349dc5 489 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
<> 134:ad3be0349dc5 490 ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
<> 134:ad3be0349dc5 491 }
<> 134:ad3be0349dc5 492
<> 134:ad3be0349dc5 493 /**
<> 134:ad3be0349dc5 494 * @}
<> 134:ad3be0349dc5 495 */
<> 134:ad3be0349dc5 496
<> 134:ad3be0349dc5 497 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
<> 134:ad3be0349dc5 498 * @{
<> 134:ad3be0349dc5 499 */
<> 134:ad3be0349dc5 500
<> 134:ad3be0349dc5 501 /**
<> 134:ad3be0349dc5 502 * @brief Generate software SYNC event
<> 134:ad3be0349dc5 503 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
<> 134:ad3be0349dc5 504 * @retval None
<> 134:ad3be0349dc5 505 */
<> 134:ad3be0349dc5 506 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
<> 134:ad3be0349dc5 507 {
<> 134:ad3be0349dc5 508 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
<> 134:ad3be0349dc5 509 }
<> 134:ad3be0349dc5 510
<> 134:ad3be0349dc5 511 /**
<> 134:ad3be0349dc5 512 * @brief Get the frequency error direction latched in the time of the last
<> 134:ad3be0349dc5 513 * SYNC event
<> 134:ad3be0349dc5 514 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
<> 134:ad3be0349dc5 515 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 516 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
<> 134:ad3be0349dc5 517 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
<> 134:ad3be0349dc5 518 */
<> 134:ad3be0349dc5 519 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
<> 134:ad3be0349dc5 520 {
<> 134:ad3be0349dc5 521 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
<> 134:ad3be0349dc5 522 }
<> 134:ad3be0349dc5 523
<> 134:ad3be0349dc5 524 /**
<> 134:ad3be0349dc5 525 * @brief Get the frequency error counter value latched in the time of the last SYNC event
<> 134:ad3be0349dc5 526 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
<> 134:ad3be0349dc5 527 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
<> 134:ad3be0349dc5 528 */
<> 134:ad3be0349dc5 529 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
<> 134:ad3be0349dc5 530 {
<> 134:ad3be0349dc5 531 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
<> 134:ad3be0349dc5 532 }
<> 134:ad3be0349dc5 533
<> 134:ad3be0349dc5 534 /**
<> 134:ad3be0349dc5 535 * @}
<> 134:ad3be0349dc5 536 */
<> 134:ad3be0349dc5 537
<> 134:ad3be0349dc5 538 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
<> 134:ad3be0349dc5 539 * @{
<> 134:ad3be0349dc5 540 */
<> 134:ad3be0349dc5 541
<> 134:ad3be0349dc5 542 /**
<> 134:ad3be0349dc5 543 * @brief Check if SYNC event OK signal occurred or not
<> 134:ad3be0349dc5 544 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
<> 134:ad3be0349dc5 545 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 546 */
<> 134:ad3be0349dc5 547 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
<> 134:ad3be0349dc5 548 {
<> 134:ad3be0349dc5 549 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
<> 134:ad3be0349dc5 550 }
<> 134:ad3be0349dc5 551
<> 134:ad3be0349dc5 552 /**
<> 134:ad3be0349dc5 553 * @brief Check if SYNC warning signal occurred or not
<> 134:ad3be0349dc5 554 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
<> 134:ad3be0349dc5 555 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 556 */
<> 134:ad3be0349dc5 557 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
<> 134:ad3be0349dc5 558 {
<> 134:ad3be0349dc5 559 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
<> 134:ad3be0349dc5 560 }
<> 134:ad3be0349dc5 561
<> 134:ad3be0349dc5 562 /**
<> 134:ad3be0349dc5 563 * @brief Check if Synchronization or trimming error signal occurred or not
<> 134:ad3be0349dc5 564 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
<> 134:ad3be0349dc5 565 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 566 */
<> 134:ad3be0349dc5 567 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
<> 134:ad3be0349dc5 568 {
<> 134:ad3be0349dc5 569 return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
<> 134:ad3be0349dc5 570 }
<> 134:ad3be0349dc5 571
<> 134:ad3be0349dc5 572 /**
<> 134:ad3be0349dc5 573 * @brief Check if Expected SYNC signal occurred or not
<> 134:ad3be0349dc5 574 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
<> 134:ad3be0349dc5 575 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 576 */
<> 134:ad3be0349dc5 577 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
<> 134:ad3be0349dc5 578 {
<> 134:ad3be0349dc5 579 return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
<> 134:ad3be0349dc5 580 }
<> 134:ad3be0349dc5 581
<> 134:ad3be0349dc5 582 /**
<> 134:ad3be0349dc5 583 * @brief Check if SYNC error signal occurred or not
<> 134:ad3be0349dc5 584 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
<> 134:ad3be0349dc5 585 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 586 */
<> 134:ad3be0349dc5 587 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
<> 134:ad3be0349dc5 588 {
<> 134:ad3be0349dc5 589 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
<> 134:ad3be0349dc5 590 }
<> 134:ad3be0349dc5 591
<> 134:ad3be0349dc5 592 /**
<> 134:ad3be0349dc5 593 * @brief Check if SYNC missed error signal occurred or not
<> 134:ad3be0349dc5 594 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
<> 134:ad3be0349dc5 595 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 596 */
<> 134:ad3be0349dc5 597 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
<> 134:ad3be0349dc5 598 {
<> 134:ad3be0349dc5 599 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
<> 134:ad3be0349dc5 600 }
<> 134:ad3be0349dc5 601
<> 134:ad3be0349dc5 602 /**
<> 134:ad3be0349dc5 603 * @brief Check if Trimming overflow or underflow occurred or not
<> 134:ad3be0349dc5 604 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
<> 134:ad3be0349dc5 605 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 606 */
<> 134:ad3be0349dc5 607 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
<> 134:ad3be0349dc5 608 {
<> 134:ad3be0349dc5 609 return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
<> 134:ad3be0349dc5 610 }
<> 134:ad3be0349dc5 611
<> 134:ad3be0349dc5 612 /**
<> 134:ad3be0349dc5 613 * @brief Clear the SYNC event OK flag
<> 134:ad3be0349dc5 614 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
<> 134:ad3be0349dc5 615 * @retval None
<> 134:ad3be0349dc5 616 */
<> 134:ad3be0349dc5 617 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
<> 134:ad3be0349dc5 618 {
<> 134:ad3be0349dc5 619 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
<> 134:ad3be0349dc5 620 }
<> 134:ad3be0349dc5 621
<> 134:ad3be0349dc5 622 /**
<> 134:ad3be0349dc5 623 * @brief Clear the SYNC warning flag
<> 134:ad3be0349dc5 624 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
<> 134:ad3be0349dc5 625 * @retval None
<> 134:ad3be0349dc5 626 */
<> 134:ad3be0349dc5 627 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
<> 134:ad3be0349dc5 628 {
<> 134:ad3be0349dc5 629 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
<> 134:ad3be0349dc5 630 }
<> 134:ad3be0349dc5 631
<> 134:ad3be0349dc5 632 /**
<> 134:ad3be0349dc5 633 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
<> 134:ad3be0349dc5 634 * the ERR flag
<> 134:ad3be0349dc5 635 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
<> 134:ad3be0349dc5 636 * @retval None
<> 134:ad3be0349dc5 637 */
<> 134:ad3be0349dc5 638 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
<> 134:ad3be0349dc5 639 {
<> 134:ad3be0349dc5 640 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
<> 134:ad3be0349dc5 641 }
<> 134:ad3be0349dc5 642
<> 134:ad3be0349dc5 643 /**
<> 134:ad3be0349dc5 644 * @brief Clear Expected SYNC flag
<> 134:ad3be0349dc5 645 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
<> 134:ad3be0349dc5 646 * @retval None
<> 134:ad3be0349dc5 647 */
<> 134:ad3be0349dc5 648 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
<> 134:ad3be0349dc5 649 {
<> 134:ad3be0349dc5 650 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
<> 134:ad3be0349dc5 651 }
<> 134:ad3be0349dc5 652
<> 134:ad3be0349dc5 653 /**
<> 134:ad3be0349dc5 654 * @}
<> 134:ad3be0349dc5 655 */
<> 134:ad3be0349dc5 656
<> 134:ad3be0349dc5 657 /** @defgroup CRS_LL_EF_IT_Management IT_Management
<> 134:ad3be0349dc5 658 * @{
<> 134:ad3be0349dc5 659 */
<> 134:ad3be0349dc5 660
<> 134:ad3be0349dc5 661 /**
<> 134:ad3be0349dc5 662 * @brief Enable SYNC event OK interrupt
<> 134:ad3be0349dc5 663 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
<> 134:ad3be0349dc5 664 * @retval None
<> 134:ad3be0349dc5 665 */
<> 134:ad3be0349dc5 666 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
<> 134:ad3be0349dc5 667 {
<> 134:ad3be0349dc5 668 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
<> 134:ad3be0349dc5 669 }
<> 134:ad3be0349dc5 670
<> 134:ad3be0349dc5 671 /**
<> 134:ad3be0349dc5 672 * @brief Disable SYNC event OK interrupt
<> 134:ad3be0349dc5 673 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
<> 134:ad3be0349dc5 674 * @retval None
<> 134:ad3be0349dc5 675 */
<> 134:ad3be0349dc5 676 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
<> 134:ad3be0349dc5 677 {
<> 134:ad3be0349dc5 678 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
<> 134:ad3be0349dc5 679 }
<> 134:ad3be0349dc5 680
<> 134:ad3be0349dc5 681 /**
<> 134:ad3be0349dc5 682 * @brief Check if SYNC event OK interrupt is enabled or not
<> 134:ad3be0349dc5 683 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
<> 134:ad3be0349dc5 684 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 685 */
<> 134:ad3be0349dc5 686 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
<> 134:ad3be0349dc5 687 {
<> 134:ad3be0349dc5 688 return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
<> 134:ad3be0349dc5 689 }
<> 134:ad3be0349dc5 690
<> 134:ad3be0349dc5 691 /**
<> 134:ad3be0349dc5 692 * @brief Enable SYNC warning interrupt
<> 134:ad3be0349dc5 693 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
<> 134:ad3be0349dc5 694 * @retval None
<> 134:ad3be0349dc5 695 */
<> 134:ad3be0349dc5 696 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
<> 134:ad3be0349dc5 697 {
<> 134:ad3be0349dc5 698 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
<> 134:ad3be0349dc5 699 }
<> 134:ad3be0349dc5 700
<> 134:ad3be0349dc5 701 /**
<> 134:ad3be0349dc5 702 * @brief Disable SYNC warning interrupt
<> 134:ad3be0349dc5 703 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
<> 134:ad3be0349dc5 704 * @retval None
<> 134:ad3be0349dc5 705 */
<> 134:ad3be0349dc5 706 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
<> 134:ad3be0349dc5 707 {
<> 134:ad3be0349dc5 708 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
<> 134:ad3be0349dc5 709 }
<> 134:ad3be0349dc5 710
<> 134:ad3be0349dc5 711 /**
<> 134:ad3be0349dc5 712 * @brief Check if SYNC warning interrupt is enabled or not
<> 134:ad3be0349dc5 713 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
<> 134:ad3be0349dc5 714 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 715 */
<> 134:ad3be0349dc5 716 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
<> 134:ad3be0349dc5 717 {
<> 134:ad3be0349dc5 718 return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
<> 134:ad3be0349dc5 719 }
<> 134:ad3be0349dc5 720
<> 134:ad3be0349dc5 721 /**
<> 134:ad3be0349dc5 722 * @brief Enable Synchronization or trimming error interrupt
<> 134:ad3be0349dc5 723 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
<> 134:ad3be0349dc5 724 * @retval None
<> 134:ad3be0349dc5 725 */
<> 134:ad3be0349dc5 726 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
<> 134:ad3be0349dc5 727 {
<> 134:ad3be0349dc5 728 SET_BIT(CRS->CR, CRS_CR_ERRIE);
<> 134:ad3be0349dc5 729 }
<> 134:ad3be0349dc5 730
<> 134:ad3be0349dc5 731 /**
<> 134:ad3be0349dc5 732 * @brief Disable Synchronization or trimming error interrupt
<> 134:ad3be0349dc5 733 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
<> 134:ad3be0349dc5 734 * @retval None
<> 134:ad3be0349dc5 735 */
<> 134:ad3be0349dc5 736 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
<> 134:ad3be0349dc5 737 {
<> 134:ad3be0349dc5 738 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
<> 134:ad3be0349dc5 739 }
<> 134:ad3be0349dc5 740
<> 134:ad3be0349dc5 741 /**
<> 134:ad3be0349dc5 742 * @brief Check if Synchronization or trimming error interrupt is enabled or not
<> 134:ad3be0349dc5 743 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
<> 134:ad3be0349dc5 744 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 745 */
<> 134:ad3be0349dc5 746 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
<> 134:ad3be0349dc5 747 {
<> 134:ad3be0349dc5 748 return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
<> 134:ad3be0349dc5 749 }
<> 134:ad3be0349dc5 750
<> 134:ad3be0349dc5 751 /**
<> 134:ad3be0349dc5 752 * @brief Enable Expected SYNC interrupt
<> 134:ad3be0349dc5 753 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
<> 134:ad3be0349dc5 754 * @retval None
<> 134:ad3be0349dc5 755 */
<> 134:ad3be0349dc5 756 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
<> 134:ad3be0349dc5 757 {
<> 134:ad3be0349dc5 758 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
<> 134:ad3be0349dc5 759 }
<> 134:ad3be0349dc5 760
<> 134:ad3be0349dc5 761 /**
<> 134:ad3be0349dc5 762 * @brief Disable Expected SYNC interrupt
<> 134:ad3be0349dc5 763 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
<> 134:ad3be0349dc5 764 * @retval None
<> 134:ad3be0349dc5 765 */
<> 134:ad3be0349dc5 766 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
<> 134:ad3be0349dc5 767 {
<> 134:ad3be0349dc5 768 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
<> 134:ad3be0349dc5 769 }
<> 134:ad3be0349dc5 770
<> 134:ad3be0349dc5 771 /**
<> 134:ad3be0349dc5 772 * @brief Check if Expected SYNC interrupt is enabled or not
<> 134:ad3be0349dc5 773 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
<> 134:ad3be0349dc5 774 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 775 */
<> 134:ad3be0349dc5 776 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
<> 134:ad3be0349dc5 777 {
<> 134:ad3be0349dc5 778 return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
<> 134:ad3be0349dc5 779 }
<> 134:ad3be0349dc5 780
<> 134:ad3be0349dc5 781 /**
<> 134:ad3be0349dc5 782 * @}
<> 134:ad3be0349dc5 783 */
<> 134:ad3be0349dc5 784
<> 134:ad3be0349dc5 785 #if defined(USE_FULL_LL_DRIVER)
<> 134:ad3be0349dc5 786 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
<> 134:ad3be0349dc5 787 * @{
<> 134:ad3be0349dc5 788 */
<> 134:ad3be0349dc5 789
<> 134:ad3be0349dc5 790 ErrorStatus LL_CRS_DeInit(void);
<> 134:ad3be0349dc5 791
<> 134:ad3be0349dc5 792 /**
<> 134:ad3be0349dc5 793 * @}
<> 134:ad3be0349dc5 794 */
<> 134:ad3be0349dc5 795 #endif /* USE_FULL_LL_DRIVER */
<> 134:ad3be0349dc5 796
<> 134:ad3be0349dc5 797 /**
<> 134:ad3be0349dc5 798 * @}
<> 134:ad3be0349dc5 799 */
<> 134:ad3be0349dc5 800
<> 134:ad3be0349dc5 801 /**
<> 134:ad3be0349dc5 802 * @}
<> 134:ad3be0349dc5 803 */
<> 134:ad3be0349dc5 804
<> 134:ad3be0349dc5 805 #endif /* defined(CRS) */
<> 134:ad3be0349dc5 806
<> 134:ad3be0349dc5 807 /**
<> 134:ad3be0349dc5 808 * @}
<> 134:ad3be0349dc5 809 */
<> 134:ad3be0349dc5 810
<> 134:ad3be0349dc5 811 #ifdef __cplusplus
<> 134:ad3be0349dc5 812 }
<> 134:ad3be0349dc5 813 #endif
<> 134:ad3be0349dc5 814
<> 134:ad3be0349dc5 815 #endif /* __STM32F0xx_LL_CRS_H */
<> 134:ad3be0349dc5 816
<> 134:ad3be0349dc5 817 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/