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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_bus.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
134:ad3be0349dc5
Child:
160:5571c4ff569f
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 134:ad3be0349dc5 1 /**
<> 134:ad3be0349dc5 2 ******************************************************************************
<> 134:ad3be0349dc5 3 * @file stm32f0xx_ll_bus.h
<> 134:ad3be0349dc5 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.4.0
<> 134:ad3be0349dc5 6 * @date 27-May-2016
<> 134:ad3be0349dc5 7 * @brief Header file of BUS LL module.
<> 134:ad3be0349dc5 8
<> 134:ad3be0349dc5 9 @verbatim
<> 134:ad3be0349dc5 10 ##### RCC Limitations #####
<> 134:ad3be0349dc5 11 ==============================================================================
<> 134:ad3be0349dc5 12 [..]
<> 134:ad3be0349dc5 13 A delay between an RCC peripheral clock enable and the effective peripheral
<> 134:ad3be0349dc5 14 enabling should be taken into account in order to manage the peripheral read/write
<> 134:ad3be0349dc5 15 from/to registers.
<> 134:ad3be0349dc5 16 (+) This delay depends on the peripheral mapping.
<> 134:ad3be0349dc5 17 (++) AHB & APB peripherals, 1 dummy read is necessary
<> 134:ad3be0349dc5 18
<> 134:ad3be0349dc5 19 [..]
<> 134:ad3be0349dc5 20 Workarounds:
<> 134:ad3be0349dc5 21 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
<> 134:ad3be0349dc5 22 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
<> 134:ad3be0349dc5 23
<> 134:ad3be0349dc5 24 @endverbatim
<> 134:ad3be0349dc5 25 ******************************************************************************
<> 134:ad3be0349dc5 26 * @attention
<> 134:ad3be0349dc5 27 *
<> 134:ad3be0349dc5 28 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 134:ad3be0349dc5 29 *
<> 134:ad3be0349dc5 30 * Redistribution and use in source and binary forms, with or without modification,
<> 134:ad3be0349dc5 31 * are permitted provided that the following conditions are met:
<> 134:ad3be0349dc5 32 * 1. Redistributions of source code must retain the above copyright notice,
<> 134:ad3be0349dc5 33 * this list of conditions and the following disclaimer.
<> 134:ad3be0349dc5 34 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 134:ad3be0349dc5 35 * this list of conditions and the following disclaimer in the documentation
<> 134:ad3be0349dc5 36 * and/or other materials provided with the distribution.
<> 134:ad3be0349dc5 37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 134:ad3be0349dc5 38 * may be used to endorse or promote products derived from this software
<> 134:ad3be0349dc5 39 * without specific prior written permission.
<> 134:ad3be0349dc5 40 *
<> 134:ad3be0349dc5 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 134:ad3be0349dc5 42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 134:ad3be0349dc5 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 134:ad3be0349dc5 44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 134:ad3be0349dc5 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 134:ad3be0349dc5 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 134:ad3be0349dc5 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 134:ad3be0349dc5 48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 134:ad3be0349dc5 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 134:ad3be0349dc5 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 134:ad3be0349dc5 51 *
<> 134:ad3be0349dc5 52 ******************************************************************************
<> 134:ad3be0349dc5 53 */
<> 134:ad3be0349dc5 54
<> 134:ad3be0349dc5 55 /* Define to prevent recursive inclusion -------------------------------------*/
<> 134:ad3be0349dc5 56 #ifndef __STM32F0xx_LL_BUS_H
<> 134:ad3be0349dc5 57 #define __STM32F0xx_LL_BUS_H
<> 134:ad3be0349dc5 58
<> 134:ad3be0349dc5 59 #ifdef __cplusplus
<> 134:ad3be0349dc5 60 extern "C" {
<> 134:ad3be0349dc5 61 #endif
<> 134:ad3be0349dc5 62
<> 134:ad3be0349dc5 63 /* Includes ------------------------------------------------------------------*/
<> 134:ad3be0349dc5 64 #include "stm32f0xx.h"
<> 134:ad3be0349dc5 65
<> 134:ad3be0349dc5 66 /** @addtogroup STM32F0xx_LL_Driver
<> 134:ad3be0349dc5 67 * @{
<> 134:ad3be0349dc5 68 */
<> 134:ad3be0349dc5 69
<> 134:ad3be0349dc5 70 #if defined(RCC)
<> 134:ad3be0349dc5 71
<> 134:ad3be0349dc5 72 /** @defgroup BUS_LL BUS
<> 134:ad3be0349dc5 73 * @{
<> 134:ad3be0349dc5 74 */
<> 134:ad3be0349dc5 75
<> 134:ad3be0349dc5 76 /* Private types -------------------------------------------------------------*/
<> 134:ad3be0349dc5 77 /* Private variables ---------------------------------------------------------*/
<> 134:ad3be0349dc5 78
<> 134:ad3be0349dc5 79 /* Private constants ---------------------------------------------------------*/
<> 134:ad3be0349dc5 80
<> 134:ad3be0349dc5 81 /* Private macros ------------------------------------------------------------*/
<> 134:ad3be0349dc5 82
<> 134:ad3be0349dc5 83 /* Exported types ------------------------------------------------------------*/
<> 134:ad3be0349dc5 84 /* Exported constants --------------------------------------------------------*/
<> 134:ad3be0349dc5 85 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
<> 134:ad3be0349dc5 86 * @{
<> 134:ad3be0349dc5 87 */
<> 134:ad3be0349dc5 88
<> 134:ad3be0349dc5 89 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
<> 134:ad3be0349dc5 90 * @{
<> 134:ad3be0349dc5 91 */
<> 134:ad3be0349dc5 92 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
<> 134:ad3be0349dc5 93 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
<> 134:ad3be0349dc5 94 #if defined(DMA2)
<> 134:ad3be0349dc5 95 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
<> 134:ad3be0349dc5 96 #endif /*DMA2*/
<> 134:ad3be0349dc5 97 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
<> 134:ad3be0349dc5 98 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
<> 134:ad3be0349dc5 99 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
<> 134:ad3be0349dc5 100 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
<> 134:ad3be0349dc5 101 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
<> 134:ad3be0349dc5 102 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
<> 134:ad3be0349dc5 103 #if defined(GPIOD)
<> 134:ad3be0349dc5 104 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
<> 134:ad3be0349dc5 105 #endif /*GPIOD*/
<> 134:ad3be0349dc5 106 #if defined(GPIOE)
<> 134:ad3be0349dc5 107 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
<> 134:ad3be0349dc5 108 #endif /*GPIOE*/
<> 134:ad3be0349dc5 109 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
<> 134:ad3be0349dc5 110 #if defined(TSC)
<> 134:ad3be0349dc5 111 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
<> 134:ad3be0349dc5 112 #endif /*TSC*/
<> 134:ad3be0349dc5 113 /**
<> 134:ad3be0349dc5 114 * @}
<> 134:ad3be0349dc5 115 */
<> 134:ad3be0349dc5 116
<> 134:ad3be0349dc5 117 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
<> 134:ad3be0349dc5 118 * @{
<> 134:ad3be0349dc5 119 */
<> 134:ad3be0349dc5 120 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
<> 134:ad3be0349dc5 121 #if defined(TIM2)
<> 134:ad3be0349dc5 122 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
<> 134:ad3be0349dc5 123 #endif /*TIM2*/
<> 134:ad3be0349dc5 124 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
<> 134:ad3be0349dc5 125 #if defined(TIM6)
<> 134:ad3be0349dc5 126 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
<> 134:ad3be0349dc5 127 #endif /*TIM6*/
<> 134:ad3be0349dc5 128 #if defined(TIM7)
<> 134:ad3be0349dc5 129 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
<> 134:ad3be0349dc5 130 #endif /*TIM7*/
<> 134:ad3be0349dc5 131 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
<> 134:ad3be0349dc5 132 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
<> 134:ad3be0349dc5 133 #if defined(SPI2)
<> 134:ad3be0349dc5 134 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
<> 134:ad3be0349dc5 135 #endif /*SPI2*/
<> 134:ad3be0349dc5 136 #if defined(USART2)
<> 134:ad3be0349dc5 137 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
<> 134:ad3be0349dc5 138 #endif /* USART2 */
<> 134:ad3be0349dc5 139 #if defined(USART3)
<> 134:ad3be0349dc5 140 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
<> 134:ad3be0349dc5 141 #endif /* USART3 */
<> 134:ad3be0349dc5 142 #if defined(USART4)
<> 134:ad3be0349dc5 143 #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN
<> 134:ad3be0349dc5 144 #endif /* USART4 */
<> 134:ad3be0349dc5 145 #if defined(USART5)
<> 134:ad3be0349dc5 146 #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN
<> 134:ad3be0349dc5 147 #endif /* USART5 */
<> 134:ad3be0349dc5 148 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
<> 134:ad3be0349dc5 149 #if defined(I2C2)
<> 134:ad3be0349dc5 150 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
<> 134:ad3be0349dc5 151 #endif /*I2C2*/
<> 134:ad3be0349dc5 152 #if defined(USB)
<> 134:ad3be0349dc5 153 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
<> 134:ad3be0349dc5 154 #endif /* USB */
<> 134:ad3be0349dc5 155 #if defined(CAN)
<> 134:ad3be0349dc5 156 #define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
<> 134:ad3be0349dc5 157 #endif /*CAN*/
<> 134:ad3be0349dc5 158 #if defined(CRS)
<> 134:ad3be0349dc5 159 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN
<> 134:ad3be0349dc5 160 #endif /*CRS*/
<> 134:ad3be0349dc5 161 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
<> 134:ad3be0349dc5 162 #if defined(DAC)
<> 134:ad3be0349dc5 163 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
<> 134:ad3be0349dc5 164 #endif /*DAC*/
<> 134:ad3be0349dc5 165 #if defined(CEC)
<> 134:ad3be0349dc5 166 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
<> 134:ad3be0349dc5 167 #endif /*CEC*/
<> 134:ad3be0349dc5 168 /**
<> 134:ad3be0349dc5 169 * @}
<> 134:ad3be0349dc5 170 */
<> 134:ad3be0349dc5 171
<> 134:ad3be0349dc5 172 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
<> 134:ad3be0349dc5 173 * @{
<> 134:ad3be0349dc5 174 */
<> 134:ad3be0349dc5 175 #define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU
<> 134:ad3be0349dc5 176 #define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
<> 134:ad3be0349dc5 177 #define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
<> 134:ad3be0349dc5 178 #if defined(USART8)
<> 134:ad3be0349dc5 179 #define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN
<> 134:ad3be0349dc5 180 #endif /*USART8*/
<> 134:ad3be0349dc5 181 #if defined(USART7)
<> 134:ad3be0349dc5 182 #define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN
<> 134:ad3be0349dc5 183 #endif /*USART7*/
<> 134:ad3be0349dc5 184 #if defined(USART6)
<> 134:ad3be0349dc5 185 #define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN
<> 134:ad3be0349dc5 186 #endif /*USART6*/
<> 134:ad3be0349dc5 187 #define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
<> 134:ad3be0349dc5 188 #define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
<> 134:ad3be0349dc5 189 #define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN
<> 134:ad3be0349dc5 190 #if defined(TIM15)
<> 134:ad3be0349dc5 191 #define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
<> 134:ad3be0349dc5 192 #endif /*TIM15*/
<> 134:ad3be0349dc5 193 #define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
<> 134:ad3be0349dc5 194 #define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
<> 134:ad3be0349dc5 195 #define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN
<> 134:ad3be0349dc5 196 /**
<> 134:ad3be0349dc5 197 * @}
<> 134:ad3be0349dc5 198 */
<> 134:ad3be0349dc5 199
<> 134:ad3be0349dc5 200 /**
<> 134:ad3be0349dc5 201 * @}
<> 134:ad3be0349dc5 202 */
<> 134:ad3be0349dc5 203
<> 134:ad3be0349dc5 204 /* Exported macro ------------------------------------------------------------*/
<> 134:ad3be0349dc5 205 /* Exported functions --------------------------------------------------------*/
<> 134:ad3be0349dc5 206 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
<> 134:ad3be0349dc5 207 * @{
<> 134:ad3be0349dc5 208 */
<> 134:ad3be0349dc5 209
<> 134:ad3be0349dc5 210 /** @defgroup BUS_LL_EF_AHB1 AHB1
<> 134:ad3be0349dc5 211 * @{
<> 134:ad3be0349dc5 212 */
<> 134:ad3be0349dc5 213
<> 134:ad3be0349dc5 214 /**
<> 134:ad3be0349dc5 215 * @brief Enable AHB1 peripherals clock.
<> 134:ad3be0349dc5 216 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 217 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 218 * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 219 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 220 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 221 * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 222 * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 223 * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 224 * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 225 * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 226 * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 227 * AHBENR TSCEN LL_AHB1_GRP1_EnableClock
<> 134:ad3be0349dc5 228 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 229 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 134:ad3be0349dc5 230 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 134:ad3be0349dc5 231 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
<> 134:ad3be0349dc5 232 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 134:ad3be0349dc5 233 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 134:ad3be0349dc5 234 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 134:ad3be0349dc5 235 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 134:ad3be0349dc5 236 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 134:ad3be0349dc5 237 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
<> 134:ad3be0349dc5 238 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 134:ad3be0349dc5 239 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<> 134:ad3be0349dc5 240 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
<> 134:ad3be0349dc5 241 *
<> 134:ad3be0349dc5 242 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 243 * @retval None
<> 134:ad3be0349dc5 244 */
<> 134:ad3be0349dc5 245 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
<> 134:ad3be0349dc5 246 {
<> 134:ad3be0349dc5 247 __IO uint32_t tmpreg;
<> 134:ad3be0349dc5 248 SET_BIT(RCC->AHBENR, Periphs);
<> 134:ad3be0349dc5 249 /* Delay after an RCC peripheral clock enabling */
<> 134:ad3be0349dc5 250 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
<> 134:ad3be0349dc5 251 (void)tmpreg;
<> 134:ad3be0349dc5 252 }
<> 134:ad3be0349dc5 253
<> 134:ad3be0349dc5 254 /**
<> 134:ad3be0349dc5 255 * @brief Check if AHB1 peripheral clock is enabled or not
<> 134:ad3be0349dc5 256 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 257 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 258 * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 259 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 260 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 261 * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 262 * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 263 * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 264 * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 265 * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 266 * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 267 * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock
<> 134:ad3be0349dc5 268 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 269 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 134:ad3be0349dc5 270 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 134:ad3be0349dc5 271 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
<> 134:ad3be0349dc5 272 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 134:ad3be0349dc5 273 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 134:ad3be0349dc5 274 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 134:ad3be0349dc5 275 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 134:ad3be0349dc5 276 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 134:ad3be0349dc5 277 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
<> 134:ad3be0349dc5 278 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 134:ad3be0349dc5 279 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<> 134:ad3be0349dc5 280 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
<> 134:ad3be0349dc5 281 *
<> 134:ad3be0349dc5 282 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 283 * @retval State of Periphs (1 or 0).
<> 134:ad3be0349dc5 284 */
<> 134:ad3be0349dc5 285 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
<> 134:ad3be0349dc5 286 {
<> 134:ad3be0349dc5 287 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
<> 134:ad3be0349dc5 288 }
<> 134:ad3be0349dc5 289
<> 134:ad3be0349dc5 290 /**
<> 134:ad3be0349dc5 291 * @brief Disable AHB1 peripherals clock.
<> 134:ad3be0349dc5 292 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 293 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 294 * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 295 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 296 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 297 * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 298 * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 299 * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 300 * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 301 * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 302 * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 303 * AHBENR TSCEN LL_AHB1_GRP1_DisableClock
<> 134:ad3be0349dc5 304 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 305 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 134:ad3be0349dc5 306 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 134:ad3be0349dc5 307 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
<> 134:ad3be0349dc5 308 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 134:ad3be0349dc5 309 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 134:ad3be0349dc5 310 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 134:ad3be0349dc5 311 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 134:ad3be0349dc5 312 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 134:ad3be0349dc5 313 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
<> 134:ad3be0349dc5 314 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 134:ad3be0349dc5 315 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<> 134:ad3be0349dc5 316 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
<> 134:ad3be0349dc5 317 *
<> 134:ad3be0349dc5 318 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 319 * @retval None
<> 134:ad3be0349dc5 320 */
<> 134:ad3be0349dc5 321 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
<> 134:ad3be0349dc5 322 {
<> 134:ad3be0349dc5 323 CLEAR_BIT(RCC->AHBENR, Periphs);
<> 134:ad3be0349dc5 324 }
<> 134:ad3be0349dc5 325
<> 134:ad3be0349dc5 326 /**
<> 134:ad3be0349dc5 327 * @brief Force AHB1 peripherals reset.
<> 134:ad3be0349dc5 328 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 329 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 330 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 331 * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 332 * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 333 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 334 * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset
<> 134:ad3be0349dc5 335 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 336 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
<> 134:ad3be0349dc5 337 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 134:ad3be0349dc5 338 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 134:ad3be0349dc5 339 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 134:ad3be0349dc5 340 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
<> 134:ad3be0349dc5 341 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 134:ad3be0349dc5 342 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<> 134:ad3be0349dc5 343 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
<> 134:ad3be0349dc5 344 *
<> 134:ad3be0349dc5 345 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 346 * @retval None
<> 134:ad3be0349dc5 347 */
<> 134:ad3be0349dc5 348 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
<> 134:ad3be0349dc5 349 {
<> 134:ad3be0349dc5 350 SET_BIT(RCC->AHBRSTR, Periphs);
<> 134:ad3be0349dc5 351 }
<> 134:ad3be0349dc5 352
<> 134:ad3be0349dc5 353 /**
<> 134:ad3be0349dc5 354 * @brief Release AHB1 peripherals reset.
<> 134:ad3be0349dc5 355 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 356 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 357 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 358 * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 359 * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 360 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 361 * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset
<> 134:ad3be0349dc5 362 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 363 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
<> 134:ad3be0349dc5 364 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 134:ad3be0349dc5 365 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 134:ad3be0349dc5 366 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 134:ad3be0349dc5 367 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
<> 134:ad3be0349dc5 368 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 134:ad3be0349dc5 369 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<> 134:ad3be0349dc5 370 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
<> 134:ad3be0349dc5 371 *
<> 134:ad3be0349dc5 372 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 373 * @retval None
<> 134:ad3be0349dc5 374 */
<> 134:ad3be0349dc5 375 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
<> 134:ad3be0349dc5 376 {
<> 134:ad3be0349dc5 377 CLEAR_BIT(RCC->AHBRSTR, Periphs);
<> 134:ad3be0349dc5 378 }
<> 134:ad3be0349dc5 379
<> 134:ad3be0349dc5 380 /**
<> 134:ad3be0349dc5 381 * @}
<> 134:ad3be0349dc5 382 */
<> 134:ad3be0349dc5 383
<> 134:ad3be0349dc5 384 /** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1
<> 134:ad3be0349dc5 385 * @{
<> 134:ad3be0349dc5 386 */
<> 134:ad3be0349dc5 387
<> 134:ad3be0349dc5 388 /**
<> 134:ad3be0349dc5 389 * @brief Enable APB1 peripherals clock (available in register 1).
<> 134:ad3be0349dc5 390 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 391 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 392 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 393 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 394 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 395 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 396 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 397 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 398 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 399 * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 400 * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 401 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 402 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 403 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 404 * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 405 * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 406 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 407 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
<> 134:ad3be0349dc5 408 * APB1ENR CECEN LL_APB1_GRP1_EnableClock
<> 134:ad3be0349dc5 409 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 410 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
<> 134:ad3be0349dc5 411 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 134:ad3be0349dc5 412 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
<> 134:ad3be0349dc5 413 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
<> 134:ad3be0349dc5 414 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<> 134:ad3be0349dc5 415 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 134:ad3be0349dc5 416 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
<> 134:ad3be0349dc5 417 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
<> 134:ad3be0349dc5 418 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
<> 134:ad3be0349dc5 419 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
<> 134:ad3be0349dc5 420 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
<> 134:ad3be0349dc5 421 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 134:ad3be0349dc5 422 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
<> 134:ad3be0349dc5 423 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
<> 134:ad3be0349dc5 424 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
<> 134:ad3be0349dc5 425 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
<> 134:ad3be0349dc5 426 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 134:ad3be0349dc5 427 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
<> 134:ad3be0349dc5 428 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<> 134:ad3be0349dc5 429 *
<> 134:ad3be0349dc5 430 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 431 * @retval None
<> 134:ad3be0349dc5 432 */
<> 134:ad3be0349dc5 433 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
<> 134:ad3be0349dc5 434 {
<> 134:ad3be0349dc5 435 __IO uint32_t tmpreg;
<> 134:ad3be0349dc5 436 SET_BIT(RCC->APB1ENR, Periphs);
<> 134:ad3be0349dc5 437 /* Delay after an RCC peripheral clock enabling */
<> 134:ad3be0349dc5 438 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
<> 134:ad3be0349dc5 439 (void)tmpreg;
<> 134:ad3be0349dc5 440 }
<> 134:ad3be0349dc5 441
<> 134:ad3be0349dc5 442 /**
<> 134:ad3be0349dc5 443 * @brief Check if APB1 peripheral clock is enabled or not (available in register 1).
<> 134:ad3be0349dc5 444 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 445 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 446 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 447 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 448 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 449 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 450 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 451 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 452 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 453 * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 454 * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 455 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 456 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 457 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 458 * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 459 * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 460 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 461 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
<> 134:ad3be0349dc5 462 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock
<> 134:ad3be0349dc5 463 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 464 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
<> 134:ad3be0349dc5 465 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 134:ad3be0349dc5 466 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
<> 134:ad3be0349dc5 467 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
<> 134:ad3be0349dc5 468 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<> 134:ad3be0349dc5 469 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 134:ad3be0349dc5 470 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
<> 134:ad3be0349dc5 471 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
<> 134:ad3be0349dc5 472 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
<> 134:ad3be0349dc5 473 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
<> 134:ad3be0349dc5 474 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
<> 134:ad3be0349dc5 475 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 134:ad3be0349dc5 476 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
<> 134:ad3be0349dc5 477 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
<> 134:ad3be0349dc5 478 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
<> 134:ad3be0349dc5 479 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
<> 134:ad3be0349dc5 480 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 134:ad3be0349dc5 481 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
<> 134:ad3be0349dc5 482 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<> 134:ad3be0349dc5 483 *
<> 134:ad3be0349dc5 484 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 485 * @retval State of Periphs (1 or 0).
<> 134:ad3be0349dc5 486 */
<> 134:ad3be0349dc5 487 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
<> 134:ad3be0349dc5 488 {
<> 134:ad3be0349dc5 489 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
<> 134:ad3be0349dc5 490 }
<> 134:ad3be0349dc5 491
<> 134:ad3be0349dc5 492 /**
<> 134:ad3be0349dc5 493 * @brief Disable APB1 peripherals clock (available in register 1).
<> 134:ad3be0349dc5 494 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 495 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 496 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 497 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 498 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 499 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 500 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 501 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 502 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 503 * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 504 * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 505 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 506 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 507 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 508 * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 509 * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 510 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 511 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
<> 134:ad3be0349dc5 512 * APB1ENR CECEN LL_APB1_GRP1_DisableClock
<> 134:ad3be0349dc5 513 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 514 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
<> 134:ad3be0349dc5 515 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 134:ad3be0349dc5 516 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
<> 134:ad3be0349dc5 517 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
<> 134:ad3be0349dc5 518 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<> 134:ad3be0349dc5 519 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 134:ad3be0349dc5 520 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
<> 134:ad3be0349dc5 521 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
<> 134:ad3be0349dc5 522 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
<> 134:ad3be0349dc5 523 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
<> 134:ad3be0349dc5 524 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
<> 134:ad3be0349dc5 525 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 134:ad3be0349dc5 526 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
<> 134:ad3be0349dc5 527 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
<> 134:ad3be0349dc5 528 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
<> 134:ad3be0349dc5 529 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
<> 134:ad3be0349dc5 530 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 134:ad3be0349dc5 531 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
<> 134:ad3be0349dc5 532 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<> 134:ad3be0349dc5 533 *
<> 134:ad3be0349dc5 534 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 535 * @retval None
<> 134:ad3be0349dc5 536 */
<> 134:ad3be0349dc5 537 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
<> 134:ad3be0349dc5 538 {
<> 134:ad3be0349dc5 539 CLEAR_BIT(RCC->APB1ENR, Periphs);
<> 134:ad3be0349dc5 540 }
<> 134:ad3be0349dc5 541
<> 134:ad3be0349dc5 542 /**
<> 134:ad3be0349dc5 543 * @brief Force APB1 peripherals reset (available in register 1).
<> 134:ad3be0349dc5 544 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 545 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 546 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 547 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 548 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 549 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 550 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 551 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 552 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 553 * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 554 * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 555 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 556 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 557 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 558 * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 559 * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 560 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 561 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
<> 134:ad3be0349dc5 562 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset
<> 134:ad3be0349dc5 563 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 564 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
<> 134:ad3be0349dc5 565 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
<> 134:ad3be0349dc5 566 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 134:ad3be0349dc5 567 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
<> 134:ad3be0349dc5 568 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
<> 134:ad3be0349dc5 569 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<> 134:ad3be0349dc5 570 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 134:ad3be0349dc5 571 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
<> 134:ad3be0349dc5 572 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
<> 134:ad3be0349dc5 573 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
<> 134:ad3be0349dc5 574 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
<> 134:ad3be0349dc5 575 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
<> 134:ad3be0349dc5 576 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 134:ad3be0349dc5 577 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
<> 134:ad3be0349dc5 578 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
<> 134:ad3be0349dc5 579 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
<> 134:ad3be0349dc5 580 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
<> 134:ad3be0349dc5 581 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 134:ad3be0349dc5 582 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
<> 134:ad3be0349dc5 583 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<> 134:ad3be0349dc5 584 *
<> 134:ad3be0349dc5 585 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 586 * @retval None
<> 134:ad3be0349dc5 587 */
<> 134:ad3be0349dc5 588 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
<> 134:ad3be0349dc5 589 {
<> 134:ad3be0349dc5 590 SET_BIT(RCC->APB1RSTR, Periphs);
<> 134:ad3be0349dc5 591 }
<> 134:ad3be0349dc5 592
<> 134:ad3be0349dc5 593 /**
<> 134:ad3be0349dc5 594 * @brief Release APB1 peripherals reset (available in register 1).
<> 134:ad3be0349dc5 595 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 596 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 597 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 598 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 599 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 600 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 601 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 602 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 603 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 604 * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 605 * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 606 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 607 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 608 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 609 * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 610 * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 611 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 612 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
<> 134:ad3be0349dc5 613 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset
<> 134:ad3be0349dc5 614 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 615 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
<> 134:ad3be0349dc5 616 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
<> 134:ad3be0349dc5 617 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 134:ad3be0349dc5 618 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
<> 134:ad3be0349dc5 619 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
<> 134:ad3be0349dc5 620 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<> 134:ad3be0349dc5 621 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 134:ad3be0349dc5 622 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
<> 134:ad3be0349dc5 623 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
<> 134:ad3be0349dc5 624 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
<> 134:ad3be0349dc5 625 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
<> 134:ad3be0349dc5 626 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
<> 134:ad3be0349dc5 627 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 134:ad3be0349dc5 628 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
<> 134:ad3be0349dc5 629 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
<> 134:ad3be0349dc5 630 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
<> 134:ad3be0349dc5 631 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
<> 134:ad3be0349dc5 632 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 134:ad3be0349dc5 633 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
<> 134:ad3be0349dc5 634 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<> 134:ad3be0349dc5 635 *
<> 134:ad3be0349dc5 636 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 637 * @retval None
<> 134:ad3be0349dc5 638 */
<> 134:ad3be0349dc5 639 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
<> 134:ad3be0349dc5 640 {
<> 134:ad3be0349dc5 641 CLEAR_BIT(RCC->APB1RSTR, Periphs);
<> 134:ad3be0349dc5 642 }
<> 134:ad3be0349dc5 643
<> 134:ad3be0349dc5 644 /**
<> 134:ad3be0349dc5 645 * @}
<> 134:ad3be0349dc5 646 */
<> 134:ad3be0349dc5 647
<> 134:ad3be0349dc5 648 /** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2
<> 134:ad3be0349dc5 649 * @{
<> 134:ad3be0349dc5 650 */
<> 134:ad3be0349dc5 651
<> 134:ad3be0349dc5 652 /**
<> 134:ad3be0349dc5 653 * @brief Enable APB1 peripherals clock (available in register 2).
<> 134:ad3be0349dc5 654 * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n
<> 134:ad3be0349dc5 655 * APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n
<> 134:ad3be0349dc5 656 * APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n
<> 134:ad3be0349dc5 657 * APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n
<> 134:ad3be0349dc5 658 * APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n
<> 134:ad3be0349dc5 659 * APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n
<> 134:ad3be0349dc5 660 * APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n
<> 134:ad3be0349dc5 661 * APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n
<> 134:ad3be0349dc5 662 * APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n
<> 134:ad3be0349dc5 663 * APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n
<> 134:ad3be0349dc5 664 * APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n
<> 134:ad3be0349dc5 665 * APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock
<> 134:ad3be0349dc5 666 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 667 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
<> 134:ad3be0349dc5 668 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
<> 134:ad3be0349dc5 669 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
<> 134:ad3be0349dc5 670 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
<> 134:ad3be0349dc5 671 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
<> 134:ad3be0349dc5 672 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
<> 134:ad3be0349dc5 673 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
<> 134:ad3be0349dc5 674 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
<> 134:ad3be0349dc5 675 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
<> 134:ad3be0349dc5 676 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
<> 134:ad3be0349dc5 677 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
<> 134:ad3be0349dc5 678 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
<> 134:ad3be0349dc5 679 *
<> 134:ad3be0349dc5 680 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 681 * @retval None
<> 134:ad3be0349dc5 682 */
<> 134:ad3be0349dc5 683 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
<> 134:ad3be0349dc5 684 {
<> 134:ad3be0349dc5 685 __IO uint32_t tmpreg;
<> 134:ad3be0349dc5 686 SET_BIT(RCC->APB2ENR, Periphs);
<> 134:ad3be0349dc5 687 /* Delay after an RCC peripheral clock enabling */
<> 134:ad3be0349dc5 688 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
<> 134:ad3be0349dc5 689 (void)tmpreg;
<> 134:ad3be0349dc5 690 }
<> 134:ad3be0349dc5 691
<> 134:ad3be0349dc5 692 /**
<> 134:ad3be0349dc5 693 * @brief Check if APB1 peripheral clock is enabled or not (available in register 2).
<> 134:ad3be0349dc5 694 * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n
<> 134:ad3be0349dc5 695 * APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n
<> 134:ad3be0349dc5 696 * APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n
<> 134:ad3be0349dc5 697 * APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n
<> 134:ad3be0349dc5 698 * APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n
<> 134:ad3be0349dc5 699 * APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n
<> 134:ad3be0349dc5 700 * APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n
<> 134:ad3be0349dc5 701 * APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n
<> 134:ad3be0349dc5 702 * APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n
<> 134:ad3be0349dc5 703 * APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n
<> 134:ad3be0349dc5 704 * APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n
<> 134:ad3be0349dc5 705 * APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock
<> 134:ad3be0349dc5 706 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 707 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
<> 134:ad3be0349dc5 708 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
<> 134:ad3be0349dc5 709 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
<> 134:ad3be0349dc5 710 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
<> 134:ad3be0349dc5 711 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
<> 134:ad3be0349dc5 712 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
<> 134:ad3be0349dc5 713 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
<> 134:ad3be0349dc5 714 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
<> 134:ad3be0349dc5 715 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
<> 134:ad3be0349dc5 716 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
<> 134:ad3be0349dc5 717 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
<> 134:ad3be0349dc5 718 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
<> 134:ad3be0349dc5 719 *
<> 134:ad3be0349dc5 720 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 721 * @retval State of Periphs (1 or 0).
<> 134:ad3be0349dc5 722 */
<> 134:ad3be0349dc5 723 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
<> 134:ad3be0349dc5 724 {
<> 134:ad3be0349dc5 725 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
<> 134:ad3be0349dc5 726 }
<> 134:ad3be0349dc5 727
<> 134:ad3be0349dc5 728 /**
<> 134:ad3be0349dc5 729 * @brief Disable APB1 peripherals clock (available in register 2).
<> 134:ad3be0349dc5 730 * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n
<> 134:ad3be0349dc5 731 * APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n
<> 134:ad3be0349dc5 732 * APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n
<> 134:ad3be0349dc5 733 * APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n
<> 134:ad3be0349dc5 734 * APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n
<> 134:ad3be0349dc5 735 * APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n
<> 134:ad3be0349dc5 736 * APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n
<> 134:ad3be0349dc5 737 * APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n
<> 134:ad3be0349dc5 738 * APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n
<> 134:ad3be0349dc5 739 * APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n
<> 134:ad3be0349dc5 740 * APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n
<> 134:ad3be0349dc5 741 * APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock
<> 134:ad3be0349dc5 742 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 743 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
<> 134:ad3be0349dc5 744 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
<> 134:ad3be0349dc5 745 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
<> 134:ad3be0349dc5 746 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
<> 134:ad3be0349dc5 747 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
<> 134:ad3be0349dc5 748 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
<> 134:ad3be0349dc5 749 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
<> 134:ad3be0349dc5 750 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
<> 134:ad3be0349dc5 751 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
<> 134:ad3be0349dc5 752 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
<> 134:ad3be0349dc5 753 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
<> 134:ad3be0349dc5 754 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
<> 134:ad3be0349dc5 755 *
<> 134:ad3be0349dc5 756 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 757 * @retval None
<> 134:ad3be0349dc5 758 */
<> 134:ad3be0349dc5 759 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
<> 134:ad3be0349dc5 760 {
<> 134:ad3be0349dc5 761 CLEAR_BIT(RCC->APB2ENR, Periphs);
<> 134:ad3be0349dc5 762 }
<> 134:ad3be0349dc5 763
<> 134:ad3be0349dc5 764 /**
<> 134:ad3be0349dc5 765 * @brief Force APB1 peripherals reset (available in register 2).
<> 134:ad3be0349dc5 766 * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n
<> 134:ad3be0349dc5 767 * APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n
<> 134:ad3be0349dc5 768 * APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n
<> 134:ad3be0349dc5 769 * APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n
<> 134:ad3be0349dc5 770 * APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n
<> 134:ad3be0349dc5 771 * APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n
<> 134:ad3be0349dc5 772 * APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n
<> 134:ad3be0349dc5 773 * APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n
<> 134:ad3be0349dc5 774 * APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n
<> 134:ad3be0349dc5 775 * APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n
<> 134:ad3be0349dc5 776 * APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n
<> 134:ad3be0349dc5 777 * APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset
<> 134:ad3be0349dc5 778 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 779 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
<> 134:ad3be0349dc5 780 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
<> 134:ad3be0349dc5 781 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
<> 134:ad3be0349dc5 782 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
<> 134:ad3be0349dc5 783 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
<> 134:ad3be0349dc5 784 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
<> 134:ad3be0349dc5 785 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
<> 134:ad3be0349dc5 786 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
<> 134:ad3be0349dc5 787 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
<> 134:ad3be0349dc5 788 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
<> 134:ad3be0349dc5 789 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
<> 134:ad3be0349dc5 790 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
<> 134:ad3be0349dc5 791 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
<> 134:ad3be0349dc5 792 *
<> 134:ad3be0349dc5 793 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 794 * @retval None
<> 134:ad3be0349dc5 795 */
<> 134:ad3be0349dc5 796 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
<> 134:ad3be0349dc5 797 {
<> 134:ad3be0349dc5 798 SET_BIT(RCC->APB2RSTR, Periphs);
<> 134:ad3be0349dc5 799 }
<> 134:ad3be0349dc5 800
<> 134:ad3be0349dc5 801 /**
<> 134:ad3be0349dc5 802 * @brief Release APB1 peripherals reset (available in register 2).
<> 134:ad3be0349dc5 803 * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n
<> 134:ad3be0349dc5 804 * APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n
<> 134:ad3be0349dc5 805 * APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n
<> 134:ad3be0349dc5 806 * APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n
<> 134:ad3be0349dc5 807 * APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n
<> 134:ad3be0349dc5 808 * APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n
<> 134:ad3be0349dc5 809 * APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n
<> 134:ad3be0349dc5 810 * APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n
<> 134:ad3be0349dc5 811 * APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n
<> 134:ad3be0349dc5 812 * APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n
<> 134:ad3be0349dc5 813 * APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n
<> 134:ad3be0349dc5 814 * APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset
<> 134:ad3be0349dc5 815 * @param Periphs This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 816 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
<> 134:ad3be0349dc5 817 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
<> 134:ad3be0349dc5 818 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
<> 134:ad3be0349dc5 819 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
<> 134:ad3be0349dc5 820 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
<> 134:ad3be0349dc5 821 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
<> 134:ad3be0349dc5 822 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
<> 134:ad3be0349dc5 823 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
<> 134:ad3be0349dc5 824 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
<> 134:ad3be0349dc5 825 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
<> 134:ad3be0349dc5 826 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
<> 134:ad3be0349dc5 827 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
<> 134:ad3be0349dc5 828 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
<> 134:ad3be0349dc5 829 *
<> 134:ad3be0349dc5 830 * (*) value not defined in all devices.
<> 134:ad3be0349dc5 831 * @retval None
<> 134:ad3be0349dc5 832 */
<> 134:ad3be0349dc5 833 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
<> 134:ad3be0349dc5 834 {
<> 134:ad3be0349dc5 835 CLEAR_BIT(RCC->APB2RSTR, Periphs);
<> 134:ad3be0349dc5 836 }
<> 134:ad3be0349dc5 837
<> 134:ad3be0349dc5 838 /**
<> 134:ad3be0349dc5 839 * @}
<> 134:ad3be0349dc5 840 */
<> 134:ad3be0349dc5 841
<> 134:ad3be0349dc5 842
<> 134:ad3be0349dc5 843 /**
<> 134:ad3be0349dc5 844 * @}
<> 134:ad3be0349dc5 845 */
<> 134:ad3be0349dc5 846
<> 134:ad3be0349dc5 847 /**
<> 134:ad3be0349dc5 848 * @}
<> 134:ad3be0349dc5 849 */
<> 134:ad3be0349dc5 850
<> 134:ad3be0349dc5 851 #endif /* defined(RCC) */
<> 134:ad3be0349dc5 852
<> 134:ad3be0349dc5 853 /**
<> 134:ad3be0349dc5 854 * @}
<> 134:ad3be0349dc5 855 */
<> 134:ad3be0349dc5 856
<> 134:ad3be0349dc5 857 #ifdef __cplusplus
<> 134:ad3be0349dc5 858 }
<> 134:ad3be0349dc5 859 #endif
<> 134:ad3be0349dc5 860
<> 134:ad3be0349dc5 861 #endif /* __STM32F0xx_LL_BUS_H */
<> 134:ad3be0349dc5 862
<> 134:ad3be0349dc5 863 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/