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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Parent:: 134:ad3be0349dc5

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	85:024bf7f99721	1	/**
bogdanm	85:024bf7f99721	2	******************************************************************************
bogdanm	85:024bf7f99721	3	* @file stm32f0xx_hal_tim.h
bogdanm	85:024bf7f99721	4	* @author MCD Application Team
<>	134:ad3be0349dc5	5	* @version V1.5.0
<>	134:ad3be0349dc5	6	* @date 04-November-2016
bogdanm	85:024bf7f99721	7	* @brief Header file of TIM HAL module.
bogdanm	85:024bf7f99721	8	******************************************************************************
bogdanm	85:024bf7f99721	9	* @attention
bogdanm	85:024bf7f99721	10	*
Kojto	122:f9eeca106725	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	85:024bf7f99721	12	*
bogdanm	85:024bf7f99721	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	85:024bf7f99721	14	* are permitted provided that the following conditions are met:
bogdanm	85:024bf7f99721	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	85:024bf7f99721	16	* this list of conditions and the following disclaimer.
bogdanm	85:024bf7f99721	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	85:024bf7f99721	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	85:024bf7f99721	19	* and/or other materials provided with the distribution.
bogdanm	85:024bf7f99721	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	85:024bf7f99721	21	* may be used to endorse or promote products derived from this software
bogdanm	85:024bf7f99721	22	* without specific prior written permission.
bogdanm	85:024bf7f99721	23	*
bogdanm	85:024bf7f99721	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	85:024bf7f99721	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	85:024bf7f99721	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	85:024bf7f99721	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	85:024bf7f99721	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	85:024bf7f99721	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	85:024bf7f99721	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	85:024bf7f99721	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	85:024bf7f99721	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	85:024bf7f99721	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	85:024bf7f99721	34	*
bogdanm	85:024bf7f99721	35	******************************************************************************
Kojto	108:34e6b704fe68	36	*/
bogdanm	85:024bf7f99721	37
bogdanm	85:024bf7f99721	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	85:024bf7f99721	39	#ifndef __STM32F0xx_HAL_TIM_H
bogdanm	85:024bf7f99721	40	#define __STM32F0xx_HAL_TIM_H
bogdanm	85:024bf7f99721	41
bogdanm	85:024bf7f99721	42	#ifdef __cplusplus
bogdanm	85:024bf7f99721	43	extern "C" {
bogdanm	85:024bf7f99721	44	#endif
bogdanm	85:024bf7f99721	45
bogdanm	85:024bf7f99721	46	/* Includes ------------------------------------------------------------------*/
bogdanm	85:024bf7f99721	47	#include "stm32f0xx_hal_def.h"
bogdanm	85:024bf7f99721	48
bogdanm	85:024bf7f99721	49	/** @addtogroup STM32F0xx_HAL_Driver
bogdanm	85:024bf7f99721	50	* @{
bogdanm	85:024bf7f99721	51	*/
bogdanm	85:024bf7f99721	52
bogdanm	85:024bf7f99721	53	/** @addtogroup TIM
bogdanm	85:024bf7f99721	54	* @{
Kojto	108:34e6b704fe68	55	*/
bogdanm	85:024bf7f99721	56
Kojto	108:34e6b704fe68	57	/* Exported types ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	58	/** @defgroup TIM_Exported_Types TIM Exported Types
bogdanm	92:4fc01daae5a5	59	* @{
bogdanm	92:4fc01daae5a5	60	*/
Kojto	108:34e6b704fe68	61	/**
Kojto	108:34e6b704fe68	62	* @brief TIM Time base Configuration Structure definition
bogdanm	85:024bf7f99721	63	*/
bogdanm	85:024bf7f99721	64	typedef struct
bogdanm	85:024bf7f99721	65	{
bogdanm	85:024bf7f99721	66	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm	85:024bf7f99721	67	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	85:024bf7f99721	68
bogdanm	85:024bf7f99721	69	uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm	85:024bf7f99721	70	This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm	85:024bf7f99721	71
bogdanm	85:024bf7f99721	72	uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm	85:024bf7f99721	73	Auto-Reload Register at the next update event.
Kojto	108:34e6b704fe68	74	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm	85:024bf7f99721	75
bogdanm	85:024bf7f99721	76	uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm	85:024bf7f99721	77	This parameter can be a value of @ref TIM_ClockDivision */
bogdanm	85:024bf7f99721	78
bogdanm	85:024bf7f99721	79	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm	85:024bf7f99721	80	reaches zero, an update event is generated and counting restarts
bogdanm	85:024bf7f99721	81	from the RCR value (N).
bogdanm	85:024bf7f99721	82	This means in PWM mode that (N+1) corresponds to:
bogdanm	85:024bf7f99721	83	- the number of PWM periods in edge-aligned mode
bogdanm	85:024bf7f99721	84	- the number of half PWM period in center-aligned mode
Kojto	108:34e6b704fe68	85	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
bogdanm	85:024bf7f99721	86	@note This parameter is valid only for TIM1 and TIM8. */
<>	134:ad3be0349dc5	87
<>	134:ad3be0349dc5	88	uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
<>	134:ad3be0349dc5	89	This parameter can be a value of @ref TIM_AutoReloadPreload */
bogdanm	85:024bf7f99721	90	} TIM_Base_InitTypeDef;
bogdanm	85:024bf7f99721	91
Kojto	108:34e6b704fe68	92	/**
Kojto	108:34e6b704fe68	93	* @brief TIM Output Compare Configuration Structure definition
bogdanm	85:024bf7f99721	94	*/
bogdanm	85:024bf7f99721	95	typedef struct
Kojto	108:34e6b704fe68	96	{
bogdanm	85:024bf7f99721	97	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	85:024bf7f99721	98	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	85:024bf7f99721	99
Kojto	108:34e6b704fe68	100	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
Kojto	108:34e6b704fe68	101	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	85:024bf7f99721	102
bogdanm	85:024bf7f99721	103	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	85:024bf7f99721	104	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	85:024bf7f99721	105
bogdanm	85:024bf7f99721	106	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	85:024bf7f99721	107	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	85:024bf7f99721	108	@note This parameter is valid only for TIM1 and TIM8. */
Kojto	108:34e6b704fe68	109
bogdanm	85:024bf7f99721	110	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm	85:024bf7f99721	111	This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm	85:024bf7f99721	112	@note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm	85:024bf7f99721	113
bogdanm	85:024bf7f99721	114
bogdanm	85:024bf7f99721	115	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	85:024bf7f99721	116	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	85:024bf7f99721	117	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	85:024bf7f99721	118
bogdanm	85:024bf7f99721	119	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	85:024bf7f99721	120	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	85:024bf7f99721	121	@note This parameter is valid only for TIM1 and TIM8. */
Kojto	108:34e6b704fe68	122	} TIM_OC_InitTypeDef;
bogdanm	85:024bf7f99721	123
Kojto	108:34e6b704fe68	124	/**
Kojto	108:34e6b704fe68	125	* @brief TIM One Pulse Mode Configuration Structure definition
bogdanm	85:024bf7f99721	126	*/
bogdanm	85:024bf7f99721	127	typedef struct
Kojto	108:34e6b704fe68	128	{
bogdanm	85:024bf7f99721	129	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	85:024bf7f99721	130	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	85:024bf7f99721	131
Kojto	108:34e6b704fe68	132	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
Kojto	108:34e6b704fe68	133	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	85:024bf7f99721	134
bogdanm	85:024bf7f99721	135	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	85:024bf7f99721	136	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	85:024bf7f99721	137
bogdanm	85:024bf7f99721	138	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	85:024bf7f99721	139	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	85:024bf7f99721	140	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	85:024bf7f99721	141
bogdanm	85:024bf7f99721	142	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	85:024bf7f99721	143	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	85:024bf7f99721	144	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	85:024bf7f99721	145
bogdanm	85:024bf7f99721	146	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	85:024bf7f99721	147	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	85:024bf7f99721	148	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	85:024bf7f99721	149
bogdanm	85:024bf7f99721	150	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	85:024bf7f99721	151	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	85:024bf7f99721	152
bogdanm	85:024bf7f99721	153	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	85:024bf7f99721	154	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	85:024bf7f99721	155
bogdanm	85:024bf7f99721	156	uint32_t ICFilter; /*!< Specifies the input capture filter.
Kojto	108:34e6b704fe68	157	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
Kojto	108:34e6b704fe68	158	} TIM_OnePulse_InitTypeDef;
bogdanm	85:024bf7f99721	159
bogdanm	85:024bf7f99721	160
Kojto	108:34e6b704fe68	161	/**
Kojto	108:34e6b704fe68	162	* @brief TIM Input Capture Configuration Structure definition
bogdanm	85:024bf7f99721	163	*/
bogdanm	85:024bf7f99721	164	typedef struct
Kojto	108:34e6b704fe68	165	{
bogdanm	85:024bf7f99721	166	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	85:024bf7f99721	167	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	85:024bf7f99721	168
bogdanm	85:024bf7f99721	169	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	85:024bf7f99721	170	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	85:024bf7f99721	171
bogdanm	85:024bf7f99721	172	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	85:024bf7f99721	173	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	85:024bf7f99721	174
bogdanm	85:024bf7f99721	175	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	85:024bf7f99721	176	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	85:024bf7f99721	177	} TIM_IC_InitTypeDef;
bogdanm	85:024bf7f99721	178
Kojto	108:34e6b704fe68	179	/**
Kojto	108:34e6b704fe68	180	* @brief TIM Encoder Configuration Structure definition
bogdanm	85:024bf7f99721	181	*/
bogdanm	85:024bf7f99721	182	typedef struct
bogdanm	85:024bf7f99721	183	{
bogdanm	85:024bf7f99721	184	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm	85:024bf7f99721	185	This parameter can be a value of @ref TIM_Encoder_Mode */
Kojto	108:34e6b704fe68	186
bogdanm	85:024bf7f99721	187	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	85:024bf7f99721	188	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	85:024bf7f99721	189
bogdanm	85:024bf7f99721	190	uint32_t IC1Selection; /*!< Specifies the input.
bogdanm	85:024bf7f99721	191	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	85:024bf7f99721	192
bogdanm	85:024bf7f99721	193	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	85:024bf7f99721	194	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	85:024bf7f99721	195
bogdanm	85:024bf7f99721	196	uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm	85:024bf7f99721	197	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
Kojto	108:34e6b704fe68	198
bogdanm	85:024bf7f99721	199	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	85:024bf7f99721	200	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	85:024bf7f99721	201
bogdanm	85:024bf7f99721	202	uint32_t IC2Selection; /*!< Specifies the input.
bogdanm	85:024bf7f99721	203	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	85:024bf7f99721	204
bogdanm	85:024bf7f99721	205	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	85:024bf7f99721	206	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	85:024bf7f99721	207
bogdanm	85:024bf7f99721	208	uint32_t IC2Filter; /*!< Specifies the input capture filter.
Kojto	108:34e6b704fe68	209	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	85:024bf7f99721	210	} TIM_Encoder_InitTypeDef;
bogdanm	85:024bf7f99721	211
bogdanm	85:024bf7f99721	212
Kojto	108:34e6b704fe68	213	/**
Kojto	108:34e6b704fe68	214	* @brief TIM Clock Configuration Handle Structure definition
bogdanm	85:024bf7f99721	215	*/
bogdanm	85:024bf7f99721	216	typedef struct
bogdanm	85:024bf7f99721	217	{
bogdanm	85:024bf7f99721	218	uint32_t ClockSource; /*!< TIM clock sources
Kojto	108:34e6b704fe68	219	This parameter can be a value of @ref TIM_Clock_Source */
bogdanm	85:024bf7f99721	220	uint32_t ClockPolarity; /*!< TIM clock polarity
bogdanm	85:024bf7f99721	221	This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm	85:024bf7f99721	222	uint32_t ClockPrescaler; /*!< TIM clock prescaler
bogdanm	85:024bf7f99721	223	This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm	85:024bf7f99721	224	uint32_t ClockFilter; /*!< TIM clock filter
Kojto	108:34e6b704fe68	225	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	85:024bf7f99721	226	}TIM_ClockConfigTypeDef;
bogdanm	85:024bf7f99721	227
Kojto	108:34e6b704fe68	228	/**
Kojto	108:34e6b704fe68	229	* @brief TIM Clear Input Configuration Handle Structure definition
bogdanm	85:024bf7f99721	230	*/
bogdanm	85:024bf7f99721	231	typedef struct
Kojto	108:34e6b704fe68	232	{
bogdanm	85:024bf7f99721	233	uint32_t ClearInputState; /*!< TIM clear Input state
Kojto	108:34e6b704fe68	234	This parameter can be ENABLE or DISABLE */
bogdanm	85:024bf7f99721	235	uint32_t ClearInputSource; /*!< TIM clear Input sources
Kojto	122:f9eeca106725	236	This parameter can be a value of @ref TIMEx_Clock_Clear_Input_Source */
bogdanm	85:024bf7f99721	237	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
bogdanm	85:024bf7f99721	238	This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm	85:024bf7f99721	239	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
bogdanm	85:024bf7f99721	240	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm	85:024bf7f99721	241	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
Kojto	108:34e6b704fe68	242	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	85:024bf7f99721	243	}TIM_ClearInputConfigTypeDef;
bogdanm	85:024bf7f99721	244
Kojto	108:34e6b704fe68	245	/**
Kojto	108:34e6b704fe68	246	* @brief TIM Slave configuration Structure definition
bogdanm	85:024bf7f99721	247	*/
bogdanm	85:024bf7f99721	248	typedef struct {
bogdanm	85:024bf7f99721	249	uint32_t SlaveMode; /*!< Slave mode selection
Kojto	108:34e6b704fe68	250	This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm	85:024bf7f99721	251	uint32_t InputTrigger; /*!< Input Trigger source
bogdanm	85:024bf7f99721	252	This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm	85:024bf7f99721	253	uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm	85:024bf7f99721	254	This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm	85:024bf7f99721	255	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm	85:024bf7f99721	256	This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm	85:024bf7f99721	257	uint32_t TriggerFilter; /*!< Input trigger filter
Kojto	108:34e6b704fe68	258	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	85:024bf7f99721	259
bogdanm	85:024bf7f99721	260	}TIM_SlaveConfigTypeDef;
bogdanm	85:024bf7f99721	261
Kojto	108:34e6b704fe68	262	/**
Kojto	108:34e6b704fe68	263	* @brief HAL State structures definition
bogdanm	85:024bf7f99721	264	*/
bogdanm	85:024bf7f99721	265	typedef enum
bogdanm	85:024bf7f99721	266	{
<>	134:ad3be0349dc5	267	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
<>	134:ad3be0349dc5	268	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
<>	134:ad3be0349dc5	269	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
<>	134:ad3be0349dc5	270	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
<>	134:ad3be0349dc5	271	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
bogdanm	85:024bf7f99721	272	}HAL_TIM_StateTypeDef;
bogdanm	85:024bf7f99721	273
Kojto	108:34e6b704fe68	274	/**
Kojto	108:34e6b704fe68	275	* @brief HAL Active channel structures definition
bogdanm	85:024bf7f99721	276	*/
bogdanm	85:024bf7f99721	277	typedef enum
bogdanm	85:024bf7f99721	278	{
<>	134:ad3be0349dc5	279	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
<>	134:ad3be0349dc5	280	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
<>	134:ad3be0349dc5	281	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
<>	134:ad3be0349dc5	282	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
<>	134:ad3be0349dc5	283	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
bogdanm	85:024bf7f99721	284	}HAL_TIM_ActiveChannel;
bogdanm	85:024bf7f99721	285
Kojto	108:34e6b704fe68	286	/**
Kojto	108:34e6b704fe68	287	* @brief TIM Time Base Handle Structure definition
bogdanm	85:024bf7f99721	288	*/
bogdanm	85:024bf7f99721	289	typedef struct
bogdanm	85:024bf7f99721	290	{
Kojto	108:34e6b704fe68	291	TIM_TypeDef Instance; /!< Register base address */
bogdanm	85:024bf7f99721	292	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
Kojto	108:34e6b704fe68	293	HAL_TIM_ActiveChannel Channel; /!< Active channel /
bogdanm	85:024bf7f99721	294	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
Kojto	93:e188a91d3eaa	295	This array is accessed by a @ref TIM_DMA_Handle_index */
bogdanm	85:024bf7f99721	296	HAL_LockTypeDef Lock; /!< Locking object /
Kojto	108:34e6b704fe68	297	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
bogdanm	85:024bf7f99721	298	}TIM_HandleTypeDef;
bogdanm	85:024bf7f99721	299
bogdanm	92:4fc01daae5a5	300	/**
bogdanm	92:4fc01daae5a5	301	* @}
bogdanm	92:4fc01daae5a5	302	*/
bogdanm	92:4fc01daae5a5	303
bogdanm	85:024bf7f99721	304	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	305	/** @defgroup TIM_Exported_Constants TIM Exported Constants
bogdanm	85:024bf7f99721	306	* @{
bogdanm	85:024bf7f99721	307	*/
bogdanm	85:024bf7f99721	308
Kojto	108:34e6b704fe68	309	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
bogdanm	85:024bf7f99721	310	* @{
bogdanm	85:024bf7f99721	311	*/
<>	134:ad3be0349dc5	312	#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /!< Polarity for TIx source /
bogdanm	85:024bf7f99721	313	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
bogdanm	85:024bf7f99721	314	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
bogdanm	85:024bf7f99721	315	/**
bogdanm	85:024bf7f99721	316	* @}
bogdanm	85:024bf7f99721	317	*/
bogdanm	85:024bf7f99721	318
bogdanm	92:4fc01daae5a5	319	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
bogdanm	85:024bf7f99721	320	* @{
bogdanm	85:024bf7f99721	321	*/
Kojto	108:34e6b704fe68	322	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
<>	134:ad3be0349dc5	323	#define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /!< Polarity for ETR source /
bogdanm	85:024bf7f99721	324	/**
bogdanm	85:024bf7f99721	325	* @}
bogdanm	85:024bf7f99721	326	*/
bogdanm	85:024bf7f99721	327
bogdanm	92:4fc01daae5a5	328	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
bogdanm	85:024bf7f99721	329	* @{
bogdanm	85:024bf7f99721	330	*/
<>	134:ad3be0349dc5	331	#define TIM_ETRPRESCALER_DIV1 (0x0000U) /!< No prescaler is used /
bogdanm	85:024bf7f99721	332	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
bogdanm	85:024bf7f99721	333	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
bogdanm	85:024bf7f99721	334	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
bogdanm	85:024bf7f99721	335	/**
bogdanm	85:024bf7f99721	336	* @}
bogdanm	85:024bf7f99721	337	*/
bogdanm	85:024bf7f99721	338
bogdanm	92:4fc01daae5a5	339	/** @defgroup TIM_Counter_Mode TIM Counter Mode
bogdanm	85:024bf7f99721	340	* @{
bogdanm	85:024bf7f99721	341	*/
<>	134:ad3be0349dc5	342	#define TIM_COUNTERMODE_UP (0x0000U)
bogdanm	85:024bf7f99721	343	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm	85:024bf7f99721	344	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm	85:024bf7f99721	345	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm	85:024bf7f99721	346	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm	85:024bf7f99721	347	/**
bogdanm	85:024bf7f99721	348	* @}
bogdanm	85:024bf7f99721	349	*/
bogdanm	85:024bf7f99721	350
Kojto	108:34e6b704fe68	351	/** @defgroup TIM_ClockDivision TIM Clock Division
bogdanm	85:024bf7f99721	352	* @{
bogdanm	85:024bf7f99721	353	*/
<>	134:ad3be0349dc5	354	#define TIM_CLOCKDIVISION_DIV1 (0x0000U)
Kojto	108:34e6b704fe68	355	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
Kojto	108:34e6b704fe68	356	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
Kojto	108:34e6b704fe68	357	/**
Kojto	108:34e6b704fe68	358	* @}
Kojto	108:34e6b704fe68	359	*/
bogdanm	92:4fc01daae5a5	360
<>	134:ad3be0349dc5	361	/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
<>	134:ad3be0349dc5	362	* @{
<>	134:ad3be0349dc5	363	*/
<>	134:ad3be0349dc5	364	#define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /!< TIMx_ARR register is not buffered /
<>	134:ad3be0349dc5	365	#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /!< TIMx_ARR register is buffered /
<>	134:ad3be0349dc5	366	/**
<>	134:ad3be0349dc5	367	* @}
<>	134:ad3be0349dc5	368	*/
<>	134:ad3be0349dc5	369
Kojto	108:34e6b704fe68	370	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
Kojto	108:34e6b704fe68	371	* @{
Kojto	108:34e6b704fe68	372	*/
<>	134:ad3be0349dc5	373	#define TIM_OCMODE_TIMING (0x0000U)
bogdanm	85:024bf7f99721	374	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
bogdanm	85:024bf7f99721	375	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
bogdanm	85:024bf7f99721	376	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
bogdanm	85:024bf7f99721	377	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
bogdanm	85:024bf7f99721	378	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
bogdanm	85:024bf7f99721	379	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
bogdanm	85:024bf7f99721	380	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
bogdanm	85:024bf7f99721	381	/**
bogdanm	85:024bf7f99721	382	* @}
bogdanm	85:024bf7f99721	383	*/
bogdanm	85:024bf7f99721	384
bogdanm	92:4fc01daae5a5	385	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
bogdanm	85:024bf7f99721	386	* @{
bogdanm	85:024bf7f99721	387	*/
<>	134:ad3be0349dc5	388	#define TIM_OCFAST_DISABLE (0x0000U)
bogdanm	85:024bf7f99721	389	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm	85:024bf7f99721	390	/**
bogdanm	85:024bf7f99721	391	* @}
bogdanm	85:024bf7f99721	392	*/
bogdanm	92:4fc01daae5a5	393
bogdanm	92:4fc01daae5a5	394	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
bogdanm	85:024bf7f99721	395	* @{
bogdanm	85:024bf7f99721	396	*/
<>	134:ad3be0349dc5	397	#define TIM_OCPOLARITY_HIGH (0x0000U)
bogdanm	85:024bf7f99721	398	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm	85:024bf7f99721	399	/**
bogdanm	85:024bf7f99721	400	* @}
bogdanm	85:024bf7f99721	401	*/
bogdanm	85:024bf7f99721	402
bogdanm	92:4fc01daae5a5	403	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
bogdanm	85:024bf7f99721	404	* @{
Kojto	108:34e6b704fe68	405	*/
<>	134:ad3be0349dc5	406	#define TIM_OCNPOLARITY_HIGH (0x0000U)
bogdanm	85:024bf7f99721	407	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
bogdanm	85:024bf7f99721	408	/**
bogdanm	85:024bf7f99721	409	* @}
bogdanm	85:024bf7f99721	410	*/
bogdanm	85:024bf7f99721	411
bogdanm	92:4fc01daae5a5	412	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
bogdanm	85:024bf7f99721	413	* @{
bogdanm	85:024bf7f99721	414	*/
bogdanm	85:024bf7f99721	415	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
<>	134:ad3be0349dc5	416	#define TIM_OCIDLESTATE_RESET (0x0000U)
bogdanm	85:024bf7f99721	417	/**
bogdanm	85:024bf7f99721	418	* @}
bogdanm	85:024bf7f99721	419	*/
bogdanm	85:024bf7f99721	420
bogdanm	92:4fc01daae5a5	421	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
bogdanm	85:024bf7f99721	422	* @{
bogdanm	85:024bf7f99721	423	*/
bogdanm	85:024bf7f99721	424	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
<>	134:ad3be0349dc5	425	#define TIM_OCNIDLESTATE_RESET (0x0000U)
bogdanm	85:024bf7f99721	426	/**
bogdanm	85:024bf7f99721	427	* @}
bogdanm	85:024bf7f99721	428	*/
bogdanm	85:024bf7f99721	429
bogdanm	92:4fc01daae5a5	430	/** @defgroup TIM_Channel TIM Channel
bogdanm	85:024bf7f99721	431	* @{
bogdanm	85:024bf7f99721	432	*/
<>	134:ad3be0349dc5	433	#define TIM_CHANNEL_1 (0x0000U)
<>	134:ad3be0349dc5	434	#define TIM_CHANNEL_2 (0x0004U)
<>	134:ad3be0349dc5	435	#define TIM_CHANNEL_3 (0x0008U)
<>	134:ad3be0349dc5	436	#define TIM_CHANNEL_4 (0x000CU)
<>	134:ad3be0349dc5	437	#define TIM_CHANNEL_ALL (0x0018U)
bogdanm	85:024bf7f99721	438	/**
bogdanm	85:024bf7f99721	439	* @}
bogdanm	85:024bf7f99721	440	*/
bogdanm	85:024bf7f99721	441
bogdanm	92:4fc01daae5a5	442	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
bogdanm	85:024bf7f99721	443	* @{
bogdanm	85:024bf7f99721	444	*/
bogdanm	85:024bf7f99721	445	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm	85:024bf7f99721	446	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm	85:024bf7f99721	447	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm	85:024bf7f99721	448	/**
bogdanm	85:024bf7f99721	449	* @}
bogdanm	85:024bf7f99721	450	*/
bogdanm	85:024bf7f99721	451
bogdanm	92:4fc01daae5a5	452	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
bogdanm	85:024bf7f99721	453	* @{
bogdanm	85:024bf7f99721	454	*/
bogdanm	85:024bf7f99721	455	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	85:024bf7f99721	456	connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm	85:024bf7f99721	457	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	85:024bf7f99721	458	connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm	85:024bf7f99721	459	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
bogdanm	85:024bf7f99721	460	/**
bogdanm	85:024bf7f99721	461	* @}
bogdanm	85:024bf7f99721	462	*/
bogdanm	85:024bf7f99721	463
bogdanm	92:4fc01daae5a5	464	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
bogdanm	85:024bf7f99721	465	* @{
bogdanm	85:024bf7f99721	466	*/
<>	134:ad3be0349dc5	467	#define TIM_ICPSC_DIV1 (0x0000U) /!< Capture performed each time an edge is detected on the capture input /
bogdanm	85:024bf7f99721	468	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
bogdanm	85:024bf7f99721	469	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
bogdanm	85:024bf7f99721	470	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
bogdanm	85:024bf7f99721	471	/**
bogdanm	85:024bf7f99721	472	* @}
bogdanm	85:024bf7f99721	473	*/
bogdanm	85:024bf7f99721	474
bogdanm	92:4fc01daae5a5	475	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
bogdanm	85:024bf7f99721	476	* @{
bogdanm	85:024bf7f99721	477	*/
bogdanm	85:024bf7f99721	478	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
<>	134:ad3be0349dc5	479	#define TIM_OPMODE_REPETITIVE (0x0000U)
bogdanm	85:024bf7f99721	480	/**
bogdanm	85:024bf7f99721	481	* @}
bogdanm	85:024bf7f99721	482	*/
Kojto	108:34e6b704fe68	483
bogdanm	92:4fc01daae5a5	484	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
bogdanm	85:024bf7f99721	485	* @{
Kojto	108:34e6b704fe68	486	*/
bogdanm	85:024bf7f99721	487	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm	85:024bf7f99721	488	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm	85:024bf7f99721	489	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
bogdanm	85:024bf7f99721	490	/**
bogdanm	85:024bf7f99721	491	* @}
bogdanm	85:024bf7f99721	492	*/
Kojto	108:34e6b704fe68	493
Kojto	108:34e6b704fe68	494	/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
bogdanm	85:024bf7f99721	495	* @{
Kojto	108:34e6b704fe68	496	*/
bogdanm	85:024bf7f99721	497	#define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm	85:024bf7f99721	498	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm	85:024bf7f99721	499	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm	85:024bf7f99721	500	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm	85:024bf7f99721	501	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm	85:024bf7f99721	502	#define TIM_IT_COM (TIM_DIER_COMIE)
bogdanm	85:024bf7f99721	503	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm	85:024bf7f99721	504	#define TIM_IT_BREAK (TIM_DIER_BIE)
bogdanm	85:024bf7f99721	505	/**
bogdanm	85:024bf7f99721	506	* @}
bogdanm	85:024bf7f99721	507	*/
bogdanm	85:024bf7f99721	508
Kojto	108:34e6b704fe68	509	/** @defgroup TIM_Commutation_Source TIM Commutation Source
bogdanm	92:4fc01daae5a5	510	* @{
bogdanm	92:4fc01daae5a5	511	*/
bogdanm	85:024bf7f99721	512	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
<>	134:ad3be0349dc5	513	#define TIM_COMMUTATION_SOFTWARE (0x0000U)
bogdanm	85:024bf7f99721	514
bogdanm	92:4fc01daae5a5	515	/**
bogdanm	92:4fc01daae5a5	516	* @}
bogdanm	92:4fc01daae5a5	517	*/
Kojto	108:34e6b704fe68	518
bogdanm	92:4fc01daae5a5	519	/** @defgroup TIM_DMA_sources TIM DMA Sources
bogdanm	85:024bf7f99721	520	* @{
bogdanm	85:024bf7f99721	521	*/
bogdanm	85:024bf7f99721	522	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm	85:024bf7f99721	523	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm	85:024bf7f99721	524	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm	85:024bf7f99721	525	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm	85:024bf7f99721	526	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm	85:024bf7f99721	527	#define TIM_DMA_COM (TIM_DIER_COMDE)
bogdanm	85:024bf7f99721	528	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm	85:024bf7f99721	529	/**
bogdanm	85:024bf7f99721	530	* @}
bogdanm	85:024bf7f99721	531	*/
bogdanm	85:024bf7f99721	532
bogdanm	92:4fc01daae5a5	533	/** @defgroup TIM_Event_Source TIM Event Source
bogdanm	85:024bf7f99721	534	* @{
bogdanm	85:024bf7f99721	535	*/
Kojto	108:34e6b704fe68	536	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
Kojto	108:34e6b704fe68	537	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
Kojto	108:34e6b704fe68	538	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
Kojto	108:34e6b704fe68	539	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
Kojto	108:34e6b704fe68	540	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
Kojto	108:34e6b704fe68	541	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
Kojto	108:34e6b704fe68	542	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
Kojto	108:34e6b704fe68	543	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
bogdanm	85:024bf7f99721	544	/**
bogdanm	85:024bf7f99721	545	* @}
bogdanm	85:024bf7f99721	546	*/
bogdanm	85:024bf7f99721	547
bogdanm	92:4fc01daae5a5	548	/** @defgroup TIM_Flag_definition TIM Flag Definition
bogdanm	85:024bf7f99721	549	* @{
bogdanm	85:024bf7f99721	550	*/
bogdanm	85:024bf7f99721	551	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm	85:024bf7f99721	552	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm	85:024bf7f99721	553	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm	85:024bf7f99721	554	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm	85:024bf7f99721	555	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm	85:024bf7f99721	556	#define TIM_FLAG_COM (TIM_SR_COMIF)
bogdanm	85:024bf7f99721	557	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm	85:024bf7f99721	558	#define TIM_FLAG_BREAK (TIM_SR_BIF)
bogdanm	85:024bf7f99721	559	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm	85:024bf7f99721	560	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm	85:024bf7f99721	561	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm	85:024bf7f99721	562	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm	85:024bf7f99721	563	/**
bogdanm	85:024bf7f99721	564	* @}
bogdanm	85:024bf7f99721	565	*/
bogdanm	85:024bf7f99721	566
bogdanm	92:4fc01daae5a5	567	/** @defgroup TIM_Clock_Source TIM Clock Source
bogdanm	85:024bf7f99721	568	* @{
bogdanm	85:024bf7f99721	569	*/
Kojto	108:34e6b704fe68	570	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
Kojto	108:34e6b704fe68	571	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
<>	134:ad3be0349dc5	572	#define TIM_CLOCKSOURCE_ITR0 (0x0000U)
bogdanm	85:024bf7f99721	573	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm	85:024bf7f99721	574	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm	85:024bf7f99721	575	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
bogdanm	85:024bf7f99721	576	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm	85:024bf7f99721	577	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
bogdanm	85:024bf7f99721	578	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
bogdanm	85:024bf7f99721	579	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm	85:024bf7f99721	580	/**
bogdanm	85:024bf7f99721	581	* @}
bogdanm	85:024bf7f99721	582	*/
bogdanm	85:024bf7f99721	583
bogdanm	92:4fc01daae5a5	584	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
bogdanm	85:024bf7f99721	585	* @{
bogdanm	85:024bf7f99721	586	*/
Kojto	108:34e6b704fe68	587	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
Kojto	108:34e6b704fe68	588	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
Kojto	108:34e6b704fe68	589	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
Kojto	108:34e6b704fe68	590	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
Kojto	108:34e6b704fe68	591	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
bogdanm	85:024bf7f99721	592	/**
bogdanm	85:024bf7f99721	593	* @}
bogdanm	85:024bf7f99721	594	*/
Kojto	108:34e6b704fe68	595
bogdanm	92:4fc01daae5a5	596	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
bogdanm	85:024bf7f99721	597	* @{
Kojto	108:34e6b704fe68	598	*/
bogdanm	85:024bf7f99721	599	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	85:024bf7f99721	600	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
bogdanm	85:024bf7f99721	601	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
bogdanm	85:024bf7f99721	602	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
bogdanm	85:024bf7f99721	603	/**
bogdanm	85:024bf7f99721	604	* @}
bogdanm	85:024bf7f99721	605	*/
bogdanm	85:024bf7f99721	606
bogdanm	92:4fc01daae5a5	607	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
bogdanm	85:024bf7f99721	608	* @{
bogdanm	85:024bf7f99721	609	*/
Kojto	108:34e6b704fe68	610	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
Kojto	108:34e6b704fe68	611	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
bogdanm	85:024bf7f99721	612	/**
bogdanm	85:024bf7f99721	613	* @}
Kojto	108:34e6b704fe68	614	*/
bogdanm	85:024bf7f99721	615
bogdanm	92:4fc01daae5a5	616	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
bogdanm	85:024bf7f99721	617	* @{
bogdanm	85:024bf7f99721	618	*/
bogdanm	85:024bf7f99721	619	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	85:024bf7f99721	620	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
bogdanm	85:024bf7f99721	621	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
bogdanm	85:024bf7f99721	622	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
bogdanm	85:024bf7f99721	623	/**
bogdanm	85:024bf7f99721	624	* @}
bogdanm	85:024bf7f99721	625	*/
bogdanm	85:024bf7f99721	626
Kojto	108:34e6b704fe68	627	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
bogdanm	85:024bf7f99721	628	* @{
bogdanm	85:024bf7f99721	629	*/
bogdanm	85:024bf7f99721	630	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
<>	134:ad3be0349dc5	631	#define TIM_OSSR_DISABLE (0x0000U)
bogdanm	85:024bf7f99721	632	/**
bogdanm	85:024bf7f99721	633	* @}
bogdanm	85:024bf7f99721	634	*/
bogdanm	85:024bf7f99721	635
Kojto	108:34e6b704fe68	636	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
bogdanm	85:024bf7f99721	637	* @{
bogdanm	85:024bf7f99721	638	*/
bogdanm	85:024bf7f99721	639	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
<>	134:ad3be0349dc5	640	#define TIM_OSSI_DISABLE (0x0000U)
bogdanm	85:024bf7f99721	641	/**
bogdanm	85:024bf7f99721	642	* @}
bogdanm	85:024bf7f99721	643	*/
Kojto	108:34e6b704fe68	644
Kojto	108:34e6b704fe68	645	/** @defgroup TIM_Lock_level TIM Lock level
bogdanm	85:024bf7f99721	646	* @{
bogdanm	85:024bf7f99721	647	*/
<>	134:ad3be0349dc5	648	#define TIM_LOCKLEVEL_OFF (0x0000U)
bogdanm	85:024bf7f99721	649	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm	85:024bf7f99721	650	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm	85:024bf7f99721	651	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm	85:024bf7f99721	652	/**
bogdanm	85:024bf7f99721	653	* @}
bogdanm	85:024bf7f99721	654	*/
Kojto	108:34e6b704fe68	655
Kojto	108:34e6b704fe68	656	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
bogdanm	85:024bf7f99721	657	* @{
bogdanm	85:024bf7f99721	658	*/
bogdanm	85:024bf7f99721	659	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
<>	134:ad3be0349dc5	660	#define TIM_BREAK_DISABLE (0x0000U)
bogdanm	85:024bf7f99721	661	/**
bogdanm	85:024bf7f99721	662	* @}
bogdanm	85:024bf7f99721	663	*/
Kojto	108:34e6b704fe68	664
bogdanm	92:4fc01daae5a5	665	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
bogdanm	85:024bf7f99721	666	* @{
bogdanm	85:024bf7f99721	667	*/
<>	134:ad3be0349dc5	668	#define TIM_BREAKPOLARITY_LOW (0x0000U)
bogdanm	85:024bf7f99721	669	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm	85:024bf7f99721	670	/**
bogdanm	85:024bf7f99721	671	* @}
bogdanm	85:024bf7f99721	672	*/
bogdanm	92:4fc01daae5a5	673	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
bogdanm	85:024bf7f99721	674	* @{
bogdanm	85:024bf7f99721	675	*/
bogdanm	85:024bf7f99721	676	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
<>	134:ad3be0349dc5	677	#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)
bogdanm	85:024bf7f99721	678	/**
bogdanm	85:024bf7f99721	679	* @}
bogdanm	85:024bf7f99721	680	*/
bogdanm	85:024bf7f99721	681
bogdanm	92:4fc01daae5a5	682	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
bogdanm	85:024bf7f99721	683	* @{
bogdanm	85:024bf7f99721	684	*/
<>	134:ad3be0349dc5	685	#define TIM_TRGO_RESET (0x0000U)
Kojto	108:34e6b704fe68	686	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
Kojto	108:34e6b704fe68	687	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
Kojto	108:34e6b704fe68	688	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
Kojto	108:34e6b704fe68	689	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
Kojto	108:34e6b704fe68	690	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
Kojto	108:34e6b704fe68	691	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
Kojto	108:34e6b704fe68	692	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	85:024bf7f99721	693	/**
bogdanm	85:024bf7f99721	694	* @}
Kojto	108:34e6b704fe68	695	*/
bogdanm	85:024bf7f99721	696
bogdanm	92:4fc01daae5a5	697	/** @defgroup TIM_Slave_Mode TIM Slave Mode
bogdanm	85:024bf7f99721	698	* @{
bogdanm	85:024bf7f99721	699	*/
<>	134:ad3be0349dc5	700	#define TIM_SLAVEMODE_DISABLE (0x0000U)
<>	134:ad3be0349dc5	701	#define TIM_SLAVEMODE_RESET (0x0004U)
<>	134:ad3be0349dc5	702	#define TIM_SLAVEMODE_GATED (0x0005U)
<>	134:ad3be0349dc5	703	#define TIM_SLAVEMODE_TRIGGER (0x0006U)
<>	134:ad3be0349dc5	704	#define TIM_SLAVEMODE_EXTERNAL1 (0x0007U)
bogdanm	85:024bf7f99721	705	/**
bogdanm	85:024bf7f99721	706	* @}
bogdanm	85:024bf7f99721	707	*/
bogdanm	85:024bf7f99721	708
Kojto	108:34e6b704fe68	709	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
bogdanm	85:024bf7f99721	710	* @{
bogdanm	85:024bf7f99721	711	*/
<>	134:ad3be0349dc5	712	#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U)
<>	134:ad3be0349dc5	713	#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U)
bogdanm	85:024bf7f99721	714	/**
bogdanm	85:024bf7f99721	715	* @}
bogdanm	85:024bf7f99721	716	*/
Kojto	108:34e6b704fe68	717
bogdanm	92:4fc01daae5a5	718	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
bogdanm	85:024bf7f99721	719	* @{
bogdanm	85:024bf7f99721	720	*/
<>	134:ad3be0349dc5	721	#define TIM_TS_ITR0 (0x0000U)
<>	134:ad3be0349dc5	722	#define TIM_TS_ITR1 (0x0010U)
<>	134:ad3be0349dc5	723	#define TIM_TS_ITR2 (0x0020U)
<>	134:ad3be0349dc5	724	#define TIM_TS_ITR3 (0x0030U)
<>	134:ad3be0349dc5	725	#define TIM_TS_TI1F_ED (0x0040U)
<>	134:ad3be0349dc5	726	#define TIM_TS_TI1FP1 (0x0050U)
<>	134:ad3be0349dc5	727	#define TIM_TS_TI2FP2 (0x0060U)
<>	134:ad3be0349dc5	728	#define TIM_TS_ETRF (0x0070U)
<>	134:ad3be0349dc5	729	#define TIM_TS_NONE (0xFFFFU)
bogdanm	85:024bf7f99721	730	/**
bogdanm	85:024bf7f99721	731	* @}
bogdanm	85:024bf7f99721	732	*/
bogdanm	85:024bf7f99721	733
bogdanm	92:4fc01daae5a5	734	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
bogdanm	85:024bf7f99721	735	* @{
bogdanm	85:024bf7f99721	736	*/
Kojto	108:34e6b704fe68	737	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
Kojto	108:34e6b704fe68	738	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
Kojto	108:34e6b704fe68	739	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
Kojto	108:34e6b704fe68	740	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
Kojto	108:34e6b704fe68	741	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	85:024bf7f99721	742	/**
bogdanm	85:024bf7f99721	743	* @}
bogdanm	85:024bf7f99721	744	*/
bogdanm	85:024bf7f99721	745
bogdanm	92:4fc01daae5a5	746	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
bogdanm	85:024bf7f99721	747	* @{
bogdanm	85:024bf7f99721	748	*/
bogdanm	85:024bf7f99721	749	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	85:024bf7f99721	750	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
bogdanm	85:024bf7f99721	751	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
bogdanm	85:024bf7f99721	752	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
bogdanm	85:024bf7f99721	753	/**
bogdanm	85:024bf7f99721	754	* @}
bogdanm	85:024bf7f99721	755	*/
bogdanm	85:024bf7f99721	756
bogdanm	92:4fc01daae5a5	757	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
bogdanm	85:024bf7f99721	758	* @{
bogdanm	85:024bf7f99721	759	*/
<>	134:ad3be0349dc5	760	#define TIM_TI1SELECTION_CH1 (0x0000U)
bogdanm	85:024bf7f99721	761	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm	85:024bf7f99721	762	/**
bogdanm	85:024bf7f99721	763	* @}
bogdanm	85:024bf7f99721	764	*/
bogdanm	85:024bf7f99721	765
Kojto	108:34e6b704fe68	766	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
bogdanm	85:024bf7f99721	767	* @{
bogdanm	85:024bf7f99721	768	*/
Kojto	108:34e6b704fe68	769	#define TIM_DMABASE_CR1 (0x00000000)
Kojto	108:34e6b704fe68	770	#define TIM_DMABASE_CR2 (0x00000001)
Kojto	108:34e6b704fe68	771	#define TIM_DMABASE_SMCR (0x00000002)
Kojto	108:34e6b704fe68	772	#define TIM_DMABASE_DIER (0x00000003)
Kojto	108:34e6b704fe68	773	#define TIM_DMABASE_SR (0x00000004)
Kojto	108:34e6b704fe68	774	#define TIM_DMABASE_EGR (0x00000005)
Kojto	108:34e6b704fe68	775	#define TIM_DMABASE_CCMR1 (0x00000006)
Kojto	108:34e6b704fe68	776	#define TIM_DMABASE_CCMR2 (0x00000007)
Kojto	108:34e6b704fe68	777	#define TIM_DMABASE_CCER (0x00000008)
Kojto	108:34e6b704fe68	778	#define TIM_DMABASE_CNT (0x00000009)
Kojto	108:34e6b704fe68	779	#define TIM_DMABASE_PSC (0x0000000A)
Kojto	108:34e6b704fe68	780	#define TIM_DMABASE_ARR (0x0000000B)
Kojto	108:34e6b704fe68	781	#define TIM_DMABASE_RCR (0x0000000C)
Kojto	108:34e6b704fe68	782	#define TIM_DMABASE_CCR1 (0x0000000D)
Kojto	108:34e6b704fe68	783	#define TIM_DMABASE_CCR2 (0x0000000E)
Kojto	108:34e6b704fe68	784	#define TIM_DMABASE_CCR3 (0x0000000F)
Kojto	108:34e6b704fe68	785	#define TIM_DMABASE_CCR4 (0x00000010)
Kojto	108:34e6b704fe68	786	#define TIM_DMABASE_BDTR (0x00000011)
Kojto	108:34e6b704fe68	787	#define TIM_DMABASE_DCR (0x00000012)
Kojto	108:34e6b704fe68	788	#define TIM_DMABASE_OR (0x00000013)
bogdanm	85:024bf7f99721	789	/**
bogdanm	85:024bf7f99721	790	* @}
bogdanm	85:024bf7f99721	791	*/
bogdanm	85:024bf7f99721	792
bogdanm	92:4fc01daae5a5	793	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
bogdanm	85:024bf7f99721	794	* @{
bogdanm	85:024bf7f99721	795	*/
Kojto	108:34e6b704fe68	796	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
Kojto	108:34e6b704fe68	797	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
Kojto	108:34e6b704fe68	798	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
Kojto	108:34e6b704fe68	799	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
Kojto	108:34e6b704fe68	800	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
Kojto	108:34e6b704fe68	801	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
Kojto	108:34e6b704fe68	802	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
Kojto	108:34e6b704fe68	803	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
Kojto	108:34e6b704fe68	804	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
Kojto	108:34e6b704fe68	805	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
Kojto	108:34e6b704fe68	806	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
Kojto	108:34e6b704fe68	807	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
Kojto	108:34e6b704fe68	808	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
Kojto	108:34e6b704fe68	809	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
Kojto	108:34e6b704fe68	810	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
Kojto	108:34e6b704fe68	811	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
Kojto	108:34e6b704fe68	812	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
Kojto	108:34e6b704fe68	813	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
bogdanm	85:024bf7f99721	814	/**
bogdanm	85:024bf7f99721	815	* @}
bogdanm	85:024bf7f99721	816	*/
bogdanm	85:024bf7f99721	817
Kojto	93:e188a91d3eaa	818	/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
bogdanm	85:024bf7f99721	819	* @{
bogdanm	85:024bf7f99721	820	*/
<>	134:ad3be0349dc5	821	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /!< Index of the DMA handle used for Update DMA requests /
<>	134:ad3be0349dc5	822	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
<>	134:ad3be0349dc5	823	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
<>	134:ad3be0349dc5	824	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
<>	134:ad3be0349dc5	825	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
<>	134:ad3be0349dc5	826	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /!< Index of the DMA handle used for Commutation DMA requests /
<>	134:ad3be0349dc5	827	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /!< Index of the DMA handle used for Trigger DMA requests /
bogdanm	85:024bf7f99721	828	/**
bogdanm	85:024bf7f99721	829	* @}
bogdanm	85:024bf7f99721	830	*/
bogdanm	85:024bf7f99721	831
Kojto	108:34e6b704fe68	832	/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
bogdanm	85:024bf7f99721	833	* @{
bogdanm	85:024bf7f99721	834	*/
<>	134:ad3be0349dc5	835	#define TIM_CCx_ENABLE (0x0001U)
<>	134:ad3be0349dc5	836	#define TIM_CCx_DISABLE (0x0000U)
<>	134:ad3be0349dc5	837	#define TIM_CCxN_ENABLE (0x0004U)
<>	134:ad3be0349dc5	838	#define TIM_CCxN_DISABLE (0x0000U)
bogdanm	85:024bf7f99721	839	/**
bogdanm	85:024bf7f99721	840	* @}
bogdanm	85:024bf7f99721	841	*/
bogdanm	85:024bf7f99721	842
bogdanm	85:024bf7f99721	843	/**
bogdanm	85:024bf7f99721	844	* @}
bogdanm	85:024bf7f99721	845	*/
Kojto	108:34e6b704fe68	846
Kojto	108:34e6b704fe68	847	/* Private Constants -----------------------------------------------------------*/
Kojto	108:34e6b704fe68	848	/** @defgroup TIM_Private_Constants TIM Private Constants
Kojto	108:34e6b704fe68	849	* @{
Kojto	108:34e6b704fe68	850	*/
Kojto	108:34e6b704fe68	851
Kojto	108:34e6b704fe68	852	/* The counter of a timer instance is disabled only if all the CCx and CCxN
Kojto	108:34e6b704fe68	853	channels have been disabled */
Kojto	108:34e6b704fe68	854	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
Kojto	108:34e6b704fe68	855	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
Kojto	108:34e6b704fe68	856
Kojto	108:34e6b704fe68	857	/**
Kojto	108:34e6b704fe68	858	* @}
Kojto	108:34e6b704fe68	859	*/
Kojto	108:34e6b704fe68	860
Kojto	108:34e6b704fe68	861	/* Private Macros -----------------------------------------------------------*/
Kojto	108:34e6b704fe68	862	/** @defgroup TIM_Private_Macros TIM Private Macros
Kojto	108:34e6b704fe68	863	* @{
Kojto	108:34e6b704fe68	864	*/
Kojto	108:34e6b704fe68	865
Kojto	108:34e6b704fe68	866	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
Kojto	108:34e6b704fe68	867	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
Kojto	108:34e6b704fe68	868	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
Kojto	108:34e6b704fe68	869	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
Kojto	108:34e6b704fe68	870	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
Kojto	108:34e6b704fe68	871
Kojto	108:34e6b704fe68	872	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
Kojto	108:34e6b704fe68	873	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
Kojto	108:34e6b704fe68	874	((DIV) == TIM_CLOCKDIVISION_DIV4))
Kojto	108:34e6b704fe68	875
<>	134:ad3be0349dc5	876	#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) \|\| \
<>	134:ad3be0349dc5	877	((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
<>	134:ad3be0349dc5	878
Kojto	108:34e6b704fe68	879	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
Kojto	108:34e6b704fe68	880	((MODE) == TIM_OCMODE_PWM2))
Kojto	108:34e6b704fe68	881
Kojto	108:34e6b704fe68	882	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
Kojto	108:34e6b704fe68	883	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
Kojto	108:34e6b704fe68	884	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
Kojto	108:34e6b704fe68	885	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
Kojto	108:34e6b704fe68	886	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
Kojto	108:34e6b704fe68	887	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
Kojto	108:34e6b704fe68	888
Kojto	108:34e6b704fe68	889	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
Kojto	108:34e6b704fe68	890	((STATE) == TIM_OCFAST_ENABLE))
Kojto	108:34e6b704fe68	891
Kojto	108:34e6b704fe68	892	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
Kojto	108:34e6b704fe68	893	((POLARITY) == TIM_OCPOLARITY_LOW))
Kojto	108:34e6b704fe68	894
Kojto	108:34e6b704fe68	895	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
Kojto	108:34e6b704fe68	896	((POLARITY) == TIM_OCNPOLARITY_LOW))
Kojto	108:34e6b704fe68	897
Kojto	108:34e6b704fe68	898	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
Kojto	108:34e6b704fe68	899	((STATE) == TIM_OCIDLESTATE_RESET))
Kojto	108:34e6b704fe68	900
Kojto	108:34e6b704fe68	901	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
Kojto	108:34e6b704fe68	902	((STATE) == TIM_OCNIDLESTATE_RESET))
Kojto	108:34e6b704fe68	903
Kojto	108:34e6b704fe68	904	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	108:34e6b704fe68	905	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	108:34e6b704fe68	906	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	108:34e6b704fe68	907	((CHANNEL) == TIM_CHANNEL_4) \|\| \
Kojto	108:34e6b704fe68	908	((CHANNEL) == TIM_CHANNEL_ALL))
Kojto	108:34e6b704fe68	909
Kojto	108:34e6b704fe68	910	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	108:34e6b704fe68	911	((CHANNEL) == TIM_CHANNEL_2))
Kojto	108:34e6b704fe68	912
Kojto	108:34e6b704fe68	913	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	108:34e6b704fe68	914	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	108:34e6b704fe68	915	((CHANNEL) == TIM_CHANNEL_3))
Kojto	108:34e6b704fe68	916
Kojto	108:34e6b704fe68	917	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
Kojto	108:34e6b704fe68	918	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
Kojto	108:34e6b704fe68	919	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
Kojto	108:34e6b704fe68	920
Kojto	108:34e6b704fe68	921	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
Kojto	108:34e6b704fe68	922	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
Kojto	108:34e6b704fe68	923	((SELECTION) == TIM_ICSELECTION_TRC))
Kojto	108:34e6b704fe68	924
Kojto	108:34e6b704fe68	925	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
Kojto	108:34e6b704fe68	926	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
Kojto	108:34e6b704fe68	927	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
Kojto	108:34e6b704fe68	928	((PRESCALER) == TIM_ICPSC_DIV8))
Kojto	108:34e6b704fe68	929
Kojto	108:34e6b704fe68	930	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
Kojto	108:34e6b704fe68	931	((MODE) == TIM_OPMODE_REPETITIVE))
Kojto	108:34e6b704fe68	932
Kojto	108:34e6b704fe68	933	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
Kojto	108:34e6b704fe68	934	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
Kojto	108:34e6b704fe68	935	((MODE) == TIM_ENCODERMODE_TI12))
Kojto	108:34e6b704fe68	936
<>	134:ad3be0349dc5	937	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
Kojto	108:34e6b704fe68	938
<>	134:ad3be0349dc5	939	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
Kojto	108:34e6b704fe68	940
Kojto	108:34e6b704fe68	941	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
Kojto	108:34e6b704fe68	942	((FLAG) == TIM_FLAG_CC1) \|\| \
Kojto	108:34e6b704fe68	943	((FLAG) == TIM_FLAG_CC2) \|\| \
Kojto	108:34e6b704fe68	944	((FLAG) == TIM_FLAG_CC3) \|\| \
Kojto	108:34e6b704fe68	945	((FLAG) == TIM_FLAG_CC4) \|\| \
Kojto	108:34e6b704fe68	946	((FLAG) == TIM_FLAG_COM) \|\| \
Kojto	108:34e6b704fe68	947	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
Kojto	108:34e6b704fe68	948	((FLAG) == TIM_FLAG_BREAK) \|\| \
Kojto	108:34e6b704fe68	949	((FLAG) == TIM_FLAG_CC1OF) \|\| \
Kojto	108:34e6b704fe68	950	((FLAG) == TIM_FLAG_CC2OF) \|\| \
Kojto	108:34e6b704fe68	951	((FLAG) == TIM_FLAG_CC3OF) \|\| \
Kojto	108:34e6b704fe68	952	((FLAG) == TIM_FLAG_CC4OF))
Kojto	108:34e6b704fe68	953
Kojto	108:34e6b704fe68	954	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
Kojto	108:34e6b704fe68	955	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
Kojto	108:34e6b704fe68	956	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
Kojto	108:34e6b704fe68	957	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
Kojto	108:34e6b704fe68	958	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
Kojto	108:34e6b704fe68	959	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
Kojto	108:34e6b704fe68	960	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
Kojto	108:34e6b704fe68	961	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
Kojto	108:34e6b704fe68	962	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
Kojto	108:34e6b704fe68	963	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
Kojto	108:34e6b704fe68	964
Kojto	108:34e6b704fe68	965	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
Kojto	108:34e6b704fe68	966	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
Kojto	108:34e6b704fe68	967	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
Kojto	108:34e6b704fe68	968	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
Kojto	108:34e6b704fe68	969	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
Kojto	108:34e6b704fe68	970
Kojto	108:34e6b704fe68	971	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
Kojto	108:34e6b704fe68	972	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
Kojto	108:34e6b704fe68	973	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
Kojto	108:34e6b704fe68	974	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
Kojto	108:34e6b704fe68	975
<>	134:ad3be0349dc5	976	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
Kojto	108:34e6b704fe68	977
Kojto	108:34e6b704fe68	978	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
Kojto	108:34e6b704fe68	979	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
Kojto	108:34e6b704fe68	980
Kojto	108:34e6b704fe68	981	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
Kojto	108:34e6b704fe68	982	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
Kojto	108:34e6b704fe68	983	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
Kojto	108:34e6b704fe68	984	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
Kojto	108:34e6b704fe68	985
<>	134:ad3be0349dc5	986	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
Kojto	108:34e6b704fe68	987
Kojto	108:34e6b704fe68	988	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
Kojto	108:34e6b704fe68	989	((STATE) == TIM_OSSR_DISABLE))
Kojto	108:34e6b704fe68	990
Kojto	108:34e6b704fe68	991	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
Kojto	108:34e6b704fe68	992	((STATE) == TIM_OSSI_DISABLE))
Kojto	108:34e6b704fe68	993
Kojto	108:34e6b704fe68	994	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
Kojto	108:34e6b704fe68	995	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
Kojto	108:34e6b704fe68	996	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
Kojto	108:34e6b704fe68	997	((LEVEL) == TIM_LOCKLEVEL_3))
Kojto	108:34e6b704fe68	998
Kojto	108:34e6b704fe68	999	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
Kojto	108:34e6b704fe68	1000	((STATE) == TIM_BREAK_DISABLE))
Kojto	108:34e6b704fe68	1001
Kojto	108:34e6b704fe68	1002	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
Kojto	108:34e6b704fe68	1003	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
Kojto	108:34e6b704fe68	1004
Kojto	108:34e6b704fe68	1005	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
Kojto	108:34e6b704fe68	1006	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
Kojto	108:34e6b704fe68	1007
Kojto	108:34e6b704fe68	1008	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
Kojto	108:34e6b704fe68	1009	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
Kojto	108:34e6b704fe68	1010	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
Kojto	108:34e6b704fe68	1011	((SOURCE) == TIM_TRGO_OC1) \|\| \
Kojto	108:34e6b704fe68	1012	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
Kojto	108:34e6b704fe68	1013	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
Kojto	108:34e6b704fe68	1014	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
Kojto	108:34e6b704fe68	1015	((SOURCE) == TIM_TRGO_OC4REF))
Kojto	108:34e6b704fe68	1016
Kojto	108:34e6b704fe68	1017	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
Kojto	108:34e6b704fe68	1018	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
Kojto	108:34e6b704fe68	1019	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
Kojto	108:34e6b704fe68	1020	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
Kojto	108:34e6b704fe68	1021	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
Kojto	108:34e6b704fe68	1022
Kojto	108:34e6b704fe68	1023	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
Kojto	108:34e6b704fe68	1024	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
Kojto	108:34e6b704fe68	1025
Kojto	108:34e6b704fe68	1026	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
Kojto	108:34e6b704fe68	1027	((SELECTION) == TIM_TS_ITR1) \|\| \
Kojto	108:34e6b704fe68	1028	((SELECTION) == TIM_TS_ITR2) \|\| \
Kojto	108:34e6b704fe68	1029	((SELECTION) == TIM_TS_ITR3) \|\| \
Kojto	108:34e6b704fe68	1030	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
Kojto	108:34e6b704fe68	1031	((SELECTION) == TIM_TS_TI1FP1) \|\| \
Kojto	108:34e6b704fe68	1032	((SELECTION) == TIM_TS_TI2FP2) \|\| \
Kojto	108:34e6b704fe68	1033	((SELECTION) == TIM_TS_ETRF))
Kojto	108:34e6b704fe68	1034
Kojto	108:34e6b704fe68	1035	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
Kojto	108:34e6b704fe68	1036	((SELECTION) == TIM_TS_ITR1) \|\| \
Kojto	108:34e6b704fe68	1037	((SELECTION) == TIM_TS_ITR2) \|\| \
Kojto	108:34e6b704fe68	1038	((SELECTION) == TIM_TS_ITR3) \|\| \
Kojto	108:34e6b704fe68	1039	((SELECTION) == TIM_TS_NONE))
Kojto	108:34e6b704fe68	1040
Kojto	108:34e6b704fe68	1041	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
Kojto	108:34e6b704fe68	1042	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
Kojto	108:34e6b704fe68	1043	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
Kojto	108:34e6b704fe68	1044	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
Kojto	108:34e6b704fe68	1045	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
Kojto	108:34e6b704fe68	1046
Kojto	108:34e6b704fe68	1047	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
Kojto	108:34e6b704fe68	1048	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
Kojto	108:34e6b704fe68	1049	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
Kojto	108:34e6b704fe68	1050	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
Kojto	108:34e6b704fe68	1051
<>	134:ad3be0349dc5	1052	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
Kojto	108:34e6b704fe68	1053
Kojto	108:34e6b704fe68	1054	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
Kojto	108:34e6b704fe68	1055	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
Kojto	108:34e6b704fe68	1056
Kojto	108:34e6b704fe68	1057	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
Kojto	108:34e6b704fe68	1058	((BASE) == TIM_DMABASE_CR2) \|\| \
Kojto	108:34e6b704fe68	1059	((BASE) == TIM_DMABASE_SMCR) \|\| \
Kojto	108:34e6b704fe68	1060	((BASE) == TIM_DMABASE_DIER) \|\| \
Kojto	108:34e6b704fe68	1061	((BASE) == TIM_DMABASE_SR) \|\| \
Kojto	108:34e6b704fe68	1062	((BASE) == TIM_DMABASE_EGR) \|\| \
Kojto	108:34e6b704fe68	1063	((BASE) == TIM_DMABASE_CCMR1) \|\| \
Kojto	108:34e6b704fe68	1064	((BASE) == TIM_DMABASE_CCMR2) \|\| \
Kojto	108:34e6b704fe68	1065	((BASE) == TIM_DMABASE_CCER) \|\| \
Kojto	108:34e6b704fe68	1066	((BASE) == TIM_DMABASE_CNT) \|\| \
Kojto	108:34e6b704fe68	1067	((BASE) == TIM_DMABASE_PSC) \|\| \
Kojto	108:34e6b704fe68	1068	((BASE) == TIM_DMABASE_ARR) \|\| \
Kojto	108:34e6b704fe68	1069	((BASE) == TIM_DMABASE_RCR) \|\| \
Kojto	108:34e6b704fe68	1070	((BASE) == TIM_DMABASE_CCR1) \|\| \
Kojto	108:34e6b704fe68	1071	((BASE) == TIM_DMABASE_CCR2) \|\| \
Kojto	108:34e6b704fe68	1072	((BASE) == TIM_DMABASE_CCR3) \|\| \
Kojto	108:34e6b704fe68	1073	((BASE) == TIM_DMABASE_CCR4) \|\| \
Kojto	108:34e6b704fe68	1074	((BASE) == TIM_DMABASE_BDTR) \|\| \
Kojto	108:34e6b704fe68	1075	((BASE) == TIM_DMABASE_DCR) \|\| \
Kojto	108:34e6b704fe68	1076	((BASE) == TIM_DMABASE_OR))
Kojto	108:34e6b704fe68	1077
Kojto	108:34e6b704fe68	1078	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
Kojto	108:34e6b704fe68	1079	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1080	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1081	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1082	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1083	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1084	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1085	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1086	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1087	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1088	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1089	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1090	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1091	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1092	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1093	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1094	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
Kojto	108:34e6b704fe68	1095	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
Kojto	108:34e6b704fe68	1096
<>	134:ad3be0349dc5	1097	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
Kojto	108:34e6b704fe68	1098
Kojto	108:34e6b704fe68	1099	/** @brief Set TIM IC prescaler
Kojto	108:34e6b704fe68	1100	* @param __HANDLE__: TIM handle
Kojto	108:34e6b704fe68	1101	* @param __CHANNEL__: specifies TIM Channel
Kojto	108:34e6b704fe68	1102	* @param __ICPSC__: specifies the prescaler value.
Kojto	108:34e6b704fe68	1103	* @retval None
Kojto	108:34e6b704fe68	1104	*/
Kojto	108:34e6b704fe68	1105	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
Kojto	108:34e6b704fe68	1106	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
<>	134:ad3be0349dc5	1107	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
Kojto	108:34e6b704fe68	1108	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
<>	134:ad3be0349dc5	1109	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
Kojto	108:34e6b704fe68	1110
Kojto	108:34e6b704fe68	1111	/** @brief Reset TIM IC prescaler
Kojto	108:34e6b704fe68	1112	* @param __HANDLE__: TIM handle
Kojto	108:34e6b704fe68	1113	* @param __CHANNEL__: specifies TIM Channel
Kojto	108:34e6b704fe68	1114	* @retval None
Kojto	108:34e6b704fe68	1115	*/
Kojto	108:34e6b704fe68	1116	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
Kojto	108:34e6b704fe68	1117	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
Kojto	108:34e6b704fe68	1118	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
Kojto	108:34e6b704fe68	1119	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
Kojto	108:34e6b704fe68	1120	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
Kojto	108:34e6b704fe68	1121
Kojto	108:34e6b704fe68	1122
Kojto	108:34e6b704fe68	1123	/** @brief Set TIM IC polarity
Kojto	108:34e6b704fe68	1124	* @param __HANDLE__: TIM handle
Kojto	108:34e6b704fe68	1125	* @param __CHANNEL__: specifies TIM Channel
Kojto	108:34e6b704fe68	1126	* @param __POLARITY__: specifies TIM Channel Polarity
Kojto	108:34e6b704fe68	1127	* @retval None
Kojto	108:34e6b704fe68	1128	*/
Kojto	108:34e6b704fe68	1129	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
Kojto	108:34e6b704fe68	1130	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
<>	134:ad3be0349dc5	1131	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
<>	134:ad3be0349dc5	1132	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
<>	134:ad3be0349dc5	1133	((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 12U)))
Kojto	108:34e6b704fe68	1134
Kojto	108:34e6b704fe68	1135	/** @brief Reset TIM IC polarity
Kojto	108:34e6b704fe68	1136	* @param __HANDLE__: TIM handle
Kojto	108:34e6b704fe68	1137	* @param __CHANNEL__: specifies TIM Channel
Kojto	108:34e6b704fe68	1138	* @retval None
Kojto	108:34e6b704fe68	1139	*/
Kojto	108:34e6b704fe68	1140	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
Kojto	108:34e6b704fe68	1141	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
Kojto	108:34e6b704fe68	1142	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
Kojto	108:34e6b704fe68	1143	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
<>	134:ad3be0349dc5	1144	((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P \| TIM_CCER_CC4NP)))
Kojto	108:34e6b704fe68	1145
Kojto	108:34e6b704fe68	1146	/**
Kojto	108:34e6b704fe68	1147	* @}
Kojto	108:34e6b704fe68	1148	*/
Kojto	108:34e6b704fe68	1149
Kojto	108:34e6b704fe68	1150	/* Private Functions --------------------------------------------------------*/
Kojto	108:34e6b704fe68	1151	/** @addtogroup TIM_Private_Functions
Kojto	108:34e6b704fe68	1152	* @{
Kojto	108:34e6b704fe68	1153	*/
Kojto	108:34e6b704fe68	1154	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
Kojto	108:34e6b704fe68	1155	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
Kojto	108:34e6b704fe68	1156	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
Kojto	108:34e6b704fe68	1157	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
Kojto	108:34e6b704fe68	1158	void TIM_DMAError(DMA_HandleTypeDef *hdma);
Kojto	108:34e6b704fe68	1159	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
Kojto	108:34e6b704fe68	1160	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
Kojto	108:34e6b704fe68	1161	/**
Kojto	108:34e6b704fe68	1162	* @}
Kojto	108:34e6b704fe68	1163	*/
Kojto	108:34e6b704fe68	1164
bogdanm	85:024bf7f99721	1165	/* Exported macros -----------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1166	/** @defgroup TIM_Exported_Macros TIM Exported Macros
bogdanm	85:024bf7f99721	1167	* @{
bogdanm	85:024bf7f99721	1168	*/
bogdanm	85:024bf7f99721	1169
bogdanm	85:024bf7f99721	1170	/** @brief Reset TIM handle state
bogdanm	85:024bf7f99721	1171	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1172	* @retval None
bogdanm	85:024bf7f99721	1173	*/
bogdanm	85:024bf7f99721	1174	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm	85:024bf7f99721	1175
bogdanm	85:024bf7f99721	1176	/**
bogdanm	85:024bf7f99721	1177	* @brief Enable the TIM peripheral.
bogdanm	85:024bf7f99721	1178	* @param __HANDLE__: TIM handle
bogdanm	85:024bf7f99721	1179	* @retval None
bogdanm	85:024bf7f99721	1180	*/
bogdanm	85:024bf7f99721	1181	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
bogdanm	85:024bf7f99721	1182
bogdanm	85:024bf7f99721	1183	/**
bogdanm	85:024bf7f99721	1184	* @brief Enable the TIM main Output.
bogdanm	85:024bf7f99721	1185	* @param __HANDLE__: TIM handle
bogdanm	85:024bf7f99721	1186	* @retval None
bogdanm	85:024bf7f99721	1187	*/
bogdanm	85:024bf7f99721	1188	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
bogdanm	85:024bf7f99721	1189
bogdanm	85:024bf7f99721	1190	/**
bogdanm	85:024bf7f99721	1191	* @brief Disable the TIM peripheral.
bogdanm	85:024bf7f99721	1192	* @param __HANDLE__: TIM handle
bogdanm	85:024bf7f99721	1193	* @retval None
bogdanm	85:024bf7f99721	1194	*/
bogdanm	85:024bf7f99721	1195	#define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm	85:024bf7f99721	1196	do { \
Kojto	108:34e6b704fe68	1197	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
bogdanm	85:024bf7f99721	1198	{ \
Kojto	108:34e6b704fe68	1199	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
bogdanm	85:024bf7f99721	1200	{ \
bogdanm	92:4fc01daae5a5	1201	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm	85:024bf7f99721	1202	} \
bogdanm	85:024bf7f99721	1203	} \
bogdanm	85:024bf7f99721	1204	} while(0)
bogdanm	85:024bf7f99721	1205	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
Kojto	108:34e6b704fe68	1206	channels have been disabled */
bogdanm	85:024bf7f99721	1207	/**
bogdanm	85:024bf7f99721	1208	* @brief Disable the TIM main Output.
bogdanm	85:024bf7f99721	1209	* @param __HANDLE__: TIM handle
bogdanm	85:024bf7f99721	1210	* @retval None
Kojto	108:34e6b704fe68	1211	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
bogdanm	85:024bf7f99721	1212	*/
bogdanm	85:024bf7f99721	1213	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
bogdanm	85:024bf7f99721	1214	do { \
Kojto	108:34e6b704fe68	1215	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
bogdanm	85:024bf7f99721	1216	{ \
Kojto	108:34e6b704fe68	1217	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
bogdanm	85:024bf7f99721	1218	{ \
bogdanm	92:4fc01daae5a5	1219	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
bogdanm	85:024bf7f99721	1220	} \
bogdanm	85:024bf7f99721	1221	} \
bogdanm	85:024bf7f99721	1222	} while(0)
bogdanm	85:024bf7f99721	1223
Kojto	108:34e6b704fe68	1224	/**
Kojto	108:34e6b704fe68	1225	* @brief Enables the specified TIM interrupt.
Kojto	108:34e6b704fe68	1226	* @param __HANDLE__: specifies the TIM Handle.
Kojto	108:34e6b704fe68	1227	* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
Kojto	108:34e6b704fe68	1228	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1229	* @arg TIM_IT_UPDATE: Update interrupt
Kojto	108:34e6b704fe68	1230	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
Kojto	108:34e6b704fe68	1231	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
Kojto	108:34e6b704fe68	1232	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
Kojto	108:34e6b704fe68	1233	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
Kojto	108:34e6b704fe68	1234	* @arg TIM_IT_COM: Commutation interrupt
Kojto	108:34e6b704fe68	1235	* @arg TIM_IT_TRIGGER: Trigger interrupt
Kojto	108:34e6b704fe68	1236	* @arg TIM_IT_BREAK: Break interrupt
Kojto	108:34e6b704fe68	1237	* @retval None
Kojto	108:34e6b704fe68	1238	*/
bogdanm	85:024bf7f99721	1239	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
Kojto	108:34e6b704fe68	1240
Kojto	108:34e6b704fe68	1241	/**
Kojto	108:34e6b704fe68	1242	* @brief Disables the specified TIM interrupt.
Kojto	108:34e6b704fe68	1243	* @param __HANDLE__: specifies the TIM Handle.
Kojto	108:34e6b704fe68	1244	* @param __INTERRUPT__: specifies the TIM interrupt source to disable.
Kojto	108:34e6b704fe68	1245	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1246	* @arg TIM_IT_UPDATE: Update interrupt
Kojto	108:34e6b704fe68	1247	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
Kojto	108:34e6b704fe68	1248	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
Kojto	108:34e6b704fe68	1249	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
Kojto	108:34e6b704fe68	1250	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
Kojto	108:34e6b704fe68	1251	* @arg TIM_IT_COM: Commutation interrupt
Kojto	108:34e6b704fe68	1252	* @arg TIM_IT_TRIGGER: Trigger interrupt
Kojto	108:34e6b704fe68	1253	* @arg TIM_IT_BREAK: Break interrupt
Kojto	108:34e6b704fe68	1254	* @retval None
Kojto	108:34e6b704fe68	1255	*/
bogdanm	92:4fc01daae5a5	1256	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Kojto	108:34e6b704fe68	1257
Kojto	108:34e6b704fe68	1258	/**
Kojto	108:34e6b704fe68	1259	* @brief Enables the specified DMA request.
Kojto	108:34e6b704fe68	1260	* @param __HANDLE__: specifies the TIM Handle.
Kojto	108:34e6b704fe68	1261	* @param __DMA__: specifies the TIM DMA request to enable.
Kojto	108:34e6b704fe68	1262	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1263	* @arg TIM_DMA_UPDATE: Update DMA request
Kojto	108:34e6b704fe68	1264	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
Kojto	108:34e6b704fe68	1265	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
Kojto	108:34e6b704fe68	1266	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
Kojto	108:34e6b704fe68	1267	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
Kojto	108:34e6b704fe68	1268	* @arg TIM_DMA_COM: Commutation DMA request
Kojto	108:34e6b704fe68	1269	* @arg TIM_DMA_TRIGGER: Trigger DMA request
Kojto	108:34e6b704fe68	1270	* @retval None
Kojto	108:34e6b704fe68	1271	*/
Kojto	108:34e6b704fe68	1272	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
Kojto	108:34e6b704fe68	1273
Kojto	108:34e6b704fe68	1274	/**
Kojto	108:34e6b704fe68	1275	* @brief Disables the specified DMA request.
Kojto	108:34e6b704fe68	1276	* @param __HANDLE__: specifies the TIM Handle.
Kojto	108:34e6b704fe68	1277	* @param __DMA__: specifies the TIM DMA request to disable.
Kojto	108:34e6b704fe68	1278	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1279	* @arg TIM_DMA_UPDATE: Update DMA request
Kojto	108:34e6b704fe68	1280	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
Kojto	108:34e6b704fe68	1281	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
Kojto	108:34e6b704fe68	1282	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
Kojto	108:34e6b704fe68	1283	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
Kojto	108:34e6b704fe68	1284	* @arg TIM_DMA_COM: Commutation DMA request
Kojto	108:34e6b704fe68	1285	* @arg TIM_DMA_TRIGGER: Trigger DMA request
Kojto	108:34e6b704fe68	1286	* @retval None
Kojto	108:34e6b704fe68	1287	*/
bogdanm	92:4fc01daae5a5	1288	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Kojto	108:34e6b704fe68	1289
Kojto	108:34e6b704fe68	1290	/**
Kojto	108:34e6b704fe68	1291	* @brief Checks whether the specified TIM interrupt flag is set or not.
Kojto	108:34e6b704fe68	1292	* @param __HANDLE__: specifies the TIM Handle.
Kojto	108:34e6b704fe68	1293	* @param __FLAG__: specifies the TIM interrupt flag to check.
Kojto	108:34e6b704fe68	1294	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1295	* @arg TIM_FLAG_UPDATE: Update interrupt flag
Kojto	108:34e6b704fe68	1296	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
Kojto	108:34e6b704fe68	1297	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
Kojto	108:34e6b704fe68	1298	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
Kojto	108:34e6b704fe68	1299	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
Kojto	108:34e6b704fe68	1300	* @arg TIM_FLAG_COM: Commutation interrupt flag
Kojto	108:34e6b704fe68	1301	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
Kojto	108:34e6b704fe68	1302	* @arg TIM_FLAG_BREAK: Break interrupt flag
Kojto	108:34e6b704fe68	1303	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
Kojto	108:34e6b704fe68	1304	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
Kojto	108:34e6b704fe68	1305	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
Kojto	108:34e6b704fe68	1306	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Kojto	108:34e6b704fe68	1307	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	108:34e6b704fe68	1308	*/
bogdanm	85:024bf7f99721	1309	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Kojto	108:34e6b704fe68	1310
Kojto	108:34e6b704fe68	1311	/**
Kojto	108:34e6b704fe68	1312	* @brief Clears the specified TIM interrupt flag.
Kojto	108:34e6b704fe68	1313	* @param __HANDLE__: specifies the TIM Handle.
Kojto	108:34e6b704fe68	1314	* @param __FLAG__: specifies the TIM interrupt flag to clear.
Kojto	108:34e6b704fe68	1315	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1316	* @arg TIM_FLAG_UPDATE: Update interrupt flag
Kojto	108:34e6b704fe68	1317	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
Kojto	108:34e6b704fe68	1318	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
Kojto	108:34e6b704fe68	1319	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
Kojto	108:34e6b704fe68	1320	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
Kojto	108:34e6b704fe68	1321	* @arg TIM_FLAG_COM: Commutation interrupt flag
Kojto	108:34e6b704fe68	1322	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
Kojto	108:34e6b704fe68	1323	* @arg TIM_FLAG_BREAK: Break interrupt flag
Kojto	108:34e6b704fe68	1324	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
Kojto	108:34e6b704fe68	1325	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
Kojto	108:34e6b704fe68	1326	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
Kojto	108:34e6b704fe68	1327	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Kojto	108:34e6b704fe68	1328	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	108:34e6b704fe68	1329	*/
bogdanm	92:4fc01daae5a5	1330	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm	85:024bf7f99721	1331
Kojto	108:34e6b704fe68	1332	/**
Kojto	108:34e6b704fe68	1333	* @brief Checks whether the specified TIM interrupt has occurred or not.
Kojto	108:34e6b704fe68	1334	* @param __HANDLE__: TIM handle
Kojto	108:34e6b704fe68	1335	* @param __INTERRUPT__: specifies the TIM interrupt source to check.
Kojto	108:34e6b704fe68	1336	* @retval The state of TIM_IT (SET or RESET).
Kojto	108:34e6b704fe68	1337	*/
Kojto	108:34e6b704fe68	1338	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Kojto	108:34e6b704fe68	1339
Kojto	108:34e6b704fe68	1340	/**
Kojto	108:34e6b704fe68	1341	* @brief Clear the TIM interrupt pending bits
Kojto	108:34e6b704fe68	1342	* @param __HANDLE__: TIM handle
Kojto	108:34e6b704fe68	1343	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	108:34e6b704fe68	1344	* @retval None
Kojto	108:34e6b704fe68	1345	*/
bogdanm	92:4fc01daae5a5	1346	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm	85:024bf7f99721	1347
Kojto	108:34e6b704fe68	1348	/**
Kojto	108:34e6b704fe68	1349	* @brief Indicates whether or not the TIM Counter is used as downcounter
Kojto	108:34e6b704fe68	1350	* @param __HANDLE__: TIM handle.
Kojto	108:34e6b704fe68	1351	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
Kojto	108:34e6b704fe68	1352	* @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
Kojto	108:34e6b704fe68	1353	mode.
Kojto	108:34e6b704fe68	1354	*/
Kojto	108:34e6b704fe68	1355	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm	85:024bf7f99721	1356
Kojto	108:34e6b704fe68	1357	/**
Kojto	108:34e6b704fe68	1358	* @brief Sets the TIM active prescaler register value on update event.
Kojto	108:34e6b704fe68	1359	* @param __HANDLE__: TIM handle.
Kojto	108:34e6b704fe68	1360	* @param __PRESC__: specifies the active prescaler register new value.
Kojto	108:34e6b704fe68	1361	* @retval None
Kojto	108:34e6b704fe68	1362	*/
Kojto	122:f9eeca106725	1363	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm	85:024bf7f99721	1364
bogdanm	85:024bf7f99721	1365	/**
bogdanm	85:024bf7f99721	1366	* @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm	85:024bf7f99721	1367	* calling another time ConfigChannel function.
bogdanm	85:024bf7f99721	1368	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1369	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	85:024bf7f99721	1370	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1371	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	85:024bf7f99721	1372	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	85:024bf7f99721	1373	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	85:024bf7f99721	1374	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	85:024bf7f99721	1375	* @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm	85:024bf7f99721	1376	* @retval None
bogdanm	85:024bf7f99721	1377	*/
Kojto	108:34e6b704fe68	1378	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
<>	134:ad3be0349dc5	1379	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
bogdanm	85:024bf7f99721	1380
bogdanm	85:024bf7f99721	1381	/**
bogdanm	85:024bf7f99721	1382	* @brief Gets the TIM Capture Compare Register value on runtime
bogdanm	85:024bf7f99721	1383	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1384	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm	85:024bf7f99721	1385	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1386	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm	85:024bf7f99721	1387	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm	85:024bf7f99721	1388	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm	85:024bf7f99721	1389	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm	85:024bf7f99721	1390	* @retval None
bogdanm	85:024bf7f99721	1391	*/
Kojto	108:34e6b704fe68	1392	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
<>	134:ad3be0349dc5	1393	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
bogdanm	85:024bf7f99721	1394
bogdanm	85:024bf7f99721	1395	/**
bogdanm	85:024bf7f99721	1396	* @brief Sets the TIM Counter Register value on runtime.
bogdanm	85:024bf7f99721	1397	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1398	* @param __COUNTER__: specifies the Counter register new value.
bogdanm	85:024bf7f99721	1399	* @retval None
bogdanm	85:024bf7f99721	1400	*/
Kojto	108:34e6b704fe68	1401	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm	85:024bf7f99721	1402
bogdanm	85:024bf7f99721	1403	/**
bogdanm	85:024bf7f99721	1404	* @brief Gets the TIM Counter Register value on runtime.
bogdanm	85:024bf7f99721	1405	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1406	* @retval None
bogdanm	85:024bf7f99721	1407	*/
Kojto	108:34e6b704fe68	1408	#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
bogdanm	85:024bf7f99721	1409	((__HANDLE__)->Instance->CNT)
Kojto	108:34e6b704fe68	1410
bogdanm	85:024bf7f99721	1411	/**
bogdanm	85:024bf7f99721	1412	* @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm	85:024bf7f99721	1413	* another time any Init function.
bogdanm	85:024bf7f99721	1414	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1415	* @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm	85:024bf7f99721	1416	* @retval None
bogdanm	85:024bf7f99721	1417	*/
Kojto	108:34e6b704fe68	1418	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
bogdanm	85:024bf7f99721	1419	do{ \
bogdanm	85:024bf7f99721	1420	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm	85:024bf7f99721	1421	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm	85:024bf7f99721	1422	} while(0)
bogdanm	85:024bf7f99721	1423
bogdanm	85:024bf7f99721	1424	/**
bogdanm	85:024bf7f99721	1425	* @brief Gets the TIM Autoreload Register value on runtime
bogdanm	85:024bf7f99721	1426	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1427	* @retval None
bogdanm	85:024bf7f99721	1428	*/
Kojto	108:34e6b704fe68	1429	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
bogdanm	85:024bf7f99721	1430	((__HANDLE__)->Instance->ARR)
Kojto	108:34e6b704fe68	1431
bogdanm	85:024bf7f99721	1432	/**
bogdanm	85:024bf7f99721	1433	* @brief Sets the TIM Clock Division value on runtime without calling
Kojto	108:34e6b704fe68	1434	* another time any Init function.
bogdanm	85:024bf7f99721	1435	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1436	* @param __CKD__: specifies the clock division value.
bogdanm	85:024bf7f99721	1437	* This parameter can be one of the following value:
bogdanm	85:024bf7f99721	1438	* @arg TIM_CLOCKDIVISION_DIV1
bogdanm	85:024bf7f99721	1439	* @arg TIM_CLOCKDIVISION_DIV2
Kojto	108:34e6b704fe68	1440	* @arg TIM_CLOCKDIVISION_DIV4
bogdanm	85:024bf7f99721	1441	* @retval None
bogdanm	85:024bf7f99721	1442	*/
Kojto	108:34e6b704fe68	1443	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
bogdanm	85:024bf7f99721	1444	do{ \
bogdanm	92:4fc01daae5a5	1445	(__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \
bogdanm	85:024bf7f99721	1446	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
bogdanm	85:024bf7f99721	1447	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm	85:024bf7f99721	1448	} while(0)
Kojto	108:34e6b704fe68	1449
bogdanm	85:024bf7f99721	1450	/**
bogdanm	85:024bf7f99721	1451	* @brief Gets the TIM Clock Division value on runtime
Kojto	108:34e6b704fe68	1452	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1453	* @retval None
bogdanm	85:024bf7f99721	1454	*/
Kojto	108:34e6b704fe68	1455	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
bogdanm	85:024bf7f99721	1456	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Kojto	108:34e6b704fe68	1457
bogdanm	85:024bf7f99721	1458	/**
<>	134:ad3be0349dc5	1459	* @brief Sets the TIM Output compare preload.
<>	134:ad3be0349dc5	1460	* @param __HANDLE__: TIM handle.
<>	134:ad3be0349dc5	1461	* @param __CHANNEL__: TIM Channels to be configured.
<>	134:ad3be0349dc5	1462	* This parameter can be one of the following values:
<>	134:ad3be0349dc5	1463	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	134:ad3be0349dc5	1464	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	134:ad3be0349dc5	1465	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	134:ad3be0349dc5	1466	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	134:ad3be0349dc5	1467	* @retval None
<>	134:ad3be0349dc5	1468	*/
<>	134:ad3be0349dc5	1469	#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
<>	134:ad3be0349dc5	1470	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1PE) :\
<>	134:ad3be0349dc5	1471	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2PE) :\
<>	134:ad3be0349dc5	1472	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3PE) :\
<>	134:ad3be0349dc5	1473	((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4PE))
<>	134:ad3be0349dc5	1474
<>	134:ad3be0349dc5	1475	/**
<>	134:ad3be0349dc5	1476	* @brief Resets the TIM Output compare preload.
<>	134:ad3be0349dc5	1477	* @param __HANDLE__: TIM handle.
<>	134:ad3be0349dc5	1478	* @param __CHANNEL__: TIM Channels to be configured.
<>	134:ad3be0349dc5	1479	* This parameter can be one of the following values:
<>	134:ad3be0349dc5	1480	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	134:ad3be0349dc5	1481	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	134:ad3be0349dc5	1482	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	134:ad3be0349dc5	1483	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	134:ad3be0349dc5	1484	* @retval None
<>	134:ad3be0349dc5	1485	*/
<>	134:ad3be0349dc5	1486	#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
<>	134:ad3be0349dc5	1487	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
<>	134:ad3be0349dc5	1488	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
<>	134:ad3be0349dc5	1489	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
<>	134:ad3be0349dc5	1490	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
<>	134:ad3be0349dc5	1491
<>	134:ad3be0349dc5	1492
<>	134:ad3be0349dc5	1493	/**
bogdanm	85:024bf7f99721	1494	* @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm	85:024bf7f99721	1495	* another time HAL_TIM_IC_ConfigChannel() function.
bogdanm	85:024bf7f99721	1496	* @param __HANDLE__: TIM handle.
bogdanm	85:024bf7f99721	1497	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	85:024bf7f99721	1498	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1499	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	85:024bf7f99721	1500	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	85:024bf7f99721	1501	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	85:024bf7f99721	1502	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	85:024bf7f99721	1503	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm	85:024bf7f99721	1504	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1505	* @arg TIM_ICPSC_DIV1: no prescaler
bogdanm	85:024bf7f99721	1506	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm	85:024bf7f99721	1507	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm	85:024bf7f99721	1508	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm	85:024bf7f99721	1509	* @retval None
bogdanm	85:024bf7f99721	1510	*/
Kojto	108:34e6b704fe68	1511	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	85:024bf7f99721	1512	do{ \
Kojto	108:34e6b704fe68	1513	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
Kojto	108:34e6b704fe68	1514	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
Kojto	108:34e6b704fe68	1515	} while(0)
bogdanm	85:024bf7f99721	1516
bogdanm	85:024bf7f99721	1517	/**
bogdanm	85:024bf7f99721	1518	* @brief Gets the TIM Input Capture prescaler on runtime
bogdanm	85:024bf7f99721	1519	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1520	* @param __CHANNEL__: TIM Channels to be configured.
bogdanm	85:024bf7f99721	1521	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1522	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm	85:024bf7f99721	1523	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm	85:024bf7f99721	1524	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm	85:024bf7f99721	1525	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm	85:024bf7f99721	1526	* @retval None
bogdanm	85:024bf7f99721	1527	*/
Kojto	108:34e6b704fe68	1528	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
bogdanm	85:024bf7f99721	1529	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
<>	134:ad3be0349dc5	1530	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
bogdanm	85:024bf7f99721	1531	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
<>	134:ad3be0349dc5	1532	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
Kojto	108:34e6b704fe68	1533
bogdanm	85:024bf7f99721	1534	/**
bogdanm	92:4fc01daae5a5	1535	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	92:4fc01daae5a5	1536	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1537	* @note When the USR bit of the TIMx_CR1 register is set, only counter
bogdanm	92:4fc01daae5a5	1538	* overflow/underflow generates an update interrupt or DMA request (if
bogdanm	92:4fc01daae5a5	1539	* enabled)
bogdanm	92:4fc01daae5a5	1540	* @retval None
bogdanm	92:4fc01daae5a5	1541	*/
bogdanm	92:4fc01daae5a5	1542	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
bogdanm	92:4fc01daae5a5	1543	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
bogdanm	92:4fc01daae5a5	1544
bogdanm	92:4fc01daae5a5	1545	/**
bogdanm	92:4fc01daae5a5	1546	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	92:4fc01daae5a5	1547	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1548	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
bogdanm	92:4fc01daae5a5	1549	* following events generate an update interrupt or DMA request (if
bogdanm	92:4fc01daae5a5	1550	* enabled):
bogdanm	92:4fc01daae5a5	1551	* (+) Counter overflow/underflow
bogdanm	92:4fc01daae5a5	1552	* (+) Setting the UG bit
bogdanm	92:4fc01daae5a5	1553	* (+) Update generation through the slave mode controller
bogdanm	92:4fc01daae5a5	1554	* @retval None
bogdanm	92:4fc01daae5a5	1555	*/
bogdanm	92:4fc01daae5a5	1556	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
bogdanm	92:4fc01daae5a5	1557	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
bogdanm	92:4fc01daae5a5	1558
bogdanm	92:4fc01daae5a5	1559	/**
Kojto	108:34e6b704fe68	1560	* @brief Sets the TIM Capture x input polarity on runtime.
Kojto	108:34e6b704fe68	1561	* @param __HANDLE__: TIM handle.
Kojto	108:34e6b704fe68	1562	* @param __CHANNEL__: TIM Channels to be configured.
Kojto	108:34e6b704fe68	1563	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1564	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
Kojto	108:34e6b704fe68	1565	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
Kojto	108:34e6b704fe68	1566	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
Kojto	108:34e6b704fe68	1567	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
Kojto	108:34e6b704fe68	1568	* @param __POLARITY__: Polarity for TIx source
Kojto	108:34e6b704fe68	1569	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
Kojto	108:34e6b704fe68	1570	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
Kojto	108:34e6b704fe68	1571	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Kojto	108:34e6b704fe68	1572	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
Kojto	108:34e6b704fe68	1573	* @retval None
Kojto	108:34e6b704fe68	1574	*/
Kojto	108:34e6b704fe68	1575	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
Kojto	108:34e6b704fe68	1576	do{ \
Kojto	108:34e6b704fe68	1577	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
Kojto	108:34e6b704fe68	1578	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
Kojto	108:34e6b704fe68	1579	}while(0)
Kojto	108:34e6b704fe68	1580
Kojto	108:34e6b704fe68	1581	/**
bogdanm	85:024bf7f99721	1582	* @}
bogdanm	85:024bf7f99721	1583	*/
bogdanm	85:024bf7f99721	1584
bogdanm	85:024bf7f99721	1585	/* Include TIM HAL Extension module */
bogdanm	85:024bf7f99721	1586	#include "stm32f0xx_hal_tim_ex.h"
bogdanm	85:024bf7f99721	1587
bogdanm	85:024bf7f99721	1588	/* Exported functions --------------------------------------------------------*/
Kojto	108:34e6b704fe68	1589	/** @addtogroup TIM_Exported_Functions
bogdanm	92:4fc01daae5a5	1590	* @{
bogdanm	92:4fc01daae5a5	1591	*/
bogdanm	85:024bf7f99721	1592
Kojto	108:34e6b704fe68	1593	/** @addtogroup TIM_Exported_Functions_Group1
bogdanm	92:4fc01daae5a5	1594	* @{
bogdanm	92:4fc01daae5a5	1595	*/
bogdanm	85:024bf7f99721	1596	/* Time Base functions ********************************************************/
bogdanm	85:024bf7f99721	1597	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1598	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1599	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1600	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1601	/* Blocking mode: Polling */
bogdanm	85:024bf7f99721	1602	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1603	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1604	/* Non-Blocking mode: Interrupt */
bogdanm	85:024bf7f99721	1605	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1606	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1607	/* Non-Blocking mode: DMA */
bogdanm	85:024bf7f99721	1608	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
bogdanm	85:024bf7f99721	1609	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1610	/**
bogdanm	92:4fc01daae5a5	1611	* @}
bogdanm	92:4fc01daae5a5	1612	*/
bogdanm	85:024bf7f99721	1613
Kojto	108:34e6b704fe68	1614	/** @addtogroup TIM_Exported_Functions_Group2
bogdanm	92:4fc01daae5a5	1615	* @{
bogdanm	92:4fc01daae5a5	1616	*/
bogdanm	85:024bf7f99721	1617	/* Timer Output Compare functions **********************************************/
bogdanm	85:024bf7f99721	1618	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1619	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1620	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1621	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1622	/* Blocking mode: Polling */
bogdanm	85:024bf7f99721	1623	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1624	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1625	/* Non-Blocking mode: Interrupt */
bogdanm	85:024bf7f99721	1626	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1627	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1628	/* Non-Blocking mode: DMA */
bogdanm	85:024bf7f99721	1629	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	85:024bf7f99721	1630	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
Kojto	108:34e6b704fe68	1631
bogdanm	92:4fc01daae5a5	1632	/**
bogdanm	92:4fc01daae5a5	1633	* @}
bogdanm	92:4fc01daae5a5	1634	*/
bogdanm	85:024bf7f99721	1635
Kojto	108:34e6b704fe68	1636	/** @addtogroup TIM_Exported_Functions_Group3
bogdanm	92:4fc01daae5a5	1637	* @{
bogdanm	92:4fc01daae5a5	1638	*/
bogdanm	85:024bf7f99721	1639	/* Timer PWM functions *********************************************************/
bogdanm	85:024bf7f99721	1640	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1641	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1642	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1643	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1644	/* Blocking mode: Polling */
bogdanm	85:024bf7f99721	1645	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1646	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1647	/* Non-Blocking mode: Interrupt */
bogdanm	85:024bf7f99721	1648	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1649	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1650	/* Non-Blocking mode: DMA */
bogdanm	85:024bf7f99721	1651	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	85:024bf7f99721	1652	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1653	/**
bogdanm	92:4fc01daae5a5	1654	* @}
bogdanm	92:4fc01daae5a5	1655	*/
bogdanm	85:024bf7f99721	1656
Kojto	108:34e6b704fe68	1657	/** @addtogroup TIM_Exported_Functions_Group4
bogdanm	92:4fc01daae5a5	1658	* @{
bogdanm	92:4fc01daae5a5	1659	*/
bogdanm	85:024bf7f99721	1660	/* Timer Input Capture functions ***********************************************/
bogdanm	85:024bf7f99721	1661	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1662	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1663	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1664	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1665	/* Blocking mode: Polling */
bogdanm	85:024bf7f99721	1666	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1667	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1668	/* Non-Blocking mode: Interrupt */
bogdanm	85:024bf7f99721	1669	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1670	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1671	/* Non-Blocking mode: DMA */
bogdanm	85:024bf7f99721	1672	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	85:024bf7f99721	1673	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1674	/**
bogdanm	92:4fc01daae5a5	1675	* @}
bogdanm	92:4fc01daae5a5	1676	*/
bogdanm	85:024bf7f99721	1677
Kojto	108:34e6b704fe68	1678	/** @addtogroup TIM_Exported_Functions_Group5
bogdanm	92:4fc01daae5a5	1679	* @{
bogdanm	92:4fc01daae5a5	1680	*/
bogdanm	85:024bf7f99721	1681	/* Timer One Pulse functions ***************************************************/
bogdanm	85:024bf7f99721	1682	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm	85:024bf7f99721	1683	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1684	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1685	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1686	/* Blocking mode: Polling */
bogdanm	85:024bf7f99721	1687	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	85:024bf7f99721	1688	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	85:024bf7f99721	1689	/* Non-Blocking mode: Interrupt */
bogdanm	85:024bf7f99721	1690	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	85:024bf7f99721	1691	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	92:4fc01daae5a5	1692	/**
bogdanm	92:4fc01daae5a5	1693	* @}
bogdanm	92:4fc01daae5a5	1694	*/
bogdanm	85:024bf7f99721	1695
Kojto	108:34e6b704fe68	1696	/** @addtogroup TIM_Exported_Functions_Group6
bogdanm	92:4fc01daae5a5	1697	* @{
bogdanm	92:4fc01daae5a5	1698	*/
bogdanm	85:024bf7f99721	1699	/* Timer Encoder functions *****************************************************/
bogdanm	85:024bf7f99721	1700	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
bogdanm	85:024bf7f99721	1701	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1702	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1703	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1704	/* Blocking mode: Polling */
bogdanm	85:024bf7f99721	1705	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1706	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1707	/* Non-Blocking mode: Interrupt */
bogdanm	85:024bf7f99721	1708	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1709	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	85:024bf7f99721	1710	/* Non-Blocking mode: DMA */
bogdanm	85:024bf7f99721	1711	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
bogdanm	85:024bf7f99721	1712	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
Kojto	108:34e6b704fe68	1713
bogdanm	92:4fc01daae5a5	1714	/**
bogdanm	92:4fc01daae5a5	1715	* @}
bogdanm	92:4fc01daae5a5	1716	*/
bogdanm	85:024bf7f99721	1717
Kojto	108:34e6b704fe68	1718	/** @addtogroup TIM_Exported_Functions_Group7
bogdanm	92:4fc01daae5a5	1719	* @{
bogdanm	92:4fc01daae5a5	1720	*/
bogdanm	85:024bf7f99721	1721	/* Interrupt Handler functions **********************************************/
bogdanm	85:024bf7f99721	1722	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1723	/**
bogdanm	92:4fc01daae5a5	1724	* @}
bogdanm	92:4fc01daae5a5	1725	*/
bogdanm	85:024bf7f99721	1726
Kojto	108:34e6b704fe68	1727	/** @addtogroup TIM_Exported_Functions_Group8
bogdanm	92:4fc01daae5a5	1728	* @{
bogdanm	92:4fc01daae5a5	1729	*/
bogdanm	85:024bf7f99721	1730	/* Control functions *********************************************************/
bogdanm	85:024bf7f99721	1731	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	85:024bf7f99721	1732	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	85:024bf7f99721	1733	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	85:024bf7f99721	1734	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm	85:024bf7f99721	1735	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
bogdanm	85:024bf7f99721	1736	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
bogdanm	85:024bf7f99721	1737	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm	85:024bf7f99721	1738	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	92:4fc01daae5a5	1739	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	85:024bf7f99721	1740	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	85:024bf7f99721	1741	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	85:024bf7f99721	1742	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	85:024bf7f99721	1743	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	85:024bf7f99721	1744	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	85:024bf7f99721	1745	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	85:024bf7f99721	1746	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm	85:024bf7f99721	1747	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
Kojto	108:34e6b704fe68	1748
bogdanm	92:4fc01daae5a5	1749	/**
bogdanm	92:4fc01daae5a5	1750	* @}
bogdanm	92:4fc01daae5a5	1751	*/
bogdanm	85:024bf7f99721	1752
bogdanm	92:4fc01daae5a5	1753	/** @addtogroup TIM_Exported_Functions_Group9
bogdanm	92:4fc01daae5a5	1754	* @{
bogdanm	92:4fc01daae5a5	1755	*/
bogdanm	85:024bf7f99721	1756	/* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm	85:024bf7f99721	1757	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1758	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1759	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1760	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1761	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1762	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1763	/**
bogdanm	92:4fc01daae5a5	1764	* @}
bogdanm	92:4fc01daae5a5	1765	*/
bogdanm	85:024bf7f99721	1766
bogdanm	92:4fc01daae5a5	1767	/** @addtogroup TIM_Exported_Functions_Group10
bogdanm	92:4fc01daae5a5	1768	* @{
bogdanm	92:4fc01daae5a5	1769	*/
bogdanm	85:024bf7f99721	1770	/* Peripheral State functions **************************************************/
bogdanm	85:024bf7f99721	1771	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1772	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1773	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1774	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1775	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm	85:024bf7f99721	1776	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
Kojto	108:34e6b704fe68	1777
bogdanm	92:4fc01daae5a5	1778	/**
bogdanm	92:4fc01daae5a5	1779	* @}
bogdanm	92:4fc01daae5a5	1780	*/
bogdanm	85:024bf7f99721	1781
bogdanm	92:4fc01daae5a5	1782	/**
bogdanm	92:4fc01daae5a5	1783	* @}
bogdanm	92:4fc01daae5a5	1784	*/
bogdanm	92:4fc01daae5a5	1785
Kojto	122:f9eeca106725	1786	/* Private Functions --------------------------------------------------------*/
Kojto	122:f9eeca106725	1787	/** @addtogroup TIM_Private_Functions
Kojto	122:f9eeca106725	1788	* @{
Kojto	122:f9eeca106725	1789	*/
Kojto	122:f9eeca106725	1790	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
Kojto	122:f9eeca106725	1791	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
Kojto	122:f9eeca106725	1792	/**
Kojto	122:f9eeca106725	1793	* @}
Kojto	122:f9eeca106725	1794	*/
Kojto	122:f9eeca106725	1795
bogdanm	92:4fc01daae5a5	1796	/**
bogdanm	92:4fc01daae5a5	1797	* @}
bogdanm	92:4fc01daae5a5	1798	*/
bogdanm	85:024bf7f99721	1799
bogdanm	85:024bf7f99721	1800	/**
bogdanm	85:024bf7f99721	1801	* @}
bogdanm	92:4fc01daae5a5	1802	*/
bogdanm	92:4fc01daae5a5	1803
bogdanm	85:024bf7f99721	1804	#ifdef __cplusplus
bogdanm	85:024bf7f99721	1805	}
bogdanm	85:024bf7f99721	1806	#endif
bogdanm	85:024bf7f99721	1807
bogdanm	85:024bf7f99721	1808	#endif /* __STM32F0xx_HAL_TIM_H */
bogdanm	85:024bf7f99721	1809
bogdanm	85:024bf7f99721	1810	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/