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mbed 2

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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
134:ad3be0349dc5 
Release 143 of the mbed library.

Who changed what in which revision?

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<> 134:ad3be0349dc5 1 /**
bogdanm 85:024bf7f99721 2 ******************************************************************************
bogdanm 85:024bf7f99721 3 * @file stm32f0xx_hal_spi.h
bogdanm 85:024bf7f99721 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.5.0
<> 134:ad3be0349dc5 6 * @date 04-November-2016
bogdanm 85:024bf7f99721 7 * @brief Header file of SPI HAL module.
bogdanm 85:024bf7f99721 8 ******************************************************************************
bogdanm 85:024bf7f99721 9 * @attention
bogdanm 85:024bf7f99721 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 85:024bf7f99721 12 *
bogdanm 85:024bf7f99721 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 85:024bf7f99721 14 * are permitted provided that the following conditions are met:
bogdanm 85:024bf7f99721 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 85:024bf7f99721 16 * this list of conditions and the following disclaimer.
bogdanm 85:024bf7f99721 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 85:024bf7f99721 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 85:024bf7f99721 19 * and/or other materials provided with the distribution.
bogdanm 85:024bf7f99721 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 85:024bf7f99721 21 * may be used to endorse or promote products derived from this software
bogdanm 85:024bf7f99721 22 * without specific prior written permission.
bogdanm 85:024bf7f99721 23 *
bogdanm 85:024bf7f99721 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 85:024bf7f99721 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 85:024bf7f99721 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 85:024bf7f99721 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 85:024bf7f99721 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 85:024bf7f99721 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 85:024bf7f99721 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 85:024bf7f99721 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 85:024bf7f99721 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 85:024bf7f99721 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 85:024bf7f99721 34 *
Kojto 108:34e6b704fe68 35 ******************************************************************************
bogdanm 85:024bf7f99721 36 */
bogdanm 85:024bf7f99721 37
bogdanm 85:024bf7f99721 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 85:024bf7f99721 39 #ifndef __STM32F0xx_HAL_SPI_H
bogdanm 85:024bf7f99721 40 #define __STM32F0xx_HAL_SPI_H
bogdanm 85:024bf7f99721 41
bogdanm 85:024bf7f99721 42 #ifdef __cplusplus
<> 134:ad3be0349dc5 43 extern "C" {
bogdanm 85:024bf7f99721 44 #endif
bogdanm 85:024bf7f99721 45
bogdanm 85:024bf7f99721 46 /* Includes ------------------------------------------------------------------*/
bogdanm 85:024bf7f99721 47 #include "stm32f0xx_hal_def.h"
bogdanm 85:024bf7f99721 48
bogdanm 85:024bf7f99721 49 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 85:024bf7f99721 50 * @{
bogdanm 85:024bf7f99721 51 */
bogdanm 85:024bf7f99721 52
bogdanm 85:024bf7f99721 53 /** @addtogroup SPI
bogdanm 85:024bf7f99721 54 * @{
Kojto 108:34e6b704fe68 55 */
bogdanm 85:024bf7f99721 56
Kojto 108:34e6b704fe68 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58 /** @defgroup SPI_Exported_Types SPI Exported Types
bogdanm 92:4fc01daae5a5 59 * @{
bogdanm 92:4fc01daae5a5 60 */
bogdanm 85:024bf7f99721 61
Kojto 108:34e6b704fe68 62 /**
Kojto 108:34e6b704fe68 63 * @brief SPI Configuration Structure definition
bogdanm 85:024bf7f99721 64 */
bogdanm 85:024bf7f99721 65 typedef struct
bogdanm 85:024bf7f99721 66 {
bogdanm 85:024bf7f99721 67 uint32_t Mode; /*!< Specifies the SPI operating mode.
Kojto 108:34e6b704fe68 68 This parameter can be a value of @ref SPI_Mode */
bogdanm 85:024bf7f99721 69
bogdanm 85:024bf7f99721 70 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
bogdanm 85:024bf7f99721 71 This parameter can be a value of @ref SPI_Direction */
bogdanm 85:024bf7f99721 72
bogdanm 85:024bf7f99721 73 uint32_t DataSize; /*!< Specifies the SPI data size.
Kojto 108:34e6b704fe68 74 This parameter can be a value of @ref SPI_Data_Size */
bogdanm 85:024bf7f99721 75
bogdanm 85:024bf7f99721 76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
bogdanm 85:024bf7f99721 77 This parameter can be a value of @ref SPI_Clock_Polarity */
bogdanm 85:024bf7f99721 78
bogdanm 85:024bf7f99721 79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
bogdanm 85:024bf7f99721 80 This parameter can be a value of @ref SPI_Clock_Phase */
bogdanm 85:024bf7f99721 81
bogdanm 85:024bf7f99721 82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
bogdanm 85:024bf7f99721 83 hardware (NSS pin) or by software using the SSI bit.
bogdanm 85:024bf7f99721 84 This parameter can be a value of @ref SPI_Slave_Select_management */
bogdanm 85:024bf7f99721 85
bogdanm 85:024bf7f99721 86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
bogdanm 85:024bf7f99721 87 used to configure the transmit and receive SCK clock.
bogdanm 85:024bf7f99721 88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
bogdanm 85:024bf7f99721 89 @note The communication clock is derived from the master
bogdanm 85:024bf7f99721 90 clock. The slave clock does not need to be set. */
bogdanm 85:024bf7f99721 91
bogdanm 85:024bf7f99721 92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
bogdanm 85:024bf7f99721 93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
Kojto 108:34e6b704fe68 94
<> 134:ad3be0349dc5 95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
bogdanm 85:024bf7f99721 96 This parameter can be a value of @ref SPI_TI_mode */
bogdanm 85:024bf7f99721 97
bogdanm 85:024bf7f99721 98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
bogdanm 85:024bf7f99721 99 This parameter can be a value of @ref SPI_CRC_Calculation */
bogdanm 85:024bf7f99721 100
bogdanm 85:024bf7f99721 101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
Kojto 122:f9eeca106725 102 This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
bogdanm 85:024bf7f99721 103
Kojto 108:34e6b704fe68 104 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
Kojto 108:34e6b704fe68 105 CRC Length is only used with Data8 and Data16, not other data size
Kojto 108:34e6b704fe68 106 This parameter can be a value of @ref SPI_CRC_length */
bogdanm 85:024bf7f99721 107
bogdanm 85:024bf7f99721 108 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
Kojto 93:e188a91d3eaa 109 This parameter can be a value of @ref SPI_NSSP_Mode
Kojto 108:34e6b704fe68 110 This mode is activated by the NSSP bit in the SPIx_CR2 register and
Kojto 108:34e6b704fe68 111 it takes effect only if the SPI interface is configured as Motorola SPI
Kojto 108:34e6b704fe68 112 master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
bogdanm 85:024bf7f99721 113 CPOL setting is ignored).. */
bogdanm 85:024bf7f99721 114 } SPI_InitTypeDef;
bogdanm 85:024bf7f99721 115
Kojto 108:34e6b704fe68 116 /**
<> 134:ad3be0349dc5 117 * @brief HAL SPI State structure definition
Kojto 108:34e6b704fe68 118 */
bogdanm 85:024bf7f99721 119 typedef enum
bogdanm 85:024bf7f99721 120 {
<> 134:ad3be0349dc5 121 HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
<> 134:ad3be0349dc5 122 HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
<> 134:ad3be0349dc5 123 HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
<> 134:ad3be0349dc5 124 HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
<> 134:ad3be0349dc5 125 HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
<> 134:ad3be0349dc5 126 HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
<> 134:ad3be0349dc5 127 HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
<> 134:ad3be0349dc5 128 HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
<> 134:ad3be0349dc5 129 } HAL_SPI_StateTypeDef;
bogdanm 85:024bf7f99721 130
Kojto 108:34e6b704fe68 131 /**
Kojto 108:34e6b704fe68 132 * @brief SPI handle Structure definition
Kojto 108:34e6b704fe68 133 */
bogdanm 85:024bf7f99721 134 typedef struct __SPI_HandleTypeDef
bogdanm 85:024bf7f99721 135 {
Kojto 122:f9eeca106725 136 SPI_TypeDef *Instance; /*!< SPI registers base address */
Kojto 108:34e6b704fe68 137
Kojto 122:f9eeca106725 138 SPI_InitTypeDef Init; /*!< SPI communication parameters */
Kojto 108:34e6b704fe68 139
Kojto 122:f9eeca106725 140 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
Kojto 108:34e6b704fe68 141
Kojto 122:f9eeca106725 142 uint16_t TxXferSize; /*!< SPI Tx Transfer size */
Kojto 108:34e6b704fe68 143
Kojto 122:f9eeca106725 144 __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
Kojto 108:34e6b704fe68 145
Kojto 122:f9eeca106725 146 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
Kojto 108:34e6b704fe68 147
Kojto 122:f9eeca106725 148 uint16_t RxXferSize; /*!< SPI Rx Transfer size */
Kojto 108:34e6b704fe68 149
Kojto 122:f9eeca106725 150 __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
bogdanm 85:024bf7f99721 151
Kojto 122:f9eeca106725 152 uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
Kojto 108:34e6b704fe68 153
<> 134:ad3be0349dc5 154 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
Kojto 108:34e6b704fe68 155
<> 134:ad3be0349dc5 156 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
Kojto 108:34e6b704fe68 157
Kojto 122:f9eeca106725 158 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
bogdanm 85:024bf7f99721 159
Kojto 122:f9eeca106725 160 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
bogdanm 85:024bf7f99721 161
Kojto 122:f9eeca106725 162 HAL_LockTypeDef Lock; /*!< Locking object */
bogdanm 85:024bf7f99721 163
Kojto 122:f9eeca106725 164 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
bogdanm 85:024bf7f99721 165
Kojto 122:f9eeca106725 166 __IO uint32_t ErrorCode; /*!< SPI Error code */
bogdanm 85:024bf7f99721 167
<> 134:ad3be0349dc5 168 } SPI_HandleTypeDef;
bogdanm 85:024bf7f99721 169
bogdanm 92:4fc01daae5a5 170 /**
bogdanm 92:4fc01daae5a5 171 * @}
Kojto 108:34e6b704fe68 172 */
bogdanm 92:4fc01daae5a5 173
bogdanm 85:024bf7f99721 174 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 175 /** @defgroup SPI_Exported_Constants SPI Exported Constants
bogdanm 85:024bf7f99721 176 * @{
bogdanm 85:024bf7f99721 177 */
bogdanm 85:024bf7f99721 178
Kojto 108:34e6b704fe68 179 /** @defgroup SPI_Error_Code SPI Error Code
Kojto 93:e188a91d3eaa 180 * @{
Kojto 108:34e6b704fe68 181 */
<> 134:ad3be0349dc5 182 #define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
<> 134:ad3be0349dc5 183 #define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
<> 134:ad3be0349dc5 184 #define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
<> 134:ad3be0349dc5 185 #define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
<> 134:ad3be0349dc5 186 #define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
<> 134:ad3be0349dc5 187 #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
<> 134:ad3be0349dc5 188 #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
<> 134:ad3be0349dc5 189 #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
Kojto 93:e188a91d3eaa 190 /**
Kojto 93:e188a91d3eaa 191 * @}
Kojto 93:e188a91d3eaa 192 */
Kojto 93:e188a91d3eaa 193
Kojto 108:34e6b704fe68 194 /** @defgroup SPI_Mode SPI Mode
bogdanm 85:024bf7f99721 195 * @{
Kojto 108:34e6b704fe68 196 */
<> 134:ad3be0349dc5 197 #define SPI_MODE_SLAVE (0x00000000U)
bogdanm 85:024bf7f99721 198 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
bogdanm 85:024bf7f99721 199 /**
bogdanm 85:024bf7f99721 200 * @}
bogdanm 85:024bf7f99721 201 */
bogdanm 85:024bf7f99721 202
Kojto 108:34e6b704fe68 203 /** @defgroup SPI_Direction SPI Direction Mode
bogdanm 85:024bf7f99721 204 * @{
bogdanm 85:024bf7f99721 205 */
<> 134:ad3be0349dc5 206 #define SPI_DIRECTION_2LINES (0x00000000U)
Kojto 108:34e6b704fe68 207 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
Kojto 108:34e6b704fe68 208 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
bogdanm 85:024bf7f99721 209 /**
bogdanm 85:024bf7f99721 210 * @}
bogdanm 85:024bf7f99721 211 */
Kojto 108:34e6b704fe68 212
Kojto 108:34e6b704fe68 213 /** @defgroup SPI_Data_Size SPI Data Size
bogdanm 85:024bf7f99721 214 * @{
bogdanm 85:024bf7f99721 215 */
<> 134:ad3be0349dc5 216 #define SPI_DATASIZE_4BIT (0x00000300U)
<> 134:ad3be0349dc5 217 #define SPI_DATASIZE_5BIT (0x00000400U)
<> 134:ad3be0349dc5 218 #define SPI_DATASIZE_6BIT (0x00000500U)
<> 134:ad3be0349dc5 219 #define SPI_DATASIZE_7BIT (0x00000600U)
<> 134:ad3be0349dc5 220 #define SPI_DATASIZE_8BIT (0x00000700U)
<> 134:ad3be0349dc5 221 #define SPI_DATASIZE_9BIT (0x00000800U)
<> 134:ad3be0349dc5 222 #define SPI_DATASIZE_10BIT (0x00000900U)
<> 134:ad3be0349dc5 223 #define SPI_DATASIZE_11BIT (0x00000A00U)
<> 134:ad3be0349dc5 224 #define SPI_DATASIZE_12BIT (0x00000B00U)
<> 134:ad3be0349dc5 225 #define SPI_DATASIZE_13BIT (0x00000C00U)
<> 134:ad3be0349dc5 226 #define SPI_DATASIZE_14BIT (0x00000D00U)
<> 134:ad3be0349dc5 227 #define SPI_DATASIZE_15BIT (0x00000E00U)
<> 134:ad3be0349dc5 228 #define SPI_DATASIZE_16BIT (0x00000F00U)
bogdanm 85:024bf7f99721 229 /**
bogdanm 85:024bf7f99721 230 * @}
Kojto 108:34e6b704fe68 231 */
bogdanm 85:024bf7f99721 232
bogdanm 92:4fc01daae5a5 233 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
bogdanm 85:024bf7f99721 234 * @{
Kojto 108:34e6b704fe68 235 */
<> 134:ad3be0349dc5 236 #define SPI_POLARITY_LOW (0x00000000U)
<> 134:ad3be0349dc5 237 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
bogdanm 85:024bf7f99721 238 /**
bogdanm 85:024bf7f99721 239 * @}
bogdanm 85:024bf7f99721 240 */
bogdanm 85:024bf7f99721 241
bogdanm 92:4fc01daae5a5 242 /** @defgroup SPI_Clock_Phase SPI Clock Phase
bogdanm 85:024bf7f99721 243 * @{
bogdanm 85:024bf7f99721 244 */
<> 134:ad3be0349dc5 245 #define SPI_PHASE_1EDGE (0x00000000U)
<> 134:ad3be0349dc5 246 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
bogdanm 85:024bf7f99721 247 /**
bogdanm 85:024bf7f99721 248 * @}
bogdanm 85:024bf7f99721 249 */
bogdanm 85:024bf7f99721 250
<> 134:ad3be0349dc5 251 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
bogdanm 85:024bf7f99721 252 * @{
Kojto 108:34e6b704fe68 253 */
bogdanm 85:024bf7f99721 254 #define SPI_NSS_SOFT SPI_CR1_SSM
<> 134:ad3be0349dc5 255 #define SPI_NSS_HARD_INPUT (0x00000000U)
<> 134:ad3be0349dc5 256 #define SPI_NSS_HARD_OUTPUT (0x00040000U)
bogdanm 92:4fc01daae5a5 257 /**
bogdanm 85:024bf7f99721 258 * @}
bogdanm 85:024bf7f99721 259 */
Kojto 108:34e6b704fe68 260
Kojto 108:34e6b704fe68 261 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
bogdanm 85:024bf7f99721 262 * @{
Kojto 108:34e6b704fe68 263 */
Kojto 108:34e6b704fe68 264 #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
<> 134:ad3be0349dc5 265 #define SPI_NSS_PULSE_DISABLE (0x00000000U)
bogdanm 85:024bf7f99721 266 /**
bogdanm 85:024bf7f99721 267 * @}
bogdanm 85:024bf7f99721 268 */
Kojto 108:34e6b704fe68 269
bogdanm 92:4fc01daae5a5 270 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
bogdanm 85:024bf7f99721 271 * @{
bogdanm 85:024bf7f99721 272 */
<> 134:ad3be0349dc5 273 #define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
<> 134:ad3be0349dc5 274 #define SPI_BAUDRATEPRESCALER_4 (0x00000008U)
<> 134:ad3be0349dc5 275 #define SPI_BAUDRATEPRESCALER_8 (0x00000010U)
<> 134:ad3be0349dc5 276 #define SPI_BAUDRATEPRESCALER_16 (0x00000018U)
<> 134:ad3be0349dc5 277 #define SPI_BAUDRATEPRESCALER_32 (0x00000020U)
<> 134:ad3be0349dc5 278 #define SPI_BAUDRATEPRESCALER_64 (0x00000028U)
<> 134:ad3be0349dc5 279 #define SPI_BAUDRATEPRESCALER_128 (0x00000030U)
<> 134:ad3be0349dc5 280 #define SPI_BAUDRATEPRESCALER_256 (0x00000038U)
bogdanm 85:024bf7f99721 281 /**
bogdanm 85:024bf7f99721 282 * @}
Kojto 108:34e6b704fe68 283 */
bogdanm 85:024bf7f99721 284
<> 134:ad3be0349dc5 285 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
bogdanm 85:024bf7f99721 286 * @{
Kojto 108:34e6b704fe68 287 */
<> 134:ad3be0349dc5 288 #define SPI_FIRSTBIT_MSB (0x00000000U)
bogdanm 85:024bf7f99721 289 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
bogdanm 85:024bf7f99721 290 /**
bogdanm 85:024bf7f99721 291 * @}
bogdanm 85:024bf7f99721 292 */
bogdanm 85:024bf7f99721 293
<> 134:ad3be0349dc5 294 /** @defgroup SPI_TI_mode SPI TI Mode
bogdanm 85:024bf7f99721 295 * @{
bogdanm 85:024bf7f99721 296 */
<> 134:ad3be0349dc5 297 #define SPI_TIMODE_DISABLE (0x00000000U)
Kojto 108:34e6b704fe68 298 #define SPI_TIMODE_ENABLE SPI_CR2_FRF
bogdanm 85:024bf7f99721 299 /**
bogdanm 85:024bf7f99721 300 * @}
bogdanm 85:024bf7f99721 301 */
bogdanm 85:024bf7f99721 302
Kojto 108:34e6b704fe68 303 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
Kojto 108:34e6b704fe68 304 * @{
Kojto 108:34e6b704fe68 305 */
<> 134:ad3be0349dc5 306 #define SPI_CRCCALCULATION_DISABLE (0x00000000U)
Kojto 108:34e6b704fe68 307 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
Kojto 108:34e6b704fe68 308 /**
Kojto 108:34e6b704fe68 309 * @}
Kojto 108:34e6b704fe68 310 */
Kojto 108:34e6b704fe68 311
Kojto 108:34e6b704fe68 312 /** @defgroup SPI_CRC_length SPI CRC Length
bogdanm 85:024bf7f99721 313 * @{
bogdanm 85:024bf7f99721 314 * This parameter can be one of the following values:
Kojto 108:34e6b704fe68 315 * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
bogdanm 85:024bf7f99721 316 * SPI_CRC_LENGTH_8BIT : CRC 8bit
Kojto 108:34e6b704fe68 317 * SPI_CRC_LENGTH_16BIT : CRC 16bit
bogdanm 85:024bf7f99721 318 */
<> 134:ad3be0349dc5 319 #define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
<> 134:ad3be0349dc5 320 #define SPI_CRC_LENGTH_8BIT (0x00000001U)
<> 134:ad3be0349dc5 321 #define SPI_CRC_LENGTH_16BIT (0x00000002U)
bogdanm 85:024bf7f99721 322 /**
bogdanm 85:024bf7f99721 323 * @}
bogdanm 85:024bf7f99721 324 */
Kojto 108:34e6b704fe68 325
Kojto 108:34e6b704fe68 326 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
bogdanm 85:024bf7f99721 327 * @{
bogdanm 85:024bf7f99721 328 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 329 * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
Kojto 108:34e6b704fe68 330 * RXNE event is generated if the FIFO
Kojto 108:34e6b704fe68 331 * level is greater or equal to 1/2(16-bits).
Kojto 108:34e6b704fe68 332 * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
Kojto 93:e188a91d3eaa 333 * level is greater or equal to 1/4(8 bits). */
Kojto 108:34e6b704fe68 334 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
Kojto 108:34e6b704fe68 335 #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
<> 134:ad3be0349dc5 336 #define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
bogdanm 85:024bf7f99721 337
bogdanm 85:024bf7f99721 338 /**
bogdanm 85:024bf7f99721 339 * @}
bogdanm 85:024bf7f99721 340 */
bogdanm 85:024bf7f99721 341
<> 134:ad3be0349dc5 342 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
Kojto 93:e188a91d3eaa 343 * @{
Kojto 93:e188a91d3eaa 344 */
bogdanm 85:024bf7f99721 345 #define SPI_IT_TXE SPI_CR2_TXEIE
bogdanm 85:024bf7f99721 346 #define SPI_IT_RXNE SPI_CR2_RXNEIE
bogdanm 85:024bf7f99721 347 #define SPI_IT_ERR SPI_CR2_ERRIE
bogdanm 85:024bf7f99721 348 /**
bogdanm 85:024bf7f99721 349 * @}
bogdanm 85:024bf7f99721 350 */
bogdanm 85:024bf7f99721 351
<> 134:ad3be0349dc5 352 /** @defgroup SPI_Flags_definition SPI Flags Definition
Kojto 108:34e6b704fe68 353 * @{
Kojto 108:34e6b704fe68 354 */
<> 134:ad3be0349dc5 355 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
<> 134:ad3be0349dc5 356 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
<> 134:ad3be0349dc5 357 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
<> 134:ad3be0349dc5 358 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
<> 134:ad3be0349dc5 359 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
<> 134:ad3be0349dc5 360 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
bogdanm 92:4fc01daae5a5 361 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
<> 134:ad3be0349dc5 362 #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
<> 134:ad3be0349dc5 363 #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
bogdanm 92:4fc01daae5a5 364 /**
bogdanm 92:4fc01daae5a5 365 * @}
bogdanm 92:4fc01daae5a5 366 */
bogdanm 85:024bf7f99721 367
Kojto 108:34e6b704fe68 368 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
bogdanm 85:024bf7f99721 369 * @{
Kojto 108:34e6b704fe68 370 */
<> 134:ad3be0349dc5 371 #define SPI_FTLVL_EMPTY (0x00000000U)
<> 134:ad3be0349dc5 372 #define SPI_FTLVL_QUARTER_FULL (0x00000800U)
<> 134:ad3be0349dc5 373 #define SPI_FTLVL_HALF_FULL (0x00001000U)
<> 134:ad3be0349dc5 374 #define SPI_FTLVL_FULL (0x00001800U)
bogdanm 85:024bf7f99721 375
bogdanm 85:024bf7f99721 376 /**
bogdanm 85:024bf7f99721 377 * @}
Kojto 108:34e6b704fe68 378 */
bogdanm 85:024bf7f99721 379
Kojto 108:34e6b704fe68 380 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
bogdanm 85:024bf7f99721 381 * @{
Kojto 108:34e6b704fe68 382 */
<> 134:ad3be0349dc5 383 #define SPI_FRLVL_EMPTY (0x00000000U)
<> 134:ad3be0349dc5 384 #define SPI_FRLVL_QUARTER_FULL (0x00000200U)
<> 134:ad3be0349dc5 385 #define SPI_FRLVL_HALF_FULL (0x00000400U)
<> 134:ad3be0349dc5 386 #define SPI_FRLVL_FULL (0x00000600U)
bogdanm 85:024bf7f99721 387 /**
bogdanm 85:024bf7f99721 388 * @}
bogdanm 85:024bf7f99721 389 */
bogdanm 85:024bf7f99721 390
bogdanm 85:024bf7f99721 391 /**
bogdanm 85:024bf7f99721 392 * @}
bogdanm 85:024bf7f99721 393 */
<> 134:ad3be0349dc5 394
<> 134:ad3be0349dc5 395 /* Exported macros -----------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 396 /** @defgroup SPI_Exported_Macros SPI Exported Macros
bogdanm 92:4fc01daae5a5 397 * @{
bogdanm 92:4fc01daae5a5 398 */
Kojto 108:34e6b704fe68 399
Kojto 108:34e6b704fe68 400 /** @brief Reset SPI handle state.
<> 134:ad3be0349dc5 401 * @param __HANDLE__: specifies the SPI Handle.
<> 134:ad3be0349dc5 402 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 85:024bf7f99721 403 * @retval None
bogdanm 85:024bf7f99721 404 */
bogdanm 85:024bf7f99721 405 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
bogdanm 85:024bf7f99721 406
Kojto 108:34e6b704fe68 407 /** @brief Enable or disable the specified SPI interrupts.
Kojto 108:34e6b704fe68 408 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 85:024bf7f99721 409 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto 108:34e6b704fe68 410 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<> 134:ad3be0349dc5 411 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 412 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm 85:024bf7f99721 413 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 85:024bf7f99721 414 * @arg SPI_IT_ERR: Error interrupt enable
bogdanm 85:024bf7f99721 415 * @retval None
bogdanm 85:024bf7f99721 416 */
bogdanm 85:024bf7f99721 417 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Kojto 93:e188a91d3eaa 418 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
Kojto 108:34e6b704fe68 419
Kojto 108:34e6b704fe68 420 /** @brief Check whether the specified SPI interrupt source is enabled or not.
Kojto 108:34e6b704fe68 421 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 85:024bf7f99721 422 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto 108:34e6b704fe68 423 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
bogdanm 85:024bf7f99721 424 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 425 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm 85:024bf7f99721 426 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 85:024bf7f99721 427 * @arg SPI_IT_ERR: Error interrupt enable
bogdanm 85:024bf7f99721 428 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 85:024bf7f99721 429 */
bogdanm 85:024bf7f99721 430 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 85:024bf7f99721 431
Kojto 108:34e6b704fe68 432 /** @brief Check whether the specified SPI flag is set or not.
Kojto 108:34e6b704fe68 433 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 85:024bf7f99721 434 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto 108:34e6b704fe68 435 * @param __FLAG__: specifies the flag to check.
<> 134:ad3be0349dc5 436 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 437 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
bogdanm 85:024bf7f99721 438 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
bogdanm 85:024bf7f99721 439 * @arg SPI_FLAG_CRCERR: CRC error flag
bogdanm 85:024bf7f99721 440 * @arg SPI_FLAG_MODF: Mode fault flag
bogdanm 85:024bf7f99721 441 * @arg SPI_FLAG_OVR: Overrun flag
bogdanm 85:024bf7f99721 442 * @arg SPI_FLAG_BSY: Busy flag
Kojto 108:34e6b704fe68 443 * @arg SPI_FLAG_FRE: Frame format error flag
Kojto 93:e188a91d3eaa 444 * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
Kojto 108:34e6b704fe68 445 * @arg SPI_FLAG_FRLVL: SPI fifo reception level
bogdanm 85:024bf7f99721 446 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 85:024bf7f99721 447 */
bogdanm 85:024bf7f99721 448 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm 85:024bf7f99721 449
Kojto 108:34e6b704fe68 450 /** @brief Clear the SPI CRCERR pending flag.
Kojto 108:34e6b704fe68 451 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 85:024bf7f99721 452 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 85:024bf7f99721 453 * @retval None
bogdanm 85:024bf7f99721 454 */
bogdanm 92:4fc01daae5a5 455 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Kojto 108:34e6b704fe68 456
Kojto 108:34e6b704fe68 457 /** @brief Clear the SPI MODF pending flag.
Kojto 108:34e6b704fe68 458 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 85:024bf7f99721 459 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 85:024bf7f99721 460 * @retval None
Kojto 108:34e6b704fe68 461 */
<> 134:ad3be0349dc5 462 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
<> 134:ad3be0349dc5 463 do{ \
<> 134:ad3be0349dc5 464 __IO uint32_t tmpreg_modf = 0x00U; \
<> 134:ad3be0349dc5 465 tmpreg_modf = (__HANDLE__)->Instance->SR; \
<> 134:ad3be0349dc5 466 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
<> 134:ad3be0349dc5 467 UNUSED(tmpreg_modf); \
<> 134:ad3be0349dc5 468 } while(0)
bogdanm 85:024bf7f99721 469
Kojto 108:34e6b704fe68 470 /** @brief Clear the SPI OVR pending flag.
Kojto 108:34e6b704fe68 471 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 85:024bf7f99721 472 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 85:024bf7f99721 473 * @retval None
Kojto 108:34e6b704fe68 474 */
<> 134:ad3be0349dc5 475 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
<> 134:ad3be0349dc5 476 do{ \
<> 134:ad3be0349dc5 477 __IO uint32_t tmpreg_ovr = 0x00U; \
<> 134:ad3be0349dc5 478 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
<> 134:ad3be0349dc5 479 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
<> 134:ad3be0349dc5 480 UNUSED(tmpreg_ovr); \
<> 134:ad3be0349dc5 481 } while(0)
Kojto 108:34e6b704fe68 482
Kojto 108:34e6b704fe68 483 /** @brief Clear the SPI FRE pending flag.
Kojto 108:34e6b704fe68 484 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 85:024bf7f99721 485 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 85:024bf7f99721 486 * @retval None
Kojto 108:34e6b704fe68 487 */
<> 134:ad3be0349dc5 488 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
<> 134:ad3be0349dc5 489 do{ \
<> 134:ad3be0349dc5 490 __IO uint32_t tmpreg_fre = 0x00U; \
<> 134:ad3be0349dc5 491 tmpreg_fre = (__HANDLE__)->Instance->SR; \
<> 134:ad3be0349dc5 492 UNUSED(tmpreg_fre); \
<> 134:ad3be0349dc5 493 }while(0)
Kojto 108:34e6b704fe68 494
Kojto 108:34e6b704fe68 495 /** @brief Enable the SPI peripheral.
Kojto 108:34e6b704fe68 496 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 85:024bf7f99721 497 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 85:024bf7f99721 498 * @retval None
bogdanm 85:024bf7f99721 499 */
bogdanm 85:024bf7f99721 500 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
bogdanm 85:024bf7f99721 501
Kojto 108:34e6b704fe68 502 /** @brief Disable the SPI peripheral.
Kojto 108:34e6b704fe68 503 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 85:024bf7f99721 504 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 85:024bf7f99721 505 * @retval None
bogdanm 85:024bf7f99721 506 */
Kojto 93:e188a91d3eaa 507 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
bogdanm 85:024bf7f99721 508
Kojto 108:34e6b704fe68 509 /**
Kojto 108:34e6b704fe68 510 * @}
Kojto 108:34e6b704fe68 511 */
Kojto 108:34e6b704fe68 512
<> 134:ad3be0349dc5 513 /* Private macros ------------------------------------------------------------*/
<> 134:ad3be0349dc5 514 /** @defgroup SPI_Private_Macros SPI Private Macros
Kojto 108:34e6b704fe68 515 * @{
Kojto 108:34e6b704fe68 516 */
Kojto 108:34e6b704fe68 517
Kojto 108:34e6b704fe68 518 /** @brief Set the SPI transmit-only mode.
Kojto 108:34e6b704fe68 519 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 85:024bf7f99721 520 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 85:024bf7f99721 521 * @retval None
bogdanm 85:024bf7f99721 522 */
Kojto 108:34e6b704fe68 523 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
Kojto 108:34e6b704fe68 524
Kojto 108:34e6b704fe68 525 /** @brief Set the SPI receive-only mode.
Kojto 108:34e6b704fe68 526 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 85:024bf7f99721 527 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 85:024bf7f99721 528 * @retval None
bogdanm 85:024bf7f99721 529 */
Kojto 108:34e6b704fe68 530 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
Kojto 108:34e6b704fe68 531
Kojto 108:34e6b704fe68 532 /** @brief Reset the CRC calculation of the SPI.
Kojto 108:34e6b704fe68 533 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 85:024bf7f99721 534 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 85:024bf7f99721 535 * @retval None
bogdanm 85:024bf7f99721 536 */
Kojto 108:34e6b704fe68 537 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
Kojto 108:34e6b704fe68 538 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
bogdanm 85:024bf7f99721 539
Kojto 122:f9eeca106725 540 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
Kojto 122:f9eeca106725 541 ((MODE) == SPI_MODE_MASTER))
bogdanm 85:024bf7f99721 542
<> 134:ad3be0349dc5 543 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
<> 134:ad3be0349dc5 544 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
<> 134:ad3be0349dc5 545 ((MODE) == SPI_DIRECTION_1LINE))
Kojto 122:f9eeca106725 546
Kojto 122:f9eeca106725 547 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
Kojto 122:f9eeca106725 548
<> 134:ad3be0349dc5 549 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
<> 134:ad3be0349dc5 550 ((MODE) == SPI_DIRECTION_1LINE))
Kojto 122:f9eeca106725 551
Kojto 122:f9eeca106725 552 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
Kojto 122:f9eeca106725 553 ((DATASIZE) == SPI_DATASIZE_15BIT) || \
Kojto 122:f9eeca106725 554 ((DATASIZE) == SPI_DATASIZE_14BIT) || \
Kojto 122:f9eeca106725 555 ((DATASIZE) == SPI_DATASIZE_13BIT) || \
Kojto 122:f9eeca106725 556 ((DATASIZE) == SPI_DATASIZE_12BIT) || \
Kojto 122:f9eeca106725 557 ((DATASIZE) == SPI_DATASIZE_11BIT) || \
Kojto 122:f9eeca106725 558 ((DATASIZE) == SPI_DATASIZE_10BIT) || \
Kojto 122:f9eeca106725 559 ((DATASIZE) == SPI_DATASIZE_9BIT) || \
Kojto 122:f9eeca106725 560 ((DATASIZE) == SPI_DATASIZE_8BIT) || \
Kojto 122:f9eeca106725 561 ((DATASIZE) == SPI_DATASIZE_7BIT) || \
Kojto 122:f9eeca106725 562 ((DATASIZE) == SPI_DATASIZE_6BIT) || \
Kojto 122:f9eeca106725 563 ((DATASIZE) == SPI_DATASIZE_5BIT) || \
Kojto 122:f9eeca106725 564 ((DATASIZE) == SPI_DATASIZE_4BIT))
Kojto 122:f9eeca106725 565
Kojto 122:f9eeca106725 566 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
Kojto 122:f9eeca106725 567 ((CPOL) == SPI_POLARITY_HIGH))
Kojto 122:f9eeca106725 568
Kojto 122:f9eeca106725 569 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
Kojto 122:f9eeca106725 570 ((CPHA) == SPI_PHASE_2EDGE))
Kojto 122:f9eeca106725 571
<> 134:ad3be0349dc5 572 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
Kojto 122:f9eeca106725 573 ((NSS) == SPI_NSS_HARD_INPUT) || \
Kojto 122:f9eeca106725 574 ((NSS) == SPI_NSS_HARD_OUTPUT))
Kojto 122:f9eeca106725 575
Kojto 122:f9eeca106725 576 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
Kojto 122:f9eeca106725 577 ((NSSP) == SPI_NSS_PULSE_DISABLE))
Kojto 122:f9eeca106725 578
<> 134:ad3be0349dc5 579 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
<> 134:ad3be0349dc5 580 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
<> 134:ad3be0349dc5 581 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
<> 134:ad3be0349dc5 582 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
<> 134:ad3be0349dc5 583 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
<> 134:ad3be0349dc5 584 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
Kojto 122:f9eeca106725 585 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
Kojto 122:f9eeca106725 586 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
Kojto 122:f9eeca106725 587
Kojto 122:f9eeca106725 588 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
Kojto 122:f9eeca106725 589 ((BIT) == SPI_FIRSTBIT_LSB))
Kojto 122:f9eeca106725 590
Kojto 122:f9eeca106725 591 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
Kojto 122:f9eeca106725 592 ((MODE) == SPI_TIMODE_ENABLE))
Kojto 122:f9eeca106725 593
Kojto 122:f9eeca106725 594 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
Kojto 122:f9eeca106725 595 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
Kojto 122:f9eeca106725 596
Kojto 122:f9eeca106725 597 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
Kojto 122:f9eeca106725 598 ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
Kojto 122:f9eeca106725 599 ((LENGTH) == SPI_CRC_LENGTH_16BIT))
Kojto 122:f9eeca106725 600
<> 134:ad3be0349dc5 601 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
Kojto 108:34e6b704fe68 602
bogdanm 92:4fc01daae5a5 603 /**
bogdanm 92:4fc01daae5a5 604 * @}
bogdanm 92:4fc01daae5a5 605 */
Kojto 108:34e6b704fe68 606
Kojto 108:34e6b704fe68 607 /* Include SPI HAL Extended module */
Kojto 108:34e6b704fe68 608 #include "stm32f0xx_hal_spi_ex.h"
Kojto 108:34e6b704fe68 609
bogdanm 85:024bf7f99721 610 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 611 /** @addtogroup SPI_Exported_Functions
bogdanm 92:4fc01daae5a5 612 * @{
bogdanm 92:4fc01daae5a5 613 */
bogdanm 85:024bf7f99721 614
Kojto 108:34e6b704fe68 615 /** @addtogroup SPI_Exported_Functions_Group1
bogdanm 92:4fc01daae5a5 616 * @{
bogdanm 92:4fc01daae5a5 617 */
<> 134:ad3be0349dc5 618 /* Initialization/de-initialization functions ********************************/
bogdanm 85:024bf7f99721 619 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
<> 134:ad3be0349dc5 620 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
bogdanm 85:024bf7f99721 621 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
bogdanm 85:024bf7f99721 622 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 623 /**
bogdanm 92:4fc01daae5a5 624 * @}
bogdanm 92:4fc01daae5a5 625 */
bogdanm 85:024bf7f99721 626
bogdanm 92:4fc01daae5a5 627 /** @addtogroup SPI_Exported_Functions_Group2
bogdanm 92:4fc01daae5a5 628 * @{
bogdanm 92:4fc01daae5a5 629 */
<> 134:ad3be0349dc5 630 /* I/O operation functions ***************************************************/
bogdanm 85:024bf7f99721 631 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 85:024bf7f99721 632 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 134:ad3be0349dc5 633 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
<> 134:ad3be0349dc5 634 uint32_t Timeout);
bogdanm 85:024bf7f99721 635 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 85:024bf7f99721 636 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 134:ad3be0349dc5 637 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
<> 134:ad3be0349dc5 638 uint16_t Size);
bogdanm 85:024bf7f99721 639 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 85:024bf7f99721 640 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 134:ad3be0349dc5 641 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
<> 134:ad3be0349dc5 642 uint16_t Size);
Kojto 93:e188a91d3eaa 643 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
Kojto 93:e188a91d3eaa 644 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
Kojto 93:e188a91d3eaa 645 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
<> 134:ad3be0349dc5 646 /* Transfer Abort functions */
<> 134:ad3be0349dc5 647 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
<> 134:ad3be0349dc5 648 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
Kojto 93:e188a91d3eaa 649
bogdanm 85:024bf7f99721 650 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
bogdanm 85:024bf7f99721 651 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 85:024bf7f99721 652 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 85:024bf7f99721 653 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
Kojto 93:e188a91d3eaa 654 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
Kojto 93:e188a91d3eaa 655 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
Kojto 93:e188a91d3eaa 656 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 85:024bf7f99721 657 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
<> 134:ad3be0349dc5 658 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 659 /**
bogdanm 92:4fc01daae5a5 660 * @}
bogdanm 92:4fc01daae5a5 661 */
bogdanm 85:024bf7f99721 662
bogdanm 92:4fc01daae5a5 663 /** @addtogroup SPI_Exported_Functions_Group3
bogdanm 92:4fc01daae5a5 664 * @{
bogdanm 92:4fc01daae5a5 665 */
<> 134:ad3be0349dc5 666 /* Peripheral State and Error functions ***************************************/
bogdanm 85:024bf7f99721 667 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
Kojto 108:34e6b704fe68 668 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 669 /**
bogdanm 92:4fc01daae5a5 670 * @}
bogdanm 92:4fc01daae5a5 671 */
bogdanm 85:024bf7f99721 672
bogdanm 85:024bf7f99721 673 /**
bogdanm 85:024bf7f99721 674 * @}
bogdanm 92:4fc01daae5a5 675 */
bogdanm 85:024bf7f99721 676
bogdanm 85:024bf7f99721 677 /**
bogdanm 85:024bf7f99721 678 * @}
Kojto 108:34e6b704fe68 679 */
Kojto 108:34e6b704fe68 680
Kojto 108:34e6b704fe68 681 /**
Kojto 108:34e6b704fe68 682 * @}
Kojto 108:34e6b704fe68 683 */
bogdanm 85:024bf7f99721 684
bogdanm 85:024bf7f99721 685 #ifdef __cplusplus
bogdanm 85:024bf7f99721 686 }
bogdanm 85:024bf7f99721 687 #endif
bogdanm 85:024bf7f99721 688
bogdanm 85:024bf7f99721 689 #endif /* __STM32F0xx_HAL_SPI_H */
bogdanm 85:024bf7f99721 690
bogdanm 85:024bf7f99721 691 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/