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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Parent:: 134:ad3be0349dc5

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	85:024bf7f99721	1	/**
bogdanm	85:024bf7f99721	2	******************************************************************************
bogdanm	85:024bf7f99721	3	* @file stm32f0xx_hal_rcc_ex.h
bogdanm	85:024bf7f99721	4	* @author MCD Application Team
<>	134:ad3be0349dc5	5	* @version V1.5.0
<>	134:ad3be0349dc5	6	* @date 04-November-2016
bogdanm	85:024bf7f99721	7	* @brief Header file of RCC HAL Extension module.
bogdanm	85:024bf7f99721	8	******************************************************************************
bogdanm	85:024bf7f99721	9	* @attention
bogdanm	85:024bf7f99721	10	*
Kojto	122:f9eeca106725	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	85:024bf7f99721	12	*
bogdanm	85:024bf7f99721	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	85:024bf7f99721	14	* are permitted provided that the following conditions are met:
bogdanm	85:024bf7f99721	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	85:024bf7f99721	16	* this list of conditions and the following disclaimer.
bogdanm	85:024bf7f99721	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	85:024bf7f99721	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	85:024bf7f99721	19	* and/or other materials provided with the distribution.
bogdanm	85:024bf7f99721	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	85:024bf7f99721	21	* may be used to endorse or promote products derived from this software
bogdanm	85:024bf7f99721	22	* without specific prior written permission.
bogdanm	85:024bf7f99721	23	*
bogdanm	85:024bf7f99721	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	85:024bf7f99721	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	85:024bf7f99721	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	85:024bf7f99721	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	85:024bf7f99721	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	85:024bf7f99721	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	85:024bf7f99721	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	85:024bf7f99721	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	85:024bf7f99721	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	85:024bf7f99721	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	85:024bf7f99721	34	*
bogdanm	85:024bf7f99721	35	******************************************************************************
bogdanm	85:024bf7f99721	36	*/
bogdanm	85:024bf7f99721	37
bogdanm	85:024bf7f99721	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	85:024bf7f99721	39	#ifndef __STM32F0xx_HAL_RCC_EX_H
Kojto	122:f9eeca106725	40	#define __STM32F0xx_HAL_RCC_EX_H
bogdanm	85:024bf7f99721	41
bogdanm	85:024bf7f99721	42	#ifdef __cplusplus
bogdanm	85:024bf7f99721	43	extern "C" {
bogdanm	85:024bf7f99721	44	#endif
bogdanm	85:024bf7f99721	45
bogdanm	85:024bf7f99721	46	/* Includes ------------------------------------------------------------------*/
bogdanm	85:024bf7f99721	47	#include "stm32f0xx_hal_def.h"
bogdanm	85:024bf7f99721	48
bogdanm	85:024bf7f99721	49	/** @addtogroup STM32F0xx_HAL_Driver
bogdanm	85:024bf7f99721	50	* @{
bogdanm	85:024bf7f99721	51	*/
bogdanm	85:024bf7f99721	52
Kojto	108:34e6b704fe68	53	/** @addtogroup RCC
Kojto	108:34e6b704fe68	54	* @{
Kojto	108:34e6b704fe68	55	*/
Kojto	108:34e6b704fe68	56
Kojto	108:34e6b704fe68	57	/** @addtogroup RCC_Private_Macros
Kojto	108:34e6b704fe68	58	* @{
Kojto	108:34e6b704fe68	59	*/
Kojto	122:f9eeca106725	60	#if defined(RCC_HSI48_SUPPORT)
Kojto	108:34e6b704fe68	61	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
Kojto	108:34e6b704fe68	62	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Kojto	108:34e6b704fe68	63	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Kojto	108:34e6b704fe68	64	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Kojto	108:34e6b704fe68	65	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
Kojto	108:34e6b704fe68	66	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) \|\| \
Kojto	108:34e6b704fe68	67	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
Kojto	122:f9eeca106725	68
Kojto	108:34e6b704fe68	69	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	70	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	108:34e6b704fe68	71	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
Kojto	108:34e6b704fe68	72	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
Kojto	108:34e6b704fe68	73
Kojto	108:34e6b704fe68	74	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
Kojto	108:34e6b704fe68	75	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
Kojto	108:34e6b704fe68	76	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
Kojto	108:34e6b704fe68	77	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
Kojto	122:f9eeca106725	78
Kojto	108:34e6b704fe68	79	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	80	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
Kojto	108:34e6b704fe68	81	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	122:f9eeca106725	82
Kojto	108:34e6b704fe68	83	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
Kojto	122:f9eeca106725	84
Kojto	108:34e6b704fe68	85	#else
Kojto	122:f9eeca106725	86
Kojto	108:34e6b704fe68	87	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
Kojto	108:34e6b704fe68	88	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Kojto	108:34e6b704fe68	89	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Kojto	108:34e6b704fe68	90	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Kojto	108:34e6b704fe68	91	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
Kojto	108:34e6b704fe68	92	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14))
Kojto	108:34e6b704fe68	93	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	94	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	108:34e6b704fe68	95	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto	108:34e6b704fe68	96
Kojto	108:34e6b704fe68	97	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
Kojto	108:34e6b704fe68	98	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
Kojto	108:34e6b704fe68	99	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
Kojto	108:34e6b704fe68	100	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	101	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	108:34e6b704fe68	102
Kojto	122:f9eeca106725	103	#endif /* RCC_HSI48_SUPPORT */
Kojto	108:34e6b704fe68	104
Kojto	122:f9eeca106725	105	#if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
Kojto	108:34e6b704fe68	106
Kojto	122:f9eeca106725	107	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
Kojto	122:f9eeca106725	108	((SOURCE) == RCC_MCO1SOURCE_LSI) \|\| \
Kojto	122:f9eeca106725	109	((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
Kojto	122:f9eeca106725	110	((SOURCE) == RCC_MCO1SOURCE_SYSCLK) \|\| \
Kojto	122:f9eeca106725	111	((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| \
Kojto	122:f9eeca106725	112	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| \
Kojto	122:f9eeca106725	113	((SOURCE) == RCC_MCO1SOURCE_PLLCLK) \|\| \
Kojto	122:f9eeca106725	114	((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) \|\| \
Kojto	122:f9eeca106725	115	((SOURCE) == RCC_MCO1SOURCE_HSI14))
Kojto	108:34e6b704fe68	116
Kojto	122:f9eeca106725	117	#elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48)
Kojto	108:34e6b704fe68	118
Kojto	122:f9eeca106725	119	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
Kojto	122:f9eeca106725	120	((SOURCE) == RCC_MCO1SOURCE_LSI) \|\| \
Kojto	122:f9eeca106725	121	((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
Kojto	122:f9eeca106725	122	((SOURCE) == RCC_MCO1SOURCE_SYSCLK) \|\| \
Kojto	122:f9eeca106725	123	((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| \
Kojto	122:f9eeca106725	124	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| \
Kojto	122:f9eeca106725	125	((SOURCE) == RCC_MCO1SOURCE_PLLCLK) \|\| \
Kojto	122:f9eeca106725	126	((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) \|\| \
Kojto	122:f9eeca106725	127	((SOURCE) == RCC_MCO1SOURCE_HSI14) \|\| \
Kojto	122:f9eeca106725	128	((SOURCE) == RCC_MCO1SOURCE_HSI48))
Kojto	108:34e6b704fe68	129
Kojto	122:f9eeca106725	130	#elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
Kojto	108:34e6b704fe68	131
Kojto	122:f9eeca106725	132	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
Kojto	122:f9eeca106725	133	((SOURCE) == RCC_MCO1SOURCE_LSI) \|\| \
Kojto	122:f9eeca106725	134	((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
Kojto	122:f9eeca106725	135	((SOURCE) == RCC_MCO1SOURCE_SYSCLK) \|\| \
Kojto	122:f9eeca106725	136	((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| \
Kojto	122:f9eeca106725	137	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| \
Kojto	122:f9eeca106725	138	((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) \|\| \
Kojto	122:f9eeca106725	139	((SOURCE) == RCC_MCO1SOURCE_HSI14))
Kojto	122:f9eeca106725	140
Kojto	122:f9eeca106725	141	#endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */
Kojto	108:34e6b704fe68	142
Kojto	108:34e6b704fe68	143	/**
Kojto	108:34e6b704fe68	144	* @}
Kojto	108:34e6b704fe68	145	*/
Kojto	108:34e6b704fe68	146
Kojto	108:34e6b704fe68	147	/** @addtogroup RCC_Exported_Constants
Kojto	108:34e6b704fe68	148	* @{
Kojto	108:34e6b704fe68	149	*/
Kojto	122:f9eeca106725	150	#if defined(RCC_HSI48_SUPPORT)
Kojto	108:34e6b704fe68	151
Kojto	108:34e6b704fe68	152	/** @addtogroup RCC_PLL_Clock_Source
Kojto	108:34e6b704fe68	153	* @{
Kojto	108:34e6b704fe68	154	*/
Kojto	108:34e6b704fe68	155	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto	108:34e6b704fe68	156	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
Kojto	108:34e6b704fe68	157
Kojto	108:34e6b704fe68	158	/**
Kojto	108:34e6b704fe68	159	* @}
Kojto	108:34e6b704fe68	160	*/
Kojto	108:34e6b704fe68	161
Kojto	108:34e6b704fe68	162	/** @addtogroup RCC_Interrupt
Kojto	108:34e6b704fe68	163	* @{
Kojto	108:34e6b704fe68	164	*/
Kojto	108:34e6b704fe68	165	#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
Kojto	108:34e6b704fe68	166	/**
Kojto	108:34e6b704fe68	167	* @}
Kojto	108:34e6b704fe68	168	*/
Kojto	108:34e6b704fe68	169
Kojto	108:34e6b704fe68	170	/** @addtogroup RCC_Flag
Kojto	108:34e6b704fe68	171	* @{
Kojto	108:34e6b704fe68	172	*/
<>	134:ad3be0349dc5	173	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5U) \| RCC_CR2_HSI48RDY_BitNumber))
Kojto	108:34e6b704fe68	174	/**
Kojto	108:34e6b704fe68	175	* @}
Kojto	108:34e6b704fe68	176	*/
Kojto	108:34e6b704fe68	177
Kojto	108:34e6b704fe68	178	/** @addtogroup RCC_System_Clock_Source
Kojto	108:34e6b704fe68	179	* @{
Kojto	108:34e6b704fe68	180	*/
Kojto	108:34e6b704fe68	181	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
Kojto	108:34e6b704fe68	182	/**
Kojto	108:34e6b704fe68	183	* @}
Kojto	108:34e6b704fe68	184	*/
Kojto	108:34e6b704fe68	185
Kojto	108:34e6b704fe68	186	/** @addtogroup RCC_System_Clock_Source_Status
Kojto	108:34e6b704fe68	187	* @{
Kojto	108:34e6b704fe68	188	*/
Kojto	108:34e6b704fe68	189	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
Kojto	108:34e6b704fe68	190	/**
Kojto	108:34e6b704fe68	191	* @}
Kojto	108:34e6b704fe68	192	*/
Kojto	108:34e6b704fe68	193
Kojto	108:34e6b704fe68	194	#else
Kojto	108:34e6b704fe68	195	/** @addtogroup RCC_PLL_Clock_Source
Kojto	108:34e6b704fe68	196	* @{
Kojto	108:34e6b704fe68	197	*/
Kojto	108:34e6b704fe68	198
Kojto	108:34e6b704fe68	199	#if defined(STM32F070xB) \|\| defined(STM32F070x6) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	200	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto	108:34e6b704fe68	201	#else
Kojto	108:34e6b704fe68	202	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
Kojto	108:34e6b704fe68	203	#endif
Kojto	108:34e6b704fe68	204
Kojto	108:34e6b704fe68	205	/**
Kojto	108:34e6b704fe68	206	* @}
Kojto	108:34e6b704fe68	207	*/
Kojto	108:34e6b704fe68	208
Kojto	122:f9eeca106725	209	#endif /* RCC_HSI48_SUPPORT */
Kojto	108:34e6b704fe68	210
Kojto	108:34e6b704fe68	211	/** @addtogroup RCC_MCO_Clock_Source
Kojto	108:34e6b704fe68	212	* @{
Kojto	108:34e6b704fe68	213	*/
Kojto	108:34e6b704fe68	214
Kojto	122:f9eeca106725	215	#if defined(RCC_CFGR_PLLNODIV)
Kojto	108:34e6b704fe68	216
Kojto	122:f9eeca106725	217	#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
Kojto	108:34e6b704fe68	218
Kojto	122:f9eeca106725	219	#endif /* RCC_CFGR_PLLNODIV */
Kojto	108:34e6b704fe68	220
Kojto	122:f9eeca106725	221	#if defined(RCC_CFGR_MCO_HSI48)
Kojto	108:34e6b704fe68	222
Kojto	122:f9eeca106725	223	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
Kojto	108:34e6b704fe68	224
Kojto	122:f9eeca106725	225	#endif /* SRCC_CFGR_MCO_HSI48 */
Kojto	108:34e6b704fe68	226	/**
Kojto	108:34e6b704fe68	227	* @}
Kojto	108:34e6b704fe68	228	*/
Kojto	108:34e6b704fe68	229
Kojto	108:34e6b704fe68	230	/**
Kojto	108:34e6b704fe68	231	* @}
Kojto	108:34e6b704fe68	232	*/
Kojto	108:34e6b704fe68	233
Kojto	108:34e6b704fe68	234	/**
Kojto	108:34e6b704fe68	235	* @}
Kojto	108:34e6b704fe68	236	*/
Kojto	108:34e6b704fe68	237
bogdanm	85:024bf7f99721	238	/** @addtogroup RCCEx
bogdanm	85:024bf7f99721	239	* @{
bogdanm	85:024bf7f99721	240	*/
bogdanm	85:024bf7f99721	241
Kojto	122:f9eeca106725	242	/* Private Constants -------------------------------------------------------------*/
Kojto	122:f9eeca106725	243	#if defined(CRS)
Kojto	122:f9eeca106725	244	/** @addtogroup RCCEx_Private_Constants
Kojto	122:f9eeca106725	245	* @{
Kojto	122:f9eeca106725	246	*/
Kojto	122:f9eeca106725	247
Kojto	122:f9eeca106725	248	/* CRS IT Error Mask */
Kojto	122:f9eeca106725	249	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
Kojto	122:f9eeca106725	250
Kojto	122:f9eeca106725	251	/* CRS Flag Error Mask */
Kojto	122:f9eeca106725	252	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
Kojto	122:f9eeca106725	253
Kojto	122:f9eeca106725	254	/**
Kojto	122:f9eeca106725	255	* @}
Kojto	122:f9eeca106725	256	*/
Kojto	122:f9eeca106725	257	#endif /* CRS */
Kojto	122:f9eeca106725	258
Kojto	108:34e6b704fe68	259	/* Private macro -------------------------------------------------------------*/
Kojto	108:34e6b704fe68	260	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
Kojto	108:34e6b704fe68	261	* @{
Kojto	108:34e6b704fe68	262	*/
Kojto	108:34e6b704fe68	263	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	108:34e6b704fe68	264	\|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	265
Kojto	122:f9eeca106725	266	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	108:34e6b704fe68	267	RCC_PERIPHCLK_RTC))
Kojto	108:34e6b704fe68	268	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
Kojto	108:34e6b704fe68	269	STM32F030xC */
Kojto	108:34e6b704fe68	270
Kojto	108:34e6b704fe68	271	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	108:34e6b704fe68	272
Kojto	122:f9eeca106725	273	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	108:34e6b704fe68	274	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
Kojto	108:34e6b704fe68	275	#endif /* STM32F070x6 \|\| STM32F070xB */
Kojto	108:34e6b704fe68	276
Kojto	108:34e6b704fe68	277	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
Kojto	108:34e6b704fe68	278
Kojto	122:f9eeca106725	279	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	108:34e6b704fe68	280	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
Kojto	108:34e6b704fe68	281	RCC_PERIPHCLK_USB))
Kojto	108:34e6b704fe68	282	#endif /* STM32F042x6 \|\| STM32F048xx */
Kojto	108:34e6b704fe68	283
Kojto	108:34e6b704fe68	284	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	108:34e6b704fe68	285
Kojto	122:f9eeca106725	286	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	108:34e6b704fe68	287	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
Kojto	108:34e6b704fe68	288	#endif /* STM32F051x8 \|\| STM32F058xx */
Kojto	108:34e6b704fe68	289
Kojto	108:34e6b704fe68	290	#if defined(STM32F071xB)
Kojto	108:34e6b704fe68	291
Kojto	122:f9eeca106725	292	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
Kojto	108:34e6b704fe68	293	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
Kojto	108:34e6b704fe68	294	RCC_PERIPHCLK_RTC))
Kojto	108:34e6b704fe68	295	#endif /* STM32F071xB */
Kojto	108:34e6b704fe68	296
Kojto	108:34e6b704fe68	297	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	108:34e6b704fe68	298
Kojto	122:f9eeca106725	299	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
Kojto	108:34e6b704fe68	300	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
Kojto	108:34e6b704fe68	301	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
Kojto	108:34e6b704fe68	302	#endif /* STM32F072xB \|\| STM32F078xx */
Kojto	108:34e6b704fe68	303
Kojto	108:34e6b704fe68	304	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	305
Kojto	122:f9eeca106725	306	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
Kojto	108:34e6b704fe68	307	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
Kojto	108:34e6b704fe68	308	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USART3 ))
Kojto	108:34e6b704fe68	309	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	310
Kojto	108:34e6b704fe68	311	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	108:34e6b704fe68	312
Kojto	108:34e6b704fe68	313	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
Kojto	122:f9eeca106725	314	((SOURCE) == RCC_USBCLKSOURCE_PLL))
Kojto	108:34e6b704fe68	315
Kojto	108:34e6b704fe68	316	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
Kojto	108:34e6b704fe68	317
Kojto	108:34e6b704fe68	318	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	108:34e6b704fe68	319
Kojto	122:f9eeca106725	320	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) \|\| \
Kojto	122:f9eeca106725	321	((SOURCE) == RCC_USBCLKSOURCE_PLL))
Kojto	108:34e6b704fe68	322
Kojto	108:34e6b704fe68	323	#endif /* STM32F070x6 \|\| STM32F070xB */
Kojto	108:34e6b704fe68	324
Kojto	108:34e6b704fe68	325	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	326	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	327
Kojto	108:34e6b704fe68	328	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
Kojto	108:34e6b704fe68	329	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
Kojto	108:34e6b704fe68	330	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
Kojto	108:34e6b704fe68	331	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
Kojto	108:34e6b704fe68	332
Kojto	108:34e6b704fe68	333	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	334	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	335
Kojto	108:34e6b704fe68	336	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	337
Kojto	108:34e6b704fe68	338	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
Kojto	108:34e6b704fe68	339	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
Kojto	108:34e6b704fe68	340	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
Kojto	108:34e6b704fe68	341	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
Kojto	108:34e6b704fe68	342	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	343
Kojto	108:34e6b704fe68	344
Kojto	108:34e6b704fe68	345	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	346	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	347	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	348	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	349
Kojto	108:34e6b704fe68	350	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	351	((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto	108:34e6b704fe68	352	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	353	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	354	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	355	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	356
Kojto	122:f9eeca106725	357	#if defined(RCC_CFGR_MCOPRE)
Kojto	108:34e6b704fe68	358
Kojto	122:f9eeca106725	359	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
Kojto	122:f9eeca106725	360	((DIV) == RCC_MCODIV_4) \|\| ((DIV) == RCC_MCODIV_8) \|\| \
Kojto	122:f9eeca106725	361	((DIV) == RCC_MCODIV_16) \|\| ((DIV) == RCC_MCODIV_32) \|\| \
Kojto	122:f9eeca106725	362	((DIV) == RCC_MCODIV_64) \|\| ((DIV) == RCC_MCODIV_128))
Kojto	122:f9eeca106725	363	#else
Kojto	122:f9eeca106725	364
Kojto	122:f9eeca106725	365	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
Kojto	122:f9eeca106725	366
Kojto	122:f9eeca106725	367	#endif /* RCC_CFGR_MCOPRE */
Kojto	108:34e6b704fe68	368
Kojto	122:f9eeca106725	369	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| \
Kojto	122:f9eeca106725	370	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
Kojto	122:f9eeca106725	371	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| \
Kojto	122:f9eeca106725	372	((__DRIVE__) == RCC_LSEDRIVE_HIGH))
Kojto	108:34e6b704fe68	373
Kojto	122:f9eeca106725	374	#if defined(CRS)
Kojto	108:34e6b704fe68	375
Kojto	108:34e6b704fe68	376	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
Kojto	108:34e6b704fe68	377	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
Kojto	108:34e6b704fe68	378	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
Kojto	108:34e6b704fe68	379	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
Kojto	108:34e6b704fe68	380	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
Kojto	108:34e6b704fe68	381	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
Kojto	108:34e6b704fe68	382	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
Kojto	108:34e6b704fe68	383	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
Kojto	108:34e6b704fe68	384	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
<>	134:ad3be0349dc5	385	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU))
<>	134:ad3be0349dc5	386	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU))
<>	134:ad3be0349dc5	387	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU))
Kojto	108:34e6b704fe68	388	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
Kojto	108:34e6b704fe68	389	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
Kojto	122:f9eeca106725	390	#endif /* CRS */
Kojto	108:34e6b704fe68	391	/**
Kojto	108:34e6b704fe68	392	* @}
Kojto	108:34e6b704fe68	393	*/
Kojto	108:34e6b704fe68	394
bogdanm	85:024bf7f99721	395	/* Exported types ------------------------------------------------------------*/
bogdanm	85:024bf7f99721	396
bogdanm	92:4fc01daae5a5	397	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
bogdanm	92:4fc01daae5a5	398	* @{
bogdanm	92:4fc01daae5a5	399	*/
bogdanm	92:4fc01daae5a5	400
bogdanm	85:024bf7f99721	401	/**
bogdanm	85:024bf7f99721	402	* @brief RCC extended clocks structure definition
bogdanm	85:024bf7f99721	403	*/
Kojto	108:34e6b704fe68	404	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	108:34e6b704fe68	405	\|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	406	typedef struct
bogdanm	85:024bf7f99721	407	{
bogdanm	85:024bf7f99721	408	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	409	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	410
bogdanm	85:024bf7f99721	411	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	412	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	413
bogdanm	85:024bf7f99721	414	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	415	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	416
bogdanm	85:024bf7f99721	417	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	418	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	419
bogdanm	85:024bf7f99721	420	}RCC_PeriphCLKInitTypeDef;
Kojto	93:e188a91d3eaa	421	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
Kojto	93:e188a91d3eaa	422	STM32F030xC */
Kojto	93:e188a91d3eaa	423
Kojto	93:e188a91d3eaa	424	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	93:e188a91d3eaa	425	typedef struct
Kojto	93:e188a91d3eaa	426	{
Kojto	93:e188a91d3eaa	427	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	93:e188a91d3eaa	428	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	93:e188a91d3eaa	429
Kojto	93:e188a91d3eaa	430	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	93:e188a91d3eaa	431	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	93:e188a91d3eaa	432
Kojto	93:e188a91d3eaa	433	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	93:e188a91d3eaa	434	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	93:e188a91d3eaa	435
Kojto	93:e188a91d3eaa	436	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	93:e188a91d3eaa	437	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	93:e188a91d3eaa	438
Kojto	93:e188a91d3eaa	439	uint32_t UsbClockSelection; /*!< USB clock source
Kojto	93:e188a91d3eaa	440	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	93:e188a91d3eaa	441
Kojto	93:e188a91d3eaa	442	}RCC_PeriphCLKInitTypeDef;
Kojto	93:e188a91d3eaa	443	#endif /* STM32F070x6 \|\| STM32F070xB */
bogdanm	85:024bf7f99721	444
bogdanm	85:024bf7f99721	445	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
bogdanm	85:024bf7f99721	446	typedef struct
bogdanm	85:024bf7f99721	447	{
bogdanm	85:024bf7f99721	448	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	449	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	450
bogdanm	85:024bf7f99721	451	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	452	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	453
bogdanm	85:024bf7f99721	454	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	455	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	456
bogdanm	85:024bf7f99721	457	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	458	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	459
bogdanm	85:024bf7f99721	460	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	461	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	462
bogdanm	85:024bf7f99721	463	uint32_t UsbClockSelection; /*!< USB clock source
bogdanm	85:024bf7f99721	464	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	85:024bf7f99721	465
bogdanm	85:024bf7f99721	466	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	467	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	85:024bf7f99721	468
bogdanm	85:024bf7f99721	469	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	85:024bf7f99721	470	typedef struct
bogdanm	85:024bf7f99721	471	{
bogdanm	85:024bf7f99721	472	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	473	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	474
bogdanm	85:024bf7f99721	475	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	476	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	477
bogdanm	85:024bf7f99721	478	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	479	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	480
bogdanm	85:024bf7f99721	481	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	482	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	483
bogdanm	85:024bf7f99721	484	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	485	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	486
bogdanm	85:024bf7f99721	487	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	488	#endif /* STM32F051x8 \|\| STM32F058xx */
bogdanm	85:024bf7f99721	489
bogdanm	85:024bf7f99721	490	#if defined(STM32F071xB)
bogdanm	85:024bf7f99721	491	typedef struct
bogdanm	85:024bf7f99721	492	{
bogdanm	85:024bf7f99721	493	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	494	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	495
bogdanm	85:024bf7f99721	496	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	497	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	498
bogdanm	85:024bf7f99721	499	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	500	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	501
bogdanm	85:024bf7f99721	502	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	85:024bf7f99721	503	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	85:024bf7f99721	504
bogdanm	85:024bf7f99721	505	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	506	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	507
bogdanm	85:024bf7f99721	508	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	509	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	510
bogdanm	85:024bf7f99721	511	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	512	#endif /* STM32F071xB */
bogdanm	85:024bf7f99721	513
bogdanm	92:4fc01daae5a5	514	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	515	typedef struct
bogdanm	85:024bf7f99721	516	{
bogdanm	85:024bf7f99721	517	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	518	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	519
bogdanm	85:024bf7f99721	520	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	521	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	522
bogdanm	85:024bf7f99721	523	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	524	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	525
bogdanm	85:024bf7f99721	526	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	85:024bf7f99721	527	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	85:024bf7f99721	528
bogdanm	85:024bf7f99721	529	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	530	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	531
bogdanm	85:024bf7f99721	532	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	533	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	534
bogdanm	85:024bf7f99721	535	uint32_t UsbClockSelection; /*!< USB clock source
bogdanm	85:024bf7f99721	536	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	85:024bf7f99721	537
bogdanm	85:024bf7f99721	538	}RCC_PeriphCLKInitTypeDef;
bogdanm	92:4fc01daae5a5	539	#endif /* STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	540
bogdanm	92:4fc01daae5a5	541
bogdanm	92:4fc01daae5a5	542	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	543	typedef struct
bogdanm	85:024bf7f99721	544	{
bogdanm	85:024bf7f99721	545	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	546	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	547
bogdanm	85:024bf7f99721	548	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	549	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	550
bogdanm	85:024bf7f99721	551	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	552	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	553
bogdanm	85:024bf7f99721	554	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	85:024bf7f99721	555	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	85:024bf7f99721	556
bogdanm	92:4fc01daae5a5	557	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	92:4fc01daae5a5	558	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
bogdanm	92:4fc01daae5a5	559
bogdanm	85:024bf7f99721	560	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	561	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	562
bogdanm	85:024bf7f99721	563	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	564	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	565
bogdanm	85:024bf7f99721	566	}RCC_PeriphCLKInitTypeDef;
bogdanm	92:4fc01daae5a5	567	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	568
Kojto	122:f9eeca106725	569	#if defined(CRS)
bogdanm	85:024bf7f99721	570
bogdanm	85:024bf7f99721	571	/**
bogdanm	85:024bf7f99721	572	* @brief RCC_CRS Init structure definition
bogdanm	85:024bf7f99721	573	*/
bogdanm	85:024bf7f99721	574	typedef struct
bogdanm	85:024bf7f99721	575	{
bogdanm	85:024bf7f99721	576	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
bogdanm	85:024bf7f99721	577	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
bogdanm	85:024bf7f99721	578
bogdanm	85:024bf7f99721	579	uint32_t Source; /*!< Specifies the SYNC signal source.
bogdanm	85:024bf7f99721	580	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
bogdanm	85:024bf7f99721	581
bogdanm	85:024bf7f99721	582	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
bogdanm	85:024bf7f99721	583	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
bogdanm	85:024bf7f99721	584
bogdanm	85:024bf7f99721	585	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
Kojto	122:f9eeca106725	586	It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
bogdanm	85:024bf7f99721	587	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
bogdanm	85:024bf7f99721	588
bogdanm	85:024bf7f99721	589	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
bogdanm	85:024bf7f99721	590	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
bogdanm	85:024bf7f99721	591
bogdanm	85:024bf7f99721	592	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
bogdanm	85:024bf7f99721	593	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
Kojto	122:f9eeca106725	594
bogdanm	85:024bf7f99721	595	}RCC_CRSInitTypeDef;
bogdanm	85:024bf7f99721	596
bogdanm	85:024bf7f99721	597	/**
bogdanm	85:024bf7f99721	598	* @brief RCC_CRS Synchronization structure definition
bogdanm	85:024bf7f99721	599	*/
bogdanm	85:024bf7f99721	600	typedef struct
bogdanm	85:024bf7f99721	601	{
bogdanm	85:024bf7f99721	602	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
Kojto	122:f9eeca106725	603	This parameter must be a number between 0 and 0xFFFF */
bogdanm	85:024bf7f99721	604
bogdanm	85:024bf7f99721	605	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
bogdanm	85:024bf7f99721	606	This parameter must be a number between 0 and 0x3F */
Kojto	122:f9eeca106725	607
bogdanm	85:024bf7f99721	608	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
bogdanm	85:024bf7f99721	609	value latched in the time of the last SYNC event.
bogdanm	85:024bf7f99721	610	This parameter must be a number between 0 and 0xFFFF */
Kojto	122:f9eeca106725	611
bogdanm	85:024bf7f99721	612	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
bogdanm	85:024bf7f99721	613	frequency error counter latched in the time of the last SYNC event.
bogdanm	85:024bf7f99721	614	It shows whether the actual frequency is below or above the target.
bogdanm	85:024bf7f99721	615	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
bogdanm	85:024bf7f99721	616
bogdanm	85:024bf7f99721	617	}RCC_CRSSynchroInfoTypeDef;
bogdanm	85:024bf7f99721	618
Kojto	122:f9eeca106725	619	#endif /* CRS */
bogdanm	92:4fc01daae5a5	620
bogdanm	92:4fc01daae5a5	621	/**
bogdanm	92:4fc01daae5a5	622	* @}
bogdanm	92:4fc01daae5a5	623	*/
bogdanm	85:024bf7f99721	624
bogdanm	85:024bf7f99721	625	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	626
bogdanm	92:4fc01daae5a5	627	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
bogdanm	85:024bf7f99721	628	* @{
bogdanm	85:024bf7f99721	629	*/
bogdanm	85:024bf7f99721	630
bogdanm	92:4fc01daae5a5	631	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
bogdanm	85:024bf7f99721	632	* @{
bogdanm	85:024bf7f99721	633	*/
Kojto	108:34e6b704fe68	634	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	108:34e6b704fe68	635	\|\| defined(STM32F030xC)
<>	134:ad3be0349dc5	636	#define RCC_PERIPHCLK_USART1 (0x00000001U)
<>	134:ad3be0349dc5	637	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
<>	134:ad3be0349dc5	638	#define RCC_PERIPHCLK_RTC (0x00010000U)
bogdanm	85:024bf7f99721	639
Kojto	93:e188a91d3eaa	640	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
Kojto	93:e188a91d3eaa	641	STM32F030xC */
Kojto	93:e188a91d3eaa	642
Kojto	93:e188a91d3eaa	643	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
<>	134:ad3be0349dc5	644	#define RCC_PERIPHCLK_USART1 (0x00000001U)
<>	134:ad3be0349dc5	645	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
<>	134:ad3be0349dc5	646	#define RCC_PERIPHCLK_RTC (0x00010000U)
<>	134:ad3be0349dc5	647	#define RCC_PERIPHCLK_USB (0x00020000U)
Kojto	93:e188a91d3eaa	648
Kojto	93:e188a91d3eaa	649	#endif /* STM32F070x6 \|\| STM32F070xB */
bogdanm	92:4fc01daae5a5	650
bogdanm	92:4fc01daae5a5	651	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
<>	134:ad3be0349dc5	652	#define RCC_PERIPHCLK_USART1 (0x00000001U)
<>	134:ad3be0349dc5	653	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
<>	134:ad3be0349dc5	654	#define RCC_PERIPHCLK_CEC (0x00000400U)
<>	134:ad3be0349dc5	655	#define RCC_PERIPHCLK_RTC (0x00010000U)
<>	134:ad3be0349dc5	656	#define RCC_PERIPHCLK_USB (0x00020000U)
bogdanm	92:4fc01daae5a5	657
bogdanm	92:4fc01daae5a5	658	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	85:024bf7f99721	659
bogdanm	85:024bf7f99721	660	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
<>	134:ad3be0349dc5	661	#define RCC_PERIPHCLK_USART1 (0x00000001U)
<>	134:ad3be0349dc5	662	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
<>	134:ad3be0349dc5	663	#define RCC_PERIPHCLK_CEC (0x00000400U)
<>	134:ad3be0349dc5	664	#define RCC_PERIPHCLK_RTC (0x00010000U)
bogdanm	85:024bf7f99721	665
bogdanm	85:024bf7f99721	666	#endif /* STM32F051x8 \|\| STM32F058xx */
bogdanm	85:024bf7f99721	667
bogdanm	85:024bf7f99721	668	#if defined(STM32F071xB)
<>	134:ad3be0349dc5	669	#define RCC_PERIPHCLK_USART1 (0x00000001U)
<>	134:ad3be0349dc5	670	#define RCC_PERIPHCLK_USART2 (0x00000002U)
<>	134:ad3be0349dc5	671	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
<>	134:ad3be0349dc5	672	#define RCC_PERIPHCLK_CEC (0x00000400U)
<>	134:ad3be0349dc5	673	#define RCC_PERIPHCLK_RTC (0x00010000U)
bogdanm	85:024bf7f99721	674
bogdanm	85:024bf7f99721	675	#endif /* STM32F071xB */
bogdanm	85:024bf7f99721	676
bogdanm	92:4fc01daae5a5	677	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
<>	134:ad3be0349dc5	678	#define RCC_PERIPHCLK_USART1 (0x00000001U)
<>	134:ad3be0349dc5	679	#define RCC_PERIPHCLK_USART2 (0x00000002U)
<>	134:ad3be0349dc5	680	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
<>	134:ad3be0349dc5	681	#define RCC_PERIPHCLK_CEC (0x00000400U)
<>	134:ad3be0349dc5	682	#define RCC_PERIPHCLK_RTC (0x00010000U)
<>	134:ad3be0349dc5	683	#define RCC_PERIPHCLK_USB (0x00020000U)
bogdanm	85:024bf7f99721	684
bogdanm	92:4fc01daae5a5	685	#endif /* STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	686
bogdanm	92:4fc01daae5a5	687	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
<>	134:ad3be0349dc5	688	#define RCC_PERIPHCLK_USART1 (0x00000001U)
<>	134:ad3be0349dc5	689	#define RCC_PERIPHCLK_USART2 (0x00000002U)
<>	134:ad3be0349dc5	690	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
<>	134:ad3be0349dc5	691	#define RCC_PERIPHCLK_CEC (0x00000400U)
<>	134:ad3be0349dc5	692	#define RCC_PERIPHCLK_RTC (0x00010000U)
<>	134:ad3be0349dc5	693	#define RCC_PERIPHCLK_USART3 (0x00040000U)
bogdanm	85:024bf7f99721	694
bogdanm	92:4fc01daae5a5	695	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	696
bogdanm	85:024bf7f99721	697	/**
bogdanm	85:024bf7f99721	698	* @}
bogdanm	85:024bf7f99721	699	*/
bogdanm	85:024bf7f99721	700
bogdanm	92:4fc01daae5a5	701	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	702
bogdanm	92:4fc01daae5a5	703	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
bogdanm	85:024bf7f99721	704	* @{
bogdanm	85:024bf7f99721	705	*/
Kojto	122:f9eeca106725	706	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /!< HSI48 clock selected as USB clock source /
Kojto	122:f9eeca106725	707	#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /!< PLL clock (PLLCLK) selected as USB clock /
bogdanm	85:024bf7f99721	708
bogdanm	85:024bf7f99721	709	/**
bogdanm	85:024bf7f99721	710	* @}
bogdanm	85:024bf7f99721	711	*/
bogdanm	85:024bf7f99721	712
bogdanm	92:4fc01daae5a5	713	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	714
Kojto	93:e188a91d3eaa	715	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	93:e188a91d3eaa	716
Kojto	93:e188a91d3eaa	717	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
Kojto	93:e188a91d3eaa	718	* @{
Kojto	93:e188a91d3eaa	719	*/
<>	134:ad3be0349dc5	720	#define RCC_USBCLKSOURCE_NONE (0x00000000U) /!< USB clock disabled /
Kojto	122:f9eeca106725	721	#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /!< PLL clock (PLLCLK) selected as USB clock /
Kojto	93:e188a91d3eaa	722
Kojto	93:e188a91d3eaa	723	/**
Kojto	93:e188a91d3eaa	724	* @}
Kojto	93:e188a91d3eaa	725	*/
Kojto	93:e188a91d3eaa	726
Kojto	93:e188a91d3eaa	727	#endif /* STM32F070x6 \|\| STM32F070xB */
Kojto	93:e188a91d3eaa	728
Kojto	108:34e6b704fe68	729	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	730	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	731
bogdanm	92:4fc01daae5a5	732	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
bogdanm	85:024bf7f99721	733	* @{
bogdanm	85:024bf7f99721	734	*/
bogdanm	85:024bf7f99721	735	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
bogdanm	85:024bf7f99721	736	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
bogdanm	85:024bf7f99721	737	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
bogdanm	85:024bf7f99721	738	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
bogdanm	85:024bf7f99721	739
bogdanm	85:024bf7f99721	740	/**
bogdanm	85:024bf7f99721	741	* @}
bogdanm	85:024bf7f99721	742	*/
bogdanm	85:024bf7f99721	743
bogdanm	92:4fc01daae5a5	744	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	745	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	746
bogdanm	92:4fc01daae5a5	747	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	748
bogdanm	92:4fc01daae5a5	749	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
bogdanm	92:4fc01daae5a5	750	* @{
bogdanm	92:4fc01daae5a5	751	*/
bogdanm	92:4fc01daae5a5	752	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
bogdanm	92:4fc01daae5a5	753	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
bogdanm	92:4fc01daae5a5	754	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
bogdanm	92:4fc01daae5a5	755	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
bogdanm	92:4fc01daae5a5	756
bogdanm	92:4fc01daae5a5	757	/**
bogdanm	92:4fc01daae5a5	758	* @}
bogdanm	92:4fc01daae5a5	759	*/
bogdanm	92:4fc01daae5a5	760
bogdanm	92:4fc01daae5a5	761	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	762
bogdanm	85:024bf7f99721	763
Kojto	108:34e6b704fe68	764	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	765	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	766	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	767	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	768
bogdanm	92:4fc01daae5a5	769	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
bogdanm	85:024bf7f99721	770	* @{
bogdanm	85:024bf7f99721	771	*/
bogdanm	85:024bf7f99721	772	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
bogdanm	85:024bf7f99721	773	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
bogdanm	85:024bf7f99721	774
bogdanm	85:024bf7f99721	775	/**
bogdanm	85:024bf7f99721	776	* @}
bogdanm	85:024bf7f99721	777	*/
bogdanm	85:024bf7f99721	778
bogdanm	92:4fc01daae5a5	779	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	780	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	781	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	782	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	783
bogdanm	92:4fc01daae5a5	784	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
bogdanm	92:4fc01daae5a5	785	* @{
bogdanm	92:4fc01daae5a5	786	*/
bogdanm	92:4fc01daae5a5	787
Kojto	122:f9eeca106725	788	#if defined(RCC_CFGR_MCOPRE)
Kojto	122:f9eeca106725	789
<>	134:ad3be0349dc5	790	#define RCC_MCODIV_1 (0x00000000U)
<>	134:ad3be0349dc5	791	#define RCC_MCODIV_2 (0x10000000U)
<>	134:ad3be0349dc5	792	#define RCC_MCODIV_4 (0x20000000U)
<>	134:ad3be0349dc5	793	#define RCC_MCODIV_8 (0x30000000U)
<>	134:ad3be0349dc5	794	#define RCC_MCODIV_16 (0x40000000U)
<>	134:ad3be0349dc5	795	#define RCC_MCODIV_32 (0x50000000U)
<>	134:ad3be0349dc5	796	#define RCC_MCODIV_64 (0x60000000U)
<>	134:ad3be0349dc5	797	#define RCC_MCODIV_128 (0x70000000U)
Kojto	122:f9eeca106725	798
Kojto	122:f9eeca106725	799	#else
bogdanm	85:024bf7f99721	800
<>	134:ad3be0349dc5	801	#define RCC_MCODIV_1 (0x00000000U)
bogdanm	85:024bf7f99721	802
Kojto	122:f9eeca106725	803	#endif /* RCC_CFGR_MCOPRE */
bogdanm	92:4fc01daae5a5	804
bogdanm	85:024bf7f99721	805	/**
bogdanm	85:024bf7f99721	806	* @}
bogdanm	85:024bf7f99721	807	*/
bogdanm	85:024bf7f99721	808
Kojto	122:f9eeca106725	809	/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
bogdanm	85:024bf7f99721	810	* @{
bogdanm	85:024bf7f99721	811	*/
Kojto	122:f9eeca106725	812
<>	134:ad3be0349dc5	813	#define RCC_LSEDRIVE_LOW (0x00000000U) /!< Xtal mode lower driving capability /
Kojto	122:f9eeca106725	814	#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /!< Xtal mode medium low driving capability /
Kojto	122:f9eeca106725	815	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /!< Xtal mode medium high driving capability /
Kojto	122:f9eeca106725	816	#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
Kojto	122:f9eeca106725	817
bogdanm	85:024bf7f99721	818	/**
bogdanm	85:024bf7f99721	819	* @}
bogdanm	85:024bf7f99721	820	*/
bogdanm	85:024bf7f99721	821
Kojto	122:f9eeca106725	822	#if defined(CRS)
Kojto	122:f9eeca106725	823
Kojto	122:f9eeca106725	824	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
bogdanm	85:024bf7f99721	825	* @{
bogdanm	85:024bf7f99721	826	*/
<>	134:ad3be0349dc5	827	#define RCC_CRS_NONE (0x00000000U)
<>	134:ad3be0349dc5	828	#define RCC_CRS_TIMEOUT (0x00000001U)
<>	134:ad3be0349dc5	829	#define RCC_CRS_SYNCOK (0x00000002U)
<>	134:ad3be0349dc5	830	#define RCC_CRS_SYNCWARN (0x00000004U)
<>	134:ad3be0349dc5	831	#define RCC_CRS_SYNCERR (0x00000008U)
<>	134:ad3be0349dc5	832	#define RCC_CRS_SYNCMISS (0x00000010U)
<>	134:ad3be0349dc5	833	#define RCC_CRS_TRIMOVF (0x00000020U)
Kojto	122:f9eeca106725	834
Kojto	122:f9eeca106725	835	/**
Kojto	122:f9eeca106725	836	* @}
Kojto	122:f9eeca106725	837	*/
Kojto	122:f9eeca106725	838
Kojto	122:f9eeca106725	839	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source
Kojto	122:f9eeca106725	840	* @{
Kojto	122:f9eeca106725	841	*/
Kojto	122:f9eeca106725	842	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /!< Synchro Signal source GPIO /
Kojto	122:f9eeca106725	843	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
Kojto	122:f9eeca106725	844	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
Kojto	122:f9eeca106725	845	/**
Kojto	122:f9eeca106725	846	* @}
Kojto	122:f9eeca106725	847	*/
Kojto	122:f9eeca106725	848
Kojto	122:f9eeca106725	849	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider
Kojto	122:f9eeca106725	850	* @{
Kojto	122:f9eeca106725	851	*/
Kojto	122:f9eeca106725	852	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /!< Synchro Signal not divided (default) /
bogdanm	85:024bf7f99721	853	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
bogdanm	85:024bf7f99721	854	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
bogdanm	85:024bf7f99721	855	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
bogdanm	85:024bf7f99721	856	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
bogdanm	85:024bf7f99721	857	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
bogdanm	85:024bf7f99721	858	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
bogdanm	85:024bf7f99721	859	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
bogdanm	85:024bf7f99721	860	/**
bogdanm	85:024bf7f99721	861	* @}
bogdanm	85:024bf7f99721	862	*/
bogdanm	85:024bf7f99721	863
Kojto	122:f9eeca106725	864	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity
bogdanm	85:024bf7f99721	865	* @{
bogdanm	85:024bf7f99721	866	*/
Kojto	122:f9eeca106725	867	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /!< Synchro Active on rising edge (default) /
Kojto	122:f9eeca106725	868	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
bogdanm	85:024bf7f99721	869	/**
bogdanm	85:024bf7f99721	870	* @}
bogdanm	85:024bf7f99721	871	*/
Kojto	122:f9eeca106725	872
Kojto	122:f9eeca106725	873	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value
bogdanm	85:024bf7f99721	874	* @{
bogdanm	85:024bf7f99721	875	*/
Kojto	122:f9eeca106725	876	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
Kojto	122:f9eeca106725	877	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
bogdanm	85:024bf7f99721	878	/**
bogdanm	85:024bf7f99721	879	* @}
bogdanm	85:024bf7f99721	880	*/
bogdanm	85:024bf7f99721	881
Kojto	122:f9eeca106725	882	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value
bogdanm	85:024bf7f99721	883	* @{
bogdanm	85:024bf7f99721	884	*/
Kojto	122:f9eeca106725	885	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /!< Default Frequency error limit /
bogdanm	85:024bf7f99721	886	/**
bogdanm	85:024bf7f99721	887	* @}
bogdanm	85:024bf7f99721	888	*/
bogdanm	85:024bf7f99721	889
Kojto	122:f9eeca106725	890	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye
bogdanm	85:024bf7f99721	891	* @{
bogdanm	85:024bf7f99721	892	*/
Kojto	122:f9eeca106725	893	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
Kojto	122:f9eeca106725	894	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
Kojto	122:f9eeca106725	895	corresponds to a higher output frequency */
bogdanm	85:024bf7f99721	896	/**
bogdanm	85:024bf7f99721	897	* @}
bogdanm	85:024bf7f99721	898	*/
bogdanm	85:024bf7f99721	899
Kojto	122:f9eeca106725	900	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction
bogdanm	85:024bf7f99721	901	* @{
bogdanm	85:024bf7f99721	902	*/
Kojto	122:f9eeca106725	903	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /!< Upcounting direction, the actual frequency is above the target /
Kojto	122:f9eeca106725	904	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
bogdanm	85:024bf7f99721	905	/**
bogdanm	85:024bf7f99721	906	* @}
bogdanm	85:024bf7f99721	907	*/
bogdanm	85:024bf7f99721	908
bogdanm	92:4fc01daae5a5	909	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
bogdanm	85:024bf7f99721	910	* @{
bogdanm	85:024bf7f99721	911	*/
Kojto	122:f9eeca106725	912	#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /!< SYNC event OK /
Kojto	122:f9eeca106725	913	#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /!< SYNC warning /
Kojto	122:f9eeca106725	914	#define RCC_CRS_IT_ERR CRS_CR_ERRIE /!< Error /
Kojto	122:f9eeca106725	915	#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /!< Expected SYNC /
Kojto	122:f9eeca106725	916	#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /!< SYNC error /
Kojto	122:f9eeca106725	917	#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /!< SYNC missed /
Kojto	122:f9eeca106725	918	#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /!< Trimming overflow or underflow /
bogdanm	85:024bf7f99721	919
bogdanm	85:024bf7f99721	920	/**
bogdanm	85:024bf7f99721	921	* @}
bogdanm	85:024bf7f99721	922	*/
bogdanm	85:024bf7f99721	923
bogdanm	92:4fc01daae5a5	924	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
bogdanm	85:024bf7f99721	925	* @{
bogdanm	85:024bf7f99721	926	*/
Kojto	122:f9eeca106725	927	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK flag /
Kojto	122:f9eeca106725	928	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning flag /
Kojto	122:f9eeca106725	929	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /!< Error flag /
Kojto	122:f9eeca106725	930	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC flag /
Kojto	122:f9eeca106725	931	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
Kojto	122:f9eeca106725	932	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
Kojto	122:f9eeca106725	933	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	85:024bf7f99721	934
bogdanm	85:024bf7f99721	935	/**
bogdanm	85:024bf7f99721	936	* @}
bogdanm	85:024bf7f99721	937	*/
bogdanm	85:024bf7f99721	938
Kojto	122:f9eeca106725	939	#endif /* CRS */
Kojto	93:e188a91d3eaa	940
bogdanm	85:024bf7f99721	941	/**
bogdanm	85:024bf7f99721	942	* @}
bogdanm	85:024bf7f99721	943	*/
bogdanm	85:024bf7f99721	944
bogdanm	92:4fc01daae5a5	945	/* Exported macros ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	946	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
bogdanm	85:024bf7f99721	947	* @{
bogdanm	85:024bf7f99721	948	*/
bogdanm	85:024bf7f99721	949
bogdanm	92:4fc01daae5a5	950	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
bogdanm	92:4fc01daae5a5	951	* @brief Enables or disables the AHB1 peripheral clock.
bogdanm	85:024bf7f99721	952	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	953	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	954	* using it.
bogdanm	92:4fc01daae5a5	955	* @{
bogdanm	85:024bf7f99721	956	*/
Kojto	122:f9eeca106725	957	#if defined(GPIOD)
bogdanm	85:024bf7f99721	958
Kojto	108:34e6b704fe68	959	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	960	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	961	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
Kojto	108:34e6b704fe68	962	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	963	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
Kojto	108:34e6b704fe68	964	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	965	} while(0)
bogdanm	85:024bf7f99721	966
Kojto	108:34e6b704fe68	967	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
bogdanm	85:024bf7f99721	968
Kojto	122:f9eeca106725	969	#endif /* GPIOD */
bogdanm	85:024bf7f99721	970
Kojto	122:f9eeca106725	971	#if defined(GPIOE)
bogdanm	85:024bf7f99721	972
Kojto	108:34e6b704fe68	973	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	974	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	975	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
Kojto	108:34e6b704fe68	976	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	977	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
Kojto	108:34e6b704fe68	978	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	979	} while(0)
bogdanm	85:024bf7f99721	980
Kojto	108:34e6b704fe68	981	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
bogdanm	85:024bf7f99721	982
Kojto	122:f9eeca106725	983	#endif /* GPIOE */
bogdanm	85:024bf7f99721	984
Kojto	108:34e6b704fe68	985	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	986	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	987	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	988	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	989
Kojto	108:34e6b704fe68	990	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	991	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	992	SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
Kojto	108:34e6b704fe68	993	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	994	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
Kojto	108:34e6b704fe68	995	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	996	} while(0)
bogdanm	85:024bf7f99721	997
Kojto	108:34e6b704fe68	998	#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
bogdanm	85:024bf7f99721	999
bogdanm	92:4fc01daae5a5	1000	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1001	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1002	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1003	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1004
bogdanm	92:4fc01daae5a5	1005	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1006
Kojto	108:34e6b704fe68	1007	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1008	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1009	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto	108:34e6b704fe68	1010	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1011	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto	108:34e6b704fe68	1012	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1013	} while(0)
bogdanm	92:4fc01daae5a5	1014
Kojto	108:34e6b704fe68	1015	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
bogdanm	92:4fc01daae5a5	1016
bogdanm	92:4fc01daae5a5	1017	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1018
bogdanm	85:024bf7f99721	1019	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	85:024bf7f99721	1020	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	1021	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	1022	* using it.
bogdanm	85:024bf7f99721	1023	*/
Kojto	108:34e6b704fe68	1024	#if defined(STM32F030x8)\
Kojto	108:34e6b704fe68	1025	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1026	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1027	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1028	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1029
Kojto	108:34e6b704fe68	1030	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1031	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1032	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	108:34e6b704fe68	1033	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1034	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	108:34e6b704fe68	1035	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1036	} while(0)
Kojto	108:34e6b704fe68	1037
Kojto	108:34e6b704fe68	1038	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm	85:024bf7f99721	1039
Kojto	108:34e6b704fe68	1040	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	1041	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
Kojto	108:34e6b704fe68	1042	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1043	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1044
Kojto	108:34e6b704fe68	1045	#if defined(STM32F030x8)\
Kojto	108:34e6b704fe68	1046	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1047	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1048	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1049	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1050
Kojto	108:34e6b704fe68	1051	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1052	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1053	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto	108:34e6b704fe68	1054	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1055	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto	108:34e6b704fe68	1056	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1057	} while(0)
Kojto	108:34e6b704fe68	1058
Kojto	108:34e6b704fe68	1059	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm	85:024bf7f99721	1060
bogdanm	92:4fc01daae5a5	1061	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1062	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1063	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1064	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1065
Kojto	108:34e6b704fe68	1066	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	108:34e6b704fe68	1067	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1068	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1069	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1070	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1071
Kojto	108:34e6b704fe68	1072	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1073	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1074	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	108:34e6b704fe68	1075	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1076	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	108:34e6b704fe68	1077	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1078	} while(0)
bogdanm	85:024bf7f99721	1079
Kojto	108:34e6b704fe68	1080	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm	85:024bf7f99721	1081
bogdanm	92:4fc01daae5a5	1082	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
bogdanm	92:4fc01daae5a5	1083	/* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	1084	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1085	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1086	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1087
Kojto	108:34e6b704fe68	1088	#if defined(STM32F030x8) \
Kojto	108:34e6b704fe68	1089	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1090	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1091	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1092
Kojto	108:34e6b704fe68	1093	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1094	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1095	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	108:34e6b704fe68	1096	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1097	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	108:34e6b704fe68	1098	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1099	} while(0)
Kojto	108:34e6b704fe68	1100	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1101	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1102	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto	108:34e6b704fe68	1103	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1104	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto	108:34e6b704fe68	1105	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1106	} while(0)
bogdanm	85:024bf7f99721	1107
Kojto	108:34e6b704fe68	1108	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	108:34e6b704fe68	1109	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm	85:024bf7f99721	1110
bogdanm	85:024bf7f99721	1111	#endif /* STM32F030x8 \|\| */
bogdanm	85:024bf7f99721	1112	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1113	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1114	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1115
Kojto	108:34e6b704fe68	1116	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1117	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1118	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1119
Kojto	108:34e6b704fe68	1120	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1121	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1122	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	108:34e6b704fe68	1123	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1124	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	108:34e6b704fe68	1125	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1126	} while(0)
bogdanm	85:024bf7f99721	1127
Kojto	108:34e6b704fe68	1128	#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm	85:024bf7f99721	1129
bogdanm	85:024bf7f99721	1130	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1131	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1132	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1133
Kojto	108:34e6b704fe68	1134	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1135	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1136	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1137	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1138
Kojto	108:34e6b704fe68	1139	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1140	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1141	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	108:34e6b704fe68	1142	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1143	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	108:34e6b704fe68	1144	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1145	} while(0)
bogdanm	85:024bf7f99721	1146
Kojto	108:34e6b704fe68	1147	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
bogdanm	85:024bf7f99721	1148
bogdanm	92:4fc01daae5a5	1149	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1150	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1151	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1152	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1153
Kojto	108:34e6b704fe68	1154	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1155	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1156
Kojto	108:34e6b704fe68	1157	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1158	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1159	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	108:34e6b704fe68	1160	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1161	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	108:34e6b704fe68	1162	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1163	} while(0)
Kojto	108:34e6b704fe68	1164	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1165	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1166	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	108:34e6b704fe68	1167	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1168	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	108:34e6b704fe68	1169	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1170	} while(0)
Kojto	108:34e6b704fe68	1171	#define __HAL_RCC_USART4_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1172	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1173	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
Kojto	108:34e6b704fe68	1174	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1175	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
Kojto	108:34e6b704fe68	1176	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1177	} while(0)
bogdanm	85:024bf7f99721	1178
Kojto	108:34e6b704fe68	1179	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	108:34e6b704fe68	1180	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	108:34e6b704fe68	1181	#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
bogdanm	85:024bf7f99721	1182
Kojto	93:e188a91d3eaa	1183	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1184	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1185
Kojto	108:34e6b704fe68	1186	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1187	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
bogdanm	85:024bf7f99721	1188
Kojto	108:34e6b704fe68	1189	#define __HAL_RCC_USB_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1190	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1191	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
Kojto	108:34e6b704fe68	1192	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1193	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
Kojto	108:34e6b704fe68	1194	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1195	} while(0)
bogdanm	85:024bf7f99721	1196
Kojto	108:34e6b704fe68	1197	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
bogdanm	85:024bf7f99721	1198
Kojto	93:e188a91d3eaa	1199	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	93:e188a91d3eaa	1200	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
bogdanm	85:024bf7f99721	1201
Kojto	108:34e6b704fe68	1202	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
Kojto	108:34e6b704fe68	1203	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1204
Kojto	108:34e6b704fe68	1205	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1206	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1207	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
Kojto	108:34e6b704fe68	1208	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1209	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
Kojto	108:34e6b704fe68	1210	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1211	} while(0)
Kojto	108:34e6b704fe68	1212	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
bogdanm	85:024bf7f99721	1213
bogdanm	92:4fc01daae5a5	1214	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
bogdanm	92:4fc01daae5a5	1215	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1216
Kojto	122:f9eeca106725	1217	#if defined(CRS)
bogdanm	85:024bf7f99721	1218
Kojto	108:34e6b704fe68	1219	#define __HAL_RCC_CRS_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1220	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1221	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
Kojto	108:34e6b704fe68	1222	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1223	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
Kojto	108:34e6b704fe68	1224	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1225	} while(0)
bogdanm	85:024bf7f99721	1226
Kojto	108:34e6b704fe68	1227	#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
bogdanm	85:024bf7f99721	1228
Kojto	122:f9eeca106725	1229	#endif /* CRS */
bogdanm	92:4fc01daae5a5	1230
Kojto	93:e188a91d3eaa	1231	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	92:4fc01daae5a5	1232
Kojto	108:34e6b704fe68	1233	#define __HAL_RCC_USART5_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1234	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1235	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
Kojto	108:34e6b704fe68	1236	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1237	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
Kojto	108:34e6b704fe68	1238	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1239	} while(0)
bogdanm	92:4fc01daae5a5	1240
Kojto	108:34e6b704fe68	1241	#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
bogdanm	92:4fc01daae5a5	1242
Kojto	93:e188a91d3eaa	1243	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1244
bogdanm	85:024bf7f99721	1245	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	85:024bf7f99721	1246	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	1247	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	1248	* using it.
bogdanm	85:024bf7f99721	1249	*/
Kojto	108:34e6b704fe68	1250	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1251	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1252	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1253	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1254
Kojto	108:34e6b704fe68	1255	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1256	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1257	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
Kojto	108:34e6b704fe68	1258	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1259	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
Kojto	108:34e6b704fe68	1260	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1261	} while(0)
bogdanm	85:024bf7f99721	1262
Kojto	108:34e6b704fe68	1263	#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
bogdanm	85:024bf7f99721	1264
Kojto	93:e188a91d3eaa	1265	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	85:024bf7f99721	1266	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1267	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1268	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	93:e188a91d3eaa	1269
Kojto	93:e188a91d3eaa	1270	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	93:e188a91d3eaa	1271
Kojto	108:34e6b704fe68	1272	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1273	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1274	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto	108:34e6b704fe68	1275	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1276	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto	108:34e6b704fe68	1277	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1278	} while(0)
Kojto	93:e188a91d3eaa	1279
Kojto	108:34e6b704fe68	1280	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto	93:e188a91d3eaa	1281
Kojto	93:e188a91d3eaa	1282	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	92:4fc01daae5a5	1283
bogdanm	92:4fc01daae5a5	1284	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	1285
Kojto	108:34e6b704fe68	1286	#define __HAL_RCC_USART7_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1287	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1288	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
Kojto	108:34e6b704fe68	1289	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1290	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
Kojto	108:34e6b704fe68	1291	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1292	} while(0)
Kojto	108:34e6b704fe68	1293	#define __HAL_RCC_USART8_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1294	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1295	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
Kojto	108:34e6b704fe68	1296	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1297	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
Kojto	108:34e6b704fe68	1298	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1299	} while(0)
bogdanm	92:4fc01daae5a5	1300
Kojto	108:34e6b704fe68	1301	#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
Kojto	108:34e6b704fe68	1302	#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
bogdanm	92:4fc01daae5a5	1303
bogdanm	92:4fc01daae5a5	1304	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1305
bogdanm	92:4fc01daae5a5	1306	/**
bogdanm	92:4fc01daae5a5	1307	* @}
bogdanm	92:4fc01daae5a5	1308	*/
bogdanm	92:4fc01daae5a5	1309
bogdanm	92:4fc01daae5a5	1310
bogdanm	92:4fc01daae5a5	1311	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
bogdanm	92:4fc01daae5a5	1312	* @brief Forces or releases peripheral reset.
bogdanm	92:4fc01daae5a5	1313	* @{
bogdanm	92:4fc01daae5a5	1314	*/
bogdanm	85:024bf7f99721	1315
bogdanm	85:024bf7f99721	1316	/** @brief Force or release AHB peripheral reset.
bogdanm	85:024bf7f99721	1317	*/
Kojto	122:f9eeca106725	1318	#if defined(GPIOD)
bogdanm	85:024bf7f99721	1319
Kojto	108:34e6b704fe68	1320	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
bogdanm	85:024bf7f99721	1321
Kojto	108:34e6b704fe68	1322	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
bogdanm	85:024bf7f99721	1323
Kojto	122:f9eeca106725	1324	#endif /* GPIOD */
bogdanm	85:024bf7f99721	1325
Kojto	122:f9eeca106725	1326	#if defined(GPIOE)
bogdanm	85:024bf7f99721	1327
Kojto	108:34e6b704fe68	1328	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
bogdanm	85:024bf7f99721	1329
Kojto	108:34e6b704fe68	1330	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
bogdanm	85:024bf7f99721	1331
Kojto	122:f9eeca106725	1332	#endif /* GPIOE */
bogdanm	85:024bf7f99721	1333
Kojto	108:34e6b704fe68	1334	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1335	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1336	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1337	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1338
Kojto	108:34e6b704fe68	1339	#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
bogdanm	85:024bf7f99721	1340
Kojto	108:34e6b704fe68	1341	#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
bogdanm	85:024bf7f99721	1342
bogdanm	92:4fc01daae5a5	1343	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1344	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1345	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1346	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1347
bogdanm	85:024bf7f99721	1348	/** @brief Force or release APB1 peripheral reset.
bogdanm	85:024bf7f99721	1349	*/
Kojto	108:34e6b704fe68	1350	#if defined(STM32F030x8) \
Kojto	108:34e6b704fe68	1351	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1352	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1353	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1354	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1355
Kojto	108:34e6b704fe68	1356	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	108:34e6b704fe68	1357	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	85:024bf7f99721	1358
Kojto	108:34e6b704fe68	1359	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto	108:34e6b704fe68	1360	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm	85:024bf7f99721	1361
Kojto	93:e188a91d3eaa	1362	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	85:024bf7f99721	1363	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1364	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1365	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1366
Kojto	108:34e6b704fe68	1367	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	108:34e6b704fe68	1368	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1369	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1370	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1371	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1372
Kojto	108:34e6b704fe68	1373	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	85:024bf7f99721	1374
Kojto	108:34e6b704fe68	1375	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm	85:024bf7f99721	1376
bogdanm	92:4fc01daae5a5	1377	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
bogdanm	92:4fc01daae5a5	1378	/* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	1379	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1380	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1381	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1382
Kojto	108:34e6b704fe68	1383	#if defined(STM32F030x8) \
Kojto	108:34e6b704fe68	1384	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1385	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1386	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1387
Kojto	108:34e6b704fe68	1388	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	108:34e6b704fe68	1389	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	85:024bf7f99721	1390
Kojto	108:34e6b704fe68	1391	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	108:34e6b704fe68	1392	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm	85:024bf7f99721	1393
bogdanm	85:024bf7f99721	1394	#endif /* STM32F030x8 \|\| */
bogdanm	85:024bf7f99721	1395	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1396	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1397	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1398
Kojto	108:34e6b704fe68	1399	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1400	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1401	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1402
Kojto	108:34e6b704fe68	1403	#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	85:024bf7f99721	1404
Kojto	108:34e6b704fe68	1405	#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm	85:024bf7f99721	1406
bogdanm	85:024bf7f99721	1407	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1408	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1409	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1410
Kojto	108:34e6b704fe68	1411	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1412	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1413	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1414	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1415
Kojto	108:34e6b704fe68	1416	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
bogdanm	85:024bf7f99721	1417
Kojto	108:34e6b704fe68	1418	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
bogdanm	85:024bf7f99721	1419
bogdanm	92:4fc01daae5a5	1420	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1421	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1422	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1423	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1424
Kojto	108:34e6b704fe68	1425	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1426	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1427
Kojto	108:34e6b704fe68	1428	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	108:34e6b704fe68	1429	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	108:34e6b704fe68	1430	#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
bogdanm	85:024bf7f99721	1431
Kojto	108:34e6b704fe68	1432	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	108:34e6b704fe68	1433	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	108:34e6b704fe68	1434	#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
bogdanm	85:024bf7f99721	1435
Kojto	93:e188a91d3eaa	1436	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1437	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1438
Kojto	108:34e6b704fe68	1439	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1440	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
bogdanm	85:024bf7f99721	1441
Kojto	108:34e6b704fe68	1442	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
bogdanm	85:024bf7f99721	1443
Kojto	108:34e6b704fe68	1444	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
bogdanm	85:024bf7f99721	1445
Kojto	93:e188a91d3eaa	1446	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	93:e188a91d3eaa	1447	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
bogdanm	85:024bf7f99721	1448
Kojto	108:34e6b704fe68	1449	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
Kojto	108:34e6b704fe68	1450	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1451
Kojto	108:34e6b704fe68	1452	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
bogdanm	85:024bf7f99721	1453
Kojto	108:34e6b704fe68	1454	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
bogdanm	85:024bf7f99721	1455
bogdanm	92:4fc01daae5a5	1456	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
bogdanm	92:4fc01daae5a5	1457	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1458
Kojto	122:f9eeca106725	1459	#if defined(CRS)
bogdanm	85:024bf7f99721	1460
Kojto	108:34e6b704fe68	1461	#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
bogdanm	85:024bf7f99721	1462
Kojto	108:34e6b704fe68	1463	#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
bogdanm	85:024bf7f99721	1464
Kojto	122:f9eeca106725	1465	#endif /* CRS */
bogdanm	92:4fc01daae5a5	1466
Kojto	93:e188a91d3eaa	1467	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	92:4fc01daae5a5	1468
Kojto	108:34e6b704fe68	1469	#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
bogdanm	92:4fc01daae5a5	1470
Kojto	108:34e6b704fe68	1471	#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
bogdanm	92:4fc01daae5a5	1472
Kojto	93:e188a91d3eaa	1473	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1474
bogdanm	85:024bf7f99721	1475
bogdanm	85:024bf7f99721	1476	/** @brief Force or release APB2 peripheral reset.
bogdanm	85:024bf7f99721	1477	*/
Kojto	108:34e6b704fe68	1478	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1479	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1480	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1481	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1482
Kojto	108:34e6b704fe68	1483	#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
bogdanm	85:024bf7f99721	1484
Kojto	108:34e6b704fe68	1485	#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
bogdanm	85:024bf7f99721	1486
Kojto	93:e188a91d3eaa	1487	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	85:024bf7f99721	1488	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1489	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1490	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	93:e188a91d3eaa	1491
Kojto	93:e188a91d3eaa	1492	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	93:e188a91d3eaa	1493
Kojto	108:34e6b704fe68	1494	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
Kojto	93:e188a91d3eaa	1495
Kojto	108:34e6b704fe68	1496	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto	93:e188a91d3eaa	1497
Kojto	93:e188a91d3eaa	1498	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	92:4fc01daae5a5	1499
bogdanm	92:4fc01daae5a5	1500	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	1501
Kojto	108:34e6b704fe68	1502	#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART7RST))
Kojto	108:34e6b704fe68	1503	#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART8RST))
bogdanm	85:024bf7f99721	1504
Kojto	108:34e6b704fe68	1505	#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
Kojto	108:34e6b704fe68	1506	#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
bogdanm	92:4fc01daae5a5	1507
bogdanm	92:4fc01daae5a5	1508	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1509
bogdanm	92:4fc01daae5a5	1510	/**
bogdanm	92:4fc01daae5a5	1511	* @}
bogdanm	92:4fc01daae5a5	1512	*/
Kojto	108:34e6b704fe68	1513
Kojto	108:34e6b704fe68	1514	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
Kojto	108:34e6b704fe68	1515	* @brief Get the enable or disable status of peripheral clock.
Kojto	108:34e6b704fe68	1516	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	108:34e6b704fe68	1517	* is disabled and the application software has to enable this clock before
Kojto	108:34e6b704fe68	1518	* using it.
Kojto	108:34e6b704fe68	1519	* @{
Kojto	108:34e6b704fe68	1520	*/
Kojto	108:34e6b704fe68	1521	/** @brief AHB Peripheral Clock Enable Disable Status
Kojto	108:34e6b704fe68	1522	*/
Kojto	122:f9eeca106725	1523	#if defined(GPIOD)
Kojto	108:34e6b704fe68	1524
Kojto	108:34e6b704fe68	1525	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
Kojto	108:34e6b704fe68	1526	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
Kojto	108:34e6b704fe68	1527
Kojto	122:f9eeca106725	1528	#endif /* GPIOD */
Kojto	108:34e6b704fe68	1529
Kojto	122:f9eeca106725	1530	#if defined(GPIOE)
Kojto	108:34e6b704fe68	1531
Kojto	108:34e6b704fe68	1532	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
Kojto	108:34e6b704fe68	1533	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
Kojto	108:34e6b704fe68	1534
Kojto	122:f9eeca106725	1535	#endif /* GPIOE */
Kojto	108:34e6b704fe68	1536
Kojto	108:34e6b704fe68	1537	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1538	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1539	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1540	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1541
Kojto	108:34e6b704fe68	1542	#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
Kojto	108:34e6b704fe68	1543	#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
Kojto	108:34e6b704fe68	1544
Kojto	108:34e6b704fe68	1545	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	1546	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1547	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	1548	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1549
Kojto	108:34e6b704fe68	1550	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1551
Kojto	108:34e6b704fe68	1552	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
Kojto	108:34e6b704fe68	1553	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
Kojto	108:34e6b704fe68	1554
Kojto	108:34e6b704fe68	1555	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1556
Kojto	108:34e6b704fe68	1557	/** @brief APB1 Peripheral Clock Enable Disable Status
Kojto	108:34e6b704fe68	1558	*/
Kojto	108:34e6b704fe68	1559	#if defined(STM32F030x8)\
Kojto	108:34e6b704fe68	1560	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1561	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1562	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1563	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1564
Kojto	108:34e6b704fe68	1565	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
Kojto	108:34e6b704fe68	1566	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Kojto	108:34e6b704fe68	1567
Kojto	108:34e6b704fe68	1568	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	1569	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
Kojto	108:34e6b704fe68	1570	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1571	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1572
Kojto	108:34e6b704fe68	1573	#if defined(STM32F030x8)\
Kojto	108:34e6b704fe68	1574	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1575	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1576	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1577	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1578
Kojto	108:34e6b704fe68	1579	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Kojto	108:34e6b704fe68	1580	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Kojto	108:34e6b704fe68	1581
Kojto	108:34e6b704fe68	1582	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	1583	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1584	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1585	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1586
Kojto	108:34e6b704fe68	1587	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	108:34e6b704fe68	1588	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1589	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1590	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1591	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1592
Kojto	108:34e6b704fe68	1593	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	108:34e6b704fe68	1594	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	108:34e6b704fe68	1595
Kojto	108:34e6b704fe68	1596	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
Kojto	108:34e6b704fe68	1597	/* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	1598	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1599	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	1600	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1601
Kojto	108:34e6b704fe68	1602	#if defined(STM32F030x8) \
Kojto	108:34e6b704fe68	1603	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1604	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1605	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1606
Kojto	108:34e6b704fe68	1607	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	108:34e6b704fe68	1608	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Kojto	108:34e6b704fe68	1609	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	108:34e6b704fe68	1610	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Kojto	108:34e6b704fe68	1611
Kojto	108:34e6b704fe68	1612	#endif /* STM32F030x8 \|\| */
Kojto	108:34e6b704fe68	1613	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1614	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1615	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1616
Kojto	108:34e6b704fe68	1617	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1618	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1619	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1620
Kojto	108:34e6b704fe68	1621	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
Kojto	108:34e6b704fe68	1622	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
Kojto	108:34e6b704fe68	1623
Kojto	108:34e6b704fe68	1624	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1625	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	1626	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1627
Kojto	108:34e6b704fe68	1628	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1629	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1630	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1631	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1632
Kojto	108:34e6b704fe68	1633	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
Kojto	108:34e6b704fe68	1634	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Kojto	108:34e6b704fe68	1635
Kojto	108:34e6b704fe68	1636	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	1637	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1638	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	1639	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1640
Kojto	108:34e6b704fe68	1641	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1642	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1643
Kojto	108:34e6b704fe68	1644	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto	108:34e6b704fe68	1645	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto	108:34e6b704fe68	1646	#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET)
Kojto	108:34e6b704fe68	1647	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto	108:34e6b704fe68	1648	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto	108:34e6b704fe68	1649	#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET)
Kojto	108:34e6b704fe68	1650
Kojto	108:34e6b704fe68	1651	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1652	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1653
Kojto	108:34e6b704fe68	1654	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1655	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
Kojto	108:34e6b704fe68	1656
Kojto	108:34e6b704fe68	1657	#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
Kojto	108:34e6b704fe68	1658	#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
Kojto	108:34e6b704fe68	1659
Kojto	108:34e6b704fe68	1660	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	108:34e6b704fe68	1661	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
Kojto	108:34e6b704fe68	1662
Kojto	108:34e6b704fe68	1663	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
Kojto	108:34e6b704fe68	1664	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1665
Kojto	108:34e6b704fe68	1666	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
Kojto	108:34e6b704fe68	1667	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto	108:34e6b704fe68	1668
Kojto	108:34e6b704fe68	1669	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
Kojto	108:34e6b704fe68	1670	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1671
Kojto	122:f9eeca106725	1672	#if defined(CRS)
Kojto	108:34e6b704fe68	1673
Kojto	108:34e6b704fe68	1674	#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET)
Kojto	108:34e6b704fe68	1675	#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET)
Kojto	108:34e6b704fe68	1676
Kojto	122:f9eeca106725	1677	#endif /* CRS */
Kojto	108:34e6b704fe68	1678
Kojto	108:34e6b704fe68	1679	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1680
Kojto	108:34e6b704fe68	1681	#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET)
Kojto	108:34e6b704fe68	1682	#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET)
Kojto	108:34e6b704fe68	1683
Kojto	108:34e6b704fe68	1684	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1685
Kojto	108:34e6b704fe68	1686	/** @brief APB1 Peripheral Clock Enable Disable Status
Kojto	108:34e6b704fe68	1687	*/
Kojto	108:34e6b704fe68	1688	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1689	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1690	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1691	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1692
Kojto	108:34e6b704fe68	1693	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
Kojto	108:34e6b704fe68	1694	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
Kojto	108:34e6b704fe68	1695
Kojto	108:34e6b704fe68	1696	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	108:34e6b704fe68	1697	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1698	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1699	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1700
Kojto	108:34e6b704fe68	1701	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1702
Kojto	108:34e6b704fe68	1703	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
Kojto	108:34e6b704fe68	1704	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
Kojto	108:34e6b704fe68	1705
Kojto	108:34e6b704fe68	1706	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1707
Kojto	108:34e6b704fe68	1708	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1709
Kojto	108:34e6b704fe68	1710	#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET)
Kojto	108:34e6b704fe68	1711	#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET)
Kojto	108:34e6b704fe68	1712	#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET)
Kojto	108:34e6b704fe68	1713	#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET)
Kojto	108:34e6b704fe68	1714
Kojto	108:34e6b704fe68	1715	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1716	/**
Kojto	108:34e6b704fe68	1717	* @}
Kojto	108:34e6b704fe68	1718	*/
Kojto	108:34e6b704fe68	1719
bogdanm	92:4fc01daae5a5	1720
bogdanm	92:4fc01daae5a5	1721	/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
bogdanm	92:4fc01daae5a5	1722	* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
bogdanm	85:024bf7f99721	1723	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	85:024bf7f99721	1724	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
bogdanm	85:024bf7f99721	1725	* you have to select another source of the system clock then stop the HSI14.
bogdanm	85:024bf7f99721	1726	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
bogdanm	85:024bf7f99721	1727	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
bogdanm	85:024bf7f99721	1728	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
bogdanm	85:024bf7f99721	1729	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
bogdanm	85:024bf7f99721	1730	* clock cycles.
bogdanm	92:4fc01daae5a5	1731	* @{
bogdanm	85:024bf7f99721	1732	*/
Kojto	122:f9eeca106725	1733	#if defined(RCC_HSI48_SUPPORT)
bogdanm	92:4fc01daae5a5	1734
bogdanm	85:024bf7f99721	1735	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
bogdanm	85:024bf7f99721	1736	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
bogdanm	85:024bf7f99721	1737
bogdanm	85:024bf7f99721	1738	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
bogdanm	85:024bf7f99721	1739	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	1740	* @arg @ref RCC_HSI48_ON HSI48 enabled
Kojto	122:f9eeca106725	1741	* @arg @ref RCC_HSI48_OFF HSI48 disabled
bogdanm	85:024bf7f99721	1742	*/
bogdanm	85:024bf7f99721	1743	#define __HAL_RCC_GET_HSI48_STATE() \
Kojto	122:f9eeca106725	1744	(((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
bogdanm	85:024bf7f99721	1745
Kojto	122:f9eeca106725	1746	#endif /* RCC_HSI48_SUPPORT */
bogdanm	85:024bf7f99721	1747
bogdanm	92:4fc01daae5a5	1748	/**
bogdanm	92:4fc01daae5a5	1749	* @}
bogdanm	92:4fc01daae5a5	1750	*/
bogdanm	92:4fc01daae5a5	1751
bogdanm	92:4fc01daae5a5	1752	/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
bogdanm	92:4fc01daae5a5	1753	* @{
bogdanm	92:4fc01daae5a5	1754	*/
Kojto	108:34e6b704fe68	1755	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1756	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1757	\|\| defined(STM32F070x6) \|\| defined(STM32F070xB)
bogdanm	85:024bf7f99721	1758
bogdanm	85:024bf7f99721	1759	/** @brief Macro to configure the USB clock (USBCLK).
Kojto	122:f9eeca106725	1760	* @param __USBCLKSOURCE__ specifies the USB clock source.
bogdanm	85:024bf7f99721	1761	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1762	@if STM32F070xB
Kojto	122:f9eeca106725	1763	@elseif STM32F070x6
Kojto	122:f9eeca106725	1764	@else
Kojto	122:f9eeca106725	1765	* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
Kojto	122:f9eeca106725	1766	@endif
Kojto	122:f9eeca106725	1767	* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
bogdanm	85:024bf7f99721	1768	*/
Kojto	122:f9eeca106725	1769	#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
Kojto	122:f9eeca106725	1770	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSOURCE__))
bogdanm	85:024bf7f99721	1771
bogdanm	85:024bf7f99721	1772	/** @brief Macro to get the USB clock source.
bogdanm	85:024bf7f99721	1773	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	1774	@if STM32F070xB
Kojto	122:f9eeca106725	1775	@elseif STM32F070x6
Kojto	122:f9eeca106725	1776	@else
Kojto	122:f9eeca106725	1777	* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
Kojto	122:f9eeca106725	1778	@endif
Kojto	122:f9eeca106725	1779	* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
bogdanm	85:024bf7f99721	1780	*/
bogdanm	85:024bf7f99721	1781	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
bogdanm	85:024bf7f99721	1782
bogdanm	92:4fc01daae5a5	1783	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	93:e188a91d3eaa	1784	/* STM32F072xB \|\| STM32F078xx \|\| */
Kojto	93:e188a91d3eaa	1785	/* STM32F070x6 \|\| STM32F070xB */
bogdanm	85:024bf7f99721	1786
Kojto	108:34e6b704fe68	1787	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1788	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1789	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1790	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1791
bogdanm	85:024bf7f99721	1792	/** @brief Macro to configure the CEC clock.
Kojto	122:f9eeca106725	1793	* @param __CECCLKSOURCE__ specifies the CEC clock source.
bogdanm	85:024bf7f99721	1794	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1795	* @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
Kojto	122:f9eeca106725	1796	* @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
bogdanm	85:024bf7f99721	1797	*/
Kojto	122:f9eeca106725	1798	#define __HAL_RCC_CEC_CONFIG(__CECCLKSOURCE__) \
Kojto	122:f9eeca106725	1799	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSOURCE__))
bogdanm	85:024bf7f99721	1800
bogdanm	85:024bf7f99721	1801	/** @brief Macro to get the HDMI CEC clock source.
bogdanm	85:024bf7f99721	1802	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	1803	* @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
Kojto	122:f9eeca106725	1804	* @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
bogdanm	85:024bf7f99721	1805	*/
bogdanm	85:024bf7f99721	1806	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
bogdanm	85:024bf7f99721	1807
bogdanm	92:4fc01daae5a5	1808	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1809	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1810	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1811	/* STM32F091xC \|\| defined(STM32F098xx) */
bogdanm	85:024bf7f99721	1812
Kojto	108:34e6b704fe68	1813	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1814	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	93:e188a91d3eaa	1815	/** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto	122:f9eeca106725	1816	* @param __USART2CLKSOURCE__ specifies the USART2 clock source.
Kojto	93:e188a91d3eaa	1817	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1818	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
Kojto	122:f9eeca106725	1819	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
Kojto	122:f9eeca106725	1820	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
Kojto	122:f9eeca106725	1821	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
Kojto	93:e188a91d3eaa	1822	*/
Kojto	122:f9eeca106725	1823	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
Kojto	122:f9eeca106725	1824	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
Kojto	93:e188a91d3eaa	1825
Kojto	93:e188a91d3eaa	1826	/** @brief Macro to get the USART2 clock source.
Kojto	93:e188a91d3eaa	1827	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	1828	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
Kojto	122:f9eeca106725	1829	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
Kojto	122:f9eeca106725	1830	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
Kojto	122:f9eeca106725	1831	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
Kojto	93:e188a91d3eaa	1832	*/
Kojto	93:e188a91d3eaa	1833	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
Kojto	93:e188a91d3eaa	1834	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx*/
bogdanm	92:4fc01daae5a5	1835
bogdanm	92:4fc01daae5a5	1836	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	1837	/** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto	122:f9eeca106725	1838	* @param __USART3CLKSOURCE__ specifies the USART3 clock source.
bogdanm	92:4fc01daae5a5	1839	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1840	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
Kojto	122:f9eeca106725	1841	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
Kojto	122:f9eeca106725	1842	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
Kojto	122:f9eeca106725	1843	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
bogdanm	92:4fc01daae5a5	1844	*/
Kojto	122:f9eeca106725	1845	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
Kojto	122:f9eeca106725	1846	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
bogdanm	85:024bf7f99721	1847
bogdanm	92:4fc01daae5a5	1848	/** @brief Macro to get the USART3 clock source.
bogdanm	92:4fc01daae5a5	1849	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	1850	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
Kojto	122:f9eeca106725	1851	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
Kojto	122:f9eeca106725	1852	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
Kojto	122:f9eeca106725	1853	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
bogdanm	92:4fc01daae5a5	1854	*/
bogdanm	92:4fc01daae5a5	1855	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
bogdanm	92:4fc01daae5a5	1856
Kojto	93:e188a91d3eaa	1857	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1858	/**
bogdanm	92:4fc01daae5a5	1859	* @}
bogdanm	92:4fc01daae5a5	1860	*/
Kojto	122:f9eeca106725	1861
Kojto	122:f9eeca106725	1862	/** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration
Kojto	122:f9eeca106725	1863	* @{
Kojto	122:f9eeca106725	1864	*/
Kojto	122:f9eeca106725	1865
Kojto	122:f9eeca106725	1866	/**
Kojto	122:f9eeca106725	1867	* @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
Kojto	122:f9eeca106725	1868	* @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
Kojto	122:f9eeca106725	1869	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1870	* @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
Kojto	122:f9eeca106725	1871	* @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
Kojto	122:f9eeca106725	1872	* @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
Kojto	122:f9eeca106725	1873	* @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
Kojto	122:f9eeca106725	1874	* @retval None
Kojto	122:f9eeca106725	1875	*/
Kojto	122:f9eeca106725	1876	#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
Kojto	122:f9eeca106725	1877	RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
Kojto	122:f9eeca106725	1878
Kojto	122:f9eeca106725	1879	/**
Kojto	122:f9eeca106725	1880	* @}
Kojto	122:f9eeca106725	1881	*/
Kojto	122:f9eeca106725	1882
Kojto	122:f9eeca106725	1883	#if defined(CRS)
bogdanm	92:4fc01daae5a5	1884
bogdanm	92:4fc01daae5a5	1885	/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
bogdanm	92:4fc01daae5a5	1886	* @{
bogdanm	92:4fc01daae5a5	1887	*/
bogdanm	85:024bf7f99721	1888	/* Interrupt & Flag management */
bogdanm	85:024bf7f99721	1889
bogdanm	85:024bf7f99721	1890	/**
Kojto	122:f9eeca106725	1891	* @brief Enable the specified CRS interrupts.
Kojto	122:f9eeca106725	1892	* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
bogdanm	85:024bf7f99721	1893	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1894	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
Kojto	122:f9eeca106725	1895	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
Kojto	122:f9eeca106725	1896	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
Kojto	122:f9eeca106725	1897	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
bogdanm	85:024bf7f99721	1898	* @retval None
bogdanm	85:024bf7f99721	1899	*/
Kojto	122:f9eeca106725	1900	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
bogdanm	85:024bf7f99721	1901
bogdanm	85:024bf7f99721	1902	/**
Kojto	122:f9eeca106725	1903	* @brief Disable the specified CRS interrupts.
Kojto	122:f9eeca106725	1904	* @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
bogdanm	85:024bf7f99721	1905	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1906	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
Kojto	122:f9eeca106725	1907	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
Kojto	122:f9eeca106725	1908	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
Kojto	122:f9eeca106725	1909	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
bogdanm	85:024bf7f99721	1910	* @retval None
bogdanm	85:024bf7f99721	1911	*/
Kojto	122:f9eeca106725	1912	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
bogdanm	85:024bf7f99721	1913
Kojto	122:f9eeca106725	1914	/** @brief Check whether the CRS interrupt has occurred or not.
Kojto	122:f9eeca106725	1915	* @param __INTERRUPT__ specifies the CRS interrupt source to check.
bogdanm	85:024bf7f99721	1916	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1917	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
Kojto	122:f9eeca106725	1918	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
Kojto	122:f9eeca106725	1919	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
Kojto	122:f9eeca106725	1920	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
bogdanm	85:024bf7f99721	1921	* @retval The new state of __INTERRUPT__ (SET or RESET).
bogdanm	85:024bf7f99721	1922	*/
Kojto	122:f9eeca106725	1923	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
bogdanm	85:024bf7f99721	1924
Kojto	122:f9eeca106725	1925	/** @brief Clear the CRS interrupt pending bits
Kojto	122:f9eeca106725	1926	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
bogdanm	85:024bf7f99721	1927	* This parameter can be any combination of the following values:
Kojto	122:f9eeca106725	1928	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
Kojto	122:f9eeca106725	1929	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
Kojto	122:f9eeca106725	1930	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
Kojto	122:f9eeca106725	1931	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
Kojto	122:f9eeca106725	1932	* @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
Kojto	122:f9eeca106725	1933	* @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
Kojto	122:f9eeca106725	1934	* @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
bogdanm	85:024bf7f99721	1935	*/
Kojto	122:f9eeca106725	1936	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
Kojto	122:f9eeca106725	1937	if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
Kojto	122:f9eeca106725	1938	{ \
Kojto	122:f9eeca106725	1939	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
Kojto	122:f9eeca106725	1940	} \
Kojto	122:f9eeca106725	1941	else \
Kojto	122:f9eeca106725	1942	{ \
Kojto	122:f9eeca106725	1943	WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
Kojto	122:f9eeca106725	1944	} \
Kojto	122:f9eeca106725	1945	} while(0)
bogdanm	85:024bf7f99721	1946
bogdanm	85:024bf7f99721	1947	/**
Kojto	122:f9eeca106725	1948	* @brief Check whether the specified CRS flag is set or not.
Kojto	122:f9eeca106725	1949	* @param __FLAG__ specifies the flag to check.
bogdanm	85:024bf7f99721	1950	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1951	* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
Kojto	122:f9eeca106725	1952	* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
Kojto	122:f9eeca106725	1953	* @arg @ref RCC_CRS_FLAG_ERR Error
Kojto	122:f9eeca106725	1954	* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
Kojto	122:f9eeca106725	1955	* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
Kojto	122:f9eeca106725	1956	* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
Kojto	122:f9eeca106725	1957	* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
bogdanm	85:024bf7f99721	1958	* @retval The new state of _FLAG_ (TRUE or FALSE).
bogdanm	85:024bf7f99721	1959	*/
Kojto	122:f9eeca106725	1960	#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
bogdanm	85:024bf7f99721	1961
bogdanm	85:024bf7f99721	1962	/**
Kojto	122:f9eeca106725	1963	* @brief Clear the CRS specified FLAG.
Kojto	122:f9eeca106725	1964	* @param __FLAG__ specifies the flag to clear.
bogdanm	85:024bf7f99721	1965	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1966	* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
Kojto	122:f9eeca106725	1967	* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
Kojto	122:f9eeca106725	1968	* @arg @ref RCC_CRS_FLAG_ERR Error
Kojto	122:f9eeca106725	1969	* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
Kojto	122:f9eeca106725	1970	* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
Kojto	122:f9eeca106725	1971	* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
Kojto	122:f9eeca106725	1972	* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
Kojto	122:f9eeca106725	1973	* @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
bogdanm	85:024bf7f99721	1974	* @retval None
bogdanm	85:024bf7f99721	1975	*/
Kojto	122:f9eeca106725	1976	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
Kojto	122:f9eeca106725	1977	if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
Kojto	122:f9eeca106725	1978	{ \
Kojto	122:f9eeca106725	1979	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
Kojto	122:f9eeca106725	1980	} \
Kojto	122:f9eeca106725	1981	else \
Kojto	122:f9eeca106725	1982	{ \
Kojto	122:f9eeca106725	1983	WRITE_REG(CRS->ICR, (__FLAG__)); \
Kojto	122:f9eeca106725	1984	} \
Kojto	122:f9eeca106725	1985	} while(0)
bogdanm	85:024bf7f99721	1986
bogdanm	92:4fc01daae5a5	1987	/**
bogdanm	92:4fc01daae5a5	1988	* @}
bogdanm	92:4fc01daae5a5	1989	*/
bogdanm	85:024bf7f99721	1990
bogdanm	92:4fc01daae5a5	1991	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
bogdanm	92:4fc01daae5a5	1992	* @{
bogdanm	92:4fc01daae5a5	1993	*/
bogdanm	85:024bf7f99721	1994	/**
Kojto	122:f9eeca106725	1995	* @brief Enable the oscillator clock for frequency error counter.
bogdanm	85:024bf7f99721	1996	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	85:024bf7f99721	1997	* @retval None
bogdanm	85:024bf7f99721	1998	*/
Kojto	122:f9eeca106725	1999	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
bogdanm	85:024bf7f99721	2000
bogdanm	85:024bf7f99721	2001	/**
Kojto	122:f9eeca106725	2002	* @brief Disable the oscillator clock for frequency error counter.
bogdanm	85:024bf7f99721	2003	* @retval None
bogdanm	85:024bf7f99721	2004	*/
Kojto	122:f9eeca106725	2005	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
bogdanm	85:024bf7f99721	2006
bogdanm	85:024bf7f99721	2007	/**
Kojto	122:f9eeca106725	2008	* @brief Enable the automatic hardware adjustement of TRIM bits.
bogdanm	85:024bf7f99721	2009	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	85:024bf7f99721	2010	* @retval None
bogdanm	85:024bf7f99721	2011	*/
Kojto	122:f9eeca106725	2012	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
bogdanm	85:024bf7f99721	2013
bogdanm	85:024bf7f99721	2014	/**
Kojto	122:f9eeca106725	2015	* @brief Disable the automatic hardware adjustement of TRIM bits.
bogdanm	85:024bf7f99721	2016	* @retval None
bogdanm	85:024bf7f99721	2017	*/
Kojto	122:f9eeca106725	2018	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
bogdanm	85:024bf7f99721	2019
bogdanm	85:024bf7f99721	2020	/**
bogdanm	85:024bf7f99721	2021	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
bogdanm	85:024bf7f99721	2022	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
bogdanm	85:024bf7f99721	2023	* of the synchronization source after prescaling. It is then decreased by one in order to
bogdanm	85:024bf7f99721	2024	* reach the expected synchronization on the zero value. The formula is the following:
bogdanm	85:024bf7f99721	2025	* RELOAD = (fTARGET / fSYNC) -1
Kojto	122:f9eeca106725	2026	* @param __FTARGET__ Target frequency (value in Hz)
Kojto	122:f9eeca106725	2027	* @param __FSYNC__ Synchronization signal frequency (value in Hz)
bogdanm	85:024bf7f99721	2028	* @retval None
bogdanm	85:024bf7f99721	2029	*/
Kojto	122:f9eeca106725	2030	#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
bogdanm	85:024bf7f99721	2031
bogdanm	92:4fc01daae5a5	2032	/**
bogdanm	92:4fc01daae5a5	2033	* @}
bogdanm	92:4fc01daae5a5	2034	*/
Kojto	122:f9eeca106725	2035
Kojto	122:f9eeca106725	2036	#endif /* CRS */
Kojto	122:f9eeca106725	2037
bogdanm	85:024bf7f99721	2038	/**
bogdanm	85:024bf7f99721	2039	* @}
Kojto	122:f9eeca106725	2040	*/
bogdanm	85:024bf7f99721	2041
bogdanm	85:024bf7f99721	2042	/* Exported functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	2043	/** @addtogroup RCCEx_Exported_Functions
bogdanm	92:4fc01daae5a5	2044	* @{
bogdanm	92:4fc01daae5a5	2045	*/
bogdanm	92:4fc01daae5a5	2046
Kojto	122:f9eeca106725	2047	/** @addtogroup RCCEx_Exported_Functions_Group1
bogdanm	92:4fc01daae5a5	2048	* @{
bogdanm	92:4fc01daae5a5	2049	*/
bogdanm	92:4fc01daae5a5	2050
bogdanm	85:024bf7f99721	2051	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	85:024bf7f99721	2052	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	108:34e6b704fe68	2053	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
bogdanm	85:024bf7f99721	2054
Kojto	122:f9eeca106725	2055	/**
Kojto	122:f9eeca106725	2056	* @}
Kojto	122:f9eeca106725	2057	*/
Kojto	122:f9eeca106725	2058
Kojto	122:f9eeca106725	2059	#if defined(CRS)
Kojto	122:f9eeca106725	2060
Kojto	122:f9eeca106725	2061	/** @addtogroup RCCEx_Exported_Functions_Group3
Kojto	122:f9eeca106725	2062	* @{
Kojto	122:f9eeca106725	2063	*/
bogdanm	85:024bf7f99721	2064
Kojto	122:f9eeca106725	2065	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
Kojto	122:f9eeca106725	2066	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
Kojto	122:f9eeca106725	2067	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
Kojto	122:f9eeca106725	2068	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
Kojto	122:f9eeca106725	2069	void HAL_RCCEx_CRS_IRQHandler(void);
Kojto	122:f9eeca106725	2070	void HAL_RCCEx_CRS_SyncOkCallback(void);
Kojto	122:f9eeca106725	2071	void HAL_RCCEx_CRS_SyncWarnCallback(void);
Kojto	122:f9eeca106725	2072	void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
Kojto	122:f9eeca106725	2073	void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
Kojto	122:f9eeca106725	2074
Kojto	122:f9eeca106725	2075	/**
Kojto	122:f9eeca106725	2076	* @}
Kojto	122:f9eeca106725	2077	*/
Kojto	122:f9eeca106725	2078
Kojto	122:f9eeca106725	2079	#endif /* CRS */
bogdanm	85:024bf7f99721	2080
bogdanm	85:024bf7f99721	2081	/**
bogdanm	85:024bf7f99721	2082	* @}
bogdanm	85:024bf7f99721	2083	*/
bogdanm	85:024bf7f99721	2084
bogdanm	85:024bf7f99721	2085	/**
bogdanm	85:024bf7f99721	2086	* @}
bogdanm	85:024bf7f99721	2087	*/
bogdanm	92:4fc01daae5a5	2088
bogdanm	92:4fc01daae5a5	2089	/**
bogdanm	92:4fc01daae5a5	2090	* @}
bogdanm	92:4fc01daae5a5	2091	*/
bogdanm	92:4fc01daae5a5	2092
bogdanm	92:4fc01daae5a5	2093	/**
bogdanm	92:4fc01daae5a5	2094	* @}
bogdanm	92:4fc01daae5a5	2095	*/
bogdanm	85:024bf7f99721	2096
bogdanm	85:024bf7f99721	2097	#ifdef __cplusplus
bogdanm	85:024bf7f99721	2098	}
bogdanm	85:024bf7f99721	2099	#endif
bogdanm	85:024bf7f99721	2100
bogdanm	85:024bf7f99721	2101	#endif /* __STM32F0xx_HAL_RCC_EX_H */
bogdanm	85:024bf7f99721	2102
bogdanm	85:024bf7f99721	2103	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/