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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Parent:: 134:ad3be0349dc5

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	85:024bf7f99721	1	/**
bogdanm	85:024bf7f99721	2	******************************************************************************
bogdanm	85:024bf7f99721	3	* @file stm32f0xx_hal_dma.h
bogdanm	85:024bf7f99721	4	* @author MCD Application Team
<>	134:ad3be0349dc5	5	* @version V1.5.0
<>	134:ad3be0349dc5	6	* @date 04-November-2016
bogdanm	85:024bf7f99721	7	* @brief Header file of DMA HAL module.
bogdanm	85:024bf7f99721	8	******************************************************************************
bogdanm	85:024bf7f99721	9	* @attention
bogdanm	85:024bf7f99721	10	*
Kojto	122:f9eeca106725	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	85:024bf7f99721	12	*
bogdanm	85:024bf7f99721	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	85:024bf7f99721	14	* are permitted provided that the following conditions are met:
bogdanm	85:024bf7f99721	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	85:024bf7f99721	16	* this list of conditions and the following disclaimer.
bogdanm	85:024bf7f99721	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	85:024bf7f99721	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	85:024bf7f99721	19	* and/or other materials provided with the distribution.
bogdanm	85:024bf7f99721	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	85:024bf7f99721	21	* may be used to endorse or promote products derived from this software
bogdanm	85:024bf7f99721	22	* without specific prior written permission.
bogdanm	85:024bf7f99721	23	*
bogdanm	85:024bf7f99721	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	85:024bf7f99721	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	85:024bf7f99721	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	85:024bf7f99721	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	85:024bf7f99721	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	85:024bf7f99721	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	85:024bf7f99721	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	85:024bf7f99721	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	85:024bf7f99721	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	85:024bf7f99721	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	85:024bf7f99721	34	*
bogdanm	85:024bf7f99721	35	******************************************************************************
bogdanm	85:024bf7f99721	36	*/
bogdanm	85:024bf7f99721	37
bogdanm	85:024bf7f99721	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	85:024bf7f99721	39	#ifndef __STM32F0xx_HAL_DMA_H
bogdanm	85:024bf7f99721	40	#define __STM32F0xx_HAL_DMA_H
bogdanm	85:024bf7f99721	41
bogdanm	85:024bf7f99721	42	#ifdef __cplusplus
bogdanm	85:024bf7f99721	43	extern "C" {
bogdanm	85:024bf7f99721	44	#endif
bogdanm	85:024bf7f99721	45
bogdanm	85:024bf7f99721	46	/* Includes ------------------------------------------------------------------*/
bogdanm	85:024bf7f99721	47	#include "stm32f0xx_hal_def.h"
bogdanm	85:024bf7f99721	48
bogdanm	85:024bf7f99721	49	/** @addtogroup STM32F0xx_HAL_Driver
bogdanm	85:024bf7f99721	50	* @{
bogdanm	85:024bf7f99721	51	*/
bogdanm	85:024bf7f99721	52
bogdanm	85:024bf7f99721	53	/** @addtogroup DMA
bogdanm	85:024bf7f99721	54	* @{
bogdanm	85:024bf7f99721	55	*/
bogdanm	85:024bf7f99721	56
bogdanm	85:024bf7f99721	57	/* Exported types ------------------------------------------------------------*/
Kojto	108:34e6b704fe68	58
bogdanm	92:4fc01daae5a5	59	/** @defgroup DMA_Exported_Types DMA Exported Types
bogdanm	92:4fc01daae5a5	60	* @{
bogdanm	92:4fc01daae5a5	61	*/
bogdanm	85:024bf7f99721	62
bogdanm	85:024bf7f99721	63	/**
bogdanm	85:024bf7f99721	64	* @brief DMA Configuration Structure definition
bogdanm	85:024bf7f99721	65	*/
bogdanm	85:024bf7f99721	66	typedef struct
bogdanm	85:024bf7f99721	67	{
bogdanm	85:024bf7f99721	68	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm	85:024bf7f99721	69	from memory to memory or from peripheral to memory.
bogdanm	85:024bf7f99721	70	This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm	85:024bf7f99721	71
bogdanm	85:024bf7f99721	72	uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm	85:024bf7f99721	73	This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm	85:024bf7f99721	74
bogdanm	85:024bf7f99721	75	uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm	85:024bf7f99721	76	This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm	85:024bf7f99721	77
bogdanm	85:024bf7f99721	78	uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm	85:024bf7f99721	79	This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm	85:024bf7f99721	80
bogdanm	85:024bf7f99721	81	uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm	85:024bf7f99721	82	This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm	85:024bf7f99721	83
bogdanm	85:024bf7f99721	84	uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
bogdanm	85:024bf7f99721	85	This parameter can be a value of @ref DMA_mode
bogdanm	85:024bf7f99721	86	@note The circular buffer mode cannot be used if the memory-to-memory
bogdanm	85:024bf7f99721	87	data transfer is configured on the selected Channel */
bogdanm	85:024bf7f99721	88
bogdanm	85:024bf7f99721	89	uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
bogdanm	85:024bf7f99721	90	This parameter can be a value of @ref DMA_Priority_level */
bogdanm	85:024bf7f99721	91	} DMA_InitTypeDef;
bogdanm	85:024bf7f99721	92
bogdanm	92:4fc01daae5a5	93	/**
bogdanm	92:4fc01daae5a5	94	* @brief HAL DMA State structures definition
bogdanm	92:4fc01daae5a5	95	*/
bogdanm	85:024bf7f99721	96	typedef enum
bogdanm	85:024bf7f99721	97	{
<>	134:ad3be0349dc5	98	HAL_DMA_STATE_RESET = 0x00U, /!< DMA not yet initialized or disabled /
<>	134:ad3be0349dc5	99	HAL_DMA_STATE_READY = 0x01U, /!< DMA initialized and ready for use /
<>	134:ad3be0349dc5	100	HAL_DMA_STATE_BUSY = 0x02U, /!< DMA process is ongoing /
<>	134:ad3be0349dc5	101	HAL_DMA_STATE_TIMEOUT = 0x03U /!< DMA timeout state /
bogdanm	85:024bf7f99721	102	}HAL_DMA_StateTypeDef;
bogdanm	85:024bf7f99721	103
bogdanm	85:024bf7f99721	104	/**
bogdanm	85:024bf7f99721	105	* @brief HAL DMA Error Code structure definition
bogdanm	85:024bf7f99721	106	*/
bogdanm	85:024bf7f99721	107	typedef enum
bogdanm	85:024bf7f99721	108	{
<>	134:ad3be0349dc5	109	HAL_DMA_FULL_TRANSFER = 0x00U, /!< Full transfer /
<>	134:ad3be0349dc5	110	HAL_DMA_HALF_TRANSFER = 0x01U /!< Half Transfer /
<>	134:ad3be0349dc5	111	}HAL_DMA_LevelCompleteTypeDef;
<>	134:ad3be0349dc5	112
<>	134:ad3be0349dc5	113	/**
<>	134:ad3be0349dc5	114	* @brief HAL DMA Callback ID structure definition
<>	134:ad3be0349dc5	115	*/
<>	134:ad3be0349dc5	116	typedef enum
<>	134:ad3be0349dc5	117	{
<>	134:ad3be0349dc5	118	HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /!< Full transfer /
<>	134:ad3be0349dc5	119	HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /!< Half transfer /
<>	134:ad3be0349dc5	120	HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /!< Error /
<>	134:ad3be0349dc5	121	HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /!< Abort /
<>	134:ad3be0349dc5	122	HAL_DMA_XFER_ALL_CB_ID = 0x04U /!< All /
<>	134:ad3be0349dc5	123
<>	134:ad3be0349dc5	124	}HAL_DMA_CallbackIDTypeDef;
bogdanm	85:024bf7f99721	125
bogdanm	85:024bf7f99721	126	/**
bogdanm	85:024bf7f99721	127	* @brief DMA handle Structure definition
bogdanm	85:024bf7f99721	128	*/
bogdanm	85:024bf7f99721	129	typedef struct __DMA_HandleTypeDef
bogdanm	85:024bf7f99721	130	{
bogdanm	85:024bf7f99721	131	DMA_Channel_TypeDef Instance; /!< Register base address */
bogdanm	85:024bf7f99721	132
bogdanm	85:024bf7f99721	133	DMA_InitTypeDef Init; /!< DMA communication parameters /
bogdanm	85:024bf7f99721	134
bogdanm	85:024bf7f99721	135	HAL_LockTypeDef Lock; /!< DMA locking object /
bogdanm	85:024bf7f99721	136
Kojto	108:34e6b704fe68	137	__IO HAL_DMA_StateTypeDef State; /!< DMA transfer state /
bogdanm	85:024bf7f99721	138
bogdanm	85:024bf7f99721	139	void Parent; /!< Parent object state */
bogdanm	85:024bf7f99721	140
bogdanm	85:024bf7f99721	141	void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer complete callback /
bogdanm	85:024bf7f99721	142
bogdanm	85:024bf7f99721	143	void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA Half transfer complete callback /
bogdanm	92:4fc01daae5a5	144
bogdanm	85:024bf7f99721	145	void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer error callback /
bogdanm	85:024bf7f99721	146
<>	134:ad3be0349dc5	147	void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /!< DMA transfer abort callback /
Kojto	122:f9eeca106725	148
bogdanm	85:024bf7f99721	149	__IO uint32_t ErrorCode; /!< DMA Error code /
<>	134:ad3be0349dc5	150
<>	134:ad3be0349dc5	151	DMA_TypeDef DmaBaseAddress; /!< DMA Channel Base Address */
<>	134:ad3be0349dc5	152
<>	134:ad3be0349dc5	153	uint32_t ChannelIndex; /!< DMA Channel Index /
bogdanm	85:024bf7f99721	154	} DMA_HandleTypeDef;
Kojto	108:34e6b704fe68	155
bogdanm	92:4fc01daae5a5	156	/**
bogdanm	92:4fc01daae5a5	157	* @}
bogdanm	92:4fc01daae5a5	158	*/
bogdanm	85:024bf7f99721	159
bogdanm	85:024bf7f99721	160	/* Exported constants --------------------------------------------------------*/
Kojto	108:34e6b704fe68	161
bogdanm	92:4fc01daae5a5	162	/** @defgroup DMA_Exported_Constants DMA Exported Constants
bogdanm	85:024bf7f99721	163	* @{
bogdanm	85:024bf7f99721	164	*/
bogdanm	85:024bf7f99721	165
bogdanm	92:4fc01daae5a5	166	/** @defgroup DMA_Error_Code DMA Error Code
bogdanm	85:024bf7f99721	167	* @{
bogdanm	85:024bf7f99721	168	*/
<>	134:ad3be0349dc5	169	#define HAL_DMA_ERROR_NONE (0x00000000U) /!< No error /
<>	134:ad3be0349dc5	170	#define HAL_DMA_ERROR_TE (0x00000001U) /!< Transfer error /
<>	134:ad3be0349dc5	171	#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /!< no ongoin transfer /
<>	134:ad3be0349dc5	172	#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /!< Timeout error /
<>	134:ad3be0349dc5	173	#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /!< Not supported mode /
bogdanm	85:024bf7f99721	174	/**
bogdanm	85:024bf7f99721	175	* @}
bogdanm	85:024bf7f99721	176	*/
bogdanm	85:024bf7f99721	177
bogdanm	92:4fc01daae5a5	178	/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
bogdanm	85:024bf7f99721	179	* @{
bogdanm	85:024bf7f99721	180	*/
<>	134:ad3be0349dc5	181	#define DMA_PERIPH_TO_MEMORY (0x00000000U) /!< Peripheral to memory direction /
bogdanm	85:024bf7f99721	182	#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /!< Memory to peripheral direction /
bogdanm	85:024bf7f99721	183	#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /!< Memory to memory direction /
bogdanm	85:024bf7f99721	184
bogdanm	85:024bf7f99721	185	/**
bogdanm	85:024bf7f99721	186	* @}
bogdanm	85:024bf7f99721	187	*/
Kojto	108:34e6b704fe68	188
bogdanm	92:4fc01daae5a5	189	/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
bogdanm	85:024bf7f99721	190	* @{
bogdanm	85:024bf7f99721	191	*/
bogdanm	85:024bf7f99721	192	#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /!< Peripheral increment mode Enable /
<>	134:ad3be0349dc5	193	#define DMA_PINC_DISABLE (0x00000000U) /!< Peripheral increment mode Disable /
bogdanm	85:024bf7f99721	194	/**
bogdanm	85:024bf7f99721	195	* @}
bogdanm	85:024bf7f99721	196	*/
bogdanm	85:024bf7f99721	197
bogdanm	92:4fc01daae5a5	198	/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
bogdanm	85:024bf7f99721	199	* @{
bogdanm	85:024bf7f99721	200	*/
bogdanm	85:024bf7f99721	201	#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /!< Memory increment mode Enable /
<>	134:ad3be0349dc5	202	#define DMA_MINC_DISABLE (0x00000000U) /!< Memory increment mode Disable /
bogdanm	85:024bf7f99721	203	/**
bogdanm	85:024bf7f99721	204	* @}
bogdanm	85:024bf7f99721	205	*/
bogdanm	85:024bf7f99721	206
bogdanm	92:4fc01daae5a5	207	/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
bogdanm	85:024bf7f99721	208	* @{
bogdanm	85:024bf7f99721	209	*/
<>	134:ad3be0349dc5	210	#define DMA_PDATAALIGN_BYTE (0x00000000U) /!< Peripheral data alignment : Byte /
bogdanm	85:024bf7f99721	211	#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /!< Peripheral data alignment : HalfWord /
bogdanm	85:024bf7f99721	212	#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /!< Peripheral data alignment : Word /
bogdanm	85:024bf7f99721	213	/**
bogdanm	85:024bf7f99721	214	* @}
bogdanm	85:024bf7f99721	215	*/
bogdanm	85:024bf7f99721	216
bogdanm	92:4fc01daae5a5	217	/** @defgroup DMA_Memory_data_size DMA Memory data size
bogdanm	85:024bf7f99721	218	* @{
bogdanm	85:024bf7f99721	219	*/
<>	134:ad3be0349dc5	220	#define DMA_MDATAALIGN_BYTE (0x00000000U) /!< Memory data alignment : Byte /
bogdanm	85:024bf7f99721	221	#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /!< Memory data alignment : HalfWord /
bogdanm	85:024bf7f99721	222	#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /!< Memory data alignment : Word /
bogdanm	85:024bf7f99721	223	/**
bogdanm	85:024bf7f99721	224	* @}
bogdanm	85:024bf7f99721	225	*/
bogdanm	85:024bf7f99721	226
bogdanm	92:4fc01daae5a5	227	/** @defgroup DMA_mode DMA mode
bogdanm	85:024bf7f99721	228	* @{
bogdanm	85:024bf7f99721	229	*/
<>	134:ad3be0349dc5	230	#define DMA_NORMAL (0x00000000U) /!< Normal Mode /
bogdanm	85:024bf7f99721	231	#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /!< Circular Mode /
bogdanm	85:024bf7f99721	232	/**
bogdanm	85:024bf7f99721	233	* @}
bogdanm	85:024bf7f99721	234	*/
bogdanm	85:024bf7f99721	235
bogdanm	92:4fc01daae5a5	236	/** @defgroup DMA_Priority_level DMA Priority level
bogdanm	85:024bf7f99721	237	* @{
bogdanm	85:024bf7f99721	238	*/
<>	134:ad3be0349dc5	239	#define DMA_PRIORITY_LOW (0x00000000U) /!< Priority level : Low /
bogdanm	85:024bf7f99721	240	#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /!< Priority level : Medium /
bogdanm	85:024bf7f99721	241	#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /!< Priority level : High /
bogdanm	85:024bf7f99721	242	#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /!< Priority level : Very_High /
bogdanm	85:024bf7f99721	243	/**
bogdanm	85:024bf7f99721	244	* @}
bogdanm	85:024bf7f99721	245	*/
bogdanm	85:024bf7f99721	246
bogdanm	85:024bf7f99721	247
bogdanm	92:4fc01daae5a5	248	/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
bogdanm	85:024bf7f99721	249	* @{
bogdanm	85:024bf7f99721	250	*/
bogdanm	85:024bf7f99721	251	#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
bogdanm	85:024bf7f99721	252	#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
bogdanm	85:024bf7f99721	253	#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
bogdanm	85:024bf7f99721	254	/**
bogdanm	85:024bf7f99721	255	* @}
bogdanm	85:024bf7f99721	256	*/
bogdanm	85:024bf7f99721	257
bogdanm	92:4fc01daae5a5	258	/** @defgroup DMA_flag_definitions DMA flag definitions
bogdanm	85:024bf7f99721	259	* @{
bogdanm	85:024bf7f99721	260	*/
bogdanm	85:024bf7f99721	261
<>	134:ad3be0349dc5	262	#define DMA_FLAG_GL1 (0x00000001U) /!< Channel 1 global interrupt flag /
<>	134:ad3be0349dc5	263	#define DMA_FLAG_TC1 (0x00000002U) /!< Channel 1 transfer complete flag /
<>	134:ad3be0349dc5	264	#define DMA_FLAG_HT1 (0x00000004U) /!< Channel 1 half transfer flag /
<>	134:ad3be0349dc5	265	#define DMA_FLAG_TE1 (0x00000008U) /!< Channel 1 transfer error flag /
<>	134:ad3be0349dc5	266	#define DMA_FLAG_GL2 (0x00000010U) /!< Channel 2 global interrupt flag /
<>	134:ad3be0349dc5	267	#define DMA_FLAG_TC2 (0x00000020U) /!< Channel 2 transfer complete flag /
<>	134:ad3be0349dc5	268	#define DMA_FLAG_HT2 (0x00000040U) /!< Channel 2 half transfer flag /
<>	134:ad3be0349dc5	269	#define DMA_FLAG_TE2 (0x00000080U) /!< Channel 2 transfer error flag /
<>	134:ad3be0349dc5	270	#define DMA_FLAG_GL3 (0x00000100U) /!< Channel 3 global interrupt flag /
<>	134:ad3be0349dc5	271	#define DMA_FLAG_TC3 (0x00000200U) /!< Channel 3 transfer complete flag /
<>	134:ad3be0349dc5	272	#define DMA_FLAG_HT3 (0x00000400U) /!< Channel 3 half transfer flag /
<>	134:ad3be0349dc5	273	#define DMA_FLAG_TE3 (0x00000800U) /!< Channel 3 transfer error flag /
<>	134:ad3be0349dc5	274	#define DMA_FLAG_GL4 (0x00001000U) /!< Channel 4 global interrupt flag /
<>	134:ad3be0349dc5	275	#define DMA_FLAG_TC4 (0x00002000U) /!< Channel 4 transfer complete flag /
<>	134:ad3be0349dc5	276	#define DMA_FLAG_HT4 (0x00004000U) /!< Channel 4 half transfer flag /
<>	134:ad3be0349dc5	277	#define DMA_FLAG_TE4 (0x00008000U) /!< Channel 4 transfer error flag /
<>	134:ad3be0349dc5	278	#define DMA_FLAG_GL5 (0x00010000U) /!< Channel 5 global interrupt flag /
<>	134:ad3be0349dc5	279	#define DMA_FLAG_TC5 (0x00020000U) /!< Channel 5 transfer complete flag /
<>	134:ad3be0349dc5	280	#define DMA_FLAG_HT5 (0x00040000U) /!< Channel 5 half transfer flag /
<>	134:ad3be0349dc5	281	#define DMA_FLAG_TE5 (0x00080000U) /!< Channel 5 transfer error flag /
<>	134:ad3be0349dc5	282	#define DMA_FLAG_GL6 (0x00100000U) /!< Channel 6 global interrupt flag /
<>	134:ad3be0349dc5	283	#define DMA_FLAG_TC6 (0x00200000U) /!< Channel 6 transfer complete flag /
<>	134:ad3be0349dc5	284	#define DMA_FLAG_HT6 (0x00400000U) /!< Channel 6 half transfer flag /
<>	134:ad3be0349dc5	285	#define DMA_FLAG_TE6 (0x00800000U) /!< Channel 6 transfer error flag /
<>	134:ad3be0349dc5	286	#define DMA_FLAG_GL7 (0x01000000U) /!< Channel 7 global interrupt flag /
<>	134:ad3be0349dc5	287	#define DMA_FLAG_TC7 (0x02000000U) /!< Channel 7 transfer complete flag /
<>	134:ad3be0349dc5	288	#define DMA_FLAG_HT7 (0x04000000U) /!< Channel 7 half transfer flag /
<>	134:ad3be0349dc5	289	#define DMA_FLAG_TE7 (0x08000000U) /!< Channel 7 transfer error flag /
bogdanm	85:024bf7f99721	290
Kojto	108:34e6b704fe68	291	/**
Kojto	108:34e6b704fe68	292	* @}
Kojto	108:34e6b704fe68	293	*/
Kojto	108:34e6b704fe68	294
Kojto	108:34e6b704fe68	295	#if defined(SYSCFG_CFGR1_DMA_RMP)
Kojto	108:34e6b704fe68	296	/** @defgroup HAL_DMA_remapping HAL DMA remapping
Kojto	108:34e6b704fe68	297	* Elements values convention: 0xYYYYYYYY
Kojto	108:34e6b704fe68	298	* - YYYYYYYY : Position in the SYSCFG register CFGR1
Kojto	108:34e6b704fe68	299	* @{
Kojto	108:34e6b704fe68	300	*/
Kojto	108:34e6b704fe68	301	#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
Kojto	108:34e6b704fe68	302	0: No remap (ADC DMA requests mapped on DMA channel 1
Kojto	108:34e6b704fe68	303	1: Remap (ADC DMA requests mapped on DMA channel 2 */
Kojto	108:34e6b704fe68	304	#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
Kojto	108:34e6b704fe68	305	0: No remap (USART1_TX DMA request mapped on DMA channel 2
Kojto	108:34e6b704fe68	306	1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
Kojto	108:34e6b704fe68	307	#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
Kojto	108:34e6b704fe68	308	0: No remap (USART1_RX DMA request mapped on DMA channel 3
Kojto	108:34e6b704fe68	309	1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
Kojto	108:34e6b704fe68	310	#define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
Kojto	108:34e6b704fe68	311	0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
Kojto	108:34e6b704fe68	312	1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
Kojto	108:34e6b704fe68	313	#define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
Kojto	108:34e6b704fe68	314	0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
Kojto	108:34e6b704fe68	315	1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
Kojto	108:34e6b704fe68	316	#if defined (STM32F070xB)
Kojto	108:34e6b704fe68	317	#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only.
Kojto	108:34e6b704fe68	318	0: Disabled, need to remap before use
Kojto	108:34e6b704fe68	319	1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
Kojto	108:34e6b704fe68	320
Kojto	108:34e6b704fe68	321	#endif
Kojto	108:34e6b704fe68	322
Kojto	108:34e6b704fe68	323	#if defined (STM32F071xB) \|\| defined (STM32F072xB) \|\| defined (STM32F078xx)
Kojto	108:34e6b704fe68	324	#define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
Kojto	108:34e6b704fe68	325	0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
Kojto	108:34e6b704fe68	326	1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
Kojto	108:34e6b704fe68	327	#define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
Kojto	108:34e6b704fe68	328	0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
Kojto	108:34e6b704fe68	329	1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
Kojto	108:34e6b704fe68	330	#define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
Kojto	108:34e6b704fe68	331	0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
Kojto	108:34e6b704fe68	332	1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
Kojto	108:34e6b704fe68	333	#define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
Kojto	108:34e6b704fe68	334	0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
Kojto	108:34e6b704fe68	335	1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
Kojto	108:34e6b704fe68	336	#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
Kojto	108:34e6b704fe68	337	0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
Kojto	108:34e6b704fe68	338	1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
Kojto	108:34e6b704fe68	339	#define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
Kojto	108:34e6b704fe68	340	0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
Kojto	108:34e6b704fe68	341	1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
Kojto	108:34e6b704fe68	342	#define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
Kojto	108:34e6b704fe68	343	0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
Kojto	108:34e6b704fe68	344	1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
Kojto	108:34e6b704fe68	345	#define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
Kojto	108:34e6b704fe68	346	0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
Kojto	108:34e6b704fe68	347	1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
Kojto	108:34e6b704fe68	348	#define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
Kojto	108:34e6b704fe68	349	0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
Kojto	108:34e6b704fe68	350	1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
Kojto	108:34e6b704fe68	351	#endif
bogdanm	85:024bf7f99721	352
bogdanm	85:024bf7f99721	353	/**
bogdanm	85:024bf7f99721	354	* @}
bogdanm	85:024bf7f99721	355	*/
bogdanm	85:024bf7f99721	356
Kojto	108:34e6b704fe68	357	#endif /* SYSCFG_CFGR1_DMA_RMP */
bogdanm	85:024bf7f99721	358	/**
bogdanm	85:024bf7f99721	359	* @}
bogdanm	85:024bf7f99721	360	*/
bogdanm	92:4fc01daae5a5	361
Kojto	108:34e6b704fe68	362	/* Exported macro ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	363	/** @defgroup DMA_Exported_Macros DMA Exported Macros
bogdanm	92:4fc01daae5a5	364	* @{
bogdanm	92:4fc01daae5a5	365	*/
bogdanm	85:024bf7f99721	366
bogdanm	85:024bf7f99721	367	/** @brief Reset DMA handle state
bogdanm	85:024bf7f99721	368	* @param __HANDLE__: DMA handle.
bogdanm	85:024bf7f99721	369	* @retval None
bogdanm	85:024bf7f99721	370	*/
bogdanm	85:024bf7f99721	371	#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm	85:024bf7f99721	372
bogdanm	85:024bf7f99721	373	/**
bogdanm	85:024bf7f99721	374	* @brief Enable the specified DMA Channel.
bogdanm	85:024bf7f99721	375	* @param __HANDLE__: DMA handle
Kojto	108:34e6b704fe68	376	* @retval None
bogdanm	85:024bf7f99721	377	*/
<>	134:ad3be0349dc5	378	#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR \|= DMA_CCR_EN)
bogdanm	85:024bf7f99721	379
bogdanm	85:024bf7f99721	380	/**
bogdanm	85:024bf7f99721	381	* @brief Disable the specified DMA Channel.
bogdanm	85:024bf7f99721	382	* @param __HANDLE__: DMA handle
Kojto	108:34e6b704fe68	383	* @retval None
bogdanm	85:024bf7f99721	384	*/
<>	134:ad3be0349dc5	385	#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
bogdanm	85:024bf7f99721	386
bogdanm	85:024bf7f99721	387
bogdanm	85:024bf7f99721	388	/* Interrupt & Flag management */
bogdanm	85:024bf7f99721	389
bogdanm	85:024bf7f99721	390	/**
bogdanm	85:024bf7f99721	391	* @brief Enables the specified DMA Channel interrupts.
bogdanm	85:024bf7f99721	392	* @param __HANDLE__: DMA handle
bogdanm	85:024bf7f99721	393	* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm	85:024bf7f99721	394	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	395	* @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm	85:024bf7f99721	396	* @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm	85:024bf7f99721	397	* @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm	85:024bf7f99721	398	* @retval None
bogdanm	85:024bf7f99721	399	*/
<>	134:ad3be0349dc5	400	#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR \|= (__INTERRUPT__))
bogdanm	85:024bf7f99721	401
bogdanm	85:024bf7f99721	402	/**
bogdanm	85:024bf7f99721	403	* @brief Disables the specified DMA Channel interrupts.
bogdanm	85:024bf7f99721	404	* @param __HANDLE__: DMA handle
bogdanm	85:024bf7f99721	405	* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm	85:024bf7f99721	406	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	407	* @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm	85:024bf7f99721	408	* @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm	85:024bf7f99721	409	* @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm	85:024bf7f99721	410	* @retval None
bogdanm	85:024bf7f99721	411	*/
<>	134:ad3be0349dc5	412	#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
bogdanm	85:024bf7f99721	413
bogdanm	85:024bf7f99721	414	/**
Kojto	108:34e6b704fe68	415	* @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
bogdanm	85:024bf7f99721	416	* @param __HANDLE__: DMA handle
bogdanm	85:024bf7f99721	417	* @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm	85:024bf7f99721	418	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	419	* @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm	85:024bf7f99721	420	* @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm	85:024bf7f99721	421	* @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm	85:024bf7f99721	422	* @retval The state of DMA_IT (SET or RESET).
bogdanm	85:024bf7f99721	423	*/
<>	134:ad3be0349dc5	424	#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
bogdanm	85:024bf7f99721	425
Kojto	122:f9eeca106725	426	/**
Kojto	122:f9eeca106725	427	* @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
Kojto	122:f9eeca106725	428	* @param __HANDLE__: DMA handle
Kojto	122:f9eeca106725	429	*
Kojto	122:f9eeca106725	430	* @retval The number of remaining data units in the current DMA Channel transfer.
Kojto	122:f9eeca106725	431	*/
Kojto	122:f9eeca106725	432	#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Kojto	122:f9eeca106725	433
Kojto	108:34e6b704fe68	434	#if defined(SYSCFG_CFGR1_DMA_RMP)
Kojto	108:34e6b704fe68	435	/** @brief DMA remapping enable/disable macros
Kojto	108:34e6b704fe68	436	* @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
Kojto	108:34e6b704fe68	437	*/
Kojto	108:34e6b704fe68	438	#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
Kojto	108:34e6b704fe68	439	SYSCFG->CFGR1 \|= (__DMA_REMAP__); \
Kojto	108:34e6b704fe68	440	}while(0)
Kojto	108:34e6b704fe68	441	#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
Kojto	108:34e6b704fe68	442	SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
Kojto	108:34e6b704fe68	443	}while(0)
Kojto	108:34e6b704fe68	444	#endif /* SYSCFG_CFGR1_DMA_RMP */
Kojto	108:34e6b704fe68	445
bogdanm	85:024bf7f99721	446	/**
bogdanm	85:024bf7f99721	447	* @}
bogdanm	85:024bf7f99721	448	*/
bogdanm	85:024bf7f99721	449
bogdanm	85:024bf7f99721	450	/* Include DMA HAL Extension module */
bogdanm	85:024bf7f99721	451	#include "stm32f0xx_hal_dma_ex.h"
bogdanm	85:024bf7f99721	452
bogdanm	85:024bf7f99721	453	/* Exported functions --------------------------------------------------------*/
Kojto	108:34e6b704fe68	454	/** @addtogroup DMA_Exported_Functions
bogdanm	92:4fc01daae5a5	455	* @{
bogdanm	92:4fc01daae5a5	456	*/
Kojto	108:34e6b704fe68	457
bogdanm	92:4fc01daae5a5	458	/** @addtogroup DMA_Exported_Functions_Group1
bogdanm	92:4fc01daae5a5	459	* @{
bogdanm	92:4fc01daae5a5	460	*/
bogdanm	85:024bf7f99721	461	/* Initialization and de-initialization functions *****************************/
bogdanm	85:024bf7f99721	462	HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm	85:024bf7f99721	463	HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
bogdanm	92:4fc01daae5a5	464	/**
bogdanm	92:4fc01daae5a5	465	* @}
bogdanm	92:4fc01daae5a5	466	*/
bogdanm	85:024bf7f99721	467
bogdanm	92:4fc01daae5a5	468	/** @addtogroup DMA_Exported_Functions_Group2
bogdanm	92:4fc01daae5a5	469	* @{
bogdanm	92:4fc01daae5a5	470	*/
Kojto	108:34e6b704fe68	471	/* Input and Output operation functions *****************************************************/
bogdanm	85:024bf7f99721	472	HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm	85:024bf7f99721	473	HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm	85:024bf7f99721	474	HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
Kojto	122:f9eeca106725	475	HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
bogdanm	85:024bf7f99721	476	HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm	85:024bf7f99721	477	void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
<>	134:ad3be0349dc5	478	HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void ( pCallback)( DMA_HandleTypeDef * _hdma));
<>	134:ad3be0349dc5	479	HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
<>	134:ad3be0349dc5	480
bogdanm	92:4fc01daae5a5	481	/**
bogdanm	92:4fc01daae5a5	482	* @}
bogdanm	92:4fc01daae5a5	483	*/
bogdanm	85:024bf7f99721	484
bogdanm	92:4fc01daae5a5	485	/** @addtogroup DMA_Exported_Functions_Group3
bogdanm	92:4fc01daae5a5	486	* @{
bogdanm	92:4fc01daae5a5	487	*/
Kojto	108:34e6b704fe68	488	/* Peripheral State and Error functions ***************************************/
bogdanm	85:024bf7f99721	489	HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm	85:024bf7f99721	490	uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
bogdanm	92:4fc01daae5a5	491	/**
bogdanm	92:4fc01daae5a5	492	* @}
Kojto	108:34e6b704fe68	493	*/
Kojto	108:34e6b704fe68	494
Kojto	108:34e6b704fe68	495	/**
Kojto	108:34e6b704fe68	496	* @}
Kojto	108:34e6b704fe68	497	*/
Kojto	108:34e6b704fe68	498
Kojto	108:34e6b704fe68	499	/** @addtogroup DMA_Private_Macros
Kojto	108:34e6b704fe68	500	* @{
bogdanm	92:4fc01daae5a5	501	*/
Kojto	108:34e6b704fe68	502	#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) \|\| \
Kojto	108:34e6b704fe68	503	((DIRECTION) == DMA_MEMORY_TO_PERIPH) \|\| \
Kojto	108:34e6b704fe68	504	((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto	108:34e6b704fe68	505	#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) \|\| \
Kojto	108:34e6b704fe68	506	((STATE) == DMA_PINC_DISABLE))
Kojto	108:34e6b704fe68	507
Kojto	108:34e6b704fe68	508	#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) \|\| \
Kojto	108:34e6b704fe68	509	((STATE) == DMA_MINC_DISABLE))
Kojto	108:34e6b704fe68	510
Kojto	108:34e6b704fe68	511	#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) \|\| \
Kojto	108:34e6b704fe68	512	((SIZE) == DMA_PDATAALIGN_HALFWORD) \|\| \
Kojto	108:34e6b704fe68	513	((SIZE) == DMA_PDATAALIGN_WORD))
Kojto	108:34e6b704fe68	514
Kojto	108:34e6b704fe68	515	#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) \|\| \
Kojto	108:34e6b704fe68	516	((SIZE) == DMA_MDATAALIGN_HALFWORD) \|\| \
Kojto	108:34e6b704fe68	517	((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto	108:34e6b704fe68	518
Kojto	108:34e6b704fe68	519	#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) \|\| \
Kojto	108:34e6b704fe68	520	((MODE) == DMA_CIRCULAR))
Kojto	108:34e6b704fe68	521	#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) \|\| \
Kojto	108:34e6b704fe68	522	((PRIORITY) == DMA_PRIORITY_MEDIUM) \|\| \
Kojto	108:34e6b704fe68	523	((PRIORITY) == DMA_PRIORITY_HIGH) \|\| \
Kojto	108:34e6b704fe68	524	((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
<>	134:ad3be0349dc5	525	#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
Kojto	108:34e6b704fe68	526
Kojto	108:34e6b704fe68	527	#if defined(SYSCFG_CFGR1_DMA_RMP)
Kojto	108:34e6b704fe68	528
Kojto	108:34e6b704fe68	529	#if defined (STM32F071xB) \|\| defined (STM32F072xB) \|\| defined (STM32F078xx)
Kojto	108:34e6b704fe68	530	#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) \|\| \
Kojto	108:34e6b704fe68	531	((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) \|\| \
Kojto	108:34e6b704fe68	532	((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) \|\| \
Kojto	108:34e6b704fe68	533	((RMP) == DMA_REMAP_TIM16_DMA_CH4) \|\| \
Kojto	108:34e6b704fe68	534	((RMP) == DMA_REMAP_TIM17_DMA_CH2) \|\| \
Kojto	108:34e6b704fe68	535	((RMP) == DMA_REMAP_TIM16_DMA_CH6) \|\| \
Kojto	108:34e6b704fe68	536	((RMP) == DMA_REMAP_TIM17_DMA_CH7) \|\| \
Kojto	108:34e6b704fe68	537	((RMP) == DMA_REMAP_SPI2_DMA_CH67) \|\| \
Kojto	108:34e6b704fe68	538	((RMP) == DMA_REMAP_USART2_DMA_CH67) \|\| \
Kojto	108:34e6b704fe68	539	((RMP) == DMA_REMAP_USART3_DMA_CH32) \|\| \
Kojto	108:34e6b704fe68	540	((RMP) == DMA_REMAP_I2C1_DMA_CH76) \|\| \
Kojto	108:34e6b704fe68	541	((RMP) == DMA_REMAP_TIM1_DMA_CH6) \|\| \
Kojto	108:34e6b704fe68	542	((RMP) == DMA_REMAP_TIM2_DMA_CH7) \|\| \
Kojto	108:34e6b704fe68	543	((RMP) == DMA_REMAP_TIM3_DMA_CH6))
Kojto	108:34e6b704fe68	544	#elif defined (STM32F070xB)
Kojto	108:34e6b704fe68	545	#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) \|\| \
Kojto	108:34e6b704fe68	546	((RMP) == DMA_REMAP_ADC_DMA_CH2) \|\| \
Kojto	108:34e6b704fe68	547	((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) \|\| \
Kojto	108:34e6b704fe68	548	((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) \|\| \
Kojto	108:34e6b704fe68	549	((RMP) == DMA_REMAP_TIM16_DMA_CH4) \|\| \
Kojto	108:34e6b704fe68	550	((RMP) == DMA_REMAP_TIM17_DMA_CH2))
Kojto	108:34e6b704fe68	551	#else
Kojto	108:34e6b704fe68	552	#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) \|\| \
Kojto	108:34e6b704fe68	553	((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) \|\| \
Kojto	108:34e6b704fe68	554	((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) \|\| \
Kojto	108:34e6b704fe68	555	((RMP) == DMA_REMAP_TIM16_DMA_CH4) \|\| \
Kojto	108:34e6b704fe68	556	((RMP) == DMA_REMAP_TIM17_DMA_CH2))
Kojto	108:34e6b704fe68	557	#endif
Kojto	108:34e6b704fe68	558
Kojto	108:34e6b704fe68	559	#endif /* SYSCFG_CFGR1_DMA_RMP */
Kojto	108:34e6b704fe68	560
Kojto	108:34e6b704fe68	561
Kojto	108:34e6b704fe68	562	/**
Kojto	108:34e6b704fe68	563	* @}
Kojto	108:34e6b704fe68	564	*/
bogdanm	92:4fc01daae5a5	565
bogdanm	92:4fc01daae5a5	566	/**
bogdanm	92:4fc01daae5a5	567	* @}
bogdanm	92:4fc01daae5a5	568	*/
bogdanm	85:024bf7f99721	569
bogdanm	85:024bf7f99721	570	/**
bogdanm	85:024bf7f99721	571	* @}
bogdanm	85:024bf7f99721	572	*/
bogdanm	85:024bf7f99721	573
bogdanm	85:024bf7f99721	574	#ifdef __cplusplus
bogdanm	85:024bf7f99721	575	}
bogdanm	85:024bf7f99721	576	#endif
bogdanm	85:024bf7f99721	577
bogdanm	85:024bf7f99721	578	#endif /* __STM32F0xx_HAL_DMA_H */
bogdanm	85:024bf7f99721	579
bogdanm	85:024bf7f99721	580	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	92:4fc01daae5a5	581