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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
134:ad3be0349dc5 
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 85:024bf7f99721 1 /**
bogdanm 85:024bf7f99721 2 ******************************************************************************
bogdanm 85:024bf7f99721 3 * @file stm32f0xx_hal.h
bogdanm 85:024bf7f99721 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.5.0
<> 134:ad3be0349dc5 6 * @date 04-November-2016
bogdanm 85:024bf7f99721 7 * @brief This file contains all the functions prototypes for the HAL
bogdanm 85:024bf7f99721 8 * module driver.
bogdanm 85:024bf7f99721 9 ******************************************************************************
bogdanm 85:024bf7f99721 10 * @attention
bogdanm 85:024bf7f99721 11 *
Kojto 122:f9eeca106725 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 85:024bf7f99721 13 *
bogdanm 85:024bf7f99721 14 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 85:024bf7f99721 15 * are permitted provided that the following conditions are met:
bogdanm 85:024bf7f99721 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 85:024bf7f99721 17 * this list of conditions and the following disclaimer.
bogdanm 85:024bf7f99721 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 85:024bf7f99721 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 85:024bf7f99721 20 * and/or other materials provided with the distribution.
bogdanm 85:024bf7f99721 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 85:024bf7f99721 22 * may be used to endorse or promote products derived from this software
bogdanm 85:024bf7f99721 23 * without specific prior written permission.
bogdanm 85:024bf7f99721 24 *
bogdanm 85:024bf7f99721 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 85:024bf7f99721 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 85:024bf7f99721 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 85:024bf7f99721 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 85:024bf7f99721 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 85:024bf7f99721 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 85:024bf7f99721 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 85:024bf7f99721 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 85:024bf7f99721 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 85:024bf7f99721 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 85:024bf7f99721 35 *
bogdanm 85:024bf7f99721 36 ******************************************************************************
bogdanm 85:024bf7f99721 37 */
bogdanm 85:024bf7f99721 38
bogdanm 85:024bf7f99721 39 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 85:024bf7f99721 40 #ifndef __STM32F0xx_HAL_H
bogdanm 85:024bf7f99721 41 #define __STM32F0xx_HAL_H
bogdanm 85:024bf7f99721 42
bogdanm 85:024bf7f99721 43 #ifdef __cplusplus
bogdanm 85:024bf7f99721 44 extern "C" {
bogdanm 85:024bf7f99721 45 #endif
bogdanm 85:024bf7f99721 46
bogdanm 85:024bf7f99721 47 /* Includes ------------------------------------------------------------------*/
bogdanm 85:024bf7f99721 48 #include "stm32f0xx_hal_conf.h"
bogdanm 85:024bf7f99721 49
bogdanm 85:024bf7f99721 50 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 85:024bf7f99721 51 * @{
bogdanm 85:024bf7f99721 52 */
bogdanm 85:024bf7f99721 53
bogdanm 85:024bf7f99721 54 /** @addtogroup HAL
bogdanm 85:024bf7f99721 55 * @{
bogdanm 85:024bf7f99721 56 */
bogdanm 85:024bf7f99721 57
Kojto 108:34e6b704fe68 58 /* Private macros ------------------------------------------------------------*/
Kojto 108:34e6b704fe68 59 /** @addtogroup HAL_Private_Macros
Kojto 108:34e6b704fe68 60 * @{
Kojto 108:34e6b704fe68 61 */
Kojto 108:34e6b704fe68 62 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 108:34e6b704fe68 63 defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
Kojto 108:34e6b704fe68 64 defined(STM32F070xB) || defined(STM32F030x6)
Kojto 108:34e6b704fe68 65 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \
Kojto 108:34e6b704fe68 66 (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
Kojto 108:34e6b704fe68 67 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
Kojto 108:34e6b704fe68 68 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
Kojto 108:34e6b704fe68 69 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
Kojto 108:34e6b704fe68 70 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
Kojto 108:34e6b704fe68 71 #else
Kojto 108:34e6b704fe68 72 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
Kojto 108:34e6b704fe68 73 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
Kojto 108:34e6b704fe68 74 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
Kojto 108:34e6b704fe68 75 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
Kojto 108:34e6b704fe68 76 #endif
Kojto 108:34e6b704fe68 77 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
Kojto 108:34e6b704fe68 78 #define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
Kojto 108:34e6b704fe68 79 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
Kojto 108:34e6b704fe68 80 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 108:34e6b704fe68 81 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
Kojto 108:34e6b704fe68 82 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
Kojto 108:34e6b704fe68 83 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
Kojto 108:34e6b704fe68 84 #endif /* STM32F091xC || STM32F098xx */
Kojto 108:34e6b704fe68 85 /**
Kojto 108:34e6b704fe68 86 * @}
Kojto 108:34e6b704fe68 87 */
Kojto 108:34e6b704fe68 88
bogdanm 85:024bf7f99721 89 /* Exported types ------------------------------------------------------------*/
bogdanm 85:024bf7f99721 90 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 91 /** @defgroup HAL_Exported_Constants HAL Exported Constants
Kojto 108:34e6b704fe68 92 * @{
bogdanm 92:4fc01daae5a5 93 */
bogdanm 92:4fc01daae5a5 94
bogdanm 92:4fc01daae5a5 95 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
bogdanm 92:4fc01daae5a5 96 /** @defgroup HAL_Pin_remapping HAL Pin remapping
bogdanm 85:024bf7f99721 97 * @{
bogdanm 85:024bf7f99721 98 */
bogdanm 85:024bf7f99721 99 #define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins).
bogdanm 85:024bf7f99721 100 0: No remap (pin pair PA9/10 mapped on the pins)
bogdanm 85:024bf7f99721 101 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */
bogdanm 85:024bf7f99721 102
bogdanm 85:024bf7f99721 103 /**
bogdanm 85:024bf7f99721 104 * @}
bogdanm 85:024bf7f99721 105 */
bogdanm 92:4fc01daae5a5 106 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
bogdanm 85:024bf7f99721 107
Kojto 93:e188a91d3eaa 108 #if defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 92:4fc01daae5a5 109 /** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection
Kojto 93:e188a91d3eaa 110 * @note Applicable on STM32F09x
bogdanm 85:024bf7f99721 111 * @{
bogdanm 85:024bf7f99721 112 */
bogdanm 92:4fc01daae5a5 113 #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */
bogdanm 92:4fc01daae5a5 114 #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */
bogdanm 92:4fc01daae5a5 115 #define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */
bogdanm 92:4fc01daae5a5 116
bogdanm 92:4fc01daae5a5 117 /**
bogdanm 92:4fc01daae5a5 118 * @}
bogdanm 92:4fc01daae5a5 119 */
Kojto 93:e188a91d3eaa 120 #endif /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 121
bogdanm 92:4fc01daae5a5 122
Kojto 108:34e6b704fe68 123 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
bogdanm 92:4fc01daae5a5 124 * @{
bogdanm 92:4fc01daae5a5 125 */
bogdanm 92:4fc01daae5a5 126
Kojto 108:34e6b704fe68 127 /** @brief Fast-mode Plus driving capability on a specific GPIO
Kojto 108:34e6b704fe68 128 */
Kojto 108:34e6b704fe68 129 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 108:34e6b704fe68 130 defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
Kojto 108:34e6b704fe68 131 defined(STM32F070xB) || defined(STM32F030x6)
Kojto 108:34e6b704fe68 132 #define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */
Kojto 108:34e6b704fe68 133 #define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */
bogdanm 85:024bf7f99721 134 #endif
Kojto 108:34e6b704fe68 135 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */
Kojto 108:34e6b704fe68 136 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */
Kojto 108:34e6b704fe68 137 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */
Kojto 108:34e6b704fe68 138 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */
bogdanm 85:024bf7f99721 139
bogdanm 85:024bf7f99721 140 /**
Kojto 108:34e6b704fe68 141 * @}
Kojto 108:34e6b704fe68 142 */
Kojto 108:34e6b704fe68 143
bogdanm 85:024bf7f99721 144
bogdanm 92:4fc01daae5a5 145 #if defined(STM32F091xC) || defined (STM32F098xx)
bogdanm 92:4fc01daae5a5 146 /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
Kojto 93:e188a91d3eaa 147 * @brief ISR Wrapper
Kojto 93:e188a91d3eaa 148 * @note applicable on STM32F09x
bogdanm 92:4fc01daae5a5 149 * @{
bogdanm 92:4fc01daae5a5 150 */
<> 134:ad3be0349dc5 151 #define HAL_SYSCFG_ITLINE0 ( 0x00000000U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 152 #define HAL_SYSCFG_ITLINE1 ( 0x00000001U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 153 #define HAL_SYSCFG_ITLINE2 ( 0x00000002U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 154 #define HAL_SYSCFG_ITLINE3 ( 0x00000003U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 155 #define HAL_SYSCFG_ITLINE4 ( 0x00000004U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 156 #define HAL_SYSCFG_ITLINE5 ( 0x00000005U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 157 #define HAL_SYSCFG_ITLINE6 ( 0x00000006U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 158 #define HAL_SYSCFG_ITLINE7 ( 0x00000007U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 159 #define HAL_SYSCFG_ITLINE8 ( 0x00000008U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 160 #define HAL_SYSCFG_ITLINE9 ( 0x00000009U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 161 #define HAL_SYSCFG_ITLINE10 ( 0x0000000AU) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 162 #define HAL_SYSCFG_ITLINE11 ( 0x0000000BU) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 163 #define HAL_SYSCFG_ITLINE12 ( 0x0000000CU) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 164 #define HAL_SYSCFG_ITLINE13 ( 0x0000000DU) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 165 #define HAL_SYSCFG_ITLINE14 ( 0x0000000EU) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 166 #define HAL_SYSCFG_ITLINE15 ( 0x0000000FU) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 167 #define HAL_SYSCFG_ITLINE16 ( 0x00000010U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 168 #define HAL_SYSCFG_ITLINE17 ( 0x00000011U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 169 #define HAL_SYSCFG_ITLINE18 ( 0x00000012U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 170 #define HAL_SYSCFG_ITLINE19 ( 0x00000013U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 171 #define HAL_SYSCFG_ITLINE20 ( 0x00000014U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 172 #define HAL_SYSCFG_ITLINE21 ( 0x00000015U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 173 #define HAL_SYSCFG_ITLINE22 ( 0x00000016U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 174 #define HAL_SYSCFG_ITLINE23 ( 0x00000017U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 175 #define HAL_SYSCFG_ITLINE24 ( 0x00000018U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 176 #define HAL_SYSCFG_ITLINE25 ( 0x00000019U) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 177 #define HAL_SYSCFG_ITLINE26 ( 0x0000001AU) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 178 #define HAL_SYSCFG_ITLINE27 ( 0x0000001BU) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 179 #define HAL_SYSCFG_ITLINE28 ( 0x0000001CU) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 180 #define HAL_SYSCFG_ITLINE29 ( 0x0000001DU) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 181 #define HAL_SYSCFG_ITLINE30 ( 0x0000001EU) /*!< Internal define for macro handling */
<> 134:ad3be0349dc5 182 #define HAL_SYSCFG_ITLINE31 ( 0x0000001FU) /*!< Internal define for macro handling */
bogdanm 92:4fc01daae5a5 183
<> 134:ad3be0349dc5 184 #define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */
bogdanm 92:4fc01daae5a5 185 #if defined(STM32F091xC)
<> 134:ad3be0349dc5 186 #define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */
bogdanm 92:4fc01daae5a5 187 #endif
<> 134:ad3be0349dc5 188 #define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */
<> 134:ad3be0349dc5 189 #define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */
<> 134:ad3be0349dc5 190 #define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */
<> 134:ad3be0349dc5 191 #define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */
<> 134:ad3be0349dc5 192 #define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */
<> 134:ad3be0349dc5 193 #define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */
<> 134:ad3be0349dc5 194 #define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */
<> 134:ad3be0349dc5 195 #define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */
<> 134:ad3be0349dc5 196 #define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */
<> 134:ad3be0349dc5 197 #define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */
<> 134:ad3be0349dc5 198 #define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */
<> 134:ad3be0349dc5 199 #define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */
<> 134:ad3be0349dc5 200 #define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */
<> 134:ad3be0349dc5 201 #define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */
<> 134:ad3be0349dc5 202 #define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */
<> 134:ad3be0349dc5 203 #define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */
<> 134:ad3be0349dc5 204 #define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */
<> 134:ad3be0349dc5 205 #define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */
<> 134:ad3be0349dc5 206 #define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */
<> 134:ad3be0349dc5 207 #define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */
<> 134:ad3be0349dc5 208 #define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */
<> 134:ad3be0349dc5 209 #define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */
<> 134:ad3be0349dc5 210 #define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */
<> 134:ad3be0349dc5 211 #define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */
<> 134:ad3be0349dc5 212 #define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */
<> 134:ad3be0349dc5 213 #define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */
<> 134:ad3be0349dc5 214 #define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */
<> 134:ad3be0349dc5 215 #define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */
<> 134:ad3be0349dc5 216 #define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */
<> 134:ad3be0349dc5 217 #define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */
<> 134:ad3be0349dc5 218 #define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */
<> 134:ad3be0349dc5 219 #define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */
<> 134:ad3be0349dc5 220 #define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */
<> 134:ad3be0349dc5 221 #define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */
<> 134:ad3be0349dc5 222 #define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */
<> 134:ad3be0349dc5 223 #define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */
<> 134:ad3be0349dc5 224 #define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */
<> 134:ad3be0349dc5 225 #define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */
<> 134:ad3be0349dc5 226 #define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */
<> 134:ad3be0349dc5 227 #define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */
<> 134:ad3be0349dc5 228 #define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */
<> 134:ad3be0349dc5 229 #define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */
<> 134:ad3be0349dc5 230 #define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */
<> 134:ad3be0349dc5 231 #define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */
<> 134:ad3be0349dc5 232 #define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */
<> 134:ad3be0349dc5 233 #define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */
<> 134:ad3be0349dc5 234 #define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */
<> 134:ad3be0349dc5 235 #define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */
<> 134:ad3be0349dc5 236 #define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */
<> 134:ad3be0349dc5 237 #define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */
<> 134:ad3be0349dc5 238 #define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */
<> 134:ad3be0349dc5 239 #define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */
<> 134:ad3be0349dc5 240 #define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */
<> 134:ad3be0349dc5 241 #define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */
<> 134:ad3be0349dc5 242 #define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */
<> 134:ad3be0349dc5 243 #define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */
<> 134:ad3be0349dc5 244 #define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */
<> 134:ad3be0349dc5 245 #define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */
<> 134:ad3be0349dc5 246 #define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */
<> 134:ad3be0349dc5 247 #define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */
<> 134:ad3be0349dc5 248 #define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */
<> 134:ad3be0349dc5 249 #define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */
<> 134:ad3be0349dc5 250 #define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */
<> 134:ad3be0349dc5 251 #define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */
<> 134:ad3be0349dc5 252 #define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */
<> 134:ad3be0349dc5 253 #define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */
<> 134:ad3be0349dc5 254 #define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */
<> 134:ad3be0349dc5 255 #define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */
bogdanm 92:4fc01daae5a5 256 /**
bogdanm 92:4fc01daae5a5 257 * @}
bogdanm 92:4fc01daae5a5 258 */
bogdanm 92:4fc01daae5a5 259 #endif /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 260
bogdanm 92:4fc01daae5a5 261 /**
bogdanm 92:4fc01daae5a5 262 * @}
bogdanm 92:4fc01daae5a5 263 */
bogdanm 85:024bf7f99721 264
bogdanm 85:024bf7f99721 265 /* Exported macros -----------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 266 /** @defgroup HAL_Exported_Macros HAL Exported Macros
bogdanm 92:4fc01daae5a5 267 * @{
bogdanm 92:4fc01daae5a5 268 */
bogdanm 85:024bf7f99721 269
bogdanm 92:4fc01daae5a5 270 /** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals
bogdanm 92:4fc01daae5a5 271 * @brief Freeze/Unfreeze Peripherals in Debug mode
bogdanm 92:4fc01daae5a5 272 * @{
bogdanm 85:024bf7f99721 273 */
bogdanm 92:4fc01daae5a5 274
bogdanm 92:4fc01daae5a5 275 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
bogdanm 92:4fc01daae5a5 276 #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
bogdanm 92:4fc01daae5a5 277 #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
bogdanm 92:4fc01daae5a5 278 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
bogdanm 85:024bf7f99721 279
bogdanm 92:4fc01daae5a5 280 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
Kojto 108:34e6b704fe68 281 #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
Kojto 108:34e6b704fe68 282 #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
bogdanm 92:4fc01daae5a5 283 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
bogdanm 85:024bf7f99721 284
bogdanm 92:4fc01daae5a5 285 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
Kojto 108:34e6b704fe68 286 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
Kojto 108:34e6b704fe68 287 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
bogdanm 92:4fc01daae5a5 288 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
bogdanm 85:024bf7f99721 289
bogdanm 92:4fc01daae5a5 290 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
Kojto 108:34e6b704fe68 291 #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
Kojto 108:34e6b704fe68 292 #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
bogdanm 92:4fc01daae5a5 293 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
bogdanm 85:024bf7f99721 294
bogdanm 92:4fc01daae5a5 295 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
Kojto 108:34e6b704fe68 296 #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
Kojto 108:34e6b704fe68 297 #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
bogdanm 92:4fc01daae5a5 298 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
bogdanm 92:4fc01daae5a5 299
bogdanm 92:4fc01daae5a5 300 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
Kojto 108:34e6b704fe68 301 #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
Kojto 108:34e6b704fe68 302 #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
bogdanm 92:4fc01daae5a5 303 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
bogdanm 85:024bf7f99721 304
bogdanm 92:4fc01daae5a5 305 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
Kojto 108:34e6b704fe68 306 #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
Kojto 108:34e6b704fe68 307 #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
bogdanm 92:4fc01daae5a5 308 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
bogdanm 92:4fc01daae5a5 309
bogdanm 92:4fc01daae5a5 310 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
Kojto 108:34e6b704fe68 311 #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
Kojto 108:34e6b704fe68 312 #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
bogdanm 92:4fc01daae5a5 313 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
bogdanm 85:024bf7f99721 314
bogdanm 92:4fc01daae5a5 315 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
Kojto 108:34e6b704fe68 316 #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
Kojto 108:34e6b704fe68 317 #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
bogdanm 92:4fc01daae5a5 318 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
bogdanm 85:024bf7f99721 319
bogdanm 92:4fc01daae5a5 320 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
Kojto 108:34e6b704fe68 321 #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
Kojto 108:34e6b704fe68 322 #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
bogdanm 92:4fc01daae5a5 323 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
bogdanm 85:024bf7f99721 324
bogdanm 92:4fc01daae5a5 325 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
Kojto 108:34e6b704fe68 326 #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
Kojto 108:34e6b704fe68 327 #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
bogdanm 92:4fc01daae5a5 328 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
bogdanm 85:024bf7f99721 329
bogdanm 92:4fc01daae5a5 330 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
Kojto 108:34e6b704fe68 331 #define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
Kojto 108:34e6b704fe68 332 #define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
bogdanm 92:4fc01daae5a5 333 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
bogdanm 85:024bf7f99721 334
bogdanm 92:4fc01daae5a5 335 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
Kojto 108:34e6b704fe68 336 #define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
Kojto 108:34e6b704fe68 337 #define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
bogdanm 92:4fc01daae5a5 338 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
bogdanm 85:024bf7f99721 339
bogdanm 92:4fc01daae5a5 340 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
Kojto 108:34e6b704fe68 341 #define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
Kojto 108:34e6b704fe68 342 #define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
bogdanm 92:4fc01daae5a5 343 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
bogdanm 85:024bf7f99721 344
bogdanm 92:4fc01daae5a5 345 /**
bogdanm 92:4fc01daae5a5 346 * @}
bogdanm 92:4fc01daae5a5 347 */
bogdanm 92:4fc01daae5a5 348
bogdanm 92:4fc01daae5a5 349 /** @defgroup Memory_Mapping_Selection Memory Mapping Selection
bogdanm 92:4fc01daae5a5 350 * @{
bogdanm 92:4fc01daae5a5 351 */
bogdanm 92:4fc01daae5a5 352 #if defined(SYSCFG_CFGR1_MEM_MODE)
bogdanm 85:024bf7f99721 353 /** @brief Main Flash memory mapped at 0x00000000
bogdanm 85:024bf7f99721 354 */
Kojto 108:34e6b704fe68 355 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
bogdanm 92:4fc01daae5a5 356 #endif /* SYSCFG_CFGR1_MEM_MODE */
bogdanm 85:024bf7f99721 357
bogdanm 92:4fc01daae5a5 358 #if defined(SYSCFG_CFGR1_MEM_MODE_0)
bogdanm 85:024bf7f99721 359 /** @brief System Flash memory mapped at 0x00000000
bogdanm 85:024bf7f99721 360 */
Kojto 108:34e6b704fe68 361 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
bogdanm 85:024bf7f99721 362 SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
bogdanm 85:024bf7f99721 363 }while(0)
bogdanm 92:4fc01daae5a5 364 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
bogdanm 85:024bf7f99721 365
bogdanm 92:4fc01daae5a5 366 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
bogdanm 85:024bf7f99721 367 /** @brief Embedded SRAM mapped at 0x00000000
bogdanm 85:024bf7f99721 368 */
Kojto 108:34e6b704fe68 369 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
bogdanm 85:024bf7f99721 370 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
bogdanm 92:4fc01daae5a5 371 }while(0)
bogdanm 92:4fc01daae5a5 372 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
bogdanm 92:4fc01daae5a5 373 /**
bogdanm 92:4fc01daae5a5 374 * @}
bogdanm 92:4fc01daae5a5 375 */
bogdanm 85:024bf7f99721 376
bogdanm 85:024bf7f99721 377
bogdanm 92:4fc01daae5a5 378 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
bogdanm 92:4fc01daae5a5 379 /** @defgroup HAL_Pin_remap HAL Pin remap
bogdanm 92:4fc01daae5a5 380 * @brief Pin remapping enable/disable macros
bogdanm 92:4fc01daae5a5 381 * @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_remapping
bogdanm 92:4fc01daae5a5 382 * @{
bogdanm 85:024bf7f99721 383 */
bogdanm 85:024bf7f99721 384 #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
bogdanm 85:024bf7f99721 385 SYSCFG->CFGR1 |= (__PIN_REMAP__); \
bogdanm 85:024bf7f99721 386 }while(0)
bogdanm 92:4fc01daae5a5 387 #define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
bogdanm 85:024bf7f99721 388 SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \
bogdanm 85:024bf7f99721 389 }while(0)
bogdanm 92:4fc01daae5a5 390 /**
bogdanm 92:4fc01daae5a5 391 * @}
bogdanm 92:4fc01daae5a5 392 */
bogdanm 92:4fc01daae5a5 393 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
bogdanm 85:024bf7f99721 394
Kojto 108:34e6b704fe68 395 /** @brief Fast-mode Plus driving capability enable/disable macros
Kojto 108:34e6b704fe68 396 * @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
Kojto 108:34e6b704fe68 397 * That you can find above these macros.
bogdanm 85:024bf7f99721 398 */
Kojto 108:34e6b704fe68 399 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
Kojto 108:34e6b704fe68 400 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
bogdanm 85:024bf7f99721 401 }while(0)
bogdanm 85:024bf7f99721 402
Kojto 108:34e6b704fe68 403 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
Kojto 108:34e6b704fe68 404 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
bogdanm 85:024bf7f99721 405 }while(0)
bogdanm 92:4fc01daae5a5 406 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
bogdanm 92:4fc01daae5a5 407 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
bogdanm 92:4fc01daae5a5 408 * @{
bogdanm 92:4fc01daae5a5 409 */
bogdanm 85:024bf7f99721 410 /** @brief SYSCFG Break Lockup lock
bogdanm 85:024bf7f99721 411 * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
bogdanm 85:024bf7f99721 412 * @note The selected configuration is locked and can be unlocked by system reset
bogdanm 85:024bf7f99721 413 */
bogdanm 85:024bf7f99721 414 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
bogdanm 85:024bf7f99721 415 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
bogdanm 85:024bf7f99721 416 }while(0)
bogdanm 92:4fc01daae5a5 417 /**
bogdanm 92:4fc01daae5a5 418 * @}
bogdanm 92:4fc01daae5a5 419 */
bogdanm 92:4fc01daae5a5 420 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
bogdanm 85:024bf7f99721 421
bogdanm 92:4fc01daae5a5 422 #if defined(SYSCFG_CFGR2_PVD_LOCK)
bogdanm 92:4fc01daae5a5 423 /** @defgroup PVD_Lock_Enable PVD Lock
bogdanm 92:4fc01daae5a5 424 * @{
bogdanm 92:4fc01daae5a5 425 */
bogdanm 85:024bf7f99721 426 /** @brief SYSCFG Break PVD lock
bogdanm 85:024bf7f99721 427 * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
bogdanm 85:024bf7f99721 428 * @note The selected configuration is locked and can be unlocked by system reset
bogdanm 85:024bf7f99721 429 */
bogdanm 85:024bf7f99721 430 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
bogdanm 85:024bf7f99721 431 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
bogdanm 85:024bf7f99721 432 }while(0)
bogdanm 92:4fc01daae5a5 433 /**
bogdanm 92:4fc01daae5a5 434 * @}
bogdanm 92:4fc01daae5a5 435 */
bogdanm 92:4fc01daae5a5 436 #endif /* SYSCFG_CFGR2_PVD_LOCK */
bogdanm 85:024bf7f99721 437
bogdanm 92:4fc01daae5a5 438 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
bogdanm 92:4fc01daae5a5 439 /** @defgroup SRAM_Parity_Lock SRAM Parity Lock
bogdanm 92:4fc01daae5a5 440 * @{
bogdanm 92:4fc01daae5a5 441 */
bogdanm 85:024bf7f99721 442 /** @brief SYSCFG Break SRAM PARITY lock
bogdanm 85:024bf7f99721 443 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
bogdanm 85:024bf7f99721 444 * @note The selected configuration is locked and can be unlocked by system reset
bogdanm 85:024bf7f99721 445 */
bogdanm 85:024bf7f99721 446 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
bogdanm 85:024bf7f99721 447 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
bogdanm 85:024bf7f99721 448 }while(0)
bogdanm 92:4fc01daae5a5 449 /**
bogdanm 92:4fc01daae5a5 450 * @}
bogdanm 92:4fc01daae5a5 451 */
bogdanm 92:4fc01daae5a5 452 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
bogdanm 85:024bf7f99721 453
bogdanm 92:4fc01daae5a5 454 #if defined(SYSCFG_CFGR2_SRAM_PEF)
bogdanm 92:4fc01daae5a5 455 /** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM
bogdanm 85:024bf7f99721 456 * @brief Parity check on RAM disable macro
bogdanm 85:024bf7f99721 457 * @note Disabling the parity check on RAM locks the configuration bit.
bogdanm 85:024bf7f99721 458 * To re-enable the parity check on RAM perform a system reset.
bogdanm 92:4fc01daae5a5 459 * @{
bogdanm 85:024bf7f99721 460 */
bogdanm 85:024bf7f99721 461 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
bogdanm 92:4fc01daae5a5 462 /**
bogdanm 92:4fc01daae5a5 463 * @}
bogdanm 92:4fc01daae5a5 464 */
bogdanm 92:4fc01daae5a5 465 #endif /* SYSCFG_CFGR2_SRAM_PEF */
bogdanm 85:024bf7f99721 466
bogdanm 85:024bf7f99721 467
bogdanm 92:4fc01daae5a5 468 #if defined(STM32F091xC) || defined (STM32F098xx)
bogdanm 92:4fc01daae5a5 469 /** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check
bogdanm 92:4fc01daae5a5 470 * @brief ISR wrapper check
Kojto 93:e188a91d3eaa 471 * @note This feature is applicable on STM32F09x
Kojto 93:e188a91d3eaa 472 * @note Allow to determine interrupt source per line.
bogdanm 92:4fc01daae5a5 473 * @{
bogdanm 92:4fc01daae5a5 474 */
<> 134:ad3be0349dc5 475 #define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
bogdanm 92:4fc01daae5a5 476 /**
bogdanm 92:4fc01daae5a5 477 * @}
bogdanm 92:4fc01daae5a5 478 */
bogdanm 92:4fc01daae5a5 479 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
bogdanm 85:024bf7f99721 480
bogdanm 92:4fc01daae5a5 481 #if defined(STM32F091xC) || defined (STM32F098xx)
bogdanm 92:4fc01daae5a5 482 /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
bogdanm 92:4fc01daae5a5 483 * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
Kojto 93:e188a91d3eaa 484 * @note This feature is applicable on STM32F09x
bogdanm 92:4fc01daae5a5 485 * @param __SOURCE__: This parameter can be a value of @ref HAL_IRDA_ENV_SEL
bogdanm 92:4fc01daae5a5 486 * @{
bogdanm 92:4fc01daae5a5 487 */
bogdanm 92:4fc01daae5a5 488 #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
bogdanm 92:4fc01daae5a5 489 SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \
bogdanm 92:4fc01daae5a5 490 SYSCFG->CFGR1 |= (__SOURCE__); \
bogdanm 92:4fc01daae5a5 491 }while(0)
bogdanm 92:4fc01daae5a5 492
bogdanm 92:4fc01daae5a5 493 #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0)
bogdanm 92:4fc01daae5a5 494 /**
bogdanm 92:4fc01daae5a5 495 * @}
bogdanm 92:4fc01daae5a5 496 */
bogdanm 92:4fc01daae5a5 497 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
bogdanm 92:4fc01daae5a5 498
bogdanm 92:4fc01daae5a5 499 /**
bogdanm 92:4fc01daae5a5 500 * @}
Kojto 108:34e6b704fe68 501 */
Kojto 108:34e6b704fe68 502
bogdanm 92:4fc01daae5a5 503 /* Exported functions --------------------------------------------------------*/
Kojto 108:34e6b704fe68 504
Kojto 108:34e6b704fe68 505 /** @addtogroup HAL_Exported_Functions
bogdanm 92:4fc01daae5a5 506 * @{
bogdanm 92:4fc01daae5a5 507 */
bogdanm 92:4fc01daae5a5 508
Kojto 108:34e6b704fe68 509 /** @addtogroup HAL_Exported_Functions_Group1
bogdanm 92:4fc01daae5a5 510 * @{
bogdanm 92:4fc01daae5a5 511 */
bogdanm 92:4fc01daae5a5 512 /* Initialization and de-initialization functions ******************************/
bogdanm 85:024bf7f99721 513 HAL_StatusTypeDef HAL_Init(void);
bogdanm 85:024bf7f99721 514 HAL_StatusTypeDef HAL_DeInit(void);
bogdanm 85:024bf7f99721 515 void HAL_MspInit(void);
bogdanm 85:024bf7f99721 516 void HAL_MspDeInit(void);
bogdanm 85:024bf7f99721 517 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
bogdanm 92:4fc01daae5a5 518 /**
bogdanm 92:4fc01daae5a5 519 * @}
bogdanm 92:4fc01daae5a5 520 */
bogdanm 85:024bf7f99721 521
Kojto 108:34e6b704fe68 522 /** @addtogroup HAL_Exported_Functions_Group2
bogdanm 92:4fc01daae5a5 523 * @{
bogdanm 92:4fc01daae5a5 524 */
Kojto 108:34e6b704fe68 525
Kojto 108:34e6b704fe68 526 /* Peripheral Control functions ************************************************/
bogdanm 85:024bf7f99721 527 void HAL_IncTick(void);
bogdanm 85:024bf7f99721 528 void HAL_Delay(__IO uint32_t Delay);
bogdanm 85:024bf7f99721 529 uint32_t HAL_GetTick(void);
bogdanm 85:024bf7f99721 530 void HAL_SuspendTick(void);
bogdanm 85:024bf7f99721 531 void HAL_ResumeTick(void);
bogdanm 85:024bf7f99721 532 uint32_t HAL_GetHalVersion(void);
bogdanm 85:024bf7f99721 533 uint32_t HAL_GetREVID(void);
bogdanm 85:024bf7f99721 534 uint32_t HAL_GetDEVID(void);
Kojto 108:34e6b704fe68 535 void HAL_DBGMCU_EnableDBGStopMode(void);
Kojto 108:34e6b704fe68 536 void HAL_DBGMCU_DisableDBGStopMode(void);
Kojto 108:34e6b704fe68 537 void HAL_DBGMCU_EnableDBGStandbyMode(void);
Kojto 108:34e6b704fe68 538 void HAL_DBGMCU_DisableDBGStandbyMode(void);
bogdanm 92:4fc01daae5a5 539 /**
bogdanm 92:4fc01daae5a5 540 * @}
bogdanm 92:4fc01daae5a5 541 */
bogdanm 85:024bf7f99721 542
bogdanm 85:024bf7f99721 543 /**
bogdanm 85:024bf7f99721 544 * @}
Kojto 108:34e6b704fe68 545 */
Kojto 108:34e6b704fe68 546
Kojto 108:34e6b704fe68 547 /**
Kojto 108:34e6b704fe68 548 * @}
bogdanm 85:024bf7f99721 549 */
bogdanm 85:024bf7f99721 550
bogdanm 85:024bf7f99721 551 /**
bogdanm 85:024bf7f99721 552 * @}
Kojto 108:34e6b704fe68 553 */
bogdanm 92:4fc01daae5a5 554
bogdanm 85:024bf7f99721 555 #ifdef __cplusplus
bogdanm 85:024bf7f99721 556 }
bogdanm 85:024bf7f99721 557 #endif
bogdanm 85:024bf7f99721 558
bogdanm 85:024bf7f99721 559 #endif /* __STM32F0xx_HAL_H */
bogdanm 85:024bf7f99721 560
bogdanm 85:024bf7f99721 561 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/