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TARGET_TY51822R3/TOOLCHAIN_IAR/nrf51.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	143:86740a56073b	1
AnnaBridge	143:86740a56073b	2	/**************************************************************************************************//
AnnaBridge	143:86740a56073b	3	* @file nrf51.h
AnnaBridge	143:86740a56073b	4	*
AnnaBridge	143:86740a56073b	5	* @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
AnnaBridge	143:86740a56073b	6	* nrf51 from Nordic Semiconductor.
AnnaBridge	143:86740a56073b	7	*
AnnaBridge	143:86740a56073b	8	* @version V522
AnnaBridge	143:86740a56073b	9	* @date 23. February 2016
AnnaBridge	143:86740a56073b	10	*
AnnaBridge	143:86740a56073b	11	* @note Generated with SVDConv V2.81d
AnnaBridge	143:86740a56073b	12	* from CMSIS SVD File 'nrf51.svd' Version 522,
AnnaBridge	143:86740a56073b	13	*
AnnaBridge	143:86740a56073b	14	* @par Copyright (c) 2013, Nordic Semiconductor ASA
AnnaBridge	143:86740a56073b	15	* All rights reserved.
AnnaBridge	143:86740a56073b	16	*
AnnaBridge	143:86740a56073b	17	* Redistribution and use in source and binary forms, with or without
AnnaBridge	143:86740a56073b	18	* modification, are permitted provided that the following conditions are met:
AnnaBridge	143:86740a56073b	19	*
AnnaBridge	143:86740a56073b	20	* * Redistributions of source code must retain the above copyright notice, this
AnnaBridge	143:86740a56073b	21	* list of conditions and the following disclaimer.
AnnaBridge	143:86740a56073b	22	*
AnnaBridge	143:86740a56073b	23	* * Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	143:86740a56073b	24	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	143:86740a56073b	25	* and/or other materials provided with the distribution.
AnnaBridge	143:86740a56073b	26	*
AnnaBridge	143:86740a56073b	27	* * Neither the name of Nordic Semiconductor ASA nor the names of its
AnnaBridge	143:86740a56073b	28	* contributors may be used to endorse or promote products derived from
AnnaBridge	143:86740a56073b	29	* this software without specific prior written permission.
AnnaBridge	143:86740a56073b	30	*
AnnaBridge	143:86740a56073b	31	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	143:86740a56073b	32	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	143:86740a56073b	33	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	143:86740a56073b	34	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	143:86740a56073b	35	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	143:86740a56073b	36	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	143:86740a56073b	37	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	143:86740a56073b	38	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	143:86740a56073b	39	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	143:86740a56073b	40	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	143:86740a56073b	41	*
AnnaBridge	143:86740a56073b	42	*
AnnaBridge	143:86740a56073b	43	*******************************************************************************************************/
AnnaBridge	143:86740a56073b	44
AnnaBridge	143:86740a56073b	45
AnnaBridge	143:86740a56073b	46
AnnaBridge	143:86740a56073b	47	/** @addtogroup Nordic Semiconductor
AnnaBridge	143:86740a56073b	48	* @{
AnnaBridge	143:86740a56073b	49	*/
AnnaBridge	143:86740a56073b	50
AnnaBridge	143:86740a56073b	51	/** @addtogroup nrf51
AnnaBridge	143:86740a56073b	52	* @{
AnnaBridge	143:86740a56073b	53	*/
AnnaBridge	143:86740a56073b	54
AnnaBridge	143:86740a56073b	55	#ifndef NRF51_H
AnnaBridge	143:86740a56073b	56	#define NRF51_H
AnnaBridge	143:86740a56073b	57
AnnaBridge	143:86740a56073b	58	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	59	extern "C" {
AnnaBridge	143:86740a56073b	60	#endif
AnnaBridge	143:86740a56073b	61
AnnaBridge	143:86740a56073b	62
AnnaBridge	143:86740a56073b	63	/* ------------------------- Interrupt Number Definition ------------------------ */
AnnaBridge	143:86740a56073b	64
AnnaBridge	143:86740a56073b	65	typedef enum {
AnnaBridge	143:86740a56073b	66	/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
AnnaBridge	143:86740a56073b	67	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
AnnaBridge	143:86740a56073b	68	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
AnnaBridge	143:86740a56073b	69	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
AnnaBridge	143:86740a56073b	70	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
AnnaBridge	143:86740a56073b	71	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
AnnaBridge	143:86740a56073b	72	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
AnnaBridge	143:86740a56073b	73	SysTick_IRQn = -1, /!< 15 System Tick Timer /
AnnaBridge	143:86740a56073b	74	/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
AnnaBridge	143:86740a56073b	75	POWER_CLOCK_IRQn = 0, /!< 0 POWER_CLOCK /
AnnaBridge	143:86740a56073b	76	RADIO_IRQn = 1, /!< 1 RADIO /
AnnaBridge	143:86740a56073b	77	UART0_IRQn = 2, /!< 2 UART0 /
AnnaBridge	143:86740a56073b	78	SPI0_TWI0_IRQn = 3, /!< 3 SPI0_TWI0 /
AnnaBridge	143:86740a56073b	79	SPI1_TWI1_IRQn = 4, /!< 4 SPI1_TWI1 /
AnnaBridge	143:86740a56073b	80	GPIOTE_IRQn = 6, /!< 6 GPIOTE /
AnnaBridge	143:86740a56073b	81	ADC_IRQn = 7, /!< 7 ADC /
AnnaBridge	143:86740a56073b	82	TIMER0_IRQn = 8, /!< 8 TIMER0 /
AnnaBridge	143:86740a56073b	83	TIMER1_IRQn = 9, /!< 9 TIMER1 /
AnnaBridge	143:86740a56073b	84	TIMER2_IRQn = 10, /!< 10 TIMER2 /
AnnaBridge	143:86740a56073b	85	RTC0_IRQn = 11, /!< 11 RTC0 /
AnnaBridge	143:86740a56073b	86	TEMP_IRQn = 12, /!< 12 TEMP /
AnnaBridge	143:86740a56073b	87	RNG_IRQn = 13, /!< 13 RNG /
AnnaBridge	143:86740a56073b	88	ECB_IRQn = 14, /!< 14 ECB /
AnnaBridge	143:86740a56073b	89	CCM_AAR_IRQn = 15, /!< 15 CCM_AAR /
AnnaBridge	143:86740a56073b	90	WDT_IRQn = 16, /!< 16 WDT /
AnnaBridge	143:86740a56073b	91	RTC1_IRQn = 17, /!< 17 RTC1 /
AnnaBridge	143:86740a56073b	92	QDEC_IRQn = 18, /!< 18 QDEC /
AnnaBridge	143:86740a56073b	93	LPCOMP_IRQn = 19, /!< 19 LPCOMP /
AnnaBridge	143:86740a56073b	94	SWI0_IRQn = 20, /!< 20 SWI0 /
AnnaBridge	143:86740a56073b	95	SWI1_IRQn = 21, /!< 21 SWI1 /
AnnaBridge	143:86740a56073b	96	SWI2_IRQn = 22, /!< 22 SWI2 /
AnnaBridge	143:86740a56073b	97	SWI3_IRQn = 23, /!< 23 SWI3 /
AnnaBridge	143:86740a56073b	98	SWI4_IRQn = 24, /!< 24 SWI4 /
AnnaBridge	143:86740a56073b	99	SWI5_IRQn = 25 /!< 25 SWI5 /
AnnaBridge	143:86740a56073b	100	} IRQn_Type;
AnnaBridge	143:86740a56073b	101
AnnaBridge	143:86740a56073b	102
AnnaBridge	143:86740a56073b	103	/** @addtogroup Configuration_of_CMSIS
AnnaBridge	143:86740a56073b	104	* @{
AnnaBridge	143:86740a56073b	105	*/
AnnaBridge	143:86740a56073b	106
AnnaBridge	143:86740a56073b	107
AnnaBridge	143:86740a56073b	108	/* ================================================================================ */
AnnaBridge	143:86740a56073b	109	/* ================ Processor and Core Peripheral Section ================ */
AnnaBridge	143:86740a56073b	110	/* ================================================================================ */
AnnaBridge	143:86740a56073b	111
AnnaBridge	143:86740a56073b	112	/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
AnnaBridge	143:86740a56073b	113	#define __CM0_REV 0x0301 /!< Cortex-M0 Core Revision /
AnnaBridge	143:86740a56073b	114	#define __MPU_PRESENT 0 /!< MPU present or not /
AnnaBridge	143:86740a56073b	115	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
AnnaBridge	143:86740a56073b	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
AnnaBridge	143:86740a56073b	117	/** @} / / End of group Configuration_of_CMSIS */
AnnaBridge	143:86740a56073b	118
AnnaBridge	143:86740a56073b	119	#include "core_cm0.h" /!< Cortex-M0 processor and core peripherals /
AnnaBridge	143:86740a56073b	120	#include "system_nrf51.h" /!< nrf51 System /
AnnaBridge	143:86740a56073b	121
AnnaBridge	143:86740a56073b	122
AnnaBridge	143:86740a56073b	123	/* ================================================================================ */
AnnaBridge	143:86740a56073b	124	/* ================ Device Specific Peripheral Section ================ */
AnnaBridge	143:86740a56073b	125	/* ================================================================================ */
AnnaBridge	143:86740a56073b	126
AnnaBridge	143:86740a56073b	127
AnnaBridge	143:86740a56073b	128	/** @addtogroup Device_Peripheral_Registers
AnnaBridge	143:86740a56073b	129	* @{
AnnaBridge	143:86740a56073b	130	*/
AnnaBridge	143:86740a56073b	131
AnnaBridge	143:86740a56073b	132
AnnaBridge	143:86740a56073b	133	/* ------------------- Start of section using anonymous unions ------------------ */
AnnaBridge	143:86740a56073b	134	#if defined(__CC_ARM)
AnnaBridge	143:86740a56073b	135	#pragma push
AnnaBridge	143:86740a56073b	136	#pragma anon_unions
AnnaBridge	143:86740a56073b	137	#elif defined(__ICCARM__)
AnnaBridge	143:86740a56073b	138	#pragma language=extended
AnnaBridge	143:86740a56073b	139	#elif defined(__GNUC__)
AnnaBridge	143:86740a56073b	140	/* anonymous unions are enabled by default */
AnnaBridge	143:86740a56073b	141	#elif defined(__TMS470__)
AnnaBridge	143:86740a56073b	142	/* anonymous unions are enabled by default */
AnnaBridge	143:86740a56073b	143	#elif defined(__TASKING__)
AnnaBridge	143:86740a56073b	144	#pragma warning 586
AnnaBridge	143:86740a56073b	145	#else
AnnaBridge	143:86740a56073b	146	#warning Not supported compiler type
AnnaBridge	143:86740a56073b	147	#endif
AnnaBridge	143:86740a56073b	148
AnnaBridge	143:86740a56073b	149
AnnaBridge	143:86740a56073b	150	typedef struct {
AnnaBridge	143:86740a56073b	151	__IO uint32_t CPU0; /!< Configurable priority configuration register for CPU0. /
AnnaBridge	143:86740a56073b	152	__IO uint32_t SPIS1; /!< Configurable priority configuration register for SPIS1. /
AnnaBridge	143:86740a56073b	153	__IO uint32_t RADIO; /!< Configurable priority configuration register for RADIO. /
AnnaBridge	143:86740a56073b	154	__IO uint32_t ECB; /!< Configurable priority configuration register for ECB. /
AnnaBridge	143:86740a56073b	155	__IO uint32_t CCM; /!< Configurable priority configuration register for CCM. /
AnnaBridge	143:86740a56073b	156	__IO uint32_t AAR; /!< Configurable priority configuration register for AAR. /
AnnaBridge	143:86740a56073b	157	} AMLI_RAMPRI_Type;
AnnaBridge	143:86740a56073b	158
AnnaBridge	143:86740a56073b	159	typedef struct {
AnnaBridge	143:86740a56073b	160	__IO uint32_t SCK; /!< Pin select for SCK. /
AnnaBridge	143:86740a56073b	161	__IO uint32_t MOSI; /!< Pin select for MOSI. /
AnnaBridge	143:86740a56073b	162	__IO uint32_t MISO; /!< Pin select for MISO. /
AnnaBridge	143:86740a56073b	163	} SPIM_PSEL_Type;
AnnaBridge	143:86740a56073b	164
AnnaBridge	143:86740a56073b	165	typedef struct {
AnnaBridge	143:86740a56073b	166	__IO uint32_t PTR; /!< Data pointer. /
AnnaBridge	143:86740a56073b	167	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to receive. /
AnnaBridge	143:86740a56073b	168	__I uint32_t AMOUNT; /!< Number of bytes received in the last transaction. /
AnnaBridge	143:86740a56073b	169	} SPIM_RXD_Type;
AnnaBridge	143:86740a56073b	170
AnnaBridge	143:86740a56073b	171	typedef struct {
AnnaBridge	143:86740a56073b	172	__IO uint32_t PTR; /!< Data pointer. /
AnnaBridge	143:86740a56073b	173	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to send. /
AnnaBridge	143:86740a56073b	174	__I uint32_t AMOUNT; /!< Number of bytes sent in the last transaction. /
AnnaBridge	143:86740a56073b	175	} SPIM_TXD_Type;
AnnaBridge	143:86740a56073b	176
AnnaBridge	143:86740a56073b	177	typedef struct {
AnnaBridge	143:86740a56073b	178	__O uint32_t EN; /!< Enable channel group. /
AnnaBridge	143:86740a56073b	179	__O uint32_t DIS; /!< Disable channel group. /
AnnaBridge	143:86740a56073b	180	} PPI_TASKS_CHG_Type;
AnnaBridge	143:86740a56073b	181
AnnaBridge	143:86740a56073b	182	typedef struct {
AnnaBridge	143:86740a56073b	183	__IO uint32_t EEP; /!< Channel event end-point. /
AnnaBridge	143:86740a56073b	184	__IO uint32_t TEP; /!< Channel task end-point. /
AnnaBridge	143:86740a56073b	185	} PPI_CH_Type;
AnnaBridge	143:86740a56073b	186
AnnaBridge	143:86740a56073b	187
AnnaBridge	143:86740a56073b	188	/* ================================================================================ */
AnnaBridge	143:86740a56073b	189	/* ================ POWER ================ */
AnnaBridge	143:86740a56073b	190	/* ================================================================================ */
AnnaBridge	143:86740a56073b	191
AnnaBridge	143:86740a56073b	192
AnnaBridge	143:86740a56073b	193	/**
AnnaBridge	143:86740a56073b	194	* @brief Power Control. (POWER)
AnnaBridge	143:86740a56073b	195	*/
AnnaBridge	143:86740a56073b	196
AnnaBridge	143:86740a56073b	197	typedef struct { /!< POWER Structure /
AnnaBridge	143:86740a56073b	198	__I uint32_t RESERVED0[30];
AnnaBridge	143:86740a56073b	199	__O uint32_t TASKS_CONSTLAT; /!< Enable constant latency mode. /
AnnaBridge	143:86740a56073b	200	__O uint32_t TASKS_LOWPWR; /!< Enable low power mode (variable latency). /
AnnaBridge	143:86740a56073b	201	__I uint32_t RESERVED1[34];
AnnaBridge	143:86740a56073b	202	__IO uint32_t EVENTS_POFWARN; /!< Power failure warning. /
AnnaBridge	143:86740a56073b	203	__I uint32_t RESERVED2[126];
AnnaBridge	143:86740a56073b	204	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	205	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	206	__I uint32_t RESERVED3[61];
AnnaBridge	143:86740a56073b	207	__IO uint32_t RESETREAS; /!< Reset reason. /
AnnaBridge	143:86740a56073b	208	__I uint32_t RESERVED4[9];
AnnaBridge	143:86740a56073b	209	__I uint32_t RAMSTATUS; /!< Ram status register. /
AnnaBridge	143:86740a56073b	210	__I uint32_t RESERVED5[53];
AnnaBridge	143:86740a56073b	211	__O uint32_t SYSTEMOFF; /!< System off register. /
AnnaBridge	143:86740a56073b	212	__I uint32_t RESERVED6[3];
AnnaBridge	143:86740a56073b	213	__IO uint32_t POFCON; /!< Power failure configuration. /
AnnaBridge	143:86740a56073b	214	__I uint32_t RESERVED7[2];
AnnaBridge	143:86740a56073b	215	__IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
AnnaBridge	143:86740a56073b	216	register. */
AnnaBridge	143:86740a56073b	217	__I uint32_t RESERVED8;
AnnaBridge	143:86740a56073b	218	__IO uint32_t RAMON; /!< Ram on/off. /
AnnaBridge	143:86740a56073b	219	__I uint32_t RESERVED9[7];
AnnaBridge	143:86740a56073b	220	__IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
AnnaBridge	143:86740a56073b	221	is a retained register. */
AnnaBridge	143:86740a56073b	222	__I uint32_t RESERVED10[3];
AnnaBridge	143:86740a56073b	223	__IO uint32_t RAMONB; /!< Ram on/off. /
AnnaBridge	143:86740a56073b	224	__I uint32_t RESERVED11[8];
AnnaBridge	143:86740a56073b	225	__IO uint32_t DCDCEN; /!< DCDC converter enable configuration register. /
AnnaBridge	143:86740a56073b	226	__I uint32_t RESERVED12[291];
AnnaBridge	143:86740a56073b	227	__IO uint32_t DCDCFORCE; /!< DCDC power-up force register. /
AnnaBridge	143:86740a56073b	228	} NRF_POWER_Type;
AnnaBridge	143:86740a56073b	229
AnnaBridge	143:86740a56073b	230
AnnaBridge	143:86740a56073b	231	/* ================================================================================ */
AnnaBridge	143:86740a56073b	232	/* ================ CLOCK ================ */
AnnaBridge	143:86740a56073b	233	/* ================================================================================ */
AnnaBridge	143:86740a56073b	234
AnnaBridge	143:86740a56073b	235
AnnaBridge	143:86740a56073b	236	/**
AnnaBridge	143:86740a56073b	237	* @brief Clock control. (CLOCK)
AnnaBridge	143:86740a56073b	238	*/
AnnaBridge	143:86740a56073b	239
AnnaBridge	143:86740a56073b	240	typedef struct { /!< CLOCK Structure /
AnnaBridge	143:86740a56073b	241	__O uint32_t TASKS_HFCLKSTART; /!< Start HFCLK clock source. /
AnnaBridge	143:86740a56073b	242	__O uint32_t TASKS_HFCLKSTOP; /!< Stop HFCLK clock source. /
AnnaBridge	143:86740a56073b	243	__O uint32_t TASKS_LFCLKSTART; /!< Start LFCLK clock source. /
AnnaBridge	143:86740a56073b	244	__O uint32_t TASKS_LFCLKSTOP; /!< Stop LFCLK clock source. /
AnnaBridge	143:86740a56073b	245	__O uint32_t TASKS_CAL; /!< Start calibration of LFCLK RC oscillator. /
AnnaBridge	143:86740a56073b	246	__O uint32_t TASKS_CTSTART; /!< Start calibration timer. /
AnnaBridge	143:86740a56073b	247	__O uint32_t TASKS_CTSTOP; /!< Stop calibration timer. /
AnnaBridge	143:86740a56073b	248	__I uint32_t RESERVED0[57];
AnnaBridge	143:86740a56073b	249	__IO uint32_t EVENTS_HFCLKSTARTED; /!< HFCLK oscillator started. /
AnnaBridge	143:86740a56073b	250	__IO uint32_t EVENTS_LFCLKSTARTED; /!< LFCLK oscillator started. /
AnnaBridge	143:86740a56073b	251	__I uint32_t RESERVED1;
AnnaBridge	143:86740a56073b	252	__IO uint32_t EVENTS_DONE; /!< Calibration of LFCLK RC oscillator completed. /
AnnaBridge	143:86740a56073b	253	__IO uint32_t EVENTS_CTTO; /!< Calibration timer timeout. /
AnnaBridge	143:86740a56073b	254	__I uint32_t RESERVED2[124];
AnnaBridge	143:86740a56073b	255	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	256	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	257	__I uint32_t RESERVED3[63];
AnnaBridge	143:86740a56073b	258	__I uint32_t HFCLKRUN; /!< Task HFCLKSTART trigger status. /
AnnaBridge	143:86740a56073b	259	__I uint32_t HFCLKSTAT; /!< High frequency clock status. /
AnnaBridge	143:86740a56073b	260	__I uint32_t RESERVED4;
AnnaBridge	143:86740a56073b	261	__I uint32_t LFCLKRUN; /!< Task LFCLKSTART triggered status. /
AnnaBridge	143:86740a56073b	262	__I uint32_t LFCLKSTAT; /!< Low frequency clock status. /
AnnaBridge	143:86740a56073b	263	__I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
AnnaBridge	143:86740a56073b	264	triggered. */
AnnaBridge	143:86740a56073b	265	__I uint32_t RESERVED5[62];
AnnaBridge	143:86740a56073b	266	__IO uint32_t LFCLKSRC; /!< Clock source for the LFCLK clock. /
AnnaBridge	143:86740a56073b	267	__I uint32_t RESERVED6[7];
AnnaBridge	143:86740a56073b	268	__IO uint32_t CTIV; /!< Calibration timer interval. /
AnnaBridge	143:86740a56073b	269	__I uint32_t RESERVED7[5];
AnnaBridge	143:86740a56073b	270	__IO uint32_t XTALFREQ; /!< Crystal frequency. /
AnnaBridge	143:86740a56073b	271	} NRF_CLOCK_Type;
AnnaBridge	143:86740a56073b	272
AnnaBridge	143:86740a56073b	273
AnnaBridge	143:86740a56073b	274	/* ================================================================================ */
AnnaBridge	143:86740a56073b	275	/* ================ MPU ================ */
AnnaBridge	143:86740a56073b	276	/* ================================================================================ */
AnnaBridge	143:86740a56073b	277
AnnaBridge	143:86740a56073b	278
AnnaBridge	143:86740a56073b	279	/**
AnnaBridge	143:86740a56073b	280	* @brief Memory Protection Unit. (MPU)
AnnaBridge	143:86740a56073b	281	*/
AnnaBridge	143:86740a56073b	282
AnnaBridge	143:86740a56073b	283	typedef struct { /!< MPU Structure /
AnnaBridge	143:86740a56073b	284	__I uint32_t RESERVED0[330];
AnnaBridge	143:86740a56073b	285	__IO uint32_t PERR0; /!< Configuration of peripherals in mpu regions. /
AnnaBridge	143:86740a56073b	286	__IO uint32_t RLENR0; /!< Length of RAM region 0. /
AnnaBridge	143:86740a56073b	287	__I uint32_t RESERVED1[52];
AnnaBridge	143:86740a56073b	288	__IO uint32_t PROTENSET0; /!< Erase and write protection bit enable set register. /
AnnaBridge	143:86740a56073b	289	__IO uint32_t PROTENSET1; /!< Erase and write protection bit enable set register. /
AnnaBridge	143:86740a56073b	290	__IO uint32_t DISABLEINDEBUG; /!< Disable erase and write protection mechanism in debug mode. /
AnnaBridge	143:86740a56073b	291	__IO uint32_t PROTBLOCKSIZE; /!< Erase and write protection block size. /
AnnaBridge	143:86740a56073b	292	} NRF_MPU_Type;
AnnaBridge	143:86740a56073b	293
AnnaBridge	143:86740a56073b	294
AnnaBridge	143:86740a56073b	295	/* ================================================================================ */
AnnaBridge	143:86740a56073b	296	/* ================ AMLI ================ */
AnnaBridge	143:86740a56073b	297	/* ================================================================================ */
AnnaBridge	143:86740a56073b	298
AnnaBridge	143:86740a56073b	299
AnnaBridge	143:86740a56073b	300	/**
AnnaBridge	143:86740a56073b	301	* @brief AHB Multi-Layer Interface. (AMLI)
AnnaBridge	143:86740a56073b	302	*/
AnnaBridge	143:86740a56073b	303
AnnaBridge	143:86740a56073b	304	typedef struct { /!< AMLI Structure /
AnnaBridge	143:86740a56073b	305	__I uint32_t RESERVED0[896];
AnnaBridge	143:86740a56073b	306	AMLI_RAMPRI_Type RAMPRI; /!< RAM configurable priority configuration structure. /
AnnaBridge	143:86740a56073b	307	} NRF_AMLI_Type;
AnnaBridge	143:86740a56073b	308
AnnaBridge	143:86740a56073b	309
AnnaBridge	143:86740a56073b	310	/* ================================================================================ */
AnnaBridge	143:86740a56073b	311	/* ================ RADIO ================ */
AnnaBridge	143:86740a56073b	312	/* ================================================================================ */
AnnaBridge	143:86740a56073b	313
AnnaBridge	143:86740a56073b	314
AnnaBridge	143:86740a56073b	315	/**
AnnaBridge	143:86740a56073b	316	* @brief The radio. (RADIO)
AnnaBridge	143:86740a56073b	317	*/
AnnaBridge	143:86740a56073b	318
AnnaBridge	143:86740a56073b	319	typedef struct { /!< RADIO Structure /
AnnaBridge	143:86740a56073b	320	__O uint32_t TASKS_TXEN; /!< Enable radio in TX mode. /
AnnaBridge	143:86740a56073b	321	__O uint32_t TASKS_RXEN; /!< Enable radio in RX mode. /
AnnaBridge	143:86740a56073b	322	__O uint32_t TASKS_START; /!< Start radio. /
AnnaBridge	143:86740a56073b	323	__O uint32_t TASKS_STOP; /!< Stop radio. /
AnnaBridge	143:86740a56073b	324	__O uint32_t TASKS_DISABLE; /!< Disable radio. /
AnnaBridge	143:86740a56073b	325	__O uint32_t TASKS_RSSISTART; /!< Start the RSSI and take one sample of the receive signal strength. /
AnnaBridge	143:86740a56073b	326	__O uint32_t TASKS_RSSISTOP; /!< Stop the RSSI measurement. /
AnnaBridge	143:86740a56073b	327	__O uint32_t TASKS_BCSTART; /!< Start the bit counter. /
AnnaBridge	143:86740a56073b	328	__O uint32_t TASKS_BCSTOP; /!< Stop the bit counter. /
AnnaBridge	143:86740a56073b	329	__I uint32_t RESERVED0[55];
AnnaBridge	143:86740a56073b	330	__IO uint32_t EVENTS_READY; /!< Ready event. /
AnnaBridge	143:86740a56073b	331	__IO uint32_t EVENTS_ADDRESS; /!< Address event. /
AnnaBridge	143:86740a56073b	332	__IO uint32_t EVENTS_PAYLOAD; /!< Payload event. /
AnnaBridge	143:86740a56073b	333	__IO uint32_t EVENTS_END; /!< End event. /
AnnaBridge	143:86740a56073b	334	__IO uint32_t EVENTS_DISABLED; /!< Disable event. /
AnnaBridge	143:86740a56073b	335	__IO uint32_t EVENTS_DEVMATCH; /!< A device address match occurred on the last received packet. /
AnnaBridge	143:86740a56073b	336	__IO uint32_t EVENTS_DEVMISS; /!< No device address match occurred on the last received packet. /
AnnaBridge	143:86740a56073b	337	__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
AnnaBridge	143:86740a56073b	338	sample is ready for readout at the RSSISAMPLE register. */
AnnaBridge	143:86740a56073b	339	__I uint32_t RESERVED1[2];
AnnaBridge	143:86740a56073b	340	__IO uint32_t EVENTS_BCMATCH; /!< Bit counter reached bit count value specified in BCC register. /
AnnaBridge	143:86740a56073b	341	__I uint32_t RESERVED2[53];
AnnaBridge	143:86740a56073b	342	__IO uint32_t SHORTS; /!< Shortcuts for the radio. /
AnnaBridge	143:86740a56073b	343	__I uint32_t RESERVED3[64];
AnnaBridge	143:86740a56073b	344	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	345	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	346	__I uint32_t RESERVED4[61];
AnnaBridge	143:86740a56073b	347	__I uint32_t CRCSTATUS; /!< CRC status of received packet. /
AnnaBridge	143:86740a56073b	348	__I uint32_t RESERVED5;
AnnaBridge	143:86740a56073b	349	__I uint32_t RXMATCH; /!< Received address. /
AnnaBridge	143:86740a56073b	350	__I uint32_t RXCRC; /!< Received CRC. /
AnnaBridge	143:86740a56073b	351	__I uint32_t DAI; /!< Device address match index. /
AnnaBridge	143:86740a56073b	352	__I uint32_t RESERVED6[60];
AnnaBridge	143:86740a56073b	353	__IO uint32_t PACKETPTR; /!< Packet pointer. Decision point: START task. /
AnnaBridge	143:86740a56073b	354	__IO uint32_t FREQUENCY; /!< Frequency. /
AnnaBridge	143:86740a56073b	355	__IO uint32_t TXPOWER; /!< Output power. /
AnnaBridge	143:86740a56073b	356	__IO uint32_t MODE; /!< Data rate and modulation. /
AnnaBridge	143:86740a56073b	357	__IO uint32_t PCNF0; /!< Packet configuration 0. /
AnnaBridge	143:86740a56073b	358	__IO uint32_t PCNF1; /!< Packet configuration 1. /
AnnaBridge	143:86740a56073b	359	__IO uint32_t BASE0; /!< Radio base address 0. Decision point: START task. /
AnnaBridge	143:86740a56073b	360	__IO uint32_t BASE1; /!< Radio base address 1. Decision point: START task. /
AnnaBridge	143:86740a56073b	361	__IO uint32_t PREFIX0; /!< Prefixes bytes for logical addresses 0 to 3. /
AnnaBridge	143:86740a56073b	362	__IO uint32_t PREFIX1; /!< Prefixes bytes for logical addresses 4 to 7. /
AnnaBridge	143:86740a56073b	363	__IO uint32_t TXADDRESS; /!< Transmit address select. /
AnnaBridge	143:86740a56073b	364	__IO uint32_t RXADDRESSES; /!< Receive address select. /
AnnaBridge	143:86740a56073b	365	__IO uint32_t CRCCNF; /!< CRC configuration. /
AnnaBridge	143:86740a56073b	366	__IO uint32_t CRCPOLY; /!< CRC polynomial. /
AnnaBridge	143:86740a56073b	367	__IO uint32_t CRCINIT; /!< CRC initial value. /
AnnaBridge	143:86740a56073b	368	__IO uint32_t TEST; /!< Test features enable register. /
AnnaBridge	143:86740a56073b	369	__IO uint32_t TIFS; /!< Inter Frame Spacing in microseconds. /
AnnaBridge	143:86740a56073b	370	__I uint32_t RSSISAMPLE; /!< RSSI sample. /
AnnaBridge	143:86740a56073b	371	__I uint32_t RESERVED7;
AnnaBridge	143:86740a56073b	372	__I uint32_t STATE; /!< Current radio state. /
AnnaBridge	143:86740a56073b	373	__IO uint32_t DATAWHITEIV; /!< Data whitening initial value. /
AnnaBridge	143:86740a56073b	374	__I uint32_t RESERVED8[2];
AnnaBridge	143:86740a56073b	375	__IO uint32_t BCC; /!< Bit counter compare. /
AnnaBridge	143:86740a56073b	376	__I uint32_t RESERVED9[39];
AnnaBridge	143:86740a56073b	377	__IO uint32_t DAB[8]; /!< Device address base segment. /
AnnaBridge	143:86740a56073b	378	__IO uint32_t DAP[8]; /!< Device address prefix. /
AnnaBridge	143:86740a56073b	379	__IO uint32_t DACNF; /!< Device address match configuration. /
AnnaBridge	143:86740a56073b	380	__I uint32_t RESERVED10[56];
AnnaBridge	143:86740a56073b	381	__IO uint32_t OVERRIDE0; /!< Trim value override register 0. /
AnnaBridge	143:86740a56073b	382	__IO uint32_t OVERRIDE1; /!< Trim value override register 1. /
AnnaBridge	143:86740a56073b	383	__IO uint32_t OVERRIDE2; /!< Trim value override register 2. /
AnnaBridge	143:86740a56073b	384	__IO uint32_t OVERRIDE3; /!< Trim value override register 3. /
AnnaBridge	143:86740a56073b	385	__IO uint32_t OVERRIDE4; /!< Trim value override register 4. /
AnnaBridge	143:86740a56073b	386	__I uint32_t RESERVED11[561];
AnnaBridge	143:86740a56073b	387	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	388	} NRF_RADIO_Type;
AnnaBridge	143:86740a56073b	389
AnnaBridge	143:86740a56073b	390
AnnaBridge	143:86740a56073b	391	/* ================================================================================ */
AnnaBridge	143:86740a56073b	392	/* ================ UART ================ */
AnnaBridge	143:86740a56073b	393	/* ================================================================================ */
AnnaBridge	143:86740a56073b	394
AnnaBridge	143:86740a56073b	395
AnnaBridge	143:86740a56073b	396	/**
AnnaBridge	143:86740a56073b	397	* @brief Universal Asynchronous Receiver/Transmitter. (UART)
AnnaBridge	143:86740a56073b	398	*/
AnnaBridge	143:86740a56073b	399
AnnaBridge	143:86740a56073b	400	typedef struct { /!< UART Structure /
AnnaBridge	143:86740a56073b	401	__O uint32_t TASKS_STARTRX; /!< Start UART receiver. /
AnnaBridge	143:86740a56073b	402	__O uint32_t TASKS_STOPRX; /!< Stop UART receiver. /
AnnaBridge	143:86740a56073b	403	__O uint32_t TASKS_STARTTX; /!< Start UART transmitter. /
AnnaBridge	143:86740a56073b	404	__O uint32_t TASKS_STOPTX; /!< Stop UART transmitter. /
AnnaBridge	143:86740a56073b	405	__I uint32_t RESERVED0[3];
AnnaBridge	143:86740a56073b	406	__O uint32_t TASKS_SUSPEND; /!< Suspend UART. /
AnnaBridge	143:86740a56073b	407	__I uint32_t RESERVED1[56];
AnnaBridge	143:86740a56073b	408	__IO uint32_t EVENTS_CTS; /!< CTS activated. /
AnnaBridge	143:86740a56073b	409	__IO uint32_t EVENTS_NCTS; /!< CTS deactivated. /
AnnaBridge	143:86740a56073b	410	__IO uint32_t EVENTS_RXDRDY; /!< Data received in RXD. /
AnnaBridge	143:86740a56073b	411	__I uint32_t RESERVED2[4];
AnnaBridge	143:86740a56073b	412	__IO uint32_t EVENTS_TXDRDY; /!< Data sent from TXD. /
AnnaBridge	143:86740a56073b	413	__I uint32_t RESERVED3;
AnnaBridge	143:86740a56073b	414	__IO uint32_t EVENTS_ERROR; /!< Error detected. /
AnnaBridge	143:86740a56073b	415	__I uint32_t RESERVED4[7];
AnnaBridge	143:86740a56073b	416	__IO uint32_t EVENTS_RXTO; /!< Receiver timeout. /
AnnaBridge	143:86740a56073b	417	__I uint32_t RESERVED5[46];
AnnaBridge	143:86740a56073b	418	__IO uint32_t SHORTS; /!< Shortcuts for UART. /
AnnaBridge	143:86740a56073b	419	__I uint32_t RESERVED6[64];
AnnaBridge	143:86740a56073b	420	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	421	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	422	__I uint32_t RESERVED7[93];
AnnaBridge	143:86740a56073b	423	__IO uint32_t ERRORSRC; /!< Error source. Write error field to 1 to clear error. /
AnnaBridge	143:86740a56073b	424	__I uint32_t RESERVED8[31];
AnnaBridge	143:86740a56073b	425	__IO uint32_t ENABLE; /!< Enable UART and acquire IOs. /
AnnaBridge	143:86740a56073b	426	__I uint32_t RESERVED9;
AnnaBridge	143:86740a56073b	427	__IO uint32_t PSELRTS; /!< Pin select for RTS. /
AnnaBridge	143:86740a56073b	428	__IO uint32_t PSELTXD; /!< Pin select for TXD. /
AnnaBridge	143:86740a56073b	429	__IO uint32_t PSELCTS; /!< Pin select for CTS. /
AnnaBridge	143:86740a56073b	430	__IO uint32_t PSELRXD; /!< Pin select for RXD. /
AnnaBridge	143:86740a56073b	431	__I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
AnnaBridge	143:86740a56073b	432	Once read the character is consumed. If read when no character
AnnaBridge	143:86740a56073b	433	available, the UART will stop working. */
AnnaBridge	143:86740a56073b	434	__O uint32_t TXD; /!< TXD register. /
AnnaBridge	143:86740a56073b	435	__I uint32_t RESERVED10;
AnnaBridge	143:86740a56073b	436	__IO uint32_t BAUDRATE; /!< UART Baudrate. /
AnnaBridge	143:86740a56073b	437	__I uint32_t RESERVED11[17];
AnnaBridge	143:86740a56073b	438	__IO uint32_t CONFIG; /!< Configuration of parity and hardware flow control register. /
AnnaBridge	143:86740a56073b	439	__I uint32_t RESERVED12[675];
AnnaBridge	143:86740a56073b	440	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	441	} NRF_UART_Type;
AnnaBridge	143:86740a56073b	442
AnnaBridge	143:86740a56073b	443
AnnaBridge	143:86740a56073b	444	/* ================================================================================ */
AnnaBridge	143:86740a56073b	445	/* ================ SPI ================ */
AnnaBridge	143:86740a56073b	446	/* ================================================================================ */
AnnaBridge	143:86740a56073b	447
AnnaBridge	143:86740a56073b	448
AnnaBridge	143:86740a56073b	449	/**
AnnaBridge	143:86740a56073b	450	* @brief SPI master 0. (SPI)
AnnaBridge	143:86740a56073b	451	*/
AnnaBridge	143:86740a56073b	452
AnnaBridge	143:86740a56073b	453	typedef struct { /!< SPI Structure /
AnnaBridge	143:86740a56073b	454	__I uint32_t RESERVED0[66];
AnnaBridge	143:86740a56073b	455	__IO uint32_t EVENTS_READY; /!< TXD byte sent and RXD byte received. /
AnnaBridge	143:86740a56073b	456	__I uint32_t RESERVED1[126];
AnnaBridge	143:86740a56073b	457	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	458	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	459	__I uint32_t RESERVED2[125];
AnnaBridge	143:86740a56073b	460	__IO uint32_t ENABLE; /!< Enable SPI. /
AnnaBridge	143:86740a56073b	461	__I uint32_t RESERVED3;
AnnaBridge	143:86740a56073b	462	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
AnnaBridge	143:86740a56073b	463	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
AnnaBridge	143:86740a56073b	464	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
AnnaBridge	143:86740a56073b	465	__I uint32_t RESERVED4;
AnnaBridge	143:86740a56073b	466	__I uint32_t RXD; /!< RX data. /
AnnaBridge	143:86740a56073b	467	__IO uint32_t TXD; /!< TX data. /
AnnaBridge	143:86740a56073b	468	__I uint32_t RESERVED5;
AnnaBridge	143:86740a56073b	469	__IO uint32_t FREQUENCY; /!< SPI frequency /
AnnaBridge	143:86740a56073b	470	__I uint32_t RESERVED6[11];
AnnaBridge	143:86740a56073b	471	__IO uint32_t CONFIG; /!< Configuration register. /
AnnaBridge	143:86740a56073b	472	__I uint32_t RESERVED7[681];
AnnaBridge	143:86740a56073b	473	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	474	} NRF_SPI_Type;
AnnaBridge	143:86740a56073b	475
AnnaBridge	143:86740a56073b	476
AnnaBridge	143:86740a56073b	477	/* ================================================================================ */
AnnaBridge	143:86740a56073b	478	/* ================ TWI ================ */
AnnaBridge	143:86740a56073b	479	/* ================================================================================ */
AnnaBridge	143:86740a56073b	480
AnnaBridge	143:86740a56073b	481
AnnaBridge	143:86740a56073b	482	/**
AnnaBridge	143:86740a56073b	483	* @brief Two-wire interface master 0. (TWI)
AnnaBridge	143:86740a56073b	484	*/
AnnaBridge	143:86740a56073b	485
AnnaBridge	143:86740a56073b	486	typedef struct { /!< TWI Structure /
AnnaBridge	143:86740a56073b	487	__O uint32_t TASKS_STARTRX; /!< Start 2-Wire master receive sequence. /
AnnaBridge	143:86740a56073b	488	__I uint32_t RESERVED0;
AnnaBridge	143:86740a56073b	489	__O uint32_t TASKS_STARTTX; /!< Start 2-Wire master transmit sequence. /
AnnaBridge	143:86740a56073b	490	__I uint32_t RESERVED1[2];
AnnaBridge	143:86740a56073b	491	__O uint32_t TASKS_STOP; /!< Stop 2-Wire transaction. /
AnnaBridge	143:86740a56073b	492	__I uint32_t RESERVED2;
AnnaBridge	143:86740a56073b	493	__O uint32_t TASKS_SUSPEND; /!< Suspend 2-Wire transaction. /
AnnaBridge	143:86740a56073b	494	__O uint32_t TASKS_RESUME; /!< Resume 2-Wire transaction. /
AnnaBridge	143:86740a56073b	495	__I uint32_t RESERVED3[56];
AnnaBridge	143:86740a56073b	496	__IO uint32_t EVENTS_STOPPED; /!< Two-wire stopped. /
AnnaBridge	143:86740a56073b	497	__IO uint32_t EVENTS_RXDREADY; /!< Two-wire ready to deliver new RXD byte received. /
AnnaBridge	143:86740a56073b	498	__I uint32_t RESERVED4[4];
AnnaBridge	143:86740a56073b	499	__IO uint32_t EVENTS_TXDSENT; /!< Two-wire finished sending last TXD byte. /
AnnaBridge	143:86740a56073b	500	__I uint32_t RESERVED5;
AnnaBridge	143:86740a56073b	501	__IO uint32_t EVENTS_ERROR; /!< Two-wire error detected. /
AnnaBridge	143:86740a56073b	502	__I uint32_t RESERVED6[4];
AnnaBridge	143:86740a56073b	503	__IO uint32_t EVENTS_BB; /!< Two-wire byte boundary. /
AnnaBridge	143:86740a56073b	504	__I uint32_t RESERVED7[3];
AnnaBridge	143:86740a56073b	505	__IO uint32_t EVENTS_SUSPENDED; /!< Two-wire suspended. /
AnnaBridge	143:86740a56073b	506	__I uint32_t RESERVED8[45];
AnnaBridge	143:86740a56073b	507	__IO uint32_t SHORTS; /!< Shortcuts for TWI. /
AnnaBridge	143:86740a56073b	508	__I uint32_t RESERVED9[64];
AnnaBridge	143:86740a56073b	509	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	510	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	511	__I uint32_t RESERVED10[110];
AnnaBridge	143:86740a56073b	512	__IO uint32_t ERRORSRC; /!< Two-wire error source. Write error field to 1 to clear error. /
AnnaBridge	143:86740a56073b	513	__I uint32_t RESERVED11[14];
AnnaBridge	143:86740a56073b	514	__IO uint32_t ENABLE; /!< Enable two-wire master. /
AnnaBridge	143:86740a56073b	515	__I uint32_t RESERVED12;
AnnaBridge	143:86740a56073b	516	__IO uint32_t PSELSCL; /!< Pin select for SCL. /
AnnaBridge	143:86740a56073b	517	__IO uint32_t PSELSDA; /!< Pin select for SDA. /
AnnaBridge	143:86740a56073b	518	__I uint32_t RESERVED13[2];
AnnaBridge	143:86740a56073b	519	__I uint32_t RXD; /!< RX data register. /
AnnaBridge	143:86740a56073b	520	__IO uint32_t TXD; /!< TX data register. /
AnnaBridge	143:86740a56073b	521	__I uint32_t RESERVED14;
AnnaBridge	143:86740a56073b	522	__IO uint32_t FREQUENCY; /!< Two-wire frequency. /
AnnaBridge	143:86740a56073b	523	__I uint32_t RESERVED15[24];
AnnaBridge	143:86740a56073b	524	__IO uint32_t ADDRESS; /!< Address used in the two-wire transfer. /
AnnaBridge	143:86740a56073b	525	__I uint32_t RESERVED16[668];
AnnaBridge	143:86740a56073b	526	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	527	} NRF_TWI_Type;
AnnaBridge	143:86740a56073b	528
AnnaBridge	143:86740a56073b	529
AnnaBridge	143:86740a56073b	530	/* ================================================================================ */
AnnaBridge	143:86740a56073b	531	/* ================ SPIS ================ */
AnnaBridge	143:86740a56073b	532	/* ================================================================================ */
AnnaBridge	143:86740a56073b	533
AnnaBridge	143:86740a56073b	534
AnnaBridge	143:86740a56073b	535	/**
AnnaBridge	143:86740a56073b	536	* @brief SPI slave 1. (SPIS)
AnnaBridge	143:86740a56073b	537	*/
AnnaBridge	143:86740a56073b	538
AnnaBridge	143:86740a56073b	539	typedef struct { /!< SPIS Structure /
AnnaBridge	143:86740a56073b	540	__I uint32_t RESERVED0[9];
AnnaBridge	143:86740a56073b	541	__O uint32_t TASKS_ACQUIRE; /!< Acquire SPI semaphore. /
AnnaBridge	143:86740a56073b	542	__O uint32_t TASKS_RELEASE; /!< Release SPI semaphore. /
AnnaBridge	143:86740a56073b	543	__I uint32_t RESERVED1[54];
AnnaBridge	143:86740a56073b	544	__IO uint32_t EVENTS_END; /!< Granted transaction completed. /
AnnaBridge	143:86740a56073b	545	__I uint32_t RESERVED2[2];
AnnaBridge	143:86740a56073b	546	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached /
AnnaBridge	143:86740a56073b	547	__I uint32_t RESERVED3[5];
AnnaBridge	143:86740a56073b	548	__IO uint32_t EVENTS_ACQUIRED; /!< Semaphore acquired. /
AnnaBridge	143:86740a56073b	549	__I uint32_t RESERVED4[53];
AnnaBridge	143:86740a56073b	550	__IO uint32_t SHORTS; /!< Shortcuts for SPIS. /
AnnaBridge	143:86740a56073b	551	__I uint32_t RESERVED5[64];
AnnaBridge	143:86740a56073b	552	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	553	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	554	__I uint32_t RESERVED6[61];
AnnaBridge	143:86740a56073b	555	__I uint32_t SEMSTAT; /!< Semaphore status. /
AnnaBridge	143:86740a56073b	556	__I uint32_t RESERVED7[15];
AnnaBridge	143:86740a56073b	557	__IO uint32_t STATUS; /!< Status from last transaction. /
AnnaBridge	143:86740a56073b	558	__I uint32_t RESERVED8[47];
AnnaBridge	143:86740a56073b	559	__IO uint32_t ENABLE; /!< Enable SPIS. /
AnnaBridge	143:86740a56073b	560	__I uint32_t RESERVED9;
AnnaBridge	143:86740a56073b	561	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
AnnaBridge	143:86740a56073b	562	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
AnnaBridge	143:86740a56073b	563	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
AnnaBridge	143:86740a56073b	564	__IO uint32_t PSELCSN; /!< Pin select for CSN. /
AnnaBridge	143:86740a56073b	565	__I uint32_t RESERVED10[7];
AnnaBridge	143:86740a56073b	566	__IO uint32_t RXDPTR; /!< RX data pointer. /
AnnaBridge	143:86740a56073b	567	__IO uint32_t MAXRX; /!< Maximum number of bytes in the receive buffer. /
AnnaBridge	143:86740a56073b	568	__I uint32_t AMOUNTRX; /!< Number of bytes received in last granted transaction. /
AnnaBridge	143:86740a56073b	569	__I uint32_t RESERVED11;
AnnaBridge	143:86740a56073b	570	__IO uint32_t TXDPTR; /!< TX data pointer. /
AnnaBridge	143:86740a56073b	571	__IO uint32_t MAXTX; /!< Maximum number of bytes in the transmit buffer. /
AnnaBridge	143:86740a56073b	572	__I uint32_t AMOUNTTX; /!< Number of bytes transmitted in last granted transaction. /
AnnaBridge	143:86740a56073b	573	__I uint32_t RESERVED12;
AnnaBridge	143:86740a56073b	574	__IO uint32_t CONFIG; /!< Configuration register. /
AnnaBridge	143:86740a56073b	575	__I uint32_t RESERVED13;
AnnaBridge	143:86740a56073b	576	__IO uint32_t DEF; /!< Default character. /
AnnaBridge	143:86740a56073b	577	__I uint32_t RESERVED14[24];
AnnaBridge	143:86740a56073b	578	__IO uint32_t ORC; /!< Over-read character. /
AnnaBridge	143:86740a56073b	579	__I uint32_t RESERVED15[654];
AnnaBridge	143:86740a56073b	580	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	581	} NRF_SPIS_Type;
AnnaBridge	143:86740a56073b	582
AnnaBridge	143:86740a56073b	583
AnnaBridge	143:86740a56073b	584	/* ================================================================================ */
AnnaBridge	143:86740a56073b	585	/* ================ SPIM ================ */
AnnaBridge	143:86740a56073b	586	/* ================================================================================ */
AnnaBridge	143:86740a56073b	587
AnnaBridge	143:86740a56073b	588
AnnaBridge	143:86740a56073b	589	/**
AnnaBridge	143:86740a56073b	590	* @brief SPI master with easyDMA 1. (SPIM)
AnnaBridge	143:86740a56073b	591	*/
AnnaBridge	143:86740a56073b	592
AnnaBridge	143:86740a56073b	593	typedef struct { /!< SPIM Structure /
AnnaBridge	143:86740a56073b	594	__I uint32_t RESERVED0[4];
AnnaBridge	143:86740a56073b	595	__O uint32_t TASKS_START; /!< Start SPI transaction. /
AnnaBridge	143:86740a56073b	596	__O uint32_t TASKS_STOP; /!< Stop SPI transaction. /
AnnaBridge	143:86740a56073b	597	__I uint32_t RESERVED1;
AnnaBridge	143:86740a56073b	598	__O uint32_t TASKS_SUSPEND; /!< Suspend SPI transaction. /
AnnaBridge	143:86740a56073b	599	__O uint32_t TASKS_RESUME; /!< Resume SPI transaction. /
AnnaBridge	143:86740a56073b	600	__I uint32_t RESERVED2[56];
AnnaBridge	143:86740a56073b	601	__IO uint32_t EVENTS_STOPPED; /!< SPI transaction has stopped. /
AnnaBridge	143:86740a56073b	602	__I uint32_t RESERVED3[2];
AnnaBridge	143:86740a56073b	603	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached. /
AnnaBridge	143:86740a56073b	604	__I uint32_t RESERVED4[3];
AnnaBridge	143:86740a56073b	605	__IO uint32_t EVENTS_ENDTX; /!< End of TXD buffer reached. /
AnnaBridge	143:86740a56073b	606	__I uint32_t RESERVED5[10];
AnnaBridge	143:86740a56073b	607	__IO uint32_t EVENTS_STARTED; /!< Transaction started. /
AnnaBridge	143:86740a56073b	608	__I uint32_t RESERVED6[109];
AnnaBridge	143:86740a56073b	609	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	610	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	611	__I uint32_t RESERVED7[125];
AnnaBridge	143:86740a56073b	612	__IO uint32_t ENABLE; /!< Enable SPIM. /
AnnaBridge	143:86740a56073b	613	__I uint32_t RESERVED8;
AnnaBridge	143:86740a56073b	614	SPIM_PSEL_Type PSEL; /!< Pin select configuration. /
AnnaBridge	143:86740a56073b	615	__I uint32_t RESERVED9[4];
AnnaBridge	143:86740a56073b	616	__IO uint32_t FREQUENCY; /!< SPI frequency. /
AnnaBridge	143:86740a56073b	617	__I uint32_t RESERVED10[3];
AnnaBridge	143:86740a56073b	618	SPIM_RXD_Type RXD; /!< RXD EasyDMA configuration and status. /
AnnaBridge	143:86740a56073b	619	__I uint32_t RESERVED11;
AnnaBridge	143:86740a56073b	620	SPIM_TXD_Type TXD; /!< TXD EasyDMA configuration and status. /
AnnaBridge	143:86740a56073b	621	__I uint32_t RESERVED12;
AnnaBridge	143:86740a56073b	622	__IO uint32_t CONFIG; /!< Configuration register. /
AnnaBridge	143:86740a56073b	623	__I uint32_t RESERVED13[26];
AnnaBridge	143:86740a56073b	624	__IO uint32_t ORC; /!< Over-read character. /
AnnaBridge	143:86740a56073b	625	__I uint32_t RESERVED14[654];
AnnaBridge	143:86740a56073b	626	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	627	} NRF_SPIM_Type;
AnnaBridge	143:86740a56073b	628
AnnaBridge	143:86740a56073b	629
AnnaBridge	143:86740a56073b	630	/* ================================================================================ */
AnnaBridge	143:86740a56073b	631	/* ================ GPIOTE ================ */
AnnaBridge	143:86740a56073b	632	/* ================================================================================ */
AnnaBridge	143:86740a56073b	633
AnnaBridge	143:86740a56073b	634
AnnaBridge	143:86740a56073b	635	/**
AnnaBridge	143:86740a56073b	636	* @brief GPIO tasks and events. (GPIOTE)
AnnaBridge	143:86740a56073b	637	*/
AnnaBridge	143:86740a56073b	638
AnnaBridge	143:86740a56073b	639	typedef struct { /!< GPIOTE Structure /
AnnaBridge	143:86740a56073b	640	__O uint32_t TASKS_OUT[4]; /!< Tasks asssociated with GPIOTE channels. /
AnnaBridge	143:86740a56073b	641	__I uint32_t RESERVED0[60];
AnnaBridge	143:86740a56073b	642	__IO uint32_t EVENTS_IN[4]; /!< Tasks asssociated with GPIOTE channels. /
AnnaBridge	143:86740a56073b	643	__I uint32_t RESERVED1[27];
AnnaBridge	143:86740a56073b	644	__IO uint32_t EVENTS_PORT; /!< Event generated from multiple pins. /
AnnaBridge	143:86740a56073b	645	__I uint32_t RESERVED2[97];
AnnaBridge	143:86740a56073b	646	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	647	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	648	__I uint32_t RESERVED3[129];
AnnaBridge	143:86740a56073b	649	__IO uint32_t CONFIG[4]; /!< Channel configuration registers. /
AnnaBridge	143:86740a56073b	650	__I uint32_t RESERVED4[695];
AnnaBridge	143:86740a56073b	651	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	652	} NRF_GPIOTE_Type;
AnnaBridge	143:86740a56073b	653
AnnaBridge	143:86740a56073b	654
AnnaBridge	143:86740a56073b	655	/* ================================================================================ */
AnnaBridge	143:86740a56073b	656	/* ================ ADC ================ */
AnnaBridge	143:86740a56073b	657	/* ================================================================================ */
AnnaBridge	143:86740a56073b	658
AnnaBridge	143:86740a56073b	659
AnnaBridge	143:86740a56073b	660	/**
AnnaBridge	143:86740a56073b	661	* @brief Analog to digital converter. (ADC)
AnnaBridge	143:86740a56073b	662	*/
AnnaBridge	143:86740a56073b	663
AnnaBridge	143:86740a56073b	664	typedef struct { /!< ADC Structure /
AnnaBridge	143:86740a56073b	665	__O uint32_t TASKS_START; /!< Start an ADC conversion. /
AnnaBridge	143:86740a56073b	666	__O uint32_t TASKS_STOP; /!< Stop ADC. /
AnnaBridge	143:86740a56073b	667	__I uint32_t RESERVED0[62];
AnnaBridge	143:86740a56073b	668	__IO uint32_t EVENTS_END; /!< ADC conversion complete. /
AnnaBridge	143:86740a56073b	669	__I uint32_t RESERVED1[128];
AnnaBridge	143:86740a56073b	670	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	671	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	672	__I uint32_t RESERVED2[61];
AnnaBridge	143:86740a56073b	673	__I uint32_t BUSY; /!< ADC busy register. /
AnnaBridge	143:86740a56073b	674	__I uint32_t RESERVED3[63];
AnnaBridge	143:86740a56073b	675	__IO uint32_t ENABLE; /!< ADC enable. /
AnnaBridge	143:86740a56073b	676	__IO uint32_t CONFIG; /!< ADC configuration register. /
AnnaBridge	143:86740a56073b	677	__I uint32_t RESULT; /!< Result of ADC conversion. /
AnnaBridge	143:86740a56073b	678	__I uint32_t RESERVED4[700];
AnnaBridge	143:86740a56073b	679	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	680	} NRF_ADC_Type;
AnnaBridge	143:86740a56073b	681
AnnaBridge	143:86740a56073b	682
AnnaBridge	143:86740a56073b	683	/* ================================================================================ */
AnnaBridge	143:86740a56073b	684	/* ================ TIMER ================ */
AnnaBridge	143:86740a56073b	685	/* ================================================================================ */
AnnaBridge	143:86740a56073b	686
AnnaBridge	143:86740a56073b	687
AnnaBridge	143:86740a56073b	688	/**
AnnaBridge	143:86740a56073b	689	* @brief Timer 0. (TIMER)
AnnaBridge	143:86740a56073b	690	*/
AnnaBridge	143:86740a56073b	691
AnnaBridge	143:86740a56073b	692	typedef struct { /!< TIMER Structure /
AnnaBridge	143:86740a56073b	693	__O uint32_t TASKS_START; /!< Start Timer. /
AnnaBridge	143:86740a56073b	694	__O uint32_t TASKS_STOP; /!< Stop Timer. /
AnnaBridge	143:86740a56073b	695	__O uint32_t TASKS_COUNT; /!< Increment Timer (In counter mode). /
AnnaBridge	143:86740a56073b	696	__O uint32_t TASKS_CLEAR; /!< Clear timer. /
AnnaBridge	143:86740a56073b	697	__O uint32_t TASKS_SHUTDOWN; /!< Shutdown timer. /
AnnaBridge	143:86740a56073b	698	__I uint32_t RESERVED0[11];
AnnaBridge	143:86740a56073b	699	__O uint32_t TASKS_CAPTURE[4]; /!< Capture Timer value to CC[n] registers. /
AnnaBridge	143:86740a56073b	700	__I uint32_t RESERVED1[60];
AnnaBridge	143:86740a56073b	701	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
AnnaBridge	143:86740a56073b	702	__I uint32_t RESERVED2[44];
AnnaBridge	143:86740a56073b	703	__IO uint32_t SHORTS; /!< Shortcuts for Timer. /
AnnaBridge	143:86740a56073b	704	__I uint32_t RESERVED3[64];
AnnaBridge	143:86740a56073b	705	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	706	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	707	__I uint32_t RESERVED4[126];
AnnaBridge	143:86740a56073b	708	__IO uint32_t MODE; /!< Timer Mode selection. /
AnnaBridge	143:86740a56073b	709	__IO uint32_t BITMODE; /!< Sets timer behaviour. /
AnnaBridge	143:86740a56073b	710	__I uint32_t RESERVED5;
AnnaBridge	143:86740a56073b	711	__IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
AnnaBridge	143:86740a56073b	712	clock frequency is divided by 2^SCALE. */
AnnaBridge	143:86740a56073b	713	__I uint32_t RESERVED6[11];
AnnaBridge	143:86740a56073b	714	__IO uint32_t CC[4]; /!< Capture/compare registers. /
AnnaBridge	143:86740a56073b	715	__I uint32_t RESERVED7[683];
AnnaBridge	143:86740a56073b	716	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	717	} NRF_TIMER_Type;
AnnaBridge	143:86740a56073b	718
AnnaBridge	143:86740a56073b	719
AnnaBridge	143:86740a56073b	720	/* ================================================================================ */
AnnaBridge	143:86740a56073b	721	/* ================ RTC ================ */
AnnaBridge	143:86740a56073b	722	/* ================================================================================ */
AnnaBridge	143:86740a56073b	723
AnnaBridge	143:86740a56073b	724
AnnaBridge	143:86740a56073b	725	/**
AnnaBridge	143:86740a56073b	726	* @brief Real time counter 0. (RTC)
AnnaBridge	143:86740a56073b	727	*/
AnnaBridge	143:86740a56073b	728
AnnaBridge	143:86740a56073b	729	typedef struct { /!< RTC Structure /
AnnaBridge	143:86740a56073b	730	__O uint32_t TASKS_START; /!< Start RTC Counter. /
AnnaBridge	143:86740a56073b	731	__O uint32_t TASKS_STOP; /!< Stop RTC Counter. /
AnnaBridge	143:86740a56073b	732	__O uint32_t TASKS_CLEAR; /!< Clear RTC Counter. /
AnnaBridge	143:86740a56073b	733	__O uint32_t TASKS_TRIGOVRFLW; /!< Set COUNTER to 0xFFFFFFF0. /
AnnaBridge	143:86740a56073b	734	__I uint32_t RESERVED0[60];
AnnaBridge	143:86740a56073b	735	__IO uint32_t EVENTS_TICK; /!< Event on COUNTER increment. /
AnnaBridge	143:86740a56073b	736	__IO uint32_t EVENTS_OVRFLW; /!< Event on COUNTER overflow. /
AnnaBridge	143:86740a56073b	737	__I uint32_t RESERVED1[14];
AnnaBridge	143:86740a56073b	738	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
AnnaBridge	143:86740a56073b	739	__I uint32_t RESERVED2[109];
AnnaBridge	143:86740a56073b	740	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	741	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	742	__I uint32_t RESERVED3[13];
AnnaBridge	143:86740a56073b	743	__IO uint32_t EVTEN; /!< Configures event enable routing to PPI for each RTC event. /
AnnaBridge	143:86740a56073b	744	__IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
AnnaBridge	143:86740a56073b	745	the value of EVTEN. */
AnnaBridge	143:86740a56073b	746	__IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
AnnaBridge	143:86740a56073b	747	gives the value of EVTEN. */
AnnaBridge	143:86740a56073b	748	__I uint32_t RESERVED4[110];
AnnaBridge	143:86740a56073b	749	__I uint32_t COUNTER; /!< Current COUNTER value. /
AnnaBridge	143:86740a56073b	750	__IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
AnnaBridge	143:86740a56073b	751	Must be written when RTC is STOPed. */
AnnaBridge	143:86740a56073b	752	__I uint32_t RESERVED5[13];
AnnaBridge	143:86740a56073b	753	__IO uint32_t CC[4]; /!< Capture/compare registers. /
AnnaBridge	143:86740a56073b	754	__I uint32_t RESERVED6[683];
AnnaBridge	143:86740a56073b	755	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	756	} NRF_RTC_Type;
AnnaBridge	143:86740a56073b	757
AnnaBridge	143:86740a56073b	758
AnnaBridge	143:86740a56073b	759	/* ================================================================================ */
AnnaBridge	143:86740a56073b	760	/* ================ TEMP ================ */
AnnaBridge	143:86740a56073b	761	/* ================================================================================ */
AnnaBridge	143:86740a56073b	762
AnnaBridge	143:86740a56073b	763
AnnaBridge	143:86740a56073b	764	/**
AnnaBridge	143:86740a56073b	765	* @brief Temperature Sensor. (TEMP)
AnnaBridge	143:86740a56073b	766	*/
AnnaBridge	143:86740a56073b	767
AnnaBridge	143:86740a56073b	768	typedef struct { /!< TEMP Structure /
AnnaBridge	143:86740a56073b	769	__O uint32_t TASKS_START; /!< Start temperature measurement. /
AnnaBridge	143:86740a56073b	770	__O uint32_t TASKS_STOP; /!< Stop temperature measurement. /
AnnaBridge	143:86740a56073b	771	__I uint32_t RESERVED0[62];
AnnaBridge	143:86740a56073b	772	__IO uint32_t EVENTS_DATARDY; /!< Temperature measurement complete, data ready event. /
AnnaBridge	143:86740a56073b	773	__I uint32_t RESERVED1[128];
AnnaBridge	143:86740a56073b	774	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	775	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	776	__I uint32_t RESERVED2[127];
AnnaBridge	143:86740a56073b	777	__I int32_t TEMP; /!< Die temperature in degC, 2's complement format, 0.25 degC pecision. /
AnnaBridge	143:86740a56073b	778	__I uint32_t RESERVED3[700];
AnnaBridge	143:86740a56073b	779	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	780	} NRF_TEMP_Type;
AnnaBridge	143:86740a56073b	781
AnnaBridge	143:86740a56073b	782
AnnaBridge	143:86740a56073b	783	/* ================================================================================ */
AnnaBridge	143:86740a56073b	784	/* ================ RNG ================ */
AnnaBridge	143:86740a56073b	785	/* ================================================================================ */
AnnaBridge	143:86740a56073b	786
AnnaBridge	143:86740a56073b	787
AnnaBridge	143:86740a56073b	788	/**
AnnaBridge	143:86740a56073b	789	* @brief Random Number Generator. (RNG)
AnnaBridge	143:86740a56073b	790	*/
AnnaBridge	143:86740a56073b	791
AnnaBridge	143:86740a56073b	792	typedef struct { /!< RNG Structure /
AnnaBridge	143:86740a56073b	793	__O uint32_t TASKS_START; /!< Start the random number generator. /
AnnaBridge	143:86740a56073b	794	__O uint32_t TASKS_STOP; /!< Stop the random number generator. /
AnnaBridge	143:86740a56073b	795	__I uint32_t RESERVED0[62];
AnnaBridge	143:86740a56073b	796	__IO uint32_t EVENTS_VALRDY; /!< New random number generated and written to VALUE register. /
AnnaBridge	143:86740a56073b	797	__I uint32_t RESERVED1[63];
AnnaBridge	143:86740a56073b	798	__IO uint32_t SHORTS; /!< Shortcuts for the RNG. /
AnnaBridge	143:86740a56073b	799	__I uint32_t RESERVED2[64];
AnnaBridge	143:86740a56073b	800	__IO uint32_t INTENSET; /!< Interrupt enable set register /
AnnaBridge	143:86740a56073b	801	__IO uint32_t INTENCLR; /!< Interrupt enable clear register /
AnnaBridge	143:86740a56073b	802	__I uint32_t RESERVED3[126];
AnnaBridge	143:86740a56073b	803	__IO uint32_t CONFIG; /!< Configuration register. /
AnnaBridge	143:86740a56073b	804	__I uint32_t VALUE; /!< RNG random number. /
AnnaBridge	143:86740a56073b	805	__I uint32_t RESERVED4[700];
AnnaBridge	143:86740a56073b	806	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	807	} NRF_RNG_Type;
AnnaBridge	143:86740a56073b	808
AnnaBridge	143:86740a56073b	809
AnnaBridge	143:86740a56073b	810	/* ================================================================================ */
AnnaBridge	143:86740a56073b	811	/* ================ ECB ================ */
AnnaBridge	143:86740a56073b	812	/* ================================================================================ */
AnnaBridge	143:86740a56073b	813
AnnaBridge	143:86740a56073b	814
AnnaBridge	143:86740a56073b	815	/**
AnnaBridge	143:86740a56073b	816	* @brief AES ECB Mode Encryption. (ECB)
AnnaBridge	143:86740a56073b	817	*/
AnnaBridge	143:86740a56073b	818
AnnaBridge	143:86740a56073b	819	typedef struct { /!< ECB Structure /
AnnaBridge	143:86740a56073b	820	__O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
AnnaBridge	143:86740a56073b	821	will not initiate a new encryption and the ERRORECB event will
AnnaBridge	143:86740a56073b	822	be triggered. */
AnnaBridge	143:86740a56073b	823	__O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
AnnaBridge	143:86740a56073b	824	this will will trigger the ERRORECB event. */
AnnaBridge	143:86740a56073b	825	__I uint32_t RESERVED0[62];
AnnaBridge	143:86740a56073b	826	__IO uint32_t EVENTS_ENDECB; /!< ECB block encrypt complete. /
AnnaBridge	143:86740a56073b	827	__IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
AnnaBridge	143:86740a56073b	828	error. */
AnnaBridge	143:86740a56073b	829	__I uint32_t RESERVED1[127];
AnnaBridge	143:86740a56073b	830	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	831	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	832	__I uint32_t RESERVED2[126];
AnnaBridge	143:86740a56073b	833	__IO uint32_t ECBDATAPTR; /!< ECB block encrypt memory pointer. /
AnnaBridge	143:86740a56073b	834	__I uint32_t RESERVED3[701];
AnnaBridge	143:86740a56073b	835	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	836	} NRF_ECB_Type;
AnnaBridge	143:86740a56073b	837
AnnaBridge	143:86740a56073b	838
AnnaBridge	143:86740a56073b	839	/* ================================================================================ */
AnnaBridge	143:86740a56073b	840	/* ================ AAR ================ */
AnnaBridge	143:86740a56073b	841	/* ================================================================================ */
AnnaBridge	143:86740a56073b	842
AnnaBridge	143:86740a56073b	843
AnnaBridge	143:86740a56073b	844	/**
AnnaBridge	143:86740a56073b	845	* @brief Accelerated Address Resolver. (AAR)
AnnaBridge	143:86740a56073b	846	*/
AnnaBridge	143:86740a56073b	847
AnnaBridge	143:86740a56073b	848	typedef struct { /!< AAR Structure /
AnnaBridge	143:86740a56073b	849	__O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
AnnaBridge	143:86740a56073b	850	data structure. */
AnnaBridge	143:86740a56073b	851	__I uint32_t RESERVED0;
AnnaBridge	143:86740a56073b	852	__O uint32_t TASKS_STOP; /!< Stop resolving addresses. /
AnnaBridge	143:86740a56073b	853	__I uint32_t RESERVED1[61];
AnnaBridge	143:86740a56073b	854	__IO uint32_t EVENTS_END; /!< Address resolution procedure completed. /
AnnaBridge	143:86740a56073b	855	__IO uint32_t EVENTS_RESOLVED; /!< Address resolved. /
AnnaBridge	143:86740a56073b	856	__IO uint32_t EVENTS_NOTRESOLVED; /!< Address not resolved. /
AnnaBridge	143:86740a56073b	857	__I uint32_t RESERVED2[126];
AnnaBridge	143:86740a56073b	858	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	859	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	860	__I uint32_t RESERVED3[61];
AnnaBridge	143:86740a56073b	861	__I uint32_t STATUS; /!< Resolution status. /
AnnaBridge	143:86740a56073b	862	__I uint32_t RESERVED4[63];
AnnaBridge	143:86740a56073b	863	__IO uint32_t ENABLE; /!< Enable AAR. /
AnnaBridge	143:86740a56073b	864	__IO uint32_t NIRK; /!< Number of Identity root Keys in the IRK data structure. /
AnnaBridge	143:86740a56073b	865	__IO uint32_t IRKPTR; /!< Pointer to the IRK data structure. /
AnnaBridge	143:86740a56073b	866	__I uint32_t RESERVED5;
AnnaBridge	143:86740a56073b	867	__IO uint32_t ADDRPTR; /!< Pointer to the resolvable address (6 bytes). /
AnnaBridge	143:86740a56073b	868	__IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
AnnaBridge	143:86740a56073b	869	resolution. A minimum of 3 bytes must be reserved. */
AnnaBridge	143:86740a56073b	870	__I uint32_t RESERVED6[697];
AnnaBridge	143:86740a56073b	871	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	872	} NRF_AAR_Type;
AnnaBridge	143:86740a56073b	873
AnnaBridge	143:86740a56073b	874
AnnaBridge	143:86740a56073b	875	/* ================================================================================ */
AnnaBridge	143:86740a56073b	876	/* ================ CCM ================ */
AnnaBridge	143:86740a56073b	877	/* ================================================================================ */
AnnaBridge	143:86740a56073b	878
AnnaBridge	143:86740a56073b	879
AnnaBridge	143:86740a56073b	880	/**
AnnaBridge	143:86740a56073b	881	* @brief AES CCM Mode Encryption. (CCM)
AnnaBridge	143:86740a56073b	882	*/
AnnaBridge	143:86740a56073b	883
AnnaBridge	143:86740a56073b	884	typedef struct { /!< CCM Structure /
AnnaBridge	143:86740a56073b	885	__O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
AnnaBridge	143:86740a56073b	886	itself when completed. */
AnnaBridge	143:86740a56073b	887	__O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
AnnaBridge	143:86740a56073b	888	completed. */
AnnaBridge	143:86740a56073b	889	__O uint32_t TASKS_STOP; /!< Stop encrypt/decrypt. /
AnnaBridge	143:86740a56073b	890	__I uint32_t RESERVED0[61];
AnnaBridge	143:86740a56073b	891	__IO uint32_t EVENTS_ENDKSGEN; /!< Keystream generation completed. /
AnnaBridge	143:86740a56073b	892	__IO uint32_t EVENTS_ENDCRYPT; /!< Encrypt/decrypt completed. /
AnnaBridge	143:86740a56073b	893	__IO uint32_t EVENTS_ERROR; /!< Error happened. /
AnnaBridge	143:86740a56073b	894	__I uint32_t RESERVED1[61];
AnnaBridge	143:86740a56073b	895	__IO uint32_t SHORTS; /!< Shortcuts for the CCM. /
AnnaBridge	143:86740a56073b	896	__I uint32_t RESERVED2[64];
AnnaBridge	143:86740a56073b	897	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	898	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	899	__I uint32_t RESERVED3[61];
AnnaBridge	143:86740a56073b	900	__I uint32_t MICSTATUS; /!< CCM RX MIC check result. /
AnnaBridge	143:86740a56073b	901	__I uint32_t RESERVED4[63];
AnnaBridge	143:86740a56073b	902	__IO uint32_t ENABLE; /!< CCM enable. /
AnnaBridge	143:86740a56073b	903	__IO uint32_t MODE; /!< Operation mode. /
AnnaBridge	143:86740a56073b	904	__IO uint32_t CNFPTR; /!< Pointer to a data structure holding AES key and NONCE vector. /
AnnaBridge	143:86740a56073b	905	__IO uint32_t INPTR; /!< Pointer to the input packet. /
AnnaBridge	143:86740a56073b	906	__IO uint32_t OUTPTR; /!< Pointer to the output packet. /
AnnaBridge	143:86740a56073b	907	__IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
AnnaBridge	143:86740a56073b	908	resolution. A minimum of 43 bytes must be reserved. */
AnnaBridge	143:86740a56073b	909	__I uint32_t RESERVED5[697];
AnnaBridge	143:86740a56073b	910	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	911	} NRF_CCM_Type;
AnnaBridge	143:86740a56073b	912
AnnaBridge	143:86740a56073b	913
AnnaBridge	143:86740a56073b	914	/* ================================================================================ */
AnnaBridge	143:86740a56073b	915	/* ================ WDT ================ */
AnnaBridge	143:86740a56073b	916	/* ================================================================================ */
AnnaBridge	143:86740a56073b	917
AnnaBridge	143:86740a56073b	918
AnnaBridge	143:86740a56073b	919	/**
AnnaBridge	143:86740a56073b	920	* @brief Watchdog Timer. (WDT)
AnnaBridge	143:86740a56073b	921	*/
AnnaBridge	143:86740a56073b	922
AnnaBridge	143:86740a56073b	923	typedef struct { /!< WDT Structure /
AnnaBridge	143:86740a56073b	924	__O uint32_t TASKS_START; /!< Start the watchdog. /
AnnaBridge	143:86740a56073b	925	__I uint32_t RESERVED0[63];
AnnaBridge	143:86740a56073b	926	__IO uint32_t EVENTS_TIMEOUT; /!< Watchdog timeout. /
AnnaBridge	143:86740a56073b	927	__I uint32_t RESERVED1[128];
AnnaBridge	143:86740a56073b	928	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	929	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	930	__I uint32_t RESERVED2[61];
AnnaBridge	143:86740a56073b	931	__I uint32_t RUNSTATUS; /!< Watchdog running status. /
AnnaBridge	143:86740a56073b	932	__I uint32_t REQSTATUS; /!< Request status. /
AnnaBridge	143:86740a56073b	933	__I uint32_t RESERVED3[63];
AnnaBridge	143:86740a56073b	934	__IO uint32_t CRV; /!< Counter reload value in number of 32kiHz clock cycles. /
AnnaBridge	143:86740a56073b	935	__IO uint32_t RREN; /!< Reload request enable. /
AnnaBridge	143:86740a56073b	936	__IO uint32_t CONFIG; /!< Configuration register. /
AnnaBridge	143:86740a56073b	937	__I uint32_t RESERVED4[60];
AnnaBridge	143:86740a56073b	938	__O uint32_t RR[8]; /!< Reload requests registers. /
AnnaBridge	143:86740a56073b	939	__I uint32_t RESERVED5[631];
AnnaBridge	143:86740a56073b	940	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	941	} NRF_WDT_Type;
AnnaBridge	143:86740a56073b	942
AnnaBridge	143:86740a56073b	943
AnnaBridge	143:86740a56073b	944	/* ================================================================================ */
AnnaBridge	143:86740a56073b	945	/* ================ QDEC ================ */
AnnaBridge	143:86740a56073b	946	/* ================================================================================ */
AnnaBridge	143:86740a56073b	947
AnnaBridge	143:86740a56073b	948
AnnaBridge	143:86740a56073b	949	/**
AnnaBridge	143:86740a56073b	950	* @brief Rotary decoder. (QDEC)
AnnaBridge	143:86740a56073b	951	*/
AnnaBridge	143:86740a56073b	952
AnnaBridge	143:86740a56073b	953	typedef struct { /!< QDEC Structure /
AnnaBridge	143:86740a56073b	954	__O uint32_t TASKS_START; /!< Start the quadrature decoder. /
AnnaBridge	143:86740a56073b	955	__O uint32_t TASKS_STOP; /!< Stop the quadrature decoder. /
AnnaBridge	143:86740a56073b	956	__O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
AnnaBridge	143:86740a56073b	957	and clears the ACC registers. */
AnnaBridge	143:86740a56073b	958	__I uint32_t RESERVED0[61];
AnnaBridge	143:86740a56073b	959	__IO uint32_t EVENTS_SAMPLERDY; /!< A new sample is written to the sample register. /
AnnaBridge	143:86740a56073b	960	__IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
AnnaBridge	143:86740a56073b	961	ACC register different than zero. */
AnnaBridge	143:86740a56073b	962	__IO uint32_t EVENTS_ACCOF; /!< ACC or ACCDBL register overflow. /
AnnaBridge	143:86740a56073b	963	__I uint32_t RESERVED1[61];
AnnaBridge	143:86740a56073b	964	__IO uint32_t SHORTS; /!< Shortcuts for the QDEC. /
AnnaBridge	143:86740a56073b	965	__I uint32_t RESERVED2[64];
AnnaBridge	143:86740a56073b	966	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	967	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	968	__I uint32_t RESERVED3[125];
AnnaBridge	143:86740a56073b	969	__IO uint32_t ENABLE; /!< Enable the QDEC. /
AnnaBridge	143:86740a56073b	970	__IO uint32_t LEDPOL; /!< LED output pin polarity. /
AnnaBridge	143:86740a56073b	971	__IO uint32_t SAMPLEPER; /!< Sample period. /
AnnaBridge	143:86740a56073b	972	__I int32_t SAMPLE; /!< Motion sample value. /
AnnaBridge	143:86740a56073b	973	__IO uint32_t REPORTPER; /!< Number of samples to generate an EVENT_REPORTRDY. /
AnnaBridge	143:86740a56073b	974	__I int32_t ACC; /!< Accumulated valid transitions register. /
AnnaBridge	143:86740a56073b	975	__I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
AnnaBridge	143:86740a56073b	976	task. */
AnnaBridge	143:86740a56073b	977	__IO uint32_t PSELLED; /!< Pin select for LED output. /
AnnaBridge	143:86740a56073b	978	__IO uint32_t PSELA; /!< Pin select for phase A input. /
AnnaBridge	143:86740a56073b	979	__IO uint32_t PSELB; /!< Pin select for phase B input. /
AnnaBridge	143:86740a56073b	980	__IO uint32_t DBFEN; /!< Enable debouncer input filters. /
AnnaBridge	143:86740a56073b	981	__I uint32_t RESERVED4[5];
AnnaBridge	143:86740a56073b	982	__IO uint32_t LEDPRE; /!< Time LED is switched ON before the sample. /
AnnaBridge	143:86740a56073b	983	__I uint32_t ACCDBL; /!< Accumulated double (error) transitions register. /
AnnaBridge	143:86740a56073b	984	__I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
AnnaBridge	143:86740a56073b	985	task. */
AnnaBridge	143:86740a56073b	986	__I uint32_t RESERVED5[684];
AnnaBridge	143:86740a56073b	987	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	988	} NRF_QDEC_Type;
AnnaBridge	143:86740a56073b	989
AnnaBridge	143:86740a56073b	990
AnnaBridge	143:86740a56073b	991	/* ================================================================================ */
AnnaBridge	143:86740a56073b	992	/* ================ LPCOMP ================ */
AnnaBridge	143:86740a56073b	993	/* ================================================================================ */
AnnaBridge	143:86740a56073b	994
AnnaBridge	143:86740a56073b	995
AnnaBridge	143:86740a56073b	996	/**
AnnaBridge	143:86740a56073b	997	* @brief Low power comparator. (LPCOMP)
AnnaBridge	143:86740a56073b	998	*/
AnnaBridge	143:86740a56073b	999
AnnaBridge	143:86740a56073b	1000	typedef struct { /!< LPCOMP Structure /
AnnaBridge	143:86740a56073b	1001	__O uint32_t TASKS_START; /!< Start the comparator. /
AnnaBridge	143:86740a56073b	1002	__O uint32_t TASKS_STOP; /!< Stop the comparator. /
AnnaBridge	143:86740a56073b	1003	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value. /
AnnaBridge	143:86740a56073b	1004	__I uint32_t RESERVED0[61];
AnnaBridge	143:86740a56073b	1005	__IO uint32_t EVENTS_READY; /!< LPCOMP is ready and output is valid. /
AnnaBridge	143:86740a56073b	1006	__IO uint32_t EVENTS_DOWN; /!< Input voltage crossed the threshold going down. /
AnnaBridge	143:86740a56073b	1007	__IO uint32_t EVENTS_UP; /!< Input voltage crossed the threshold going up. /
AnnaBridge	143:86740a56073b	1008	__IO uint32_t EVENTS_CROSS; /!< Input voltage crossed the threshold in any direction. /
AnnaBridge	143:86740a56073b	1009	__I uint32_t RESERVED1[60];
AnnaBridge	143:86740a56073b	1010	__IO uint32_t SHORTS; /!< Shortcuts for the LPCOMP. /
AnnaBridge	143:86740a56073b	1011	__I uint32_t RESERVED2[64];
AnnaBridge	143:86740a56073b	1012	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	143:86740a56073b	1013	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	143:86740a56073b	1014	__I uint32_t RESERVED3[61];
AnnaBridge	143:86740a56073b	1015	__I uint32_t RESULT; /!< Result of last compare. /
AnnaBridge	143:86740a56073b	1016	__I uint32_t RESERVED4[63];
AnnaBridge	143:86740a56073b	1017	__IO uint32_t ENABLE; /!< Enable the LPCOMP. /
AnnaBridge	143:86740a56073b	1018	__IO uint32_t PSEL; /!< Input pin select. /
AnnaBridge	143:86740a56073b	1019	__IO uint32_t REFSEL; /!< Reference select. /
AnnaBridge	143:86740a56073b	1020	__IO uint32_t EXTREFSEL; /!< External reference select. /
AnnaBridge	143:86740a56073b	1021	__I uint32_t RESERVED5[4];
AnnaBridge	143:86740a56073b	1022	__IO uint32_t ANADETECT; /!< Analog detect configuration. /
AnnaBridge	143:86740a56073b	1023	__I uint32_t RESERVED6[694];
AnnaBridge	143:86740a56073b	1024	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	143:86740a56073b	1025	} NRF_LPCOMP_Type;
AnnaBridge	143:86740a56073b	1026
AnnaBridge	143:86740a56073b	1027
AnnaBridge	143:86740a56073b	1028	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1029	/* ================ SWI ================ */
AnnaBridge	143:86740a56073b	1030	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1031
AnnaBridge	143:86740a56073b	1032
AnnaBridge	143:86740a56073b	1033	/**
AnnaBridge	143:86740a56073b	1034	* @brief SW Interrupts. (SWI)
AnnaBridge	143:86740a56073b	1035	*/
AnnaBridge	143:86740a56073b	1036
AnnaBridge	143:86740a56073b	1037	typedef struct { /!< SWI Structure /
AnnaBridge	143:86740a56073b	1038	__I uint32_t UNUSED; /!< Unused. /
AnnaBridge	143:86740a56073b	1039	} NRF_SWI_Type;
AnnaBridge	143:86740a56073b	1040
AnnaBridge	143:86740a56073b	1041
AnnaBridge	143:86740a56073b	1042	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1043	/* ================ NVMC ================ */
AnnaBridge	143:86740a56073b	1044	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1045
AnnaBridge	143:86740a56073b	1046
AnnaBridge	143:86740a56073b	1047	/**
AnnaBridge	143:86740a56073b	1048	* @brief Non Volatile Memory Controller. (NVMC)
AnnaBridge	143:86740a56073b	1049	*/
AnnaBridge	143:86740a56073b	1050
AnnaBridge	143:86740a56073b	1051	typedef struct { /!< NVMC Structure /
AnnaBridge	143:86740a56073b	1052	__I uint32_t RESERVED0[256];
AnnaBridge	143:86740a56073b	1053	__I uint32_t READY; /!< Ready flag. /
AnnaBridge	143:86740a56073b	1054	__I uint32_t RESERVED1[64];
AnnaBridge	143:86740a56073b	1055	__IO uint32_t CONFIG; /!< Configuration register. /
AnnaBridge	143:86740a56073b	1056
AnnaBridge	143:86740a56073b	1057	union {
AnnaBridge	143:86740a56073b	1058	__IO uint32_t ERASEPCR1; /!< Register for erasing a non-protected non-volatile memory page. /
AnnaBridge	143:86740a56073b	1059	__IO uint32_t ERASEPAGE; /!< Register for erasing a non-protected non-volatile memory page. /
AnnaBridge	143:86740a56073b	1060	};
AnnaBridge	143:86740a56073b	1061	__IO uint32_t ERASEALL; /!< Register for erasing all non-volatile user memory. /
AnnaBridge	143:86740a56073b	1062	__IO uint32_t ERASEPCR0; /!< Register for erasing a protected non-volatile memory page. /
AnnaBridge	143:86740a56073b	1063	__IO uint32_t ERASEUICR; /!< Register for start erasing User Information Congfiguration Registers. /
AnnaBridge	143:86740a56073b	1064	} NRF_NVMC_Type;
AnnaBridge	143:86740a56073b	1065
AnnaBridge	143:86740a56073b	1066
AnnaBridge	143:86740a56073b	1067	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1068	/* ================ PPI ================ */
AnnaBridge	143:86740a56073b	1069	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1070
AnnaBridge	143:86740a56073b	1071
AnnaBridge	143:86740a56073b	1072	/**
AnnaBridge	143:86740a56073b	1073	* @brief PPI controller. (PPI)
AnnaBridge	143:86740a56073b	1074	*/
AnnaBridge	143:86740a56073b	1075
AnnaBridge	143:86740a56073b	1076	typedef struct { /!< PPI Structure /
AnnaBridge	143:86740a56073b	1077	PPI_TASKS_CHG_Type TASKS_CHG[4]; /!< Channel group tasks. /
AnnaBridge	143:86740a56073b	1078	__I uint32_t RESERVED0[312];
AnnaBridge	143:86740a56073b	1079	__IO uint32_t CHEN; /!< Channel enable. /
AnnaBridge	143:86740a56073b	1080	__IO uint32_t CHENSET; /!< Channel enable set. /
AnnaBridge	143:86740a56073b	1081	__IO uint32_t CHENCLR; /!< Channel enable clear. /
AnnaBridge	143:86740a56073b	1082	__I uint32_t RESERVED1;
AnnaBridge	143:86740a56073b	1083	PPI_CH_Type CH[16]; /!< PPI Channel. /
AnnaBridge	143:86740a56073b	1084	__I uint32_t RESERVED2[156];
AnnaBridge	143:86740a56073b	1085	__IO uint32_t CHG[4]; /!< Channel group configuration. /
AnnaBridge	143:86740a56073b	1086	} NRF_PPI_Type;
AnnaBridge	143:86740a56073b	1087
AnnaBridge	143:86740a56073b	1088
AnnaBridge	143:86740a56073b	1089	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1090	/* ================ FICR ================ */
AnnaBridge	143:86740a56073b	1091	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1092
AnnaBridge	143:86740a56073b	1093
AnnaBridge	143:86740a56073b	1094	/**
AnnaBridge	143:86740a56073b	1095	* @brief Factory Information Configuration. (FICR)
AnnaBridge	143:86740a56073b	1096	*/
AnnaBridge	143:86740a56073b	1097
AnnaBridge	143:86740a56073b	1098	typedef struct { /!< FICR Structure /
AnnaBridge	143:86740a56073b	1099	__I uint32_t RESERVED0[4];
AnnaBridge	143:86740a56073b	1100	__I uint32_t CODEPAGESIZE; /!< Code memory page size in bytes. /
AnnaBridge	143:86740a56073b	1101	__I uint32_t CODESIZE; /!< Code memory size in pages. /
AnnaBridge	143:86740a56073b	1102	__I uint32_t RESERVED1[4];
AnnaBridge	143:86740a56073b	1103	__I uint32_t CLENR0; /!< Length of code region 0 in bytes. /
AnnaBridge	143:86740a56073b	1104	__I uint32_t PPFC; /!< Pre-programmed factory code present. /
AnnaBridge	143:86740a56073b	1105	__I uint32_t RESERVED2;
AnnaBridge	143:86740a56073b	1106	__I uint32_t NUMRAMBLOCK; /!< Number of individualy controllable RAM blocks. /
AnnaBridge	143:86740a56073b	1107
AnnaBridge	143:86740a56073b	1108	union {
AnnaBridge	143:86740a56073b	1109	__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
AnnaBridge	143:86740a56073b	1110	kept for backward compatinility purposes. Use SIZERAMBLOCKS
AnnaBridge	143:86740a56073b	1111	instead. */
AnnaBridge	143:86740a56073b	1112	__I uint32_t SIZERAMBLOCKS; /!< Size of RAM blocks in bytes. /
AnnaBridge	143:86740a56073b	1113	};
AnnaBridge	143:86740a56073b	1114	__I uint32_t RESERVED3[5];
AnnaBridge	143:86740a56073b	1115	__I uint32_t CONFIGID; /!< Configuration identifier. /
AnnaBridge	143:86740a56073b	1116	__I uint32_t DEVICEID[2]; /!< Device identifier. /
AnnaBridge	143:86740a56073b	1117	__I uint32_t RESERVED4[6];
AnnaBridge	143:86740a56073b	1118	__I uint32_t ER[4]; /!< Encryption root. /
AnnaBridge	143:86740a56073b	1119	__I uint32_t IR[4]; /!< Identity root. /
AnnaBridge	143:86740a56073b	1120	__I uint32_t DEVICEADDRTYPE; /!< Device address type. /
AnnaBridge	143:86740a56073b	1121	__I uint32_t DEVICEADDR[2]; /!< Device address. /
AnnaBridge	143:86740a56073b	1122	__I uint32_t OVERRIDEEN; /!< Radio calibration override enable. /
AnnaBridge	143:86740a56073b	1123	__I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
AnnaBridge	143:86740a56073b	1124	mode. */
AnnaBridge	143:86740a56073b	1125	__I uint32_t RESERVED5[10];
AnnaBridge	143:86740a56073b	1126	__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
AnnaBridge	143:86740a56073b	1127	mode. */
AnnaBridge	143:86740a56073b	1128	} NRF_FICR_Type;
AnnaBridge	143:86740a56073b	1129
AnnaBridge	143:86740a56073b	1130
AnnaBridge	143:86740a56073b	1131	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1132	/* ================ UICR ================ */
AnnaBridge	143:86740a56073b	1133	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1134
AnnaBridge	143:86740a56073b	1135
AnnaBridge	143:86740a56073b	1136	/**
AnnaBridge	143:86740a56073b	1137	* @brief User Information Configuration. (UICR)
AnnaBridge	143:86740a56073b	1138	*/
AnnaBridge	143:86740a56073b	1139
AnnaBridge	143:86740a56073b	1140	typedef struct { /!< UICR Structure /
AnnaBridge	143:86740a56073b	1141	__IO uint32_t CLENR0; /!< Length of code region 0. /
AnnaBridge	143:86740a56073b	1142	__IO uint32_t RBPCONF; /!< Readback protection configuration. /
AnnaBridge	143:86740a56073b	1143	__IO uint32_t XTALFREQ; /!< Reset value for CLOCK XTALFREQ register. /
AnnaBridge	143:86740a56073b	1144	__I uint32_t RESERVED0;
AnnaBridge	143:86740a56073b	1145	__I uint32_t FWID; /!< Firmware ID. /
AnnaBridge	143:86740a56073b	1146
AnnaBridge	143:86740a56073b	1147	union {
AnnaBridge	143:86740a56073b	1148	__IO uint32_t NRFFW[15]; /!< Reserved for Nordic firmware design. /
AnnaBridge	143:86740a56073b	1149	__IO uint32_t BOOTLOADERADDR; /!< Bootloader start address. /
AnnaBridge	143:86740a56073b	1150	};
AnnaBridge	143:86740a56073b	1151	__IO uint32_t NRFHW[12]; /!< Reserved for Nordic hardware design. /
AnnaBridge	143:86740a56073b	1152	__IO uint32_t CUSTOMER[32]; /!< Reserved for customer. /
AnnaBridge	143:86740a56073b	1153	} NRF_UICR_Type;
AnnaBridge	143:86740a56073b	1154
AnnaBridge	143:86740a56073b	1155
AnnaBridge	143:86740a56073b	1156	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1157	/* ================ GPIO ================ */
AnnaBridge	143:86740a56073b	1158	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1159
AnnaBridge	143:86740a56073b	1160
AnnaBridge	143:86740a56073b	1161	/**
AnnaBridge	143:86740a56073b	1162	* @brief General purpose input and output. (GPIO)
AnnaBridge	143:86740a56073b	1163	*/
AnnaBridge	143:86740a56073b	1164
AnnaBridge	143:86740a56073b	1165	typedef struct { /!< GPIO Structure /
AnnaBridge	143:86740a56073b	1166	__I uint32_t RESERVED0[321];
AnnaBridge	143:86740a56073b	1167	__IO uint32_t OUT; /!< Write GPIO port. /
AnnaBridge	143:86740a56073b	1168	__IO uint32_t OUTSET; /!< Set individual bits in GPIO port. /
AnnaBridge	143:86740a56073b	1169	__IO uint32_t OUTCLR; /!< Clear individual bits in GPIO port. /
AnnaBridge	143:86740a56073b	1170	__I uint32_t IN; /!< Read GPIO port. /
AnnaBridge	143:86740a56073b	1171	__IO uint32_t DIR; /!< Direction of GPIO pins. /
AnnaBridge	143:86740a56073b	1172	__IO uint32_t DIRSET; /!< DIR set register. /
AnnaBridge	143:86740a56073b	1173	__IO uint32_t DIRCLR; /!< DIR clear register. /
AnnaBridge	143:86740a56073b	1174	__I uint32_t RESERVED1[120];
AnnaBridge	143:86740a56073b	1175	__IO uint32_t PIN_CNF[32]; /!< Configuration of GPIO pins. /
AnnaBridge	143:86740a56073b	1176	} NRF_GPIO_Type;
AnnaBridge	143:86740a56073b	1177
AnnaBridge	143:86740a56073b	1178
AnnaBridge	143:86740a56073b	1179	/* -------------------- End of section using anonymous unions ------------------- */
AnnaBridge	143:86740a56073b	1180	#if defined(__CC_ARM)
AnnaBridge	143:86740a56073b	1181	#pragma pop
AnnaBridge	143:86740a56073b	1182	#elif defined(__ICCARM__)
AnnaBridge	143:86740a56073b	1183	/* leave anonymous unions enabled */
AnnaBridge	143:86740a56073b	1184	#elif defined(__GNUC__)
AnnaBridge	143:86740a56073b	1185	/* anonymous unions are enabled by default */
AnnaBridge	143:86740a56073b	1186	#elif defined(__TMS470__)
AnnaBridge	143:86740a56073b	1187	/* anonymous unions are enabled by default */
AnnaBridge	143:86740a56073b	1188	#elif defined(__TASKING__)
AnnaBridge	143:86740a56073b	1189	#pragma warning restore
AnnaBridge	143:86740a56073b	1190	#else
AnnaBridge	143:86740a56073b	1191	#warning Not supported compiler type
AnnaBridge	143:86740a56073b	1192	#endif
AnnaBridge	143:86740a56073b	1193
AnnaBridge	143:86740a56073b	1194
AnnaBridge	143:86740a56073b	1195
AnnaBridge	143:86740a56073b	1196
AnnaBridge	143:86740a56073b	1197	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1198	/* ================ Peripheral memory map ================ */
AnnaBridge	143:86740a56073b	1199	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1200
AnnaBridge	143:86740a56073b	1201	#define NRF_POWER_BASE 0x40000000UL
AnnaBridge	143:86740a56073b	1202	#define NRF_CLOCK_BASE 0x40000000UL
AnnaBridge	143:86740a56073b	1203	#define NRF_MPU_BASE 0x40000000UL
AnnaBridge	143:86740a56073b	1204	#define NRF_AMLI_BASE 0x40000000UL
AnnaBridge	143:86740a56073b	1205	#define NRF_RADIO_BASE 0x40001000UL
AnnaBridge	143:86740a56073b	1206	#define NRF_UART0_BASE 0x40002000UL
AnnaBridge	143:86740a56073b	1207	#define NRF_SPI0_BASE 0x40003000UL
AnnaBridge	143:86740a56073b	1208	#define NRF_TWI0_BASE 0x40003000UL
AnnaBridge	143:86740a56073b	1209	#define NRF_SPI1_BASE 0x40004000UL
AnnaBridge	143:86740a56073b	1210	#define NRF_TWI1_BASE 0x40004000UL
AnnaBridge	143:86740a56073b	1211	#define NRF_SPIS1_BASE 0x40004000UL
AnnaBridge	143:86740a56073b	1212	#define NRF_SPIM1_BASE 0x40004000UL
AnnaBridge	143:86740a56073b	1213	#define NRF_GPIOTE_BASE 0x40006000UL
AnnaBridge	143:86740a56073b	1214	#define NRF_ADC_BASE 0x40007000UL
AnnaBridge	143:86740a56073b	1215	#define NRF_TIMER0_BASE 0x40008000UL
AnnaBridge	143:86740a56073b	1216	#define NRF_TIMER1_BASE 0x40009000UL
AnnaBridge	143:86740a56073b	1217	#define NRF_TIMER2_BASE 0x4000A000UL
AnnaBridge	143:86740a56073b	1218	#define NRF_RTC0_BASE 0x4000B000UL
AnnaBridge	143:86740a56073b	1219	#define NRF_TEMP_BASE 0x4000C000UL
AnnaBridge	143:86740a56073b	1220	#define NRF_RNG_BASE 0x4000D000UL
AnnaBridge	143:86740a56073b	1221	#define NRF_ECB_BASE 0x4000E000UL
AnnaBridge	143:86740a56073b	1222	#define NRF_AAR_BASE 0x4000F000UL
AnnaBridge	143:86740a56073b	1223	#define NRF_CCM_BASE 0x4000F000UL
AnnaBridge	143:86740a56073b	1224	#define NRF_WDT_BASE 0x40010000UL
AnnaBridge	143:86740a56073b	1225	#define NRF_RTC1_BASE 0x40011000UL
AnnaBridge	143:86740a56073b	1226	#define NRF_QDEC_BASE 0x40012000UL
AnnaBridge	143:86740a56073b	1227	#define NRF_LPCOMP_BASE 0x40013000UL
AnnaBridge	143:86740a56073b	1228	#define NRF_SWI_BASE 0x40014000UL
AnnaBridge	143:86740a56073b	1229	#define NRF_NVMC_BASE 0x4001E000UL
AnnaBridge	143:86740a56073b	1230	#define NRF_PPI_BASE 0x4001F000UL
AnnaBridge	143:86740a56073b	1231	#define NRF_FICR_BASE 0x10000000UL
AnnaBridge	143:86740a56073b	1232	#define NRF_UICR_BASE 0x10001000UL
AnnaBridge	143:86740a56073b	1233	#define NRF_GPIO_BASE 0x50000000UL
AnnaBridge	143:86740a56073b	1234
AnnaBridge	143:86740a56073b	1235
AnnaBridge	143:86740a56073b	1236	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1237	/* ================ Peripheral declaration ================ */
AnnaBridge	143:86740a56073b	1238	/* ================================================================================ */
AnnaBridge	143:86740a56073b	1239
AnnaBridge	143:86740a56073b	1240	#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
AnnaBridge	143:86740a56073b	1241	#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
AnnaBridge	143:86740a56073b	1242	#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
AnnaBridge	143:86740a56073b	1243	#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
AnnaBridge	143:86740a56073b	1244	#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
AnnaBridge	143:86740a56073b	1245	#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
AnnaBridge	143:86740a56073b	1246	#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
AnnaBridge	143:86740a56073b	1247	#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
AnnaBridge	143:86740a56073b	1248	#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
AnnaBridge	143:86740a56073b	1249	#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
AnnaBridge	143:86740a56073b	1250	#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
AnnaBridge	143:86740a56073b	1251	#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
AnnaBridge	143:86740a56073b	1252	#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
AnnaBridge	143:86740a56073b	1253	#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
AnnaBridge	143:86740a56073b	1254	#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
AnnaBridge	143:86740a56073b	1255	#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
AnnaBridge	143:86740a56073b	1256	#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
AnnaBridge	143:86740a56073b	1257	#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
AnnaBridge	143:86740a56073b	1258	#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
AnnaBridge	143:86740a56073b	1259	#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
AnnaBridge	143:86740a56073b	1260	#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
AnnaBridge	143:86740a56073b	1261	#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
AnnaBridge	143:86740a56073b	1262	#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
AnnaBridge	143:86740a56073b	1263	#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
AnnaBridge	143:86740a56073b	1264	#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
AnnaBridge	143:86740a56073b	1265	#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
AnnaBridge	143:86740a56073b	1266	#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
AnnaBridge	143:86740a56073b	1267	#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
AnnaBridge	143:86740a56073b	1268	#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
AnnaBridge	143:86740a56073b	1269	#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
AnnaBridge	143:86740a56073b	1270	#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
AnnaBridge	143:86740a56073b	1271	#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
AnnaBridge	143:86740a56073b	1272	#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
AnnaBridge	143:86740a56073b	1273
AnnaBridge	143:86740a56073b	1274
AnnaBridge	143:86740a56073b	1275	/** @} / / End of group Device_Peripheral_Registers */
AnnaBridge	143:86740a56073b	1276	/** @} / / End of group nrf51 */
AnnaBridge	143:86740a56073b	1277	/** @} / / End of group Nordic Semiconductor */
AnnaBridge	143:86740a56073b	1278
AnnaBridge	143:86740a56073b	1279	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	1280	}
AnnaBridge	143:86740a56073b	1281	#endif
AnnaBridge	143:86740a56073b	1282
AnnaBridge	143:86740a56073b	1283
AnnaBridge	143:86740a56073b	1284	#endif /* nrf51_H */
AnnaBridge	143:86740a56073b	1285