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TARGET_SDT32620B/TOOLCHAIN_IAR/spis_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-06-03 14:21:38 -0500 (Fri, 03 Jun 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 23194 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MXC_SPIS_REGS_H_
AnnaBridge 167:84c0a372a020 38 #define _MXC_SPIS_REGS_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 41 extern "C" {
AnnaBridge 167:84c0a372a020 42 #endif
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 #include <stdint.h>
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /*
AnnaBridge 167:84c0a372a020 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 167:84c0a372a020 48 */
AnnaBridge 167:84c0a372a020 49 #ifndef __IO
AnnaBridge 167:84c0a372a020 50 #define __IO volatile
AnnaBridge 167:84c0a372a020 51 #endif
AnnaBridge 167:84c0a372a020 52 #ifndef __I
AnnaBridge 167:84c0a372a020 53 #define __I volatile const
AnnaBridge 167:84c0a372a020 54 #endif
AnnaBridge 167:84c0a372a020 55 #ifndef __O
AnnaBridge 167:84c0a372a020 56 #define __O volatile
AnnaBridge 167:84c0a372a020 57 #endif
AnnaBridge 167:84c0a372a020 58 #ifndef __RO
AnnaBridge 167:84c0a372a020 59 #define __RO volatile const
AnnaBridge 167:84c0a372a020 60 #endif
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 /*
AnnaBridge 167:84c0a372a020 64 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 167:84c0a372a020 65 access to each register in module.
AnnaBridge 167:84c0a372a020 66 */
AnnaBridge 167:84c0a372a020 67
AnnaBridge 167:84c0a372a020 68 /* Offset Register Description
AnnaBridge 167:84c0a372a020 69 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 70 typedef struct {
AnnaBridge 167:84c0a372a020 71 __IO uint32_t gen_ctrl; /* 0x0000 SPI Slave General Control Register */
AnnaBridge 167:84c0a372a020 72 __IO uint32_t fifo_ctrl; /* 0x0004 SPI Slave FIFO Control Register */
AnnaBridge 167:84c0a372a020 73 __IO uint32_t fifo_stat; /* 0x0008 SPI Slave FIFO Status Register */
AnnaBridge 167:84c0a372a020 74 __IO uint32_t intfl; /* 0x000C SPI Slave Interrupt Flags */
AnnaBridge 167:84c0a372a020 75 __IO uint32_t inten; /* 0x0010 SPI Slave Interrupt Enable/Disable Settings */
AnnaBridge 167:84c0a372a020 76 } mxc_spis_regs_t;
AnnaBridge 167:84c0a372a020 77
AnnaBridge 167:84c0a372a020 78
AnnaBridge 167:84c0a372a020 79 /* Offset Register Description
AnnaBridge 167:84c0a372a020 80 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 81 typedef struct {
AnnaBridge 167:84c0a372a020 82 union { /* 0x0000-0x07FC SPI Slave FIFO TX Write Space */
AnnaBridge 167:84c0a372a020 83 __IO uint8_t tx_8[2048];
AnnaBridge 167:84c0a372a020 84 __IO uint16_t tx_16[1024];
AnnaBridge 167:84c0a372a020 85 __IO uint32_t tx_32[512];
AnnaBridge 167:84c0a372a020 86 };
AnnaBridge 167:84c0a372a020 87 union { /* 0x0800-0x0FFC SPI Slave FIFO RX Read Space */
AnnaBridge 167:84c0a372a020 88 __IO uint8_t rx_8[2048];
AnnaBridge 167:84c0a372a020 89 __IO uint16_t rx_16[1024];
AnnaBridge 167:84c0a372a020 90 __IO uint32_t rx_32[512];
AnnaBridge 167:84c0a372a020 91 };
AnnaBridge 167:84c0a372a020 92 } mxc_spis_fifo_regs_t;
AnnaBridge 167:84c0a372a020 93
AnnaBridge 167:84c0a372a020 94
AnnaBridge 167:84c0a372a020 95 /*
AnnaBridge 167:84c0a372a020 96 Register offsets for module SPIS.
AnnaBridge 167:84c0a372a020 97 */
AnnaBridge 167:84c0a372a020 98
AnnaBridge 167:84c0a372a020 99 #define MXC_R_SPIS_OFFS_GEN_CTRL ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 100 #define MXC_R_SPIS_OFFS_FIFO_CTRL ((uint32_t)0x00000004UL)
AnnaBridge 167:84c0a372a020 101 #define MXC_R_SPIS_OFFS_FIFO_STAT ((uint32_t)0x00000008UL)
AnnaBridge 167:84c0a372a020 102 #define MXC_R_SPIS_OFFS_INTFL ((uint32_t)0x0000000CUL)
AnnaBridge 167:84c0a372a020 103 #define MXC_R_SPIS_OFFS_INTEN ((uint32_t)0x00000010UL)
AnnaBridge 167:84c0a372a020 104 #define MXC_R_SPIS_FIFO_OFFS_TX ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 105 #define MXC_R_SPIS_FIFO_OFFS_RX ((uint32_t)0x00000800UL)
AnnaBridge 167:84c0a372a020 106
AnnaBridge 167:84c0a372a020 107
AnnaBridge 167:84c0a372a020 108 /*
AnnaBridge 167:84c0a372a020 109 Field positions and masks for module SPIS.
AnnaBridge 167:84c0a372a020 110 */
AnnaBridge 167:84c0a372a020 111
AnnaBridge 167:84c0a372a020 112 #define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS 0
AnnaBridge 167:84c0a372a020 113 #define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS))
AnnaBridge 167:84c0a372a020 114 #define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS 1
AnnaBridge 167:84c0a372a020 115 #define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS))
AnnaBridge 167:84c0a372a020 116 #define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS 2
AnnaBridge 167:84c0a372a020 117 #define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS))
AnnaBridge 167:84c0a372a020 118 #define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS 4
AnnaBridge 167:84c0a372a020 119 #define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS))
AnnaBridge 167:84c0a372a020 120 #define MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS 16
AnnaBridge 167:84c0a372a020 121 #define MXC_F_SPIS_GEN_CTRL_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS))
AnnaBridge 167:84c0a372a020 122 #define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS 20
AnnaBridge 167:84c0a372a020 123 #define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS))
AnnaBridge 167:84c0a372a020 124
AnnaBridge 167:84c0a372a020 125 #define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0
AnnaBridge 167:84c0a372a020 126 #define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
AnnaBridge 167:84c0a372a020 127 #define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS 8
AnnaBridge 167:84c0a372a020 128 #define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
AnnaBridge 167:84c0a372a020 129
AnnaBridge 167:84c0a372a020 130 #define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS 0
AnnaBridge 167:84c0a372a020 131 #define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS))
AnnaBridge 167:84c0a372a020 132 #define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS 8
AnnaBridge 167:84c0a372a020 133 #define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS))
AnnaBridge 167:84c0a372a020 134
AnnaBridge 167:84c0a372a020 135 #define MXC_F_SPIS_INTFL_TX_FIFO_AE_POS 0
AnnaBridge 167:84c0a372a020 136 #define MXC_F_SPIS_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_FIFO_AE_POS))
AnnaBridge 167:84c0a372a020 137 #define MXC_F_SPIS_INTFL_RX_FIFO_AF_POS 1
AnnaBridge 167:84c0a372a020 138 #define MXC_F_SPIS_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_FIFO_AF_POS))
AnnaBridge 167:84c0a372a020 139 #define MXC_F_SPIS_INTFL_TX_NO_DATA_POS 2
AnnaBridge 167:84c0a372a020 140 #define MXC_F_SPIS_INTFL_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_NO_DATA_POS))
AnnaBridge 167:84c0a372a020 141 #define MXC_F_SPIS_INTFL_RX_LOST_DATA_POS 3
AnnaBridge 167:84c0a372a020 142 #define MXC_F_SPIS_INTFL_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_LOST_DATA_POS))
AnnaBridge 167:84c0a372a020 143 #define MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS 4
AnnaBridge 167:84c0a372a020 144 #define MXC_F_SPIS_INTFL_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS))
AnnaBridge 167:84c0a372a020 145 #define MXC_F_SPIS_INTFL_SS_ASSERTED_POS 5
AnnaBridge 167:84c0a372a020 146 #define MXC_F_SPIS_INTFL_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_ASSERTED_POS))
AnnaBridge 167:84c0a372a020 147 #define MXC_F_SPIS_INTFL_SS_DEASSERTED_POS 6
AnnaBridge 167:84c0a372a020 148 #define MXC_F_SPIS_INTFL_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_DEASSERTED_POS))
AnnaBridge 167:84c0a372a020 149
AnnaBridge 167:84c0a372a020 150 #define MXC_F_SPIS_INTEN_TX_FIFO_AE_POS 0
AnnaBridge 167:84c0a372a020 151 #define MXC_F_SPIS_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_FIFO_AE_POS))
AnnaBridge 167:84c0a372a020 152 #define MXC_F_SPIS_INTEN_RX_FIFO_AF_POS 1
AnnaBridge 167:84c0a372a020 153 #define MXC_F_SPIS_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_FIFO_AF_POS))
AnnaBridge 167:84c0a372a020 154 #define MXC_F_SPIS_INTEN_TX_NO_DATA_POS 2
AnnaBridge 167:84c0a372a020 155 #define MXC_F_SPIS_INTEN_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_NO_DATA_POS))
AnnaBridge 167:84c0a372a020 156 #define MXC_F_SPIS_INTEN_RX_LOST_DATA_POS 3
AnnaBridge 167:84c0a372a020 157 #define MXC_F_SPIS_INTEN_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_LOST_DATA_POS))
AnnaBridge 167:84c0a372a020 158 #define MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS 4
AnnaBridge 167:84c0a372a020 159 #define MXC_F_SPIS_INTEN_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS))
AnnaBridge 167:84c0a372a020 160 #define MXC_F_SPIS_INTEN_SS_ASSERTED_POS 5
AnnaBridge 167:84c0a372a020 161 #define MXC_F_SPIS_INTEN_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_ASSERTED_POS))
AnnaBridge 167:84c0a372a020 162 #define MXC_F_SPIS_INTEN_SS_DEASSERTED_POS 6
AnnaBridge 167:84c0a372a020 163 #define MXC_F_SPIS_INTEN_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_DEASSERTED_POS))
AnnaBridge 167:84c0a372a020 164
AnnaBridge 167:84c0a372a020 165 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 166 }
AnnaBridge 167:84c0a372a020 167 #endif
AnnaBridge 167:84c0a372a020 168
AnnaBridge 167:84c0a372a020 169 #endif /* _MXC_SPIS_REGS_H_ */
AnnaBridge 167:84c0a372a020 170