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TARGET_SDT32620B/TOOLCHAIN_IAR/spim.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /**
AnnaBridge 167:84c0a372a020 2 * @file
AnnaBridge 167:84c0a372a020 3 * @brief Registers, Bit Masks and Bit Positions for the SPI Master module.
AnnaBridge 167:84c0a372a020 4 */
AnnaBridge 167:84c0a372a020 5 /* ****************************************************************************
AnnaBridge 167:84c0a372a020 6 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 7 *
AnnaBridge 167:84c0a372a020 8 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 9 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 10 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 12 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 13 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 14 *
AnnaBridge 167:84c0a372a020 15 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 16 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 17 *
AnnaBridge 167:84c0a372a020 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 21 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 22 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 24 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 27 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 28 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 29 *
AnnaBridge 167:84c0a372a020 30 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 31 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 32 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 33 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 34 * ownership rights.
AnnaBridge 167:84c0a372a020 35 *
AnnaBridge 167:84c0a372a020 36 * $Date: 2017-02-16 12:03:47 -0600 (Thu, 16 Feb 2017) $
AnnaBridge 167:84c0a372a020 37 * $Revision: 26464 $
AnnaBridge 167:84c0a372a020 38 *
AnnaBridge 167:84c0a372a020 39 **************************************************************************** */
AnnaBridge 167:84c0a372a020 40
AnnaBridge 167:84c0a372a020 41 /* **** Includes **** */
AnnaBridge 167:84c0a372a020 42 #include "mxc_config.h"
AnnaBridge 167:84c0a372a020 43 #include "mxc_sys.h"
AnnaBridge 167:84c0a372a020 44 #include "spim_regs.h"
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /* Define to prevent redundant inclusion */
AnnaBridge 167:84c0a372a020 47 #ifndef _SPIM_H_
AnnaBridge 167:84c0a372a020 48 #define _SPIM_H_
AnnaBridge 167:84c0a372a020 49
AnnaBridge 167:84c0a372a020 50 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 51 extern "C" {
AnnaBridge 167:84c0a372a020 52 #endif
AnnaBridge 167:84c0a372a020 53
AnnaBridge 167:84c0a372a020 54 /**
AnnaBridge 167:84c0a372a020 55 * @ingroup periphlibs
AnnaBridge 167:84c0a372a020 56 * @defgroup spim SPI Master
AnnaBridge 167:84c0a372a020 57 * @brief Serial Peripheral Interface Master (SPIM) API.
AnnaBridge 167:84c0a372a020 58 * @{
AnnaBridge 167:84c0a372a020 59 */
AnnaBridge 167:84c0a372a020 60
AnnaBridge 167:84c0a372a020 61 /* **** Definitions **** */
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 /**
AnnaBridge 167:84c0a372a020 64 * Enumeration type for selecting the active levels for the SPI Master Slave Select (SS) lines.
AnnaBridge 167:84c0a372a020 65 */
AnnaBridge 167:84c0a372a020 66 typedef enum {
AnnaBridge 167:84c0a372a020 67 SPIM_SSEL0_HIGH = (0x1 << 0), /**< Slave Select 0 High. */
AnnaBridge 167:84c0a372a020 68 SPIM_SSEL0_LOW = 0, /**< Slave Select 0 Low. */
AnnaBridge 167:84c0a372a020 69 SPIM_SSEL1_HIGH = (0x1 << 1), /**< Slave Select 1 High. */
AnnaBridge 167:84c0a372a020 70 SPIM_SSEL1_LOW = 0, /**< Slave Select 1 Low. */
AnnaBridge 167:84c0a372a020 71 SPIM_SSEL2_HIGH = (0x1 << 2), /**< Slave Select 2 High. */
AnnaBridge 167:84c0a372a020 72 SPIM_SSEL2_LOW = 0, /**< Slave Select 2 Low. */
AnnaBridge 167:84c0a372a020 73 SPIM_SSEL3_HIGH = (0x1 << 3), /**< Slave Select 3 High. */
AnnaBridge 167:84c0a372a020 74 SPIM_SSEL3_LOW = 0, /**< Slave Select 3 Low. */
AnnaBridge 167:84c0a372a020 75 SPIM_SSEL4_HIGH = (0x1 << 4), /**< Slave Select 4 High. */
AnnaBridge 167:84c0a372a020 76 SPIM_SSEL4_LOW = 0 /**< Slave Select 4 Low. */
AnnaBridge 167:84c0a372a020 77 }
AnnaBridge 167:84c0a372a020 78 spim_ssel_t;
AnnaBridge 167:84c0a372a020 79
AnnaBridge 167:84c0a372a020 80 /**
AnnaBridge 167:84c0a372a020 81 * Enumeration type for setting the number data lines to use for communication.
AnnaBridge 167:84c0a372a020 82 */
AnnaBridge 167:84c0a372a020 83 typedef enum {
AnnaBridge 167:84c0a372a020 84 SPIM_WIDTH_1 = 0, /**< 1 Data Line. */
AnnaBridge 167:84c0a372a020 85 SPIM_WIDTH_2 = 1, /**< 2 Data Lines (x2). */
AnnaBridge 167:84c0a372a020 86 SPIM_WIDTH_4 = 2 /**< 4 Data Lines (x4). */
AnnaBridge 167:84c0a372a020 87 } spim_width_t;
AnnaBridge 167:84c0a372a020 88
AnnaBridge 167:84c0a372a020 89 /**
AnnaBridge 167:84c0a372a020 90 * Structure type for configuring a SPIM port.
AnnaBridge 167:84c0a372a020 91 */
AnnaBridge 167:84c0a372a020 92 typedef struct {
AnnaBridge 167:84c0a372a020 93 uint8_t mode; /**< SPIM mode selection, 0 to 3. */
AnnaBridge 167:84c0a372a020 94 uint32_t ssel_pol; /**< Mask of active levels for the slave select signals, see #spim_ssel_t. */
AnnaBridge 167:84c0a372a020 95 uint32_t baud; /**< Baud rate in Hz. */
AnnaBridge 167:84c0a372a020 96 } spim_cfg_t;
AnnaBridge 167:84c0a372a020 97
AnnaBridge 167:84c0a372a020 98 /**
AnnaBridge 167:84c0a372a020 99 * Structure type representing a SPI Master Transaction request.
AnnaBridge 167:84c0a372a020 100 */
AnnaBridge 167:84c0a372a020 101 typedef struct spim_req spim_req_t;
AnnaBridge 167:84c0a372a020 102
AnnaBridge 167:84c0a372a020 103 /**
AnnaBridge 167:84c0a372a020 104 * @brief Callback function type used in asynchromous SPIM communications requests.
AnnaBridge 167:84c0a372a020 105 * @details The function declaration for the SPIM callback is:
AnnaBridge 167:84c0a372a020 106 * @code
AnnaBridge 167:84c0a372a020 107 * void callback(spim_req_t * req, int error_code);
AnnaBridge 167:84c0a372a020 108 * @endcode
AnnaBridge 167:84c0a372a020 109 * | | |
AnnaBridge 167:84c0a372a020 110 * | -----: | :----------------------------------------- |
AnnaBridge 167:84c0a372a020 111 * | \p req | Pointer to a #spim_req object representing the active SPIM active transaction. |
AnnaBridge 167:84c0a372a020 112 * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
AnnaBridge 167:84c0a372a020 113 * @addtogroup spim_async
AnnaBridge 167:84c0a372a020 114 */
AnnaBridge 167:84c0a372a020 115 typedef void (*spim_callback_fn)(spim_req_t * req, int error_code);
AnnaBridge 167:84c0a372a020 116
AnnaBridge 167:84c0a372a020 117 /**
AnnaBridge 167:84c0a372a020 118 * @brief Structure definition for an SPI Master Transaction request.
AnnaBridge 167:84c0a372a020 119 * @note When using this structure for an asynchronous operation, the
AnnaBridge 167:84c0a372a020 120 * structure must remain allocated until the callback is completed.
AnnaBridge 167:84c0a372a020 121 * @addtogroup spim_async
AnnaBridge 167:84c0a372a020 122 */
AnnaBridge 167:84c0a372a020 123 struct spim_req {
AnnaBridge 167:84c0a372a020 124 uint8_t ssel; /**< Number of the Slave Select to use. */
AnnaBridge 167:84c0a372a020 125 uint8_t deass; /**< Set to de-assert slave select at the completions of the transaction.*/
AnnaBridge 167:84c0a372a020 126 const uint8_t *tx_data; /**< Pointer to a buffer to transmit data from. */
AnnaBridge 167:84c0a372a020 127 uint8_t *rx_data; /**< Pointer to a buffer to store data received. */
AnnaBridge 167:84c0a372a020 128 spim_width_t width; /**< Number of data lines to use, see #spim_width_t. */
AnnaBridge 167:84c0a372a020 129 unsigned len; /**< Number of bytes to send from the \p tx_data buffer. */
AnnaBridge 167:84c0a372a020 130 unsigned read_num; /**< Number of bytes read and stored in \p rx_data buffer. */
AnnaBridge 167:84c0a372a020 131 unsigned write_num; /**< Number of bytes sent from the \p tx_data buffer, this will be filled by the driver after up to \p len bytes have been transmitted. */
AnnaBridge 167:84c0a372a020 132 spim_callback_fn callback; /**< Function pointer to a callback function if desired, NULL otherwise */
AnnaBridge 167:84c0a372a020 133 };
AnnaBridge 167:84c0a372a020 134
AnnaBridge 167:84c0a372a020 135 /* **** Globals **** */
AnnaBridge 167:84c0a372a020 136
AnnaBridge 167:84c0a372a020 137 /* **** Function Prototypes **** */
AnnaBridge 167:84c0a372a020 138
AnnaBridge 167:84c0a372a020 139 /**
AnnaBridge 167:84c0a372a020 140 * @brief Initialize the SPIM peripheral module.
AnnaBridge 167:84c0a372a020 141 *
AnnaBridge 167:84c0a372a020 142 * @param spim Pointer to the SPIM register structure.
AnnaBridge 167:84c0a372a020 143 * @param cfg Pointer to an SPIM configuration object.
AnnaBridge 167:84c0a372a020 144 * @param sys_cfg Pointer to a system configuration object to select the
AnnaBridge 167:84c0a372a020 145 * peripheral clock rate and assign the requested GPIO.
AnnaBridge 167:84c0a372a020 146 *
AnnaBridge 167:84c0a372a020 147 * @return #E_NO_ERROR if the SPIM port is initialized successfully, @ref MXC_Error_Codes
AnnaBridge 167:84c0a372a020 148 * "error" if unsuccessful.
AnnaBridge 167:84c0a372a020 149 */
AnnaBridge 167:84c0a372a020 150 int SPIM_Init(mxc_spim_regs_t *spim, const spim_cfg_t *cfg, const sys_cfg_spim_t *sys_cfg);
AnnaBridge 167:84c0a372a020 151
AnnaBridge 167:84c0a372a020 152 /**
AnnaBridge 167:84c0a372a020 153 * @brief Shutdown the SPIM peripheral module instance represented by the
AnnaBridge 167:84c0a372a020 154 * @p spim parameter.
AnnaBridge 167:84c0a372a020 155 *
AnnaBridge 167:84c0a372a020 156 * @param spim Pointer to the SPIM register structure.
AnnaBridge 167:84c0a372a020 157 *
AnnaBridge 167:84c0a372a020 158 * @return #E_NO_ERROR if the SPIM is shutdown successfully, @ref
AnnaBridge 167:84c0a372a020 159 * MXC_Error_Codes "error" if unsuccessful.
AnnaBridge 167:84c0a372a020 160 */
AnnaBridge 167:84c0a372a020 161 int SPIM_Shutdown(mxc_spim_regs_t *spim);
AnnaBridge 167:84c0a372a020 162
AnnaBridge 167:84c0a372a020 163 /**
AnnaBridge 167:84c0a372a020 164 * @brief Send Clock cycles on SCK without reading or writing.
AnnaBridge 167:84c0a372a020 165 *
AnnaBridge 167:84c0a372a020 166 * @param spim Pointer to the SPIM register structure.
AnnaBridge 167:84c0a372a020 167 * @param len Number of clock cycles to send.
AnnaBridge 167:84c0a372a020 168 * @param ssel Slave select number.
AnnaBridge 167:84c0a372a020 169 * @param deass De-assert slave select at the end of the transaction.
AnnaBridge 167:84c0a372a020 170 *
AnnaBridge 167:84c0a372a020 171 * @return Cycles transacted if everything is successful, @ref
AnnaBridge 167:84c0a372a020 172 * MXC_Error_Codes "error" if unsuccessful.
AnnaBridge 167:84c0a372a020 173 */
AnnaBridge 167:84c0a372a020 174 int SPIM_Clocks(mxc_spim_regs_t *spim, uint32_t len, uint8_t ssel, uint8_t deass);
AnnaBridge 167:84c0a372a020 175
AnnaBridge 167:84c0a372a020 176 /**
AnnaBridge 167:84c0a372a020 177 * @brief Read/write SPIM data. This function will block until the
AnnaBridge 167:84c0a372a020 178 * transaction is complete.
AnnaBridge 167:84c0a372a020 179 *
AnnaBridge 167:84c0a372a020 180 * @param spim Pointer to the SPIM register structure.
AnnaBridge 167:84c0a372a020 181 * @param req Request for a SPIM transaction.
AnnaBridge 167:84c0a372a020 182 * @note If a callback function is registered it will not be called when using a blocking function.
AnnaBridge 167:84c0a372a020 183 *
AnnaBridge 167:84c0a372a020 184 * @return Bytes transacted if everything is successful, error if
AnnaBridge 167:84c0a372a020 185 * unsuccessful.
AnnaBridge 167:84c0a372a020 186 */
AnnaBridge 167:84c0a372a020 187 int SPIM_Trans(mxc_spim_regs_t *spim, spim_req_t *req);
AnnaBridge 167:84c0a372a020 188 /**
AnnaBridge 167:84c0a372a020 189 * @defgroup spim_async SPIM Asynchrous Functions
AnnaBridge 167:84c0a372a020 190 * @{
AnnaBridge 167:84c0a372a020 191 */
AnnaBridge 167:84c0a372a020 192 /**
AnnaBridge 167:84c0a372a020 193 * @brief Asynchronously read/write SPIM data.
AnnaBridge 167:84c0a372a020 194 *
AnnaBridge 167:84c0a372a020 195 * @param spim Pointer to the SPIM register structure.
AnnaBridge 167:84c0a372a020 196 * @param req Request for a SPIM transaction.
AnnaBridge 167:84c0a372a020 197 * @note Request struct must remain allocated until callback.
AnnaBridge 167:84c0a372a020 198 *
AnnaBridge 167:84c0a372a020 199 * @return #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes
AnnaBridge 167:84c0a372a020 200 * "error" if unsuccessful.
AnnaBridge 167:84c0a372a020 201 */
AnnaBridge 167:84c0a372a020 202 int SPIM_TransAsync(mxc_spim_regs_t *spim, spim_req_t *req);
AnnaBridge 167:84c0a372a020 203
AnnaBridge 167:84c0a372a020 204 /**
AnnaBridge 167:84c0a372a020 205 * @brief Abort asynchronous request.
AnnaBridge 167:84c0a372a020 206 *
AnnaBridge 167:84c0a372a020 207 * @param req Pointer to a request structure for a SPIM transaction.
AnnaBridge 167:84c0a372a020 208 *
AnnaBridge 167:84c0a372a020 209 * @return #E_NO_ERROR if request aborted, , @ref MXC_Error_Codes "error" if
AnnaBridge 167:84c0a372a020 210 * unsuccessful.
AnnaBridge 167:84c0a372a020 211 */
AnnaBridge 167:84c0a372a020 212 int SPIM_AbortAsync(spim_req_t *req);
AnnaBridge 167:84c0a372a020 213
AnnaBridge 167:84c0a372a020 214 /**
AnnaBridge 167:84c0a372a020 215 * @brief SPIM interrupt handler.
AnnaBridge 167:84c0a372a020 216 * @details This function should be called by the application from the
AnnaBridge 167:84c0a372a020 217 * interrupt handler if SPIM interrupts are enabled. Alternately,
AnnaBridge 167:84c0a372a020 218 * this function can be periodically polled by the application if
AnnaBridge 167:84c0a372a020 219 * SPIM interrupts are disabled.
AnnaBridge 167:84c0a372a020 220 *
AnnaBridge 167:84c0a372a020 221 * @param spim Base address of the SPIM module.
AnnaBridge 167:84c0a372a020 222 */
AnnaBridge 167:84c0a372a020 223 void SPIM_Handler(mxc_spim_regs_t *spim);
AnnaBridge 167:84c0a372a020 224
AnnaBridge 167:84c0a372a020 225 /**
AnnaBridge 167:84c0a372a020 226 * @brief Check the SPIM to see if it's busy.
AnnaBridge 167:84c0a372a020 227 *
AnnaBridge 167:84c0a372a020 228 * @param spim Pointer to the SPIM register structure.
AnnaBridge 167:84c0a372a020 229 *
AnnaBridge 167:84c0a372a020 230 * @retval #E_NO_ERROR if idle.
AnnaBridge 167:84c0a372a020 231 * @retval #E_BUSY if in use.
AnnaBridge 167:84c0a372a020 232 */
AnnaBridge 167:84c0a372a020 233 int SPIM_Busy(mxc_spim_regs_t *spim);
AnnaBridge 167:84c0a372a020 234 /**@} end of spim_async define group */
AnnaBridge 167:84c0a372a020 235
AnnaBridge 167:84c0a372a020 236 /**
AnnaBridge 167:84c0a372a020 237 * @brief Attempts to prepare the SPIM for Low Power Sleep Modes.
AnnaBridge 167:84c0a372a020 238 * @details Checks for any ongoing transactions. Disables interrupts if the
AnnaBridge 167:84c0a372a020 239 * SPIM is idle.
AnnaBridge 167:84c0a372a020 240 *
AnnaBridge 167:84c0a372a020 241 * @param spim The spim
AnnaBridge 167:84c0a372a020 242 *
AnnaBridge 167:84c0a372a020 243 * @return #E_NO_ERROR if ready to sleep.
AnnaBridge 167:84c0a372a020 244 * @return #E_BUSY if not able to sleep at this time.
AnnaBridge 167:84c0a372a020 245 */
AnnaBridge 167:84c0a372a020 246 int SPIM_PrepForSleep(mxc_spim_regs_t *spim);
AnnaBridge 167:84c0a372a020 247
AnnaBridge 167:84c0a372a020 248 /**
AnnaBridge 167:84c0a372a020 249 * @brief Enables the SPIM without overwriting the existing configuration.
AnnaBridge 167:84c0a372a020 250 *
AnnaBridge 167:84c0a372a020 251 * @param spim Pointer to the SPIM register structure.
AnnaBridge 167:84c0a372a020 252 */
AnnaBridge 167:84c0a372a020 253 __STATIC_INLINE void SPIM_Enable(mxc_spim_regs_t *spim)
AnnaBridge 167:84c0a372a020 254 {
AnnaBridge 167:84c0a372a020 255 spim->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN |
AnnaBridge 167:84c0a372a020 256 MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN);
AnnaBridge 167:84c0a372a020 257 }
AnnaBridge 167:84c0a372a020 258
AnnaBridge 167:84c0a372a020 259 /**
AnnaBridge 167:84c0a372a020 260 * @brief Drains/empties the data in the RX FIFO.
AnnaBridge 167:84c0a372a020 261 *
AnnaBridge 167:84c0a372a020 262 * @param spim Pointer to the SPIM register structure.
AnnaBridge 167:84c0a372a020 263 */
AnnaBridge 167:84c0a372a020 264 __STATIC_INLINE void SPIM_DrainRX(mxc_spim_regs_t *spim)
AnnaBridge 167:84c0a372a020 265 {
AnnaBridge 167:84c0a372a020 266 uint32_t ctrl_save = spim->gen_ctrl;
AnnaBridge 167:84c0a372a020 267 spim->gen_ctrl = (ctrl_save & ~MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN);
AnnaBridge 167:84c0a372a020 268 spim->gen_ctrl = ctrl_save;
AnnaBridge 167:84c0a372a020 269 }
AnnaBridge 167:84c0a372a020 270
AnnaBridge 167:84c0a372a020 271 /**
AnnaBridge 167:84c0a372a020 272 * @brief Drains/empties the data in the TX FIFO.
AnnaBridge 167:84c0a372a020 273 *
AnnaBridge 167:84c0a372a020 274 * @param spim Pointer to the SPIM register structure.
AnnaBridge 167:84c0a372a020 275 */
AnnaBridge 167:84c0a372a020 276 __STATIC_INLINE void SPIM_DrainTX(mxc_spim_regs_t *spim)
AnnaBridge 167:84c0a372a020 277 {
AnnaBridge 167:84c0a372a020 278 uint32_t ctrl_save = spim->gen_ctrl;
AnnaBridge 167:84c0a372a020 279 spim->gen_ctrl = (ctrl_save & ~MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN);
AnnaBridge 167:84c0a372a020 280 spim->gen_ctrl = ctrl_save;
AnnaBridge 167:84c0a372a020 281 }
AnnaBridge 167:84c0a372a020 282
AnnaBridge 167:84c0a372a020 283 /**
AnnaBridge 167:84c0a372a020 284 * @brief Returns the number of bytes free in the TX FIFO.
AnnaBridge 167:84c0a372a020 285 *
AnnaBridge 167:84c0a372a020 286 * @param spim Pointer to the SPIM register structure.
AnnaBridge 167:84c0a372a020 287 *
AnnaBridge 167:84c0a372a020 288 * @return Number of bytes free in Transmit FIFO.
AnnaBridge 167:84c0a372a020 289 */
AnnaBridge 167:84c0a372a020 290 __STATIC_INLINE unsigned SPIM_NumWriteAvail(mxc_spim_regs_t *spim)
AnnaBridge 167:84c0a372a020 291 {
AnnaBridge 167:84c0a372a020 292 return (MXC_CFG_SPIM_FIFO_DEPTH - ((spim->fifo_ctrl &
AnnaBridge 167:84c0a372a020 293 MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED) >> MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS));
AnnaBridge 167:84c0a372a020 294 }
AnnaBridge 167:84c0a372a020 295
AnnaBridge 167:84c0a372a020 296 /**
AnnaBridge 167:84c0a372a020 297 * @brief Returns the number of bytes available to read in the RX FIFO.
AnnaBridge 167:84c0a372a020 298 *
AnnaBridge 167:84c0a372a020 299 * @param spim Pointer to the SPIM register structure.
AnnaBridge 167:84c0a372a020 300 *
AnnaBridge 167:84c0a372a020 301 * @return Number of bytes in RX FIFO.
AnnaBridge 167:84c0a372a020 302 */
AnnaBridge 167:84c0a372a020 303 __STATIC_INLINE unsigned SPIM_NumReadAvail(mxc_spim_regs_t *spim)
AnnaBridge 167:84c0a372a020 304 {
AnnaBridge 167:84c0a372a020 305 return ((spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >>
AnnaBridge 167:84c0a372a020 306 MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS);
AnnaBridge 167:84c0a372a020 307 }
AnnaBridge 167:84c0a372a020 308
AnnaBridge 167:84c0a372a020 309 /**
AnnaBridge 167:84c0a372a020 310 * @brief Clear the SPIM interrupt flags.
AnnaBridge 167:84c0a372a020 311 *
AnnaBridge 167:84c0a372a020 312 * @param spim Pointer to the SPIM register structure.
AnnaBridge 167:84c0a372a020 313 * @param mask Mask of the SPIM interrupt flags to clear, see @ref
AnnaBridge 167:84c0a372a020 314 * SPIM_INTFL_Register Register for the SPIM interrupt flag
AnnaBridge 167:84c0a372a020 315 * bit masks.
AnnaBridge 167:84c0a372a020 316 */
AnnaBridge 167:84c0a372a020 317 __STATIC_INLINE void SPIM_ClearFlags(mxc_spim_regs_t *spim, uint32_t mask)
AnnaBridge 167:84c0a372a020 318 {
AnnaBridge 167:84c0a372a020 319 spim->intfl = mask;
AnnaBridge 167:84c0a372a020 320 }
AnnaBridge 167:84c0a372a020 321
AnnaBridge 167:84c0a372a020 322 /**
AnnaBridge 167:84c0a372a020 323 * @brief Read the current SPIM interrupt flags.
AnnaBridge 167:84c0a372a020 324 *
AnnaBridge 167:84c0a372a020 325 * @param spim Pointer to the SPIM register structure.
AnnaBridge 167:84c0a372a020 326 *
AnnaBridge 167:84c0a372a020 327 * @return Mask of currently set SPIM interrupt flags, see @ref
AnnaBridge 167:84c0a372a020 328 * SPIM_INTFL_Register Register for the SPIM interrupt flag bit
AnnaBridge 167:84c0a372a020 329 * masks.
AnnaBridge 167:84c0a372a020 330 */
AnnaBridge 167:84c0a372a020 331 __STATIC_INLINE unsigned SPIM_GetFlags(mxc_spim_regs_t *spim)
AnnaBridge 167:84c0a372a020 332 {
AnnaBridge 167:84c0a372a020 333 return (spim->intfl);
AnnaBridge 167:84c0a372a020 334 }
AnnaBridge 167:84c0a372a020 335
AnnaBridge 167:84c0a372a020 336 /**@} end of group spim_comm */
AnnaBridge 167:84c0a372a020 337 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 338 }
AnnaBridge 167:84c0a372a020 339 #endif
AnnaBridge 167:84c0a372a020 340
AnnaBridge 167:84c0a372a020 341 #endif /* _SPIM_H_ */