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TARGET_SDT32620B/TOOLCHAIN_IAR/pwrman_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-06-03 13:54:23 -0500 (Fri, 03 Jun 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 23189 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MXC_PWRMAN_REGS_H_
AnnaBridge 167:84c0a372a020 38 #define _MXC_PWRMAN_REGS_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 41 extern "C" {
AnnaBridge 167:84c0a372a020 42 #endif
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 #include <stdint.h>
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /*
AnnaBridge 167:84c0a372a020 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 167:84c0a372a020 48 */
AnnaBridge 167:84c0a372a020 49 #ifndef __IO
AnnaBridge 167:84c0a372a020 50 #define __IO volatile
AnnaBridge 167:84c0a372a020 51 #endif
AnnaBridge 167:84c0a372a020 52 #ifndef __I
AnnaBridge 167:84c0a372a020 53 #define __I volatile const
AnnaBridge 167:84c0a372a020 54 #endif
AnnaBridge 167:84c0a372a020 55 #ifndef __O
AnnaBridge 167:84c0a372a020 56 #define __O volatile
AnnaBridge 167:84c0a372a020 57 #endif
AnnaBridge 167:84c0a372a020 58 #ifndef __RO
AnnaBridge 167:84c0a372a020 59 #define __RO volatile const
AnnaBridge 167:84c0a372a020 60 #endif
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 /**
AnnaBridge 167:84c0a372a020 64 * @brief Defines PAD Modes for Wake Up Detection.
AnnaBridge 167:84c0a372a020 65 */
AnnaBridge 167:84c0a372a020 66 typedef enum {
AnnaBridge 167:84c0a372a020 67 /** WUD Mode for Selected PAD = Clear/Activate */
AnnaBridge 167:84c0a372a020 68 MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
AnnaBridge 167:84c0a372a020 69 /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
AnnaBridge 167:84c0a372a020 70 MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
AnnaBridge 167:84c0a372a020 71 /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
AnnaBridge 167:84c0a372a020 72 MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
AnnaBridge 167:84c0a372a020 73 /** WUD Mode for Selected PAD = No pad state change */
AnnaBridge 167:84c0a372a020 74 MXC_E_PWRMAN_PAD_MODE_NONE
AnnaBridge 167:84c0a372a020 75 }
AnnaBridge 167:84c0a372a020 76 mxc_pwrman_pad_mode_t;
AnnaBridge 167:84c0a372a020 77
AnnaBridge 167:84c0a372a020 78 /*
AnnaBridge 167:84c0a372a020 79 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 167:84c0a372a020 80 access to each register in module.
AnnaBridge 167:84c0a372a020 81 */
AnnaBridge 167:84c0a372a020 82
AnnaBridge 167:84c0a372a020 83 /* Offset Register Description
AnnaBridge 167:84c0a372a020 84 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 85 typedef struct {
AnnaBridge 167:84c0a372a020 86 __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */
AnnaBridge 167:84c0a372a020 87 __IO uint32_t intfl; /* 0x0004 Interrupt Flags */
AnnaBridge 167:84c0a372a020 88 __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
AnnaBridge 167:84c0a372a020 89 __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */
AnnaBridge 167:84c0a372a020 90 __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */
AnnaBridge 167:84c0a372a020 91 __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */
AnnaBridge 167:84c0a372a020 92 __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */
AnnaBridge 167:84c0a372a020 93 __IO uint32_t wud_seen0; /* 0x001C Wake-up Detect Status for P0/P1/P2/P3 */
AnnaBridge 167:84c0a372a020 94 __IO uint32_t wud_seen1; /* 0x0020 Wake-up Detect Status for P4/P5/P6/P7 */
AnnaBridge 167:84c0a372a020 95 __RO uint32_t rsv024[3]; /* 0x0024-0x002C */
AnnaBridge 167:84c0a372a020 96 __IO uint32_t pt_regmap_ctrl; /* 0x0030 PT Register Mapping Control */
AnnaBridge 167:84c0a372a020 97 __RO uint32_t rsv034; /* 0x0034 */
AnnaBridge 167:84c0a372a020 98 __IO uint32_t die_type; /* 0x0038 Die Type ID Register */
AnnaBridge 167:84c0a372a020 99 __IO uint32_t base_part_num; /* 0x003C Base Part Number */
AnnaBridge 167:84c0a372a020 100 __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */
AnnaBridge 167:84c0a372a020 101 __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */
AnnaBridge 167:84c0a372a020 102 __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */
AnnaBridge 167:84c0a372a020 103 } mxc_pwrman_regs_t;
AnnaBridge 167:84c0a372a020 104
AnnaBridge 167:84c0a372a020 105
AnnaBridge 167:84c0a372a020 106 /*
AnnaBridge 167:84c0a372a020 107 Register offsets for module PWRMAN.
AnnaBridge 167:84c0a372a020 108 */
AnnaBridge 167:84c0a372a020 109
AnnaBridge 167:84c0a372a020 110 #define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 111 #define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL)
AnnaBridge 167:84c0a372a020 112 #define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL)
AnnaBridge 167:84c0a372a020 113 #define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL)
AnnaBridge 167:84c0a372a020 114 #define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL)
AnnaBridge 167:84c0a372a020 115 #define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL)
AnnaBridge 167:84c0a372a020 116 #define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL)
AnnaBridge 167:84c0a372a020 117 #define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x0000001CUL)
AnnaBridge 167:84c0a372a020 118 #define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000020UL)
AnnaBridge 167:84c0a372a020 119 #define MXC_R_PWRMAN_OFFS_PT_REGMAP_CTRL ((uint32_t)0x00000030UL)
AnnaBridge 167:84c0a372a020 120 #define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL)
AnnaBridge 167:84c0a372a020 121 #define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL)
AnnaBridge 167:84c0a372a020 122 #define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL)
AnnaBridge 167:84c0a372a020 123 #define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL)
AnnaBridge 167:84c0a372a020 124 #define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL)
AnnaBridge 167:84c0a372a020 125
AnnaBridge 167:84c0a372a020 126
AnnaBridge 167:84c0a372a020 127 /*
AnnaBridge 167:84c0a372a020 128 Field positions and masks for module PWRMAN.
AnnaBridge 167:84c0a372a020 129 */
AnnaBridge 167:84c0a372a020 130
AnnaBridge 167:84c0a372a020 131 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2
AnnaBridge 167:84c0a372a020 132 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
AnnaBridge 167:84c0a372a020 133 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3
AnnaBridge 167:84c0a372a020 134 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
AnnaBridge 167:84c0a372a020 135 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4
AnnaBridge 167:84c0a372a020 136 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
AnnaBridge 167:84c0a372a020 137 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5
AnnaBridge 167:84c0a372a020 138 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
AnnaBridge 167:84c0a372a020 139 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8
AnnaBridge 167:84c0a372a020 140 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
AnnaBridge 167:84c0a372a020 141 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9
AnnaBridge 167:84c0a372a020 142 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
AnnaBridge 167:84c0a372a020 143 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16
AnnaBridge 167:84c0a372a020 144 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
AnnaBridge 167:84c0a372a020 145 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 17
AnnaBridge 167:84c0a372a020 146 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
AnnaBridge 167:84c0a372a020 147 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 18
AnnaBridge 167:84c0a372a020 148 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
AnnaBridge 167:84c0a372a020 149 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 19
AnnaBridge 167:84c0a372a020 150 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
AnnaBridge 167:84c0a372a020 151 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 20
AnnaBridge 167:84c0a372a020 152 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
AnnaBridge 167:84c0a372a020 153 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21
AnnaBridge 167:84c0a372a020 154 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
AnnaBridge 167:84c0a372a020 155 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22
AnnaBridge 167:84c0a372a020 156 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
AnnaBridge 167:84c0a372a020 157 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31
AnnaBridge 167:84c0a372a020 158 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
AnnaBridge 167:84c0a372a020 159
AnnaBridge 167:84c0a372a020 160 #define MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS 0
AnnaBridge 167:84c0a372a020 161 #define MXC_F_PWRMAN_INTFL_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS))
AnnaBridge 167:84c0a372a020 162 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 1
AnnaBridge 167:84c0a372a020 163 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
AnnaBridge 167:84c0a372a020 164 #define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2
AnnaBridge 167:84c0a372a020 165 #define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
AnnaBridge 167:84c0a372a020 166 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 3
AnnaBridge 167:84c0a372a020 167 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
AnnaBridge 167:84c0a372a020 168 #define MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS 4
AnnaBridge 167:84c0a372a020 169 #define MXC_F_PWRMAN_INTFL_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS))
AnnaBridge 167:84c0a372a020 170 #define MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS 5
AnnaBridge 167:84c0a372a020 171 #define MXC_F_PWRMAN_INTFL_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS))
AnnaBridge 167:84c0a372a020 172 #define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS 6
AnnaBridge 167:84c0a372a020 173 #define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS))
AnnaBridge 167:84c0a372a020 174
AnnaBridge 167:84c0a372a020 175 #define MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS 0
AnnaBridge 167:84c0a372a020 176 #define MXC_F_PWRMAN_INTEN_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS))
AnnaBridge 167:84c0a372a020 177 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 1
AnnaBridge 167:84c0a372a020 178 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
AnnaBridge 167:84c0a372a020 179 #define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2
AnnaBridge 167:84c0a372a020 180 #define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
AnnaBridge 167:84c0a372a020 181 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 3
AnnaBridge 167:84c0a372a020 182 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
AnnaBridge 167:84c0a372a020 183 #define MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS 4
AnnaBridge 167:84c0a372a020 184 #define MXC_F_PWRMAN_INTEN_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS))
AnnaBridge 167:84c0a372a020 185 #define MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS 5
AnnaBridge 167:84c0a372a020 186 #define MXC_F_PWRMAN_INTEN_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS))
AnnaBridge 167:84c0a372a020 187 #define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS 6
AnnaBridge 167:84c0a372a020 188 #define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS))
AnnaBridge 167:84c0a372a020 189
AnnaBridge 167:84c0a372a020 190 #define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS 0
AnnaBridge 167:84c0a372a020 191 #define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS))
AnnaBridge 167:84c0a372a020 192 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 1
AnnaBridge 167:84c0a372a020 193 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
AnnaBridge 167:84c0a372a020 194 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2
AnnaBridge 167:84c0a372a020 195 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
AnnaBridge 167:84c0a372a020 196 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 3
AnnaBridge 167:84c0a372a020 197 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
AnnaBridge 167:84c0a372a020 198 #define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS 4
AnnaBridge 167:84c0a372a020 199 #define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS))
AnnaBridge 167:84c0a372a020 200 #define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS 5
AnnaBridge 167:84c0a372a020 201 #define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS))
AnnaBridge 167:84c0a372a020 202 #define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS 6
AnnaBridge 167:84c0a372a020 203 #define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS))
AnnaBridge 167:84c0a372a020 204
AnnaBridge 167:84c0a372a020 205 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0
AnnaBridge 167:84c0a372a020 206 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
AnnaBridge 167:84c0a372a020 207 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8
AnnaBridge 167:84c0a372a020 208 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
AnnaBridge 167:84c0a372a020 209 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12
AnnaBridge 167:84c0a372a020 210 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
AnnaBridge 167:84c0a372a020 211 #define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS 16
AnnaBridge 167:84c0a372a020 212 #define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS))
AnnaBridge 167:84c0a372a020 213
AnnaBridge 167:84c0a372a020 214 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0
AnnaBridge 167:84c0a372a020 215 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
AnnaBridge 167:84c0a372a020 216 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1
AnnaBridge 167:84c0a372a020 217 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
AnnaBridge 167:84c0a372a020 218 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2
AnnaBridge 167:84c0a372a020 219 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
AnnaBridge 167:84c0a372a020 220 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3
AnnaBridge 167:84c0a372a020 221 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
AnnaBridge 167:84c0a372a020 222 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4
AnnaBridge 167:84c0a372a020 223 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
AnnaBridge 167:84c0a372a020 224 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5
AnnaBridge 167:84c0a372a020 225 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
AnnaBridge 167:84c0a372a020 226 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6
AnnaBridge 167:84c0a372a020 227 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
AnnaBridge 167:84c0a372a020 228 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7
AnnaBridge 167:84c0a372a020 229 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
AnnaBridge 167:84c0a372a020 230 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8
AnnaBridge 167:84c0a372a020 231 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
AnnaBridge 167:84c0a372a020 232 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9
AnnaBridge 167:84c0a372a020 233 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
AnnaBridge 167:84c0a372a020 234 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10
AnnaBridge 167:84c0a372a020 235 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
AnnaBridge 167:84c0a372a020 236 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11
AnnaBridge 167:84c0a372a020 237 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
AnnaBridge 167:84c0a372a020 238 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12
AnnaBridge 167:84c0a372a020 239 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
AnnaBridge 167:84c0a372a020 240 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13
AnnaBridge 167:84c0a372a020 241 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
AnnaBridge 167:84c0a372a020 242 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14
AnnaBridge 167:84c0a372a020 243 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
AnnaBridge 167:84c0a372a020 244 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15
AnnaBridge 167:84c0a372a020 245 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
AnnaBridge 167:84c0a372a020 246 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16
AnnaBridge 167:84c0a372a020 247 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
AnnaBridge 167:84c0a372a020 248 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17
AnnaBridge 167:84c0a372a020 249 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
AnnaBridge 167:84c0a372a020 250 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18
AnnaBridge 167:84c0a372a020 251 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
AnnaBridge 167:84c0a372a020 252 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19
AnnaBridge 167:84c0a372a020 253 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
AnnaBridge 167:84c0a372a020 254 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20
AnnaBridge 167:84c0a372a020 255 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
AnnaBridge 167:84c0a372a020 256 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21
AnnaBridge 167:84c0a372a020 257 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
AnnaBridge 167:84c0a372a020 258 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22
AnnaBridge 167:84c0a372a020 259 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
AnnaBridge 167:84c0a372a020 260 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23
AnnaBridge 167:84c0a372a020 261 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
AnnaBridge 167:84c0a372a020 262 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24
AnnaBridge 167:84c0a372a020 263 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
AnnaBridge 167:84c0a372a020 264 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25
AnnaBridge 167:84c0a372a020 265 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
AnnaBridge 167:84c0a372a020 266 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26
AnnaBridge 167:84c0a372a020 267 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
AnnaBridge 167:84c0a372a020 268 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27
AnnaBridge 167:84c0a372a020 269 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
AnnaBridge 167:84c0a372a020 270 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28
AnnaBridge 167:84c0a372a020 271 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
AnnaBridge 167:84c0a372a020 272 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29
AnnaBridge 167:84c0a372a020 273 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
AnnaBridge 167:84c0a372a020 274 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30
AnnaBridge 167:84c0a372a020 275 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
AnnaBridge 167:84c0a372a020 276 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31
AnnaBridge 167:84c0a372a020 277 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
AnnaBridge 167:84c0a372a020 278
AnnaBridge 167:84c0a372a020 279 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0
AnnaBridge 167:84c0a372a020 280 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
AnnaBridge 167:84c0a372a020 281 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1
AnnaBridge 167:84c0a372a020 282 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
AnnaBridge 167:84c0a372a020 283 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2
AnnaBridge 167:84c0a372a020 284 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
AnnaBridge 167:84c0a372a020 285 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3
AnnaBridge 167:84c0a372a020 286 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
AnnaBridge 167:84c0a372a020 287 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4
AnnaBridge 167:84c0a372a020 288 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
AnnaBridge 167:84c0a372a020 289 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5
AnnaBridge 167:84c0a372a020 290 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
AnnaBridge 167:84c0a372a020 291 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6
AnnaBridge 167:84c0a372a020 292 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
AnnaBridge 167:84c0a372a020 293 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7
AnnaBridge 167:84c0a372a020 294 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
AnnaBridge 167:84c0a372a020 295 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8
AnnaBridge 167:84c0a372a020 296 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
AnnaBridge 167:84c0a372a020 297 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9
AnnaBridge 167:84c0a372a020 298 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
AnnaBridge 167:84c0a372a020 299 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10
AnnaBridge 167:84c0a372a020 300 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
AnnaBridge 167:84c0a372a020 301 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11
AnnaBridge 167:84c0a372a020 302 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
AnnaBridge 167:84c0a372a020 303 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12
AnnaBridge 167:84c0a372a020 304 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
AnnaBridge 167:84c0a372a020 305 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13
AnnaBridge 167:84c0a372a020 306 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
AnnaBridge 167:84c0a372a020 307 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14
AnnaBridge 167:84c0a372a020 308 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
AnnaBridge 167:84c0a372a020 309 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15
AnnaBridge 167:84c0a372a020 310 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
AnnaBridge 167:84c0a372a020 311 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16
AnnaBridge 167:84c0a372a020 312 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
AnnaBridge 167:84c0a372a020 313
AnnaBridge 167:84c0a372a020 314 #define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS 0
AnnaBridge 167:84c0a372a020 315 #define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS))
AnnaBridge 167:84c0a372a020 316
AnnaBridge 167:84c0a372a020 317 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0
AnnaBridge 167:84c0a372a020 318 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
AnnaBridge 167:84c0a372a020 319
AnnaBridge 167:84c0a372a020 320 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0
AnnaBridge 167:84c0a372a020 321 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
AnnaBridge 167:84c0a372a020 322 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4
AnnaBridge 167:84c0a372a020 323 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
AnnaBridge 167:84c0a372a020 324
AnnaBridge 167:84c0a372a020 325 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0
AnnaBridge 167:84c0a372a020 326 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
AnnaBridge 167:84c0a372a020 327 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31
AnnaBridge 167:84c0a372a020 328 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
AnnaBridge 167:84c0a372a020 329
AnnaBridge 167:84c0a372a020 330 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 0
AnnaBridge 167:84c0a372a020 331 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
AnnaBridge 167:84c0a372a020 332 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS 1
AnnaBridge 167:84c0a372a020 333 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS))
AnnaBridge 167:84c0a372a020 334 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS 2
AnnaBridge 167:84c0a372a020 335 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS))
AnnaBridge 167:84c0a372a020 336 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 3
AnnaBridge 167:84c0a372a020 337 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
AnnaBridge 167:84c0a372a020 338 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 4
AnnaBridge 167:84c0a372a020 339 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
AnnaBridge 167:84c0a372a020 340 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 5
AnnaBridge 167:84c0a372a020 341 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
AnnaBridge 167:84c0a372a020 342 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6
AnnaBridge 167:84c0a372a020 343 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
AnnaBridge 167:84c0a372a020 344 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 7
AnnaBridge 167:84c0a372a020 345 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
AnnaBridge 167:84c0a372a020 346 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 8
AnnaBridge 167:84c0a372a020 347 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
AnnaBridge 167:84c0a372a020 348 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 9
AnnaBridge 167:84c0a372a020 349 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
AnnaBridge 167:84c0a372a020 350 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 10
AnnaBridge 167:84c0a372a020 351 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
AnnaBridge 167:84c0a372a020 352 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 11
AnnaBridge 167:84c0a372a020 353 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
AnnaBridge 167:84c0a372a020 354 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS 12
AnnaBridge 167:84c0a372a020 355 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS))
AnnaBridge 167:84c0a372a020 356 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS 13
AnnaBridge 167:84c0a372a020 357 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS))
AnnaBridge 167:84c0a372a020 358 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 14
AnnaBridge 167:84c0a372a020 359 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
AnnaBridge 167:84c0a372a020 360 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 15
AnnaBridge 167:84c0a372a020 361 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
AnnaBridge 167:84c0a372a020 362 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 16
AnnaBridge 167:84c0a372a020 363 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
AnnaBridge 167:84c0a372a020 364 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS 17
AnnaBridge 167:84c0a372a020 365 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS))
AnnaBridge 167:84c0a372a020 366 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS 18
AnnaBridge 167:84c0a372a020 367 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS))
AnnaBridge 167:84c0a372a020 368 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 19
AnnaBridge 167:84c0a372a020 369 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
AnnaBridge 167:84c0a372a020 370 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 20
AnnaBridge 167:84c0a372a020 371 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
AnnaBridge 167:84c0a372a020 372 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS 21
AnnaBridge 167:84c0a372a020 373 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS))
AnnaBridge 167:84c0a372a020 374 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22
AnnaBridge 167:84c0a372a020 375 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
AnnaBridge 167:84c0a372a020 376 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS 23
AnnaBridge 167:84c0a372a020 377 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS))
AnnaBridge 167:84c0a372a020 378 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS 24
AnnaBridge 167:84c0a372a020 379 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS))
AnnaBridge 167:84c0a372a020 380 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS 25
AnnaBridge 167:84c0a372a020 381 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS))
AnnaBridge 167:84c0a372a020 382 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS 26
AnnaBridge 167:84c0a372a020 383 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS))
AnnaBridge 167:84c0a372a020 384 #define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS 27
AnnaBridge 167:84c0a372a020 385 #define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS))
AnnaBridge 167:84c0a372a020 386 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 28
AnnaBridge 167:84c0a372a020 387 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
AnnaBridge 167:84c0a372a020 388 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS 29
AnnaBridge 167:84c0a372a020 389 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS))
AnnaBridge 167:84c0a372a020 390
AnnaBridge 167:84c0a372a020 391
AnnaBridge 167:84c0a372a020 392
AnnaBridge 167:84c0a372a020 393 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 394 }
AnnaBridge 167:84c0a372a020 395 #endif
AnnaBridge 167:84c0a372a020 396
AnnaBridge 167:84c0a372a020 397 #endif /* _MXC_PWRMAN_REGS_H_ */
AnnaBridge 167:84c0a372a020 398