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TARGET_SDT32620B/TOOLCHAIN_IAR/pmu_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-04-25 15:50:53 -0500 (Mon, 25 Apr 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 22510 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MXC_PMU_REGS_H_
AnnaBridge 167:84c0a372a020 38 #define _MXC_PMU_REGS_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 41 extern "C" {
AnnaBridge 167:84c0a372a020 42 #endif
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 #include <stdint.h>
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /*
AnnaBridge 167:84c0a372a020 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 167:84c0a372a020 48 */
AnnaBridge 167:84c0a372a020 49 #ifndef __IO
AnnaBridge 167:84c0a372a020 50 #define __IO volatile
AnnaBridge 167:84c0a372a020 51 #endif
AnnaBridge 167:84c0a372a020 52 #ifndef __I
AnnaBridge 167:84c0a372a020 53 #define __I volatile const
AnnaBridge 167:84c0a372a020 54 #endif
AnnaBridge 167:84c0a372a020 55 #ifndef __O
AnnaBridge 167:84c0a372a020 56 #define __O volatile
AnnaBridge 167:84c0a372a020 57 #endif
AnnaBridge 167:84c0a372a020 58 #ifndef __RO
AnnaBridge 167:84c0a372a020 59 #define __RO volatile const
AnnaBridge 167:84c0a372a020 60 #endif
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62 /*
AnnaBridge 167:84c0a372a020 63 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 167:84c0a372a020 64 access to each register in module.
AnnaBridge 167:84c0a372a020 65 */
AnnaBridge 167:84c0a372a020 66
AnnaBridge 167:84c0a372a020 67 /* Offset Register Description
AnnaBridge 167:84c0a372a020 68 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 69 typedef struct {
AnnaBridge 167:84c0a372a020 70 __IO uint32_t dscadr; /* 0x0000 PMU Channel Next Descriptor Address */
AnnaBridge 167:84c0a372a020 71 __IO uint32_t cfg; /* 0x0004 PMU Channel Configuration */
AnnaBridge 167:84c0a372a020 72 __IO uint32_t loop; /* 0x0008 PMU Channel Loop Counters */
AnnaBridge 167:84c0a372a020 73 __RO uint32_t rsv00C[5]; /* 0x000C-0x001C */
AnnaBridge 167:84c0a372a020 74 } mxc_pmu_regs_t;
AnnaBridge 167:84c0a372a020 75
AnnaBridge 167:84c0a372a020 76
AnnaBridge 167:84c0a372a020 77 /*
AnnaBridge 167:84c0a372a020 78 Register offsets for module PMU.
AnnaBridge 167:84c0a372a020 79 */
AnnaBridge 167:84c0a372a020 80
AnnaBridge 167:84c0a372a020 81 #define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 82 #define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL)
AnnaBridge 167:84c0a372a020 83 #define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL)
AnnaBridge 167:84c0a372a020 84
AnnaBridge 167:84c0a372a020 85
AnnaBridge 167:84c0a372a020 86 /*
AnnaBridge 167:84c0a372a020 87 Field positions and masks for module PMU.
AnnaBridge 167:84c0a372a020 88 */
AnnaBridge 167:84c0a372a020 89
AnnaBridge 167:84c0a372a020 90 #define MXC_F_PMU_CFG_ENABLE_POS 0
AnnaBridge 167:84c0a372a020 91 #define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
AnnaBridge 167:84c0a372a020 92 #define MXC_F_PMU_CFG_LL_STOPPED_POS 2
AnnaBridge 167:84c0a372a020 93 #define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
AnnaBridge 167:84c0a372a020 94 #define MXC_F_PMU_CFG_MANUAL_POS 3
AnnaBridge 167:84c0a372a020 95 #define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
AnnaBridge 167:84c0a372a020 96 #define MXC_F_PMU_CFG_BUS_ERROR_POS 4
AnnaBridge 167:84c0a372a020 97 #define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
AnnaBridge 167:84c0a372a020 98 #define MXC_F_PMU_CFG_TO_STAT_POS 6
AnnaBridge 167:84c0a372a020 99 #define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
AnnaBridge 167:84c0a372a020 100 #define MXC_F_PMU_CFG_TO_SEL_POS 11
AnnaBridge 167:84c0a372a020 101 #define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
AnnaBridge 167:84c0a372a020 102 #define MXC_F_PMU_CFG_PS_SEL_POS 14
AnnaBridge 167:84c0a372a020 103 #define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
AnnaBridge 167:84c0a372a020 104 #define MXC_F_PMU_CFG_INTERRUPT_POS 16
AnnaBridge 167:84c0a372a020 105 #define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
AnnaBridge 167:84c0a372a020 106 #define MXC_F_PMU_CFG_INT_EN_POS 17
AnnaBridge 167:84c0a372a020 107 #define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
AnnaBridge 167:84c0a372a020 108 #define MXC_F_PMU_CFG_BURST_SIZE_POS 24
AnnaBridge 167:84c0a372a020 109 #define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
AnnaBridge 167:84c0a372a020 110
AnnaBridge 167:84c0a372a020 111 #define MXC_F_PMU_LOOP_COUNTER_0_POS 0
AnnaBridge 167:84c0a372a020 112 #define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
AnnaBridge 167:84c0a372a020 113 #define MXC_F_PMU_LOOP_COUNTER_1_POS 16
AnnaBridge 167:84c0a372a020 114 #define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
AnnaBridge 167:84c0a372a020 115
AnnaBridge 167:84c0a372a020 116 /*
AnnaBridge 167:84c0a372a020 117 Field values
AnnaBridge 167:84c0a372a020 118 */
AnnaBridge 167:84c0a372a020 119
AnnaBridge 167:84c0a372a020 120 #define MXC_V_PMU_CFG_TO_SEL_TICKS_4 ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 121 #define MXC_V_PMU_CFG_TO_SEL_TICKS_8 ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 122 #define MXC_V_PMU_CFG_TO_SEL_TICKS_16 ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 123 #define MXC_V_PMU_CFG_TO_SEL_TICKS_32 ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 124 #define MXC_V_PMU_CFG_TO_SEL_TICKS_64 ((uint32_t)(0x00000004UL))
AnnaBridge 167:84c0a372a020 125 #define MXC_V_PMU_CFG_TO_SEL_TICKS_128 ((uint32_t)(0x00000005UL))
AnnaBridge 167:84c0a372a020 126 #define MXC_V_PMU_CFG_TO_SEL_TICKS_256 ((uint32_t)(0x00000006UL))
AnnaBridge 167:84c0a372a020 127 #define MXC_V_PMU_CFG_TO_SEL_TICKS_512 ((uint32_t)(0x00000007UL))
AnnaBridge 167:84c0a372a020 128
AnnaBridge 167:84c0a372a020 129 #define MXC_V_PMU_CFG_PS_SEL_DISABLE ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 130 #define MXC_V_PMU_CFG_PS_SEL_DIV_2_8 ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 131 #define MXC_V_PMU_CFG_PS_SEL_DIV_2_16 ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 132 #define MXC_V_PMU_CFG_PS_SEL_DIV_2_24 ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 133
AnnaBridge 167:84c0a372a020 134 /* Op codes */
AnnaBridge 167:84c0a372a020 135 #define PMU_MOVE_OP 0
AnnaBridge 167:84c0a372a020 136 #define PMU_WRITE_OP 1
AnnaBridge 167:84c0a372a020 137 #define PMU_WAIT_OP 2
AnnaBridge 167:84c0a372a020 138 #define PMU_JUMP_OP 3
AnnaBridge 167:84c0a372a020 139 #define PMU_LOOP_OP 4
AnnaBridge 167:84c0a372a020 140 #define PMU_POLL_OP 5
AnnaBridge 167:84c0a372a020 141 #define PMU_BRANCH_OP 6
AnnaBridge 167:84c0a372a020 142 #define PMU_TRANSFER_OP 7
AnnaBridge 167:84c0a372a020 143
AnnaBridge 167:84c0a372a020 144 /* Bit values used in all decroptiors */
AnnaBridge 167:84c0a372a020 145 #define PMU_NO_INTERRUPT 0 /* Interrupt flag is NOT set at end of channel execution */
AnnaBridge 167:84c0a372a020 146 #define PMU_INTERRUPT 1 /* Interrupt flag is set at end of channel execution */
AnnaBridge 167:84c0a372a020 147
AnnaBridge 167:84c0a372a020 148 #define PMU_NO_STOP 0 /* Do not stop channel after this descriptor ends */
AnnaBridge 167:84c0a372a020 149 #define PMU_STOP 1 /* Halt PMU channel after this descriptor ends */
AnnaBridge 167:84c0a372a020 150
AnnaBridge 167:84c0a372a020 151 /* Interrupt and Stop bit positions */
AnnaBridge 167:84c0a372a020 152 #define PMU_INT_POS 3
AnnaBridge 167:84c0a372a020 153 #define PMU_STOP_POS 4
AnnaBridge 167:84c0a372a020 154
AnnaBridge 167:84c0a372a020 155 /* MOVE descriptor bit values */
AnnaBridge 167:84c0a372a020 156 #define PMU_MOVE_READ_8_BIT 0 /* Read size = 8 */
AnnaBridge 167:84c0a372a020 157 #define PMU_MOVE_READ_16_BIT 1 /* Read size = 16 */
AnnaBridge 167:84c0a372a020 158 #define PMU_MOVE_READ_32_BIT 2 /* Read size = 32 */
AnnaBridge 167:84c0a372a020 159
AnnaBridge 167:84c0a372a020 160 #define PMU_MOVE_READ_NO_INC 0 /* read address not incremented */
AnnaBridge 167:84c0a372a020 161 #define PMU_MOVE_READ_INC 1 /* Auto-Increment read address */
AnnaBridge 167:84c0a372a020 162
AnnaBridge 167:84c0a372a020 163 #define PMU_MOVE_WRITE_8_BIT 0 /* Write Size = 8 */
AnnaBridge 167:84c0a372a020 164 #define PMU_MOVE_WRITE_16_BIT 1 /* Write Size = 16 */
AnnaBridge 167:84c0a372a020 165 #define PMU_MOVE_WRITE_32_BIT 2 /* Write Size = 32 */
AnnaBridge 167:84c0a372a020 166
AnnaBridge 167:84c0a372a020 167 #define PMU_MOVE_WRITE_NO_INC 0 /* Write address not incremented */
AnnaBridge 167:84c0a372a020 168 #define PMU_MOVE_WRITE_INC 1 /* Auto_Increment write address */
AnnaBridge 167:84c0a372a020 169
AnnaBridge 167:84c0a372a020 170 #define PMU_MOVE_NO_CONT 0 /* MOVE does not rely on previous MOVE */
AnnaBridge 167:84c0a372a020 171 #define PMU_MOVE_CONT 1 /* MOVE continues from read/write address */
AnnaBridge 167:84c0a372a020 172 /* and INC values defined in previous MOVE */
AnnaBridge 167:84c0a372a020 173
AnnaBridge 167:84c0a372a020 174 /* MOVE bit positions */
AnnaBridge 167:84c0a372a020 175 #define PMU_MOVE_READS_POS 5
AnnaBridge 167:84c0a372a020 176 #define PMU_MOVE_READI_POS 7
AnnaBridge 167:84c0a372a020 177 #define PMU_MOVE_WRITES_POS 8
AnnaBridge 167:84c0a372a020 178 #define PMU_MOVE_WRITEI_POS 10
AnnaBridge 167:84c0a372a020 179 #define PMU_MOVE_CONT_POS 11
AnnaBridge 167:84c0a372a020 180 #define PMU_MOVE_LEN_POS 12
AnnaBridge 167:84c0a372a020 181
AnnaBridge 167:84c0a372a020 182 /* WRITE descriptor bit values */
AnnaBridge 167:84c0a372a020 183 #define PMU_WRITE_MASKED_WRITE_VALUE 0 /* Value = READ_VALUE & (~WRITE_MASK) | WRITE_VALUE */
AnnaBridge 167:84c0a372a020 184 #define PMU_WRITE_PLUS_1 1 /* Value = READ_VALUE + 1 */
AnnaBridge 167:84c0a372a020 185 #define PMU_WRITE_MINUS_1 2 /* Value = READ_VALUE - 1 */
AnnaBridge 167:84c0a372a020 186 #define PMU_WRITE_SHIFT_RT_1 3 /* Value = READ_VALUE >> 1 */
AnnaBridge 167:84c0a372a020 187 #define PMU_WRITE_SHIFT_LT_1 4 /* Value = READ_VALUE << 1 */
AnnaBridge 167:84c0a372a020 188 #define PMU_WRITE_ROTATE_RT_1 5 /* Value = READ_VALUE rotated right by 1 (bit 0 becomes bit 31) */
AnnaBridge 167:84c0a372a020 189 #define PMU_WRITE_ROTATE_LT_1 6 /* Value = READ_VALUE rotated left by 1 (bit 31 becomes bit 0) */
AnnaBridge 167:84c0a372a020 190 #define PMU_WRITE_NOT_READ_VAL 7 /* Value = ~READ_VALUE */
AnnaBridge 167:84c0a372a020 191 #define PMU_WRITE_XOR_MASK 8 /* Value = READ_VALUE XOR WRITE_MASK */
AnnaBridge 167:84c0a372a020 192 #define PMU_WRITE_OR_MASK 9 /* Value = READ_VALUE | WRITE_MASK */
AnnaBridge 167:84c0a372a020 193 #define PMU_WRITE_AND_MASK 10 /* Value = READ_VALUE & WRITE_MASK */
AnnaBridge 167:84c0a372a020 194
AnnaBridge 167:84c0a372a020 195 /* WRITE bit positions */
AnnaBridge 167:84c0a372a020 196 #define PMU_WRITE_METHOD_POS 8
AnnaBridge 167:84c0a372a020 197
AnnaBridge 167:84c0a372a020 198 /* WAIT descriptor bit values */
AnnaBridge 167:84c0a372a020 199 #define PMU_WAIT_SEL_0 0 /* Select the interrupt source */
AnnaBridge 167:84c0a372a020 200 #define PMU_WAIT_SEL_1 1
AnnaBridge 167:84c0a372a020 201
AnnaBridge 167:84c0a372a020 202 /* WAIT bit positions */
AnnaBridge 167:84c0a372a020 203 #define PMU_WAIT_WAIT_POS 5
AnnaBridge 167:84c0a372a020 204 #define PMU_WAIT_SEL_POS 6
AnnaBridge 167:84c0a372a020 205
AnnaBridge 167:84c0a372a020 206 /* LOOP descriptor bit values */
AnnaBridge 167:84c0a372a020 207 #define PMU_LOOP_SEL_COUNTER0 0 /* select Counter0 to count down from */
AnnaBridge 167:84c0a372a020 208 #define PMU_LOOP_SEL_COUNTER1 1 /* select Counter1 to count down from */
AnnaBridge 167:84c0a372a020 209
AnnaBridge 167:84c0a372a020 210 /* LOOP bit positions */
AnnaBridge 167:84c0a372a020 211 #define PMU_LOOP_SEL_COUNTER_POS 5
AnnaBridge 167:84c0a372a020 212
AnnaBridge 167:84c0a372a020 213 /* POLL descriptor bit values */
AnnaBridge 167:84c0a372a020 214 #define PMU_POLL_OR 0 /* polling ends when at least one mask bit matches expected data */
AnnaBridge 167:84c0a372a020 215 #define PMU_POLL_AND 1 /* polling ends when all mask bits matches expected data */
AnnaBridge 167:84c0a372a020 216
AnnaBridge 167:84c0a372a020 217 /* POLL bit positions */
AnnaBridge 167:84c0a372a020 218 #define PMU_POLL_AND_POS 7
AnnaBridge 167:84c0a372a020 219
AnnaBridge 167:84c0a372a020 220 /* BRANCH descriptor bit values */
AnnaBridge 167:84c0a372a020 221 #define PMU_BRANCH_OR 0 /* branch when any mask bit = or != expected data (based on = or != branch type) */
AnnaBridge 167:84c0a372a020 222 #define PMU_BRANCH_AND 1 /* branch when all mask bit = or != expected data (based on = or != branch type) */
AnnaBridge 167:84c0a372a020 223
AnnaBridge 167:84c0a372a020 224 #define PMU_BRANCH_TYPE_NOT_EQUAL 0 /* Branch when polled data != expected data */
AnnaBridge 167:84c0a372a020 225 #define PMU_BRANCH_TYPE_EQUAL 1 /* Branch when polled data = expected data */
AnnaBridge 167:84c0a372a020 226 #define PMU_BRANCH_TYPE_LESS_OR_EQUAL 2 /* Branch when polled data <= expected data */
AnnaBridge 167:84c0a372a020 227 #define PMU_BRANCH_TYPE_GREAT_OR_EQUAL 3 /* Branch when polled data >= expected data */
AnnaBridge 167:84c0a372a020 228 #define PMU_BRANCH_TYPE_LESSER 4 /* Branch when polled data < expected data */
AnnaBridge 167:84c0a372a020 229 #define PMU_BRANCH_TYPE_GREATER 5 /* Branch when polled data > expected data */
AnnaBridge 167:84c0a372a020 230
AnnaBridge 167:84c0a372a020 231 /* BRANCH bit positions */
AnnaBridge 167:84c0a372a020 232 #define PMU_BRANCH_AND_POS 7
AnnaBridge 167:84c0a372a020 233 #define PMU_BRANCH_TYPE_POS 8
AnnaBridge 167:84c0a372a020 234
AnnaBridge 167:84c0a372a020 235 /* TRANSFER descriptor bit values */
AnnaBridge 167:84c0a372a020 236 #define PMU_TX_READ_8_BIT 0 /* Read size = 8 */
AnnaBridge 167:84c0a372a020 237 #define PMU_TX_READ_16_BIT 1 /* Read size = 16 */
AnnaBridge 167:84c0a372a020 238 #define PMU_TX_READ_32_BIT 2 /* Read size = 32 */
AnnaBridge 167:84c0a372a020 239
AnnaBridge 167:84c0a372a020 240 #define PMU_TX_READ_NO_INC 0 /* read address not incremented */
AnnaBridge 167:84c0a372a020 241 #define PMU_TX_READ_INC 1 /* Auto-Increment read address */
AnnaBridge 167:84c0a372a020 242
AnnaBridge 167:84c0a372a020 243 #define PMU_TX_WRITE_8_BIT 0 /* Write Size = 8 */
AnnaBridge 167:84c0a372a020 244 #define PMU_TX_WRITE_16_BIT 1 /* Write Size = 16 */
AnnaBridge 167:84c0a372a020 245 #define PMU_TX_WRITE_32_BIT 2 /* Write Size = 32 */
AnnaBridge 167:84c0a372a020 246
AnnaBridge 167:84c0a372a020 247 #define PMU_TX_WRITE_NO_INC 0 /* Write address not incremented */
AnnaBridge 167:84c0a372a020 248 #define PMU_TX_WRITE_INC 1 /* Auto_Increment write address */
AnnaBridge 167:84c0a372a020 249
AnnaBridge 167:84c0a372a020 250 /* TRANSFER bit positions */
AnnaBridge 167:84c0a372a020 251 #define PMU_TX_READS_POS 5
AnnaBridge 167:84c0a372a020 252 #define PMU_TX_READI_POS 7
AnnaBridge 167:84c0a372a020 253 #define PMU_TX_WRITES_POS 8
AnnaBridge 167:84c0a372a020 254 #define PMU_TX_WRITEI_POS 10
AnnaBridge 167:84c0a372a020 255 #define PMU_TX_LEN_POS 12
AnnaBridge 167:84c0a372a020 256 #define PMU_TX_BS_POS 26
AnnaBridge 167:84c0a372a020 257
AnnaBridge 167:84c0a372a020 258 /* PMU interrupt sources for the WAIT opcode */
AnnaBridge 167:84c0a372a020 259 #define PMU_WAIT_IRQ_MASK1_SEL0_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0))
AnnaBridge 167:84c0a372a020 260 #define PMU_WAIT_IRQ_MASK1_SEL0_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1))
AnnaBridge 167:84c0a372a020 261 #define PMU_WAIT_IRQ_MASK1_SEL0_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2))
AnnaBridge 167:84c0a372a020 262 #define PMU_WAIT_IRQ_MASK1_SEL0_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3))
AnnaBridge 167:84c0a372a020 263 #define PMU_WAIT_IRQ_MASK1_SEL0_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4))
AnnaBridge 167:84c0a372a020 264 #define PMU_WAIT_IRQ_MASK1_SEL0_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5))
AnnaBridge 167:84c0a372a020 265 #define PMU_WAIT_IRQ_MASK1_SEL0_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6))
AnnaBridge 167:84c0a372a020 266 #define PMU_WAIT_IRQ_MASK1_SEL0_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7))
AnnaBridge 167:84c0a372a020 267 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8))
AnnaBridge 167:84c0a372a020 268 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9))
AnnaBridge 167:84c0a372a020 269 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10))
AnnaBridge 167:84c0a372a020 270 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11))
AnnaBridge 167:84c0a372a020 271 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12))
AnnaBridge 167:84c0a372a020 272 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13))
AnnaBridge 167:84c0a372a020 273 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14))
AnnaBridge 167:84c0a372a020 274 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15))
AnnaBridge 167:84c0a372a020 275 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 16))
AnnaBridge 167:84c0a372a020 276 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 17))
AnnaBridge 167:84c0a372a020 277 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 18))
AnnaBridge 167:84c0a372a020 278 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 19))
AnnaBridge 167:84c0a372a020 279 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_RX_STALLED ((uint32_t)(0x00000001UL << 20))
AnnaBridge 167:84c0a372a020 280 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_RX_STALLED ((uint32_t)(0x00000001UL << 21))
AnnaBridge 167:84c0a372a020 281 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_RX_STALLED ((uint32_t)(0x00000001UL << 22))
AnnaBridge 167:84c0a372a020 282 #define PMU_WAIT_IRQ_MASK1_SEL0_SPIB ((uint32_t)(0x00000001UL << 23))
AnnaBridge 167:84c0a372a020 283 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_DONE ((uint32_t)(0x00000001UL << 24))
AnnaBridge 167:84c0a372a020 284 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_DONE ((uint32_t)(0x00000001UL << 25))
AnnaBridge 167:84c0a372a020 285 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_DONE ((uint32_t)(0x00000001UL << 26))
AnnaBridge 167:84c0a372a020 286 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CS ((uint32_t)(0x00000001UL << 27))
AnnaBridge 167:84c0a372a020 287 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_DONE ((uint32_t)(0x00000001UL << 28))
AnnaBridge 167:84c0a372a020 288 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_READY ((uint32_t)(0x00000001UL << 29))
AnnaBridge 167:84c0a372a020 289 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_HI ((uint32_t)(0x00000001UL << 30))
AnnaBridge 167:84c0a372a020 290 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_LOW ((uint32_t)(0x00000001UL << 31))
AnnaBridge 167:84c0a372a020 291 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP0 ((uint32_t)(0x00000001UL << 0))
AnnaBridge 167:84c0a372a020 292 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP1 ((uint32_t)(0x00000001UL << 1))
AnnaBridge 167:84c0a372a020 293 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_PRESCALE ((uint32_t)(0x00000001UL << 2))
AnnaBridge 167:84c0a372a020 294 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_OVERFLOW ((uint32_t)(0x00000001UL << 3))
AnnaBridge 167:84c0a372a020 295 #define PMU_WAIT_IRQ_MASK2_SEL0_PT0_DISABLED ((uint32_t)(0x00000001UL << 4))
AnnaBridge 167:84c0a372a020 296 #define PMU_WAIT_IRQ_MASK2_SEL0_PT1_DISABLED ((uint32_t)(0x00000001UL << 5))
AnnaBridge 167:84c0a372a020 297 #define PMU_WAIT_IRQ_MASK2_SEL0_PT2_DISABLED ((uint32_t)(0x00000001UL << 6))
AnnaBridge 167:84c0a372a020 298 #define PMU_WAIT_IRQ_MASK2_SEL0_PT3_DISABLED ((uint32_t)(0x00000001UL << 7))
AnnaBridge 167:84c0a372a020 299 #define PMU_WAIT_IRQ_MASK2_SEL0_PT4_DISABLED ((uint32_t)(0x00000001UL << 8))
AnnaBridge 167:84c0a372a020 300 #define PMU_WAIT_IRQ_MASK2_SEL0_PT5_DISABLED ((uint32_t)(0x00000001UL << 9))
AnnaBridge 167:84c0a372a020 301 #define PMU_WAIT_IRQ_MASK2_SEL0_PT6_DISABLED ((uint32_t)(0x00000001UL << 10))
AnnaBridge 167:84c0a372a020 302 #define PMU_WAIT_IRQ_MASK2_SEL0_PT7_DISABLED ((uint32_t)(0x00000001UL << 11))
AnnaBridge 167:84c0a372a020 303 #define PMU_WAIT_IRQ_MASK2_SEL0_PT8_DISABLED ((uint32_t)(0x00000001UL << 12))
AnnaBridge 167:84c0a372a020 304 #define PMU_WAIT_IRQ_MASK2_SEL0_PT9_DISABLED ((uint32_t)(0x00000001UL << 13))
AnnaBridge 167:84c0a372a020 305 #define PMU_WAIT_IRQ_MASK2_SEL0_PT10_DISABLED ((uint32_t)(0x00000001UL << 14))
AnnaBridge 167:84c0a372a020 306 #define PMU_WAIT_IRQ_MASK2_SEL0_PT11_DISABLED ((uint32_t)(0x00000001UL << 15))
AnnaBridge 167:84c0a372a020 307 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR0 ((uint32_t)(0x00000001UL << 16))
AnnaBridge 167:84c0a372a020 308 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR1 ((uint32_t)(0x00000001UL << 17))
AnnaBridge 167:84c0a372a020 309 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR2 ((uint32_t)(0x00000001UL << 18))
AnnaBridge 167:84c0a372a020 310 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR3 ((uint32_t)(0x00000001UL << 19))
AnnaBridge 167:84c0a372a020 311 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR4 ((uint32_t)(0x00000001UL << 20))
AnnaBridge 167:84c0a372a020 312 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR5 ((uint32_t)(0x00000001UL << 21))
AnnaBridge 167:84c0a372a020 313 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO0 ((uint32_t)(0x00000001UL << 22))
AnnaBridge 167:84c0a372a020 314 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO1 ((uint32_t)(0x00000001UL << 23))
AnnaBridge 167:84c0a372a020 315 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO2 ((uint32_t)(0x00000001UL << 24))
AnnaBridge 167:84c0a372a020 316 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO3 ((uint32_t)(0x00000001UL << 25))
AnnaBridge 167:84c0a372a020 317 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO4 ((uint32_t)(0x00000001UL << 26))
AnnaBridge 167:84c0a372a020 318 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO5 ((uint32_t)(0x00000001UL << 27))
AnnaBridge 167:84c0a372a020 319 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO6 ((uint32_t)(0x00000001UL << 28))
AnnaBridge 167:84c0a372a020 320 #define PMU_WAIT_IRQ_MASK2_SEL0_AES ((uint32_t)(0x00000001UL << 29))
AnnaBridge 167:84c0a372a020 321 #define PMU_WAIT_IRQ_MASK2_SEL0_MAA_DONE ((uint32_t)(0x00000001UL << 30))
AnnaBridge 167:84c0a372a020 322 #define PMU_WAIT_IRQ_MASK2_SEL0_OWM ((uint32_t)(0x00000001UL << 31))
AnnaBridge 167:84c0a372a020 323 #define PMU_WAIT_IRQ_MASK1_SEL1_GPIO7 ((uint32_t)(0x00000001UL << 0))
AnnaBridge 167:84c0a372a020 324 #define PMU_WAIT_IRQ_MASK1_SEL1_GPIO8 ((uint32_t)(0x00000001UL << 1))
AnnaBridge 167:84c0a372a020 325 #define PMU_WAIT_IRQ_MASK1_SEL1_PT12_DISABLED ((uint32_t)(0x00000001UL << 2))
AnnaBridge 167:84c0a372a020 326 #define PMU_WAIT_IRQ_MASK1_SEL1_PT13_DISABLED ((uint32_t)(0x00000001UL << 3))
AnnaBridge 167:84c0a372a020 327 #define PMU_WAIT_IRQ_MASK1_SEL1_PT14_DISABLED ((uint32_t)(0x00000001UL << 4))
AnnaBridge 167:84c0a372a020 328 #define PMU_WAIT_IRQ_MASK1_SEL1_PT15_DISABLED ((uint32_t)(0x00000001UL << 5))
AnnaBridge 167:84c0a372a020 329 #define PMU_WAIT_IRQ_MASK1_SEL1_PT0_INT ((uint32_t)(0x00000001UL << 6))
AnnaBridge 167:84c0a372a020 330 #define PMU_WAIT_IRQ_MASK1_SEL1_PT1_INT ((uint32_t)(0x00000001UL << 7))
AnnaBridge 167:84c0a372a020 331 #define PMU_WAIT_IRQ_MASK1_SEL1_PT2_INT ((uint32_t)(0x00000001UL << 8))
AnnaBridge 167:84c0a372a020 332 #define PMU_WAIT_IRQ_MASK1_SEL1_PT3_INT ((uint32_t)(0x00000001UL << 9))
AnnaBridge 167:84c0a372a020 333 #define PMU_WAIT_IRQ_MASK1_SEL1_PT4_INT ((uint32_t)(0x00000001UL << 10))
AnnaBridge 167:84c0a372a020 334 #define PMU_WAIT_IRQ_MASK1_SEL1_PT5_INT ((uint32_t)(0x00000001UL << 11))
AnnaBridge 167:84c0a372a020 335 #define PMU_WAIT_IRQ_MASK1_SEL1_PT6_INT ((uint32_t)(0x00000001UL << 12))
AnnaBridge 167:84c0a372a020 336 #define PMU_WAIT_IRQ_MASK1_SEL1_PT7_INT ((uint32_t)(0x00000001UL << 13))
AnnaBridge 167:84c0a372a020 337 #define PMU_WAIT_IRQ_MASK1_SEL1_PT8_INT ((uint32_t)(0x00000001UL << 14))
AnnaBridge 167:84c0a372a020 338 #define PMU_WAIT_IRQ_MASK1_SEL1_PT9_INT ((uint32_t)(0x00000001UL << 15))
AnnaBridge 167:84c0a372a020 339 #define PMU_WAIT_IRQ_MASK1_SEL1_PT10_INT ((uint32_t)(0x00000001UL << 16))
AnnaBridge 167:84c0a372a020 340 #define PMU_WAIT_IRQ_MASK1_SEL1_PT11_INT ((uint32_t)(0x00000001UL << 17))
AnnaBridge 167:84c0a372a020 341 #define PMU_WAIT_IRQ_MASK1_SEL1_PT12_INT ((uint32_t)(0x00000001UL << 18))
AnnaBridge 167:84c0a372a020 342 #define PMU_WAIT_IRQ_MASK1_SEL1_PT13_INT ((uint32_t)(0x00000001UL << 19))
AnnaBridge 167:84c0a372a020 343 #define PMU_WAIT_IRQ_MASK1_SEL1_PT14_INT ((uint32_t)(0x00000001UL << 20))
AnnaBridge 167:84c0a372a020 344 #define PMU_WAIT_IRQ_MASK1_SEL1_PT15_INT ((uint32_t)(0x00000001UL << 21))
AnnaBridge 167:84c0a372a020 345 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 22))
AnnaBridge 167:84c0a372a020 346 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 23))
AnnaBridge 167:84c0a372a020 347 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_NO_DATA ((uint32_t)(0x00000001UL << 24))
AnnaBridge 167:84c0a372a020 348 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_DATA_LOST ((uint32_t)(0x00000001UL << 25))
AnnaBridge 167:84c0a372a020 349 #define PMU_WAIT_IRQ_MASK1_SEL1_SPI0_TX_READY ((uint32_t)(0x00000001UL << 26))
AnnaBridge 167:84c0a372a020 350 #define PMU_WAIT_IRQ_MASK1_SEL1_SPI1_TX_READY ((uint32_t)(0x00000001UL << 27))
AnnaBridge 167:84c0a372a020 351 #define PMU_WAIT_IRQ_MASK1_SEL1_SPI2_TX_READY ((uint32_t)(0x00000001UL << 28))
AnnaBridge 167:84c0a372a020 352 #define PMU_WAIT_IRQ_MASK1_SEL1_UART0_TX_DONE ((uint32_t)(0x00000001UL << 29))
AnnaBridge 167:84c0a372a020 353 #define PMU_WAIT_IRQ_MASK1_SEL1_UART1_TX_DONE ((uint32_t)(0x00000001UL << 30))
AnnaBridge 167:84c0a372a020 354 #define PMU_WAIT_IRQ_MASK1_SEL1_UART2_TX_DONE ((uint32_t)(0x00000001UL << 31))
AnnaBridge 167:84c0a372a020 355 #define PMU_WAIT_IRQ_MASK2_SEL1_UART3_TX_DONE ((uint32_t)(0x00000001UL << 0))
AnnaBridge 167:84c0a372a020 356 #define PMU_WAIT_IRQ_MASK2_SEL1_UART0_RX_DATA_READY ((uint32_t)(0x00000001UL << 1))
AnnaBridge 167:84c0a372a020 357 #define PMU_WAIT_IRQ_MASK2_SEL1_UART1_RX_DATA_READY ((uint32_t)(0x00000001UL << 2))
AnnaBridge 167:84c0a372a020 358 #define PMU_WAIT_IRQ_MASK2_SEL1_UART2_RX_DATA_READY ((uint32_t)(0x00000001UL << 3))
AnnaBridge 167:84c0a372a020 359 #define PMU_WAIT_IRQ_MASK2_SEL1_UART3_RX_DATA_READY ((uint32_t)(0x00000001UL << 4))
AnnaBridge 167:84c0a372a020 360
AnnaBridge 167:84c0a372a020 361 /* PMU interrupt sources for the TRANSFER opcode */
AnnaBridge 167:84c0a372a020 362 #define PMU_TRANSFER_IRQ_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0))
AnnaBridge 167:84c0a372a020 363 #define PMU_TRANSFER_IRQ_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1))
AnnaBridge 167:84c0a372a020 364 #define PMU_TRANSFER_IRQ_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2))
AnnaBridge 167:84c0a372a020 365 #define PMU_TRANSFER_IRQ_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3))
AnnaBridge 167:84c0a372a020 366 #define PMU_TRANSFER_IRQ_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4))
AnnaBridge 167:84c0a372a020 367 #define PMU_TRANSFER_IRQ_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5))
AnnaBridge 167:84c0a372a020 368 #define PMU_TRANSFER_IRQ_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6))
AnnaBridge 167:84c0a372a020 369 #define PMU_TRANSFER_IRQ_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7))
AnnaBridge 167:84c0a372a020 370 #define PMU_TRANSFER_IRQ_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8))
AnnaBridge 167:84c0a372a020 371 #define PMU_TRANSFER_IRQ_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9))
AnnaBridge 167:84c0a372a020 372 #define PMU_TRANSFER_IRQ_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10))
AnnaBridge 167:84c0a372a020 373 #define PMU_TRANSFER_IRQ_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11))
AnnaBridge 167:84c0a372a020 374 #define PMU_TRANSFER_IRQ_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12))
AnnaBridge 167:84c0a372a020 375 #define PMU_TRANSFER_IRQ_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13))
AnnaBridge 167:84c0a372a020 376 #define PMU_TRANSFER_IRQ_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14))
AnnaBridge 167:84c0a372a020 377 #define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15))
AnnaBridge 167:84c0a372a020 378 #define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 16))
AnnaBridge 167:84c0a372a020 379 #define PMU_TRANSFER_IRQ_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 17))
AnnaBridge 167:84c0a372a020 380 #define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 18))
AnnaBridge 167:84c0a372a020 381 #define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 19))
AnnaBridge 167:84c0a372a020 382 #define PMU_TRANSFER_IRQ_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 20))
AnnaBridge 167:84c0a372a020 383 #define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 21))
AnnaBridge 167:84c0a372a020 384 #define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 22))
AnnaBridge 167:84c0a372a020 385 #define PMU_TRANSFER_IRQ_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 23))
AnnaBridge 167:84c0a372a020 386 #define PMU_TRANSFER_IRQ_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 24))
AnnaBridge 167:84c0a372a020 387
AnnaBridge 167:84c0a372a020 388
AnnaBridge 167:84c0a372a020 389 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 390 }
AnnaBridge 167:84c0a372a020 391 #endif
AnnaBridge 167:84c0a372a020 392
AnnaBridge 167:84c0a372a020 393 #endif /* _MXC_PMU_REGS_H_ */
AnnaBridge 167:84c0a372a020 394