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TARGET_SDT32620B/TOOLCHAIN_IAR/aes_regs.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 167:84c0a372a020 | 1 | /******************************************************************************* |
AnnaBridge | 167:84c0a372a020 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
AnnaBridge | 167:84c0a372a020 | 3 | * |
AnnaBridge | 167:84c0a372a020 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
AnnaBridge | 167:84c0a372a020 | 5 | * copy of this software and associated documentation files (the "Software"), |
AnnaBridge | 167:84c0a372a020 | 6 | * to deal in the Software without restriction, including without limitation |
AnnaBridge | 167:84c0a372a020 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
AnnaBridge | 167:84c0a372a020 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
AnnaBridge | 167:84c0a372a020 | 9 | * Software is furnished to do so, subject to the following conditions: |
AnnaBridge | 167:84c0a372a020 | 10 | * |
AnnaBridge | 167:84c0a372a020 | 11 | * The above copyright notice and this permission notice shall be included |
AnnaBridge | 167:84c0a372a020 | 12 | * in all copies or substantial portions of the Software. |
AnnaBridge | 167:84c0a372a020 | 13 | * |
AnnaBridge | 167:84c0a372a020 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
AnnaBridge | 167:84c0a372a020 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
AnnaBridge | 167:84c0a372a020 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
AnnaBridge | 167:84c0a372a020 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
AnnaBridge | 167:84c0a372a020 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
AnnaBridge | 167:84c0a372a020 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
AnnaBridge | 167:84c0a372a020 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
AnnaBridge | 167:84c0a372a020 | 21 | * |
AnnaBridge | 167:84c0a372a020 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
AnnaBridge | 167:84c0a372a020 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
AnnaBridge | 167:84c0a372a020 | 24 | * Products, Inc. Branding Policy. |
AnnaBridge | 167:84c0a372a020 | 25 | * |
AnnaBridge | 167:84c0a372a020 | 26 | * The mere transfer of this software does not imply any licenses |
AnnaBridge | 167:84c0a372a020 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
AnnaBridge | 167:84c0a372a020 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
AnnaBridge | 167:84c0a372a020 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
AnnaBridge | 167:84c0a372a020 | 30 | * ownership rights. |
AnnaBridge | 167:84c0a372a020 | 31 | * |
AnnaBridge | 167:84c0a372a020 | 32 | * $Date: 2016-03-11 11:46:37 -0600 (Fri, 11 Mar 2016) $ |
AnnaBridge | 167:84c0a372a020 | 33 | * $Revision: 21839 $ |
AnnaBridge | 167:84c0a372a020 | 34 | * |
AnnaBridge | 167:84c0a372a020 | 35 | ******************************************************************************/ |
AnnaBridge | 167:84c0a372a020 | 36 | |
AnnaBridge | 167:84c0a372a020 | 37 | #ifndef _MXC_AES_REGS_H_ |
AnnaBridge | 167:84c0a372a020 | 38 | #define _MXC_AES_REGS_H_ |
AnnaBridge | 167:84c0a372a020 | 39 | |
AnnaBridge | 167:84c0a372a020 | 40 | #ifdef __cplusplus |
AnnaBridge | 167:84c0a372a020 | 41 | extern "C" { |
AnnaBridge | 167:84c0a372a020 | 42 | #endif |
AnnaBridge | 167:84c0a372a020 | 43 | |
AnnaBridge | 167:84c0a372a020 | 44 | #include <stdint.h> |
AnnaBridge | 167:84c0a372a020 | 45 | |
AnnaBridge | 167:84c0a372a020 | 46 | /* |
AnnaBridge | 167:84c0a372a020 | 47 | If types are not defined elsewhere (CMSIS) define them here |
AnnaBridge | 167:84c0a372a020 | 48 | */ |
AnnaBridge | 167:84c0a372a020 | 49 | #ifndef __IO |
AnnaBridge | 167:84c0a372a020 | 50 | #define __IO volatile |
AnnaBridge | 167:84c0a372a020 | 51 | #endif |
AnnaBridge | 167:84c0a372a020 | 52 | #ifndef __I |
AnnaBridge | 167:84c0a372a020 | 53 | #define __I volatile const |
AnnaBridge | 167:84c0a372a020 | 54 | #endif |
AnnaBridge | 167:84c0a372a020 | 55 | #ifndef __O |
AnnaBridge | 167:84c0a372a020 | 56 | #define __O volatile |
AnnaBridge | 167:84c0a372a020 | 57 | #endif |
AnnaBridge | 167:84c0a372a020 | 58 | #ifndef __RO |
AnnaBridge | 167:84c0a372a020 | 59 | #define __RO volatile const |
AnnaBridge | 167:84c0a372a020 | 60 | #endif |
AnnaBridge | 167:84c0a372a020 | 61 | |
AnnaBridge | 167:84c0a372a020 | 62 | |
AnnaBridge | 167:84c0a372a020 | 63 | /* |
AnnaBridge | 167:84c0a372a020 | 64 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
AnnaBridge | 167:84c0a372a020 | 65 | access to each register in module. |
AnnaBridge | 167:84c0a372a020 | 66 | */ |
AnnaBridge | 167:84c0a372a020 | 67 | |
AnnaBridge | 167:84c0a372a020 | 68 | /* Offset Register Description |
AnnaBridge | 167:84c0a372a020 | 69 | ============= ============================================================================ */ |
AnnaBridge | 167:84c0a372a020 | 70 | typedef struct { |
AnnaBridge | 167:84c0a372a020 | 71 | __IO uint32_t ctrl; /* 0x0000 AES Control and Status */ |
AnnaBridge | 167:84c0a372a020 | 72 | __RO uint32_t rsv004; /* 0x0004 */ |
AnnaBridge | 167:84c0a372a020 | 73 | __IO uint32_t erase_all; /* 0x0008 Write to Trigger AES Memory Erase */ |
AnnaBridge | 167:84c0a372a020 | 74 | } mxc_aes_regs_t; |
AnnaBridge | 167:84c0a372a020 | 75 | |
AnnaBridge | 167:84c0a372a020 | 76 | |
AnnaBridge | 167:84c0a372a020 | 77 | /* Offset Register Description |
AnnaBridge | 167:84c0a372a020 | 78 | ============= ============================================================================ */ |
AnnaBridge | 167:84c0a372a020 | 79 | typedef struct { |
AnnaBridge | 167:84c0a372a020 | 80 | __IO uint32_t inp[4]; /* 0x0000-0x000C AES Input (128 bits) */ |
AnnaBridge | 167:84c0a372a020 | 81 | __IO uint32_t key[8]; /* 0x0010-0x002C AES Symmetric Key (up to 256 bits) */ |
AnnaBridge | 167:84c0a372a020 | 82 | __IO uint32_t out[4]; /* 0x0030-0x003C AES Output Data (128 bits) */ |
AnnaBridge | 167:84c0a372a020 | 83 | __IO uint32_t expkey[8]; /* 0x0040-0x005C AES Expanded Key Data (256 bits) */ |
AnnaBridge | 167:84c0a372a020 | 84 | } mxc_aes_mem_regs_t; |
AnnaBridge | 167:84c0a372a020 | 85 | |
AnnaBridge | 167:84c0a372a020 | 86 | |
AnnaBridge | 167:84c0a372a020 | 87 | /* |
AnnaBridge | 167:84c0a372a020 | 88 | Register offsets for module AES. |
AnnaBridge | 167:84c0a372a020 | 89 | */ |
AnnaBridge | 167:84c0a372a020 | 90 | |
AnnaBridge | 167:84c0a372a020 | 91 | #define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL) |
AnnaBridge | 167:84c0a372a020 | 92 | #define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL) |
AnnaBridge | 167:84c0a372a020 | 93 | #define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL) |
AnnaBridge | 167:84c0a372a020 | 94 | #define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL) |
AnnaBridge | 167:84c0a372a020 | 95 | #define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL) |
AnnaBridge | 167:84c0a372a020 | 96 | #define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL) |
AnnaBridge | 167:84c0a372a020 | 97 | #define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL) |
AnnaBridge | 167:84c0a372a020 | 98 | #define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL) |
AnnaBridge | 167:84c0a372a020 | 99 | #define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL) |
AnnaBridge | 167:84c0a372a020 | 100 | #define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL) |
AnnaBridge | 167:84c0a372a020 | 101 | #define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL) |
AnnaBridge | 167:84c0a372a020 | 102 | #define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL) |
AnnaBridge | 167:84c0a372a020 | 103 | #define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL) |
AnnaBridge | 167:84c0a372a020 | 104 | #define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL) |
AnnaBridge | 167:84c0a372a020 | 105 | #define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL) |
AnnaBridge | 167:84c0a372a020 | 106 | #define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL) |
AnnaBridge | 167:84c0a372a020 | 107 | #define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL) |
AnnaBridge | 167:84c0a372a020 | 108 | #define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL) |
AnnaBridge | 167:84c0a372a020 | 109 | #define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL) |
AnnaBridge | 167:84c0a372a020 | 110 | #define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL) |
AnnaBridge | 167:84c0a372a020 | 111 | #define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL) |
AnnaBridge | 167:84c0a372a020 | 112 | #define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL) |
AnnaBridge | 167:84c0a372a020 | 113 | #define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL) |
AnnaBridge | 167:84c0a372a020 | 114 | #define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL) |
AnnaBridge | 167:84c0a372a020 | 115 | #define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL) |
AnnaBridge | 167:84c0a372a020 | 116 | #define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL) |
AnnaBridge | 167:84c0a372a020 | 117 | |
AnnaBridge | 167:84c0a372a020 | 118 | |
AnnaBridge | 167:84c0a372a020 | 119 | /* |
AnnaBridge | 167:84c0a372a020 | 120 | Field positions and masks for module AES. |
AnnaBridge | 167:84c0a372a020 | 121 | */ |
AnnaBridge | 167:84c0a372a020 | 122 | |
AnnaBridge | 167:84c0a372a020 | 123 | #define MXC_F_AES_CTRL_START_POS 0 |
AnnaBridge | 167:84c0a372a020 | 124 | #define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS)) |
AnnaBridge | 167:84c0a372a020 | 125 | #define MXC_F_AES_CTRL_CRYPT_MODE_POS 1 |
AnnaBridge | 167:84c0a372a020 | 126 | #define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS)) |
AnnaBridge | 167:84c0a372a020 | 127 | #define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2 |
AnnaBridge | 167:84c0a372a020 | 128 | #define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) |
AnnaBridge | 167:84c0a372a020 | 129 | #define MXC_F_AES_CTRL_KEY_SIZE_POS 3 |
AnnaBridge | 167:84c0a372a020 | 130 | #define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) |
AnnaBridge | 167:84c0a372a020 | 131 | #define MXC_F_AES_CTRL_INTEN_POS 5 |
AnnaBridge | 167:84c0a372a020 | 132 | #define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS)) |
AnnaBridge | 167:84c0a372a020 | 133 | #define MXC_F_AES_CTRL_INTFL_POS 6 |
AnnaBridge | 167:84c0a372a020 | 134 | #define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS)) |
AnnaBridge | 167:84c0a372a020 | 135 | #define MXC_F_AES_CTRL_LOAD_HW_KEY_POS 7 |
AnnaBridge | 167:84c0a372a020 | 136 | #define MXC_F_AES_CTRL_LOAD_HW_KEY ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_LOAD_HW_KEY_POS)) |
AnnaBridge | 167:84c0a372a020 | 137 | |
AnnaBridge | 167:84c0a372a020 | 138 | |
AnnaBridge | 167:84c0a372a020 | 139 | |
AnnaBridge | 167:84c0a372a020 | 140 | /* |
AnnaBridge | 167:84c0a372a020 | 141 | Field values and shifted values for module AES. |
AnnaBridge | 167:84c0a372a020 | 142 | */ |
AnnaBridge | 167:84c0a372a020 | 143 | |
AnnaBridge | 167:84c0a372a020 | 144 | #define MXC_V_AES_CTRL_ENCRYPT_MODE ((uint32_t)(0x00000000UL)) |
AnnaBridge | 167:84c0a372a020 | 145 | #define MXC_V_AES_CTRL_DECRYPT_MODE ((uint32_t)(0x00000001UL)) |
AnnaBridge | 167:84c0a372a020 | 146 | |
AnnaBridge | 167:84c0a372a020 | 147 | #define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) |
AnnaBridge | 167:84c0a372a020 | 148 | #define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) |
AnnaBridge | 167:84c0a372a020 | 149 | |
AnnaBridge | 167:84c0a372a020 | 150 | #define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(0x00000000UL)) |
AnnaBridge | 167:84c0a372a020 | 151 | #define MXC_V_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(0x00000001UL)) |
AnnaBridge | 167:84c0a372a020 | 152 | |
AnnaBridge | 167:84c0a372a020 | 153 | #define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) |
AnnaBridge | 167:84c0a372a020 | 154 | #define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) |
AnnaBridge | 167:84c0a372a020 | 155 | |
AnnaBridge | 167:84c0a372a020 | 156 | #define MXC_V_AES_CTRL_KEY_SIZE_128 ((uint32_t)(0x00000000UL)) |
AnnaBridge | 167:84c0a372a020 | 157 | #define MXC_V_AES_CTRL_KEY_SIZE_192 ((uint32_t)(0x00000001UL)) |
AnnaBridge | 167:84c0a372a020 | 158 | #define MXC_V_AES_CTRL_KEY_SIZE_256 ((uint32_t)(0x00000002UL)) |
AnnaBridge | 167:84c0a372a020 | 159 | |
AnnaBridge | 167:84c0a372a020 | 160 | #define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS)) |
AnnaBridge | 167:84c0a372a020 | 161 | #define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS)) |
AnnaBridge | 167:84c0a372a020 | 162 | #define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS)) |
AnnaBridge | 167:84c0a372a020 | 163 | |
AnnaBridge | 167:84c0a372a020 | 164 | |
AnnaBridge | 167:84c0a372a020 | 165 | |
AnnaBridge | 167:84c0a372a020 | 166 | #ifdef __cplusplus |
AnnaBridge | 167:84c0a372a020 | 167 | } |
AnnaBridge | 167:84c0a372a020 | 168 | #endif |
AnnaBridge | 167:84c0a372a020 | 169 | |
AnnaBridge | 167:84c0a372a020 | 170 | #endif /* _MXC_AES_REGS_H_ */ |
AnnaBridge | 167:84c0a372a020 | 171 |