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TARGET_RDA5981X/TOOLCHAIN_GCC_ARM/RDA5991H.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 172:65be27845400 | 1 | /****************************************************************************** |
AnnaBridge | 172:65be27845400 | 2 | * @file RDA5991H.h |
AnnaBridge | 172:65be27845400 | 3 | * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for |
AnnaBridge | 172:65be27845400 | 4 | * RDA RDA5991H Device Series |
AnnaBridge | 172:65be27845400 | 5 | * @version: V1.09 |
AnnaBridge | 172:65be27845400 | 6 | * @date: 07. June 2018 |
AnnaBridge | 172:65be27845400 | 7 | * |
AnnaBridge | 172:65be27845400 | 8 | * @note |
AnnaBridge | 172:65be27845400 | 9 | * Copyright (C) 2009 ARM Limited. All rights reserved. |
AnnaBridge | 172:65be27845400 | 10 | * |
AnnaBridge | 172:65be27845400 | 11 | * @par |
AnnaBridge | 172:65be27845400 | 12 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
AnnaBridge | 172:65be27845400 | 13 | * processor based microcontrollers. This file can be freely distributed |
AnnaBridge | 172:65be27845400 | 14 | * within development tools that are supporting such ARM based processors. |
AnnaBridge | 172:65be27845400 | 15 | * |
AnnaBridge | 172:65be27845400 | 16 | * @par |
AnnaBridge | 172:65be27845400 | 17 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
AnnaBridge | 172:65be27845400 | 18 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
AnnaBridge | 172:65be27845400 | 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
AnnaBridge | 172:65be27845400 | 20 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
AnnaBridge | 172:65be27845400 | 21 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
AnnaBridge | 172:65be27845400 | 22 | * |
AnnaBridge | 172:65be27845400 | 23 | ******************************************************************************/ |
AnnaBridge | 172:65be27845400 | 24 | |
AnnaBridge | 172:65be27845400 | 25 | |
AnnaBridge | 172:65be27845400 | 26 | #ifndef __RDA5991H_H__ |
AnnaBridge | 172:65be27845400 | 27 | #define __RDA5991H_H__ |
AnnaBridge | 172:65be27845400 | 28 | |
AnnaBridge | 172:65be27845400 | 29 | /* |
AnnaBridge | 172:65be27845400 | 30 | * ========================================================================== |
AnnaBridge | 172:65be27845400 | 31 | * ---------- Interrupt Number Definition ----------------------------------- |
AnnaBridge | 172:65be27845400 | 32 | * ========================================================================== |
AnnaBridge | 172:65be27845400 | 33 | */ |
AnnaBridge | 172:65be27845400 | 34 | |
AnnaBridge | 172:65be27845400 | 35 | typedef enum IRQn |
AnnaBridge | 172:65be27845400 | 36 | { |
AnnaBridge | 172:65be27845400 | 37 | /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ |
AnnaBridge | 172:65be27845400 | 38 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
AnnaBridge | 172:65be27845400 | 39 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ |
AnnaBridge | 172:65be27845400 | 40 | BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ |
AnnaBridge | 172:65be27845400 | 41 | UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ |
AnnaBridge | 172:65be27845400 | 42 | SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ |
AnnaBridge | 172:65be27845400 | 43 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ |
AnnaBridge | 172:65be27845400 | 44 | PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ |
AnnaBridge | 172:65be27845400 | 45 | SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ |
AnnaBridge | 172:65be27845400 | 46 | |
AnnaBridge | 172:65be27845400 | 47 | /****** RDA5991H Specific Interrupt Numbers ******************************************************/ |
AnnaBridge | 172:65be27845400 | 48 | SPIFLASH_IRQn = 0, /*!< SPI Flash Interrupt */ |
AnnaBridge | 172:65be27845400 | 49 | PTA_IRQn = 1, /*!< PTA Interrupt */ |
AnnaBridge | 172:65be27845400 | 50 | SDIO_IRQn = 2, /*!< SDIO Interrupt */ |
AnnaBridge | 172:65be27845400 | 51 | USBDMA_IRQn = 3, /*!< USBDMA Interrupt */ |
AnnaBridge | 172:65be27845400 | 52 | USB_IRQn = 4, /*!< USB Interrupt */ |
AnnaBridge | 172:65be27845400 | 53 | GPIO_IRQn = 5, /*!< GPIO Interrupt */ |
AnnaBridge | 172:65be27845400 | 54 | TIMER_IRQn = 6, /*!< Timer Interrupt */ |
AnnaBridge | 172:65be27845400 | 55 | UART0_IRQn = 7, /*!< UART0 Interrupt */ |
AnnaBridge | 172:65be27845400 | 56 | MACHW_IRQn = 8, /*!< MAC Hardware Interrupt */ |
AnnaBridge | 172:65be27845400 | 57 | UART1_IRQn = 9, /*!< UART1 Interrupt */ |
AnnaBridge | 172:65be27845400 | 58 | AHBDMA_IRQn = 10, /*!< AHBDMA Interrupt */ |
AnnaBridge | 172:65be27845400 | 59 | PSRAM_IRQn = 11, /*!< PSRAM Interrupt */ |
AnnaBridge | 172:65be27845400 | 60 | SDMMC_IRQn = 12, /*!< SDMMC Interrupt */ |
AnnaBridge | 172:65be27845400 | 61 | EXIF_IRQn = 13, /*!< EXIF Interrupt */ |
AnnaBridge | 172:65be27845400 | 62 | I2C_IRQn = 14 /*!< I2C Interrupt */ |
AnnaBridge | 172:65be27845400 | 63 | } IRQn_Type; |
AnnaBridge | 172:65be27845400 | 64 | |
AnnaBridge | 172:65be27845400 | 65 | |
AnnaBridge | 172:65be27845400 | 66 | /* |
AnnaBridge | 172:65be27845400 | 67 | * ========================================================================== |
AnnaBridge | 172:65be27845400 | 68 | * ----------- Processor and Core Peripheral Section ------------------------ |
AnnaBridge | 172:65be27845400 | 69 | * ========================================================================== |
AnnaBridge | 172:65be27845400 | 70 | */ |
AnnaBridge | 172:65be27845400 | 71 | |
AnnaBridge | 172:65be27845400 | 72 | /* Configuration of the Cortex-M4 Processor and Core Peripherals */ |
AnnaBridge | 172:65be27845400 | 73 | #define __MPU_PRESENT 0 /*!< MPU present or not */ |
AnnaBridge | 172:65be27845400 | 74 | #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ |
AnnaBridge | 172:65be27845400 | 75 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
AnnaBridge | 172:65be27845400 | 76 | #define __FPU_PRESENT 1 /*!< FPU present */ |
AnnaBridge | 172:65be27845400 | 77 | |
AnnaBridge | 172:65be27845400 | 78 | |
AnnaBridge | 172:65be27845400 | 79 | #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ |
AnnaBridge | 172:65be27845400 | 80 | #include "system_RDA5991H.h" /* System Header */ |
AnnaBridge | 172:65be27845400 | 81 | |
AnnaBridge | 172:65be27845400 | 82 | |
AnnaBridge | 172:65be27845400 | 83 | /******************************************************************************/ |
AnnaBridge | 172:65be27845400 | 84 | /* Device Specific Peripheral registers structures */ |
AnnaBridge | 172:65be27845400 | 85 | /******************************************************************************/ |
AnnaBridge | 172:65be27845400 | 86 | |
AnnaBridge | 172:65be27845400 | 87 | #if defined ( __CC_ARM ) |
AnnaBridge | 172:65be27845400 | 88 | #pragma anon_unions |
AnnaBridge | 172:65be27845400 | 89 | #endif |
AnnaBridge | 172:65be27845400 | 90 | |
AnnaBridge | 172:65be27845400 | 91 | /*------------- System Control Unit (SCU) ------------------------------------*/ |
AnnaBridge | 172:65be27845400 | 92 | typedef struct |
AnnaBridge | 172:65be27845400 | 93 | { |
AnnaBridge | 172:65be27845400 | 94 | __IO uint32_t CLKGATE0; /* 0x00 : Clock Gating 0 */ |
AnnaBridge | 172:65be27845400 | 95 | __IO uint32_t PWRCTRL; /* 0x04 : Power Control */ |
AnnaBridge | 172:65be27845400 | 96 | __IO uint32_t CLKGATE1; /* 0x08 : Clock Gating 1 */ |
AnnaBridge | 172:65be27845400 | 97 | __IO uint32_t CLKGATE2; /* 0x0C : Clock Gating 2 */ |
AnnaBridge | 172:65be27845400 | 98 | __IO uint32_t RESETCTRL; /* 0x10 : Power Control */ |
AnnaBridge | 172:65be27845400 | 99 | __IO uint32_t CLKGATE3; /* 0x14 : Clock Gating 3 */ |
AnnaBridge | 172:65be27845400 | 100 | __IO uint32_t CORECFG; /* 0x18 : Core Config */ |
AnnaBridge | 172:65be27845400 | 101 | __IO uint32_t CPUCFG; /* 0x1C : CPU Config */ |
AnnaBridge | 172:65be27845400 | 102 | __IO uint32_t FTMRINITVAL; /* 0x20 : Free Timer Initial Value */ |
AnnaBridge | 172:65be27845400 | 103 | __IO uint32_t FTMRTS; /* 0x24 : Free Timer Timestamp */ |
AnnaBridge | 172:65be27845400 | 104 | __IO uint32_t CLKGATEBP; /* 0x28 : Clock Gating Bypass */ |
AnnaBridge | 172:65be27845400 | 105 | uint32_t RESERVED0[2]; |
AnnaBridge | 172:65be27845400 | 106 | __IO uint32_t PWMCFG; /* 0x34 : PWM Config */ |
AnnaBridge | 172:65be27845400 | 107 | __IO uint32_t FUN0WAKEVAL; /* 0x38 : SDIO Func0 Wake Val */ |
AnnaBridge | 172:65be27845400 | 108 | __IO uint32_t FUN1WAKEVAL; /* 0x3C : SDIO Func1 Wake Val */ |
AnnaBridge | 172:65be27845400 | 109 | __IO uint32_t BOOTJUMPADDR; /* 0x40 : Boot Jump Addr */ |
AnnaBridge | 172:65be27845400 | 110 | __IO uint32_t SDIOINTVAL; /* 0x44 : SDIO Int Val */ |
AnnaBridge | 172:65be27845400 | 111 | __IO uint32_t I2SCLKDIV; /* 0x48 : I2S Clock Divider */ |
AnnaBridge | 172:65be27845400 | 112 | __IO uint32_t BOOTJUMPADDRCFG; /* 0x4C : Boot Jump Addr Config */ |
AnnaBridge | 172:65be27845400 | 113 | __IO uint32_t FTMRPREVAL; /* 0x50 : Free Timer Prescale Init Val*/ |
AnnaBridge | 172:65be27845400 | 114 | __IO uint32_t PWROPENCFG; /* 0x54 : Power Open Config */ |
AnnaBridge | 172:65be27845400 | 115 | __IO uint32_t PWRCLOSECFG; /* 0x58 : Power Close Config */ |
AnnaBridge | 172:65be27845400 | 116 | } RDA_SCU_TypeDef; |
AnnaBridge | 172:65be27845400 | 117 | |
AnnaBridge | 172:65be27845400 | 118 | /*------------- Timer0 (TIM0) ------------------------------------------------*/ |
AnnaBridge | 172:65be27845400 | 119 | typedef struct |
AnnaBridge | 172:65be27845400 | 120 | { |
AnnaBridge | 172:65be27845400 | 121 | __IO uint32_t LDCNT; /* 0x00 : Timer Load Count Register */ |
AnnaBridge | 172:65be27845400 | 122 | __I uint32_t CVAL; /* 0x04 : Current Timer Value Register*/ |
AnnaBridge | 172:65be27845400 | 123 | __IO uint32_t TCTRL; /* 0x08 : Timer Control Register */ |
AnnaBridge | 172:65be27845400 | 124 | __I uint32_t INTCLR; /* 0x0C : Interrupt Clear Register */ |
AnnaBridge | 172:65be27845400 | 125 | } RDA_TIM0_TypeDef; |
AnnaBridge | 172:65be27845400 | 126 | |
AnnaBridge | 172:65be27845400 | 127 | /*------------- Timer1 (TIM1) ------------------------------------------------*/ |
AnnaBridge | 172:65be27845400 | 128 | typedef struct |
AnnaBridge | 172:65be27845400 | 129 | { |
AnnaBridge | 172:65be27845400 | 130 | __IO uint32_t TCTRL; /* 0x00 : Timer Control Register */ |
AnnaBridge | 172:65be27845400 | 131 | uint32_t RESERVED0[2]; |
AnnaBridge | 172:65be27845400 | 132 | __IO uint32_t LDCNT; /* 0x0C : Timer Load Count Register */ |
AnnaBridge | 172:65be27845400 | 133 | __I uint32_t CVAL; /* 0x10 : Current Timer Value Register*/ |
AnnaBridge | 172:65be27845400 | 134 | uint32_t RESERVED1; |
AnnaBridge | 172:65be27845400 | 135 | __I uint32_t INTCLR; /* 0x18 : Interrupt Clear Register */ |
AnnaBridge | 172:65be27845400 | 136 | } RDA_TIM1_TypeDef; |
AnnaBridge | 172:65be27845400 | 137 | |
AnnaBridge | 172:65be27845400 | 138 | /*------------- Timer Interrupt Status (TIMINTST) ----------------------------*/ |
AnnaBridge | 172:65be27845400 | 139 | typedef struct |
AnnaBridge | 172:65be27845400 | 140 | { |
AnnaBridge | 172:65be27845400 | 141 | __I uint32_t INTST; /* 0x00 : Timer Int Stat Register */ |
AnnaBridge | 172:65be27845400 | 142 | } RDA_TIMINTST_TypeDef; |
AnnaBridge | 172:65be27845400 | 143 | |
AnnaBridge | 172:65be27845400 | 144 | /*------------- General Purpose Input/Output (GPIO) --------------------------*/ |
AnnaBridge | 172:65be27845400 | 145 | typedef struct |
AnnaBridge | 172:65be27845400 | 146 | { |
AnnaBridge | 172:65be27845400 | 147 | __IO uint32_t CTRL; /* 0x00 : GPIO Control */ |
AnnaBridge | 172:65be27845400 | 148 | uint32_t RESERVED0; |
AnnaBridge | 172:65be27845400 | 149 | __IO uint32_t DOUT; /* 0x08 : GPIO Data Output */ |
AnnaBridge | 172:65be27845400 | 150 | __IO uint32_t DIN; /* 0x0C : GPIO Data Input */ |
AnnaBridge | 172:65be27845400 | 151 | __IO uint32_t DIR; /* 0x10 : GPIO Direction */ |
AnnaBridge | 172:65be27845400 | 152 | __IO uint32_t SLEW0; /* 0x14 : GPIO Slew Config 0 */ |
AnnaBridge | 172:65be27845400 | 153 | __IO uint32_t SLEWIOMUX; /* 0x18 : GPIO IOMUX Slew Config */ |
AnnaBridge | 172:65be27845400 | 154 | __IO uint32_t INTCTRL; /* 0x1C : GPIO Interrupt Control */ |
AnnaBridge | 172:65be27845400 | 155 | __IO uint32_t IFCTRL; /* 0x20 : Interface Control */ |
AnnaBridge | 172:65be27845400 | 156 | __IO uint32_t SLEW1; /* 0x24 : GPIO Slew Config 1 */ |
AnnaBridge | 172:65be27845400 | 157 | __IO uint32_t REVID; /* 0x28 : ASIC Reversion ID */ |
AnnaBridge | 172:65be27845400 | 158 | __IO uint32_t LPOSEL; /* 0x2C : LPO Select */ |
AnnaBridge | 172:65be27845400 | 159 | uint32_t RESERVED1; |
AnnaBridge | 172:65be27845400 | 160 | __IO uint32_t INTSEL; /* 0x34 : GPIO Interrupt Select */ |
AnnaBridge | 172:65be27845400 | 161 | uint32_t RESERVED2; |
AnnaBridge | 172:65be27845400 | 162 | __IO uint32_t SDIOCFG; /* 0x3C : SDIO Config */ |
AnnaBridge | 172:65be27845400 | 163 | __IO uint32_t MEMCFG; /* 0x40 : Memory Config */ |
AnnaBridge | 172:65be27845400 | 164 | __IO uint32_t IOMUXCTRL[8]; /* 0x44 - 0x60 : IOMUX Control */ |
AnnaBridge | 172:65be27845400 | 165 | __IO uint32_t PCCTRL; /* 0x64 : Pulse Counter Control */ |
AnnaBridge | 172:65be27845400 | 166 | } RDA_GPIO_TypeDef; |
AnnaBridge | 172:65be27845400 | 167 | |
AnnaBridge | 172:65be27845400 | 168 | /*------------- Inter-Integrated Circuit 0 (I2C0) ----------------------------*/ |
AnnaBridge | 172:65be27845400 | 169 | typedef struct |
AnnaBridge | 172:65be27845400 | 170 | { |
AnnaBridge | 172:65be27845400 | 171 | __IO uint32_t CR0; /* 0x00 : Control Register 0 */ |
AnnaBridge | 172:65be27845400 | 172 | __I uint32_t SR; /* 0x04 : Status Register */ |
AnnaBridge | 172:65be27845400 | 173 | __IO uint32_t DR; /* 0x08 : TX/RX Data Register */ |
AnnaBridge | 172:65be27845400 | 174 | __O uint32_t CMD; /* 0x0C : Command Register */ |
AnnaBridge | 172:65be27845400 | 175 | __O uint32_t ICR; /* 0x10 : Interrupt Clear Register */ |
AnnaBridge | 172:65be27845400 | 176 | __IO uint32_t CR1; /* 0x14 : Control Register 1 */ |
AnnaBridge | 172:65be27845400 | 177 | } RDA_I2C0_TypeDef; |
AnnaBridge | 172:65be27845400 | 178 | |
AnnaBridge | 172:65be27845400 | 179 | /*------------- Pulse Width Modulator (PWM) ----------------------------------*/ |
AnnaBridge | 172:65be27845400 | 180 | typedef struct |
AnnaBridge | 172:65be27845400 | 181 | { |
AnnaBridge | 172:65be27845400 | 182 | __IO uint32_t PWTCFG; /* 0x00 : PWT Config Register */ |
AnnaBridge | 172:65be27845400 | 183 | __IO uint32_t LPGCFG; /* 0x04 : LPG Config Register */ |
AnnaBridge | 172:65be27845400 | 184 | __IO uint32_t PWL0CFG; /* 0x08 : PWL0 Config Register */ |
AnnaBridge | 172:65be27845400 | 185 | __IO uint32_t PWL1CFG; /* 0x0C : PWL1 Config Register */ |
AnnaBridge | 172:65be27845400 | 186 | __IO uint32_t CLKR; /* 0x10 : Clock Config Register */ |
AnnaBridge | 172:65be27845400 | 187 | } RDA_PWM_TypeDef; |
AnnaBridge | 172:65be27845400 | 188 | |
AnnaBridge | 172:65be27845400 | 189 | /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ |
AnnaBridge | 172:65be27845400 | 190 | typedef struct |
AnnaBridge | 172:65be27845400 | 191 | { |
AnnaBridge | 172:65be27845400 | 192 | union { |
AnnaBridge | 172:65be27845400 | 193 | __I uint32_t RBR; /* 0x00 : UART Receive buffer register */ |
AnnaBridge | 172:65be27845400 | 194 | __O uint32_t THR; /* 0x00 : UART Transmit holding register */ |
AnnaBridge | 172:65be27845400 | 195 | __IO uint32_t DLL; /* 0x00 : UART Divisor latch(low) */ |
AnnaBridge | 172:65be27845400 | 196 | }; |
AnnaBridge | 172:65be27845400 | 197 | union { |
AnnaBridge | 172:65be27845400 | 198 | __IO uint32_t DLH; /* 0x04 : UART Divisor latch(high) */ |
AnnaBridge | 172:65be27845400 | 199 | __IO uint32_t IER; /* 0x04 : UART Interrupt enable register */ |
AnnaBridge | 172:65be27845400 | 200 | }; |
AnnaBridge | 172:65be27845400 | 201 | union { |
AnnaBridge | 172:65be27845400 | 202 | __I uint32_t IIR; /* 0x08 : UART Interrupt id register */ |
AnnaBridge | 172:65be27845400 | 203 | __O uint32_t FCR; /* 0x08 : UART Fifo control register */ |
AnnaBridge | 172:65be27845400 | 204 | }; |
AnnaBridge | 172:65be27845400 | 205 | __IO uint32_t LCR; /* 0x0C : UART Line control register */ |
AnnaBridge | 172:65be27845400 | 206 | __IO uint32_t MCR; /* 0x10 : UART Moderm control register */ |
AnnaBridge | 172:65be27845400 | 207 | __I uint32_t LSR; /* 0x14 : UART Line status register */ |
AnnaBridge | 172:65be27845400 | 208 | __I uint32_t MSR; /* 0x18 : UART Moderm status register */ |
AnnaBridge | 172:65be27845400 | 209 | __IO uint32_t SCR; /* 0x1C : UART Scratchpad register */ |
AnnaBridge | 172:65be27845400 | 210 | __I uint32_t FSR; /* 0x20 : UART FIFO status register */ |
AnnaBridge | 172:65be27845400 | 211 | __IO uint32_t FRR; /* 0x24 : UART FIFO tx/rx trigger resiger */ |
AnnaBridge | 172:65be27845400 | 212 | __IO uint32_t DL2; /* 0x28 : UART Baud rate adjust register */ |
AnnaBridge | 172:65be27845400 | 213 | __I uint32_t RESERVED0[4]; |
AnnaBridge | 172:65be27845400 | 214 | __I uint32_t BAUD; /* 0x3C : UART Auto baud counter */ |
AnnaBridge | 172:65be27845400 | 215 | __I uint32_t DL_SLOW; /* 0x40 : UART Divisor Adjust when slow clk */ |
AnnaBridge | 172:65be27845400 | 216 | __I uint32_t DL_FAST; /* 0x44 : UART Divisor Adjust when fast clk */ |
AnnaBridge | 172:65be27845400 | 217 | } RDA_UART_TypeDef; |
AnnaBridge | 172:65be27845400 | 218 | |
AnnaBridge | 172:65be27845400 | 219 | /*------------- Serial Peripheral Interface (SPI) ----------------------------*/ |
AnnaBridge | 172:65be27845400 | 220 | typedef struct |
AnnaBridge | 172:65be27845400 | 221 | { |
AnnaBridge | 172:65be27845400 | 222 | __IO uint32_t CFG; |
AnnaBridge | 172:65be27845400 | 223 | __IO uint32_t D0CMD; |
AnnaBridge | 172:65be27845400 | 224 | __IO uint32_t D1CMD; |
AnnaBridge | 172:65be27845400 | 225 | } RDA_SPI_TypeDef; |
AnnaBridge | 172:65be27845400 | 226 | |
AnnaBridge | 172:65be27845400 | 227 | /*------------- Integrated Interchip Sound (I2S) -----------------------------*/ |
AnnaBridge | 172:65be27845400 | 228 | typedef struct |
AnnaBridge | 172:65be27845400 | 229 | { |
AnnaBridge | 172:65be27845400 | 230 | __IO uint32_t CFG; |
AnnaBridge | 172:65be27845400 | 231 | __IO uint32_t DOUTWR; |
AnnaBridge | 172:65be27845400 | 232 | __I uint32_t DINRD; |
AnnaBridge | 172:65be27845400 | 233 | } RDA_I2S_TypeDef; |
AnnaBridge | 172:65be27845400 | 234 | |
AnnaBridge | 172:65be27845400 | 235 | /*------------- External Interface (EXIF) ------------------------------------*/ |
AnnaBridge | 172:65be27845400 | 236 | typedef struct |
AnnaBridge | 172:65be27845400 | 237 | { |
AnnaBridge | 172:65be27845400 | 238 | RDA_SPI_TypeDef SPI0; /* 0x00 - 0x08 : SPI0 registers group */ |
AnnaBridge | 172:65be27845400 | 239 | RDA_I2S_TypeDef I2S; /* 0x0C - 0x14 : I2S registers group */ |
AnnaBridge | 172:65be27845400 | 240 | __IO uint32_t MISCSTCFG; /* 0x18 : Misc status config register */ |
AnnaBridge | 172:65be27845400 | 241 | __IO uint32_t SPI1CTRL; /* 0x1C : SPI1 Control register */ |
AnnaBridge | 172:65be27845400 | 242 | uint32_t RESERVED0[4]; |
AnnaBridge | 172:65be27845400 | 243 | __IO uint32_t MISCINTCFG; /* 0x30 : Misc int config register */ |
AnnaBridge | 172:65be27845400 | 244 | __IO uint32_t MBB2W; /* 0x34 : BT to WiFi mailbox register */ |
AnnaBridge | 172:65be27845400 | 245 | __IO uint32_t MBW2B; /* 0x38 : WiFi to BT mailbox register */ |
AnnaBridge | 172:65be27845400 | 246 | __IO uint32_t MISCCFG; /* 0x3C : Misc configure register */ |
AnnaBridge | 172:65be27845400 | 247 | __IO uint32_t PWM0CFG; /* 0x40 : PWM0 configure register */ |
AnnaBridge | 172:65be27845400 | 248 | __IO uint32_t PWM1CFG; /* 0x44 : PWM1 configure register */ |
AnnaBridge | 172:65be27845400 | 249 | __IO uint32_t PWM2CFG; /* 0x48 : PWM2 configure register */ |
AnnaBridge | 172:65be27845400 | 250 | __IO uint32_t PWM3CFG; /* 0x4C : PWM3 configure register */ |
AnnaBridge | 172:65be27845400 | 251 | } RDA_EXIF_TypeDef; |
AnnaBridge | 172:65be27845400 | 252 | |
AnnaBridge | 172:65be27845400 | 253 | /*------------- Watchdog Timer (WDT) -----------------------------------------*/ |
AnnaBridge | 172:65be27845400 | 254 | typedef struct |
AnnaBridge | 172:65be27845400 | 255 | { |
AnnaBridge | 172:65be27845400 | 256 | __IO uint32_t WDTCFG; |
AnnaBridge | 172:65be27845400 | 257 | } RDA_WDT_TypeDef; |
AnnaBridge | 172:65be27845400 | 258 | |
AnnaBridge | 172:65be27845400 | 259 | /*------------- Pin Configure (PINCFG) ---------------------------------------*/ |
AnnaBridge | 172:65be27845400 | 260 | typedef struct |
AnnaBridge | 172:65be27845400 | 261 | { |
AnnaBridge | 172:65be27845400 | 262 | union { |
AnnaBridge | 172:65be27845400 | 263 | __IO uint32_t IOMUXCTRL[8]; |
AnnaBridge | 172:65be27845400 | 264 | struct { |
AnnaBridge | 172:65be27845400 | 265 | __IO uint32_t MUX0; |
AnnaBridge | 172:65be27845400 | 266 | __IO uint32_t MUX1; |
AnnaBridge | 172:65be27845400 | 267 | __IO uint32_t MODE0; |
AnnaBridge | 172:65be27845400 | 268 | __IO uint32_t MODE1; |
AnnaBridge | 172:65be27845400 | 269 | __IO uint32_t MUX2; |
AnnaBridge | 172:65be27845400 | 270 | __IO uint32_t MUX3; |
AnnaBridge | 172:65be27845400 | 271 | __IO uint32_t MODE2; |
AnnaBridge | 172:65be27845400 | 272 | __IO uint32_t MODE3; |
AnnaBridge | 172:65be27845400 | 273 | }; |
AnnaBridge | 172:65be27845400 | 274 | }; |
AnnaBridge | 172:65be27845400 | 275 | } RDA_PINCFG_TypeDef; |
AnnaBridge | 172:65be27845400 | 276 | |
AnnaBridge | 172:65be27845400 | 277 | /*------------- AHB Direct Memory Access (DMA) -------------------------------*/ |
AnnaBridge | 172:65be27845400 | 278 | typedef struct |
AnnaBridge | 172:65be27845400 | 279 | { |
AnnaBridge | 172:65be27845400 | 280 | __IO uint32_t dma_ctrl; /* 0x00 : DMA ctrl */ |
AnnaBridge | 172:65be27845400 | 281 | __IO uint32_t dma_src; /* 0x04 : DMA src */ |
AnnaBridge | 172:65be27845400 | 282 | __IO uint32_t dma_dst; /* 0x08 : DMA dst */ |
AnnaBridge | 172:65be27845400 | 283 | __IO uint32_t dma_len; /* 0x0c : DMA len */ |
AnnaBridge | 172:65be27845400 | 284 | __IO uint32_t crc_gen; /* 0x10 : CRC gen */ |
AnnaBridge | 172:65be27845400 | 285 | __IO uint32_t dma_func_ctrl; /* 0x14 : DMA func ctrl */ |
AnnaBridge | 172:65be27845400 | 286 | __IO uint32_t aes_key0; /* 0x18 : AES key 0 */ |
AnnaBridge | 172:65be27845400 | 287 | __IO uint32_t aes_key1; /* 0x1c : AES key 1 */ |
AnnaBridge | 172:65be27845400 | 288 | __IO uint32_t aes_key2; /* 0x20 : AES key 2 */ |
AnnaBridge | 172:65be27845400 | 289 | __IO uint32_t aes_key3; /* 0x24 : AES key 2 */ |
AnnaBridge | 172:65be27845400 | 290 | __IO uint32_t aes_iv0; /* 0x28 : AES iv 0 */ |
AnnaBridge | 172:65be27845400 | 291 | __IO uint32_t aes_iv1; /* 0x2c : AES iv 1 */ |
AnnaBridge | 172:65be27845400 | 292 | __IO uint32_t aes_iv2; /* 0x30 : AES iv 2 */ |
AnnaBridge | 172:65be27845400 | 293 | __IO uint32_t aes_iv3; /* 0x34 : AES iv 2 */ |
AnnaBridge | 172:65be27845400 | 294 | __IO uint32_t aes_mode; /* 0x38 : AES mode */ |
AnnaBridge | 172:65be27845400 | 295 | __IO uint32_t cios_ctrl; /* 0x3c : cios ctrl */ |
AnnaBridge | 172:65be27845400 | 296 | __IO uint32_t cios_reg0; /* 0x40 : cios reg 0 */ |
AnnaBridge | 172:65be27845400 | 297 | __IO uint32_t crc_init_val; /* 0x44 : CRC init val */ |
AnnaBridge | 172:65be27845400 | 298 | __IO uint32_t crc_out_xorval; /* 0x48 : CRC out xorval */ |
AnnaBridge | 172:65be27845400 | 299 | __I uint32_t crc_out_val; /* 0x4c : CRC out val */ |
AnnaBridge | 172:65be27845400 | 300 | uint32_t RESERVED0[12]; |
AnnaBridge | 172:65be27845400 | 301 | __IO uint32_t dma_int_out; /* 0x80 : DMA int out */ |
AnnaBridge | 172:65be27845400 | 302 | __IO uint32_t dma_int_mask; /* 0x84 : DMA int mask */ |
AnnaBridge | 172:65be27845400 | 303 | uint32_t RESERVED1[478]; |
AnnaBridge | 172:65be27845400 | 304 | __IO uint32_t cios_data_base; /* 0x800 : CIOS data base */ |
AnnaBridge | 172:65be27845400 | 305 | } RDA_DMACFG_TypeDef; |
AnnaBridge | 172:65be27845400 | 306 | |
AnnaBridge | 172:65be27845400 | 307 | /*------------- Random Number Generator (RNG) --------------------------------*/ |
AnnaBridge | 172:65be27845400 | 308 | typedef struct |
AnnaBridge | 172:65be27845400 | 309 | { |
AnnaBridge | 172:65be27845400 | 310 | __IO uint32_t TCTRL; /* 0x00 : TRNG ctrl */ |
AnnaBridge | 172:65be27845400 | 311 | __IO uint32_t PCTRL; /* 0x04 : PRNG ctrl */ |
AnnaBridge | 172:65be27845400 | 312 | __IO uint32_t PSEED; /* 0x08 : PRNG seed */ |
AnnaBridge | 172:65be27845400 | 313 | __IO uint32_t PTMRINIT; /* 0x0C : PRNG timer init */ |
AnnaBridge | 172:65be27845400 | 314 | __I uint32_t PTMR; /* 0x10 : PRNG timer */ |
AnnaBridge | 172:65be27845400 | 315 | __I uint32_t TD0; /* 0x14 : TRNG data 0 */ |
AnnaBridge | 172:65be27845400 | 316 | __I uint32_t TD0MSK; /* 0x18 : TRNG data 0 mask */ |
AnnaBridge | 172:65be27845400 | 317 | __I uint32_t TD1; /* 0x1C : TRNG data 1 */ |
AnnaBridge | 172:65be27845400 | 318 | __I uint32_t TD1MSK; /* 0x20 : TRNG data 1 mask */ |
AnnaBridge | 172:65be27845400 | 319 | __I uint32_t PD; /* 0x24 : PRNG data */ |
AnnaBridge | 172:65be27845400 | 320 | __I uint32_t THC; /* 0x28 : TRNG h/c value */ |
AnnaBridge | 172:65be27845400 | 321 | } RDA_RNG_TypeDef; |
AnnaBridge | 172:65be27845400 | 322 | |
AnnaBridge | 172:65be27845400 | 323 | /*------------- Universal Serial Bus (USB) -------------------------------------------*/ |
AnnaBridge | 172:65be27845400 | 324 | typedef struct |
AnnaBridge | 172:65be27845400 | 325 | { |
AnnaBridge | 172:65be27845400 | 326 | struct { |
AnnaBridge | 172:65be27845400 | 327 | __IO uint8_t FUNC_ADDR; /* 0x00: Function Address */ |
AnnaBridge | 172:65be27845400 | 328 | __IO uint8_t POWER; /* 0x01: Power */ |
AnnaBridge | 172:65be27845400 | 329 | __IO uint16_t INTRTX; /* 0x02-0x03: IntrTx */ |
AnnaBridge | 172:65be27845400 | 330 | }; |
AnnaBridge | 172:65be27845400 | 331 | struct { |
AnnaBridge | 172:65be27845400 | 332 | __IO uint16_t INTRRX; /* 0x04-0x05: IntrRx */ |
AnnaBridge | 172:65be27845400 | 333 | __IO uint16_t INTRTXEN; /* 0x06-0x07: IntrTx Enable */ |
AnnaBridge | 172:65be27845400 | 334 | }; |
AnnaBridge | 172:65be27845400 | 335 | struct { |
AnnaBridge | 172:65be27845400 | 336 | __IO uint16_t INTRRXEN; /* 0x08-0x09: IntrRx Enable */ |
AnnaBridge | 172:65be27845400 | 337 | __IO uint8_t INTR; /* 0x0a: Interrupt */ |
AnnaBridge | 172:65be27845400 | 338 | __IO uint8_t INTREN; /* 0x0b: Intr Enable */ |
AnnaBridge | 172:65be27845400 | 339 | }; |
AnnaBridge | 172:65be27845400 | 340 | struct { |
AnnaBridge | 172:65be27845400 | 341 | __IO uint16_t FRAMENUM; /* 0x0c-0x0d: Frame Number */ |
AnnaBridge | 172:65be27845400 | 342 | __IO uint8_t EPIDX; /* 0x0e: Endpoint Index */ |
AnnaBridge | 172:65be27845400 | 343 | __IO uint8_t TESTMODE; /* 0x0f: Test Mode */ |
AnnaBridge | 172:65be27845400 | 344 | }; |
AnnaBridge | 172:65be27845400 | 345 | struct { |
AnnaBridge | 172:65be27845400 | 346 | __IO uint16_t TXMAXPKTSIZE; /* 0x10-0x11: Tx Max Packet Size */ |
AnnaBridge | 172:65be27845400 | 347 | union { |
AnnaBridge | 172:65be27845400 | 348 | __IO uint16_t CSR0; /* 0x12-0x13: CSR0 */ |
AnnaBridge | 172:65be27845400 | 349 | __IO uint16_t TXCSR; /* 0x12-0x13: CSR0 */ |
AnnaBridge | 172:65be27845400 | 350 | }; |
AnnaBridge | 172:65be27845400 | 351 | }; |
AnnaBridge | 172:65be27845400 | 352 | struct { |
AnnaBridge | 172:65be27845400 | 353 | __IO uint16_t RXMAXPKTSIZE; /* 0x14-0x15: Rx Max Packet Size */ |
AnnaBridge | 172:65be27845400 | 354 | __IO uint16_t RXCSR; /* 0x16-0x17: Rx CSR */ |
AnnaBridge | 172:65be27845400 | 355 | }; |
AnnaBridge | 172:65be27845400 | 356 | struct { |
AnnaBridge | 172:65be27845400 | 357 | union { |
AnnaBridge | 172:65be27845400 | 358 | __IO uint16_t RXCOUNT0; /* 0x18-0x19: Rx Counter of EP0 */ |
AnnaBridge | 172:65be27845400 | 359 | __IO uint16_t RXCOUNT; /* 0x18-0x19: Rx Counter of Rx EP */ |
AnnaBridge | 172:65be27845400 | 360 | }; |
AnnaBridge | 172:65be27845400 | 361 | #if 0 |
AnnaBridge | 172:65be27845400 | 362 | uint16_t RESERVED0; /* 0x1a-0x1b: reserved */ |
AnnaBridge | 172:65be27845400 | 363 | #else |
AnnaBridge | 172:65be27845400 | 364 | /* host mode only */ |
AnnaBridge | 172:65be27845400 | 365 | __IO uint8_t TXTYPE; /* 0x1a: TxType */ |
AnnaBridge | 172:65be27845400 | 366 | __IO uint8_t TXINTERVAL; /* 0x1B: TxInterval */ |
AnnaBridge | 172:65be27845400 | 367 | |
AnnaBridge | 172:65be27845400 | 368 | #endif |
AnnaBridge | 172:65be27845400 | 369 | }; |
AnnaBridge | 172:65be27845400 | 370 | struct { |
AnnaBridge | 172:65be27845400 | 371 | __IO uint8_t RXTYPE; /* 0x1c: rxtype */ |
AnnaBridge | 172:65be27845400 | 372 | __IO uint8_t RXINTERVAL; /* 0x1d: rxInterval */ |
AnnaBridge | 172:65be27845400 | 373 | uint8_t RESERVED1[1]; /* 0x1e: reserved */ |
AnnaBridge | 172:65be27845400 | 374 | union { |
AnnaBridge | 172:65be27845400 | 375 | __IO uint8_t CONFIGDATA; /* 0x1f: Data of Core Configuration */ |
AnnaBridge | 172:65be27845400 | 376 | __IO uint8_t FIFOSIZE; /* 0x1f: Size of Selected TX/RX Fifo */ |
AnnaBridge | 172:65be27845400 | 377 | }; |
AnnaBridge | 172:65be27845400 | 378 | }; |
AnnaBridge | 172:65be27845400 | 379 | __IO uint32_t FIFOs[16]; /* 0x20-0x5F: fifos for Endpoint */ |
AnnaBridge | 172:65be27845400 | 380 | struct { |
AnnaBridge | 172:65be27845400 | 381 | __IO uint8_t DEVCTL; /* 0x60: OTG device control */ |
AnnaBridge | 172:65be27845400 | 382 | uint8_t RESERVED2; /* 0x61: unused */ |
AnnaBridge | 172:65be27845400 | 383 | __IO uint8_t TXFIFOSZ; /* 0x62: Tx Endpoint FIFO Size */ |
AnnaBridge | 172:65be27845400 | 384 | __IO uint8_t RXFIFOSZ; /* 0x63: Rx Endpoint FIFO Size */ |
AnnaBridge | 172:65be27845400 | 385 | }; |
AnnaBridge | 172:65be27845400 | 386 | struct { |
AnnaBridge | 172:65be27845400 | 387 | __IO uint16_t TXFIFOADDR; /* 0x64-0x65: Tx Endpoint FIFO Address */ |
AnnaBridge | 172:65be27845400 | 388 | __IO uint16_t RXFIFOADDR; /* 0x66-0x67: Rx Endpoint FIFO Address */ |
AnnaBridge | 172:65be27845400 | 389 | }; |
AnnaBridge | 172:65be27845400 | 390 | union { |
AnnaBridge | 172:65be27845400 | 391 | __IO uint32_t VCONTROL; /* 0x68-0x6b: UTMI+PHY Vendor Register */ |
AnnaBridge | 172:65be27845400 | 392 | __IO uint32_t VSTATUS; /* 0x68-0x6b: UTMI+PHY Vendor Register */ |
AnnaBridge | 172:65be27845400 | 393 | }; |
AnnaBridge | 172:65be27845400 | 394 | struct { |
AnnaBridge | 172:65be27845400 | 395 | __IO uint16_t HWVERSION; /* 0x6c-0x6d: Hardware Version Number Register */ |
AnnaBridge | 172:65be27845400 | 396 | uint16_t RESERVED3; /* 0x6e-0x6f: Unused */ |
AnnaBridge | 172:65be27845400 | 397 | }; |
AnnaBridge | 172:65be27845400 | 398 | __IO uint8_t ULPIREG[8]; /* 0x70-0x77: ulpi register, not used */ |
AnnaBridge | 172:65be27845400 | 399 | struct { |
AnnaBridge | 172:65be27845400 | 400 | __IO uint8_t EPINFO; /* 0x78: numbers of tx/rx ep */ |
AnnaBridge | 172:65be27845400 | 401 | __IO uint8_t RAMINFO; /* 0x79: width of RAM and number of DMA channels */ |
AnnaBridge | 172:65be27845400 | 402 | __IO uint8_t LINKINFO; /* 0x7a: delays to be applied */ |
AnnaBridge | 172:65be27845400 | 403 | __IO uint8_t VPLEN; /* 0x7b: Duration of the VBus pulsing charge */ |
AnnaBridge | 172:65be27845400 | 404 | }; |
AnnaBridge | 172:65be27845400 | 405 | struct { |
AnnaBridge | 172:65be27845400 | 406 | __IO uint8_t HSEOF; /* 0x7c: Timer buffer available on HS transaction */ |
AnnaBridge | 172:65be27845400 | 407 | __IO uint8_t FSEOF; /* 0x7d: Timer buffer available on HS transaction */ |
AnnaBridge | 172:65be27845400 | 408 | __IO uint8_t LSEOF; /* 0x7e: Timer buffer available on HS transaction */ |
AnnaBridge | 172:65be27845400 | 409 | uint8_t RESERVED4; /* 0x7f: unused */ |
AnnaBridge | 172:65be27845400 | 410 | }; |
AnnaBridge | 172:65be27845400 | 411 | uint32_t RESERVED5[3]; /* 0x80-0x8b: unused */ |
AnnaBridge | 172:65be27845400 | 412 | __IO uint32_t FIFO_CTRL; /* 0x8c: FIFO Control */ |
AnnaBridge | 172:65be27845400 | 413 | __IO uint32_t ANAREG2; /* 0x90-0x93 */ |
AnnaBridge | 172:65be27845400 | 414 | uint32_t RESERVED6[91]; /* 0x94-0x1ff: unused */ |
AnnaBridge | 172:65be27845400 | 415 | struct { |
AnnaBridge | 172:65be27845400 | 416 | __IO uint8_t DMAINTR; /* 0x200: DMA Interrrupt */ |
AnnaBridge | 172:65be27845400 | 417 | __IO uint8_t RESERVED7[3]; /* 0x201-0x203: unused; */ |
AnnaBridge | 172:65be27845400 | 418 | }; |
AnnaBridge | 172:65be27845400 | 419 | __IO uint32_t DMACTRL0; /* 0x204: channel 0 */ |
AnnaBridge | 172:65be27845400 | 420 | __IO uint32_t DMAADDR0; /* 0x208: AHB Memory Address channel 0 */ |
AnnaBridge | 172:65be27845400 | 421 | __IO uint32_t COUNT0; /* 0x20c: DMA Counter for channel 0 */ |
AnnaBridge | 172:65be27845400 | 422 | |
AnnaBridge | 172:65be27845400 | 423 | uint32_t RESERVED8; /* 0x210-0x213: unused */ |
AnnaBridge | 172:65be27845400 | 424 | __IO uint32_t DMACTRL1; /* 0x214: channel 1 */ |
AnnaBridge | 172:65be27845400 | 425 | __IO uint32_t DMAADDR1; /* 0x218: AHB Memory Address channel 1 */ |
AnnaBridge | 172:65be27845400 | 426 | __IO uint32_t COUNT1; /* 0x21c: DMA Counter for channel 1 */ |
AnnaBridge | 172:65be27845400 | 427 | uint8_t RESERVED9[224]; /* 0x220 - 0x2FF: unused */ |
AnnaBridge | 172:65be27845400 | 428 | __IO uint32_t PKCNT0; /* 0X300: packet count epnum 0 */ |
AnnaBridge | 172:65be27845400 | 429 | __IO uint32_t PKCNT1; /* 0X304: packet count epnum 1 */ |
AnnaBridge | 172:65be27845400 | 430 | __IO uint32_t PKCNT2; /* 0X308:packet count epnum 1 */ |
AnnaBridge | 172:65be27845400 | 431 | }RDA_USB_TypeDef; |
AnnaBridge | 172:65be27845400 | 432 | |
AnnaBridge | 172:65be27845400 | 433 | #if defined ( __CC_ARM ) |
AnnaBridge | 172:65be27845400 | 434 | #pragma no_anon_unions |
AnnaBridge | 172:65be27845400 | 435 | #endif |
AnnaBridge | 172:65be27845400 | 436 | |
AnnaBridge | 172:65be27845400 | 437 | |
AnnaBridge | 172:65be27845400 | 438 | /******************************************************************************/ |
AnnaBridge | 172:65be27845400 | 439 | /* Peripheral memory map */ |
AnnaBridge | 172:65be27845400 | 440 | /******************************************************************************/ |
AnnaBridge | 172:65be27845400 | 441 | //#define RDA_ICACHE_DISABLE |
AnnaBridge | 172:65be27845400 | 442 | #define RDA_PARTITION_INDEX 0 |
AnnaBridge | 172:65be27845400 | 443 | |
AnnaBridge | 172:65be27845400 | 444 | /* Base addresses */ |
AnnaBridge | 172:65be27845400 | 445 | #define RDA_ROM_BASE (0x00000000UL) |
AnnaBridge | 172:65be27845400 | 446 | #define RDA_IRAM_BASE (0x00100000UL) |
AnnaBridge | 172:65be27845400 | 447 | #define RDA_DRAM_BASE (0x00180000UL) |
AnnaBridge | 172:65be27845400 | 448 | #define RDA_PSRAM_BASE (0x10000000UL) |
AnnaBridge | 172:65be27845400 | 449 | #define RDA_FLASH_BASE (0x14000000UL) |
AnnaBridge | 172:65be27845400 | 450 | #define RDA_ICACHE_BASE (0x18000000UL) |
AnnaBridge | 172:65be27845400 | 451 | #if (0 == RDA_PARTITION_INDEX) |
AnnaBridge | 172:65be27845400 | 452 | #define RDA_PADDR_OFST (0x00001000UL) |
AnnaBridge | 172:65be27845400 | 453 | #elif (1 == RDA_PARTITION_INDEX) |
AnnaBridge | 172:65be27845400 | 454 | #define RDA_PADDR_OFST (0x0007E000UL) |
AnnaBridge | 172:65be27845400 | 455 | #else |
AnnaBridge | 172:65be27845400 | 456 | #error "Not supported" |
AnnaBridge | 172:65be27845400 | 457 | #endif |
AnnaBridge | 172:65be27845400 | 458 | #if defined(RDA_ICACHE_DISABLE) |
AnnaBridge | 172:65be27845400 | 459 | #define RDA_CODE_BASE (RDA_FLASH_BASE + RDA_PADDR_OFST) |
AnnaBridge | 172:65be27845400 | 460 | #else /* RDA_ICACHE_DISABLE */ |
AnnaBridge | 172:65be27845400 | 461 | #define RDA_CODE_BASE (RDA_ICACHE_BASE + RDA_PADDR_OFST) |
AnnaBridge | 172:65be27845400 | 462 | #endif /* RDA_ICACHE_DISABLE */ |
AnnaBridge | 172:65be27845400 | 463 | #define RDA_PER_BASE (0x40000000UL) |
AnnaBridge | 172:65be27845400 | 464 | #define RDA_AHB0_BASE (0x40000000UL) |
AnnaBridge | 172:65be27845400 | 465 | #define RDA_APB_BASE (RDA_AHB0_BASE) |
AnnaBridge | 172:65be27845400 | 466 | #define RDA_AHB1_BASE (0x40100000UL) |
AnnaBridge | 172:65be27845400 | 467 | #define RDA_PERBTBND_BASE (0x42000000UL) |
AnnaBridge | 172:65be27845400 | 468 | #define RDA_CM4_BASE (0xE0000000UL) |
AnnaBridge | 172:65be27845400 | 469 | |
AnnaBridge | 172:65be27845400 | 470 | /* APB peripherals */ |
AnnaBridge | 172:65be27845400 | 471 | #define RDA_SCU_BASE (RDA_APB_BASE + 0x00000) |
AnnaBridge | 172:65be27845400 | 472 | #define RDA_GPIO_BASE (RDA_APB_BASE + 0x01000) |
AnnaBridge | 172:65be27845400 | 473 | #define RDA_TIM0_BASE (RDA_APB_BASE + 0x02000) |
AnnaBridge | 172:65be27845400 | 474 | #define RDA_TIM1_BASE (RDA_APB_BASE + 0x02008) |
AnnaBridge | 172:65be27845400 | 475 | #define RDA_TIMINTST_BASE (RDA_APB_BASE + 0x02010) |
AnnaBridge | 172:65be27845400 | 476 | #define RDA_I2C0_BASE (RDA_APB_BASE + 0x03000) |
AnnaBridge | 172:65be27845400 | 477 | |
AnnaBridge | 172:65be27845400 | 478 | /* AHB0 peripherals */ |
AnnaBridge | 172:65be27845400 | 479 | #define RDA_PWM_BASE (RDA_AHB0_BASE + 0x04000) |
AnnaBridge | 172:65be27845400 | 480 | #define RDA_PSRAMCFG_BASE (RDA_AHB0_BASE + 0x05000) |
AnnaBridge | 172:65be27845400 | 481 | #define RDA_SDMMC_BASE (RDA_AHB0_BASE + 0x06000) |
AnnaBridge | 172:65be27845400 | 482 | #define RDA_I2C_BASE (RDA_AHB0_BASE + 0x10000) |
AnnaBridge | 172:65be27845400 | 483 | #define RDA_TRAP_BASE (RDA_AHB0_BASE + 0x11000) |
AnnaBridge | 172:65be27845400 | 484 | #define RDA_UART0_BASE (RDA_AHB0_BASE + 0x12000) |
AnnaBridge | 172:65be27845400 | 485 | #define RDA_EXIF_BASE (RDA_AHB0_BASE + 0x13000) |
AnnaBridge | 172:65be27845400 | 486 | #define RDA_PA_BASE (RDA_AHB0_BASE + 0x20000) |
AnnaBridge | 172:65be27845400 | 487 | #define RDA_CE_BASE (RDA_AHB0_BASE + 0x22000) |
AnnaBridge | 172:65be27845400 | 488 | #define RDA_MON_BASE (RDA_AHB0_BASE + 0x24000) |
AnnaBridge | 172:65be27845400 | 489 | #define RDA_SDIO_BASE (RDA_AHB0_BASE + 0x30000) |
AnnaBridge | 172:65be27845400 | 490 | #define RDA_USB_BASE (RDA_AHB0_BASE + 0x31000) |
AnnaBridge | 172:65be27845400 | 491 | |
AnnaBridge | 172:65be27845400 | 492 | /* AHB1 peripherals */ |
AnnaBridge | 172:65be27845400 | 493 | #define RDA_MEMC_BASE (RDA_AHB1_BASE + 0x00000) |
AnnaBridge | 172:65be27845400 | 494 | #define RDA_UART1_BASE (RDA_AHB1_BASE + 0x80000) |
AnnaBridge | 172:65be27845400 | 495 | #define RDA_DMACFG_BASE (RDA_AHB1_BASE + 0x81000) |
AnnaBridge | 172:65be27845400 | 496 | #define RDA_RNG_BASE (RDA_AHB1_BASE + 0x81100) |
AnnaBridge | 172:65be27845400 | 497 | |
AnnaBridge | 172:65be27845400 | 498 | /* EXIF peripherals */ |
AnnaBridge | 172:65be27845400 | 499 | #define RDA_SPI0_BASE (RDA_EXIF_BASE + 0x00000) |
AnnaBridge | 172:65be27845400 | 500 | #define RDA_I2S_BASE (RDA_EXIF_BASE + 0x0000C) |
AnnaBridge | 172:65be27845400 | 501 | |
AnnaBridge | 172:65be27845400 | 502 | /* MISC peripherals */ |
AnnaBridge | 172:65be27845400 | 503 | #define RDA_WDT_BASE (RDA_SCU_BASE + 0x0000C) |
AnnaBridge | 172:65be27845400 | 504 | #define RDA_PINCFG_BASE (RDA_GPIO_BASE + 0x00044) |
AnnaBridge | 172:65be27845400 | 505 | |
AnnaBridge | 172:65be27845400 | 506 | /******************************************************************************/ |
AnnaBridge | 172:65be27845400 | 507 | /* Peripheral declaration */ |
AnnaBridge | 172:65be27845400 | 508 | /******************************************************************************/ |
AnnaBridge | 172:65be27845400 | 509 | #define RDA_SCU ((RDA_SCU_TypeDef *) RDA_SCU_BASE ) |
AnnaBridge | 172:65be27845400 | 510 | #define RDA_GPIO ((RDA_GPIO_TypeDef *) RDA_GPIO_BASE ) |
AnnaBridge | 172:65be27845400 | 511 | #define RDA_TIM0 ((RDA_TIM0_TypeDef *) RDA_TIM0_BASE ) |
AnnaBridge | 172:65be27845400 | 512 | #define RDA_TIM1 ((RDA_TIM1_TypeDef *) RDA_TIM1_BASE ) |
AnnaBridge | 172:65be27845400 | 513 | #define RDA_TIMINTST ((RDA_TIMINTST_TypeDef *) RDA_TIMINTST_BASE ) |
AnnaBridge | 172:65be27845400 | 514 | #define RDA_I2C0 ((RDA_I2C0_TypeDef *) RDA_I2C0_BASE ) |
AnnaBridge | 172:65be27845400 | 515 | #define RDA_PWM ((RDA_PWM_TypeDef *) RDA_PWM_BASE ) |
AnnaBridge | 172:65be27845400 | 516 | #define RDA_UART0 ((RDA_UART_TypeDef *) RDA_UART0_BASE ) |
AnnaBridge | 172:65be27845400 | 517 | #define RDA_UART1 ((RDA_UART_TypeDef *) RDA_UART1_BASE ) |
AnnaBridge | 172:65be27845400 | 518 | #define RDA_SPI0 ((RDA_SPI_TypeDef *) RDA_SPI0_BASE ) |
AnnaBridge | 172:65be27845400 | 519 | #define RDA_I2S ((RDA_I2S_TypeDef *) RDA_I2S_BASE ) |
AnnaBridge | 172:65be27845400 | 520 | #define RDA_EXIF ((RDA_EXIF_TypeDef *) RDA_EXIF_BASE ) |
AnnaBridge | 172:65be27845400 | 521 | #define RDA_WDT ((RDA_WDT_TypeDef *) RDA_WDT_BASE ) |
AnnaBridge | 172:65be27845400 | 522 | #define RDA_PINCFG ((RDA_PINCFG_TypeDef *) RDA_PINCFG_BASE ) |
AnnaBridge | 172:65be27845400 | 523 | #define RDA_DMACFG ((RDA_DMACFG_TypeDef *) RDA_DMACFG_BASE ) |
AnnaBridge | 172:65be27845400 | 524 | #define RDA_RNG ((RDA_RNG_TypeDef *) RDA_RNG_BASE ) |
AnnaBridge | 172:65be27845400 | 525 | #define RDA_USB ((RDA_USB_TypeDef *) RDA_USB_BASE ) |
AnnaBridge | 172:65be27845400 | 526 | |
AnnaBridge | 172:65be27845400 | 527 | #endif /* __RDA5991H_H__ */ |