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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_IAR/stm32l4xx_hal_nor.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 145:64910690c574 | 1 | /** |
AnnaBridge | 145:64910690c574 | 2 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 3 | * @file stm32l4xx_hal_nor.h |
AnnaBridge | 145:64910690c574 | 4 | * @author MCD Application Team |
AnnaBridge | 145:64910690c574 | 5 | * @brief Header file of NOR HAL module. |
AnnaBridge | 145:64910690c574 | 6 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 7 | * @attention |
AnnaBridge | 145:64910690c574 | 8 | * |
AnnaBridge | 145:64910690c574 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 145:64910690c574 | 10 | * |
AnnaBridge | 145:64910690c574 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 145:64910690c574 | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 145:64910690c574 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 145:64910690c574 | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 145:64910690c574 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 145:64910690c574 | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 145:64910690c574 | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 145:64910690c574 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 145:64910690c574 | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 145:64910690c574 | 20 | * without specific prior written permission. |
AnnaBridge | 145:64910690c574 | 21 | * |
AnnaBridge | 145:64910690c574 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 145:64910690c574 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 145:64910690c574 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 145:64910690c574 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 145:64910690c574 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 145:64910690c574 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 145:64910690c574 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 145:64910690c574 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 145:64910690c574 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 145:64910690c574 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 145:64910690c574 | 32 | * |
AnnaBridge | 145:64910690c574 | 33 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 34 | */ |
AnnaBridge | 145:64910690c574 | 35 | |
AnnaBridge | 145:64910690c574 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 37 | #ifndef __STM32L4xx_HAL_NOR_H |
AnnaBridge | 145:64910690c574 | 38 | #define __STM32L4xx_HAL_NOR_H |
AnnaBridge | 145:64910690c574 | 39 | |
AnnaBridge | 145:64910690c574 | 40 | #ifdef __cplusplus |
AnnaBridge | 145:64910690c574 | 41 | extern "C" { |
AnnaBridge | 145:64910690c574 | 42 | #endif |
AnnaBridge | 145:64910690c574 | 43 | |
AnnaBridge | 145:64910690c574 | 44 | #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ |
AnnaBridge | 161:aa5281ff4a02 | 45 | defined(STM32L496xx) || defined(STM32L4A6xx) || \ |
AnnaBridge | 161:aa5281ff4a02 | 46 | defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 145:64910690c574 | 47 | |
AnnaBridge | 145:64910690c574 | 48 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 49 | #include "stm32l4xx_ll_fmc.h" |
AnnaBridge | 145:64910690c574 | 50 | |
AnnaBridge | 145:64910690c574 | 51 | |
AnnaBridge | 145:64910690c574 | 52 | /** @addtogroup STM32L4xx_HAL_Driver |
AnnaBridge | 145:64910690c574 | 53 | * @{ |
AnnaBridge | 145:64910690c574 | 54 | */ |
AnnaBridge | 145:64910690c574 | 55 | |
AnnaBridge | 145:64910690c574 | 56 | /** @addtogroup NOR |
AnnaBridge | 145:64910690c574 | 57 | * @{ |
AnnaBridge | 145:64910690c574 | 58 | */ |
AnnaBridge | 145:64910690c574 | 59 | |
AnnaBridge | 145:64910690c574 | 60 | /** @addtogroup NOR_Private_Constants |
AnnaBridge | 145:64910690c574 | 61 | * @{ |
AnnaBridge | 145:64910690c574 | 62 | */ |
AnnaBridge | 145:64910690c574 | 63 | |
AnnaBridge | 145:64910690c574 | 64 | /* NOR device IDs addresses */ |
AnnaBridge | 145:64910690c574 | 65 | #define MC_ADDRESS ((uint16_t)0x0000) |
AnnaBridge | 145:64910690c574 | 66 | #define DEVICE_CODE1_ADDR ((uint16_t)0x0001) |
AnnaBridge | 145:64910690c574 | 67 | #define DEVICE_CODE2_ADDR ((uint16_t)0x000E) |
AnnaBridge | 145:64910690c574 | 68 | #define DEVICE_CODE3_ADDR ((uint16_t)0x000F) |
AnnaBridge | 145:64910690c574 | 69 | |
AnnaBridge | 145:64910690c574 | 70 | /* NOR CFI IDs addresses */ |
AnnaBridge | 145:64910690c574 | 71 | #define CFI1_ADDRESS ((uint16_t)0x10) |
AnnaBridge | 145:64910690c574 | 72 | #define CFI2_ADDRESS ((uint16_t)0x11) |
AnnaBridge | 145:64910690c574 | 73 | #define CFI3_ADDRESS ((uint16_t)0x12) |
AnnaBridge | 145:64910690c574 | 74 | #define CFI4_ADDRESS ((uint16_t)0x13) |
AnnaBridge | 145:64910690c574 | 75 | |
AnnaBridge | 145:64910690c574 | 76 | /* NOR memory data width */ |
AnnaBridge | 145:64910690c574 | 77 | #define NOR_MEMORY_8B ((uint8_t)0x0) |
AnnaBridge | 145:64910690c574 | 78 | #define NOR_MEMORY_16B ((uint8_t)0x1) |
AnnaBridge | 145:64910690c574 | 79 | |
AnnaBridge | 145:64910690c574 | 80 | /* NOR memory device read/write start address */ |
AnnaBridge | 145:64910690c574 | 81 | #define NOR_MEMORY_ADRESS1 FMC_BANK1_1 |
AnnaBridge | 145:64910690c574 | 82 | #define NOR_MEMORY_ADRESS2 FMC_BANK1_2 |
AnnaBridge | 145:64910690c574 | 83 | #define NOR_MEMORY_ADRESS3 FMC_BANK1_3 |
AnnaBridge | 145:64910690c574 | 84 | #define NOR_MEMORY_ADRESS4 FMC_BANK1_4 |
AnnaBridge | 145:64910690c574 | 85 | |
AnnaBridge | 145:64910690c574 | 86 | /** |
AnnaBridge | 145:64910690c574 | 87 | * @} |
AnnaBridge | 145:64910690c574 | 88 | */ |
AnnaBridge | 145:64910690c574 | 89 | |
AnnaBridge | 145:64910690c574 | 90 | /** @addtogroup NOR_Private_Macros |
AnnaBridge | 145:64910690c574 | 91 | * @{ |
AnnaBridge | 145:64910690c574 | 92 | */ |
AnnaBridge | 145:64910690c574 | 93 | |
AnnaBridge | 145:64910690c574 | 94 | /** |
AnnaBridge | 145:64910690c574 | 95 | * @brief NOR memory address shifting. |
AnnaBridge | 145:64910690c574 | 96 | * @param __NOR_ADDRESS: NOR base address |
AnnaBridge | 145:64910690c574 | 97 | * @param __NOR_MEMORY_WIDTH_: NOR memory width |
AnnaBridge | 145:64910690c574 | 98 | * @param __ADDRESS__: NOR memory address |
AnnaBridge | 145:64910690c574 | 99 | * @retval NOR shifted address value |
AnnaBridge | 145:64910690c574 | 100 | */ |
AnnaBridge | 145:64910690c574 | 101 | #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ |
AnnaBridge | 145:64910690c574 | 102 | ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ |
AnnaBridge | 145:64910690c574 | 103 | ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ |
AnnaBridge | 145:64910690c574 | 104 | ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) |
AnnaBridge | 145:64910690c574 | 105 | |
AnnaBridge | 145:64910690c574 | 106 | /** |
AnnaBridge | 145:64910690c574 | 107 | * @brief NOR memory write data to specified address. |
AnnaBridge | 145:64910690c574 | 108 | * @param __ADDRESS__: NOR memory address |
AnnaBridge | 145:64910690c574 | 109 | * @param __DATA__: Data to write |
AnnaBridge | 145:64910690c574 | 110 | * @retval None |
AnnaBridge | 145:64910690c574 | 111 | */ |
AnnaBridge | 145:64910690c574 | 112 | #define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)) |
AnnaBridge | 145:64910690c574 | 113 | |
AnnaBridge | 145:64910690c574 | 114 | /** |
AnnaBridge | 145:64910690c574 | 115 | * @} |
AnnaBridge | 145:64910690c574 | 116 | */ |
AnnaBridge | 145:64910690c574 | 117 | |
AnnaBridge | 145:64910690c574 | 118 | /* Exported typedef ----------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 119 | /** @defgroup NOR_Exported_Types NOR Exported Types |
AnnaBridge | 145:64910690c574 | 120 | * @{ |
AnnaBridge | 145:64910690c574 | 121 | */ |
AnnaBridge | 145:64910690c574 | 122 | |
AnnaBridge | 145:64910690c574 | 123 | /** |
AnnaBridge | 145:64910690c574 | 124 | * @brief HAL SRAM State structures definition |
AnnaBridge | 145:64910690c574 | 125 | */ |
AnnaBridge | 145:64910690c574 | 126 | typedef enum |
AnnaBridge | 145:64910690c574 | 127 | { |
AnnaBridge | 145:64910690c574 | 128 | HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */ |
AnnaBridge | 145:64910690c574 | 129 | HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */ |
AnnaBridge | 145:64910690c574 | 130 | HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */ |
AnnaBridge | 145:64910690c574 | 131 | HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ |
AnnaBridge | 145:64910690c574 | 132 | HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ |
AnnaBridge | 145:64910690c574 | 133 | }HAL_NOR_StateTypeDef; |
AnnaBridge | 145:64910690c574 | 134 | |
AnnaBridge | 145:64910690c574 | 135 | /** |
AnnaBridge | 145:64910690c574 | 136 | * @brief FMC NOR Status typedef |
AnnaBridge | 145:64910690c574 | 137 | */ |
AnnaBridge | 145:64910690c574 | 138 | typedef enum |
AnnaBridge | 145:64910690c574 | 139 | { |
AnnaBridge | 145:64910690c574 | 140 | HAL_NOR_STATUS_SUCCESS = 0, |
AnnaBridge | 145:64910690c574 | 141 | HAL_NOR_STATUS_ONGOING, |
AnnaBridge | 145:64910690c574 | 142 | HAL_NOR_STATUS_ERROR, |
AnnaBridge | 145:64910690c574 | 143 | HAL_NOR_STATUS_TIMEOUT |
AnnaBridge | 145:64910690c574 | 144 | }HAL_NOR_StatusTypeDef; |
AnnaBridge | 145:64910690c574 | 145 | |
AnnaBridge | 145:64910690c574 | 146 | /** |
AnnaBridge | 145:64910690c574 | 147 | * @brief FMC NOR ID typedef |
AnnaBridge | 145:64910690c574 | 148 | */ |
AnnaBridge | 145:64910690c574 | 149 | typedef struct |
AnnaBridge | 145:64910690c574 | 150 | { |
AnnaBridge | 145:64910690c574 | 151 | uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */ |
AnnaBridge | 145:64910690c574 | 152 | |
AnnaBridge | 145:64910690c574 | 153 | uint16_t Device_Code1; |
AnnaBridge | 145:64910690c574 | 154 | |
AnnaBridge | 145:64910690c574 | 155 | uint16_t Device_Code2; |
AnnaBridge | 145:64910690c574 | 156 | |
AnnaBridge | 145:64910690c574 | 157 | uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. |
AnnaBridge | 145:64910690c574 | 158 | These codes can be accessed by performing read operations with specific |
AnnaBridge | 145:64910690c574 | 159 | control signals and addresses set.They can also be accessed by issuing |
AnnaBridge | 145:64910690c574 | 160 | an Auto Select command. */ |
AnnaBridge | 145:64910690c574 | 161 | }NOR_IDTypeDef; |
AnnaBridge | 145:64910690c574 | 162 | |
AnnaBridge | 145:64910690c574 | 163 | /** |
AnnaBridge | 145:64910690c574 | 164 | * @brief FMC NOR CFI typedef |
AnnaBridge | 145:64910690c574 | 165 | */ |
AnnaBridge | 145:64910690c574 | 166 | typedef struct |
AnnaBridge | 145:64910690c574 | 167 | { |
AnnaBridge | 145:64910690c574 | 168 | uint16_t CFI_1; |
AnnaBridge | 145:64910690c574 | 169 | |
AnnaBridge | 145:64910690c574 | 170 | uint16_t CFI_2; |
AnnaBridge | 145:64910690c574 | 171 | |
AnnaBridge | 145:64910690c574 | 172 | uint16_t CFI_3; |
AnnaBridge | 145:64910690c574 | 173 | |
AnnaBridge | 145:64910690c574 | 174 | uint16_t CFI_4; /*!< Defines the information stored in the memory's Common flash interface |
AnnaBridge | 145:64910690c574 | 175 | which contains a description of various electrical and timing parameters, |
AnnaBridge | 145:64910690c574 | 176 | density information and functions supported by the memory. */ |
AnnaBridge | 145:64910690c574 | 177 | }NOR_CFITypeDef; |
AnnaBridge | 145:64910690c574 | 178 | |
AnnaBridge | 145:64910690c574 | 179 | /** |
AnnaBridge | 145:64910690c574 | 180 | * @brief NOR handle Structure definition |
AnnaBridge | 145:64910690c574 | 181 | */ |
AnnaBridge | 145:64910690c574 | 182 | typedef struct |
AnnaBridge | 145:64910690c574 | 183 | { |
AnnaBridge | 145:64910690c574 | 184 | FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ |
AnnaBridge | 145:64910690c574 | 185 | |
AnnaBridge | 145:64910690c574 | 186 | FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ |
AnnaBridge | 145:64910690c574 | 187 | |
AnnaBridge | 145:64910690c574 | 188 | FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ |
AnnaBridge | 145:64910690c574 | 189 | |
AnnaBridge | 145:64910690c574 | 190 | HAL_LockTypeDef Lock; /*!< NOR locking object */ |
AnnaBridge | 145:64910690c574 | 191 | |
AnnaBridge | 145:64910690c574 | 192 | __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ |
AnnaBridge | 145:64910690c574 | 193 | |
AnnaBridge | 145:64910690c574 | 194 | }NOR_HandleTypeDef; |
AnnaBridge | 145:64910690c574 | 195 | |
AnnaBridge | 145:64910690c574 | 196 | /** |
AnnaBridge | 145:64910690c574 | 197 | * @} |
AnnaBridge | 145:64910690c574 | 198 | */ |
AnnaBridge | 145:64910690c574 | 199 | |
AnnaBridge | 145:64910690c574 | 200 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 201 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 202 | /** @defgroup NOR_Exported_Macros NOR Exported Macros |
AnnaBridge | 145:64910690c574 | 203 | * @{ |
AnnaBridge | 145:64910690c574 | 204 | */ |
AnnaBridge | 145:64910690c574 | 205 | |
AnnaBridge | 145:64910690c574 | 206 | /** @brief Reset NOR handle state. |
AnnaBridge | 145:64910690c574 | 207 | * @param __HANDLE__: NOR handle |
AnnaBridge | 145:64910690c574 | 208 | * @retval None |
AnnaBridge | 145:64910690c574 | 209 | */ |
AnnaBridge | 145:64910690c574 | 210 | #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) |
AnnaBridge | 145:64910690c574 | 211 | |
AnnaBridge | 145:64910690c574 | 212 | /** |
AnnaBridge | 145:64910690c574 | 213 | * @} |
AnnaBridge | 145:64910690c574 | 214 | */ |
AnnaBridge | 145:64910690c574 | 215 | |
AnnaBridge | 145:64910690c574 | 216 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 217 | /** @addtogroup NOR_Exported_Functions NOR Exported Functions |
AnnaBridge | 145:64910690c574 | 218 | * @{ |
AnnaBridge | 145:64910690c574 | 219 | */ |
AnnaBridge | 145:64910690c574 | 220 | |
AnnaBridge | 145:64910690c574 | 221 | /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions |
AnnaBridge | 145:64910690c574 | 222 | * @{ |
AnnaBridge | 145:64910690c574 | 223 | */ |
AnnaBridge | 145:64910690c574 | 224 | |
AnnaBridge | 145:64910690c574 | 225 | /* Initialization/de-initialization functions ********************************/ |
AnnaBridge | 145:64910690c574 | 226 | HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); |
AnnaBridge | 145:64910690c574 | 227 | HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); |
AnnaBridge | 145:64910690c574 | 228 | void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); |
AnnaBridge | 145:64910690c574 | 229 | void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); |
AnnaBridge | 145:64910690c574 | 230 | void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); |
AnnaBridge | 145:64910690c574 | 231 | |
AnnaBridge | 145:64910690c574 | 232 | /** |
AnnaBridge | 145:64910690c574 | 233 | * @} |
AnnaBridge | 145:64910690c574 | 234 | */ |
AnnaBridge | 145:64910690c574 | 235 | |
AnnaBridge | 145:64910690c574 | 236 | /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions |
AnnaBridge | 145:64910690c574 | 237 | * @{ |
AnnaBridge | 145:64910690c574 | 238 | */ |
AnnaBridge | 145:64910690c574 | 239 | |
AnnaBridge | 145:64910690c574 | 240 | /* I/O operation functions ***************************************************/ |
AnnaBridge | 145:64910690c574 | 241 | HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); |
AnnaBridge | 145:64910690c574 | 242 | HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); |
AnnaBridge | 145:64910690c574 | 243 | HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); |
AnnaBridge | 145:64910690c574 | 244 | HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); |
AnnaBridge | 145:64910690c574 | 245 | |
AnnaBridge | 145:64910690c574 | 246 | HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); |
AnnaBridge | 145:64910690c574 | 247 | HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); |
AnnaBridge | 145:64910690c574 | 248 | |
AnnaBridge | 145:64910690c574 | 249 | HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); |
AnnaBridge | 145:64910690c574 | 250 | HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); |
AnnaBridge | 145:64910690c574 | 251 | HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); |
AnnaBridge | 145:64910690c574 | 252 | |
AnnaBridge | 145:64910690c574 | 253 | /** |
AnnaBridge | 145:64910690c574 | 254 | * @} |
AnnaBridge | 145:64910690c574 | 255 | */ |
AnnaBridge | 145:64910690c574 | 256 | |
AnnaBridge | 145:64910690c574 | 257 | /** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions |
AnnaBridge | 145:64910690c574 | 258 | * @{ |
AnnaBridge | 145:64910690c574 | 259 | */ |
AnnaBridge | 145:64910690c574 | 260 | |
AnnaBridge | 145:64910690c574 | 261 | /* NOR Control functions *****************************************************/ |
AnnaBridge | 145:64910690c574 | 262 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); |
AnnaBridge | 145:64910690c574 | 263 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); |
AnnaBridge | 145:64910690c574 | 264 | |
AnnaBridge | 145:64910690c574 | 265 | /** |
AnnaBridge | 145:64910690c574 | 266 | * @} |
AnnaBridge | 145:64910690c574 | 267 | */ |
AnnaBridge | 145:64910690c574 | 268 | |
AnnaBridge | 145:64910690c574 | 269 | /** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions |
AnnaBridge | 145:64910690c574 | 270 | * @{ |
AnnaBridge | 145:64910690c574 | 271 | */ |
AnnaBridge | 145:64910690c574 | 272 | |
AnnaBridge | 145:64910690c574 | 273 | /* NOR State functions ********************************************************/ |
AnnaBridge | 145:64910690c574 | 274 | HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); |
AnnaBridge | 145:64910690c574 | 275 | HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); |
AnnaBridge | 145:64910690c574 | 276 | |
AnnaBridge | 145:64910690c574 | 277 | /** |
AnnaBridge | 145:64910690c574 | 278 | * @} |
AnnaBridge | 145:64910690c574 | 279 | */ |
AnnaBridge | 145:64910690c574 | 280 | |
AnnaBridge | 145:64910690c574 | 281 | /** |
AnnaBridge | 145:64910690c574 | 282 | * @} |
AnnaBridge | 145:64910690c574 | 283 | */ |
AnnaBridge | 145:64910690c574 | 284 | |
AnnaBridge | 145:64910690c574 | 285 | /** |
AnnaBridge | 145:64910690c574 | 286 | * @} |
AnnaBridge | 145:64910690c574 | 287 | */ |
AnnaBridge | 145:64910690c574 | 288 | |
AnnaBridge | 145:64910690c574 | 289 | /** |
AnnaBridge | 145:64910690c574 | 290 | * @} |
AnnaBridge | 145:64910690c574 | 291 | */ |
AnnaBridge | 145:64910690c574 | 292 | |
AnnaBridge | 145:64910690c574 | 293 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
AnnaBridge | 145:64910690c574 | 294 | /* STM32L496xx || STM32L4A6xx || */ |
AnnaBridge | 161:aa5281ff4a02 | 295 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 145:64910690c574 | 296 | |
AnnaBridge | 145:64910690c574 | 297 | #ifdef __cplusplus |
AnnaBridge | 145:64910690c574 | 298 | } |
AnnaBridge | 145:64910690c574 | 299 | #endif |
AnnaBridge | 145:64910690c574 | 300 | |
AnnaBridge | 145:64910690c574 | 301 | #endif /* __STM32L4xx_HAL_NOR_H */ |
AnnaBridge | 145:64910690c574 | 302 | |
AnnaBridge | 145:64910690c574 | 303 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |