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TARGET_NUCLEO_L432KC/TOOLCHAIN_ARM_STD/stm32l4xx_ll_system.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 145:64910690c574 | 1 | /** |
AnnaBridge | 145:64910690c574 | 2 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 3 | * @file stm32l4xx_ll_system.h |
AnnaBridge | 145:64910690c574 | 4 | * @author MCD Application Team |
AnnaBridge | 145:64910690c574 | 5 | * @brief Header file of SYSTEM LL module. |
AnnaBridge | 145:64910690c574 | 6 | @verbatim |
AnnaBridge | 145:64910690c574 | 7 | ============================================================================== |
AnnaBridge | 145:64910690c574 | 8 | ##### How to use this driver ##### |
AnnaBridge | 145:64910690c574 | 9 | ============================================================================== |
AnnaBridge | 145:64910690c574 | 10 | [..] |
AnnaBridge | 145:64910690c574 | 11 | The LL SYSTEM driver contains a set of generic APIs that can be |
AnnaBridge | 145:64910690c574 | 12 | used by user: |
AnnaBridge | 145:64910690c574 | 13 | (+) Some of the FLASH features need to be handled in the SYSTEM file. |
AnnaBridge | 145:64910690c574 | 14 | (+) Access to DBGCMU registers |
AnnaBridge | 145:64910690c574 | 15 | (+) Access to SYSCFG registers |
AnnaBridge | 145:64910690c574 | 16 | (+) Access to VREFBUF registers |
AnnaBridge | 145:64910690c574 | 17 | |
AnnaBridge | 145:64910690c574 | 18 | @endverbatim |
AnnaBridge | 145:64910690c574 | 19 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 20 | * @attention |
AnnaBridge | 145:64910690c574 | 21 | * |
AnnaBridge | 145:64910690c574 | 22 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 145:64910690c574 | 23 | * |
AnnaBridge | 145:64910690c574 | 24 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 145:64910690c574 | 25 | * are permitted provided that the following conditions are met: |
AnnaBridge | 145:64910690c574 | 26 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 145:64910690c574 | 27 | * this list of conditions and the following disclaimer. |
AnnaBridge | 145:64910690c574 | 28 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 145:64910690c574 | 29 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 145:64910690c574 | 30 | * and/or other materials provided with the distribution. |
AnnaBridge | 145:64910690c574 | 31 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 145:64910690c574 | 32 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 145:64910690c574 | 33 | * without specific prior written permission. |
AnnaBridge | 145:64910690c574 | 34 | * |
AnnaBridge | 145:64910690c574 | 35 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 145:64910690c574 | 36 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 145:64910690c574 | 37 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 145:64910690c574 | 38 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 145:64910690c574 | 39 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 145:64910690c574 | 40 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 145:64910690c574 | 41 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 145:64910690c574 | 42 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 145:64910690c574 | 43 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 145:64910690c574 | 44 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 145:64910690c574 | 45 | * |
AnnaBridge | 145:64910690c574 | 46 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 47 | */ |
AnnaBridge | 145:64910690c574 | 48 | |
AnnaBridge | 145:64910690c574 | 49 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 50 | #ifndef __STM32L4xx_LL_SYSTEM_H |
AnnaBridge | 145:64910690c574 | 51 | #define __STM32L4xx_LL_SYSTEM_H |
AnnaBridge | 145:64910690c574 | 52 | |
AnnaBridge | 145:64910690c574 | 53 | #ifdef __cplusplus |
AnnaBridge | 145:64910690c574 | 54 | extern "C" { |
AnnaBridge | 145:64910690c574 | 55 | #endif |
AnnaBridge | 145:64910690c574 | 56 | |
AnnaBridge | 145:64910690c574 | 57 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 58 | #include "stm32l4xx.h" |
AnnaBridge | 145:64910690c574 | 59 | |
AnnaBridge | 145:64910690c574 | 60 | /** @addtogroup STM32L4xx_LL_Driver |
AnnaBridge | 145:64910690c574 | 61 | * @{ |
AnnaBridge | 145:64910690c574 | 62 | */ |
AnnaBridge | 145:64910690c574 | 63 | |
AnnaBridge | 145:64910690c574 | 64 | #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) |
AnnaBridge | 145:64910690c574 | 65 | |
AnnaBridge | 145:64910690c574 | 66 | /** @defgroup SYSTEM_LL SYSTEM |
AnnaBridge | 145:64910690c574 | 67 | * @{ |
AnnaBridge | 145:64910690c574 | 68 | */ |
AnnaBridge | 145:64910690c574 | 69 | |
AnnaBridge | 145:64910690c574 | 70 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 71 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 72 | |
AnnaBridge | 145:64910690c574 | 73 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 74 | /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants |
AnnaBridge | 145:64910690c574 | 75 | * @{ |
AnnaBridge | 145:64910690c574 | 76 | */ |
AnnaBridge | 145:64910690c574 | 77 | |
AnnaBridge | 145:64910690c574 | 78 | /** |
AnnaBridge | 145:64910690c574 | 79 | * @brief Power-down in Run mode Flash key |
AnnaBridge | 145:64910690c574 | 80 | */ |
AnnaBridge | 161:aa5281ff4a02 | 81 | #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ |
AnnaBridge | 161:aa5281ff4a02 | 82 | #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 |
AnnaBridge | 161:aa5281ff4a02 | 83 | to unlock the RUN_PD bit in FLASH_ACR */ |
AnnaBridge | 145:64910690c574 | 84 | |
AnnaBridge | 145:64910690c574 | 85 | /** |
AnnaBridge | 145:64910690c574 | 86 | * @} |
AnnaBridge | 145:64910690c574 | 87 | */ |
AnnaBridge | 145:64910690c574 | 88 | |
AnnaBridge | 145:64910690c574 | 89 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 90 | |
AnnaBridge | 145:64910690c574 | 91 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 92 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 93 | /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants |
AnnaBridge | 145:64910690c574 | 94 | * @{ |
AnnaBridge | 145:64910690c574 | 95 | */ |
AnnaBridge | 145:64910690c574 | 96 | |
AnnaBridge | 145:64910690c574 | 97 | /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP |
AnnaBridge | 145:64910690c574 | 98 | * @{ |
AnnaBridge | 145:64910690c574 | 99 | */ |
AnnaBridge | 145:64910690c574 | 100 | #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ |
AnnaBridge | 145:64910690c574 | 101 | #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ |
AnnaBridge | 145:64910690c574 | 102 | #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */ |
AnnaBridge | 145:64910690c574 | 103 | #if defined(FMC_Bank1_R) |
AnnaBridge | 145:64910690c574 | 104 | #define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */ |
AnnaBridge | 145:64910690c574 | 105 | #endif /* FMC_Bank1_R */ |
AnnaBridge | 145:64910690c574 | 106 | #define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */ |
AnnaBridge | 145:64910690c574 | 107 | /** |
AnnaBridge | 145:64910690c574 | 108 | * @} |
AnnaBridge | 145:64910690c574 | 109 | */ |
AnnaBridge | 145:64910690c574 | 110 | |
AnnaBridge | 145:64910690c574 | 111 | #if defined(SYSCFG_MEMRMP_FB_MODE) |
AnnaBridge | 145:64910690c574 | 112 | /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE |
AnnaBridge | 145:64910690c574 | 113 | * @{ |
AnnaBridge | 145:64910690c574 | 114 | */ |
AnnaBridge | 145:64910690c574 | 115 | #define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) |
AnnaBridge | 145:64910690c574 | 116 | and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */ |
AnnaBridge | 145:64910690c574 | 117 | #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) |
AnnaBridge | 145:64910690c574 | 118 | and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */ |
AnnaBridge | 145:64910690c574 | 119 | /** |
AnnaBridge | 145:64910690c574 | 120 | * @} |
AnnaBridge | 145:64910690c574 | 121 | */ |
AnnaBridge | 145:64910690c574 | 122 | |
AnnaBridge | 145:64910690c574 | 123 | #endif /* SYSCFG_MEMRMP_FB_MODE */ |
AnnaBridge | 145:64910690c574 | 124 | /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS |
AnnaBridge | 145:64910690c574 | 125 | * @{ |
AnnaBridge | 145:64910690c574 | 126 | */ |
AnnaBridge | 145:64910690c574 | 127 | #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ |
AnnaBridge | 145:64910690c574 | 128 | #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ |
AnnaBridge | 145:64910690c574 | 129 | #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) |
AnnaBridge | 145:64910690c574 | 130 | #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ |
AnnaBridge | 145:64910690c574 | 131 | #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ |
AnnaBridge | 145:64910690c574 | 132 | #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) |
AnnaBridge | 145:64910690c574 | 133 | #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ |
AnnaBridge | 145:64910690c574 | 134 | #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ |
AnnaBridge | 145:64910690c574 | 135 | #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ |
AnnaBridge | 145:64910690c574 | 136 | #if defined(I2C2) |
AnnaBridge | 145:64910690c574 | 137 | #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ |
AnnaBridge | 145:64910690c574 | 138 | #endif /* I2C2 */ |
AnnaBridge | 145:64910690c574 | 139 | #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ |
AnnaBridge | 145:64910690c574 | 140 | #if defined(I2C4) |
AnnaBridge | 145:64910690c574 | 141 | #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ |
AnnaBridge | 145:64910690c574 | 142 | #endif /* I2C4 */ |
AnnaBridge | 145:64910690c574 | 143 | /** |
AnnaBridge | 145:64910690c574 | 144 | * @} |
AnnaBridge | 145:64910690c574 | 145 | */ |
AnnaBridge | 145:64910690c574 | 146 | |
AnnaBridge | 145:64910690c574 | 147 | /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT |
AnnaBridge | 145:64910690c574 | 148 | * @{ |
AnnaBridge | 145:64910690c574 | 149 | */ |
AnnaBridge | 145:64910690c574 | 150 | #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ |
AnnaBridge | 145:64910690c574 | 151 | #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ |
AnnaBridge | 145:64910690c574 | 152 | #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ |
AnnaBridge | 145:64910690c574 | 153 | #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ |
AnnaBridge | 145:64910690c574 | 154 | #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ |
AnnaBridge | 145:64910690c574 | 155 | #if defined(GPIOF) |
AnnaBridge | 145:64910690c574 | 156 | #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */ |
AnnaBridge | 145:64910690c574 | 157 | #endif /* GPIOF */ |
AnnaBridge | 145:64910690c574 | 158 | #if defined(GPIOG) |
AnnaBridge | 145:64910690c574 | 159 | #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */ |
AnnaBridge | 145:64910690c574 | 160 | #endif /* GPIOG */ |
AnnaBridge | 145:64910690c574 | 161 | #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */ |
AnnaBridge | 145:64910690c574 | 162 | #if defined(GPIOI) |
AnnaBridge | 145:64910690c574 | 163 | #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */ |
AnnaBridge | 145:64910690c574 | 164 | #endif /* GPIOI */ |
AnnaBridge | 145:64910690c574 | 165 | /** |
AnnaBridge | 145:64910690c574 | 166 | * @} |
AnnaBridge | 145:64910690c574 | 167 | */ |
AnnaBridge | 145:64910690c574 | 168 | |
AnnaBridge | 145:64910690c574 | 169 | /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE |
AnnaBridge | 145:64910690c574 | 170 | * @{ |
AnnaBridge | 145:64910690c574 | 171 | */ |
AnnaBridge | 145:64910690c574 | 172 | #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */ |
AnnaBridge | 145:64910690c574 | 173 | #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */ |
AnnaBridge | 145:64910690c574 | 174 | #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */ |
AnnaBridge | 145:64910690c574 | 175 | #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */ |
AnnaBridge | 145:64910690c574 | 176 | #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */ |
AnnaBridge | 145:64910690c574 | 177 | #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */ |
AnnaBridge | 145:64910690c574 | 178 | #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */ |
AnnaBridge | 145:64910690c574 | 179 | #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */ |
AnnaBridge | 145:64910690c574 | 180 | #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */ |
AnnaBridge | 145:64910690c574 | 181 | #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */ |
AnnaBridge | 145:64910690c574 | 182 | #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */ |
AnnaBridge | 145:64910690c574 | 183 | #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */ |
AnnaBridge | 145:64910690c574 | 184 | #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */ |
AnnaBridge | 145:64910690c574 | 185 | #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */ |
AnnaBridge | 145:64910690c574 | 186 | #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */ |
AnnaBridge | 145:64910690c574 | 187 | #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */ |
AnnaBridge | 145:64910690c574 | 188 | /** |
AnnaBridge | 145:64910690c574 | 189 | * @} |
AnnaBridge | 145:64910690c574 | 190 | */ |
AnnaBridge | 145:64910690c574 | 191 | |
AnnaBridge | 145:64910690c574 | 192 | /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK |
AnnaBridge | 145:64910690c574 | 193 | * @{ |
AnnaBridge | 145:64910690c574 | 194 | */ |
AnnaBridge | 145:64910690c574 | 195 | #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal |
AnnaBridge | 145:64910690c574 | 196 | with Break Input of TIM1/8/15/16/17 */ |
AnnaBridge | 145:64910690c574 | 197 | #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection |
AnnaBridge | 145:64910690c574 | 198 | with TIM1/8/15/16/17 Break Input |
AnnaBridge | 145:64910690c574 | 199 | and also the PVDE and PLS bits of the Power Control Interface */ |
AnnaBridge | 145:64910690c574 | 200 | #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal |
AnnaBridge | 145:64910690c574 | 201 | with Break Input of TIM1/8/15/16/17 */ |
AnnaBridge | 145:64910690c574 | 202 | #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 |
AnnaBridge | 145:64910690c574 | 203 | with Break Input of TIM1/15/16/17 */ |
AnnaBridge | 145:64910690c574 | 204 | /** |
AnnaBridge | 145:64910690c574 | 205 | * @} |
AnnaBridge | 145:64910690c574 | 206 | */ |
AnnaBridge | 145:64910690c574 | 207 | |
AnnaBridge | 145:64910690c574 | 208 | /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP |
AnnaBridge | 145:64910690c574 | 209 | * @{ |
AnnaBridge | 145:64910690c574 | 210 | */ |
AnnaBridge | 145:64910690c574 | 211 | #define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ |
AnnaBridge | 145:64910690c574 | 212 | #define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ |
AnnaBridge | 145:64910690c574 | 213 | #define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ |
AnnaBridge | 145:64910690c574 | 214 | #define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ |
AnnaBridge | 145:64910690c574 | 215 | #define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ |
AnnaBridge | 145:64910690c574 | 216 | #define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ |
AnnaBridge | 145:64910690c574 | 217 | #define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ |
AnnaBridge | 145:64910690c574 | 218 | #define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ |
AnnaBridge | 145:64910690c574 | 219 | #define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ |
AnnaBridge | 145:64910690c574 | 220 | #define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ |
AnnaBridge | 145:64910690c574 | 221 | #define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ |
AnnaBridge | 145:64910690c574 | 222 | #define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ |
AnnaBridge | 145:64910690c574 | 223 | #define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ |
AnnaBridge | 145:64910690c574 | 224 | #define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ |
AnnaBridge | 145:64910690c574 | 225 | #define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ |
AnnaBridge | 145:64910690c574 | 226 | #define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ |
AnnaBridge | 145:64910690c574 | 227 | #if defined(SYSCFG_SWPR_PAGE31) |
AnnaBridge | 145:64910690c574 | 228 | #define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ |
AnnaBridge | 145:64910690c574 | 229 | #define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ |
AnnaBridge | 145:64910690c574 | 230 | #define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ |
AnnaBridge | 145:64910690c574 | 231 | #define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ |
AnnaBridge | 145:64910690c574 | 232 | #define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ |
AnnaBridge | 145:64910690c574 | 233 | #define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ |
AnnaBridge | 145:64910690c574 | 234 | #define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ |
AnnaBridge | 145:64910690c574 | 235 | #define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ |
AnnaBridge | 145:64910690c574 | 236 | #define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ |
AnnaBridge | 145:64910690c574 | 237 | #define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ |
AnnaBridge | 145:64910690c574 | 238 | #define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ |
AnnaBridge | 145:64910690c574 | 239 | #define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ |
AnnaBridge | 145:64910690c574 | 240 | #define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ |
AnnaBridge | 145:64910690c574 | 241 | #define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ |
AnnaBridge | 145:64910690c574 | 242 | #define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ |
AnnaBridge | 145:64910690c574 | 243 | #define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ |
AnnaBridge | 145:64910690c574 | 244 | #endif /* SYSCFG_SWPR_PAGE31 */ |
AnnaBridge | 145:64910690c574 | 245 | #if defined(SYSCFG_SWPR2_PAGE63) |
AnnaBridge | 145:64910690c574 | 246 | #define LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */ |
AnnaBridge | 145:64910690c574 | 247 | #define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */ |
AnnaBridge | 145:64910690c574 | 248 | #define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */ |
AnnaBridge | 145:64910690c574 | 249 | #define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */ |
AnnaBridge | 145:64910690c574 | 250 | #define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */ |
AnnaBridge | 145:64910690c574 | 251 | #define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */ |
AnnaBridge | 145:64910690c574 | 252 | #define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */ |
AnnaBridge | 145:64910690c574 | 253 | #define LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */ |
AnnaBridge | 145:64910690c574 | 254 | #define LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */ |
AnnaBridge | 145:64910690c574 | 255 | #define LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */ |
AnnaBridge | 145:64910690c574 | 256 | #define LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */ |
AnnaBridge | 145:64910690c574 | 257 | #define LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */ |
AnnaBridge | 145:64910690c574 | 258 | #define LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */ |
AnnaBridge | 145:64910690c574 | 259 | #define LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */ |
AnnaBridge | 145:64910690c574 | 260 | #define LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */ |
AnnaBridge | 145:64910690c574 | 261 | #define LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */ |
AnnaBridge | 145:64910690c574 | 262 | #define LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */ |
AnnaBridge | 145:64910690c574 | 263 | #define LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */ |
AnnaBridge | 145:64910690c574 | 264 | #define LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */ |
AnnaBridge | 145:64910690c574 | 265 | #define LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */ |
AnnaBridge | 145:64910690c574 | 266 | #define LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */ |
AnnaBridge | 145:64910690c574 | 267 | #define LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */ |
AnnaBridge | 145:64910690c574 | 268 | #define LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */ |
AnnaBridge | 145:64910690c574 | 269 | #define LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */ |
AnnaBridge | 145:64910690c574 | 270 | #define LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */ |
AnnaBridge | 145:64910690c574 | 271 | #define LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */ |
AnnaBridge | 145:64910690c574 | 272 | #define LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */ |
AnnaBridge | 145:64910690c574 | 273 | #define LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */ |
AnnaBridge | 145:64910690c574 | 274 | #define LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */ |
AnnaBridge | 145:64910690c574 | 275 | #define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */ |
AnnaBridge | 145:64910690c574 | 276 | #define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */ |
AnnaBridge | 145:64910690c574 | 277 | #define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */ |
AnnaBridge | 145:64910690c574 | 278 | #endif /* SYSCFG_SWPR2_PAGE63 */ |
AnnaBridge | 145:64910690c574 | 279 | /** |
AnnaBridge | 145:64910690c574 | 280 | * @} |
AnnaBridge | 145:64910690c574 | 281 | */ |
AnnaBridge | 145:64910690c574 | 282 | |
AnnaBridge | 145:64910690c574 | 283 | /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment |
AnnaBridge | 145:64910690c574 | 284 | * @{ |
AnnaBridge | 145:64910690c574 | 285 | */ |
AnnaBridge | 145:64910690c574 | 286 | #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ |
AnnaBridge | 145:64910690c574 | 287 | #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ |
AnnaBridge | 145:64910690c574 | 288 | #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ |
AnnaBridge | 145:64910690c574 | 289 | #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ |
AnnaBridge | 145:64910690c574 | 290 | #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ |
AnnaBridge | 145:64910690c574 | 291 | /** |
AnnaBridge | 145:64910690c574 | 292 | * @} |
AnnaBridge | 145:64910690c574 | 293 | */ |
AnnaBridge | 145:64910690c574 | 294 | |
AnnaBridge | 145:64910690c574 | 295 | /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP |
AnnaBridge | 145:64910690c574 | 296 | * @{ |
AnnaBridge | 145:64910690c574 | 297 | */ |
AnnaBridge | 145:64910690c574 | 298 | #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 299 | #if defined(TIM3) |
AnnaBridge | 145:64910690c574 | 300 | #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 301 | #endif /* TIM3 */ |
AnnaBridge | 145:64910690c574 | 302 | #if defined(TIM4) |
AnnaBridge | 145:64910690c574 | 303 | #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 304 | #endif /* TIM4 */ |
AnnaBridge | 145:64910690c574 | 305 | #if defined(TIM5) |
AnnaBridge | 145:64910690c574 | 306 | #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 307 | #endif /* TIM5 */ |
AnnaBridge | 145:64910690c574 | 308 | #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 309 | #if defined(TIM7) |
AnnaBridge | 145:64910690c574 | 310 | #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 311 | #endif /* TIM7 */ |
AnnaBridge | 145:64910690c574 | 312 | #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 313 | #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 314 | #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 315 | #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/ |
AnnaBridge | 145:64910690c574 | 316 | #if defined(I2C2) |
AnnaBridge | 145:64910690c574 | 317 | #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/ |
AnnaBridge | 145:64910690c574 | 318 | #endif /* I2C2 */ |
AnnaBridge | 145:64910690c574 | 319 | #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/ |
AnnaBridge | 145:64910690c574 | 320 | #define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP /*!< The bxCAN receive registers are frozen*/ |
AnnaBridge | 145:64910690c574 | 321 | #if defined(CAN2) |
AnnaBridge | 145:64910690c574 | 322 | #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1FZR1_DBG_CAN2_STOP /*!< The bxCAN2 receive registers are frozen*/ |
AnnaBridge | 145:64910690c574 | 323 | #endif /* CAN2 */ |
AnnaBridge | 145:64910690c574 | 324 | #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 325 | /** |
AnnaBridge | 145:64910690c574 | 326 | * @} |
AnnaBridge | 145:64910690c574 | 327 | */ |
AnnaBridge | 145:64910690c574 | 328 | |
AnnaBridge | 145:64910690c574 | 329 | /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP |
AnnaBridge | 145:64910690c574 | 330 | * @{ |
AnnaBridge | 145:64910690c574 | 331 | */ |
AnnaBridge | 145:64910690c574 | 332 | #if defined(I2C4) |
AnnaBridge | 145:64910690c574 | 333 | #define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/ |
AnnaBridge | 145:64910690c574 | 334 | #endif /* I2C4 */ |
AnnaBridge | 145:64910690c574 | 335 | #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 336 | /** |
AnnaBridge | 145:64910690c574 | 337 | * @} |
AnnaBridge | 145:64910690c574 | 338 | */ |
AnnaBridge | 145:64910690c574 | 339 | |
AnnaBridge | 145:64910690c574 | 340 | /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP |
AnnaBridge | 145:64910690c574 | 341 | * @{ |
AnnaBridge | 145:64910690c574 | 342 | */ |
AnnaBridge | 145:64910690c574 | 343 | #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 344 | #if defined(TIM8) |
AnnaBridge | 145:64910690c574 | 345 | #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 346 | #endif /* TIM8 */ |
AnnaBridge | 145:64910690c574 | 347 | #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 348 | #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 349 | #if defined(TIM17) |
AnnaBridge | 145:64910690c574 | 350 | #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/ |
AnnaBridge | 145:64910690c574 | 351 | #endif /* TIM17 */ |
AnnaBridge | 145:64910690c574 | 352 | /** |
AnnaBridge | 145:64910690c574 | 353 | * @} |
AnnaBridge | 145:64910690c574 | 354 | */ |
AnnaBridge | 145:64910690c574 | 355 | |
AnnaBridge | 145:64910690c574 | 356 | #if defined(VREFBUF) |
AnnaBridge | 145:64910690c574 | 357 | /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE |
AnnaBridge | 145:64910690c574 | 358 | * @{ |
AnnaBridge | 145:64910690c574 | 359 | */ |
AnnaBridge | 145:64910690c574 | 360 | #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ |
AnnaBridge | 145:64910690c574 | 361 | #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ |
AnnaBridge | 145:64910690c574 | 362 | /** |
AnnaBridge | 145:64910690c574 | 363 | * @} |
AnnaBridge | 145:64910690c574 | 364 | */ |
AnnaBridge | 145:64910690c574 | 365 | #endif /* VREFBUF */ |
AnnaBridge | 145:64910690c574 | 366 | |
AnnaBridge | 145:64910690c574 | 367 | /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY |
AnnaBridge | 145:64910690c574 | 368 | * @{ |
AnnaBridge | 145:64910690c574 | 369 | */ |
AnnaBridge | 145:64910690c574 | 370 | #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ |
AnnaBridge | 145:64910690c574 | 371 | #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ |
AnnaBridge | 145:64910690c574 | 372 | #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ |
AnnaBridge | 145:64910690c574 | 373 | #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ |
AnnaBridge | 145:64910690c574 | 374 | #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ |
AnnaBridge | 161:aa5281ff4a02 | 375 | #if defined(FLASH_ACR_LATENCY_5WS) |
AnnaBridge | 161:aa5281ff4a02 | 376 | #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ |
AnnaBridge | 161:aa5281ff4a02 | 377 | #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ |
AnnaBridge | 161:aa5281ff4a02 | 378 | #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ |
AnnaBridge | 161:aa5281ff4a02 | 379 | #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */ |
AnnaBridge | 161:aa5281ff4a02 | 380 | #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ |
AnnaBridge | 161:aa5281ff4a02 | 381 | #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ |
AnnaBridge | 161:aa5281ff4a02 | 382 | #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ |
AnnaBridge | 161:aa5281ff4a02 | 383 | #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ |
AnnaBridge | 161:aa5281ff4a02 | 384 | #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ |
AnnaBridge | 161:aa5281ff4a02 | 385 | #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ |
AnnaBridge | 161:aa5281ff4a02 | 386 | #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ |
AnnaBridge | 161:aa5281ff4a02 | 387 | #endif |
AnnaBridge | 145:64910690c574 | 388 | /** |
AnnaBridge | 145:64910690c574 | 389 | * @} |
AnnaBridge | 145:64910690c574 | 390 | */ |
AnnaBridge | 145:64910690c574 | 391 | |
AnnaBridge | 145:64910690c574 | 392 | /** |
AnnaBridge | 145:64910690c574 | 393 | * @} |
AnnaBridge | 145:64910690c574 | 394 | */ |
AnnaBridge | 145:64910690c574 | 395 | |
AnnaBridge | 145:64910690c574 | 396 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 397 | |
AnnaBridge | 145:64910690c574 | 398 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 399 | /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions |
AnnaBridge | 145:64910690c574 | 400 | * @{ |
AnnaBridge | 145:64910690c574 | 401 | */ |
AnnaBridge | 145:64910690c574 | 402 | |
AnnaBridge | 145:64910690c574 | 403 | /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG |
AnnaBridge | 145:64910690c574 | 404 | * @{ |
AnnaBridge | 145:64910690c574 | 405 | */ |
AnnaBridge | 145:64910690c574 | 406 | |
AnnaBridge | 145:64910690c574 | 407 | /** |
AnnaBridge | 145:64910690c574 | 408 | * @brief Set memory mapping at address 0x00000000 |
AnnaBridge | 145:64910690c574 | 409 | * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory |
AnnaBridge | 145:64910690c574 | 410 | * @param Memory This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 411 | * @arg @ref LL_SYSCFG_REMAP_FLASH |
AnnaBridge | 145:64910690c574 | 412 | * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH |
AnnaBridge | 145:64910690c574 | 413 | * @arg @ref LL_SYSCFG_REMAP_SRAM |
AnnaBridge | 145:64910690c574 | 414 | * @arg @ref LL_SYSCFG_REMAP_FMC (*) |
AnnaBridge | 145:64910690c574 | 415 | * @arg @ref LL_SYSCFG_REMAP_QUADSPI |
AnnaBridge | 145:64910690c574 | 416 | * |
AnnaBridge | 145:64910690c574 | 417 | * (*) value not defined in all devices |
AnnaBridge | 145:64910690c574 | 418 | * @retval None |
AnnaBridge | 145:64910690c574 | 419 | */ |
AnnaBridge | 145:64910690c574 | 420 | __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) |
AnnaBridge | 145:64910690c574 | 421 | { |
AnnaBridge | 145:64910690c574 | 422 | MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory); |
AnnaBridge | 145:64910690c574 | 423 | } |
AnnaBridge | 145:64910690c574 | 424 | |
AnnaBridge | 145:64910690c574 | 425 | /** |
AnnaBridge | 145:64910690c574 | 426 | * @brief Get memory mapping at address 0x00000000 |
AnnaBridge | 145:64910690c574 | 427 | * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory |
AnnaBridge | 145:64910690c574 | 428 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 429 | * @arg @ref LL_SYSCFG_REMAP_FLASH |
AnnaBridge | 145:64910690c574 | 430 | * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH |
AnnaBridge | 145:64910690c574 | 431 | * @arg @ref LL_SYSCFG_REMAP_SRAM |
AnnaBridge | 145:64910690c574 | 432 | * @arg @ref LL_SYSCFG_REMAP_FMC (*) |
AnnaBridge | 145:64910690c574 | 433 | * @arg @ref LL_SYSCFG_REMAP_QUADSPI |
AnnaBridge | 145:64910690c574 | 434 | * |
AnnaBridge | 145:64910690c574 | 435 | * (*) value not defined in all devices |
AnnaBridge | 145:64910690c574 | 436 | */ |
AnnaBridge | 145:64910690c574 | 437 | __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) |
AnnaBridge | 145:64910690c574 | 438 | { |
AnnaBridge | 145:64910690c574 | 439 | return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)); |
AnnaBridge | 145:64910690c574 | 440 | } |
AnnaBridge | 145:64910690c574 | 441 | |
AnnaBridge | 145:64910690c574 | 442 | #if defined(SYSCFG_MEMRMP_FB_MODE) |
AnnaBridge | 145:64910690c574 | 443 | /** |
AnnaBridge | 145:64910690c574 | 444 | * @brief Select Flash bank mode (Bank flashed at 0x08000000) |
AnnaBridge | 145:64910690c574 | 445 | * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode |
AnnaBridge | 145:64910690c574 | 446 | * @param Bank This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 447 | * @arg @ref LL_SYSCFG_BANKMODE_BANK1 |
AnnaBridge | 145:64910690c574 | 448 | * @arg @ref LL_SYSCFG_BANKMODE_BANK2 |
AnnaBridge | 145:64910690c574 | 449 | * @retval None |
AnnaBridge | 145:64910690c574 | 450 | */ |
AnnaBridge | 145:64910690c574 | 451 | __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) |
AnnaBridge | 145:64910690c574 | 452 | { |
AnnaBridge | 145:64910690c574 | 453 | MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank); |
AnnaBridge | 145:64910690c574 | 454 | } |
AnnaBridge | 145:64910690c574 | 455 | |
AnnaBridge | 145:64910690c574 | 456 | /** |
AnnaBridge | 145:64910690c574 | 457 | * @brief Get Flash bank mode (Bank flashed at 0x08000000) |
AnnaBridge | 145:64910690c574 | 458 | * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode |
AnnaBridge | 145:64910690c574 | 459 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 460 | * @arg @ref LL_SYSCFG_BANKMODE_BANK1 |
AnnaBridge | 145:64910690c574 | 461 | * @arg @ref LL_SYSCFG_BANKMODE_BANK2 |
AnnaBridge | 145:64910690c574 | 462 | */ |
AnnaBridge | 145:64910690c574 | 463 | __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) |
AnnaBridge | 145:64910690c574 | 464 | { |
AnnaBridge | 145:64910690c574 | 465 | return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE)); |
AnnaBridge | 145:64910690c574 | 466 | } |
AnnaBridge | 145:64910690c574 | 467 | #endif /* SYSCFG_MEMRMP_FB_MODE */ |
AnnaBridge | 145:64910690c574 | 468 | |
AnnaBridge | 145:64910690c574 | 469 | /** |
AnnaBridge | 145:64910690c574 | 470 | * @brief Firewall protection enabled |
AnnaBridge | 145:64910690c574 | 471 | * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_EnableFirewall |
AnnaBridge | 145:64910690c574 | 472 | * @retval None |
AnnaBridge | 145:64910690c574 | 473 | */ |
AnnaBridge | 145:64910690c574 | 474 | __STATIC_INLINE void LL_SYSCFG_EnableFirewall(void) |
AnnaBridge | 145:64910690c574 | 475 | { |
AnnaBridge | 145:64910690c574 | 476 | CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS); |
AnnaBridge | 145:64910690c574 | 477 | } |
AnnaBridge | 145:64910690c574 | 478 | |
AnnaBridge | 145:64910690c574 | 479 | /** |
AnnaBridge | 145:64910690c574 | 480 | * @brief Check if Firewall protection is enabled or not |
AnnaBridge | 145:64910690c574 | 481 | * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_IsEnabledFirewall |
AnnaBridge | 145:64910690c574 | 482 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 483 | */ |
AnnaBridge | 145:64910690c574 | 484 | __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void) |
AnnaBridge | 145:64910690c574 | 485 | { |
AnnaBridge | 145:64910690c574 | 486 | return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS); |
AnnaBridge | 145:64910690c574 | 487 | } |
AnnaBridge | 145:64910690c574 | 488 | |
AnnaBridge | 145:64910690c574 | 489 | /** |
AnnaBridge | 145:64910690c574 | 490 | * @brief Enable I/O analog switch voltage booster. |
AnnaBridge | 145:64910690c574 | 491 | * @note When voltage booster is enabled, I/O analog switches are supplied |
AnnaBridge | 145:64910690c574 | 492 | * by a dedicated voltage booster, from VDD power domain. This is |
AnnaBridge | 145:64910690c574 | 493 | * the recommended configuration with low VDDA voltage operation. |
AnnaBridge | 145:64910690c574 | 494 | * @note The I/O analog switch voltage booster is relevant for peripherals |
AnnaBridge | 145:64910690c574 | 495 | * using I/O in analog input: ADC, COMP, OPAMP. |
AnnaBridge | 145:64910690c574 | 496 | * However, COMP and OPAMP inputs have a high impedance and |
AnnaBridge | 145:64910690c574 | 497 | * voltage booster do not impact performance significantly. |
AnnaBridge | 145:64910690c574 | 498 | * Therefore, the voltage booster is mainly intended for |
AnnaBridge | 145:64910690c574 | 499 | * usage with ADC. |
AnnaBridge | 145:64910690c574 | 500 | * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster |
AnnaBridge | 145:64910690c574 | 501 | * @retval None |
AnnaBridge | 145:64910690c574 | 502 | */ |
AnnaBridge | 145:64910690c574 | 503 | __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) |
AnnaBridge | 145:64910690c574 | 504 | { |
AnnaBridge | 145:64910690c574 | 505 | SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); |
AnnaBridge | 145:64910690c574 | 506 | } |
AnnaBridge | 145:64910690c574 | 507 | |
AnnaBridge | 145:64910690c574 | 508 | /** |
AnnaBridge | 145:64910690c574 | 509 | * @brief Disable I/O analog switch voltage booster. |
AnnaBridge | 145:64910690c574 | 510 | * @note When voltage booster is enabled, I/O analog switches are supplied |
AnnaBridge | 145:64910690c574 | 511 | * by a dedicated voltage booster, from VDD power domain. This is |
AnnaBridge | 145:64910690c574 | 512 | * the recommended configuration with low VDDA voltage operation. |
AnnaBridge | 145:64910690c574 | 513 | * @note The I/O analog switch voltage booster is relevant for peripherals |
AnnaBridge | 145:64910690c574 | 514 | * using I/O in analog input: ADC, COMP, OPAMP. |
AnnaBridge | 145:64910690c574 | 515 | * However, COMP and OPAMP inputs have a high impedance and |
AnnaBridge | 145:64910690c574 | 516 | * voltage booster do not impact performance significantly. |
AnnaBridge | 145:64910690c574 | 517 | * Therefore, the voltage booster is mainly intended for |
AnnaBridge | 145:64910690c574 | 518 | * usage with ADC. |
AnnaBridge | 145:64910690c574 | 519 | * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster |
AnnaBridge | 145:64910690c574 | 520 | * @retval None |
AnnaBridge | 145:64910690c574 | 521 | */ |
AnnaBridge | 145:64910690c574 | 522 | __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) |
AnnaBridge | 145:64910690c574 | 523 | { |
AnnaBridge | 145:64910690c574 | 524 | CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); |
AnnaBridge | 145:64910690c574 | 525 | } |
AnnaBridge | 145:64910690c574 | 526 | |
AnnaBridge | 145:64910690c574 | 527 | /** |
AnnaBridge | 145:64910690c574 | 528 | * @brief Enable the I2C fast mode plus driving capability. |
AnnaBridge | 145:64910690c574 | 529 | * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n |
AnnaBridge | 145:64910690c574 | 530 | * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus |
AnnaBridge | 145:64910690c574 | 531 | * @param ConfigFastModePlus This parameter can be a combination of the following values: |
AnnaBridge | 145:64910690c574 | 532 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 |
AnnaBridge | 145:64910690c574 | 533 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 |
AnnaBridge | 145:64910690c574 | 534 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) |
AnnaBridge | 145:64910690c574 | 535 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) |
AnnaBridge | 145:64910690c574 | 536 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 |
AnnaBridge | 145:64910690c574 | 537 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) |
AnnaBridge | 145:64910690c574 | 538 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 |
AnnaBridge | 145:64910690c574 | 539 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*) |
AnnaBridge | 145:64910690c574 | 540 | * |
AnnaBridge | 145:64910690c574 | 541 | * (*) value not defined in all devices |
AnnaBridge | 145:64910690c574 | 542 | * @retval None |
AnnaBridge | 145:64910690c574 | 543 | */ |
AnnaBridge | 145:64910690c574 | 544 | __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) |
AnnaBridge | 145:64910690c574 | 545 | { |
AnnaBridge | 145:64910690c574 | 546 | SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); |
AnnaBridge | 145:64910690c574 | 547 | } |
AnnaBridge | 145:64910690c574 | 548 | |
AnnaBridge | 145:64910690c574 | 549 | /** |
AnnaBridge | 145:64910690c574 | 550 | * @brief Disable the I2C fast mode plus driving capability. |
AnnaBridge | 145:64910690c574 | 551 | * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n |
AnnaBridge | 145:64910690c574 | 552 | * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus |
AnnaBridge | 145:64910690c574 | 553 | * @param ConfigFastModePlus This parameter can be a combination of the following values: |
AnnaBridge | 145:64910690c574 | 554 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 |
AnnaBridge | 145:64910690c574 | 555 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 |
AnnaBridge | 145:64910690c574 | 556 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) |
AnnaBridge | 145:64910690c574 | 557 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) |
AnnaBridge | 145:64910690c574 | 558 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 |
AnnaBridge | 145:64910690c574 | 559 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) |
AnnaBridge | 145:64910690c574 | 560 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 |
AnnaBridge | 145:64910690c574 | 561 | * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*) |
AnnaBridge | 145:64910690c574 | 562 | * |
AnnaBridge | 145:64910690c574 | 563 | * (*) value not defined in all devices |
AnnaBridge | 145:64910690c574 | 564 | * @retval None |
AnnaBridge | 145:64910690c574 | 565 | */ |
AnnaBridge | 145:64910690c574 | 566 | __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) |
AnnaBridge | 145:64910690c574 | 567 | { |
AnnaBridge | 145:64910690c574 | 568 | CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); |
AnnaBridge | 145:64910690c574 | 569 | } |
AnnaBridge | 145:64910690c574 | 570 | |
AnnaBridge | 145:64910690c574 | 571 | /** |
AnnaBridge | 145:64910690c574 | 572 | * @brief Enable Floating Point Unit Invalid operation Interrupt |
AnnaBridge | 145:64910690c574 | 573 | * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC |
AnnaBridge | 145:64910690c574 | 574 | * @retval None |
AnnaBridge | 145:64910690c574 | 575 | */ |
AnnaBridge | 145:64910690c574 | 576 | __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) |
AnnaBridge | 145:64910690c574 | 577 | { |
AnnaBridge | 145:64910690c574 | 578 | SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); |
AnnaBridge | 145:64910690c574 | 579 | } |
AnnaBridge | 145:64910690c574 | 580 | |
AnnaBridge | 145:64910690c574 | 581 | /** |
AnnaBridge | 145:64910690c574 | 582 | * @brief Enable Floating Point Unit Divide-by-zero Interrupt |
AnnaBridge | 145:64910690c574 | 583 | * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC |
AnnaBridge | 145:64910690c574 | 584 | * @retval None |
AnnaBridge | 145:64910690c574 | 585 | */ |
AnnaBridge | 145:64910690c574 | 586 | __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) |
AnnaBridge | 145:64910690c574 | 587 | { |
AnnaBridge | 145:64910690c574 | 588 | SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); |
AnnaBridge | 145:64910690c574 | 589 | } |
AnnaBridge | 145:64910690c574 | 590 | |
AnnaBridge | 145:64910690c574 | 591 | /** |
AnnaBridge | 145:64910690c574 | 592 | * @brief Enable Floating Point Unit Underflow Interrupt |
AnnaBridge | 145:64910690c574 | 593 | * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC |
AnnaBridge | 145:64910690c574 | 594 | * @retval None |
AnnaBridge | 145:64910690c574 | 595 | */ |
AnnaBridge | 145:64910690c574 | 596 | __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) |
AnnaBridge | 145:64910690c574 | 597 | { |
AnnaBridge | 145:64910690c574 | 598 | SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); |
AnnaBridge | 145:64910690c574 | 599 | } |
AnnaBridge | 145:64910690c574 | 600 | |
AnnaBridge | 145:64910690c574 | 601 | /** |
AnnaBridge | 145:64910690c574 | 602 | * @brief Enable Floating Point Unit Overflow Interrupt |
AnnaBridge | 145:64910690c574 | 603 | * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC |
AnnaBridge | 145:64910690c574 | 604 | * @retval None |
AnnaBridge | 145:64910690c574 | 605 | */ |
AnnaBridge | 145:64910690c574 | 606 | __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) |
AnnaBridge | 145:64910690c574 | 607 | { |
AnnaBridge | 145:64910690c574 | 608 | SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); |
AnnaBridge | 145:64910690c574 | 609 | } |
AnnaBridge | 145:64910690c574 | 610 | |
AnnaBridge | 145:64910690c574 | 611 | /** |
AnnaBridge | 145:64910690c574 | 612 | * @brief Enable Floating Point Unit Input denormal Interrupt |
AnnaBridge | 145:64910690c574 | 613 | * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC |
AnnaBridge | 145:64910690c574 | 614 | * @retval None |
AnnaBridge | 145:64910690c574 | 615 | */ |
AnnaBridge | 145:64910690c574 | 616 | __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) |
AnnaBridge | 145:64910690c574 | 617 | { |
AnnaBridge | 145:64910690c574 | 618 | SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); |
AnnaBridge | 145:64910690c574 | 619 | } |
AnnaBridge | 145:64910690c574 | 620 | |
AnnaBridge | 145:64910690c574 | 621 | /** |
AnnaBridge | 145:64910690c574 | 622 | * @brief Enable Floating Point Unit Inexact Interrupt |
AnnaBridge | 145:64910690c574 | 623 | * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC |
AnnaBridge | 145:64910690c574 | 624 | * @retval None |
AnnaBridge | 145:64910690c574 | 625 | */ |
AnnaBridge | 145:64910690c574 | 626 | __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) |
AnnaBridge | 145:64910690c574 | 627 | { |
AnnaBridge | 145:64910690c574 | 628 | SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); |
AnnaBridge | 145:64910690c574 | 629 | } |
AnnaBridge | 145:64910690c574 | 630 | |
AnnaBridge | 145:64910690c574 | 631 | /** |
AnnaBridge | 145:64910690c574 | 632 | * @brief Disable Floating Point Unit Invalid operation Interrupt |
AnnaBridge | 145:64910690c574 | 633 | * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC |
AnnaBridge | 145:64910690c574 | 634 | * @retval None |
AnnaBridge | 145:64910690c574 | 635 | */ |
AnnaBridge | 145:64910690c574 | 636 | __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) |
AnnaBridge | 145:64910690c574 | 637 | { |
AnnaBridge | 145:64910690c574 | 638 | CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); |
AnnaBridge | 145:64910690c574 | 639 | } |
AnnaBridge | 145:64910690c574 | 640 | |
AnnaBridge | 145:64910690c574 | 641 | /** |
AnnaBridge | 145:64910690c574 | 642 | * @brief Disable Floating Point Unit Divide-by-zero Interrupt |
AnnaBridge | 145:64910690c574 | 643 | * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC |
AnnaBridge | 145:64910690c574 | 644 | * @retval None |
AnnaBridge | 145:64910690c574 | 645 | */ |
AnnaBridge | 145:64910690c574 | 646 | __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) |
AnnaBridge | 145:64910690c574 | 647 | { |
AnnaBridge | 145:64910690c574 | 648 | CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); |
AnnaBridge | 145:64910690c574 | 649 | } |
AnnaBridge | 145:64910690c574 | 650 | |
AnnaBridge | 145:64910690c574 | 651 | /** |
AnnaBridge | 145:64910690c574 | 652 | * @brief Disable Floating Point Unit Underflow Interrupt |
AnnaBridge | 145:64910690c574 | 653 | * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC |
AnnaBridge | 145:64910690c574 | 654 | * @retval None |
AnnaBridge | 145:64910690c574 | 655 | */ |
AnnaBridge | 145:64910690c574 | 656 | __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) |
AnnaBridge | 145:64910690c574 | 657 | { |
AnnaBridge | 145:64910690c574 | 658 | CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); |
AnnaBridge | 145:64910690c574 | 659 | } |
AnnaBridge | 145:64910690c574 | 660 | |
AnnaBridge | 145:64910690c574 | 661 | /** |
AnnaBridge | 145:64910690c574 | 662 | * @brief Disable Floating Point Unit Overflow Interrupt |
AnnaBridge | 145:64910690c574 | 663 | * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC |
AnnaBridge | 145:64910690c574 | 664 | * @retval None |
AnnaBridge | 145:64910690c574 | 665 | */ |
AnnaBridge | 145:64910690c574 | 666 | __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) |
AnnaBridge | 145:64910690c574 | 667 | { |
AnnaBridge | 145:64910690c574 | 668 | CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); |
AnnaBridge | 145:64910690c574 | 669 | } |
AnnaBridge | 145:64910690c574 | 670 | |
AnnaBridge | 145:64910690c574 | 671 | /** |
AnnaBridge | 145:64910690c574 | 672 | * @brief Disable Floating Point Unit Input denormal Interrupt |
AnnaBridge | 145:64910690c574 | 673 | * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC |
AnnaBridge | 145:64910690c574 | 674 | * @retval None |
AnnaBridge | 145:64910690c574 | 675 | */ |
AnnaBridge | 145:64910690c574 | 676 | __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) |
AnnaBridge | 145:64910690c574 | 677 | { |
AnnaBridge | 145:64910690c574 | 678 | CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); |
AnnaBridge | 145:64910690c574 | 679 | } |
AnnaBridge | 145:64910690c574 | 680 | |
AnnaBridge | 145:64910690c574 | 681 | /** |
AnnaBridge | 145:64910690c574 | 682 | * @brief Disable Floating Point Unit Inexact Interrupt |
AnnaBridge | 145:64910690c574 | 683 | * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC |
AnnaBridge | 145:64910690c574 | 684 | * @retval None |
AnnaBridge | 145:64910690c574 | 685 | */ |
AnnaBridge | 145:64910690c574 | 686 | __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void) |
AnnaBridge | 145:64910690c574 | 687 | { |
AnnaBridge | 145:64910690c574 | 688 | CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); |
AnnaBridge | 145:64910690c574 | 689 | } |
AnnaBridge | 145:64910690c574 | 690 | |
AnnaBridge | 145:64910690c574 | 691 | /** |
AnnaBridge | 145:64910690c574 | 692 | * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled. |
AnnaBridge | 145:64910690c574 | 693 | * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC |
AnnaBridge | 145:64910690c574 | 694 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 695 | */ |
AnnaBridge | 145:64910690c574 | 696 | __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void) |
AnnaBridge | 145:64910690c574 | 697 | { |
AnnaBridge | 145:64910690c574 | 698 | return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)); |
AnnaBridge | 145:64910690c574 | 699 | } |
AnnaBridge | 145:64910690c574 | 700 | |
AnnaBridge | 145:64910690c574 | 701 | /** |
AnnaBridge | 145:64910690c574 | 702 | * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled. |
AnnaBridge | 145:64910690c574 | 703 | * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC |
AnnaBridge | 145:64910690c574 | 704 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 705 | */ |
AnnaBridge | 145:64910690c574 | 706 | __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void) |
AnnaBridge | 145:64910690c574 | 707 | { |
AnnaBridge | 145:64910690c574 | 708 | return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)); |
AnnaBridge | 145:64910690c574 | 709 | } |
AnnaBridge | 145:64910690c574 | 710 | |
AnnaBridge | 145:64910690c574 | 711 | /** |
AnnaBridge | 145:64910690c574 | 712 | * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled. |
AnnaBridge | 145:64910690c574 | 713 | * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC |
AnnaBridge | 145:64910690c574 | 714 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 715 | */ |
AnnaBridge | 145:64910690c574 | 716 | __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void) |
AnnaBridge | 145:64910690c574 | 717 | { |
AnnaBridge | 145:64910690c574 | 718 | return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)); |
AnnaBridge | 145:64910690c574 | 719 | } |
AnnaBridge | 145:64910690c574 | 720 | |
AnnaBridge | 145:64910690c574 | 721 | /** |
AnnaBridge | 145:64910690c574 | 722 | * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled. |
AnnaBridge | 145:64910690c574 | 723 | * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC |
AnnaBridge | 145:64910690c574 | 724 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 725 | */ |
AnnaBridge | 145:64910690c574 | 726 | __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void) |
AnnaBridge | 145:64910690c574 | 727 | { |
AnnaBridge | 145:64910690c574 | 728 | return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)); |
AnnaBridge | 145:64910690c574 | 729 | } |
AnnaBridge | 145:64910690c574 | 730 | |
AnnaBridge | 145:64910690c574 | 731 | /** |
AnnaBridge | 145:64910690c574 | 732 | * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled. |
AnnaBridge | 145:64910690c574 | 733 | * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC |
AnnaBridge | 145:64910690c574 | 734 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 735 | */ |
AnnaBridge | 145:64910690c574 | 736 | __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void) |
AnnaBridge | 145:64910690c574 | 737 | { |
AnnaBridge | 145:64910690c574 | 738 | return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)); |
AnnaBridge | 145:64910690c574 | 739 | } |
AnnaBridge | 145:64910690c574 | 740 | |
AnnaBridge | 145:64910690c574 | 741 | /** |
AnnaBridge | 145:64910690c574 | 742 | * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled. |
AnnaBridge | 145:64910690c574 | 743 | * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC |
AnnaBridge | 145:64910690c574 | 744 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 745 | */ |
AnnaBridge | 145:64910690c574 | 746 | __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) |
AnnaBridge | 145:64910690c574 | 747 | { |
AnnaBridge | 145:64910690c574 | 748 | return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)); |
AnnaBridge | 145:64910690c574 | 749 | } |
AnnaBridge | 145:64910690c574 | 750 | |
AnnaBridge | 145:64910690c574 | 751 | /** |
AnnaBridge | 145:64910690c574 | 752 | * @brief Configure source input for the EXTI external interrupt. |
AnnaBridge | 145:64910690c574 | 753 | * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n |
AnnaBridge | 145:64910690c574 | 754 | * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n |
AnnaBridge | 145:64910690c574 | 755 | * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n |
AnnaBridge | 145:64910690c574 | 756 | * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource |
AnnaBridge | 145:64910690c574 | 757 | * @param Port This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 758 | * @arg @ref LL_SYSCFG_EXTI_PORTA |
AnnaBridge | 145:64910690c574 | 759 | * @arg @ref LL_SYSCFG_EXTI_PORTB |
AnnaBridge | 145:64910690c574 | 760 | * @arg @ref LL_SYSCFG_EXTI_PORTC |
AnnaBridge | 145:64910690c574 | 761 | * @arg @ref LL_SYSCFG_EXTI_PORTD |
AnnaBridge | 145:64910690c574 | 762 | * @arg @ref LL_SYSCFG_EXTI_PORTE |
AnnaBridge | 145:64910690c574 | 763 | * @arg @ref LL_SYSCFG_EXTI_PORTF (*) |
AnnaBridge | 145:64910690c574 | 764 | * @arg @ref LL_SYSCFG_EXTI_PORTG (*) |
AnnaBridge | 145:64910690c574 | 765 | * @arg @ref LL_SYSCFG_EXTI_PORTH |
AnnaBridge | 145:64910690c574 | 766 | * @arg @ref LL_SYSCFG_EXTI_PORTI (*) |
AnnaBridge | 145:64910690c574 | 767 | * |
AnnaBridge | 145:64910690c574 | 768 | * (*) value not defined in all devices |
AnnaBridge | 145:64910690c574 | 769 | * @param Line This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 770 | * @arg @ref LL_SYSCFG_EXTI_LINE0 |
AnnaBridge | 145:64910690c574 | 771 | * @arg @ref LL_SYSCFG_EXTI_LINE1 |
AnnaBridge | 145:64910690c574 | 772 | * @arg @ref LL_SYSCFG_EXTI_LINE2 |
AnnaBridge | 145:64910690c574 | 773 | * @arg @ref LL_SYSCFG_EXTI_LINE3 |
AnnaBridge | 145:64910690c574 | 774 | * @arg @ref LL_SYSCFG_EXTI_LINE4 |
AnnaBridge | 145:64910690c574 | 775 | * @arg @ref LL_SYSCFG_EXTI_LINE5 |
AnnaBridge | 145:64910690c574 | 776 | * @arg @ref LL_SYSCFG_EXTI_LINE6 |
AnnaBridge | 145:64910690c574 | 777 | * @arg @ref LL_SYSCFG_EXTI_LINE7 |
AnnaBridge | 145:64910690c574 | 778 | * @arg @ref LL_SYSCFG_EXTI_LINE8 |
AnnaBridge | 145:64910690c574 | 779 | * @arg @ref LL_SYSCFG_EXTI_LINE9 |
AnnaBridge | 145:64910690c574 | 780 | * @arg @ref LL_SYSCFG_EXTI_LINE10 |
AnnaBridge | 145:64910690c574 | 781 | * @arg @ref LL_SYSCFG_EXTI_LINE11 |
AnnaBridge | 145:64910690c574 | 782 | * @arg @ref LL_SYSCFG_EXTI_LINE12 |
AnnaBridge | 145:64910690c574 | 783 | * @arg @ref LL_SYSCFG_EXTI_LINE13 |
AnnaBridge | 145:64910690c574 | 784 | * @arg @ref LL_SYSCFG_EXTI_LINE14 |
AnnaBridge | 145:64910690c574 | 785 | * @arg @ref LL_SYSCFG_EXTI_LINE15 |
AnnaBridge | 145:64910690c574 | 786 | * @retval None |
AnnaBridge | 145:64910690c574 | 787 | */ |
AnnaBridge | 145:64910690c574 | 788 | __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) |
AnnaBridge | 145:64910690c574 | 789 | { |
AnnaBridge | 145:64910690c574 | 790 | MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U))); |
AnnaBridge | 145:64910690c574 | 791 | } |
AnnaBridge | 145:64910690c574 | 792 | |
AnnaBridge | 145:64910690c574 | 793 | /** |
AnnaBridge | 145:64910690c574 | 794 | * @brief Get the configured defined for specific EXTI Line |
AnnaBridge | 145:64910690c574 | 795 | * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n |
AnnaBridge | 145:64910690c574 | 796 | * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n |
AnnaBridge | 145:64910690c574 | 797 | * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n |
AnnaBridge | 145:64910690c574 | 798 | * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource |
AnnaBridge | 145:64910690c574 | 799 | * @param Line This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 800 | * @arg @ref LL_SYSCFG_EXTI_LINE0 |
AnnaBridge | 145:64910690c574 | 801 | * @arg @ref LL_SYSCFG_EXTI_LINE1 |
AnnaBridge | 145:64910690c574 | 802 | * @arg @ref LL_SYSCFG_EXTI_LINE2 |
AnnaBridge | 145:64910690c574 | 803 | * @arg @ref LL_SYSCFG_EXTI_LINE3 |
AnnaBridge | 145:64910690c574 | 804 | * @arg @ref LL_SYSCFG_EXTI_LINE4 |
AnnaBridge | 145:64910690c574 | 805 | * @arg @ref LL_SYSCFG_EXTI_LINE5 |
AnnaBridge | 145:64910690c574 | 806 | * @arg @ref LL_SYSCFG_EXTI_LINE6 |
AnnaBridge | 145:64910690c574 | 807 | * @arg @ref LL_SYSCFG_EXTI_LINE7 |
AnnaBridge | 145:64910690c574 | 808 | * @arg @ref LL_SYSCFG_EXTI_LINE8 |
AnnaBridge | 145:64910690c574 | 809 | * @arg @ref LL_SYSCFG_EXTI_LINE9 |
AnnaBridge | 145:64910690c574 | 810 | * @arg @ref LL_SYSCFG_EXTI_LINE10 |
AnnaBridge | 145:64910690c574 | 811 | * @arg @ref LL_SYSCFG_EXTI_LINE11 |
AnnaBridge | 145:64910690c574 | 812 | * @arg @ref LL_SYSCFG_EXTI_LINE12 |
AnnaBridge | 145:64910690c574 | 813 | * @arg @ref LL_SYSCFG_EXTI_LINE13 |
AnnaBridge | 145:64910690c574 | 814 | * @arg @ref LL_SYSCFG_EXTI_LINE14 |
AnnaBridge | 145:64910690c574 | 815 | * @arg @ref LL_SYSCFG_EXTI_LINE15 |
AnnaBridge | 145:64910690c574 | 816 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 817 | * @arg @ref LL_SYSCFG_EXTI_PORTA |
AnnaBridge | 145:64910690c574 | 818 | * @arg @ref LL_SYSCFG_EXTI_PORTB |
AnnaBridge | 145:64910690c574 | 819 | * @arg @ref LL_SYSCFG_EXTI_PORTC |
AnnaBridge | 145:64910690c574 | 820 | * @arg @ref LL_SYSCFG_EXTI_PORTD |
AnnaBridge | 145:64910690c574 | 821 | * @arg @ref LL_SYSCFG_EXTI_PORTE |
AnnaBridge | 145:64910690c574 | 822 | * @arg @ref LL_SYSCFG_EXTI_PORTF (*) |
AnnaBridge | 145:64910690c574 | 823 | * @arg @ref LL_SYSCFG_EXTI_PORTG (*) |
AnnaBridge | 145:64910690c574 | 824 | * @arg @ref LL_SYSCFG_EXTI_PORTH |
AnnaBridge | 145:64910690c574 | 825 | * @arg @ref LL_SYSCFG_EXTI_PORTI (*) |
AnnaBridge | 145:64910690c574 | 826 | * |
AnnaBridge | 145:64910690c574 | 827 | * (*) value not defined in all devices |
AnnaBridge | 145:64910690c574 | 828 | */ |
AnnaBridge | 145:64910690c574 | 829 | __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) |
AnnaBridge | 145:64910690c574 | 830 | { |
AnnaBridge | 145:64910690c574 | 831 | return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U)); |
AnnaBridge | 145:64910690c574 | 832 | } |
AnnaBridge | 145:64910690c574 | 833 | |
AnnaBridge | 145:64910690c574 | 834 | /** |
AnnaBridge | 145:64910690c574 | 835 | * @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is |
AnnaBridge | 145:64910690c574 | 836 | * automatically cleared at the end of the SRAM2 erase operation.) |
AnnaBridge | 145:64910690c574 | 837 | * @note This bit is write-protected: setting this bit is possible only after the |
AnnaBridge | 145:64910690c574 | 838 | * correct key sequence is written in the SYSCFG_SKR register as described in |
AnnaBridge | 145:64910690c574 | 839 | * the Reference Manual. |
AnnaBridge | 145:64910690c574 | 840 | * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase |
AnnaBridge | 145:64910690c574 | 841 | * @retval None |
AnnaBridge | 145:64910690c574 | 842 | */ |
AnnaBridge | 145:64910690c574 | 843 | __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void) |
AnnaBridge | 145:64910690c574 | 844 | { |
AnnaBridge | 145:64910690c574 | 845 | /* Starts a hardware SRAM2 erase operation*/ |
AnnaBridge | 145:64910690c574 | 846 | SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER); |
AnnaBridge | 145:64910690c574 | 847 | } |
AnnaBridge | 145:64910690c574 | 848 | |
AnnaBridge | 145:64910690c574 | 849 | /** |
AnnaBridge | 145:64910690c574 | 850 | * @brief Check if SRAM2 erase operation is on going |
AnnaBridge | 145:64910690c574 | 851 | * @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing |
AnnaBridge | 145:64910690c574 | 852 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 853 | */ |
AnnaBridge | 145:64910690c574 | 854 | __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void) |
AnnaBridge | 145:64910690c574 | 855 | { |
AnnaBridge | 145:64910690c574 | 856 | return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY)); |
AnnaBridge | 145:64910690c574 | 857 | } |
AnnaBridge | 145:64910690c574 | 858 | |
AnnaBridge | 145:64910690c574 | 859 | /** |
AnnaBridge | 145:64910690c574 | 860 | * @brief Set connections to TIM1/8/15/16/17 Break inputs |
AnnaBridge | 145:64910690c574 | 861 | * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n |
AnnaBridge | 145:64910690c574 | 862 | * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n |
AnnaBridge | 145:64910690c574 | 863 | * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n |
AnnaBridge | 145:64910690c574 | 864 | * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs |
AnnaBridge | 145:64910690c574 | 865 | * @param Break This parameter can be a combination of the following values: |
AnnaBridge | 145:64910690c574 | 866 | * @arg @ref LL_SYSCFG_TIMBREAK_ECC |
AnnaBridge | 145:64910690c574 | 867 | * @arg @ref LL_SYSCFG_TIMBREAK_PVD |
AnnaBridge | 145:64910690c574 | 868 | * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY |
AnnaBridge | 145:64910690c574 | 869 | * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP |
AnnaBridge | 145:64910690c574 | 870 | * @retval None |
AnnaBridge | 145:64910690c574 | 871 | */ |
AnnaBridge | 145:64910690c574 | 872 | __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) |
AnnaBridge | 145:64910690c574 | 873 | { |
AnnaBridge | 145:64910690c574 | 874 | MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break); |
AnnaBridge | 145:64910690c574 | 875 | } |
AnnaBridge | 145:64910690c574 | 876 | |
AnnaBridge | 145:64910690c574 | 877 | /** |
AnnaBridge | 145:64910690c574 | 878 | * @brief Get connections to TIM1/8/15/16/17 Break inputs |
AnnaBridge | 145:64910690c574 | 879 | * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n |
AnnaBridge | 145:64910690c574 | 880 | * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n |
AnnaBridge | 145:64910690c574 | 881 | * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n |
AnnaBridge | 145:64910690c574 | 882 | * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs |
AnnaBridge | 145:64910690c574 | 883 | * @retval Returned value can be can be a combination of the following values: |
AnnaBridge | 145:64910690c574 | 884 | * @arg @ref LL_SYSCFG_TIMBREAK_ECC |
AnnaBridge | 145:64910690c574 | 885 | * @arg @ref LL_SYSCFG_TIMBREAK_PVD |
AnnaBridge | 145:64910690c574 | 886 | * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY |
AnnaBridge | 145:64910690c574 | 887 | * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP |
AnnaBridge | 145:64910690c574 | 888 | */ |
AnnaBridge | 145:64910690c574 | 889 | __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) |
AnnaBridge | 145:64910690c574 | 890 | { |
AnnaBridge | 145:64910690c574 | 891 | return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL)); |
AnnaBridge | 145:64910690c574 | 892 | } |
AnnaBridge | 145:64910690c574 | 893 | |
AnnaBridge | 145:64910690c574 | 894 | /** |
AnnaBridge | 145:64910690c574 | 895 | * @brief Check if SRAM2 parity error detected |
AnnaBridge | 145:64910690c574 | 896 | * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP |
AnnaBridge | 145:64910690c574 | 897 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 898 | */ |
AnnaBridge | 145:64910690c574 | 899 | __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) |
AnnaBridge | 145:64910690c574 | 900 | { |
AnnaBridge | 145:64910690c574 | 901 | return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)); |
AnnaBridge | 145:64910690c574 | 902 | } |
AnnaBridge | 145:64910690c574 | 903 | |
AnnaBridge | 145:64910690c574 | 904 | /** |
AnnaBridge | 145:64910690c574 | 905 | * @brief Clear SRAM2 parity error flag |
AnnaBridge | 145:64910690c574 | 906 | * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP |
AnnaBridge | 145:64910690c574 | 907 | * @retval None |
AnnaBridge | 145:64910690c574 | 908 | */ |
AnnaBridge | 145:64910690c574 | 909 | __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) |
AnnaBridge | 145:64910690c574 | 910 | { |
AnnaBridge | 145:64910690c574 | 911 | SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF); |
AnnaBridge | 145:64910690c574 | 912 | } |
AnnaBridge | 145:64910690c574 | 913 | |
AnnaBridge | 145:64910690c574 | 914 | /** |
AnnaBridge | 145:64910690c574 | 915 | * @brief Enable SRAM2 page write protection for Pages in range 0 to 31 |
AnnaBridge | 145:64910690c574 | 916 | * @note Write protection is cleared only by a system reset |
AnnaBridge | 145:64910690c574 | 917 | * @rmtoll SYSCFG_SWPR PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31 |
AnnaBridge | 145:64910690c574 | 918 | * @param SRAM2WRP This parameter can be a combination of the following values: |
AnnaBridge | 145:64910690c574 | 919 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0 |
AnnaBridge | 145:64910690c574 | 920 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1 |
AnnaBridge | 145:64910690c574 | 921 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2 |
AnnaBridge | 145:64910690c574 | 922 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3 |
AnnaBridge | 145:64910690c574 | 923 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4 |
AnnaBridge | 145:64910690c574 | 924 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5 |
AnnaBridge | 145:64910690c574 | 925 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6 |
AnnaBridge | 145:64910690c574 | 926 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7 |
AnnaBridge | 145:64910690c574 | 927 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8 |
AnnaBridge | 145:64910690c574 | 928 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9 |
AnnaBridge | 145:64910690c574 | 929 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10 |
AnnaBridge | 145:64910690c574 | 930 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11 |
AnnaBridge | 145:64910690c574 | 931 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12 |
AnnaBridge | 145:64910690c574 | 932 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13 |
AnnaBridge | 145:64910690c574 | 933 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14 |
AnnaBridge | 145:64910690c574 | 934 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15 |
AnnaBridge | 145:64910690c574 | 935 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*) |
AnnaBridge | 145:64910690c574 | 936 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*) |
AnnaBridge | 145:64910690c574 | 937 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*) |
AnnaBridge | 145:64910690c574 | 938 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*) |
AnnaBridge | 145:64910690c574 | 939 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*) |
AnnaBridge | 145:64910690c574 | 940 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*) |
AnnaBridge | 145:64910690c574 | 941 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*) |
AnnaBridge | 145:64910690c574 | 942 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*) |
AnnaBridge | 145:64910690c574 | 943 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*) |
AnnaBridge | 145:64910690c574 | 944 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*) |
AnnaBridge | 145:64910690c574 | 945 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*) |
AnnaBridge | 145:64910690c574 | 946 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*) |
AnnaBridge | 145:64910690c574 | 947 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*) |
AnnaBridge | 145:64910690c574 | 948 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*) |
AnnaBridge | 145:64910690c574 | 949 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*) |
AnnaBridge | 145:64910690c574 | 950 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*) |
AnnaBridge | 145:64910690c574 | 951 | * |
AnnaBridge | 145:64910690c574 | 952 | * (*) value not defined in all devices |
AnnaBridge | 145:64910690c574 | 953 | * @retval None |
AnnaBridge | 145:64910690c574 | 954 | */ |
AnnaBridge | 145:64910690c574 | 955 | /* Legacy define */ |
AnnaBridge | 145:64910690c574 | 956 | #define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31 |
AnnaBridge | 145:64910690c574 | 957 | __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP) |
AnnaBridge | 145:64910690c574 | 958 | { |
AnnaBridge | 145:64910690c574 | 959 | SET_BIT(SYSCFG->SWPR, SRAM2WRP); |
AnnaBridge | 145:64910690c574 | 960 | } |
AnnaBridge | 145:64910690c574 | 961 | |
AnnaBridge | 145:64910690c574 | 962 | #if defined(SYSCFG_SWPR2_PAGE63) |
AnnaBridge | 145:64910690c574 | 963 | /** |
AnnaBridge | 145:64910690c574 | 964 | * @brief Enable SRAM2 page write protection for Pages in range 32 to 63 |
AnnaBridge | 145:64910690c574 | 965 | * @note Write protection is cleared only by a system reset |
AnnaBridge | 145:64910690c574 | 966 | * @rmtoll SYSCFG_SWPR2 PxWP LL_SYSCFG_EnableSRAM2PageWRP_32_63 |
AnnaBridge | 145:64910690c574 | 967 | * @param SRAM2WRP This parameter can be a combination of the following values: |
AnnaBridge | 145:64910690c574 | 968 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32 (*) |
AnnaBridge | 145:64910690c574 | 969 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33 (*) |
AnnaBridge | 145:64910690c574 | 970 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34 (*) |
AnnaBridge | 145:64910690c574 | 971 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35 (*) |
AnnaBridge | 145:64910690c574 | 972 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36 (*) |
AnnaBridge | 145:64910690c574 | 973 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37 (*) |
AnnaBridge | 145:64910690c574 | 974 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38 (*) |
AnnaBridge | 145:64910690c574 | 975 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39 (*) |
AnnaBridge | 145:64910690c574 | 976 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40 (*) |
AnnaBridge | 145:64910690c574 | 977 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41 (*) |
AnnaBridge | 145:64910690c574 | 978 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42 (*) |
AnnaBridge | 145:64910690c574 | 979 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43 (*) |
AnnaBridge | 145:64910690c574 | 980 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44 (*) |
AnnaBridge | 145:64910690c574 | 981 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45 (*) |
AnnaBridge | 145:64910690c574 | 982 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46 (*) |
AnnaBridge | 145:64910690c574 | 983 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47 (*) |
AnnaBridge | 145:64910690c574 | 984 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48 (*) |
AnnaBridge | 145:64910690c574 | 985 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49 (*) |
AnnaBridge | 145:64910690c574 | 986 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50 (*) |
AnnaBridge | 145:64910690c574 | 987 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51 (*) |
AnnaBridge | 145:64910690c574 | 988 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52 (*) |
AnnaBridge | 145:64910690c574 | 989 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53 (*) |
AnnaBridge | 145:64910690c574 | 990 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54 (*) |
AnnaBridge | 145:64910690c574 | 991 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55 (*) |
AnnaBridge | 145:64910690c574 | 992 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56 (*) |
AnnaBridge | 145:64910690c574 | 993 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57 (*) |
AnnaBridge | 145:64910690c574 | 994 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58 (*) |
AnnaBridge | 145:64910690c574 | 995 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59 (*) |
AnnaBridge | 145:64910690c574 | 996 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60 (*) |
AnnaBridge | 145:64910690c574 | 997 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61 (*) |
AnnaBridge | 145:64910690c574 | 998 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62 (*) |
AnnaBridge | 145:64910690c574 | 999 | * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63 (*) |
AnnaBridge | 145:64910690c574 | 1000 | * |
AnnaBridge | 145:64910690c574 | 1001 | * (*) value not defined in all devices |
AnnaBridge | 145:64910690c574 | 1002 | * @retval None |
AnnaBridge | 145:64910690c574 | 1003 | */ |
AnnaBridge | 145:64910690c574 | 1004 | __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP) |
AnnaBridge | 145:64910690c574 | 1005 | { |
AnnaBridge | 145:64910690c574 | 1006 | SET_BIT(SYSCFG->SWPR2, SRAM2WRP); |
AnnaBridge | 145:64910690c574 | 1007 | } |
AnnaBridge | 145:64910690c574 | 1008 | #endif /* SYSCFG_SWPR2_PAGE63 */ |
AnnaBridge | 145:64910690c574 | 1009 | |
AnnaBridge | 145:64910690c574 | 1010 | /** |
AnnaBridge | 145:64910690c574 | 1011 | * @brief SRAM2 page write protection lock prior to erase |
AnnaBridge | 145:64910690c574 | 1012 | * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP |
AnnaBridge | 145:64910690c574 | 1013 | * @retval None |
AnnaBridge | 145:64910690c574 | 1014 | */ |
AnnaBridge | 145:64910690c574 | 1015 | __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void) |
AnnaBridge | 145:64910690c574 | 1016 | { |
AnnaBridge | 145:64910690c574 | 1017 | /* Writing a wrong key reactivates the write protection */ |
AnnaBridge | 145:64910690c574 | 1018 | WRITE_REG(SYSCFG->SKR, 0x00); |
AnnaBridge | 145:64910690c574 | 1019 | } |
AnnaBridge | 145:64910690c574 | 1020 | |
AnnaBridge | 145:64910690c574 | 1021 | /** |
AnnaBridge | 145:64910690c574 | 1022 | * @brief SRAM2 page write protection unlock prior to erase |
AnnaBridge | 145:64910690c574 | 1023 | * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP |
AnnaBridge | 145:64910690c574 | 1024 | * @retval None |
AnnaBridge | 145:64910690c574 | 1025 | */ |
AnnaBridge | 145:64910690c574 | 1026 | __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void) |
AnnaBridge | 145:64910690c574 | 1027 | { |
AnnaBridge | 145:64910690c574 | 1028 | /* unlock the write protection of the SRAM2ER bit */ |
AnnaBridge | 145:64910690c574 | 1029 | WRITE_REG(SYSCFG->SKR, 0xCA); |
AnnaBridge | 145:64910690c574 | 1030 | WRITE_REG(SYSCFG->SKR, 0x53); |
AnnaBridge | 145:64910690c574 | 1031 | } |
AnnaBridge | 145:64910690c574 | 1032 | |
AnnaBridge | 145:64910690c574 | 1033 | /** |
AnnaBridge | 145:64910690c574 | 1034 | * @} |
AnnaBridge | 145:64910690c574 | 1035 | */ |
AnnaBridge | 145:64910690c574 | 1036 | |
AnnaBridge | 145:64910690c574 | 1037 | |
AnnaBridge | 145:64910690c574 | 1038 | /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU |
AnnaBridge | 145:64910690c574 | 1039 | * @{ |
AnnaBridge | 145:64910690c574 | 1040 | */ |
AnnaBridge | 145:64910690c574 | 1041 | |
AnnaBridge | 145:64910690c574 | 1042 | /** |
AnnaBridge | 145:64910690c574 | 1043 | * @brief Return the device identifier |
AnnaBridge | 145:64910690c574 | 1044 | * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID |
AnnaBridge | 145:64910690c574 | 1045 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415) |
AnnaBridge | 145:64910690c574 | 1046 | */ |
AnnaBridge | 145:64910690c574 | 1047 | __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) |
AnnaBridge | 145:64910690c574 | 1048 | { |
AnnaBridge | 145:64910690c574 | 1049 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); |
AnnaBridge | 145:64910690c574 | 1050 | } |
AnnaBridge | 145:64910690c574 | 1051 | |
AnnaBridge | 145:64910690c574 | 1052 | /** |
AnnaBridge | 145:64910690c574 | 1053 | * @brief Return the device revision identifier |
AnnaBridge | 145:64910690c574 | 1054 | * @note This field indicates the revision of the device. |
AnnaBridge | 145:64910690c574 | 1055 | * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID |
AnnaBridge | 145:64910690c574 | 1056 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF |
AnnaBridge | 145:64910690c574 | 1057 | */ |
AnnaBridge | 145:64910690c574 | 1058 | __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) |
AnnaBridge | 145:64910690c574 | 1059 | { |
AnnaBridge | 161:aa5281ff4a02 | 1060 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); |
AnnaBridge | 145:64910690c574 | 1061 | } |
AnnaBridge | 145:64910690c574 | 1062 | |
AnnaBridge | 145:64910690c574 | 1063 | /** |
AnnaBridge | 145:64910690c574 | 1064 | * @brief Enable the Debug Module during SLEEP mode |
AnnaBridge | 145:64910690c574 | 1065 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode |
AnnaBridge | 145:64910690c574 | 1066 | * @retval None |
AnnaBridge | 145:64910690c574 | 1067 | */ |
AnnaBridge | 145:64910690c574 | 1068 | __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) |
AnnaBridge | 145:64910690c574 | 1069 | { |
AnnaBridge | 145:64910690c574 | 1070 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
AnnaBridge | 145:64910690c574 | 1071 | } |
AnnaBridge | 145:64910690c574 | 1072 | |
AnnaBridge | 145:64910690c574 | 1073 | /** |
AnnaBridge | 145:64910690c574 | 1074 | * @brief Disable the Debug Module during SLEEP mode |
AnnaBridge | 145:64910690c574 | 1075 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode |
AnnaBridge | 145:64910690c574 | 1076 | * @retval None |
AnnaBridge | 145:64910690c574 | 1077 | */ |
AnnaBridge | 145:64910690c574 | 1078 | __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) |
AnnaBridge | 145:64910690c574 | 1079 | { |
AnnaBridge | 145:64910690c574 | 1080 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
AnnaBridge | 145:64910690c574 | 1081 | } |
AnnaBridge | 145:64910690c574 | 1082 | |
AnnaBridge | 145:64910690c574 | 1083 | /** |
AnnaBridge | 145:64910690c574 | 1084 | * @brief Enable the Debug Module during STOP mode |
AnnaBridge | 145:64910690c574 | 1085 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode |
AnnaBridge | 145:64910690c574 | 1086 | * @retval None |
AnnaBridge | 145:64910690c574 | 1087 | */ |
AnnaBridge | 145:64910690c574 | 1088 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) |
AnnaBridge | 145:64910690c574 | 1089 | { |
AnnaBridge | 145:64910690c574 | 1090 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
AnnaBridge | 145:64910690c574 | 1091 | } |
AnnaBridge | 145:64910690c574 | 1092 | |
AnnaBridge | 145:64910690c574 | 1093 | /** |
AnnaBridge | 145:64910690c574 | 1094 | * @brief Disable the Debug Module during STOP mode |
AnnaBridge | 145:64910690c574 | 1095 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode |
AnnaBridge | 145:64910690c574 | 1096 | * @retval None |
AnnaBridge | 145:64910690c574 | 1097 | */ |
AnnaBridge | 145:64910690c574 | 1098 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) |
AnnaBridge | 145:64910690c574 | 1099 | { |
AnnaBridge | 145:64910690c574 | 1100 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
AnnaBridge | 145:64910690c574 | 1101 | } |
AnnaBridge | 145:64910690c574 | 1102 | |
AnnaBridge | 145:64910690c574 | 1103 | /** |
AnnaBridge | 145:64910690c574 | 1104 | * @brief Enable the Debug Module during STANDBY mode |
AnnaBridge | 145:64910690c574 | 1105 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode |
AnnaBridge | 145:64910690c574 | 1106 | * @retval None |
AnnaBridge | 145:64910690c574 | 1107 | */ |
AnnaBridge | 145:64910690c574 | 1108 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) |
AnnaBridge | 145:64910690c574 | 1109 | { |
AnnaBridge | 145:64910690c574 | 1110 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
AnnaBridge | 145:64910690c574 | 1111 | } |
AnnaBridge | 145:64910690c574 | 1112 | |
AnnaBridge | 145:64910690c574 | 1113 | /** |
AnnaBridge | 145:64910690c574 | 1114 | * @brief Disable the Debug Module during STANDBY mode |
AnnaBridge | 145:64910690c574 | 1115 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode |
AnnaBridge | 145:64910690c574 | 1116 | * @retval None |
AnnaBridge | 145:64910690c574 | 1117 | */ |
AnnaBridge | 145:64910690c574 | 1118 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) |
AnnaBridge | 145:64910690c574 | 1119 | { |
AnnaBridge | 145:64910690c574 | 1120 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
AnnaBridge | 145:64910690c574 | 1121 | } |
AnnaBridge | 145:64910690c574 | 1122 | |
AnnaBridge | 145:64910690c574 | 1123 | /** |
AnnaBridge | 145:64910690c574 | 1124 | * @brief Set Trace pin assignment control |
AnnaBridge | 145:64910690c574 | 1125 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n |
AnnaBridge | 145:64910690c574 | 1126 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment |
AnnaBridge | 145:64910690c574 | 1127 | * @param PinAssignment This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1128 | * @arg @ref LL_DBGMCU_TRACE_NONE |
AnnaBridge | 145:64910690c574 | 1129 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
AnnaBridge | 145:64910690c574 | 1130 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
AnnaBridge | 145:64910690c574 | 1131 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
AnnaBridge | 145:64910690c574 | 1132 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
AnnaBridge | 145:64910690c574 | 1133 | * @retval None |
AnnaBridge | 145:64910690c574 | 1134 | */ |
AnnaBridge | 145:64910690c574 | 1135 | __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) |
AnnaBridge | 145:64910690c574 | 1136 | { |
AnnaBridge | 145:64910690c574 | 1137 | MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); |
AnnaBridge | 145:64910690c574 | 1138 | } |
AnnaBridge | 145:64910690c574 | 1139 | |
AnnaBridge | 145:64910690c574 | 1140 | /** |
AnnaBridge | 145:64910690c574 | 1141 | * @brief Get Trace pin assignment control |
AnnaBridge | 145:64910690c574 | 1142 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n |
AnnaBridge | 145:64910690c574 | 1143 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment |
AnnaBridge | 145:64910690c574 | 1144 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1145 | * @arg @ref LL_DBGMCU_TRACE_NONE |
AnnaBridge | 145:64910690c574 | 1146 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
AnnaBridge | 145:64910690c574 | 1147 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
AnnaBridge | 145:64910690c574 | 1148 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
AnnaBridge | 145:64910690c574 | 1149 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
AnnaBridge | 145:64910690c574 | 1150 | */ |
AnnaBridge | 145:64910690c574 | 1151 | __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) |
AnnaBridge | 145:64910690c574 | 1152 | { |
AnnaBridge | 145:64910690c574 | 1153 | return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); |
AnnaBridge | 145:64910690c574 | 1154 | } |
AnnaBridge | 145:64910690c574 | 1155 | |
AnnaBridge | 145:64910690c574 | 1156 | /** |
AnnaBridge | 145:64910690c574 | 1157 | * @brief Freeze APB1 peripherals (group1 peripherals) |
AnnaBridge | 145:64910690c574 | 1158 | * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph |
AnnaBridge | 145:64910690c574 | 1159 | * @param Periphs This parameter can be a combination of the following values: |
AnnaBridge | 145:64910690c574 | 1160 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
AnnaBridge | 145:64910690c574 | 1161 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) |
AnnaBridge | 145:64910690c574 | 1162 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) |
AnnaBridge | 145:64910690c574 | 1163 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) |
AnnaBridge | 145:64910690c574 | 1164 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
AnnaBridge | 145:64910690c574 | 1165 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) |
AnnaBridge | 145:64910690c574 | 1166 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP |
AnnaBridge | 145:64910690c574 | 1167 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
AnnaBridge | 145:64910690c574 | 1168 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
AnnaBridge | 145:64910690c574 | 1169 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
AnnaBridge | 145:64910690c574 | 1170 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) |
AnnaBridge | 145:64910690c574 | 1171 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP |
AnnaBridge | 145:64910690c574 | 1172 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP |
AnnaBridge | 145:64910690c574 | 1173 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
AnnaBridge | 145:64910690c574 | 1174 | * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP |
AnnaBridge | 145:64910690c574 | 1175 | * |
AnnaBridge | 145:64910690c574 | 1176 | * (*) value not defined in all devices. |
AnnaBridge | 145:64910690c574 | 1177 | * @retval None |
AnnaBridge | 145:64910690c574 | 1178 | */ |
AnnaBridge | 145:64910690c574 | 1179 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) |
AnnaBridge | 145:64910690c574 | 1180 | { |
AnnaBridge | 145:64910690c574 | 1181 | SET_BIT(DBGMCU->APB1FZR1, Periphs); |
AnnaBridge | 145:64910690c574 | 1182 | } |
AnnaBridge | 145:64910690c574 | 1183 | |
AnnaBridge | 145:64910690c574 | 1184 | /** |
AnnaBridge | 145:64910690c574 | 1185 | * @brief Freeze APB1 peripherals (group2 peripherals) |
AnnaBridge | 145:64910690c574 | 1186 | * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph |
AnnaBridge | 145:64910690c574 | 1187 | * @param Periphs This parameter can be a combination of the following values: |
AnnaBridge | 145:64910690c574 | 1188 | * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*) |
AnnaBridge | 145:64910690c574 | 1189 | * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP |
AnnaBridge | 145:64910690c574 | 1190 | * |
AnnaBridge | 145:64910690c574 | 1191 | * (*) value not defined in all devices. |
AnnaBridge | 145:64910690c574 | 1192 | * @retval None |
AnnaBridge | 145:64910690c574 | 1193 | */ |
AnnaBridge | 145:64910690c574 | 1194 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) |
AnnaBridge | 145:64910690c574 | 1195 | { |
AnnaBridge | 145:64910690c574 | 1196 | SET_BIT(DBGMCU->APB1FZR2, Periphs); |
AnnaBridge | 145:64910690c574 | 1197 | } |
AnnaBridge | 145:64910690c574 | 1198 | |
AnnaBridge | 145:64910690c574 | 1199 | /** |
AnnaBridge | 145:64910690c574 | 1200 | * @brief Unfreeze APB1 peripherals (group1 peripherals) |
AnnaBridge | 145:64910690c574 | 1201 | * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph |
AnnaBridge | 145:64910690c574 | 1202 | * @param Periphs This parameter can be a combination of the following values: |
AnnaBridge | 145:64910690c574 | 1203 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
AnnaBridge | 145:64910690c574 | 1204 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) |
AnnaBridge | 145:64910690c574 | 1205 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) |
AnnaBridge | 145:64910690c574 | 1206 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) |
AnnaBridge | 145:64910690c574 | 1207 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
AnnaBridge | 145:64910690c574 | 1208 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) |
AnnaBridge | 145:64910690c574 | 1209 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP |
AnnaBridge | 145:64910690c574 | 1210 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
AnnaBridge | 145:64910690c574 | 1211 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
AnnaBridge | 145:64910690c574 | 1212 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
AnnaBridge | 145:64910690c574 | 1213 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) |
AnnaBridge | 145:64910690c574 | 1214 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP |
AnnaBridge | 145:64910690c574 | 1215 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP |
AnnaBridge | 145:64910690c574 | 1216 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
AnnaBridge | 145:64910690c574 | 1217 | * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP |
AnnaBridge | 145:64910690c574 | 1218 | * |
AnnaBridge | 145:64910690c574 | 1219 | * (*) value not defined in all devices. |
AnnaBridge | 145:64910690c574 | 1220 | * @retval None |
AnnaBridge | 145:64910690c574 | 1221 | */ |
AnnaBridge | 145:64910690c574 | 1222 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) |
AnnaBridge | 145:64910690c574 | 1223 | { |
AnnaBridge | 145:64910690c574 | 1224 | CLEAR_BIT(DBGMCU->APB1FZR1, Periphs); |
AnnaBridge | 145:64910690c574 | 1225 | } |
AnnaBridge | 145:64910690c574 | 1226 | |
AnnaBridge | 145:64910690c574 | 1227 | /** |
AnnaBridge | 145:64910690c574 | 1228 | * @brief Unfreeze APB1 peripherals (group2 peripherals) |
AnnaBridge | 145:64910690c574 | 1229 | * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph |
AnnaBridge | 145:64910690c574 | 1230 | * @param Periphs This parameter can be a combination of the following values: |
AnnaBridge | 145:64910690c574 | 1231 | * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*) |
AnnaBridge | 145:64910690c574 | 1232 | * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP |
AnnaBridge | 145:64910690c574 | 1233 | * |
AnnaBridge | 145:64910690c574 | 1234 | * (*) value not defined in all devices. |
AnnaBridge | 145:64910690c574 | 1235 | * @retval None |
AnnaBridge | 145:64910690c574 | 1236 | */ |
AnnaBridge | 145:64910690c574 | 1237 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) |
AnnaBridge | 145:64910690c574 | 1238 | { |
AnnaBridge | 145:64910690c574 | 1239 | CLEAR_BIT(DBGMCU->APB1FZR2, Periphs); |
AnnaBridge | 145:64910690c574 | 1240 | } |
AnnaBridge | 145:64910690c574 | 1241 | |
AnnaBridge | 145:64910690c574 | 1242 | /** |
AnnaBridge | 145:64910690c574 | 1243 | * @brief Freeze APB2 peripherals |
AnnaBridge | 145:64910690c574 | 1244 | * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
AnnaBridge | 145:64910690c574 | 1245 | * @param Periphs This parameter can be a combination of the following values: |
AnnaBridge | 145:64910690c574 | 1246 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
AnnaBridge | 145:64910690c574 | 1247 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) |
AnnaBridge | 145:64910690c574 | 1248 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP |
AnnaBridge | 145:64910690c574 | 1249 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP |
AnnaBridge | 145:64910690c574 | 1250 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) |
AnnaBridge | 145:64910690c574 | 1251 | * |
AnnaBridge | 145:64910690c574 | 1252 | * (*) value not defined in all devices. |
AnnaBridge | 145:64910690c574 | 1253 | * @retval None |
AnnaBridge | 145:64910690c574 | 1254 | */ |
AnnaBridge | 145:64910690c574 | 1255 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) |
AnnaBridge | 145:64910690c574 | 1256 | { |
AnnaBridge | 145:64910690c574 | 1257 | SET_BIT(DBGMCU->APB2FZ, Periphs); |
AnnaBridge | 145:64910690c574 | 1258 | } |
AnnaBridge | 145:64910690c574 | 1259 | |
AnnaBridge | 145:64910690c574 | 1260 | /** |
AnnaBridge | 145:64910690c574 | 1261 | * @brief Unfreeze APB2 peripherals |
AnnaBridge | 145:64910690c574 | 1262 | * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph |
AnnaBridge | 145:64910690c574 | 1263 | * @param Periphs This parameter can be a combination of the following values: |
AnnaBridge | 145:64910690c574 | 1264 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
AnnaBridge | 145:64910690c574 | 1265 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) |
AnnaBridge | 145:64910690c574 | 1266 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP |
AnnaBridge | 145:64910690c574 | 1267 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP |
AnnaBridge | 145:64910690c574 | 1268 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) |
AnnaBridge | 145:64910690c574 | 1269 | * |
AnnaBridge | 145:64910690c574 | 1270 | * (*) value not defined in all devices. |
AnnaBridge | 145:64910690c574 | 1271 | * @retval None |
AnnaBridge | 145:64910690c574 | 1272 | */ |
AnnaBridge | 145:64910690c574 | 1273 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) |
AnnaBridge | 145:64910690c574 | 1274 | { |
AnnaBridge | 145:64910690c574 | 1275 | CLEAR_BIT(DBGMCU->APB2FZ, Periphs); |
AnnaBridge | 145:64910690c574 | 1276 | } |
AnnaBridge | 145:64910690c574 | 1277 | |
AnnaBridge | 145:64910690c574 | 1278 | /** |
AnnaBridge | 145:64910690c574 | 1279 | * @} |
AnnaBridge | 145:64910690c574 | 1280 | */ |
AnnaBridge | 145:64910690c574 | 1281 | |
AnnaBridge | 145:64910690c574 | 1282 | #if defined(VREFBUF) |
AnnaBridge | 145:64910690c574 | 1283 | /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF |
AnnaBridge | 145:64910690c574 | 1284 | * @{ |
AnnaBridge | 145:64910690c574 | 1285 | */ |
AnnaBridge | 145:64910690c574 | 1286 | |
AnnaBridge | 145:64910690c574 | 1287 | /** |
AnnaBridge | 145:64910690c574 | 1288 | * @brief Enable Internal voltage reference |
AnnaBridge | 145:64910690c574 | 1289 | * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable |
AnnaBridge | 145:64910690c574 | 1290 | * @retval None |
AnnaBridge | 145:64910690c574 | 1291 | */ |
AnnaBridge | 145:64910690c574 | 1292 | __STATIC_INLINE void LL_VREFBUF_Enable(void) |
AnnaBridge | 145:64910690c574 | 1293 | { |
AnnaBridge | 145:64910690c574 | 1294 | SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); |
AnnaBridge | 145:64910690c574 | 1295 | } |
AnnaBridge | 145:64910690c574 | 1296 | |
AnnaBridge | 145:64910690c574 | 1297 | /** |
AnnaBridge | 145:64910690c574 | 1298 | * @brief Disable Internal voltage reference |
AnnaBridge | 145:64910690c574 | 1299 | * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable |
AnnaBridge | 145:64910690c574 | 1300 | * @retval None |
AnnaBridge | 145:64910690c574 | 1301 | */ |
AnnaBridge | 145:64910690c574 | 1302 | __STATIC_INLINE void LL_VREFBUF_Disable(void) |
AnnaBridge | 145:64910690c574 | 1303 | { |
AnnaBridge | 145:64910690c574 | 1304 | CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); |
AnnaBridge | 145:64910690c574 | 1305 | } |
AnnaBridge | 145:64910690c574 | 1306 | |
AnnaBridge | 145:64910690c574 | 1307 | /** |
AnnaBridge | 145:64910690c574 | 1308 | * @brief Enable high impedance (VREF+pin is high impedance) |
AnnaBridge | 145:64910690c574 | 1309 | * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ |
AnnaBridge | 145:64910690c574 | 1310 | * @retval None |
AnnaBridge | 145:64910690c574 | 1311 | */ |
AnnaBridge | 145:64910690c574 | 1312 | __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void) |
AnnaBridge | 145:64910690c574 | 1313 | { |
AnnaBridge | 145:64910690c574 | 1314 | SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); |
AnnaBridge | 145:64910690c574 | 1315 | } |
AnnaBridge | 145:64910690c574 | 1316 | |
AnnaBridge | 145:64910690c574 | 1317 | /** |
AnnaBridge | 145:64910690c574 | 1318 | * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output) |
AnnaBridge | 145:64910690c574 | 1319 | * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ |
AnnaBridge | 145:64910690c574 | 1320 | * @retval None |
AnnaBridge | 145:64910690c574 | 1321 | */ |
AnnaBridge | 145:64910690c574 | 1322 | __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void) |
AnnaBridge | 145:64910690c574 | 1323 | { |
AnnaBridge | 145:64910690c574 | 1324 | CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); |
AnnaBridge | 145:64910690c574 | 1325 | } |
AnnaBridge | 145:64910690c574 | 1326 | |
AnnaBridge | 145:64910690c574 | 1327 | /** |
AnnaBridge | 145:64910690c574 | 1328 | * @brief Set the Voltage reference scale |
AnnaBridge | 145:64910690c574 | 1329 | * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling |
AnnaBridge | 145:64910690c574 | 1330 | * @param Scale This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1331 | * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 |
AnnaBridge | 145:64910690c574 | 1332 | * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 |
AnnaBridge | 145:64910690c574 | 1333 | * @retval None |
AnnaBridge | 145:64910690c574 | 1334 | */ |
AnnaBridge | 145:64910690c574 | 1335 | __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale) |
AnnaBridge | 145:64910690c574 | 1336 | { |
AnnaBridge | 145:64910690c574 | 1337 | MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale); |
AnnaBridge | 145:64910690c574 | 1338 | } |
AnnaBridge | 145:64910690c574 | 1339 | |
AnnaBridge | 145:64910690c574 | 1340 | /** |
AnnaBridge | 145:64910690c574 | 1341 | * @brief Get the Voltage reference scale |
AnnaBridge | 145:64910690c574 | 1342 | * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling |
AnnaBridge | 145:64910690c574 | 1343 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1344 | * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 |
AnnaBridge | 145:64910690c574 | 1345 | * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 |
AnnaBridge | 145:64910690c574 | 1346 | */ |
AnnaBridge | 145:64910690c574 | 1347 | __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) |
AnnaBridge | 145:64910690c574 | 1348 | { |
AnnaBridge | 145:64910690c574 | 1349 | return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS)); |
AnnaBridge | 145:64910690c574 | 1350 | } |
AnnaBridge | 145:64910690c574 | 1351 | |
AnnaBridge | 145:64910690c574 | 1352 | /** |
AnnaBridge | 145:64910690c574 | 1353 | * @brief Check if Voltage reference buffer is ready |
AnnaBridge | 145:64910690c574 | 1354 | * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady |
AnnaBridge | 145:64910690c574 | 1355 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1356 | */ |
AnnaBridge | 145:64910690c574 | 1357 | __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void) |
AnnaBridge | 145:64910690c574 | 1358 | { |
AnnaBridge | 145:64910690c574 | 1359 | return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)); |
AnnaBridge | 145:64910690c574 | 1360 | } |
AnnaBridge | 145:64910690c574 | 1361 | |
AnnaBridge | 145:64910690c574 | 1362 | /** |
AnnaBridge | 145:64910690c574 | 1363 | * @brief Get the trimming code for VREFBUF calibration |
AnnaBridge | 145:64910690c574 | 1364 | * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming |
AnnaBridge | 145:64910690c574 | 1365 | * @retval Between 0 and 0x3F |
AnnaBridge | 145:64910690c574 | 1366 | */ |
AnnaBridge | 145:64910690c574 | 1367 | __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) |
AnnaBridge | 145:64910690c574 | 1368 | { |
AnnaBridge | 145:64910690c574 | 1369 | return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM)); |
AnnaBridge | 145:64910690c574 | 1370 | } |
AnnaBridge | 145:64910690c574 | 1371 | |
AnnaBridge | 145:64910690c574 | 1372 | /** |
AnnaBridge | 145:64910690c574 | 1373 | * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage) |
AnnaBridge | 145:64910690c574 | 1374 | * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming |
AnnaBridge | 145:64910690c574 | 1375 | * @param Value Between 0 and 0x3F |
AnnaBridge | 145:64910690c574 | 1376 | * @retval None |
AnnaBridge | 145:64910690c574 | 1377 | */ |
AnnaBridge | 145:64910690c574 | 1378 | __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) |
AnnaBridge | 145:64910690c574 | 1379 | { |
AnnaBridge | 145:64910690c574 | 1380 | WRITE_REG(VREFBUF->CCR, Value); |
AnnaBridge | 145:64910690c574 | 1381 | } |
AnnaBridge | 145:64910690c574 | 1382 | |
AnnaBridge | 145:64910690c574 | 1383 | /** |
AnnaBridge | 145:64910690c574 | 1384 | * @} |
AnnaBridge | 145:64910690c574 | 1385 | */ |
AnnaBridge | 145:64910690c574 | 1386 | #endif /* VREFBUF */ |
AnnaBridge | 145:64910690c574 | 1387 | |
AnnaBridge | 145:64910690c574 | 1388 | /** @defgroup SYSTEM_LL_EF_FLASH FLASH |
AnnaBridge | 145:64910690c574 | 1389 | * @{ |
AnnaBridge | 145:64910690c574 | 1390 | */ |
AnnaBridge | 145:64910690c574 | 1391 | |
AnnaBridge | 145:64910690c574 | 1392 | /** |
AnnaBridge | 145:64910690c574 | 1393 | * @brief Set FLASH Latency |
AnnaBridge | 145:64910690c574 | 1394 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency |
AnnaBridge | 145:64910690c574 | 1395 | * @param Latency This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1396 | * @arg @ref LL_FLASH_LATENCY_0 |
AnnaBridge | 145:64910690c574 | 1397 | * @arg @ref LL_FLASH_LATENCY_1 |
AnnaBridge | 145:64910690c574 | 1398 | * @arg @ref LL_FLASH_LATENCY_2 |
AnnaBridge | 145:64910690c574 | 1399 | * @arg @ref LL_FLASH_LATENCY_3 |
AnnaBridge | 145:64910690c574 | 1400 | * @arg @ref LL_FLASH_LATENCY_4 |
AnnaBridge | 161:aa5281ff4a02 | 1401 | * @arg @ref LL_FLASH_LATENCY_5 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1402 | * @arg @ref LL_FLASH_LATENCY_6 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1403 | * @arg @ref LL_FLASH_LATENCY_7 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1404 | * @arg @ref LL_FLASH_LATENCY_8 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1405 | * @arg @ref LL_FLASH_LATENCY_9 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1406 | * @arg @ref LL_FLASH_LATENCY_10 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1407 | * @arg @ref LL_FLASH_LATENCY_11 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1408 | * @arg @ref LL_FLASH_LATENCY_12 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1409 | * @arg @ref LL_FLASH_LATENCY_13 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1410 | * @arg @ref LL_FLASH_LATENCY_14 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1411 | * @arg @ref LL_FLASH_LATENCY_15 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1412 | * |
AnnaBridge | 161:aa5281ff4a02 | 1413 | * (*) value not defined in all devices. |
AnnaBridge | 145:64910690c574 | 1414 | * @retval None |
AnnaBridge | 145:64910690c574 | 1415 | */ |
AnnaBridge | 145:64910690c574 | 1416 | __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) |
AnnaBridge | 145:64910690c574 | 1417 | { |
AnnaBridge | 145:64910690c574 | 1418 | MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); |
AnnaBridge | 145:64910690c574 | 1419 | } |
AnnaBridge | 145:64910690c574 | 1420 | |
AnnaBridge | 145:64910690c574 | 1421 | /** |
AnnaBridge | 145:64910690c574 | 1422 | * @brief Get FLASH Latency |
AnnaBridge | 145:64910690c574 | 1423 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency |
AnnaBridge | 145:64910690c574 | 1424 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1425 | * @arg @ref LL_FLASH_LATENCY_0 |
AnnaBridge | 145:64910690c574 | 1426 | * @arg @ref LL_FLASH_LATENCY_1 |
AnnaBridge | 145:64910690c574 | 1427 | * @arg @ref LL_FLASH_LATENCY_2 |
AnnaBridge | 145:64910690c574 | 1428 | * @arg @ref LL_FLASH_LATENCY_3 |
AnnaBridge | 145:64910690c574 | 1429 | * @arg @ref LL_FLASH_LATENCY_4 |
AnnaBridge | 161:aa5281ff4a02 | 1430 | * @arg @ref LL_FLASH_LATENCY_5 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1431 | * @arg @ref LL_FLASH_LATENCY_6 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1432 | * @arg @ref LL_FLASH_LATENCY_7 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1433 | * @arg @ref LL_FLASH_LATENCY_8 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1434 | * @arg @ref LL_FLASH_LATENCY_9 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1435 | * @arg @ref LL_FLASH_LATENCY_10 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1436 | * @arg @ref LL_FLASH_LATENCY_11 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1437 | * @arg @ref LL_FLASH_LATENCY_12 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1438 | * @arg @ref LL_FLASH_LATENCY_13 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1439 | * @arg @ref LL_FLASH_LATENCY_14 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1440 | * @arg @ref LL_FLASH_LATENCY_15 (*) |
AnnaBridge | 161:aa5281ff4a02 | 1441 | * |
AnnaBridge | 161:aa5281ff4a02 | 1442 | * (*) value not defined in all devices. |
AnnaBridge | 145:64910690c574 | 1443 | */ |
AnnaBridge | 145:64910690c574 | 1444 | __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) |
AnnaBridge | 145:64910690c574 | 1445 | { |
AnnaBridge | 145:64910690c574 | 1446 | return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); |
AnnaBridge | 145:64910690c574 | 1447 | } |
AnnaBridge | 145:64910690c574 | 1448 | |
AnnaBridge | 145:64910690c574 | 1449 | /** |
AnnaBridge | 145:64910690c574 | 1450 | * @brief Enable Prefetch |
AnnaBridge | 145:64910690c574 | 1451 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch |
AnnaBridge | 145:64910690c574 | 1452 | * @retval None |
AnnaBridge | 145:64910690c574 | 1453 | */ |
AnnaBridge | 145:64910690c574 | 1454 | __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) |
AnnaBridge | 145:64910690c574 | 1455 | { |
AnnaBridge | 145:64910690c574 | 1456 | SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); |
AnnaBridge | 145:64910690c574 | 1457 | } |
AnnaBridge | 145:64910690c574 | 1458 | |
AnnaBridge | 145:64910690c574 | 1459 | /** |
AnnaBridge | 145:64910690c574 | 1460 | * @brief Disable Prefetch |
AnnaBridge | 145:64910690c574 | 1461 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch |
AnnaBridge | 145:64910690c574 | 1462 | * @retval None |
AnnaBridge | 145:64910690c574 | 1463 | */ |
AnnaBridge | 145:64910690c574 | 1464 | __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) |
AnnaBridge | 145:64910690c574 | 1465 | { |
AnnaBridge | 145:64910690c574 | 1466 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); |
AnnaBridge | 145:64910690c574 | 1467 | } |
AnnaBridge | 145:64910690c574 | 1468 | |
AnnaBridge | 145:64910690c574 | 1469 | /** |
AnnaBridge | 145:64910690c574 | 1470 | * @brief Check if Prefetch buffer is enabled |
AnnaBridge | 145:64910690c574 | 1471 | * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled |
AnnaBridge | 145:64910690c574 | 1472 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1473 | */ |
AnnaBridge | 145:64910690c574 | 1474 | __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) |
AnnaBridge | 145:64910690c574 | 1475 | { |
AnnaBridge | 145:64910690c574 | 1476 | return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)); |
AnnaBridge | 145:64910690c574 | 1477 | } |
AnnaBridge | 145:64910690c574 | 1478 | |
AnnaBridge | 145:64910690c574 | 1479 | /** |
AnnaBridge | 145:64910690c574 | 1480 | * @brief Enable Instruction cache |
AnnaBridge | 145:64910690c574 | 1481 | * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache |
AnnaBridge | 145:64910690c574 | 1482 | * @retval None |
AnnaBridge | 145:64910690c574 | 1483 | */ |
AnnaBridge | 145:64910690c574 | 1484 | __STATIC_INLINE void LL_FLASH_EnableInstCache(void) |
AnnaBridge | 145:64910690c574 | 1485 | { |
AnnaBridge | 145:64910690c574 | 1486 | SET_BIT(FLASH->ACR, FLASH_ACR_ICEN); |
AnnaBridge | 145:64910690c574 | 1487 | } |
AnnaBridge | 145:64910690c574 | 1488 | |
AnnaBridge | 145:64910690c574 | 1489 | /** |
AnnaBridge | 145:64910690c574 | 1490 | * @brief Disable Instruction cache |
AnnaBridge | 145:64910690c574 | 1491 | * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache |
AnnaBridge | 145:64910690c574 | 1492 | * @retval None |
AnnaBridge | 145:64910690c574 | 1493 | */ |
AnnaBridge | 145:64910690c574 | 1494 | __STATIC_INLINE void LL_FLASH_DisableInstCache(void) |
AnnaBridge | 145:64910690c574 | 1495 | { |
AnnaBridge | 145:64910690c574 | 1496 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN); |
AnnaBridge | 145:64910690c574 | 1497 | } |
AnnaBridge | 145:64910690c574 | 1498 | |
AnnaBridge | 145:64910690c574 | 1499 | /** |
AnnaBridge | 145:64910690c574 | 1500 | * @brief Enable Data cache |
AnnaBridge | 145:64910690c574 | 1501 | * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache |
AnnaBridge | 145:64910690c574 | 1502 | * @retval None |
AnnaBridge | 145:64910690c574 | 1503 | */ |
AnnaBridge | 145:64910690c574 | 1504 | __STATIC_INLINE void LL_FLASH_EnableDataCache(void) |
AnnaBridge | 145:64910690c574 | 1505 | { |
AnnaBridge | 145:64910690c574 | 1506 | SET_BIT(FLASH->ACR, FLASH_ACR_DCEN); |
AnnaBridge | 145:64910690c574 | 1507 | } |
AnnaBridge | 145:64910690c574 | 1508 | |
AnnaBridge | 145:64910690c574 | 1509 | /** |
AnnaBridge | 145:64910690c574 | 1510 | * @brief Disable Data cache |
AnnaBridge | 145:64910690c574 | 1511 | * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache |
AnnaBridge | 145:64910690c574 | 1512 | * @retval None |
AnnaBridge | 145:64910690c574 | 1513 | */ |
AnnaBridge | 145:64910690c574 | 1514 | __STATIC_INLINE void LL_FLASH_DisableDataCache(void) |
AnnaBridge | 145:64910690c574 | 1515 | { |
AnnaBridge | 145:64910690c574 | 1516 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN); |
AnnaBridge | 145:64910690c574 | 1517 | } |
AnnaBridge | 145:64910690c574 | 1518 | |
AnnaBridge | 145:64910690c574 | 1519 | /** |
AnnaBridge | 145:64910690c574 | 1520 | * @brief Enable Instruction cache reset |
AnnaBridge | 145:64910690c574 | 1521 | * @note bit can be written only when the instruction cache is disabled |
AnnaBridge | 145:64910690c574 | 1522 | * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset |
AnnaBridge | 145:64910690c574 | 1523 | * @retval None |
AnnaBridge | 145:64910690c574 | 1524 | */ |
AnnaBridge | 145:64910690c574 | 1525 | __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void) |
AnnaBridge | 145:64910690c574 | 1526 | { |
AnnaBridge | 145:64910690c574 | 1527 | SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); |
AnnaBridge | 145:64910690c574 | 1528 | } |
AnnaBridge | 145:64910690c574 | 1529 | |
AnnaBridge | 145:64910690c574 | 1530 | /** |
AnnaBridge | 145:64910690c574 | 1531 | * @brief Disable Instruction cache reset |
AnnaBridge | 145:64910690c574 | 1532 | * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset |
AnnaBridge | 145:64910690c574 | 1533 | * @retval None |
AnnaBridge | 145:64910690c574 | 1534 | */ |
AnnaBridge | 145:64910690c574 | 1535 | __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void) |
AnnaBridge | 145:64910690c574 | 1536 | { |
AnnaBridge | 145:64910690c574 | 1537 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); |
AnnaBridge | 145:64910690c574 | 1538 | } |
AnnaBridge | 145:64910690c574 | 1539 | |
AnnaBridge | 145:64910690c574 | 1540 | /** |
AnnaBridge | 145:64910690c574 | 1541 | * @brief Enable Data cache reset |
AnnaBridge | 145:64910690c574 | 1542 | * @note bit can be written only when the data cache is disabled |
AnnaBridge | 145:64910690c574 | 1543 | * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset |
AnnaBridge | 145:64910690c574 | 1544 | * @retval None |
AnnaBridge | 145:64910690c574 | 1545 | */ |
AnnaBridge | 145:64910690c574 | 1546 | __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void) |
AnnaBridge | 145:64910690c574 | 1547 | { |
AnnaBridge | 145:64910690c574 | 1548 | SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); |
AnnaBridge | 145:64910690c574 | 1549 | } |
AnnaBridge | 145:64910690c574 | 1550 | |
AnnaBridge | 145:64910690c574 | 1551 | /** |
AnnaBridge | 145:64910690c574 | 1552 | * @brief Disable Data cache reset |
AnnaBridge | 145:64910690c574 | 1553 | * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset |
AnnaBridge | 145:64910690c574 | 1554 | * @retval None |
AnnaBridge | 145:64910690c574 | 1555 | */ |
AnnaBridge | 145:64910690c574 | 1556 | __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void) |
AnnaBridge | 145:64910690c574 | 1557 | { |
AnnaBridge | 145:64910690c574 | 1558 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); |
AnnaBridge | 145:64910690c574 | 1559 | } |
AnnaBridge | 145:64910690c574 | 1560 | |
AnnaBridge | 145:64910690c574 | 1561 | /** |
AnnaBridge | 145:64910690c574 | 1562 | * @brief Enable Flash Power-down mode during run mode or Low-power run mode |
AnnaBridge | 145:64910690c574 | 1563 | * @note Flash memory can be put in power-down mode only when the code is executed |
AnnaBridge | 145:64910690c574 | 1564 | * from RAM |
AnnaBridge | 145:64910690c574 | 1565 | * @note Flash must not be accessed when power down is enabled |
AnnaBridge | 145:64910690c574 | 1566 | * @note Flash must not be put in power-down while a program or an erase operation |
AnnaBridge | 145:64910690c574 | 1567 | * is on-going |
AnnaBridge | 145:64910690c574 | 1568 | * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n |
AnnaBridge | 145:64910690c574 | 1569 | * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n |
AnnaBridge | 145:64910690c574 | 1570 | * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown |
AnnaBridge | 145:64910690c574 | 1571 | * @retval None |
AnnaBridge | 145:64910690c574 | 1572 | */ |
AnnaBridge | 145:64910690c574 | 1573 | __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) |
AnnaBridge | 145:64910690c574 | 1574 | { |
AnnaBridge | 145:64910690c574 | 1575 | /* Following values must be written consecutively to unlock the RUN_PD bit in |
AnnaBridge | 145:64910690c574 | 1576 | FLASH_ACR */ |
AnnaBridge | 145:64910690c574 | 1577 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); |
AnnaBridge | 145:64910690c574 | 1578 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); |
AnnaBridge | 145:64910690c574 | 1579 | SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); |
AnnaBridge | 145:64910690c574 | 1580 | } |
AnnaBridge | 145:64910690c574 | 1581 | |
AnnaBridge | 145:64910690c574 | 1582 | /** |
AnnaBridge | 145:64910690c574 | 1583 | * @brief Disable Flash Power-down mode during run mode or Low-power run mode |
AnnaBridge | 145:64910690c574 | 1584 | * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n |
AnnaBridge | 145:64910690c574 | 1585 | * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n |
AnnaBridge | 145:64910690c574 | 1586 | * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown |
AnnaBridge | 145:64910690c574 | 1587 | * @retval None |
AnnaBridge | 145:64910690c574 | 1588 | */ |
AnnaBridge | 145:64910690c574 | 1589 | __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void) |
AnnaBridge | 145:64910690c574 | 1590 | { |
AnnaBridge | 145:64910690c574 | 1591 | /* Following values must be written consecutively to unlock the RUN_PD bit in |
AnnaBridge | 145:64910690c574 | 1592 | FLASH_ACR */ |
AnnaBridge | 145:64910690c574 | 1593 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); |
AnnaBridge | 145:64910690c574 | 1594 | WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); |
AnnaBridge | 145:64910690c574 | 1595 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); |
AnnaBridge | 145:64910690c574 | 1596 | } |
AnnaBridge | 145:64910690c574 | 1597 | |
AnnaBridge | 145:64910690c574 | 1598 | /** |
AnnaBridge | 145:64910690c574 | 1599 | * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode |
AnnaBridge | 145:64910690c574 | 1600 | * @note Flash must not be put in power-down while a program or an erase operation |
AnnaBridge | 145:64910690c574 | 1601 | * is on-going |
AnnaBridge | 145:64910690c574 | 1602 | * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown |
AnnaBridge | 145:64910690c574 | 1603 | * @retval None |
AnnaBridge | 145:64910690c574 | 1604 | */ |
AnnaBridge | 145:64910690c574 | 1605 | __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) |
AnnaBridge | 145:64910690c574 | 1606 | { |
AnnaBridge | 145:64910690c574 | 1607 | SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); |
AnnaBridge | 145:64910690c574 | 1608 | } |
AnnaBridge | 145:64910690c574 | 1609 | |
AnnaBridge | 145:64910690c574 | 1610 | /** |
AnnaBridge | 145:64910690c574 | 1611 | * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode |
AnnaBridge | 145:64910690c574 | 1612 | * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown |
AnnaBridge | 145:64910690c574 | 1613 | * @retval None |
AnnaBridge | 145:64910690c574 | 1614 | */ |
AnnaBridge | 145:64910690c574 | 1615 | __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) |
AnnaBridge | 145:64910690c574 | 1616 | { |
AnnaBridge | 145:64910690c574 | 1617 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); |
AnnaBridge | 145:64910690c574 | 1618 | } |
AnnaBridge | 145:64910690c574 | 1619 | |
AnnaBridge | 145:64910690c574 | 1620 | /** |
AnnaBridge | 145:64910690c574 | 1621 | * @} |
AnnaBridge | 145:64910690c574 | 1622 | */ |
AnnaBridge | 145:64910690c574 | 1623 | |
AnnaBridge | 145:64910690c574 | 1624 | /** |
AnnaBridge | 145:64910690c574 | 1625 | * @} |
AnnaBridge | 145:64910690c574 | 1626 | */ |
AnnaBridge | 145:64910690c574 | 1627 | |
AnnaBridge | 145:64910690c574 | 1628 | /** |
AnnaBridge | 145:64910690c574 | 1629 | * @} |
AnnaBridge | 145:64910690c574 | 1630 | */ |
AnnaBridge | 145:64910690c574 | 1631 | |
AnnaBridge | 145:64910690c574 | 1632 | #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */ |
AnnaBridge | 145:64910690c574 | 1633 | |
AnnaBridge | 145:64910690c574 | 1634 | /** |
AnnaBridge | 145:64910690c574 | 1635 | * @} |
AnnaBridge | 145:64910690c574 | 1636 | */ |
AnnaBridge | 145:64910690c574 | 1637 | |
AnnaBridge | 145:64910690c574 | 1638 | #ifdef __cplusplus |
AnnaBridge | 145:64910690c574 | 1639 | } |
AnnaBridge | 145:64910690c574 | 1640 | #endif |
AnnaBridge | 145:64910690c574 | 1641 | |
AnnaBridge | 145:64910690c574 | 1642 | #endif /* __STM32L4xx_LL_SYSTEM_H */ |
AnnaBridge | 145:64910690c574 | 1643 | |
AnnaBridge | 145:64910690c574 | 1644 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |