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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_ll_sdmmc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_ll_sdmmc.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of SDMMC HAL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	172:65be27845400	10	*
AnnaBridge	172:65be27845400	11	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	12	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	13	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	14	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	15	*
AnnaBridge	172:65be27845400	16	******************************************************************************
AnnaBridge	172:65be27845400	17	*/
AnnaBridge	172:65be27845400	18
AnnaBridge	172:65be27845400	19	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	20	#ifndef STM32H7xx_LL_SDMMC_H
AnnaBridge	172:65be27845400	21	#define STM32H7xx_LL_SDMMC_H
AnnaBridge	172:65be27845400	22
AnnaBridge	172:65be27845400	23	#ifdef __cplusplus
AnnaBridge	172:65be27845400	24	extern "C" {
AnnaBridge	172:65be27845400	25	#endif
AnnaBridge	172:65be27845400	26
AnnaBridge	172:65be27845400	27	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	28	#include "stm32h7xx_hal_def.h"
AnnaBridge	172:65be27845400	29
AnnaBridge	172:65be27845400	30	/** @addtogroup STM32H7xx_Driver
AnnaBridge	172:65be27845400	31	* @{
AnnaBridge	172:65be27845400	32	*/
AnnaBridge	172:65be27845400	33
AnnaBridge	172:65be27845400	34	/** @addtogroup SDMMC_LL
AnnaBridge	172:65be27845400	35	* @{
AnnaBridge	172:65be27845400	36	*/
AnnaBridge	172:65be27845400	37
AnnaBridge	172:65be27845400	38	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	39	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
AnnaBridge	172:65be27845400	40	* @{
AnnaBridge	172:65be27845400	41	*/
AnnaBridge	172:65be27845400	42
AnnaBridge	172:65be27845400	43	/**
AnnaBridge	172:65be27845400	44	* @brief SDMMC Configuration Structure definition
AnnaBridge	172:65be27845400	45	*/
AnnaBridge	172:65be27845400	46	typedef struct
AnnaBridge	172:65be27845400	47	{
AnnaBridge	172:65be27845400	48	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
AnnaBridge	172:65be27845400	49	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
AnnaBridge	172:65be27845400	50
AnnaBridge	172:65be27845400	51	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
AnnaBridge	172:65be27845400	52	disabled when the bus is idle.
AnnaBridge	172:65be27845400	53	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
AnnaBridge	172:65be27845400	54
AnnaBridge	172:65be27845400	55	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
AnnaBridge	172:65be27845400	56	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
AnnaBridge	172:65be27845400	57
AnnaBridge	172:65be27845400	58	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
AnnaBridge	172:65be27845400	59	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
AnnaBridge	172:65be27845400	60
AnnaBridge	172:65be27845400	61	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
AnnaBridge	172:65be27845400	62	This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */
AnnaBridge	172:65be27845400	63
AnnaBridge	172:65be27845400	64	}SDMMC_InitTypeDef;
AnnaBridge	172:65be27845400	65
AnnaBridge	172:65be27845400	66
AnnaBridge	172:65be27845400	67	/**
AnnaBridge	172:65be27845400	68	* @brief SDMMC Command Control structure
AnnaBridge	172:65be27845400	69	*/
AnnaBridge	172:65be27845400	70	typedef struct
AnnaBridge	172:65be27845400	71	{
AnnaBridge	172:65be27845400	72	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
AnnaBridge	172:65be27845400	73	to a card as part of a command message. If a command
AnnaBridge	172:65be27845400	74	contains an argument, it must be loaded into this register
AnnaBridge	172:65be27845400	75	before writing the command to the command register. */
AnnaBridge	172:65be27845400	76
AnnaBridge	172:65be27845400	77	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
AnnaBridge	172:65be27845400	78	Max_Data = 64 */
AnnaBridge	172:65be27845400	79
AnnaBridge	172:65be27845400	80	uint32_t Response; /*!< Specifies the SDMMC response type.
AnnaBridge	172:65be27845400	81	This parameter can be a value of @ref SDMMC_LL_Response_Type */
AnnaBridge	172:65be27845400	82
AnnaBridge	172:65be27845400	83	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
AnnaBridge	172:65be27845400	84	enabled or disabled.
AnnaBridge	172:65be27845400	85	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
AnnaBridge	172:65be27845400	86
AnnaBridge	172:65be27845400	87	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
AnnaBridge	172:65be27845400	88	is enabled or disabled.
AnnaBridge	172:65be27845400	89	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
AnnaBridge	172:65be27845400	90	}SDMMC_CmdInitTypeDef;
AnnaBridge	172:65be27845400	91
AnnaBridge	172:65be27845400	92
AnnaBridge	172:65be27845400	93	/**
AnnaBridge	172:65be27845400	94	* @brief SDMMC Data Control structure
AnnaBridge	172:65be27845400	95	*/
AnnaBridge	172:65be27845400	96	typedef struct
AnnaBridge	172:65be27845400	97	{
AnnaBridge	172:65be27845400	98	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
AnnaBridge	172:65be27845400	99
AnnaBridge	172:65be27845400	100	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
AnnaBridge	172:65be27845400	101
AnnaBridge	172:65be27845400	102	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
AnnaBridge	172:65be27845400	103	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
AnnaBridge	172:65be27845400	104
AnnaBridge	172:65be27845400	105	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
AnnaBridge	172:65be27845400	106	is a read or write.
AnnaBridge	172:65be27845400	107	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
AnnaBridge	172:65be27845400	108
AnnaBridge	172:65be27845400	109	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
AnnaBridge	172:65be27845400	110	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
AnnaBridge	172:65be27845400	111
AnnaBridge	172:65be27845400	112	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
AnnaBridge	172:65be27845400	113	is enabled or disabled.
AnnaBridge	172:65be27845400	114	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
AnnaBridge	172:65be27845400	115	}SDMMC_DataInitTypeDef;
AnnaBridge	172:65be27845400	116
AnnaBridge	172:65be27845400	117	/**
AnnaBridge	172:65be27845400	118	* @}
AnnaBridge	172:65be27845400	119	*/
AnnaBridge	172:65be27845400	120
AnnaBridge	172:65be27845400	121	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	122	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
AnnaBridge	172:65be27845400	123	* @{
AnnaBridge	172:65be27845400	124	*/
AnnaBridge	172:65be27845400	125	#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /!< No error /
AnnaBridge	172:65be27845400	126	#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /!< Command response received (but CRC check failed) /
AnnaBridge	172:65be27845400	127	#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /!< Data block sent/received (CRC check failed) /
AnnaBridge	172:65be27845400	128	#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /!< Command response timeout /
AnnaBridge	172:65be27845400	129	#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /!< Data timeout /
AnnaBridge	172:65be27845400	130	#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /!< Transmit FIFO underrun /
AnnaBridge	172:65be27845400	131	#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /!< Receive FIFO overrun /
AnnaBridge	172:65be27845400	132	#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /!< Misaligned address /
AnnaBridge	172:65be27845400	133	#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
AnnaBridge	172:65be27845400	134	number of transferred bytes does not match the block length */
AnnaBridge	172:65be27845400	135	#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /!< An error in the sequence of erase command occurs /
AnnaBridge	172:65be27845400	136	#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /!< An invalid selection for erase groups /
AnnaBridge	172:65be27845400	137	#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /!< Attempt to program a write protect block /
AnnaBridge	172:65be27845400	138	#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
AnnaBridge	172:65be27845400	139	command or if there was an attempt to access a locked card */
AnnaBridge	172:65be27845400	140	#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /!< CRC check of the previous command failed /
AnnaBridge	172:65be27845400	141	#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /!< Command is not legal for the card state /
AnnaBridge	172:65be27845400	142	#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /!< Card internal ECC was applied but failed to correct the data /
AnnaBridge	172:65be27845400	143	#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /!< Internal card controller error /
AnnaBridge	172:65be27845400	144	#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /!< General or unknown error /
AnnaBridge	172:65be27845400	145	#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /!< The card could not sustain data reading in stream rmode /
AnnaBridge	172:65be27845400	146	#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /!< The card could not sustain data programming in stream mode /
AnnaBridge	172:65be27845400	147	#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /!< CID/CSD overwrite error /
AnnaBridge	172:65be27845400	148	#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /!< Only partial address space was erased /
AnnaBridge	172:65be27845400	149	#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /!< Command has been executed without using internal ECC /
AnnaBridge	172:65be27845400	150	#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
AnnaBridge	172:65be27845400	151	of erase sequence command was received */
AnnaBridge	172:65be27845400	152	#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /!< Error in sequence of authentication /
AnnaBridge	172:65be27845400	153	#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /!< Error in case of invalid voltage range /
AnnaBridge	172:65be27845400	154	#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /!< Error when addressed block is out of range /
AnnaBridge	172:65be27845400	155	#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /!< Error when command request is not applicable /
AnnaBridge	172:65be27845400	156	#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /!< the used parameter is not valid /
AnnaBridge	172:65be27845400	157	#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /!< Error when feature is not insupported /
AnnaBridge	172:65be27845400	158	#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /!< Error when transfer process is busy /
AnnaBridge	172:65be27845400	159	#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /!< Error while DMA transfer /
AnnaBridge	172:65be27845400	160	#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /!< Timeout error /
AnnaBridge	172:65be27845400	161
AnnaBridge	172:65be27845400	162	/**
AnnaBridge	172:65be27845400	163	* @brief SDMMC Commands Index
AnnaBridge	172:65be27845400	164	*/
AnnaBridge	172:65be27845400	165	#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /!< Resets the SD memory card. /
AnnaBridge	172:65be27845400	166	#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /!< Sends host capacity support information and activates the card's initialization process. /
AnnaBridge	172:65be27845400	167	#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /!< Asks any card connected to the host to send the CID numbers on the CMD line. /
AnnaBridge	172:65be27845400	168	#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /!< Asks the card to publish a new relative address (RCA). /
AnnaBridge	172:65be27845400	169	#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /!< Programs the DSR of all cards. /
AnnaBridge	172:65be27845400	170	#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
AnnaBridge	172:65be27845400	171	operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	172:65be27845400	172	#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /!< Checks switchable function (mode 0) and switch card function (mode 1). /
AnnaBridge	172:65be27845400	173	#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /!< Selects the card by its own relative address and gets deselected by any other address /
AnnaBridge	172:65be27845400	174	#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
AnnaBridge	172:65be27845400	175	and asks the card whether card supports voltage. */
AnnaBridge	172:65be27845400	176	#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /!< Addressed card sends its card specific data (CSD) on the CMD line. /
AnnaBridge	172:65be27845400	177	#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /!< Addressed card sends its card identification (CID) on the CMD line. /
AnnaBridge	172:65be27845400	178	#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /!< SD card Voltage switch to 1.8V mode. /
AnnaBridge	172:65be27845400	179	#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /!< Forces the card to stop transmission. /
AnnaBridge	172:65be27845400	180	#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /!< Addressed card sends its status register. /
AnnaBridge	172:65be27845400	181	#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /!< Reserved /
AnnaBridge	172:65be27845400	182	#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /!< Sends an addressed card into the inactive state. /
AnnaBridge	172:65be27845400	183	#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
AnnaBridge	172:65be27845400	184	(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
AnnaBridge	172:65be27845400	185	for SDHS and SDXC. */
AnnaBridge	172:65be27845400	186	#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	172:65be27845400	187	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	172:65be27845400	188	#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
AnnaBridge	172:65be27845400	189	STOP_TRANSMISSION command. */
AnnaBridge	172:65be27845400	190	#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /!< 64 bytes tuning pattern is sent for SDR50 and SDR104. /
AnnaBridge	172:65be27845400	191	#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /!< Speed class control command. /
AnnaBridge	172:65be27845400	192	#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /!< Specify block count for CMD18 and CMD25. /
AnnaBridge	172:65be27845400	193	#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	172:65be27845400	194	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	172:65be27845400	195	#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. /
AnnaBridge	172:65be27845400	196	#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /!< Reserved for manufacturers. /
AnnaBridge	172:65be27845400	197	#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /!< Programming of the programmable bits of the CSD. /
AnnaBridge	172:65be27845400	198	#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /!< Sets the write protection bit of the addressed group. /
AnnaBridge	172:65be27845400	199	#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /!< Clears the write protection bit of the addressed group. /
AnnaBridge	172:65be27845400	200	#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /!< Asks the card to send the status of the write protection bits. /
AnnaBridge	172:65be27845400	201	#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /!< Sets the address of the first write block to be erased. (For SD card only). /
AnnaBridge	172:65be27845400	202	#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /!< Sets the address of the last write block of the continuous range to be erased. /
AnnaBridge	172:65be27845400	203	#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
AnnaBridge	172:65be27845400	204	system set by switch function command (CMD6). */
AnnaBridge	172:65be27845400	205	#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
AnnaBridge	172:65be27845400	206	Reserved for each command system set by switch function command (CMD6). */
AnnaBridge	172:65be27845400	207	#define SDMMC_CMD_ERASE ((uint8_t)38U) /!< Reserved for SD security applications. /
AnnaBridge	172:65be27845400	208	#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /!< SD card doesn't support it (Reserved). /
AnnaBridge	172:65be27845400	209	#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /!< SD card doesn't support it (Reserved). /
AnnaBridge	172:65be27845400	210	#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
AnnaBridge	172:65be27845400	211	the SET_BLOCK_LEN command. */
AnnaBridge	172:65be27845400	212	#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
AnnaBridge	172:65be27845400	213	than a standard command. */
AnnaBridge	172:65be27845400	214	#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
AnnaBridge	172:65be27845400	215	for general purpose/application specific commands. */
AnnaBridge	172:65be27845400	216	#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /!< No command /
AnnaBridge	172:65be27845400	217
AnnaBridge	172:65be27845400	218	/**
AnnaBridge	172:65be27845400	219	* @brief Following commands are SD Card Specific commands.
AnnaBridge	172:65be27845400	220	* SDMMC_APP_CMD should be sent before sending these commands.
AnnaBridge	172:65be27845400	221	*/
AnnaBridge	172:65be27845400	222	#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
AnnaBridge	172:65be27845400	223	widths are given in SCR register. */
AnnaBridge	172:65be27845400	224	#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /!< (ACMD13) Sends the SD status. /
AnnaBridge	172:65be27845400	225	#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
AnnaBridge	172:65be27845400	226	32bit+CRC data block. */
AnnaBridge	172:65be27845400	227	#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
AnnaBridge	172:65be27845400	228	send its operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	172:65be27845400	229	#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card /
AnnaBridge	172:65be27845400	230	#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /!< Reads the SD Configuration Register (SCR). /
AnnaBridge	172:65be27845400	231	#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	172:65be27845400	232	#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	172:65be27845400	233
AnnaBridge	172:65be27845400	234	/**
AnnaBridge	172:65be27845400	235	* @brief Following commands are SD Card Specific security commands.
AnnaBridge	172:65be27845400	236	* SDMMC_CMD_APP_CMD should be sent before sending these commands.
AnnaBridge	172:65be27845400	237	*/
AnnaBridge	172:65be27845400	238	#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
AnnaBridge	172:65be27845400	239	#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
AnnaBridge	172:65be27845400	240	#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
AnnaBridge	172:65be27845400	241	#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
AnnaBridge	172:65be27845400	242	#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
AnnaBridge	172:65be27845400	243	#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
AnnaBridge	172:65be27845400	244	#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
AnnaBridge	172:65be27845400	245	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
AnnaBridge	172:65be27845400	246	#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
AnnaBridge	172:65be27845400	247	#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
AnnaBridge	172:65be27845400	248	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
AnnaBridge	172:65be27845400	249
AnnaBridge	172:65be27845400	250	/**
AnnaBridge	172:65be27845400	251	* @brief Masks for errors Card Status R1 (OCR Register)
AnnaBridge	172:65be27845400	252	*/
AnnaBridge	172:65be27845400	253	#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
AnnaBridge	172:65be27845400	254	#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
AnnaBridge	172:65be27845400	255	#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
AnnaBridge	172:65be27845400	256	#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
AnnaBridge	172:65be27845400	257	#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
AnnaBridge	172:65be27845400	258	#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
AnnaBridge	172:65be27845400	259	#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
AnnaBridge	172:65be27845400	260	#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
AnnaBridge	172:65be27845400	261	#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
AnnaBridge	172:65be27845400	262	#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
AnnaBridge	172:65be27845400	263	#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
AnnaBridge	172:65be27845400	264	#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
AnnaBridge	172:65be27845400	265	#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
AnnaBridge	172:65be27845400	266	#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
AnnaBridge	172:65be27845400	267	#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
AnnaBridge	172:65be27845400	268	#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
AnnaBridge	172:65be27845400	269	#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
AnnaBridge	172:65be27845400	270	#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
AnnaBridge	172:65be27845400	271	#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
AnnaBridge	172:65be27845400	272	#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
AnnaBridge	172:65be27845400	273
AnnaBridge	172:65be27845400	274	/**
AnnaBridge	172:65be27845400	275	* @brief Masks for R6 Response
AnnaBridge	172:65be27845400	276	*/
AnnaBridge	172:65be27845400	277	#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
AnnaBridge	172:65be27845400	278	#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
AnnaBridge	172:65be27845400	279	#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
AnnaBridge	172:65be27845400	280
AnnaBridge	172:65be27845400	281	#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
AnnaBridge	172:65be27845400	282	#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
AnnaBridge	172:65be27845400	283	#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	284	#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
AnnaBridge	172:65be27845400	285	#define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U)
AnnaBridge	172:65be27845400	286	#define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U)
AnnaBridge	172:65be27845400	287	#define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U)
AnnaBridge	172:65be27845400	288	#define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U)
AnnaBridge	172:65be27845400	289
AnnaBridge	172:65be27845400	290	#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
AnnaBridge	172:65be27845400	291
AnnaBridge	172:65be27845400	292	#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
AnnaBridge	172:65be27845400	293
AnnaBridge	172:65be27845400	294	#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	295
AnnaBridge	172:65be27845400	296	#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
AnnaBridge	172:65be27845400	297	#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
AnnaBridge	172:65be27845400	298	#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
AnnaBridge	172:65be27845400	299
AnnaBridge	172:65be27845400	300	#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
AnnaBridge	172:65be27845400	301
AnnaBridge	172:65be27845400	302	#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
AnnaBridge	172:65be27845400	303	#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
AnnaBridge	172:65be27845400	304	#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
AnnaBridge	172:65be27845400	305	#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
AnnaBridge	172:65be27845400	306	#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
AnnaBridge	172:65be27845400	307
AnnaBridge	172:65be27845400	308	#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
AnnaBridge	172:65be27845400	309	#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
AnnaBridge	172:65be27845400	310
AnnaBridge	172:65be27845400	311	/**
AnnaBridge	172:65be27845400	312	* @brief Command Class supported
AnnaBridge	172:65be27845400	313	*/
AnnaBridge	172:65be27845400	314	#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
AnnaBridge	172:65be27845400	315
AnnaBridge	172:65be27845400	316	#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
AnnaBridge	172:65be27845400	317	#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
AnnaBridge	172:65be27845400	318	#define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */
AnnaBridge	172:65be27845400	319
AnnaBridge	172:65be27845400	320	/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
AnnaBridge	172:65be27845400	321	* @{
AnnaBridge	172:65be27845400	322	*/
AnnaBridge	172:65be27845400	323	#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	324	#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
AnnaBridge	172:65be27845400	325
AnnaBridge	172:65be27845400	326	#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) \|\| \
AnnaBridge	172:65be27845400	327	((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
AnnaBridge	172:65be27845400	328	/**
AnnaBridge	172:65be27845400	329	* @}
AnnaBridge	172:65be27845400	330	*/
AnnaBridge	172:65be27845400	331
AnnaBridge	172:65be27845400	332	/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
AnnaBridge	172:65be27845400	333	* @{
AnnaBridge	172:65be27845400	334	*/
AnnaBridge	172:65be27845400	335	#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	336	#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
AnnaBridge	172:65be27845400	337
AnnaBridge	172:65be27845400	338	#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) \|\| \
AnnaBridge	172:65be27845400	339	((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
AnnaBridge	172:65be27845400	340	/**
AnnaBridge	172:65be27845400	341	* @}
AnnaBridge	172:65be27845400	342	*/
AnnaBridge	172:65be27845400	343
AnnaBridge	172:65be27845400	344	/** @defgroup SDMMC_LL_Bus_Wide Bus Width
AnnaBridge	172:65be27845400	345	* @{
AnnaBridge	172:65be27845400	346	*/
AnnaBridge	172:65be27845400	347	#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	348	#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
AnnaBridge	172:65be27845400	349	#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
AnnaBridge	172:65be27845400	350
AnnaBridge	172:65be27845400	351	#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) \|\| \
AnnaBridge	172:65be27845400	352	((WIDE) == SDMMC_BUS_WIDE_4B) \|\| \
AnnaBridge	172:65be27845400	353	((WIDE) == SDMMC_BUS_WIDE_8B))
AnnaBridge	172:65be27845400	354	/**
AnnaBridge	172:65be27845400	355	* @}
AnnaBridge	172:65be27845400	356	*/
AnnaBridge	172:65be27845400	357
AnnaBridge	172:65be27845400	358	/** @defgroup SDMMC_LL_Speed_Mode
AnnaBridge	172:65be27845400	359	* @{
AnnaBridge	172:65be27845400	360	*/
AnnaBridge	172:65be27845400	361	#define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	362	#define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U)
AnnaBridge	172:65be27845400	363	#define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U)
AnnaBridge	172:65be27845400	364	#define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U)
AnnaBridge	172:65be27845400	365
AnnaBridge	172:65be27845400	366	#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) \|\| \
AnnaBridge	172:65be27845400	367	((MODE) == SDMMC_SPEED_MODE_DEFAULT) \|\| \
AnnaBridge	172:65be27845400	368	((MODE) == SDMMC_SPEED_MODE_HIGH) \|\| \
AnnaBridge	172:65be27845400	369	((MODE) == SDMMC_SPEED_MODE_ULTRA))
AnnaBridge	172:65be27845400	370	/**
AnnaBridge	172:65be27845400	371	* @}
AnnaBridge	172:65be27845400	372	*/
AnnaBridge	172:65be27845400	373
AnnaBridge	172:65be27845400	374	/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
AnnaBridge	172:65be27845400	375	* @{
AnnaBridge	172:65be27845400	376	*/
AnnaBridge	172:65be27845400	377	#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	378	#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
AnnaBridge	172:65be27845400	379
AnnaBridge	172:65be27845400	380	#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
AnnaBridge	172:65be27845400	381	((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
AnnaBridge	172:65be27845400	382	/**
AnnaBridge	172:65be27845400	383	* @}
AnnaBridge	172:65be27845400	384	*/
AnnaBridge	172:65be27845400	385
AnnaBridge	172:65be27845400	386	/** @defgroup SDMMC_LL_Clock_Division Clock Division
AnnaBridge	172:65be27845400	387	* @{
AnnaBridge	172:65be27845400	388	*/
AnnaBridge	172:65be27845400	389	/* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */
AnnaBridge	172:65be27845400	390	#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U)
AnnaBridge	172:65be27845400	391	/**
AnnaBridge	172:65be27845400	392	* @}
AnnaBridge	172:65be27845400	393	*/
AnnaBridge	172:65be27845400	394
AnnaBridge	172:65be27845400	395
AnnaBridge	172:65be27845400	396	/** @defgroup SDMMC_LL_Command_Index Command Index
AnnaBridge	172:65be27845400	397	* @{
AnnaBridge	172:65be27845400	398	*/
AnnaBridge	172:65be27845400	399	#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
AnnaBridge	172:65be27845400	400	/**
AnnaBridge	172:65be27845400	401	* @}
AnnaBridge	172:65be27845400	402	*/
AnnaBridge	172:65be27845400	403
AnnaBridge	172:65be27845400	404	/** @defgroup SDMMC_LL_Response_Type Response Type
AnnaBridge	172:65be27845400	405	* @{
AnnaBridge	172:65be27845400	406	*/
AnnaBridge	172:65be27845400	407	#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	408	#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
AnnaBridge	172:65be27845400	409	#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
AnnaBridge	172:65be27845400	410
AnnaBridge	172:65be27845400	411	#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) \|\| \
AnnaBridge	172:65be27845400	412	((RESPONSE) == SDMMC_RESPONSE_SHORT) \|\| \
AnnaBridge	172:65be27845400	413	((RESPONSE) == SDMMC_RESPONSE_LONG))
AnnaBridge	172:65be27845400	414	/**
AnnaBridge	172:65be27845400	415	* @}
AnnaBridge	172:65be27845400	416	*/
AnnaBridge	172:65be27845400	417
AnnaBridge	172:65be27845400	418	/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
AnnaBridge	172:65be27845400	419	* @{
AnnaBridge	172:65be27845400	420	*/
AnnaBridge	172:65be27845400	421	#define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	422	#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
AnnaBridge	172:65be27845400	423	#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
AnnaBridge	172:65be27845400	424
AnnaBridge	172:65be27845400	425	#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) \|\| \
AnnaBridge	172:65be27845400	426	((WAIT) == SDMMC_WAIT_IT) \|\| \
AnnaBridge	172:65be27845400	427	((WAIT) == SDMMC_WAIT_PEND))
AnnaBridge	172:65be27845400	428	/**
AnnaBridge	172:65be27845400	429	* @}
AnnaBridge	172:65be27845400	430	*/
AnnaBridge	172:65be27845400	431
AnnaBridge	172:65be27845400	432	/** @defgroup SDMMC_LL_CPSM_State CPSM State
AnnaBridge	172:65be27845400	433	* @{
AnnaBridge	172:65be27845400	434	*/
AnnaBridge	172:65be27845400	435	#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	436	#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
AnnaBridge	172:65be27845400	437
AnnaBridge	172:65be27845400	438	#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) \|\| \
AnnaBridge	172:65be27845400	439	((CPSM) == SDMMC_CPSM_ENABLE))
AnnaBridge	172:65be27845400	440	/**
AnnaBridge	172:65be27845400	441	* @}
AnnaBridge	172:65be27845400	442	*/
AnnaBridge	172:65be27845400	443
AnnaBridge	172:65be27845400	444	/** @defgroup SDMMC_LL_Response_Registers Response Register
AnnaBridge	172:65be27845400	445	* @{
AnnaBridge	172:65be27845400	446	*/
AnnaBridge	172:65be27845400	447	#define SDMMC_RESP1 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	448	#define SDMMC_RESP2 ((uint32_t)0x00000004U)
AnnaBridge	172:65be27845400	449	#define SDMMC_RESP3 ((uint32_t)0x00000008U)
AnnaBridge	172:65be27845400	450	#define SDMMC_RESP4 ((uint32_t)0x0000000CU)
AnnaBridge	172:65be27845400	451
AnnaBridge	172:65be27845400	452	#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) \|\| \
AnnaBridge	172:65be27845400	453	((RESP) == SDMMC_RESP2) \|\| \
AnnaBridge	172:65be27845400	454	((RESP) == SDMMC_RESP3) \|\| \
AnnaBridge	172:65be27845400	455	((RESP) == SDMMC_RESP4))
AnnaBridge	172:65be27845400	456
AnnaBridge	172:65be27845400	457	/** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode
AnnaBridge	172:65be27845400	458	* @{
AnnaBridge	172:65be27845400	459	*/
AnnaBridge	172:65be27845400	460	#define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000)
AnnaBridge	172:65be27845400	461	#define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN)
AnnaBridge	172:65be27845400	462	#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN \| SDMMC_IDMA_IDMABMODE)
AnnaBridge	172:65be27845400	463	#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN \| SDMMC_IDMA_IDMABMODE \| SDMMC_IDMA_IDMABACT)
AnnaBridge	172:65be27845400	464
AnnaBridge	172:65be27845400	465	/**
AnnaBridge	172:65be27845400	466	* @}
AnnaBridge	172:65be27845400	467	*/
AnnaBridge	172:65be27845400	468
AnnaBridge	172:65be27845400	469	/** @defgroup SDMMC_LL_Data_Length Data Lenght
AnnaBridge	172:65be27845400	470	* @{
AnnaBridge	172:65be27845400	471	*/
AnnaBridge	172:65be27845400	472	#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
AnnaBridge	172:65be27845400	473	/**
AnnaBridge	172:65be27845400	474	* @}
AnnaBridge	172:65be27845400	475	*/
AnnaBridge	172:65be27845400	476
AnnaBridge	172:65be27845400	477	/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
AnnaBridge	172:65be27845400	478	* @{
AnnaBridge	172:65be27845400	479	*/
AnnaBridge	172:65be27845400	480	#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	481	#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
AnnaBridge	172:65be27845400	482	#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
AnnaBridge	172:65be27845400	483	#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1)
AnnaBridge	172:65be27845400	484	#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
AnnaBridge	172:65be27845400	485	#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge	172:65be27845400	486	#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge	172:65be27845400	487	#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge	172:65be27845400	488	#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
AnnaBridge	172:65be27845400	489	#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	172:65be27845400	490	#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	172:65be27845400	491	#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	172:65be27845400	492	#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	172:65be27845400	493	#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	172:65be27845400	494	#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	172:65be27845400	495
AnnaBridge	172:65be27845400	496	#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) \|\| \
AnnaBridge	172:65be27845400	497	((SIZE) == SDMMC_DATABLOCK_SIZE_2B) \|\| \
AnnaBridge	172:65be27845400	498	((SIZE) == SDMMC_DATABLOCK_SIZE_4B) \|\| \
AnnaBridge	172:65be27845400	499	((SIZE) == SDMMC_DATABLOCK_SIZE_8B) \|\| \
AnnaBridge	172:65be27845400	500	((SIZE) == SDMMC_DATABLOCK_SIZE_16B) \|\| \
AnnaBridge	172:65be27845400	501	((SIZE) == SDMMC_DATABLOCK_SIZE_32B) \|\| \
AnnaBridge	172:65be27845400	502	((SIZE) == SDMMC_DATABLOCK_SIZE_64B) \|\| \
AnnaBridge	172:65be27845400	503	((SIZE) == SDMMC_DATABLOCK_SIZE_128B) \|\| \
AnnaBridge	172:65be27845400	504	((SIZE) == SDMMC_DATABLOCK_SIZE_256B) \|\| \
AnnaBridge	172:65be27845400	505	((SIZE) == SDMMC_DATABLOCK_SIZE_512B) \|\| \
AnnaBridge	172:65be27845400	506	((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) \|\| \
AnnaBridge	172:65be27845400	507	((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) \|\| \
AnnaBridge	172:65be27845400	508	((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) \|\| \
AnnaBridge	172:65be27845400	509	((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) \|\| \
AnnaBridge	172:65be27845400	510	((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
AnnaBridge	172:65be27845400	511	/**
AnnaBridge	172:65be27845400	512	* @}
AnnaBridge	172:65be27845400	513	*/
AnnaBridge	172:65be27845400	514
AnnaBridge	172:65be27845400	515	/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
AnnaBridge	172:65be27845400	516	* @{
AnnaBridge	172:65be27845400	517	*/
AnnaBridge	172:65be27845400	518	#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	519	#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
AnnaBridge	172:65be27845400	520
AnnaBridge	172:65be27845400	521	#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) \|\| \
AnnaBridge	172:65be27845400	522	((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
AnnaBridge	172:65be27845400	523	/**
AnnaBridge	172:65be27845400	524	* @}
AnnaBridge	172:65be27845400	525	*/
AnnaBridge	172:65be27845400	526
AnnaBridge	172:65be27845400	527	/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
AnnaBridge	172:65be27845400	528	* @{
AnnaBridge	172:65be27845400	529	*/
AnnaBridge	172:65be27845400	530	#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	531	#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1
AnnaBridge	172:65be27845400	532
AnnaBridge	172:65be27845400	533	#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) \|\| \
AnnaBridge	172:65be27845400	534	((MODE) == SDMMC_TRANSFER_MODE_STREAM))
AnnaBridge	172:65be27845400	535	/**
AnnaBridge	172:65be27845400	536	* @}
AnnaBridge	172:65be27845400	537	*/
AnnaBridge	172:65be27845400	538
AnnaBridge	172:65be27845400	539	/** @defgroup SDMMC_LL_DPSM_State DPSM State
AnnaBridge	172:65be27845400	540	* @{
AnnaBridge	172:65be27845400	541	*/
AnnaBridge	172:65be27845400	542	#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	543	#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
AnnaBridge	172:65be27845400	544
AnnaBridge	172:65be27845400	545	#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) \|\|\
AnnaBridge	172:65be27845400	546	((DPSM) == SDMMC_DPSM_ENABLE))
AnnaBridge	172:65be27845400	547	/**
AnnaBridge	172:65be27845400	548	* @}
AnnaBridge	172:65be27845400	549	*/
AnnaBridge	172:65be27845400	550
AnnaBridge	172:65be27845400	551	/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
AnnaBridge	172:65be27845400	552	* @{
AnnaBridge	172:65be27845400	553	*/
AnnaBridge	172:65be27845400	554	#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	555	#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
AnnaBridge	172:65be27845400	556
AnnaBridge	172:65be27845400	557	#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) \|\| \
AnnaBridge	172:65be27845400	558	((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
AnnaBridge	172:65be27845400	559	/**
AnnaBridge	172:65be27845400	560	* @}
AnnaBridge	172:65be27845400	561	*/
AnnaBridge	172:65be27845400	562
AnnaBridge	172:65be27845400	563	/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
AnnaBridge	172:65be27845400	564	* @{
AnnaBridge	172:65be27845400	565	*/
AnnaBridge	172:65be27845400	566	#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE
AnnaBridge	172:65be27845400	567	#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE
AnnaBridge	172:65be27845400	568	#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE
AnnaBridge	172:65be27845400	569	#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE
AnnaBridge	172:65be27845400	570	#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE
AnnaBridge	172:65be27845400	571	#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE
AnnaBridge	172:65be27845400	572	#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE
AnnaBridge	172:65be27845400	573	#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE
AnnaBridge	172:65be27845400	574	#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE
AnnaBridge	172:65be27845400	575	#define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE
AnnaBridge	172:65be27845400	576	#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE
AnnaBridge	172:65be27845400	577	#define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE
AnnaBridge	172:65be27845400	578	#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE
AnnaBridge	172:65be27845400	579	#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE
AnnaBridge	172:65be27845400	580	#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE
AnnaBridge	172:65be27845400	581	#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE
AnnaBridge	172:65be27845400	582	#define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE
AnnaBridge	172:65be27845400	583	#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE
AnnaBridge	172:65be27845400	584	#define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE
AnnaBridge	172:65be27845400	585	#define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE
AnnaBridge	172:65be27845400	586	#define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE
AnnaBridge	172:65be27845400	587	#define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE
AnnaBridge	172:65be27845400	588	#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE
AnnaBridge	172:65be27845400	589	/**
AnnaBridge	172:65be27845400	590	* @}
AnnaBridge	172:65be27845400	591	*/
AnnaBridge	172:65be27845400	592
AnnaBridge	172:65be27845400	593	/** @defgroup SDMMC_LL_Flags Flags
AnnaBridge	172:65be27845400	594	* @{
AnnaBridge	172:65be27845400	595	*/
AnnaBridge	172:65be27845400	596	#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
AnnaBridge	172:65be27845400	597	#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
AnnaBridge	172:65be27845400	598	#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
AnnaBridge	172:65be27845400	599	#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
AnnaBridge	172:65be27845400	600	#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
AnnaBridge	172:65be27845400	601	#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
AnnaBridge	172:65be27845400	602	#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
AnnaBridge	172:65be27845400	603	#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
AnnaBridge	172:65be27845400	604	#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
AnnaBridge	172:65be27845400	605	#define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD
AnnaBridge	172:65be27845400	606	#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
AnnaBridge	172:65be27845400	607	#define SDMMC_FLAG_DABORT SDMMC_STA_DABORT
AnnaBridge	172:65be27845400	608	#define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT
AnnaBridge	172:65be27845400	609	#define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT
AnnaBridge	172:65be27845400	610	#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
AnnaBridge	172:65be27845400	611	#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
AnnaBridge	172:65be27845400	612	#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
AnnaBridge	172:65be27845400	613	#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
AnnaBridge	172:65be27845400	614	#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
AnnaBridge	172:65be27845400	615	#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
AnnaBridge	172:65be27845400	616	#define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0
AnnaBridge	172:65be27845400	617	#define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END
AnnaBridge	172:65be27845400	618	#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
AnnaBridge	172:65be27845400	619	#define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL
AnnaBridge	172:65be27845400	620	#define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT
AnnaBridge	172:65be27845400	621	#define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND
AnnaBridge	172:65be27845400	622	#define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP
AnnaBridge	172:65be27845400	623	#define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE
AnnaBridge	172:65be27845400	624	#define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC
AnnaBridge	172:65be27845400	625
AnnaBridge	172:65be27845400	626	#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL \| SDMMC_FLAG_DCRCFAIL \| SDMMC_FLAG_CTIMEOUT \|\
AnnaBridge	172:65be27845400	627	SDMMC_FLAG_DTIMEOUT \| SDMMC_FLAG_TXUNDERR \| SDMMC_FLAG_RXOVERR \|\
AnnaBridge	172:65be27845400	628	SDMMC_FLAG_CMDREND \| SDMMC_FLAG_CMDSENT \| SDMMC_FLAG_DATAEND \|\
AnnaBridge	172:65be27845400	629	SDMMC_FLAG_DHOLD \| SDMMC_FLAG_DBCKEND \| SDMMC_FLAG_DABORT \|\
AnnaBridge	172:65be27845400	630	SDMMC_FLAG_BUSYD0END \| SDMMC_FLAG_SDIOIT \| SDMMC_FLAG_ACKFAIL \|\
AnnaBridge	172:65be27845400	631	SDMMC_FLAG_ACKTIMEOUT \| SDMMC_FLAG_VSWEND \| SDMMC_FLAG_CKSTOP \|\
AnnaBridge	172:65be27845400	632	SDMMC_FLAG_IDMATE \| SDMMC_FLAG_IDMABTC))
AnnaBridge	172:65be27845400	633
AnnaBridge	172:65be27845400	634	#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL \| SDMMC_FLAG_CTIMEOUT \| SDMMC_FLAG_CMDREND \|\
AnnaBridge	172:65be27845400	635	SDMMC_FLAG_CMDSENT \| SDMMC_FLAG_BUSYD0END))
AnnaBridge	172:65be27845400	636
AnnaBridge	172:65be27845400	637	#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL \| SDMMC_FLAG_DTIMEOUT \| SDMMC_FLAG_TXUNDERR \|\
AnnaBridge	172:65be27845400	638	SDMMC_FLAG_RXOVERR \| SDMMC_FLAG_DATAEND \| SDMMC_FLAG_DHOLD \|\
AnnaBridge	172:65be27845400	639	SDMMC_FLAG_DBCKEND \| SDMMC_FLAG_DABORT \| SDMMC_FLAG_IDMATE \|\
AnnaBridge	172:65be27845400	640	SDMMC_FLAG_IDMABTC))
AnnaBridge	172:65be27845400	641	/**
AnnaBridge	172:65be27845400	642	* @}
AnnaBridge	172:65be27845400	643	*/
AnnaBridge	172:65be27845400	644
AnnaBridge	172:65be27845400	645	/**
AnnaBridge	172:65be27845400	646	* @}
AnnaBridge	172:65be27845400	647	*/
AnnaBridge	172:65be27845400	648
AnnaBridge	172:65be27845400	649	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	650	/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
AnnaBridge	172:65be27845400	651	* @{
AnnaBridge	172:65be27845400	652	*/
AnnaBridge	172:65be27845400	653
AnnaBridge	172:65be27845400	654	/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
AnnaBridge	172:65be27845400	655	* @brief SDMMC_LL registers bit address in the alias region
AnnaBridge	172:65be27845400	656	* @{
AnnaBridge	172:65be27845400	657	*/
AnnaBridge	172:65be27845400	658	/* ---------------------- SDMMC registers bit mask --------------------------- */
AnnaBridge	172:65be27845400	659	/* --- CLKCR Register ---*/
AnnaBridge	172:65be27845400	660	/* CLKCR register clear mask */
AnnaBridge	172:65be27845400	661	#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV \| SDMMC_CLKCR_PWRSAV \|\
AnnaBridge	172:65be27845400	662	SDMMC_CLKCR_WIDBUS \|\
AnnaBridge	172:65be27845400	663	SDMMC_CLKCR_NEGEDGE \| SDMMC_CLKCR_HWFC_EN \|\
AnnaBridge	172:65be27845400	664	SDMMC_CLKCR_DDR \| SDMMC_CLKCR_BUSSPEED \|\
AnnaBridge	172:65be27845400	665	SDMMC_CLKCR_SELCLKRX))
AnnaBridge	172:65be27845400	666
AnnaBridge	172:65be27845400	667	/* --- DCTRL Register ---*/
AnnaBridge	172:65be27845400	668	/* SDMMC DCTRL Clear Mask */
AnnaBridge	172:65be27845400	669	#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN \| SDMMC_DCTRL_DTDIR \|\
AnnaBridge	172:65be27845400	670	SDMMC_DCTRL_DTMODE \| SDMMC_DCTRL_DBLOCKSIZE))
AnnaBridge	172:65be27845400	671
AnnaBridge	172:65be27845400	672	/* --- CMD Register ---*/
AnnaBridge	172:65be27845400	673	/* CMD Register clear mask */
AnnaBridge	172:65be27845400	674	#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX \| SDMMC_CMD_WAITRESP \|\
AnnaBridge	172:65be27845400	675	SDMMC_CMD_WAITINT \| SDMMC_CMD_WAITPEND \|\
AnnaBridge	172:65be27845400	676	SDMMC_CMD_CPSMEN \| SDMMC_CMD_CMDSUSPEND))
AnnaBridge	172:65be27845400	677
AnnaBridge	172:65be27845400	678	/* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 200MHz*/
AnnaBridge	172:65be27845400	679	#define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA)
AnnaBridge	172:65be27845400	680
AnnaBridge	172:65be27845400	681	/* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/
AnnaBridge	172:65be27845400	682	#define SDMMC_NSpeed_CLK_DIV ((uint8_t)0x4)
AnnaBridge	172:65be27845400	683
AnnaBridge	172:65be27845400	684	/* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/
AnnaBridge	172:65be27845400	685	#define SDMMC_HSpeed_CLK_DIV ((uint8_t)0x2)
AnnaBridge	172:65be27845400	686	/**
AnnaBridge	172:65be27845400	687	* @}
AnnaBridge	172:65be27845400	688	*/
AnnaBridge	172:65be27845400	689
AnnaBridge	172:65be27845400	690	/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
AnnaBridge	172:65be27845400	691	* @brief macros to handle interrupts and specific clock configurations
AnnaBridge	172:65be27845400	692	* @{
AnnaBridge	172:65be27845400	693	*/
AnnaBridge	172:65be27845400	694
AnnaBridge	172:65be27845400	695	/**
AnnaBridge	172:65be27845400	696	* @brief Enable the SDMMC device interrupt.
AnnaBridge	172:65be27845400	697	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	698	* @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.
AnnaBridge	172:65be27845400	699	* This parameter can be one or a combination of the following values:
AnnaBridge	172:65be27845400	700	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	172:65be27845400	701	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	172:65be27845400	702	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	172:65be27845400	703	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	172:65be27845400	704	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	172:65be27845400	705	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	172:65be27845400	706	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	172:65be27845400	707	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	172:65be27845400	708	* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
AnnaBridge	172:65be27845400	709	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	172:65be27845400	710	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	172:65be27845400	711	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	172:65be27845400	712	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	172:65be27845400	713	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	172:65be27845400	714	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	172:65be27845400	715	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	172:65be27845400	716	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	172:65be27845400	717	* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
AnnaBridge	172:65be27845400	718	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	172:65be27845400	719	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	172:65be27845400	720	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	172:65be27845400	721	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	172:65be27845400	722	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	172:65be27845400	723	* @retval None
AnnaBridge	172:65be27845400	724	*/
AnnaBridge	172:65be27845400	725	#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
AnnaBridge	172:65be27845400	726
AnnaBridge	172:65be27845400	727	/**
AnnaBridge	172:65be27845400	728	* @brief Disable the SDMMC device interrupt.
AnnaBridge	172:65be27845400	729	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	730	* @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.
AnnaBridge	172:65be27845400	731	* This parameter can be one or a combination of the following values:
AnnaBridge	172:65be27845400	732	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	172:65be27845400	733	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	172:65be27845400	734	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	172:65be27845400	735	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	172:65be27845400	736	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	172:65be27845400	737	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	172:65be27845400	738	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	172:65be27845400	739	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	172:65be27845400	740	* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
AnnaBridge	172:65be27845400	741	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	172:65be27845400	742	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	172:65be27845400	743	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	172:65be27845400	744	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	172:65be27845400	745	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	172:65be27845400	746	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	172:65be27845400	747	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	172:65be27845400	748	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	172:65be27845400	749	* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
AnnaBridge	172:65be27845400	750	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	172:65be27845400	751	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	172:65be27845400	752	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	172:65be27845400	753	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	172:65be27845400	754	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	172:65be27845400	755	* @retval None
AnnaBridge	172:65be27845400	756	*/
AnnaBridge	172:65be27845400	757	#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
AnnaBridge	172:65be27845400	758
AnnaBridge	172:65be27845400	759	/**
AnnaBridge	172:65be27845400	760	* @brief Checks whether the specified SDMMC flag is set or not.
AnnaBridge	172:65be27845400	761	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	762	* @param __FLAG__: specifies the flag to check.
AnnaBridge	172:65be27845400	763	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	764	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	172:65be27845400	765	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	172:65be27845400	766	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	172:65be27845400	767	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
AnnaBridge	172:65be27845400	768	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	172:65be27845400	769	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	172:65be27845400	770	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	172:65be27845400	771	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	172:65be27845400	772	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
AnnaBridge	172:65be27845400	773	* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
AnnaBridge	172:65be27845400	774	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	172:65be27845400	775	* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
AnnaBridge	172:65be27845400	776	* @arg SDMMC_FLAG_CPSMACT: Command path state machine active
AnnaBridge	172:65be27845400	777	* @arg SDMMC_FLAG_DPSMACT: Data path state machine active
AnnaBridge	172:65be27845400	778	* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
AnnaBridge	172:65be27845400	779	* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
AnnaBridge	172:65be27845400	780	* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
AnnaBridge	172:65be27845400	781	* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
AnnaBridge	172:65be27845400	782	* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
AnnaBridge	172:65be27845400	783	* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
AnnaBridge	172:65be27845400	784	* @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
AnnaBridge	172:65be27845400	785	* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
AnnaBridge	172:65be27845400	786	* @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
AnnaBridge	172:65be27845400	787	* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
AnnaBridge	172:65be27845400	788	* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
AnnaBridge	172:65be27845400	789	* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
AnnaBridge	172:65be27845400	790	* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
AnnaBridge	172:65be27845400	791	* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
AnnaBridge	172:65be27845400	792	* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
AnnaBridge	172:65be27845400	793	* @retval The new state of SDMMC_FLAG (SET or RESET).
AnnaBridge	172:65be27845400	794	*/
AnnaBridge	172:65be27845400	795	#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
AnnaBridge	172:65be27845400	796
AnnaBridge	172:65be27845400	797
AnnaBridge	172:65be27845400	798	/**
AnnaBridge	172:65be27845400	799	* @brief Clears the SDMMC pending flags.
AnnaBridge	172:65be27845400	800	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	801	* @param __FLAG__: specifies the flag to clear.
AnnaBridge	172:65be27845400	802	* This parameter can be one or a combination of the following values:
AnnaBridge	172:65be27845400	803	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	172:65be27845400	804	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	172:65be27845400	805	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	172:65be27845400	806	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
AnnaBridge	172:65be27845400	807	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	172:65be27845400	808	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	172:65be27845400	809	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	172:65be27845400	810	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	172:65be27845400	811	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
AnnaBridge	172:65be27845400	812	* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
AnnaBridge	172:65be27845400	813	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	172:65be27845400	814	* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
AnnaBridge	172:65be27845400	815	* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
AnnaBridge	172:65be27845400	816	* @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
AnnaBridge	172:65be27845400	817	* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
AnnaBridge	172:65be27845400	818	* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
AnnaBridge	172:65be27845400	819	* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
AnnaBridge	172:65be27845400	820	* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
AnnaBridge	172:65be27845400	821	* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
AnnaBridge	172:65be27845400	822	* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
AnnaBridge	172:65be27845400	823	* @retval None
AnnaBridge	172:65be27845400	824	*/
AnnaBridge	172:65be27845400	825	#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
AnnaBridge	172:65be27845400	826
AnnaBridge	172:65be27845400	827	/**
AnnaBridge	172:65be27845400	828	* @brief Checks whether the specified SDMMC interrupt has occurred or not.
AnnaBridge	172:65be27845400	829	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	830	* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
AnnaBridge	172:65be27845400	831	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	832	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	172:65be27845400	833	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	172:65be27845400	834	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	172:65be27845400	835	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	172:65be27845400	836	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	172:65be27845400	837	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	172:65be27845400	838	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	172:65be27845400	839	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	172:65be27845400	840	* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
AnnaBridge	172:65be27845400	841	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	172:65be27845400	842	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	172:65be27845400	843	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	172:65be27845400	844	* @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt
AnnaBridge	172:65be27845400	845	* @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt
AnnaBridge	172:65be27845400	846	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	172:65be27845400	847	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	172:65be27845400	848	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	172:65be27845400	849	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	172:65be27845400	850	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	172:65be27845400	851	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	172:65be27845400	852	* @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
AnnaBridge	172:65be27845400	853	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	172:65be27845400	854	* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
AnnaBridge	172:65be27845400	855	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	172:65be27845400	856	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	172:65be27845400	857	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	172:65be27845400	858	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	172:65be27845400	859	* @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
AnnaBridge	172:65be27845400	860	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	172:65be27845400	861	* @retval The new state of SDMMC_IT (SET or RESET).
AnnaBridge	172:65be27845400	862	*/
AnnaBridge	172:65be27845400	863	#define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	172:65be27845400	864
AnnaBridge	172:65be27845400	865	/**
AnnaBridge	172:65be27845400	866	* @brief Clears the SDMMC's interrupt pending bits.
AnnaBridge	172:65be27845400	867	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	868	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge	172:65be27845400	869	* This parameter can be one or a combination of the following values:
AnnaBridge	172:65be27845400	870	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	172:65be27845400	871	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	172:65be27845400	872	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	172:65be27845400	873	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	172:65be27845400	874	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	172:65be27845400	875	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	172:65be27845400	876	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	172:65be27845400	877	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	172:65be27845400	878	* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
AnnaBridge	172:65be27845400	879	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	172:65be27845400	880	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	172:65be27845400	881	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	172:65be27845400	882	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	172:65be27845400	883	* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
AnnaBridge	172:65be27845400	884	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	172:65be27845400	885	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	172:65be27845400	886	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	172:65be27845400	887	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	172:65be27845400	888	* @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
AnnaBridge	172:65be27845400	889	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	172:65be27845400	890	* @retval None
AnnaBridge	172:65be27845400	891	*/
AnnaBridge	172:65be27845400	892	#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
AnnaBridge	172:65be27845400	893
AnnaBridge	172:65be27845400	894	/**
AnnaBridge	172:65be27845400	895	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	172:65be27845400	896	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	897	* @retval None
AnnaBridge	172:65be27845400	898	*/
AnnaBridge	172:65be27845400	899	#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTART)
AnnaBridge	172:65be27845400	900
AnnaBridge	172:65be27845400	901	/**
AnnaBridge	172:65be27845400	902	* @brief Disable Start the SD I/O Read Wait operations.
AnnaBridge	172:65be27845400	903	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	904	* @retval None
AnnaBridge	172:65be27845400	905	*/
AnnaBridge	172:65be27845400	906	#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
AnnaBridge	172:65be27845400	907
AnnaBridge	172:65be27845400	908	/**
AnnaBridge	172:65be27845400	909	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	172:65be27845400	910	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	911	* @retval None
AnnaBridge	172:65be27845400	912	*/
AnnaBridge	172:65be27845400	913	#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTOP)
AnnaBridge	172:65be27845400	914
AnnaBridge	172:65be27845400	915	/**
AnnaBridge	172:65be27845400	916	* @brief Disable Stop the SD I/O Read Wait operations.
AnnaBridge	172:65be27845400	917	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	918	* @retval None
AnnaBridge	172:65be27845400	919	*/
AnnaBridge	172:65be27845400	920	#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
AnnaBridge	172:65be27845400	921
AnnaBridge	172:65be27845400	922	/**
AnnaBridge	172:65be27845400	923	* @brief Enable the SD I/O Mode Operation.
AnnaBridge	172:65be27845400	924	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	925	* @retval None
AnnaBridge	172:65be27845400	926	*/
AnnaBridge	172:65be27845400	927	#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_SDIOEN)
AnnaBridge	172:65be27845400	928
AnnaBridge	172:65be27845400	929	/**
AnnaBridge	172:65be27845400	930	* @brief Disable the SD I/O Mode Operation.
AnnaBridge	172:65be27845400	931	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	932	* @retval None
AnnaBridge	172:65be27845400	933	*/
AnnaBridge	172:65be27845400	934	#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
AnnaBridge	172:65be27845400	935
AnnaBridge	172:65be27845400	936	/**
AnnaBridge	172:65be27845400	937	* @brief Enable the SD I/O Suspend command sending.
AnnaBridge	172:65be27845400	938	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	939	* @retval None
AnnaBridge	172:65be27845400	940	*/
AnnaBridge	172:65be27845400	941	#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_CMDSUSPEND)
AnnaBridge	172:65be27845400	942
AnnaBridge	172:65be27845400	943	/**
AnnaBridge	172:65be27845400	944	* @brief Disable the SD I/O Suspend command sending.
AnnaBridge	172:65be27845400	945	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	946	* @retval None
AnnaBridge	172:65be27845400	947	*/
AnnaBridge	172:65be27845400	948	#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)
AnnaBridge	172:65be27845400	949
AnnaBridge	172:65be27845400	950	/**
AnnaBridge	172:65be27845400	951	* @brief Enable the CMDTRANS mode.
AnnaBridge	172:65be27845400	952	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	953	* @retval None
AnnaBridge	172:65be27845400	954	*/
AnnaBridge	172:65be27845400	955	#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_CMDTRANS)
AnnaBridge	172:65be27845400	956
AnnaBridge	172:65be27845400	957	/**
AnnaBridge	172:65be27845400	958	* @brief Disable the CMDTRANS mode.
AnnaBridge	172:65be27845400	959	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	960	* @retval None
AnnaBridge	172:65be27845400	961	*/
AnnaBridge	172:65be27845400	962	#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
AnnaBridge	172:65be27845400	963
AnnaBridge	172:65be27845400	964	/**
AnnaBridge	172:65be27845400	965	* @brief Enable the CMDSTOP mode.
AnnaBridge	172:65be27845400	966	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	967	* @retval None
AnnaBridge	172:65be27845400	968	*/
AnnaBridge	172:65be27845400	969	#define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_CMDSTOP)
AnnaBridge	172:65be27845400	970
AnnaBridge	172:65be27845400	971	/**
AnnaBridge	172:65be27845400	972	* @brief Disable the CMDSTOP mode.
AnnaBridge	172:65be27845400	973	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	172:65be27845400	974	* @retval None
AnnaBridge	172:65be27845400	975	*/
AnnaBridge	172:65be27845400	976	#define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP)
AnnaBridge	172:65be27845400	977
AnnaBridge	172:65be27845400	978	/**
AnnaBridge	172:65be27845400	979	* @}
AnnaBridge	172:65be27845400	980	*/
AnnaBridge	172:65be27845400	981
AnnaBridge	172:65be27845400	982	/**
AnnaBridge	172:65be27845400	983	* @}
AnnaBridge	172:65be27845400	984	*/
AnnaBridge	172:65be27845400	985
AnnaBridge	172:65be27845400	986	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	987	/** @addtogroup SDMMC_LL_Exported_Functions
AnnaBridge	172:65be27845400	988	* @{
AnnaBridge	172:65be27845400	989	*/
AnnaBridge	172:65be27845400	990
AnnaBridge	172:65be27845400	991	/* Initialization/de-initialization functions **********************************/
AnnaBridge	172:65be27845400	992	/** @addtogroup HAL_SDMMC_LL_Group1
AnnaBridge	172:65be27845400	993	* @{
AnnaBridge	172:65be27845400	994	*/
AnnaBridge	172:65be27845400	995	HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
AnnaBridge	172:65be27845400	996	/**
AnnaBridge	172:65be27845400	997	* @}
AnnaBridge	172:65be27845400	998	*/
AnnaBridge	172:65be27845400	999
AnnaBridge	172:65be27845400	1000	/* I/O operation functions *****************************************************/
AnnaBridge	172:65be27845400	1001	/** @addtogroup HAL_SDMMC_LL_Group2
AnnaBridge	172:65be27845400	1002	* @{
AnnaBridge	172:65be27845400	1003	*/
AnnaBridge	172:65be27845400	1004	uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1005	HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef SDMMCx, uint32_t pWriteData);
AnnaBridge	172:65be27845400	1006	/**
AnnaBridge	172:65be27845400	1007	* @}
AnnaBridge	172:65be27845400	1008	*/
AnnaBridge	172:65be27845400	1009
AnnaBridge	172:65be27845400	1010	/* Peripheral Control functions ************************************************/
AnnaBridge	172:65be27845400	1011	/** @addtogroup HAL_SDMMC_LL_Group3
AnnaBridge	172:65be27845400	1012	* @{
AnnaBridge	172:65be27845400	1013	*/
AnnaBridge	172:65be27845400	1014	HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1015	HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1016	HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1017	uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1018
AnnaBridge	172:65be27845400	1019	/* Command path state machine (CPSM) management functions */
AnnaBridge	172:65be27845400	1020	HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef SDMMCx, SDMMC_CmdInitTypeDef Command);
AnnaBridge	172:65be27845400	1021	uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1022	uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
AnnaBridge	172:65be27845400	1023
AnnaBridge	172:65be27845400	1024	/* Data path state machine (DPSM) management functions */
AnnaBridge	172:65be27845400	1025	HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef SDMMCx, SDMMC_DataInitTypeDef Data);
AnnaBridge	172:65be27845400	1026	uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1027	uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1028
AnnaBridge	172:65be27845400	1029	/* SDMMC Cards mode management functions */
AnnaBridge	172:65be27845400	1030	HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
AnnaBridge	172:65be27845400	1031
AnnaBridge	172:65be27845400	1032	/* SDMMC Commands management functions */
AnnaBridge	172:65be27845400	1033	uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
AnnaBridge	172:65be27845400	1034	uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
AnnaBridge	172:65be27845400	1035	uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
AnnaBridge	172:65be27845400	1036	uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
AnnaBridge	172:65be27845400	1037	uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
AnnaBridge	172:65be27845400	1038	uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
AnnaBridge	172:65be27845400	1039	uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
AnnaBridge	172:65be27845400	1040	uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
AnnaBridge	172:65be27845400	1041	uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
AnnaBridge	172:65be27845400	1042	uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1043	uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1044	uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
AnnaBridge	172:65be27845400	1045	uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1046	uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1047	uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	172:65be27845400	1048	uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	172:65be27845400	1049	uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
AnnaBridge	172:65be27845400	1050	uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1051	uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1052	uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	172:65be27845400	1053	uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef SDMMCx, uint16_t pRCA);
AnnaBridge	172:65be27845400	1054	uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	172:65be27845400	1055	uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1056	uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
AnnaBridge	172:65be27845400	1057	uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	172:65be27845400	1058	uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	172:65be27845400	1059	uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	172:65be27845400	1060
AnnaBridge	172:65be27845400	1061	/**
AnnaBridge	172:65be27845400	1062	* @}
AnnaBridge	172:65be27845400	1063	*/
AnnaBridge	172:65be27845400	1064
AnnaBridge	172:65be27845400	1065	/**
AnnaBridge	172:65be27845400	1066	* @}
AnnaBridge	172:65be27845400	1067	*/
AnnaBridge	172:65be27845400	1068
AnnaBridge	172:65be27845400	1069	/**
AnnaBridge	172:65be27845400	1070	* @}
AnnaBridge	172:65be27845400	1071	*/
AnnaBridge	172:65be27845400	1072
AnnaBridge	172:65be27845400	1073	/**
AnnaBridge	172:65be27845400	1074	* @}
AnnaBridge	172:65be27845400	1075	*/
AnnaBridge	172:65be27845400	1076
AnnaBridge	172:65be27845400	1077	/**
AnnaBridge	172:65be27845400	1078	* @}
AnnaBridge	172:65be27845400	1079	*/
AnnaBridge	172:65be27845400	1080
AnnaBridge	172:65be27845400	1081	/**
AnnaBridge	172:65be27845400	1082	* @}
AnnaBridge	172:65be27845400	1083	*/
AnnaBridge	172:65be27845400	1084	#ifdef __cplusplus
AnnaBridge	172:65be27845400	1085	}
AnnaBridge	172:65be27845400	1086	#endif
AnnaBridge	172:65be27845400	1087
AnnaBridge	172:65be27845400	1088	#endif /* STM32H7xx_LL_SDMMC_H */
AnnaBridge	172:65be27845400	1089
AnnaBridge	172:65be27845400	1090	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/