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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_ll_fmc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_ll_fmc.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of FMC HAL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	172:65be27845400	10	*
AnnaBridge	172:65be27845400	11	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	12	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	13	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	14	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	15	*
AnnaBridge	172:65be27845400	16	******************************************************************************
AnnaBridge	172:65be27845400	17	*/
AnnaBridge	172:65be27845400	18
AnnaBridge	172:65be27845400	19	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	20	#ifndef STM32H7xx_LL_FMC_H
AnnaBridge	172:65be27845400	21	#define STM32H7xx_LL_FMC_H
AnnaBridge	172:65be27845400	22
AnnaBridge	172:65be27845400	23	#ifdef __cplusplus
AnnaBridge	172:65be27845400	24	extern "C" {
AnnaBridge	172:65be27845400	25	#endif
AnnaBridge	172:65be27845400	26
AnnaBridge	172:65be27845400	27	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	28	#include "stm32h7xx_hal_def.h"
AnnaBridge	172:65be27845400	29
AnnaBridge	172:65be27845400	30	/** @addtogroup STM32H7xx_HAL_Driver
AnnaBridge	172:65be27845400	31	* @{
AnnaBridge	172:65be27845400	32	*/
AnnaBridge	172:65be27845400	33
AnnaBridge	172:65be27845400	34	/** @addtogroup FMC_LL
AnnaBridge	172:65be27845400	35	* @{
AnnaBridge	172:65be27845400	36	*/
AnnaBridge	172:65be27845400	37
AnnaBridge	172:65be27845400	38	/** @addtogroup FMC_LL_Private_Macros
AnnaBridge	172:65be27845400	39	* @{
AnnaBridge	172:65be27845400	40	*/
AnnaBridge	172:65be27845400	41
AnnaBridge	172:65be27845400	42	#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) \|\| \
AnnaBridge	172:65be27845400	43	((__BANK__) == FMC_NORSRAM_BANK2) \|\| \
AnnaBridge	172:65be27845400	44	((__BANK__) == FMC_NORSRAM_BANK3) \|\| \
AnnaBridge	172:65be27845400	45	((__BANK__) == FMC_NORSRAM_BANK4))
AnnaBridge	172:65be27845400	46	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
AnnaBridge	172:65be27845400	47	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
AnnaBridge	172:65be27845400	48	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
AnnaBridge	172:65be27845400	49	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
AnnaBridge	172:65be27845400	50	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
AnnaBridge	172:65be27845400	51	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	172:65be27845400	52	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
AnnaBridge	172:65be27845400	53	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
AnnaBridge	172:65be27845400	54	#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) \|\| \
AnnaBridge	172:65be27845400	55	((__SIZE__) == FMC_PAGE_SIZE_128) \|\| \
AnnaBridge	172:65be27845400	56	((__SIZE__) == FMC_PAGE_SIZE_256) \|\| \
AnnaBridge	172:65be27845400	57	((__SIZE__) == FMC_PAGE_SIZE_512) \|\| \
AnnaBridge	172:65be27845400	58	((__SIZE__) == FMC_PAGE_SIZE_1024))
AnnaBridge	172:65be27845400	59	#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) \|\| \
AnnaBridge	172:65be27845400	60	((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
AnnaBridge	172:65be27845400	61	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
AnnaBridge	172:65be27845400	62	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
AnnaBridge	172:65be27845400	63	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
AnnaBridge	172:65be27845400	64	((__MODE__) == FMC_ACCESS_MODE_D))
AnnaBridge	172:65be27845400	65	#define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) \|\| \
AnnaBridge	172:65be27845400	66	((__NBL__) == FMC_NBL_SETUPTIME_1) \|\| \
AnnaBridge	172:65be27845400	67	((__NBL__) == FMC_NBL_SETUPTIME_2) \|\| \
AnnaBridge	172:65be27845400	68	((__NBL__) == FMC_NBL_SETUPTIME_3))
AnnaBridge	172:65be27845400	69	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
AnnaBridge	172:65be27845400	70	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
AnnaBridge	172:65be27845400	71	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
AnnaBridge	172:65be27845400	72	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
AnnaBridge	172:65be27845400	73	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
AnnaBridge	172:65be27845400	74	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
AnnaBridge	172:65be27845400	75	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
AnnaBridge	172:65be27845400	76	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
AnnaBridge	172:65be27845400	77	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
AnnaBridge	172:65be27845400	78	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
AnnaBridge	172:65be27845400	79	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
AnnaBridge	172:65be27845400	80	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
AnnaBridge	172:65be27845400	81	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
AnnaBridge	172:65be27845400	82	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
AnnaBridge	172:65be27845400	83	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
AnnaBridge	172:65be27845400	84	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
AnnaBridge	172:65be27845400	85	((__BURST__) == FMC_WRITE_BURST_ENABLE))
AnnaBridge	172:65be27845400	86	#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
AnnaBridge	172:65be27845400	87	((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
AnnaBridge	172:65be27845400	88	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	172:65be27845400	89	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
AnnaBridge	172:65be27845400	90	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
AnnaBridge	172:65be27845400	91	#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
AnnaBridge	172:65be27845400	92	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	172:65be27845400	93	#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
AnnaBridge	172:65be27845400	94	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
AnnaBridge	172:65be27845400	95	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
AnnaBridge	172:65be27845400	96
AnnaBridge	172:65be27845400	97
AnnaBridge	172:65be27845400	98	#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
AnnaBridge	172:65be27845400	99	#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) \|\| \
AnnaBridge	172:65be27845400	100	((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
AnnaBridge	172:65be27845400	101	#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	172:65be27845400	102	((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
AnnaBridge	172:65be27845400	103	#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) \|\| \
AnnaBridge	172:65be27845400	104	((__STATE__) == FMC_NAND_ECC_ENABLE))
AnnaBridge	172:65be27845400	105
AnnaBridge	172:65be27845400	106	#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
AnnaBridge	172:65be27845400	107	((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
AnnaBridge	172:65be27845400	108	((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
AnnaBridge	172:65be27845400	109	((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
AnnaBridge	172:65be27845400	110	((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
AnnaBridge	172:65be27845400	111	((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
AnnaBridge	172:65be27845400	112	#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
AnnaBridge	172:65be27845400	113	#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
AnnaBridge	172:65be27845400	114	#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
AnnaBridge	172:65be27845400	115	#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
AnnaBridge	172:65be27845400	116	#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
AnnaBridge	172:65be27845400	117	#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
AnnaBridge	172:65be27845400	118	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
AnnaBridge	172:65be27845400	119
AnnaBridge	172:65be27845400	120
AnnaBridge	172:65be27845400	121	#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	172:65be27845400	122	((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
AnnaBridge	172:65be27845400	123	((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32))
AnnaBridge	172:65be27845400	124	#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
AnnaBridge	172:65be27845400	125	((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
AnnaBridge	172:65be27845400	126	#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
AnnaBridge	172:65be27845400	127	((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
AnnaBridge	172:65be27845400	128	((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
AnnaBridge	172:65be27845400	129	#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) \|\| \
AnnaBridge	172:65be27845400	130	((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
AnnaBridge	172:65be27845400	131	#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
AnnaBridge	172:65be27845400	132	((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
AnnaBridge	172:65be27845400	133	((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
AnnaBridge	172:65be27845400	134	#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
AnnaBridge	172:65be27845400	135	((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
AnnaBridge	172:65be27845400	136	((__COMMAND__) == FMC_SDRAM_CMD_PALL) \|\| \
AnnaBridge	172:65be27845400	137	((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
AnnaBridge	172:65be27845400	138	((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
AnnaBridge	172:65be27845400	139	((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
AnnaBridge	172:65be27845400	140	((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
AnnaBridge	172:65be27845400	141	#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
AnnaBridge	172:65be27845400	142	((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
AnnaBridge	172:65be27845400	143	((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
AnnaBridge	172:65be27845400	144	#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
AnnaBridge	172:65be27845400	145	#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
AnnaBridge	172:65be27845400	146	#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
AnnaBridge	172:65be27845400	147	#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
AnnaBridge	172:65be27845400	148	#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
AnnaBridge	172:65be27845400	149	#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
AnnaBridge	172:65be27845400	150	#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
AnnaBridge	172:65be27845400	151	#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U))
AnnaBridge	172:65be27845400	152	#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U)
AnnaBridge	172:65be27845400	153	#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U)
AnnaBridge	172:65be27845400	154	#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
AnnaBridge	172:65be27845400	155	#define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) \|\| \
AnnaBridge	172:65be27845400	156	((__BANK__) == FMC_SDRAM_BANK2))
AnnaBridge	172:65be27845400	157	#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
AnnaBridge	172:65be27845400	158	((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
AnnaBridge	172:65be27845400	159	((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
AnnaBridge	172:65be27845400	160	((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11))
AnnaBridge	172:65be27845400	161	#define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
AnnaBridge	172:65be27845400	162	((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
AnnaBridge	172:65be27845400	163	((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13))
AnnaBridge	172:65be27845400	164	#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
AnnaBridge	172:65be27845400	165	((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4))
AnnaBridge	172:65be27845400	166	#define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
AnnaBridge	172:65be27845400	167	((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
AnnaBridge	172:65be27845400	168	((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3))
AnnaBridge	172:65be27845400	169
AnnaBridge	172:65be27845400	170
AnnaBridge	172:65be27845400	171	/**
AnnaBridge	172:65be27845400	172	* @}
AnnaBridge	172:65be27845400	173	*/
AnnaBridge	172:65be27845400	174
AnnaBridge	172:65be27845400	175	/* Exported typedef ----------------------------------------------------------*/
AnnaBridge	172:65be27845400	176
AnnaBridge	172:65be27845400	177	/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types
AnnaBridge	172:65be27845400	178	* @{
AnnaBridge	172:65be27845400	179	*/
AnnaBridge	172:65be27845400	180
AnnaBridge	172:65be27845400	181	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
AnnaBridge	172:65be27845400	182	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
AnnaBridge	172:65be27845400	183	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
AnnaBridge	172:65be27845400	184	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
AnnaBridge	172:65be27845400	185
AnnaBridge	172:65be27845400	186	#define FMC_NORSRAM_DEVICE FMC_Bank1_R
AnnaBridge	172:65be27845400	187	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R
AnnaBridge	172:65be27845400	188	#define FMC_NAND_DEVICE FMC_Bank3_R
AnnaBridge	172:65be27845400	189	#define FMC_SDRAM_DEVICE FMC_Bank5_6_R
AnnaBridge	172:65be27845400	190
AnnaBridge	172:65be27845400	191	/**
AnnaBridge	172:65be27845400	192	* @brief FMC NORSRAM Configuration Structure definition
AnnaBridge	172:65be27845400	193	*/
AnnaBridge	172:65be27845400	194	typedef struct
AnnaBridge	172:65be27845400	195	{
AnnaBridge	172:65be27845400	196	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
AnnaBridge	172:65be27845400	197	This parameter can be a value of @ref FMC_NORSRAM_Bank */
AnnaBridge	172:65be27845400	198
AnnaBridge	172:65be27845400	199	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
AnnaBridge	172:65be27845400	200	multiplexed on the data bus or not.
AnnaBridge	172:65be27845400	201	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
AnnaBridge	172:65be27845400	202
AnnaBridge	172:65be27845400	203	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
AnnaBridge	172:65be27845400	204	the corresponding memory device.
AnnaBridge	172:65be27845400	205	This parameter can be a value of @ref FMC_Memory_Type */
AnnaBridge	172:65be27845400	206
AnnaBridge	172:65be27845400	207	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	172:65be27845400	208	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
AnnaBridge	172:65be27845400	209
AnnaBridge	172:65be27845400	210	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
AnnaBridge	172:65be27845400	211	valid only with synchronous burst Flash memories.
AnnaBridge	172:65be27845400	212	This parameter can be a value of @ref FMC_Burst_Access_Mode */
AnnaBridge	172:65be27845400	213
AnnaBridge	172:65be27845400	214	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
AnnaBridge	172:65be27845400	215	the Flash memory in burst mode.
AnnaBridge	172:65be27845400	216	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
AnnaBridge	172:65be27845400	217
AnnaBridge	172:65be27845400	218	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
AnnaBridge	172:65be27845400	219	clock cycle before the wait state or during the wait state,
AnnaBridge	172:65be27845400	220	valid only when accessing memories in burst mode.
AnnaBridge	172:65be27845400	221	This parameter can be a value of @ref FMC_Wait_Timing */
AnnaBridge	172:65be27845400	222
AnnaBridge	172:65be27845400	223	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
AnnaBridge	172:65be27845400	224	This parameter can be a value of @ref FMC_Write_Operation */
AnnaBridge	172:65be27845400	225
AnnaBridge	172:65be27845400	226	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
AnnaBridge	172:65be27845400	227	signal, valid for Flash memory access in burst mode.
AnnaBridge	172:65be27845400	228	This parameter can be a value of @ref FMC_Wait_Signal */
AnnaBridge	172:65be27845400	229
AnnaBridge	172:65be27845400	230	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
AnnaBridge	172:65be27845400	231	This parameter can be a value of @ref FMC_Extended_Mode */
AnnaBridge	172:65be27845400	232
AnnaBridge	172:65be27845400	233	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
AnnaBridge	172:65be27845400	234	valid only with asynchronous Flash memories.
AnnaBridge	172:65be27845400	235	This parameter can be a value of @ref FMC_AsynchronousWait */
AnnaBridge	172:65be27845400	236
AnnaBridge	172:65be27845400	237	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
AnnaBridge	172:65be27845400	238	This parameter can be a value of @ref FMC_Write_Burst */
AnnaBridge	172:65be27845400	239
AnnaBridge	172:65be27845400	240	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
AnnaBridge	172:65be27845400	241	This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge	172:65be27845400	242	through FMC_BCR2..4 registers.
AnnaBridge	172:65be27845400	243	This parameter can be a value of @ref FMC_Continous_Clock */
AnnaBridge	172:65be27845400	244
AnnaBridge	172:65be27845400	245	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
AnnaBridge	172:65be27845400	246	This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge	172:65be27845400	247	through FMC_BCR2..4 registers.
AnnaBridge	172:65be27845400	248	This parameter can be a value of @ref FMC_Write_FIFO */
AnnaBridge	172:65be27845400	249
AnnaBridge	172:65be27845400	250	uint32_t PageSize; /*!< Specifies the memory page size.
AnnaBridge	172:65be27845400	251	This parameter can be a value of @ref FMC_Page_Size */
AnnaBridge	172:65be27845400	252
AnnaBridge	172:65be27845400	253	}FMC_NORSRAM_InitTypeDef;
AnnaBridge	172:65be27845400	254
AnnaBridge	172:65be27845400	255	/**
AnnaBridge	172:65be27845400	256	* @brief FMC NORSRAM Timing parameters structure definition
AnnaBridge	172:65be27845400	257	*/
AnnaBridge	172:65be27845400	258	typedef struct
AnnaBridge	172:65be27845400	259	{
AnnaBridge	172:65be27845400	260	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	172:65be27845400	261	the duration of the address setup time.
AnnaBridge	172:65be27845400	262	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	172:65be27845400	263	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	172:65be27845400	264
AnnaBridge	172:65be27845400	265	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	172:65be27845400	266	the duration of the address hold time.
AnnaBridge	172:65be27845400	267	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
AnnaBridge	172:65be27845400	268	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	172:65be27845400	269
AnnaBridge	172:65be27845400	270	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	172:65be27845400	271	the duration of the data setup time.
AnnaBridge	172:65be27845400	272	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
AnnaBridge	172:65be27845400	273	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
AnnaBridge	172:65be27845400	274	NOR Flash memories. */
AnnaBridge	172:65be27845400	275
AnnaBridge	172:65be27845400	276	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	172:65be27845400	277	the duration of the bus turnaround.
AnnaBridge	172:65be27845400	278	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	172:65be27845400	279	@note This parameter is only used for multiplexed NOR Flash memories. */
AnnaBridge	172:65be27845400	280
AnnaBridge	172:65be27845400	281	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
AnnaBridge	172:65be27845400	282	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
AnnaBridge	172:65be27845400	283	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
AnnaBridge	172:65be27845400	284	accesses. */
AnnaBridge	172:65be27845400	285
AnnaBridge	172:65be27845400	286	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
AnnaBridge	172:65be27845400	287	to the memory before getting the first data.
AnnaBridge	172:65be27845400	288	The parameter value depends on the memory type as shown below:
AnnaBridge	172:65be27845400	289	- It must be set to 0 in case of a CRAM
AnnaBridge	172:65be27845400	290	- It is don't care in asynchronous NOR, SRAM or ROM accesses
AnnaBridge	172:65be27845400	291	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
AnnaBridge	172:65be27845400	292	with synchronous burst mode enable */
AnnaBridge	172:65be27845400	293
AnnaBridge	172:65be27845400	294	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
AnnaBridge	172:65be27845400	295	This parameter can be a value of @ref FMC_Access_Mode */
AnnaBridge	172:65be27845400	296	}FMC_NORSRAM_TimingTypeDef;
AnnaBridge	172:65be27845400	297
AnnaBridge	172:65be27845400	298	/**
AnnaBridge	172:65be27845400	299	* @brief FMC NAND Configuration Structure definition
AnnaBridge	172:65be27845400	300	*/
AnnaBridge	172:65be27845400	301	typedef struct
AnnaBridge	172:65be27845400	302	{
AnnaBridge	172:65be27845400	303	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
AnnaBridge	172:65be27845400	304	This parameter can be a value of @ref FMC_NAND_Bank */
AnnaBridge	172:65be27845400	305
AnnaBridge	172:65be27845400	306	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
AnnaBridge	172:65be27845400	307	This parameter can be any value of @ref FMC_Wait_feature */
AnnaBridge	172:65be27845400	308
AnnaBridge	172:65be27845400	309	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	172:65be27845400	310	This parameter can be any value of @ref FMC_NAND_Data_Width */
AnnaBridge	172:65be27845400	311
AnnaBridge	172:65be27845400	312	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
AnnaBridge	172:65be27845400	313	This parameter can be any value of @ref FMC_ECC */
AnnaBridge	172:65be27845400	314
AnnaBridge	172:65be27845400	315	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
AnnaBridge	172:65be27845400	316	This parameter can be any value of @ref FMC_ECC_Page_Size */
AnnaBridge	172:65be27845400	317
AnnaBridge	172:65be27845400	318	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	172:65be27845400	319	delay between CLE low and RE low.
AnnaBridge	172:65be27845400	320	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	172:65be27845400	321
AnnaBridge	172:65be27845400	322	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	172:65be27845400	323	delay between ALE low and RE low.
AnnaBridge	172:65be27845400	324	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	172:65be27845400	325	}FMC_NAND_InitTypeDef;
AnnaBridge	172:65be27845400	326
AnnaBridge	172:65be27845400	327	/**
AnnaBridge	172:65be27845400	328	* @brief FMC NAND Timing parameters structure definition
AnnaBridge	172:65be27845400	329	*/
AnnaBridge	172:65be27845400	330	typedef struct
AnnaBridge	172:65be27845400	331	{
AnnaBridge	172:65be27845400	332	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
AnnaBridge	172:65be27845400	333	the command assertion for NAND-Flash read or write access
AnnaBridge	172:65be27845400	334	to common/Attribute or I/O memory space (depending on
AnnaBridge	172:65be27845400	335	the memory space timing to be configured).
AnnaBridge	172:65be27845400	336	This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
AnnaBridge	172:65be27845400	337
AnnaBridge	172:65be27845400	338	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
AnnaBridge	172:65be27845400	339	command for NAND-Flash read or write access to
AnnaBridge	172:65be27845400	340	common/Attribute or I/O memory space (depending on the
AnnaBridge	172:65be27845400	341	memory space timing to be configured).
AnnaBridge	172:65be27845400	342	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
AnnaBridge	172:65be27845400	343
AnnaBridge	172:65be27845400	344	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
AnnaBridge	172:65be27845400	345	(and data for write access) after the command de-assertion
AnnaBridge	172:65be27845400	346	for NAND-Flash read or write access to common/Attribute
AnnaBridge	172:65be27845400	347	or I/O memory space (depending on the memory space timing
AnnaBridge	172:65be27845400	348	to be configured).
AnnaBridge	172:65be27845400	349	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
AnnaBridge	172:65be27845400	350
AnnaBridge	172:65be27845400	351	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
AnnaBridge	172:65be27845400	352	data bus is kept in HiZ after the start of a NAND-Flash
AnnaBridge	172:65be27845400	353	write access to common/Attribute or I/O memory space (depending
AnnaBridge	172:65be27845400	354	on the memory space timing to be configured).
AnnaBridge	172:65be27845400	355	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
AnnaBridge	172:65be27845400	356	}FMC_NAND_PCC_TimingTypeDef;
AnnaBridge	172:65be27845400	357
AnnaBridge	172:65be27845400	358	/**
AnnaBridge	172:65be27845400	359	* @brief FMC SDRAM Configuration Structure definition
AnnaBridge	172:65be27845400	360	*/
AnnaBridge	172:65be27845400	361	typedef struct
AnnaBridge	172:65be27845400	362	{
AnnaBridge	172:65be27845400	363	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
AnnaBridge	172:65be27845400	364	This parameter can be a value of @ref FMC_SDRAM_Bank */
AnnaBridge	172:65be27845400	365
AnnaBridge	172:65be27845400	366	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
AnnaBridge	172:65be27845400	367	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
AnnaBridge	172:65be27845400	368
AnnaBridge	172:65be27845400	369	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
AnnaBridge	172:65be27845400	370	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
AnnaBridge	172:65be27845400	371
AnnaBridge	172:65be27845400	372	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
AnnaBridge	172:65be27845400	373	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
AnnaBridge	172:65be27845400	374
AnnaBridge	172:65be27845400	375	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
AnnaBridge	172:65be27845400	376	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
AnnaBridge	172:65be27845400	377
AnnaBridge	172:65be27845400	378	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
AnnaBridge	172:65be27845400	379	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
AnnaBridge	172:65be27845400	380
AnnaBridge	172:65be27845400	381	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
AnnaBridge	172:65be27845400	382	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
AnnaBridge	172:65be27845400	383
AnnaBridge	172:65be27845400	384	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
AnnaBridge	172:65be27845400	385	to disable the clock before changing frequency.
AnnaBridge	172:65be27845400	386	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
AnnaBridge	172:65be27845400	387
AnnaBridge	172:65be27845400	388	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
AnnaBridge	172:65be27845400	389	commands during the CAS latency and stores data in the Read FIFO.
AnnaBridge	172:65be27845400	390	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
AnnaBridge	172:65be27845400	391
AnnaBridge	172:65be27845400	392	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
AnnaBridge	172:65be27845400	393	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
AnnaBridge	172:65be27845400	394	}FMC_SDRAM_InitTypeDef;
AnnaBridge	172:65be27845400	395
AnnaBridge	172:65be27845400	396	/**
AnnaBridge	172:65be27845400	397	* @brief FMC SDRAM Timing parameters structure definition
AnnaBridge	172:65be27845400	398	*/
AnnaBridge	172:65be27845400	399	typedef struct
AnnaBridge	172:65be27845400	400	{
AnnaBridge	172:65be27845400	401	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
AnnaBridge	172:65be27845400	402	an active or Refresh command in number of memory clock cycles.
AnnaBridge	172:65be27845400	403	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	172:65be27845400	404
AnnaBridge	172:65be27845400	405	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
AnnaBridge	172:65be27845400	406	issuing the Activate command in number of memory clock cycles.
AnnaBridge	172:65be27845400	407	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	172:65be27845400	408
AnnaBridge	172:65be27845400	409	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
AnnaBridge	172:65be27845400	410	cycles.
AnnaBridge	172:65be27845400	411	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	172:65be27845400	412
AnnaBridge	172:65be27845400	413	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
AnnaBridge	172:65be27845400	414	and the delay between two consecutive Refresh commands in number of
AnnaBridge	172:65be27845400	415	memory clock cycles.
AnnaBridge	172:65be27845400	416	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	172:65be27845400	417
AnnaBridge	172:65be27845400	418	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
AnnaBridge	172:65be27845400	419	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	172:65be27845400	420
AnnaBridge	172:65be27845400	421	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
AnnaBridge	172:65be27845400	422	in number of memory clock cycles.
AnnaBridge	172:65be27845400	423	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	172:65be27845400	424
AnnaBridge	172:65be27845400	425	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
AnnaBridge	172:65be27845400	426	command in number of memory clock cycles.
AnnaBridge	172:65be27845400	427	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	172:65be27845400	428	}FMC_SDRAM_TimingTypeDef;
AnnaBridge	172:65be27845400	429
AnnaBridge	172:65be27845400	430	/**
AnnaBridge	172:65be27845400	431	* @brief SDRAM command parameters structure definition
AnnaBridge	172:65be27845400	432	*/
AnnaBridge	172:65be27845400	433	typedef struct
AnnaBridge	172:65be27845400	434	{
AnnaBridge	172:65be27845400	435	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
AnnaBridge	172:65be27845400	436	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
AnnaBridge	172:65be27845400	437
AnnaBridge	172:65be27845400	438	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
AnnaBridge	172:65be27845400	439	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
AnnaBridge	172:65be27845400	440
AnnaBridge	172:65be27845400	441	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
AnnaBridge	172:65be27845400	442	in auto refresh mode.
AnnaBridge	172:65be27845400	443	This parameter can be a value between Min_Data = 1 and Max_Data = 15 */
AnnaBridge	172:65be27845400	444
AnnaBridge	172:65be27845400	445	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
AnnaBridge	172:65be27845400	446	}FMC_SDRAM_CommandTypeDef;
AnnaBridge	172:65be27845400	447	/**
AnnaBridge	172:65be27845400	448	* @}
AnnaBridge	172:65be27845400	449	*/
AnnaBridge	172:65be27845400	450
AnnaBridge	172:65be27845400	451	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	452	/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
AnnaBridge	172:65be27845400	453	* @{
AnnaBridge	172:65be27845400	454	*/
AnnaBridge	172:65be27845400	455
AnnaBridge	172:65be27845400	456	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
AnnaBridge	172:65be27845400	457	* @{
AnnaBridge	172:65be27845400	458	*/
AnnaBridge	172:65be27845400	459
AnnaBridge	172:65be27845400	460	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
AnnaBridge	172:65be27845400	461	* @{
AnnaBridge	172:65be27845400	462	*/
AnnaBridge	172:65be27845400	463	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	464	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
AnnaBridge	172:65be27845400	465	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
AnnaBridge	172:65be27845400	466	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
AnnaBridge	172:65be27845400	467	/**
AnnaBridge	172:65be27845400	468	* @}
AnnaBridge	172:65be27845400	469	*/
AnnaBridge	172:65be27845400	470
AnnaBridge	172:65be27845400	471	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
AnnaBridge	172:65be27845400	472	* @{
AnnaBridge	172:65be27845400	473	*/
AnnaBridge	172:65be27845400	474	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	475	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
AnnaBridge	172:65be27845400	476	/**
AnnaBridge	172:65be27845400	477	* @}
AnnaBridge	172:65be27845400	478	*/
AnnaBridge	172:65be27845400	479
AnnaBridge	172:65be27845400	480	/** @defgroup FMC_Memory_Type FMC Memory Type
AnnaBridge	172:65be27845400	481	* @{
AnnaBridge	172:65be27845400	482	*/
AnnaBridge	172:65be27845400	483	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	484	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
AnnaBridge	172:65be27845400	485	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
AnnaBridge	172:65be27845400	486	/**
AnnaBridge	172:65be27845400	487	* @}
AnnaBridge	172:65be27845400	488	*/
AnnaBridge	172:65be27845400	489
AnnaBridge	172:65be27845400	490	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
AnnaBridge	172:65be27845400	491	* @{
AnnaBridge	172:65be27845400	492	*/
AnnaBridge	172:65be27845400	493	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	494	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
AnnaBridge	172:65be27845400	495	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
AnnaBridge	172:65be27845400	496	/**
AnnaBridge	172:65be27845400	497	* @}
AnnaBridge	172:65be27845400	498	*/
AnnaBridge	172:65be27845400	499
AnnaBridge	172:65be27845400	500	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
AnnaBridge	172:65be27845400	501	* @{
AnnaBridge	172:65be27845400	502	*/
AnnaBridge	172:65be27845400	503	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
AnnaBridge	172:65be27845400	504	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	505	/**
AnnaBridge	172:65be27845400	506	* @}
AnnaBridge	172:65be27845400	507	*/
AnnaBridge	172:65be27845400	508
AnnaBridge	172:65be27845400	509	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
AnnaBridge	172:65be27845400	510	* @{
AnnaBridge	172:65be27845400	511	*/
AnnaBridge	172:65be27845400	512	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	513	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
AnnaBridge	172:65be27845400	514	/**
AnnaBridge	172:65be27845400	515	* @}
AnnaBridge	172:65be27845400	516	*/
AnnaBridge	172:65be27845400	517
AnnaBridge	172:65be27845400	518	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
AnnaBridge	172:65be27845400	519	* @{
AnnaBridge	172:65be27845400	520	*/
AnnaBridge	172:65be27845400	521	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	522	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
AnnaBridge	172:65be27845400	523	/**
AnnaBridge	172:65be27845400	524	* @}
AnnaBridge	172:65be27845400	525	*/
AnnaBridge	172:65be27845400	526
AnnaBridge	172:65be27845400	527	/** @defgroup FMC_Wait_Timing FMC Wait Timing
AnnaBridge	172:65be27845400	528	* @{
AnnaBridge	172:65be27845400	529	*/
AnnaBridge	172:65be27845400	530	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	531	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
AnnaBridge	172:65be27845400	532	/**
AnnaBridge	172:65be27845400	533	* @}
AnnaBridge	172:65be27845400	534	*/
AnnaBridge	172:65be27845400	535
AnnaBridge	172:65be27845400	536	/** @defgroup FMC_Write_Operation FMC Write Operation
AnnaBridge	172:65be27845400	537	* @{
AnnaBridge	172:65be27845400	538	*/
AnnaBridge	172:65be27845400	539	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	540	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
AnnaBridge	172:65be27845400	541	/**
AnnaBridge	172:65be27845400	542	* @}
AnnaBridge	172:65be27845400	543	*/
AnnaBridge	172:65be27845400	544
AnnaBridge	172:65be27845400	545	/** @defgroup FMC_Wait_Signal FMC Wait Signal
AnnaBridge	172:65be27845400	546	* @{
AnnaBridge	172:65be27845400	547	*/
AnnaBridge	172:65be27845400	548	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	549	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
AnnaBridge	172:65be27845400	550	/**
AnnaBridge	172:65be27845400	551	* @}
AnnaBridge	172:65be27845400	552	*/
AnnaBridge	172:65be27845400	553
AnnaBridge	172:65be27845400	554	/** @defgroup FMC_Extended_Mode FMC Extended Mode
AnnaBridge	172:65be27845400	555	* @{
AnnaBridge	172:65be27845400	556	*/
AnnaBridge	172:65be27845400	557	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	558	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
AnnaBridge	172:65be27845400	559	/**
AnnaBridge	172:65be27845400	560	* @}
AnnaBridge	172:65be27845400	561	*/
AnnaBridge	172:65be27845400	562
AnnaBridge	172:65be27845400	563	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
AnnaBridge	172:65be27845400	564	* @{
AnnaBridge	172:65be27845400	565	*/
AnnaBridge	172:65be27845400	566	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	567	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
AnnaBridge	172:65be27845400	568	/**
AnnaBridge	172:65be27845400	569	* @}
AnnaBridge	172:65be27845400	570	*/
AnnaBridge	172:65be27845400	571
AnnaBridge	172:65be27845400	572	/** @defgroup FMC_Page_Size FMC Page Size
AnnaBridge	172:65be27845400	573	* @{
AnnaBridge	172:65be27845400	574	*/
AnnaBridge	172:65be27845400	575	#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	576	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0)
AnnaBridge	172:65be27845400	577	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1)
AnnaBridge	172:65be27845400	578	#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 \| FMC_BCRx_CPSIZE_1))
AnnaBridge	172:65be27845400	579	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2)
AnnaBridge	172:65be27845400	580	/**
AnnaBridge	172:65be27845400	581	* @}
AnnaBridge	172:65be27845400	582	*/
AnnaBridge	172:65be27845400	583
AnnaBridge	172:65be27845400	584	/** @defgroup FMC_Write_Burst FMC Write Burst
AnnaBridge	172:65be27845400	585	* @{
AnnaBridge	172:65be27845400	586	*/
AnnaBridge	172:65be27845400	587	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	588	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
AnnaBridge	172:65be27845400	589	/**
AnnaBridge	172:65be27845400	590	* @}
AnnaBridge	172:65be27845400	591	*/
AnnaBridge	172:65be27845400	592
AnnaBridge	172:65be27845400	593	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
AnnaBridge	172:65be27845400	594	* @{
AnnaBridge	172:65be27845400	595	*/
AnnaBridge	172:65be27845400	596	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	597	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
AnnaBridge	172:65be27845400	598	/**
AnnaBridge	172:65be27845400	599	* @}
AnnaBridge	172:65be27845400	600	*/
AnnaBridge	172:65be27845400	601
AnnaBridge	172:65be27845400	602	/** @defgroup FMC_Write_FIFO FMC Write FIFO
AnnaBridge	172:65be27845400	603	* @{
AnnaBridge	172:65be27845400	604	*/
AnnaBridge	172:65be27845400	605	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
AnnaBridge	172:65be27845400	606	#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	607	/**
AnnaBridge	172:65be27845400	608	* @}
AnnaBridge	172:65be27845400	609	*/
AnnaBridge	172:65be27845400	610
AnnaBridge	172:65be27845400	611	/** @defgroup FMC_Access_Mode FMC Access Mode
AnnaBridge	172:65be27845400	612	* @{
AnnaBridge	172:65be27845400	613	*/
AnnaBridge	172:65be27845400	614	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	615	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
AnnaBridge	172:65be27845400	616	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
AnnaBridge	172:65be27845400	617	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
AnnaBridge	172:65be27845400	618	/**
AnnaBridge	172:65be27845400	619	* @}
AnnaBridge	172:65be27845400	620	*/
AnnaBridge	172:65be27845400	621
AnnaBridge	172:65be27845400	622	/** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup
AnnaBridge	172:65be27845400	623	* @{
AnnaBridge	172:65be27845400	624	*/
AnnaBridge	172:65be27845400	625	#define FMC_NBL_SETUPTIME_0 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	626	#define FMC_NBL_SETUPTIME_1 ((uint32_t)0x00400000U)
AnnaBridge	172:65be27845400	627	#define FMC_NBL_SETUPTIME_2 ((uint32_t)0x00800000U)
AnnaBridge	172:65be27845400	628	#define FMC_NBL_SETUPTIME_3 ((uint32_t)0x00C00000U)
AnnaBridge	172:65be27845400	629	/**
AnnaBridge	172:65be27845400	630	* @}
AnnaBridge	172:65be27845400	631	*/
AnnaBridge	172:65be27845400	632
AnnaBridge	172:65be27845400	633	/**
AnnaBridge	172:65be27845400	634	* @}
AnnaBridge	172:65be27845400	635	*/
AnnaBridge	172:65be27845400	636
AnnaBridge	172:65be27845400	637
AnnaBridge	172:65be27845400	638	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
AnnaBridge	172:65be27845400	639	* @{
AnnaBridge	172:65be27845400	640	*/
AnnaBridge	172:65be27845400	641	/** @defgroup FMC_NAND_Bank FMC NAND Bank
AnnaBridge	172:65be27845400	642	* @{
AnnaBridge	172:65be27845400	643	*/
AnnaBridge	172:65be27845400	644	#define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
AnnaBridge	172:65be27845400	645	/**
AnnaBridge	172:65be27845400	646	* @}
AnnaBridge	172:65be27845400	647	*/
AnnaBridge	172:65be27845400	648
AnnaBridge	172:65be27845400	649	/** @defgroup FMC_Wait_feature FMC Wait feature
AnnaBridge	172:65be27845400	650	* @{
AnnaBridge	172:65be27845400	651	*/
AnnaBridge	172:65be27845400	652	#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	653	#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
AnnaBridge	172:65be27845400	654	/**
AnnaBridge	172:65be27845400	655	* @}
AnnaBridge	172:65be27845400	656	*/
AnnaBridge	172:65be27845400	657
AnnaBridge	172:65be27845400	658	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
AnnaBridge	172:65be27845400	659	* @{
AnnaBridge	172:65be27845400	660	*/
AnnaBridge	172:65be27845400	661	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
AnnaBridge	172:65be27845400	662	/**
AnnaBridge	172:65be27845400	663	* @}
AnnaBridge	172:65be27845400	664	*/
AnnaBridge	172:65be27845400	665
AnnaBridge	172:65be27845400	666	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
AnnaBridge	172:65be27845400	667	* @{
AnnaBridge	172:65be27845400	668	*/
AnnaBridge	172:65be27845400	669	#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	670	#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
AnnaBridge	172:65be27845400	671	/**
AnnaBridge	172:65be27845400	672	* @}
AnnaBridge	172:65be27845400	673	*/
AnnaBridge	172:65be27845400	674
AnnaBridge	172:65be27845400	675	/** @defgroup FMC_ECC FMC ECC
AnnaBridge	172:65be27845400	676	* @{
AnnaBridge	172:65be27845400	677	*/
AnnaBridge	172:65be27845400	678	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	679	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
AnnaBridge	172:65be27845400	680	/**
AnnaBridge	172:65be27845400	681	* @}
AnnaBridge	172:65be27845400	682	*/
AnnaBridge	172:65be27845400	683
AnnaBridge	172:65be27845400	684	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
AnnaBridge	172:65be27845400	685	* @{
AnnaBridge	172:65be27845400	686	*/
AnnaBridge	172:65be27845400	687	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	688	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
AnnaBridge	172:65be27845400	689	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
AnnaBridge	172:65be27845400	690	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
AnnaBridge	172:65be27845400	691	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
AnnaBridge	172:65be27845400	692	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
AnnaBridge	172:65be27845400	693	/**
AnnaBridge	172:65be27845400	694	* @}
AnnaBridge	172:65be27845400	695	*/
AnnaBridge	172:65be27845400	696
AnnaBridge	172:65be27845400	697	/**
AnnaBridge	172:65be27845400	698	* @}
AnnaBridge	172:65be27845400	699	*/
AnnaBridge	172:65be27845400	700
AnnaBridge	172:65be27845400	701	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
AnnaBridge	172:65be27845400	702	* @{
AnnaBridge	172:65be27845400	703	*/
AnnaBridge	172:65be27845400	704	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
AnnaBridge	172:65be27845400	705	* @{
AnnaBridge	172:65be27845400	706	*/
AnnaBridge	172:65be27845400	707	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	708	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
AnnaBridge	172:65be27845400	709	/**
AnnaBridge	172:65be27845400	710	* @}
AnnaBridge	172:65be27845400	711	*/
AnnaBridge	172:65be27845400	712
AnnaBridge	172:65be27845400	713	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
AnnaBridge	172:65be27845400	714	* @{
AnnaBridge	172:65be27845400	715	*/
AnnaBridge	172:65be27845400	716	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	717	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
AnnaBridge	172:65be27845400	718	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
AnnaBridge	172:65be27845400	719	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
AnnaBridge	172:65be27845400	720	/**
AnnaBridge	172:65be27845400	721	* @}
AnnaBridge	172:65be27845400	722	*/
AnnaBridge	172:65be27845400	723
AnnaBridge	172:65be27845400	724	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
AnnaBridge	172:65be27845400	725	* @{
AnnaBridge	172:65be27845400	726	*/
AnnaBridge	172:65be27845400	727	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	728	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
AnnaBridge	172:65be27845400	729	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
AnnaBridge	172:65be27845400	730	/**
AnnaBridge	172:65be27845400	731	* @}
AnnaBridge	172:65be27845400	732	*/
AnnaBridge	172:65be27845400	733
AnnaBridge	172:65be27845400	734	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
AnnaBridge	172:65be27845400	735	* @{
AnnaBridge	172:65be27845400	736	*/
AnnaBridge	172:65be27845400	737	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	738	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
AnnaBridge	172:65be27845400	739	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
AnnaBridge	172:65be27845400	740	/**
AnnaBridge	172:65be27845400	741	* @}
AnnaBridge	172:65be27845400	742	*/
AnnaBridge	172:65be27845400	743
AnnaBridge	172:65be27845400	744	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
AnnaBridge	172:65be27845400	745	* @{
AnnaBridge	172:65be27845400	746	*/
AnnaBridge	172:65be27845400	747	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	748	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
AnnaBridge	172:65be27845400	749	/**
AnnaBridge	172:65be27845400	750	* @}
AnnaBridge	172:65be27845400	751	*/
AnnaBridge	172:65be27845400	752
AnnaBridge	172:65be27845400	753	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
AnnaBridge	172:65be27845400	754	* @{
AnnaBridge	172:65be27845400	755	*/
AnnaBridge	172:65be27845400	756	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
AnnaBridge	172:65be27845400	757	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
AnnaBridge	172:65be27845400	758	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
AnnaBridge	172:65be27845400	759	/**
AnnaBridge	172:65be27845400	760	* @}
AnnaBridge	172:65be27845400	761	*/
AnnaBridge	172:65be27845400	762
AnnaBridge	172:65be27845400	763	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
AnnaBridge	172:65be27845400	764	* @{
AnnaBridge	172:65be27845400	765	*/
AnnaBridge	172:65be27845400	766	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	767	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
AnnaBridge	172:65be27845400	768	/**
AnnaBridge	172:65be27845400	769	* @}
AnnaBridge	172:65be27845400	770	*/
AnnaBridge	172:65be27845400	771
AnnaBridge	172:65be27845400	772	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
AnnaBridge	172:65be27845400	773	* @{
AnnaBridge	172:65be27845400	774	*/
AnnaBridge	172:65be27845400	775	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	776	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
AnnaBridge	172:65be27845400	777	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
AnnaBridge	172:65be27845400	778	/**
AnnaBridge	172:65be27845400	779	* @}
AnnaBridge	172:65be27845400	780	*/
AnnaBridge	172:65be27845400	781
AnnaBridge	172:65be27845400	782	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
AnnaBridge	172:65be27845400	783	* @{
AnnaBridge	172:65be27845400	784	*/
AnnaBridge	172:65be27845400	785	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	786	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
AnnaBridge	172:65be27845400	787	/**
AnnaBridge	172:65be27845400	788	* @}
AnnaBridge	172:65be27845400	789	*/
AnnaBridge	172:65be27845400	790
AnnaBridge	172:65be27845400	791	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
AnnaBridge	172:65be27845400	792	* @{
AnnaBridge	172:65be27845400	793	*/
AnnaBridge	172:65be27845400	794	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	795	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
AnnaBridge	172:65be27845400	796	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
AnnaBridge	172:65be27845400	797	/**
AnnaBridge	172:65be27845400	798	* @}
AnnaBridge	172:65be27845400	799	*/
AnnaBridge	172:65be27845400	800
AnnaBridge	172:65be27845400	801	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
AnnaBridge	172:65be27845400	802	* @{
AnnaBridge	172:65be27845400	803	*/
AnnaBridge	172:65be27845400	804	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	805	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
AnnaBridge	172:65be27845400	806	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
AnnaBridge	172:65be27845400	807	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
AnnaBridge	172:65be27845400	808	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
AnnaBridge	172:65be27845400	809	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
AnnaBridge	172:65be27845400	810	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
AnnaBridge	172:65be27845400	811	/**
AnnaBridge	172:65be27845400	812	* @}
AnnaBridge	172:65be27845400	813	*/
AnnaBridge	172:65be27845400	814
AnnaBridge	172:65be27845400	815	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
AnnaBridge	172:65be27845400	816	* @{
AnnaBridge	172:65be27845400	817	*/
AnnaBridge	172:65be27845400	818	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
AnnaBridge	172:65be27845400	819	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
AnnaBridge	172:65be27845400	820	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
AnnaBridge	172:65be27845400	821	/**
AnnaBridge	172:65be27845400	822	* @}
AnnaBridge	172:65be27845400	823	*/
AnnaBridge	172:65be27845400	824
AnnaBridge	172:65be27845400	825	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
AnnaBridge	172:65be27845400	826	* @{
AnnaBridge	172:65be27845400	827	*/
AnnaBridge	172:65be27845400	828	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	829	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
AnnaBridge	172:65be27845400	830	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
AnnaBridge	172:65be27845400	831	/**
AnnaBridge	172:65be27845400	832	* @}
AnnaBridge	172:65be27845400	833	*/
AnnaBridge	172:65be27845400	834
AnnaBridge	172:65be27845400	835	/**
AnnaBridge	172:65be27845400	836	* @}
AnnaBridge	172:65be27845400	837	*/
AnnaBridge	172:65be27845400	838
AnnaBridge	172:65be27845400	839
AnnaBridge	172:65be27845400	840	/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
AnnaBridge	172:65be27845400	841	* @{
AnnaBridge	172:65be27845400	842	*/
AnnaBridge	172:65be27845400	843	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
AnnaBridge	172:65be27845400	844	#define FMC_IT_LEVEL ((uint32_t)0x00000010U)
AnnaBridge	172:65be27845400	845	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
AnnaBridge	172:65be27845400	846	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
AnnaBridge	172:65be27845400	847	/**
AnnaBridge	172:65be27845400	848	* @}
AnnaBridge	172:65be27845400	849	*/
AnnaBridge	172:65be27845400	850
AnnaBridge	172:65be27845400	851	/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
AnnaBridge	172:65be27845400	852	* @{
AnnaBridge	172:65be27845400	853	*/
AnnaBridge	172:65be27845400	854	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
AnnaBridge	172:65be27845400	855	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
AnnaBridge	172:65be27845400	856	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
AnnaBridge	172:65be27845400	857	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
AnnaBridge	172:65be27845400	858	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
AnnaBridge	172:65be27845400	859	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
AnnaBridge	172:65be27845400	860	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
AnnaBridge	172:65be27845400	861	/**
AnnaBridge	172:65be27845400	862	* @}
AnnaBridge	172:65be27845400	863	*/
AnnaBridge	172:65be27845400	864	/**
AnnaBridge	172:65be27845400	865	* @}
AnnaBridge	172:65be27845400	866	*/
AnnaBridge	172:65be27845400	867
AnnaBridge	172:65be27845400	868	/**
AnnaBridge	172:65be27845400	869	* @}
AnnaBridge	172:65be27845400	870	*/
AnnaBridge	172:65be27845400	871
AnnaBridge	172:65be27845400	872	/* Private macro -------------------------------------------------------------*/
AnnaBridge	172:65be27845400	873	/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
AnnaBridge	172:65be27845400	874	* @{
AnnaBridge	172:65be27845400	875	*/
AnnaBridge	172:65be27845400	876	/**
AnnaBridge	172:65be27845400	877	* @brief Enable the FMC Peripheral.
AnnaBridge	172:65be27845400	878	* @retval None
AnnaBridge	172:65be27845400	879	*/
AnnaBridge	172:65be27845400	880	#define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] \|= FMC_BCR1_FMCEN)
AnnaBridge	172:65be27845400	881
AnnaBridge	172:65be27845400	882	/**
AnnaBridge	172:65be27845400	883	* @brief Disable the FMC Peripheral.
AnnaBridge	172:65be27845400	884	* @retval None
AnnaBridge	172:65be27845400	885	*/
AnnaBridge	172:65be27845400	886	#define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
AnnaBridge	172:65be27845400	887	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
AnnaBridge	172:65be27845400	888	* @brief macros to handle NOR device enable/disable and read/write operations
AnnaBridge	172:65be27845400	889	* @{
AnnaBridge	172:65be27845400	890	*/
AnnaBridge	172:65be27845400	891
AnnaBridge	172:65be27845400	892	/**
AnnaBridge	172:65be27845400	893	* @brief Enable the NORSRAM device access.
AnnaBridge	172:65be27845400	894	* @param __INSTANCE__ FMC_NORSRAM Instance
AnnaBridge	172:65be27845400	895	* @param __BANK__ FMC_NORSRAM Bank
AnnaBridge	172:65be27845400	896	* @retval None
AnnaBridge	172:65be27845400	897	*/
AnnaBridge	172:65be27845400	898	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCRx_MBKEN)
AnnaBridge	172:65be27845400	899
AnnaBridge	172:65be27845400	900	/**
AnnaBridge	172:65be27845400	901	* @brief Disable the NORSRAM device access.
AnnaBridge	172:65be27845400	902	* @param __INSTANCE__ FMC_NORSRAM Instance
AnnaBridge	172:65be27845400	903	* @param __BANK__ FMC_NORSRAM Bank
AnnaBridge	172:65be27845400	904	* @retval None
AnnaBridge	172:65be27845400	905	*/
AnnaBridge	172:65be27845400	906	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN)
AnnaBridge	172:65be27845400	907
AnnaBridge	172:65be27845400	908	/**
AnnaBridge	172:65be27845400	909	* @}
AnnaBridge	172:65be27845400	910	*/
AnnaBridge	172:65be27845400	911
AnnaBridge	172:65be27845400	912	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
AnnaBridge	172:65be27845400	913	* @brief macros to handle NAND device enable/disable
AnnaBridge	172:65be27845400	914	* @{
AnnaBridge	172:65be27845400	915	*/
AnnaBridge	172:65be27845400	916
AnnaBridge	172:65be27845400	917	/**
AnnaBridge	172:65be27845400	918	* @brief Enable the NAND device access.
AnnaBridge	172:65be27845400	919	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	172:65be27845400	920	* @retval None
AnnaBridge	172:65be27845400	921	*/
AnnaBridge	172:65be27845400	922	#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
AnnaBridge	172:65be27845400	923
AnnaBridge	172:65be27845400	924	/**
AnnaBridge	172:65be27845400	925	* @brief Disable the NAND device access.
AnnaBridge	172:65be27845400	926	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	172:65be27845400	927	* @param __BANK__ FMC_NAND Bank
AnnaBridge	172:65be27845400	928	* @retval None
AnnaBridge	172:65be27845400	929	*/
AnnaBridge	172:65be27845400	930	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
AnnaBridge	172:65be27845400	931
AnnaBridge	172:65be27845400	932	/**
AnnaBridge	172:65be27845400	933	* @}
AnnaBridge	172:65be27845400	934	*/
AnnaBridge	172:65be27845400	935
AnnaBridge	172:65be27845400	936	/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt
AnnaBridge	172:65be27845400	937	* @brief macros to handle NAND interrupts
AnnaBridge	172:65be27845400	938	* @{
AnnaBridge	172:65be27845400	939	*/
AnnaBridge	172:65be27845400	940
AnnaBridge	172:65be27845400	941	/**
AnnaBridge	172:65be27845400	942	* @brief Enable the NAND device interrupt.
AnnaBridge	172:65be27845400	943	* @param __INSTANCE__ FMC_NAND instance
AnnaBridge	172:65be27845400	944	* @param __INTERRUPT__ FMC_NAND interrupt
AnnaBridge	172:65be27845400	945	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	946	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	172:65be27845400	947	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	172:65be27845400	948	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	172:65be27845400	949	* @retval None
AnnaBridge	172:65be27845400	950	*/
AnnaBridge	172:65be27845400	951	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
AnnaBridge	172:65be27845400	952
AnnaBridge	172:65be27845400	953	/**
AnnaBridge	172:65be27845400	954	* @brief Disable the NAND device interrupt.
AnnaBridge	172:65be27845400	955	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	172:65be27845400	956	* @param __INTERRUPT__ FMC_NAND interrupt
AnnaBridge	172:65be27845400	957	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	958	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	172:65be27845400	959	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	172:65be27845400	960	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	172:65be27845400	961	* @retval None
AnnaBridge	172:65be27845400	962	*/
AnnaBridge	172:65be27845400	963	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
AnnaBridge	172:65be27845400	964
AnnaBridge	172:65be27845400	965	/**
AnnaBridge	172:65be27845400	966	* @brief Get flag status of the NAND device.
AnnaBridge	172:65be27845400	967	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	172:65be27845400	968	* @param __BANK__ FMC_NAND Bank
AnnaBridge	172:65be27845400	969	* @param __FLAG__ FMC_NAND flag
AnnaBridge	172:65be27845400	970	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	971	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	172:65be27845400	972	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	172:65be27845400	973	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	172:65be27845400	974	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	172:65be27845400	975	* @retval The state of FLAG (SET or RESET).
AnnaBridge	172:65be27845400	976	*/
AnnaBridge	172:65be27845400	977	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge	172:65be27845400	978
AnnaBridge	172:65be27845400	979	/**
AnnaBridge	172:65be27845400	980	* @brief Clear flag status of the NAND device.
AnnaBridge	172:65be27845400	981	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	172:65be27845400	982	* @param __FLAG__ FMC_NAND flag
AnnaBridge	172:65be27845400	983	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	984	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	172:65be27845400	985	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	172:65be27845400	986	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	172:65be27845400	987	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	172:65be27845400	988	* @retval None
AnnaBridge	172:65be27845400	989	*/
AnnaBridge	172:65be27845400	990	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
AnnaBridge	172:65be27845400	991
AnnaBridge	172:65be27845400	992	/**
AnnaBridge	172:65be27845400	993	* @}
AnnaBridge	172:65be27845400	994	*/
AnnaBridge	172:65be27845400	995
AnnaBridge	172:65be27845400	996	/** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt
AnnaBridge	172:65be27845400	997	* @brief macros to handle SDRAM interrupts
AnnaBridge	172:65be27845400	998	* @{
AnnaBridge	172:65be27845400	999	*/
AnnaBridge	172:65be27845400	1000
AnnaBridge	172:65be27845400	1001	/**
AnnaBridge	172:65be27845400	1002	* @brief Enable the SDRAM device interrupt.
AnnaBridge	172:65be27845400	1003	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	172:65be27845400	1004	* @param __INTERRUPT__ FMC_SDRAM interrupt
AnnaBridge	172:65be27845400	1005	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	1006	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
AnnaBridge	172:65be27845400	1007	* @retval None
AnnaBridge	172:65be27845400	1008	*/
AnnaBridge	172:65be27845400	1009	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
AnnaBridge	172:65be27845400	1010
AnnaBridge	172:65be27845400	1011	/**
AnnaBridge	172:65be27845400	1012	* @brief Disable the SDRAM device interrupt.
AnnaBridge	172:65be27845400	1013	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	172:65be27845400	1014	* @param __INTERRUPT__ FMC_SDRAM interrupt
AnnaBridge	172:65be27845400	1015	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	1016	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
AnnaBridge	172:65be27845400	1017	* @retval None
AnnaBridge	172:65be27845400	1018	*/
AnnaBridge	172:65be27845400	1019	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
AnnaBridge	172:65be27845400	1020
AnnaBridge	172:65be27845400	1021	/**
AnnaBridge	172:65be27845400	1022	* @brief Get flag status of the SDRAM device.
AnnaBridge	172:65be27845400	1023	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	172:65be27845400	1024	* @param __FLAG__ FMC_SDRAM flag
AnnaBridge	172:65be27845400	1025	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	1026	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
AnnaBridge	172:65be27845400	1027	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
AnnaBridge	172:65be27845400	1028	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
AnnaBridge	172:65be27845400	1029	* @retval The state of FLAG (SET or RESET).
AnnaBridge	172:65be27845400	1030	*/
AnnaBridge	172:65be27845400	1031	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
AnnaBridge	172:65be27845400	1032
AnnaBridge	172:65be27845400	1033	/**
AnnaBridge	172:65be27845400	1034	* @brief Clear flag status of the SDRAM device.
AnnaBridge	172:65be27845400	1035	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	172:65be27845400	1036	* @param __FLAG__ FMC_SDRAM flag
AnnaBridge	172:65be27845400	1037	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	1038	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
AnnaBridge	172:65be27845400	1039	* @retval None
AnnaBridge	172:65be27845400	1040	*/
AnnaBridge	172:65be27845400	1041	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
AnnaBridge	172:65be27845400	1042
AnnaBridge	172:65be27845400	1043	/**
AnnaBridge	172:65be27845400	1044	* @}
AnnaBridge	172:65be27845400	1045	*/
AnnaBridge	172:65be27845400	1046	/**
AnnaBridge	172:65be27845400	1047	* @}
AnnaBridge	172:65be27845400	1048	*/
AnnaBridge	172:65be27845400	1049
AnnaBridge	172:65be27845400	1050	/**
AnnaBridge	172:65be27845400	1051	* @}
AnnaBridge	172:65be27845400	1052	*/
AnnaBridge	172:65be27845400	1053
AnnaBridge	172:65be27845400	1054	/* Private functions ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	1055	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
AnnaBridge	172:65be27845400	1056	* @{
AnnaBridge	172:65be27845400	1057	*/
AnnaBridge	172:65be27845400	1058
AnnaBridge	172:65be27845400	1059	/** @defgroup FMC_LL_NORSRAM NOR SRAM
AnnaBridge	172:65be27845400	1060	* @{
AnnaBridge	172:65be27845400	1061	*/
AnnaBridge	172:65be27845400	1062	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
AnnaBridge	172:65be27845400	1063	* @{
AnnaBridge	172:65be27845400	1064	*/
AnnaBridge	172:65be27845400	1065	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
AnnaBridge	172:65be27845400	1066	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	172:65be27845400	1067	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
AnnaBridge	172:65be27845400	1068	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
AnnaBridge	172:65be27845400	1069	/**
AnnaBridge	172:65be27845400	1070	* @}
AnnaBridge	172:65be27845400	1071	*/
AnnaBridge	172:65be27845400	1072
AnnaBridge	172:65be27845400	1073	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
AnnaBridge	172:65be27845400	1074	* @{
AnnaBridge	172:65be27845400	1075	*/
AnnaBridge	172:65be27845400	1076	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	172:65be27845400	1077	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	172:65be27845400	1078	/**
AnnaBridge	172:65be27845400	1079	* @}
AnnaBridge	172:65be27845400	1080	*/
AnnaBridge	172:65be27845400	1081	/**
AnnaBridge	172:65be27845400	1082	* @}
AnnaBridge	172:65be27845400	1083	*/
AnnaBridge	172:65be27845400	1084
AnnaBridge	172:65be27845400	1085	/** @defgroup FMC_LL_NAND NAND
AnnaBridge	172:65be27845400	1086	* @{
AnnaBridge	172:65be27845400	1087	*/
AnnaBridge	172:65be27845400	1088	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
AnnaBridge	172:65be27845400	1089	* @{
AnnaBridge	172:65be27845400	1090	*/
AnnaBridge	172:65be27845400	1091	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
AnnaBridge	172:65be27845400	1092	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	172:65be27845400	1093	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	172:65be27845400	1094	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	172:65be27845400	1095	/**
AnnaBridge	172:65be27845400	1096	* @}
AnnaBridge	172:65be27845400	1097	*/
AnnaBridge	172:65be27845400	1098
AnnaBridge	172:65be27845400	1099	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
AnnaBridge	172:65be27845400	1100	* @{
AnnaBridge	172:65be27845400	1101	*/
AnnaBridge	172:65be27845400	1102	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	172:65be27845400	1103	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	172:65be27845400	1104	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
AnnaBridge	172:65be27845400	1105	/**
AnnaBridge	172:65be27845400	1106	* @}
AnnaBridge	172:65be27845400	1107	*/
AnnaBridge	172:65be27845400	1108	/**
AnnaBridge	172:65be27845400	1109	* @}
AnnaBridge	172:65be27845400	1110	*/
AnnaBridge	172:65be27845400	1111
AnnaBridge	172:65be27845400	1112
AnnaBridge	172:65be27845400	1113	/** @defgroup FMC_LL_SDRAM SDRAM
AnnaBridge	172:65be27845400	1114	* @{
AnnaBridge	172:65be27845400	1115	*/
AnnaBridge	172:65be27845400	1116	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
AnnaBridge	172:65be27845400	1117	* @{
AnnaBridge	172:65be27845400	1118	*/
AnnaBridge	172:65be27845400	1119	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
AnnaBridge	172:65be27845400	1120	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	172:65be27845400	1121	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	172:65be27845400	1122
AnnaBridge	172:65be27845400	1123	/**
AnnaBridge	172:65be27845400	1124	* @}
AnnaBridge	172:65be27845400	1125	*/
AnnaBridge	172:65be27845400	1126
AnnaBridge	172:65be27845400	1127	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
AnnaBridge	172:65be27845400	1128	* @{
AnnaBridge	172:65be27845400	1129	*/
AnnaBridge	172:65be27845400	1130	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	172:65be27845400	1131	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	172:65be27845400	1132	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
AnnaBridge	172:65be27845400	1133	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
AnnaBridge	172:65be27845400	1134	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
AnnaBridge	172:65be27845400	1135	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	172:65be27845400	1136	/**
AnnaBridge	172:65be27845400	1137	* @}
AnnaBridge	172:65be27845400	1138	*/
AnnaBridge	172:65be27845400	1139
AnnaBridge	172:65be27845400	1140	/**
AnnaBridge	172:65be27845400	1141	* @}
AnnaBridge	172:65be27845400	1142	*/
AnnaBridge	172:65be27845400	1143
AnnaBridge	172:65be27845400	1144	/**
AnnaBridge	172:65be27845400	1145	* @}
AnnaBridge	172:65be27845400	1146	*/
AnnaBridge	172:65be27845400	1147
AnnaBridge	172:65be27845400	1148	/**
AnnaBridge	172:65be27845400	1149	* @}
AnnaBridge	172:65be27845400	1150	*/
AnnaBridge	172:65be27845400	1151
AnnaBridge	172:65be27845400	1152	/**
AnnaBridge	172:65be27845400	1153	* @}
AnnaBridge	172:65be27845400	1154	*/
AnnaBridge	172:65be27845400	1155
AnnaBridge	172:65be27845400	1156	#ifdef __cplusplus
AnnaBridge	172:65be27845400	1157	}
AnnaBridge	172:65be27845400	1158	#endif
AnnaBridge	172:65be27845400	1159
AnnaBridge	172:65be27845400	1160	#endif /* STM32H7xx_LL_FMC_H */
AnnaBridge	172:65be27845400	1161
AnnaBridge	172:65be27845400	1162	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/