The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
TARGET_NUCLEO_F767ZI/TOOLCHAIN_IAR/stm32f7xx_hal_tim.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f7xx_hal_tim.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of TIM HAL module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F7xx_HAL_TIM_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F7xx_HAL_TIM_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f7xx_hal_def.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F7xx_HAL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup TIM |
AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 53 | */ |
AnnaBridge | 171:3a7713b1edbc | 54 | |
AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 56 | /** @defgroup TIM_Exported_Types TIM Exported Types |
AnnaBridge | 171:3a7713b1edbc | 57 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 58 | */ |
AnnaBridge | 171:3a7713b1edbc | 59 | |
AnnaBridge | 171:3a7713b1edbc | 60 | /** |
AnnaBridge | 171:3a7713b1edbc | 61 | * @brief TIM Time base Configuration Structure definition |
AnnaBridge | 171:3a7713b1edbc | 62 | */ |
AnnaBridge | 171:3a7713b1edbc | 63 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 64 | { |
AnnaBridge | 171:3a7713b1edbc | 65 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
AnnaBridge | 171:3a7713b1edbc | 66 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
AnnaBridge | 171:3a7713b1edbc | 67 | |
AnnaBridge | 171:3a7713b1edbc | 68 | uint32_t CounterMode; /*!< Specifies the counter mode. |
AnnaBridge | 171:3a7713b1edbc | 69 | This parameter can be a value of @ref TIM_Counter_Mode */ |
AnnaBridge | 171:3a7713b1edbc | 70 | |
AnnaBridge | 171:3a7713b1edbc | 71 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
AnnaBridge | 171:3a7713b1edbc | 72 | Auto-Reload Register at the next update event. |
AnnaBridge | 171:3a7713b1edbc | 73 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
AnnaBridge | 171:3a7713b1edbc | 74 | |
AnnaBridge | 171:3a7713b1edbc | 75 | uint32_t ClockDivision; /*!< Specifies the clock division. |
AnnaBridge | 171:3a7713b1edbc | 76 | This parameter can be a value of @ref TIM_ClockDivision */ |
AnnaBridge | 171:3a7713b1edbc | 77 | |
AnnaBridge | 171:3a7713b1edbc | 78 | uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR down-counter |
AnnaBridge | 171:3a7713b1edbc | 79 | reaches zero, an update event is generated and counting restarts |
AnnaBridge | 171:3a7713b1edbc | 80 | from the RCR value (N). |
AnnaBridge | 171:3a7713b1edbc | 81 | This means in PWM mode that (N+1) corresponds to: |
AnnaBridge | 171:3a7713b1edbc | 82 | - the number of PWM periods in edge-aligned mode |
AnnaBridge | 171:3a7713b1edbc | 83 | - the number of half PWM period in center-aligned mode |
AnnaBridge | 171:3a7713b1edbc | 84 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
AnnaBridge | 171:3a7713b1edbc | 85 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 86 | |
AnnaBridge | 171:3a7713b1edbc | 87 | uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. |
AnnaBridge | 171:3a7713b1edbc | 88 | This parameter can be a value of @ref TIM_AutoReloadPreload */ |
AnnaBridge | 171:3a7713b1edbc | 89 | |
AnnaBridge | 171:3a7713b1edbc | 90 | } TIM_Base_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 91 | |
AnnaBridge | 171:3a7713b1edbc | 92 | /** |
AnnaBridge | 171:3a7713b1edbc | 93 | * @brief TIM Output Compare Configuration Structure definition |
AnnaBridge | 171:3a7713b1edbc | 94 | */ |
AnnaBridge | 171:3a7713b1edbc | 95 | |
AnnaBridge | 171:3a7713b1edbc | 96 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 97 | { |
AnnaBridge | 171:3a7713b1edbc | 98 | uint32_t OCMode; /*!< Specifies the TIM mode. |
AnnaBridge | 171:3a7713b1edbc | 99 | This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */ |
AnnaBridge | 171:3a7713b1edbc | 100 | |
AnnaBridge | 171:3a7713b1edbc | 101 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
AnnaBridge | 171:3a7713b1edbc | 102 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
AnnaBridge | 171:3a7713b1edbc | 103 | |
AnnaBridge | 171:3a7713b1edbc | 104 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
AnnaBridge | 171:3a7713b1edbc | 105 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 106 | |
AnnaBridge | 171:3a7713b1edbc | 107 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
AnnaBridge | 171:3a7713b1edbc | 108 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
AnnaBridge | 171:3a7713b1edbc | 109 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 110 | |
AnnaBridge | 171:3a7713b1edbc | 111 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
AnnaBridge | 171:3a7713b1edbc | 112 | This parameter can be a value of @ref TIM_Output_Fast_State |
AnnaBridge | 171:3a7713b1edbc | 113 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
AnnaBridge | 171:3a7713b1edbc | 114 | |
AnnaBridge | 171:3a7713b1edbc | 115 | |
AnnaBridge | 171:3a7713b1edbc | 116 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 171:3a7713b1edbc | 117 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
AnnaBridge | 171:3a7713b1edbc | 118 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 119 | |
AnnaBridge | 171:3a7713b1edbc | 120 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 171:3a7713b1edbc | 121 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
AnnaBridge | 171:3a7713b1edbc | 122 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 123 | } TIM_OC_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 124 | |
AnnaBridge | 171:3a7713b1edbc | 125 | /** |
AnnaBridge | 171:3a7713b1edbc | 126 | * @brief TIM One Pulse Mode Configuration Structure definition |
AnnaBridge | 171:3a7713b1edbc | 127 | */ |
AnnaBridge | 171:3a7713b1edbc | 128 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 129 | { |
AnnaBridge | 171:3a7713b1edbc | 130 | uint32_t OCMode; /*!< Specifies the TIM mode. |
AnnaBridge | 171:3a7713b1edbc | 131 | This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */ |
AnnaBridge | 171:3a7713b1edbc | 132 | |
AnnaBridge | 171:3a7713b1edbc | 133 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
AnnaBridge | 171:3a7713b1edbc | 134 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
AnnaBridge | 171:3a7713b1edbc | 135 | |
AnnaBridge | 171:3a7713b1edbc | 136 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
AnnaBridge | 171:3a7713b1edbc | 137 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 138 | |
AnnaBridge | 171:3a7713b1edbc | 139 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
AnnaBridge | 171:3a7713b1edbc | 140 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
AnnaBridge | 171:3a7713b1edbc | 141 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 142 | |
AnnaBridge | 171:3a7713b1edbc | 143 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 171:3a7713b1edbc | 144 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
AnnaBridge | 171:3a7713b1edbc | 145 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 146 | |
AnnaBridge | 171:3a7713b1edbc | 147 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 171:3a7713b1edbc | 148 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
AnnaBridge | 171:3a7713b1edbc | 149 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 150 | |
AnnaBridge | 171:3a7713b1edbc | 151 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 171:3a7713b1edbc | 152 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 153 | |
AnnaBridge | 171:3a7713b1edbc | 154 | uint32_t ICSelection; /*!< Specifies the input. |
AnnaBridge | 171:3a7713b1edbc | 155 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 156 | |
AnnaBridge | 171:3a7713b1edbc | 157 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
AnnaBridge | 171:3a7713b1edbc | 158 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 159 | } TIM_OnePulse_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 160 | |
AnnaBridge | 171:3a7713b1edbc | 161 | |
AnnaBridge | 171:3a7713b1edbc | 162 | /** |
AnnaBridge | 171:3a7713b1edbc | 163 | * @brief TIM Input Capture Configuration Structure definition |
AnnaBridge | 171:3a7713b1edbc | 164 | */ |
AnnaBridge | 171:3a7713b1edbc | 165 | |
AnnaBridge | 171:3a7713b1edbc | 166 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 167 | { |
AnnaBridge | 171:3a7713b1edbc | 168 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 171:3a7713b1edbc | 169 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 170 | |
AnnaBridge | 171:3a7713b1edbc | 171 | uint32_t ICSelection; /*!< Specifies the input. |
AnnaBridge | 171:3a7713b1edbc | 172 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 173 | |
AnnaBridge | 171:3a7713b1edbc | 174 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 171:3a7713b1edbc | 175 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 176 | |
AnnaBridge | 171:3a7713b1edbc | 177 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
AnnaBridge | 171:3a7713b1edbc | 178 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 179 | } TIM_IC_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 180 | |
AnnaBridge | 171:3a7713b1edbc | 181 | /** |
AnnaBridge | 171:3a7713b1edbc | 182 | * @brief TIM Encoder Configuration Structure definition |
AnnaBridge | 171:3a7713b1edbc | 183 | */ |
AnnaBridge | 171:3a7713b1edbc | 184 | |
AnnaBridge | 171:3a7713b1edbc | 185 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 186 | { |
AnnaBridge | 171:3a7713b1edbc | 187 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 171:3a7713b1edbc | 188 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
AnnaBridge | 171:3a7713b1edbc | 189 | |
AnnaBridge | 171:3a7713b1edbc | 190 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 171:3a7713b1edbc | 191 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 192 | |
AnnaBridge | 171:3a7713b1edbc | 193 | uint32_t IC1Selection; /*!< Specifies the input. |
AnnaBridge | 171:3a7713b1edbc | 194 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 195 | |
AnnaBridge | 171:3a7713b1edbc | 196 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 171:3a7713b1edbc | 197 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 198 | |
AnnaBridge | 171:3a7713b1edbc | 199 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
AnnaBridge | 171:3a7713b1edbc | 200 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 201 | |
AnnaBridge | 171:3a7713b1edbc | 202 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 171:3a7713b1edbc | 203 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 204 | |
AnnaBridge | 171:3a7713b1edbc | 205 | uint32_t IC2Selection; /*!< Specifies the input. |
AnnaBridge | 171:3a7713b1edbc | 206 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 207 | |
AnnaBridge | 171:3a7713b1edbc | 208 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 171:3a7713b1edbc | 209 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 210 | |
AnnaBridge | 171:3a7713b1edbc | 211 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
AnnaBridge | 171:3a7713b1edbc | 212 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 213 | } TIM_Encoder_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 214 | |
AnnaBridge | 171:3a7713b1edbc | 215 | /** |
AnnaBridge | 171:3a7713b1edbc | 216 | * @brief Clock Configuration Handle Structure definition |
AnnaBridge | 171:3a7713b1edbc | 217 | */ |
AnnaBridge | 171:3a7713b1edbc | 218 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 219 | { |
AnnaBridge | 171:3a7713b1edbc | 220 | uint32_t ClockSource; /*!< TIM clock sources. |
AnnaBridge | 171:3a7713b1edbc | 221 | This parameter can be a value of @ref TIM_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 222 | uint32_t ClockPolarity; /*!< TIM clock polarity. |
AnnaBridge | 171:3a7713b1edbc | 223 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 224 | uint32_t ClockPrescaler; /*!< TIM clock prescaler. |
AnnaBridge | 171:3a7713b1edbc | 225 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 226 | uint32_t ClockFilter; /*!< TIM clock filter. |
AnnaBridge | 171:3a7713b1edbc | 227 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 228 | }TIM_ClockConfigTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 229 | |
AnnaBridge | 171:3a7713b1edbc | 230 | /** |
AnnaBridge | 171:3a7713b1edbc | 231 | * @brief Clear Input Configuration Handle Structure definition |
AnnaBridge | 171:3a7713b1edbc | 232 | */ |
AnnaBridge | 171:3a7713b1edbc | 233 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 234 | { |
AnnaBridge | 171:3a7713b1edbc | 235 | uint32_t ClearInputState; /*!< TIM clear Input state. |
AnnaBridge | 171:3a7713b1edbc | 236 | This parameter can be ENABLE or DISABLE */ |
AnnaBridge | 171:3a7713b1edbc | 237 | uint32_t ClearInputSource; /*!< TIM clear Input sources. |
AnnaBridge | 171:3a7713b1edbc | 238 | This parameter can be a value of @ref TIMEx_ClearInput_Source */ |
AnnaBridge | 171:3a7713b1edbc | 239 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity. |
AnnaBridge | 171:3a7713b1edbc | 240 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 241 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler. |
AnnaBridge | 171:3a7713b1edbc | 242 | This parameter can be a value of @ref TIM_ClearInput_Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 243 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter. |
AnnaBridge | 171:3a7713b1edbc | 244 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 245 | }TIM_ClearInputConfigTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 246 | |
AnnaBridge | 171:3a7713b1edbc | 247 | /** |
AnnaBridge | 171:3a7713b1edbc | 248 | * @brief TIM Slave configuration Structure definition |
AnnaBridge | 171:3a7713b1edbc | 249 | */ |
AnnaBridge | 171:3a7713b1edbc | 250 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 251 | uint32_t SlaveMode; /*!< Slave mode selection |
AnnaBridge | 171:3a7713b1edbc | 252 | This parameter can be a value of @ref TIMEx_Slave_Mode */ |
AnnaBridge | 171:3a7713b1edbc | 253 | uint32_t InputTrigger; /*!< Input Trigger source |
AnnaBridge | 171:3a7713b1edbc | 254 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 255 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
AnnaBridge | 171:3a7713b1edbc | 256 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 257 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
AnnaBridge | 171:3a7713b1edbc | 258 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 259 | uint32_t TriggerFilter; /*!< Input trigger filter |
AnnaBridge | 171:3a7713b1edbc | 260 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 261 | |
AnnaBridge | 171:3a7713b1edbc | 262 | }TIM_SlaveConfigTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 263 | |
AnnaBridge | 171:3a7713b1edbc | 264 | /** |
AnnaBridge | 171:3a7713b1edbc | 265 | * @brief HAL State structures definition |
AnnaBridge | 171:3a7713b1edbc | 266 | */ |
AnnaBridge | 171:3a7713b1edbc | 267 | typedef enum |
AnnaBridge | 171:3a7713b1edbc | 268 | { |
AnnaBridge | 171:3a7713b1edbc | 269 | HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ |
AnnaBridge | 171:3a7713b1edbc | 270 | HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
AnnaBridge | 171:3a7713b1edbc | 271 | HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ |
AnnaBridge | 171:3a7713b1edbc | 272 | HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
AnnaBridge | 171:3a7713b1edbc | 273 | HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ |
AnnaBridge | 171:3a7713b1edbc | 274 | }HAL_TIM_StateTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 275 | |
AnnaBridge | 171:3a7713b1edbc | 276 | /** |
AnnaBridge | 171:3a7713b1edbc | 277 | * @brief HAL Active channel structures definition |
AnnaBridge | 171:3a7713b1edbc | 278 | */ |
AnnaBridge | 171:3a7713b1edbc | 279 | typedef enum |
AnnaBridge | 171:3a7713b1edbc | 280 | { |
AnnaBridge | 171:3a7713b1edbc | 281 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ |
AnnaBridge | 171:3a7713b1edbc | 282 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ |
AnnaBridge | 171:3a7713b1edbc | 283 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ |
AnnaBridge | 171:3a7713b1edbc | 284 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ |
AnnaBridge | 171:3a7713b1edbc | 285 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ |
AnnaBridge | 171:3a7713b1edbc | 286 | }HAL_TIM_ActiveChannel; |
AnnaBridge | 171:3a7713b1edbc | 287 | |
AnnaBridge | 171:3a7713b1edbc | 288 | /** |
AnnaBridge | 171:3a7713b1edbc | 289 | * @brief TIM Time Base Handle Structure definition |
AnnaBridge | 171:3a7713b1edbc | 290 | */ |
AnnaBridge | 171:3a7713b1edbc | 291 | typedef struct __TIM_HandleTypeDef |
AnnaBridge | 171:3a7713b1edbc | 292 | { |
AnnaBridge | 171:3a7713b1edbc | 293 | TIM_TypeDef *Instance; /*!< Register base address */ |
AnnaBridge | 171:3a7713b1edbc | 294 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
AnnaBridge | 171:3a7713b1edbc | 295 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
AnnaBridge | 171:3a7713b1edbc | 296 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
AnnaBridge | 171:3a7713b1edbc | 297 | This array is accessed by a @ref DMA_Handle_index */ |
AnnaBridge | 171:3a7713b1edbc | 298 | HAL_LockTypeDef Lock; /*!< Locking object */ |
AnnaBridge | 171:3a7713b1edbc | 299 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
AnnaBridge | 171:3a7713b1edbc | 300 | |
AnnaBridge | 171:3a7713b1edbc | 301 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
AnnaBridge | 171:3a7713b1edbc | 302 | void (* Base_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ |
AnnaBridge | 171:3a7713b1edbc | 303 | void (* Base_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ |
AnnaBridge | 171:3a7713b1edbc | 304 | void (* IC_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ |
AnnaBridge | 171:3a7713b1edbc | 305 | void (* IC_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ |
AnnaBridge | 171:3a7713b1edbc | 306 | void (* OC_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ |
AnnaBridge | 171:3a7713b1edbc | 307 | void (* OC_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ |
AnnaBridge | 171:3a7713b1edbc | 308 | void (* PWM_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ |
AnnaBridge | 171:3a7713b1edbc | 309 | void (* PWM_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ |
AnnaBridge | 171:3a7713b1edbc | 310 | void (* OnePulse_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ |
AnnaBridge | 171:3a7713b1edbc | 311 | void (* OnePulse_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ |
AnnaBridge | 171:3a7713b1edbc | 312 | void (* Encoder_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ |
AnnaBridge | 171:3a7713b1edbc | 313 | void (* Encoder_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ |
AnnaBridge | 171:3a7713b1edbc | 314 | void (* HallSensor_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ |
AnnaBridge | 171:3a7713b1edbc | 315 | void (* HallSensor_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ |
AnnaBridge | 171:3a7713b1edbc | 316 | |
AnnaBridge | 171:3a7713b1edbc | 317 | void (* PeriodElapsedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ |
AnnaBridge | 171:3a7713b1edbc | 318 | void (* TriggerCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ |
AnnaBridge | 171:3a7713b1edbc | 319 | void (* IC_CaptureCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ |
AnnaBridge | 171:3a7713b1edbc | 320 | void (* OC_DelayElapsedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ |
AnnaBridge | 171:3a7713b1edbc | 321 | void (* PWM_PulseFinishedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ |
AnnaBridge | 171:3a7713b1edbc | 322 | void (* ErrorCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ |
AnnaBridge | 171:3a7713b1edbc | 323 | void (* CommutationCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ |
AnnaBridge | 171:3a7713b1edbc | 324 | void (* BreakCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ |
AnnaBridge | 171:3a7713b1edbc | 325 | |
AnnaBridge | 171:3a7713b1edbc | 326 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
AnnaBridge | 171:3a7713b1edbc | 327 | |
AnnaBridge | 171:3a7713b1edbc | 328 | }TIM_HandleTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 329 | |
AnnaBridge | 171:3a7713b1edbc | 330 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
AnnaBridge | 171:3a7713b1edbc | 331 | /** |
AnnaBridge | 171:3a7713b1edbc | 332 | * @brief HAL TIM Callback ID enumeration definition |
AnnaBridge | 171:3a7713b1edbc | 333 | */ |
AnnaBridge | 171:3a7713b1edbc | 334 | typedef enum |
AnnaBridge | 171:3a7713b1edbc | 335 | { |
AnnaBridge | 171:3a7713b1edbc | 336 | HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, /*!< TIM Base MspInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 337 | HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, /*!< TIM Base MspDeInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 338 | HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, /*!< TIM IC MspInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 339 | HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U, /*!< TIM IC MspDeInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 340 | HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, /*!< TIM OC MspInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 341 | HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, /*!< TIM OC MspDeInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 342 | HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, /*!< TIM PWM MspInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 343 | HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U, /*!< TIM PWM MspDeInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 344 | HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, /*!< TIM One Pulse MspInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 345 | HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, /*!< TIM One Pulse MspDeInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 346 | HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, /*!< TIM Encoder MspInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 347 | HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU, /*!< TIM Encoder MspDeInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 348 | HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, /*!< TIM Encoder MspDeInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 349 | HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, /*!< TIM Encoder MspDeInit Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 350 | |
AnnaBridge | 171:3a7713b1edbc | 351 | HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, /*!< TIM Period Elapsed Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 352 | HAL_TIM_TRIGGER_CB_ID = 0x0FU, /*!< TIM Trigger Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 353 | HAL_TIM_IC_CAPTURE_CB_ID = 0x10U, /*!< TIM Input Capture Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 354 | HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x11U, /*!< TIM Output Compare Delay Elapsed Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 355 | HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x12U, /*!< TIM PWM Pulse Finished Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 356 | HAL_TIM_ERROR_CB_ID = 0x13U, /*!< TIM Error Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 357 | HAL_TIM_COMMUTATION_CB_ID = 0x14U, /*!< TIM Commutation Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 358 | HAL_TIM_BREAK_CB_ID = 0x15U /*!< TIM Break Callback ID */ |
AnnaBridge | 171:3a7713b1edbc | 359 | |
AnnaBridge | 171:3a7713b1edbc | 360 | }HAL_TIM_CallbackIDTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 361 | |
AnnaBridge | 171:3a7713b1edbc | 362 | /** |
AnnaBridge | 171:3a7713b1edbc | 363 | * @brief HAL TIM Callback pointer definition |
AnnaBridge | 171:3a7713b1edbc | 364 | */ |
AnnaBridge | 171:3a7713b1edbc | 365 | typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to the TIM callback function */ |
AnnaBridge | 171:3a7713b1edbc | 366 | |
AnnaBridge | 171:3a7713b1edbc | 367 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
AnnaBridge | 171:3a7713b1edbc | 368 | /** |
AnnaBridge | 171:3a7713b1edbc | 369 | * @} |
AnnaBridge | 171:3a7713b1edbc | 370 | */ |
AnnaBridge | 171:3a7713b1edbc | 371 | |
AnnaBridge | 171:3a7713b1edbc | 372 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 373 | /** @defgroup TIM_Exported_Constants TIM Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 374 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 375 | */ |
AnnaBridge | 171:3a7713b1edbc | 376 | |
AnnaBridge | 171:3a7713b1edbc | 377 | /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity |
AnnaBridge | 171:3a7713b1edbc | 378 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 379 | */ |
AnnaBridge | 171:3a7713b1edbc | 380 | #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /*!< Polarity for TIx source */ |
AnnaBridge | 171:3a7713b1edbc | 381 | #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ |
AnnaBridge | 171:3a7713b1edbc | 382 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
AnnaBridge | 171:3a7713b1edbc | 383 | /** |
AnnaBridge | 171:3a7713b1edbc | 384 | * @} |
AnnaBridge | 171:3a7713b1edbc | 385 | */ |
AnnaBridge | 171:3a7713b1edbc | 386 | |
AnnaBridge | 171:3a7713b1edbc | 387 | /** @defgroup TIM_ETR_Polarity TIM ETR Polarity |
AnnaBridge | 171:3a7713b1edbc | 388 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 389 | */ |
AnnaBridge | 171:3a7713b1edbc | 390 | #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ |
AnnaBridge | 171:3a7713b1edbc | 391 | #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /*!< Polarity for ETR source */ |
AnnaBridge | 171:3a7713b1edbc | 392 | /** |
AnnaBridge | 171:3a7713b1edbc | 393 | * @} |
AnnaBridge | 171:3a7713b1edbc | 394 | */ |
AnnaBridge | 171:3a7713b1edbc | 395 | |
AnnaBridge | 171:3a7713b1edbc | 396 | /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler |
AnnaBridge | 171:3a7713b1edbc | 397 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 398 | */ |
AnnaBridge | 171:3a7713b1edbc | 399 | #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /*!< No prescaler is used */ |
AnnaBridge | 171:3a7713b1edbc | 400 | #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ |
AnnaBridge | 171:3a7713b1edbc | 401 | #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ |
AnnaBridge | 171:3a7713b1edbc | 402 | #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ |
AnnaBridge | 171:3a7713b1edbc | 403 | /** |
AnnaBridge | 171:3a7713b1edbc | 404 | * @} |
AnnaBridge | 171:3a7713b1edbc | 405 | */ |
AnnaBridge | 171:3a7713b1edbc | 406 | |
AnnaBridge | 171:3a7713b1edbc | 407 | /** @defgroup TIM_Counter_Mode TIM Counter Mode |
AnnaBridge | 171:3a7713b1edbc | 408 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 409 | */ |
AnnaBridge | 171:3a7713b1edbc | 410 | #define TIM_COUNTERMODE_UP ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 411 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR |
AnnaBridge | 171:3a7713b1edbc | 412 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 |
AnnaBridge | 171:3a7713b1edbc | 413 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 |
AnnaBridge | 171:3a7713b1edbc | 414 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS |
AnnaBridge | 171:3a7713b1edbc | 415 | /** |
AnnaBridge | 171:3a7713b1edbc | 416 | * @} |
AnnaBridge | 171:3a7713b1edbc | 417 | */ |
AnnaBridge | 171:3a7713b1edbc | 418 | |
AnnaBridge | 171:3a7713b1edbc | 419 | /** @defgroup TIM_ClockDivision TIM Clock Division |
AnnaBridge | 171:3a7713b1edbc | 420 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 421 | */ |
AnnaBridge | 171:3a7713b1edbc | 422 | #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 423 | #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) |
AnnaBridge | 171:3a7713b1edbc | 424 | #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) |
AnnaBridge | 171:3a7713b1edbc | 425 | /** |
AnnaBridge | 171:3a7713b1edbc | 426 | * @} |
AnnaBridge | 171:3a7713b1edbc | 427 | */ |
AnnaBridge | 171:3a7713b1edbc | 428 | |
AnnaBridge | 171:3a7713b1edbc | 429 | /** @defgroup TIM_Output_Compare_State TIM Output Compare State |
AnnaBridge | 171:3a7713b1edbc | 430 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 431 | */ |
AnnaBridge | 171:3a7713b1edbc | 432 | #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 433 | #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) |
AnnaBridge | 171:3a7713b1edbc | 434 | |
AnnaBridge | 171:3a7713b1edbc | 435 | /** |
AnnaBridge | 171:3a7713b1edbc | 436 | * @} |
AnnaBridge | 171:3a7713b1edbc | 437 | */ |
AnnaBridge | 171:3a7713b1edbc | 438 | |
AnnaBridge | 171:3a7713b1edbc | 439 | /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload |
AnnaBridge | 171:3a7713b1edbc | 440 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 441 | */ |
AnnaBridge | 171:3a7713b1edbc | 442 | #define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000) /*!< TIMx_ARR register is not buffered */ |
AnnaBridge | 171:3a7713b1edbc | 443 | #define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ |
AnnaBridge | 171:3a7713b1edbc | 444 | |
AnnaBridge | 171:3a7713b1edbc | 445 | /** |
AnnaBridge | 171:3a7713b1edbc | 446 | * @} |
AnnaBridge | 171:3a7713b1edbc | 447 | */ |
AnnaBridge | 171:3a7713b1edbc | 448 | |
AnnaBridge | 171:3a7713b1edbc | 449 | /** @defgroup TIM_Output_Fast_State TIM Output Fast State |
AnnaBridge | 171:3a7713b1edbc | 450 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 451 | */ |
AnnaBridge | 171:3a7713b1edbc | 452 | #define TIM_OCFAST_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 453 | #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) |
AnnaBridge | 171:3a7713b1edbc | 454 | /** |
AnnaBridge | 171:3a7713b1edbc | 455 | * @} |
AnnaBridge | 171:3a7713b1edbc | 456 | */ |
AnnaBridge | 171:3a7713b1edbc | 457 | |
AnnaBridge | 171:3a7713b1edbc | 458 | /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State |
AnnaBridge | 171:3a7713b1edbc | 459 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 460 | */ |
AnnaBridge | 171:3a7713b1edbc | 461 | #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 462 | #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) |
AnnaBridge | 171:3a7713b1edbc | 463 | /** |
AnnaBridge | 171:3a7713b1edbc | 464 | * @} |
AnnaBridge | 171:3a7713b1edbc | 465 | */ |
AnnaBridge | 171:3a7713b1edbc | 466 | |
AnnaBridge | 171:3a7713b1edbc | 467 | /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity |
AnnaBridge | 171:3a7713b1edbc | 468 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 469 | */ |
AnnaBridge | 171:3a7713b1edbc | 470 | #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 471 | #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) |
AnnaBridge | 171:3a7713b1edbc | 472 | /** |
AnnaBridge | 171:3a7713b1edbc | 473 | * @} |
AnnaBridge | 171:3a7713b1edbc | 474 | */ |
AnnaBridge | 171:3a7713b1edbc | 475 | |
AnnaBridge | 171:3a7713b1edbc | 476 | /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity |
AnnaBridge | 171:3a7713b1edbc | 477 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 478 | */ |
AnnaBridge | 171:3a7713b1edbc | 479 | #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 480 | #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) |
AnnaBridge | 171:3a7713b1edbc | 481 | /** |
AnnaBridge | 171:3a7713b1edbc | 482 | * @} |
AnnaBridge | 171:3a7713b1edbc | 483 | */ |
AnnaBridge | 171:3a7713b1edbc | 484 | |
AnnaBridge | 171:3a7713b1edbc | 485 | /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State |
AnnaBridge | 171:3a7713b1edbc | 486 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 487 | */ |
AnnaBridge | 171:3a7713b1edbc | 488 | #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) |
AnnaBridge | 171:3a7713b1edbc | 489 | #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 490 | /** |
AnnaBridge | 171:3a7713b1edbc | 491 | * @} |
AnnaBridge | 171:3a7713b1edbc | 492 | */ |
AnnaBridge | 171:3a7713b1edbc | 493 | |
AnnaBridge | 171:3a7713b1edbc | 494 | /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State |
AnnaBridge | 171:3a7713b1edbc | 495 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 496 | */ |
AnnaBridge | 171:3a7713b1edbc | 497 | #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) |
AnnaBridge | 171:3a7713b1edbc | 498 | #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 499 | /** |
AnnaBridge | 171:3a7713b1edbc | 500 | * @} |
AnnaBridge | 171:3a7713b1edbc | 501 | */ |
AnnaBridge | 171:3a7713b1edbc | 502 | |
AnnaBridge | 171:3a7713b1edbc | 503 | /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity |
AnnaBridge | 171:3a7713b1edbc | 504 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 505 | */ |
AnnaBridge | 171:3a7713b1edbc | 506 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING |
AnnaBridge | 171:3a7713b1edbc | 507 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING |
AnnaBridge | 171:3a7713b1edbc | 508 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE |
AnnaBridge | 171:3a7713b1edbc | 509 | /** |
AnnaBridge | 171:3a7713b1edbc | 510 | * @} |
AnnaBridge | 171:3a7713b1edbc | 511 | */ |
AnnaBridge | 171:3a7713b1edbc | 512 | |
AnnaBridge | 171:3a7713b1edbc | 513 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
AnnaBridge | 171:3a7713b1edbc | 514 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 515 | */ |
AnnaBridge | 171:3a7713b1edbc | 516 | #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
AnnaBridge | 171:3a7713b1edbc | 517 | connected to IC1, IC2, IC3 or IC4, respectively */ |
AnnaBridge | 171:3a7713b1edbc | 518 | #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
AnnaBridge | 171:3a7713b1edbc | 519 | connected to IC2, IC1, IC4 or IC3, respectively */ |
AnnaBridge | 171:3a7713b1edbc | 520 | #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
AnnaBridge | 171:3a7713b1edbc | 521 | |
AnnaBridge | 171:3a7713b1edbc | 522 | /** |
AnnaBridge | 171:3a7713b1edbc | 523 | * @} |
AnnaBridge | 171:3a7713b1edbc | 524 | */ |
AnnaBridge | 171:3a7713b1edbc | 525 | |
AnnaBridge | 171:3a7713b1edbc | 526 | /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler |
AnnaBridge | 171:3a7713b1edbc | 527 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 528 | */ |
AnnaBridge | 171:3a7713b1edbc | 529 | #define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ |
AnnaBridge | 171:3a7713b1edbc | 530 | #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ |
AnnaBridge | 171:3a7713b1edbc | 531 | #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ |
AnnaBridge | 171:3a7713b1edbc | 532 | #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ |
AnnaBridge | 171:3a7713b1edbc | 533 | /** |
AnnaBridge | 171:3a7713b1edbc | 534 | * @} |
AnnaBridge | 171:3a7713b1edbc | 535 | */ |
AnnaBridge | 171:3a7713b1edbc | 536 | |
AnnaBridge | 171:3a7713b1edbc | 537 | /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode |
AnnaBridge | 171:3a7713b1edbc | 538 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 539 | */ |
AnnaBridge | 171:3a7713b1edbc | 540 | #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) |
AnnaBridge | 171:3a7713b1edbc | 541 | #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 542 | /** |
AnnaBridge | 171:3a7713b1edbc | 543 | * @} |
AnnaBridge | 171:3a7713b1edbc | 544 | */ |
AnnaBridge | 171:3a7713b1edbc | 545 | |
AnnaBridge | 171:3a7713b1edbc | 546 | /** @defgroup TIM_Encoder_Mode TIM Encoder Mode |
AnnaBridge | 171:3a7713b1edbc | 547 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 548 | */ |
AnnaBridge | 171:3a7713b1edbc | 549 | #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) |
AnnaBridge | 171:3a7713b1edbc | 550 | #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) |
AnnaBridge | 171:3a7713b1edbc | 551 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
AnnaBridge | 171:3a7713b1edbc | 552 | |
AnnaBridge | 171:3a7713b1edbc | 553 | /** |
AnnaBridge | 171:3a7713b1edbc | 554 | * @} |
AnnaBridge | 171:3a7713b1edbc | 555 | */ |
AnnaBridge | 171:3a7713b1edbc | 556 | |
AnnaBridge | 171:3a7713b1edbc | 557 | /** @defgroup TIM_Interrupt_definition TIM Interrupt definition |
AnnaBridge | 171:3a7713b1edbc | 558 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 559 | */ |
AnnaBridge | 171:3a7713b1edbc | 560 | #define TIM_IT_UPDATE (TIM_DIER_UIE) |
AnnaBridge | 171:3a7713b1edbc | 561 | #define TIM_IT_CC1 (TIM_DIER_CC1IE) |
AnnaBridge | 171:3a7713b1edbc | 562 | #define TIM_IT_CC2 (TIM_DIER_CC2IE) |
AnnaBridge | 171:3a7713b1edbc | 563 | #define TIM_IT_CC3 (TIM_DIER_CC3IE) |
AnnaBridge | 171:3a7713b1edbc | 564 | #define TIM_IT_CC4 (TIM_DIER_CC4IE) |
AnnaBridge | 171:3a7713b1edbc | 565 | #define TIM_IT_COM (TIM_DIER_COMIE) |
AnnaBridge | 171:3a7713b1edbc | 566 | #define TIM_IT_TRIGGER (TIM_DIER_TIE) |
AnnaBridge | 171:3a7713b1edbc | 567 | #define TIM_IT_BREAK (TIM_DIER_BIE) |
AnnaBridge | 171:3a7713b1edbc | 568 | /** |
AnnaBridge | 171:3a7713b1edbc | 569 | * @} |
AnnaBridge | 171:3a7713b1edbc | 570 | */ |
AnnaBridge | 171:3a7713b1edbc | 571 | |
AnnaBridge | 171:3a7713b1edbc | 572 | /** @defgroup TIM_Commutation_Source TIM Commutation Source |
AnnaBridge | 171:3a7713b1edbc | 573 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 574 | */ |
AnnaBridge | 171:3a7713b1edbc | 575 | #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) |
AnnaBridge | 171:3a7713b1edbc | 576 | #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 577 | /** |
AnnaBridge | 171:3a7713b1edbc | 578 | * @} |
AnnaBridge | 171:3a7713b1edbc | 579 | */ |
AnnaBridge | 171:3a7713b1edbc | 580 | |
AnnaBridge | 171:3a7713b1edbc | 581 | /** @defgroup TIM_DMA_sources TIM DMA sources |
AnnaBridge | 171:3a7713b1edbc | 582 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 583 | */ |
AnnaBridge | 171:3a7713b1edbc | 584 | #define TIM_DMA_UPDATE (TIM_DIER_UDE) |
AnnaBridge | 171:3a7713b1edbc | 585 | #define TIM_DMA_CC1 (TIM_DIER_CC1DE) |
AnnaBridge | 171:3a7713b1edbc | 586 | #define TIM_DMA_CC2 (TIM_DIER_CC2DE) |
AnnaBridge | 171:3a7713b1edbc | 587 | #define TIM_DMA_CC3 (TIM_DIER_CC3DE) |
AnnaBridge | 171:3a7713b1edbc | 588 | #define TIM_DMA_CC4 (TIM_DIER_CC4DE) |
AnnaBridge | 171:3a7713b1edbc | 589 | #define TIM_DMA_COM (TIM_DIER_COMDE) |
AnnaBridge | 171:3a7713b1edbc | 590 | #define TIM_DMA_TRIGGER (TIM_DIER_TDE) |
AnnaBridge | 171:3a7713b1edbc | 591 | /** |
AnnaBridge | 171:3a7713b1edbc | 592 | * @} |
AnnaBridge | 171:3a7713b1edbc | 593 | */ |
AnnaBridge | 171:3a7713b1edbc | 594 | |
AnnaBridge | 171:3a7713b1edbc | 595 | /** @defgroup TIM_Event_Source TIM Event Source |
AnnaBridge | 171:3a7713b1edbc | 596 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 597 | */ |
AnnaBridge | 171:3a7713b1edbc | 598 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG |
AnnaBridge | 171:3a7713b1edbc | 599 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G |
AnnaBridge | 171:3a7713b1edbc | 600 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G |
AnnaBridge | 171:3a7713b1edbc | 601 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G |
AnnaBridge | 171:3a7713b1edbc | 602 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G |
AnnaBridge | 171:3a7713b1edbc | 603 | #define TIM_EVENTSOURCE_COM TIM_EGR_COMG |
AnnaBridge | 171:3a7713b1edbc | 604 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG |
AnnaBridge | 171:3a7713b1edbc | 605 | #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG |
AnnaBridge | 171:3a7713b1edbc | 606 | #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G |
AnnaBridge | 171:3a7713b1edbc | 607 | /** |
AnnaBridge | 171:3a7713b1edbc | 608 | * @} |
AnnaBridge | 171:3a7713b1edbc | 609 | */ |
AnnaBridge | 171:3a7713b1edbc | 610 | |
AnnaBridge | 171:3a7713b1edbc | 611 | /** @defgroup TIM_Flag_definition TIM Flag definition |
AnnaBridge | 171:3a7713b1edbc | 612 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 613 | */ |
AnnaBridge | 171:3a7713b1edbc | 614 | #define TIM_FLAG_UPDATE (TIM_SR_UIF) |
AnnaBridge | 171:3a7713b1edbc | 615 | #define TIM_FLAG_CC1 (TIM_SR_CC1IF) |
AnnaBridge | 171:3a7713b1edbc | 616 | #define TIM_FLAG_CC2 (TIM_SR_CC2IF) |
AnnaBridge | 171:3a7713b1edbc | 617 | #define TIM_FLAG_CC3 (TIM_SR_CC3IF) |
AnnaBridge | 171:3a7713b1edbc | 618 | #define TIM_FLAG_CC4 (TIM_SR_CC4IF) |
AnnaBridge | 171:3a7713b1edbc | 619 | #define TIM_FLAG_COM (TIM_SR_COMIF) |
AnnaBridge | 171:3a7713b1edbc | 620 | #define TIM_FLAG_TRIGGER (TIM_SR_TIF) |
AnnaBridge | 171:3a7713b1edbc | 621 | #define TIM_FLAG_BREAK (TIM_SR_BIF) |
AnnaBridge | 171:3a7713b1edbc | 622 | #define TIM_FLAG_BREAK2 (TIM_SR_B2IF) |
AnnaBridge | 171:3a7713b1edbc | 623 | #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) |
AnnaBridge | 171:3a7713b1edbc | 624 | #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) |
AnnaBridge | 171:3a7713b1edbc | 625 | #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) |
AnnaBridge | 171:3a7713b1edbc | 626 | #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) |
AnnaBridge | 171:3a7713b1edbc | 627 | /** |
AnnaBridge | 171:3a7713b1edbc | 628 | * @} |
AnnaBridge | 171:3a7713b1edbc | 629 | */ |
AnnaBridge | 171:3a7713b1edbc | 630 | |
AnnaBridge | 171:3a7713b1edbc | 631 | /** @defgroup TIM_Clock_Source TIM Clock Source |
AnnaBridge | 171:3a7713b1edbc | 632 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 633 | */ |
AnnaBridge | 171:3a7713b1edbc | 634 | #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) |
AnnaBridge | 171:3a7713b1edbc | 635 | #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) |
AnnaBridge | 171:3a7713b1edbc | 636 | #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 637 | #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) |
AnnaBridge | 171:3a7713b1edbc | 638 | #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) |
AnnaBridge | 171:3a7713b1edbc | 639 | #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) |
AnnaBridge | 171:3a7713b1edbc | 640 | #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) |
AnnaBridge | 171:3a7713b1edbc | 641 | #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) |
AnnaBridge | 171:3a7713b1edbc | 642 | #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) |
AnnaBridge | 171:3a7713b1edbc | 643 | #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) |
AnnaBridge | 171:3a7713b1edbc | 644 | /** |
AnnaBridge | 171:3a7713b1edbc | 645 | * @} |
AnnaBridge | 171:3a7713b1edbc | 646 | */ |
AnnaBridge | 171:3a7713b1edbc | 647 | |
AnnaBridge | 171:3a7713b1edbc | 648 | /** @defgroup TIM_Clock_Polarity TIM Clock Polarity |
AnnaBridge | 171:3a7713b1edbc | 649 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 650 | */ |
AnnaBridge | 171:3a7713b1edbc | 651 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
AnnaBridge | 171:3a7713b1edbc | 652 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
AnnaBridge | 171:3a7713b1edbc | 653 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
AnnaBridge | 171:3a7713b1edbc | 654 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
AnnaBridge | 171:3a7713b1edbc | 655 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
AnnaBridge | 171:3a7713b1edbc | 656 | /** |
AnnaBridge | 171:3a7713b1edbc | 657 | * @} |
AnnaBridge | 171:3a7713b1edbc | 658 | */ |
AnnaBridge | 171:3a7713b1edbc | 659 | |
AnnaBridge | 171:3a7713b1edbc | 660 | /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler |
AnnaBridge | 171:3a7713b1edbc | 661 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 662 | */ |
AnnaBridge | 171:3a7713b1edbc | 663 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 171:3a7713b1edbc | 664 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
AnnaBridge | 171:3a7713b1edbc | 665 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
AnnaBridge | 171:3a7713b1edbc | 666 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
AnnaBridge | 171:3a7713b1edbc | 667 | /** |
AnnaBridge | 171:3a7713b1edbc | 668 | * @} |
AnnaBridge | 171:3a7713b1edbc | 669 | */ |
AnnaBridge | 171:3a7713b1edbc | 670 | |
AnnaBridge | 171:3a7713b1edbc | 671 | /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity |
AnnaBridge | 171:3a7713b1edbc | 672 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 673 | */ |
AnnaBridge | 171:3a7713b1edbc | 674 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
AnnaBridge | 171:3a7713b1edbc | 675 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
AnnaBridge | 171:3a7713b1edbc | 676 | /** |
AnnaBridge | 171:3a7713b1edbc | 677 | * @} |
AnnaBridge | 171:3a7713b1edbc | 678 | */ |
AnnaBridge | 171:3a7713b1edbc | 679 | |
AnnaBridge | 171:3a7713b1edbc | 680 | /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler |
AnnaBridge | 171:3a7713b1edbc | 681 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 682 | */ |
AnnaBridge | 171:3a7713b1edbc | 683 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 171:3a7713b1edbc | 684 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
AnnaBridge | 171:3a7713b1edbc | 685 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
AnnaBridge | 171:3a7713b1edbc | 686 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
AnnaBridge | 171:3a7713b1edbc | 687 | /** |
AnnaBridge | 171:3a7713b1edbc | 688 | * @} |
AnnaBridge | 171:3a7713b1edbc | 689 | */ |
AnnaBridge | 171:3a7713b1edbc | 690 | |
AnnaBridge | 171:3a7713b1edbc | 691 | /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state |
AnnaBridge | 171:3a7713b1edbc | 692 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 693 | */ |
AnnaBridge | 171:3a7713b1edbc | 694 | #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) |
AnnaBridge | 171:3a7713b1edbc | 695 | #define TIM_OSSR_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 696 | /** |
AnnaBridge | 171:3a7713b1edbc | 697 | * @} |
AnnaBridge | 171:3a7713b1edbc | 698 | */ |
AnnaBridge | 171:3a7713b1edbc | 699 | |
AnnaBridge | 171:3a7713b1edbc | 700 | /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state |
AnnaBridge | 171:3a7713b1edbc | 701 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 702 | */ |
AnnaBridge | 171:3a7713b1edbc | 703 | #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) |
AnnaBridge | 171:3a7713b1edbc | 704 | #define TIM_OSSI_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 705 | /** |
AnnaBridge | 171:3a7713b1edbc | 706 | * @} |
AnnaBridge | 171:3a7713b1edbc | 707 | */ |
AnnaBridge | 171:3a7713b1edbc | 708 | |
AnnaBridge | 171:3a7713b1edbc | 709 | /** @defgroup TIM_Lock_level TIM Lock level |
AnnaBridge | 171:3a7713b1edbc | 710 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 711 | */ |
AnnaBridge | 171:3a7713b1edbc | 712 | #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 713 | #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) |
AnnaBridge | 171:3a7713b1edbc | 714 | #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) |
AnnaBridge | 171:3a7713b1edbc | 715 | #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) |
AnnaBridge | 171:3a7713b1edbc | 716 | /** |
AnnaBridge | 171:3a7713b1edbc | 717 | * @} |
AnnaBridge | 171:3a7713b1edbc | 718 | */ |
AnnaBridge | 171:3a7713b1edbc | 719 | /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State |
AnnaBridge | 171:3a7713b1edbc | 720 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 721 | */ |
AnnaBridge | 171:3a7713b1edbc | 722 | #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) |
AnnaBridge | 171:3a7713b1edbc | 723 | #define TIM_BREAK_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 724 | /** |
AnnaBridge | 171:3a7713b1edbc | 725 | * @} |
AnnaBridge | 171:3a7713b1edbc | 726 | */ |
AnnaBridge | 171:3a7713b1edbc | 727 | |
AnnaBridge | 171:3a7713b1edbc | 728 | /** @defgroup TIM_Break_Polarity TIM Break Polarity |
AnnaBridge | 171:3a7713b1edbc | 729 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 730 | */ |
AnnaBridge | 171:3a7713b1edbc | 731 | #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 732 | #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) |
AnnaBridge | 171:3a7713b1edbc | 733 | /** |
AnnaBridge | 171:3a7713b1edbc | 734 | * @} |
AnnaBridge | 171:3a7713b1edbc | 735 | */ |
AnnaBridge | 171:3a7713b1edbc | 736 | |
AnnaBridge | 171:3a7713b1edbc | 737 | /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State |
AnnaBridge | 171:3a7713b1edbc | 738 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 739 | */ |
AnnaBridge | 171:3a7713b1edbc | 740 | #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) |
AnnaBridge | 171:3a7713b1edbc | 741 | #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 742 | /** |
AnnaBridge | 171:3a7713b1edbc | 743 | * @} |
AnnaBridge | 171:3a7713b1edbc | 744 | */ |
AnnaBridge | 171:3a7713b1edbc | 745 | |
AnnaBridge | 171:3a7713b1edbc | 746 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
AnnaBridge | 171:3a7713b1edbc | 747 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 748 | */ |
AnnaBridge | 171:3a7713b1edbc | 749 | #define TIM_TRGO_RESET ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 750 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
AnnaBridge | 171:3a7713b1edbc | 751 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
AnnaBridge | 171:3a7713b1edbc | 752 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
AnnaBridge | 171:3a7713b1edbc | 753 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
AnnaBridge | 171:3a7713b1edbc | 754 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
AnnaBridge | 171:3a7713b1edbc | 755 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
AnnaBridge | 171:3a7713b1edbc | 756 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
AnnaBridge | 171:3a7713b1edbc | 757 | /** |
AnnaBridge | 171:3a7713b1edbc | 758 | * @} |
AnnaBridge | 171:3a7713b1edbc | 759 | */ |
AnnaBridge | 171:3a7713b1edbc | 760 | |
AnnaBridge | 171:3a7713b1edbc | 761 | /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode |
AnnaBridge | 171:3a7713b1edbc | 762 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 763 | */ |
AnnaBridge | 171:3a7713b1edbc | 764 | #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) |
AnnaBridge | 171:3a7713b1edbc | 765 | #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 766 | /** |
AnnaBridge | 171:3a7713b1edbc | 767 | * @} |
AnnaBridge | 171:3a7713b1edbc | 768 | */ |
AnnaBridge | 171:3a7713b1edbc | 769 | |
AnnaBridge | 171:3a7713b1edbc | 770 | /** @defgroup TIM_Trigger_Selection TIM Trigger Selection |
AnnaBridge | 171:3a7713b1edbc | 771 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 772 | */ |
AnnaBridge | 171:3a7713b1edbc | 773 | #define TIM_TS_ITR0 ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 774 | #define TIM_TS_ITR1 ((uint32_t)0x0010U) |
AnnaBridge | 171:3a7713b1edbc | 775 | #define TIM_TS_ITR2 ((uint32_t)0x0020U) |
AnnaBridge | 171:3a7713b1edbc | 776 | #define TIM_TS_ITR3 ((uint32_t)0x0030U) |
AnnaBridge | 171:3a7713b1edbc | 777 | #define TIM_TS_TI1F_ED ((uint32_t)0x0040U) |
AnnaBridge | 171:3a7713b1edbc | 778 | #define TIM_TS_TI1FP1 ((uint32_t)0x0050U) |
AnnaBridge | 171:3a7713b1edbc | 779 | #define TIM_TS_TI2FP2 ((uint32_t)0x0060U) |
AnnaBridge | 171:3a7713b1edbc | 780 | #define TIM_TS_ETRF ((uint32_t)0x0070U) |
AnnaBridge | 171:3a7713b1edbc | 781 | #define TIM_TS_NONE ((uint32_t)0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 782 | /** |
AnnaBridge | 171:3a7713b1edbc | 783 | * @} |
AnnaBridge | 171:3a7713b1edbc | 784 | */ |
AnnaBridge | 171:3a7713b1edbc | 785 | |
AnnaBridge | 171:3a7713b1edbc | 786 | /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity |
AnnaBridge | 171:3a7713b1edbc | 787 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 788 | */ |
AnnaBridge | 171:3a7713b1edbc | 789 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
AnnaBridge | 171:3a7713b1edbc | 790 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
AnnaBridge | 171:3a7713b1edbc | 791 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 171:3a7713b1edbc | 792 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 171:3a7713b1edbc | 793 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 171:3a7713b1edbc | 794 | /** |
AnnaBridge | 171:3a7713b1edbc | 795 | * @} |
AnnaBridge | 171:3a7713b1edbc | 796 | */ |
AnnaBridge | 171:3a7713b1edbc | 797 | |
AnnaBridge | 171:3a7713b1edbc | 798 | /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler |
AnnaBridge | 171:3a7713b1edbc | 799 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 800 | */ |
AnnaBridge | 171:3a7713b1edbc | 801 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 171:3a7713b1edbc | 802 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
AnnaBridge | 171:3a7713b1edbc | 803 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
AnnaBridge | 171:3a7713b1edbc | 804 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
AnnaBridge | 171:3a7713b1edbc | 805 | /** |
AnnaBridge | 171:3a7713b1edbc | 806 | * @} |
AnnaBridge | 171:3a7713b1edbc | 807 | */ |
AnnaBridge | 171:3a7713b1edbc | 808 | |
AnnaBridge | 171:3a7713b1edbc | 809 | |
AnnaBridge | 171:3a7713b1edbc | 810 | /** @defgroup TIM_TI1_Selection TIM TI1 Selection |
AnnaBridge | 171:3a7713b1edbc | 811 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 812 | */ |
AnnaBridge | 171:3a7713b1edbc | 813 | #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 814 | #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) |
AnnaBridge | 171:3a7713b1edbc | 815 | /** |
AnnaBridge | 171:3a7713b1edbc | 816 | * @} |
AnnaBridge | 171:3a7713b1edbc | 817 | */ |
AnnaBridge | 171:3a7713b1edbc | 818 | |
AnnaBridge | 171:3a7713b1edbc | 819 | /** @defgroup TIM_DMA_Base_address TIM DMA Base address |
AnnaBridge | 171:3a7713b1edbc | 820 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 821 | */ |
AnnaBridge | 171:3a7713b1edbc | 822 | #define TIM_DMABASE_CR1 (0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 823 | #define TIM_DMABASE_CR2 (0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 824 | #define TIM_DMABASE_SMCR (0x00000002U) |
AnnaBridge | 171:3a7713b1edbc | 825 | #define TIM_DMABASE_DIER (0x00000003U) |
AnnaBridge | 171:3a7713b1edbc | 826 | #define TIM_DMABASE_SR (0x00000004U) |
AnnaBridge | 171:3a7713b1edbc | 827 | #define TIM_DMABASE_EGR (0x00000005U) |
AnnaBridge | 171:3a7713b1edbc | 828 | #define TIM_DMABASE_CCMR1 (0x00000006U) |
AnnaBridge | 171:3a7713b1edbc | 829 | #define TIM_DMABASE_CCMR2 (0x00000007U) |
AnnaBridge | 171:3a7713b1edbc | 830 | #define TIM_DMABASE_CCER (0x00000008U) |
AnnaBridge | 171:3a7713b1edbc | 831 | #define TIM_DMABASE_CNT (0x00000009U) |
AnnaBridge | 171:3a7713b1edbc | 832 | #define TIM_DMABASE_PSC (0x0000000AU) |
AnnaBridge | 171:3a7713b1edbc | 833 | #define TIM_DMABASE_ARR (0x0000000BU) |
AnnaBridge | 171:3a7713b1edbc | 834 | #define TIM_DMABASE_RCR (0x0000000CU) |
AnnaBridge | 171:3a7713b1edbc | 835 | #define TIM_DMABASE_CCR1 (0x0000000DU) |
AnnaBridge | 171:3a7713b1edbc | 836 | #define TIM_DMABASE_CCR2 (0x0000000EU) |
AnnaBridge | 171:3a7713b1edbc | 837 | #define TIM_DMABASE_CCR3 (0x0000000FU) |
AnnaBridge | 171:3a7713b1edbc | 838 | #define TIM_DMABASE_CCR4 (0x00000010U) |
AnnaBridge | 171:3a7713b1edbc | 839 | #define TIM_DMABASE_BDTR (0x00000011U) |
AnnaBridge | 171:3a7713b1edbc | 840 | #define TIM_DMABASE_DCR (0x00000012U) |
AnnaBridge | 171:3a7713b1edbc | 841 | #define TIM_DMABASE_OR (0x00000013U) |
AnnaBridge | 171:3a7713b1edbc | 842 | /** |
AnnaBridge | 171:3a7713b1edbc | 843 | * @} |
AnnaBridge | 171:3a7713b1edbc | 844 | */ |
AnnaBridge | 171:3a7713b1edbc | 845 | |
AnnaBridge | 171:3a7713b1edbc | 846 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
AnnaBridge | 171:3a7713b1edbc | 847 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 848 | */ |
AnnaBridge | 171:3a7713b1edbc | 849 | #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 850 | #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U) |
AnnaBridge | 171:3a7713b1edbc | 851 | #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U) |
AnnaBridge | 171:3a7713b1edbc | 852 | #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U) |
AnnaBridge | 171:3a7713b1edbc | 853 | #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U) |
AnnaBridge | 171:3a7713b1edbc | 854 | #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U) |
AnnaBridge | 171:3a7713b1edbc | 855 | #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U) |
AnnaBridge | 171:3a7713b1edbc | 856 | #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U) |
AnnaBridge | 171:3a7713b1edbc | 857 | #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U) |
AnnaBridge | 171:3a7713b1edbc | 858 | #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U) |
AnnaBridge | 171:3a7713b1edbc | 859 | #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U) |
AnnaBridge | 171:3a7713b1edbc | 860 | #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U) |
AnnaBridge | 171:3a7713b1edbc | 861 | #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U) |
AnnaBridge | 171:3a7713b1edbc | 862 | #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U) |
AnnaBridge | 171:3a7713b1edbc | 863 | #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U) |
AnnaBridge | 171:3a7713b1edbc | 864 | #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U) |
AnnaBridge | 171:3a7713b1edbc | 865 | #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U) |
AnnaBridge | 171:3a7713b1edbc | 866 | #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U) |
AnnaBridge | 171:3a7713b1edbc | 867 | /** |
AnnaBridge | 171:3a7713b1edbc | 868 | * @} |
AnnaBridge | 171:3a7713b1edbc | 869 | */ |
AnnaBridge | 171:3a7713b1edbc | 870 | |
AnnaBridge | 171:3a7713b1edbc | 871 | /** @defgroup DMA_Handle_index DMA Handle index |
AnnaBridge | 171:3a7713b1edbc | 872 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 873 | */ |
AnnaBridge | 171:3a7713b1edbc | 874 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 875 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 876 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 877 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 878 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 879 | #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 880 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 881 | /** |
AnnaBridge | 171:3a7713b1edbc | 882 | * @} |
AnnaBridge | 171:3a7713b1edbc | 883 | */ |
AnnaBridge | 171:3a7713b1edbc | 884 | |
AnnaBridge | 171:3a7713b1edbc | 885 | /** @defgroup Channel_CC_State Channel CC State |
AnnaBridge | 171:3a7713b1edbc | 886 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 887 | */ |
AnnaBridge | 171:3a7713b1edbc | 888 | #define TIM_CCx_ENABLE ((uint32_t)0x0001U) |
AnnaBridge | 171:3a7713b1edbc | 889 | #define TIM_CCx_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 890 | #define TIM_CCxN_ENABLE ((uint32_t)0x0004U) |
AnnaBridge | 171:3a7713b1edbc | 891 | #define TIM_CCxN_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 892 | /** |
AnnaBridge | 171:3a7713b1edbc | 893 | * @} |
AnnaBridge | 171:3a7713b1edbc | 894 | */ |
AnnaBridge | 171:3a7713b1edbc | 895 | |
AnnaBridge | 171:3a7713b1edbc | 896 | /** |
AnnaBridge | 171:3a7713b1edbc | 897 | * @} |
AnnaBridge | 171:3a7713b1edbc | 898 | */ |
AnnaBridge | 171:3a7713b1edbc | 899 | |
AnnaBridge | 171:3a7713b1edbc | 900 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 901 | /** @defgroup TIM_Exported_Macros TIM Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 902 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 903 | */ |
AnnaBridge | 171:3a7713b1edbc | 904 | /** @brief Reset TIM handle state |
AnnaBridge | 171:3a7713b1edbc | 905 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 906 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 907 | */ |
AnnaBridge | 171:3a7713b1edbc | 908 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) |
AnnaBridge | 171:3a7713b1edbc | 909 | |
AnnaBridge | 171:3a7713b1edbc | 910 | /** |
AnnaBridge | 171:3a7713b1edbc | 911 | * @brief Enable the TIM peripheral. |
AnnaBridge | 171:3a7713b1edbc | 912 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 913 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 914 | */ |
AnnaBridge | 171:3a7713b1edbc | 915 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
AnnaBridge | 171:3a7713b1edbc | 916 | |
AnnaBridge | 171:3a7713b1edbc | 917 | /** |
AnnaBridge | 171:3a7713b1edbc | 918 | * @brief Enable the TIM update source request. |
AnnaBridge | 171:3a7713b1edbc | 919 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 920 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 921 | */ |
AnnaBridge | 171:3a7713b1edbc | 922 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS)) |
AnnaBridge | 171:3a7713b1edbc | 923 | |
AnnaBridge | 171:3a7713b1edbc | 924 | /** |
AnnaBridge | 171:3a7713b1edbc | 925 | * @brief Enable the TIM main Output. |
AnnaBridge | 171:3a7713b1edbc | 926 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 927 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 928 | */ |
AnnaBridge | 171:3a7713b1edbc | 929 | #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) |
AnnaBridge | 171:3a7713b1edbc | 930 | |
AnnaBridge | 171:3a7713b1edbc | 931 | /** |
AnnaBridge | 171:3a7713b1edbc | 932 | * @brief Disable the TIM peripheral. |
AnnaBridge | 171:3a7713b1edbc | 933 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 934 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 935 | */ |
AnnaBridge | 171:3a7713b1edbc | 936 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 937 | do { \ |
AnnaBridge | 171:3a7713b1edbc | 938 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ |
AnnaBridge | 171:3a7713b1edbc | 939 | { \ |
AnnaBridge | 171:3a7713b1edbc | 940 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ |
AnnaBridge | 171:3a7713b1edbc | 941 | { \ |
AnnaBridge | 171:3a7713b1edbc | 942 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
AnnaBridge | 171:3a7713b1edbc | 943 | } \ |
AnnaBridge | 171:3a7713b1edbc | 944 | } \ |
AnnaBridge | 171:3a7713b1edbc | 945 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 946 | |
AnnaBridge | 171:3a7713b1edbc | 947 | /** |
AnnaBridge | 171:3a7713b1edbc | 948 | * @brief Disable the TIM update source request. |
AnnaBridge | 171:3a7713b1edbc | 949 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 950 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 951 | */ |
AnnaBridge | 171:3a7713b1edbc | 952 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) |
AnnaBridge | 171:3a7713b1edbc | 953 | |
AnnaBridge | 171:3a7713b1edbc | 954 | /** |
AnnaBridge | 171:3a7713b1edbc | 955 | * @brief Disable the TIM main Output. |
AnnaBridge | 171:3a7713b1edbc | 956 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 957 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 958 | * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled |
AnnaBridge | 171:3a7713b1edbc | 959 | */ |
AnnaBridge | 171:3a7713b1edbc | 960 | #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 961 | do { \ |
AnnaBridge | 171:3a7713b1edbc | 962 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ |
AnnaBridge | 171:3a7713b1edbc | 963 | { \ |
AnnaBridge | 171:3a7713b1edbc | 964 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ |
AnnaBridge | 171:3a7713b1edbc | 965 | { \ |
AnnaBridge | 171:3a7713b1edbc | 966 | (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ |
AnnaBridge | 171:3a7713b1edbc | 967 | } \ |
AnnaBridge | 171:3a7713b1edbc | 968 | } \ |
AnnaBridge | 171:3a7713b1edbc | 969 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 970 | |
AnnaBridge | 171:3a7713b1edbc | 971 | /** @brief Enable the specified TIM interrupt. |
AnnaBridge | 171:3a7713b1edbc | 972 | * @param __HANDLE__: specifies the TIM Handle. |
AnnaBridge | 171:3a7713b1edbc | 973 | * @param __INTERRUPT__: specifies the TIM interrupt source to enable. |
AnnaBridge | 171:3a7713b1edbc | 974 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 975 | * @arg TIM_IT_UPDATE: Update interrupt |
AnnaBridge | 171:3a7713b1edbc | 976 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
AnnaBridge | 171:3a7713b1edbc | 977 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
AnnaBridge | 171:3a7713b1edbc | 978 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
AnnaBridge | 171:3a7713b1edbc | 979 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
AnnaBridge | 171:3a7713b1edbc | 980 | * @arg TIM_IT_COM: Commutation interrupt |
AnnaBridge | 171:3a7713b1edbc | 981 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
AnnaBridge | 171:3a7713b1edbc | 982 | * @arg TIM_IT_BREAK: Break interrupt |
AnnaBridge | 171:3a7713b1edbc | 983 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 984 | */ |
AnnaBridge | 171:3a7713b1edbc | 985 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
AnnaBridge | 171:3a7713b1edbc | 986 | |
AnnaBridge | 171:3a7713b1edbc | 987 | /** @brief Disable the specified TIM interrupt. |
AnnaBridge | 171:3a7713b1edbc | 988 | * @param __HANDLE__: specifies the TIM Handle. |
AnnaBridge | 171:3a7713b1edbc | 989 | * @param __INTERRUPT__: specifies the TIM interrupt source to disable. |
AnnaBridge | 171:3a7713b1edbc | 990 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 991 | * @arg TIM_IT_UPDATE: Update interrupt |
AnnaBridge | 171:3a7713b1edbc | 992 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
AnnaBridge | 171:3a7713b1edbc | 993 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
AnnaBridge | 171:3a7713b1edbc | 994 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
AnnaBridge | 171:3a7713b1edbc | 995 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
AnnaBridge | 171:3a7713b1edbc | 996 | * @arg TIM_IT_COM: Commutation interrupt |
AnnaBridge | 171:3a7713b1edbc | 997 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
AnnaBridge | 171:3a7713b1edbc | 998 | * @arg TIM_IT_BREAK: Break interrupt |
AnnaBridge | 171:3a7713b1edbc | 999 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1000 | */ |
AnnaBridge | 171:3a7713b1edbc | 1001 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
AnnaBridge | 171:3a7713b1edbc | 1002 | |
AnnaBridge | 171:3a7713b1edbc | 1003 | /** @brief Enable the specified DMA request. |
AnnaBridge | 171:3a7713b1edbc | 1004 | * @param __HANDLE__: specifies the TIM Handle. |
AnnaBridge | 171:3a7713b1edbc | 1005 | * @param __DMA__: specifies the TIM DMA request to enable. |
AnnaBridge | 171:3a7713b1edbc | 1006 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1007 | * @arg TIM_DMA_UPDATE: Update DMA request |
AnnaBridge | 171:3a7713b1edbc | 1008 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1009 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1010 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1011 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1012 | * @arg TIM_DMA_COM: Commutation DMA request |
AnnaBridge | 171:3a7713b1edbc | 1013 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
AnnaBridge | 171:3a7713b1edbc | 1014 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1015 | */ |
AnnaBridge | 171:3a7713b1edbc | 1016 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
AnnaBridge | 171:3a7713b1edbc | 1017 | |
AnnaBridge | 171:3a7713b1edbc | 1018 | /** @brief Disable the specified DMA request. |
AnnaBridge | 171:3a7713b1edbc | 1019 | * @param __HANDLE__: specifies the TIM Handle. |
AnnaBridge | 171:3a7713b1edbc | 1020 | * @param __DMA__: specifies the TIM DMA request to disable. |
AnnaBridge | 171:3a7713b1edbc | 1021 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1022 | * @arg TIM_DMA_UPDATE: Update DMA request |
AnnaBridge | 171:3a7713b1edbc | 1023 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1024 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1025 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1026 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1027 | * @arg TIM_DMA_COM: Commutation DMA request |
AnnaBridge | 171:3a7713b1edbc | 1028 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
AnnaBridge | 171:3a7713b1edbc | 1029 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1030 | */ |
AnnaBridge | 171:3a7713b1edbc | 1031 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
AnnaBridge | 171:3a7713b1edbc | 1032 | |
AnnaBridge | 171:3a7713b1edbc | 1033 | /** @brief Check whether the specified TIM interrupt flag is set or not. |
AnnaBridge | 171:3a7713b1edbc | 1034 | * @param __HANDLE__: specifies the TIM Handle. |
AnnaBridge | 171:3a7713b1edbc | 1035 | * @param __FLAG__: specifies the TIM interrupt flag to check. |
AnnaBridge | 171:3a7713b1edbc | 1036 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1037 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1038 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1039 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1040 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1041 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1042 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1043 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1044 | * @arg TIM_FLAG_BREAK: Break interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1045 | * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1046 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1047 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1048 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1049 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1050 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
AnnaBridge | 171:3a7713b1edbc | 1051 | */ |
AnnaBridge | 171:3a7713b1edbc | 1052 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
AnnaBridge | 171:3a7713b1edbc | 1053 | |
AnnaBridge | 171:3a7713b1edbc | 1054 | /** @brief Clear the specified TIM interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1055 | * @param __HANDLE__: specifies the TIM Handle. |
AnnaBridge | 171:3a7713b1edbc | 1056 | * @param __FLAG__: specifies the TIM interrupt flag to clear. |
AnnaBridge | 171:3a7713b1edbc | 1057 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1058 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1059 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1060 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1061 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1062 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1063 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1064 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1065 | * @arg TIM_FLAG_BREAK: Break interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1066 | * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1067 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1068 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1069 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1070 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1071 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
AnnaBridge | 171:3a7713b1edbc | 1072 | */ |
AnnaBridge | 171:3a7713b1edbc | 1073 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
AnnaBridge | 171:3a7713b1edbc | 1074 | |
AnnaBridge | 171:3a7713b1edbc | 1075 | /** |
AnnaBridge | 171:3a7713b1edbc | 1076 | * @brief Check whether the specified TIM interrupt source is enabled or not. |
AnnaBridge | 171:3a7713b1edbc | 1077 | * @param __HANDLE__: TIM handle |
AnnaBridge | 171:3a7713b1edbc | 1078 | * @param __INTERRUPT__: specifies the TIM interrupt source to check. |
AnnaBridge | 171:3a7713b1edbc | 1079 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1080 | * @arg TIM_IT_UPDATE: Update interrupt |
AnnaBridge | 171:3a7713b1edbc | 1081 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1082 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1083 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1084 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1085 | * @arg TIM_IT_COM: Commutation interrupt |
AnnaBridge | 171:3a7713b1edbc | 1086 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
AnnaBridge | 171:3a7713b1edbc | 1087 | * @arg TIM_IT_BREAK: Break interrupt |
AnnaBridge | 171:3a7713b1edbc | 1088 | * @retval The state of TIM_IT (SET or RESET). |
AnnaBridge | 171:3a7713b1edbc | 1089 | */ |
AnnaBridge | 171:3a7713b1edbc | 1090 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
AnnaBridge | 171:3a7713b1edbc | 1091 | |
AnnaBridge | 171:3a7713b1edbc | 1092 | /** @brief Clear the TIM interrupt pending bits. |
AnnaBridge | 171:3a7713b1edbc | 1093 | * @param __HANDLE__: TIM handle |
AnnaBridge | 171:3a7713b1edbc | 1094 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
AnnaBridge | 171:3a7713b1edbc | 1095 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1096 | * @arg TIM_IT_UPDATE: Update interrupt |
AnnaBridge | 171:3a7713b1edbc | 1097 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1098 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1099 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1100 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1101 | * @arg TIM_IT_COM: Commutation interrupt |
AnnaBridge | 171:3a7713b1edbc | 1102 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
AnnaBridge | 171:3a7713b1edbc | 1103 | * @arg TIM_IT_BREAK: Break interrupt |
AnnaBridge | 171:3a7713b1edbc | 1104 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1105 | */ |
AnnaBridge | 171:3a7713b1edbc | 1106 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) |
AnnaBridge | 171:3a7713b1edbc | 1107 | |
AnnaBridge | 171:3a7713b1edbc | 1108 | /** |
AnnaBridge | 171:3a7713b1edbc | 1109 | * @brief Indicates whether or not the TIM Counter is used as downcounter. |
AnnaBridge | 171:3a7713b1edbc | 1110 | * @param __HANDLE__: TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1111 | * @retval False (Counter used as upcounter) or True (Counter used as downcounter) |
AnnaBridge | 171:3a7713b1edbc | 1112 | * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder |
AnnaBridge | 171:3a7713b1edbc | 1113 | mode. |
AnnaBridge | 171:3a7713b1edbc | 1114 | */ |
AnnaBridge | 171:3a7713b1edbc | 1115 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
AnnaBridge | 171:3a7713b1edbc | 1116 | |
AnnaBridge | 171:3a7713b1edbc | 1117 | /** |
AnnaBridge | 171:3a7713b1edbc | 1118 | * @brief Set the TIM Prescaler on runtime. |
AnnaBridge | 171:3a7713b1edbc | 1119 | * @param __HANDLE__: TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1120 | * @param __PRESC__: specifies the Prescaler new value. |
AnnaBridge | 171:3a7713b1edbc | 1121 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1122 | */ |
AnnaBridge | 171:3a7713b1edbc | 1123 | #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) |
AnnaBridge | 171:3a7713b1edbc | 1124 | |
AnnaBridge | 171:3a7713b1edbc | 1125 | /** |
AnnaBridge | 171:3a7713b1edbc | 1126 | * @brief Set the TIM Counter Register value on runtime. |
AnnaBridge | 171:3a7713b1edbc | 1127 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1128 | * @param __COUNTER__ specifies the Counter register new value. |
AnnaBridge | 171:3a7713b1edbc | 1129 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1130 | */ |
AnnaBridge | 171:3a7713b1edbc | 1131 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
AnnaBridge | 171:3a7713b1edbc | 1132 | |
AnnaBridge | 171:3a7713b1edbc | 1133 | /** |
AnnaBridge | 171:3a7713b1edbc | 1134 | * @brief Get the TIM Counter Register value on runtime. |
AnnaBridge | 171:3a7713b1edbc | 1135 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1136 | * @retval 16-bit or 32-bit value of the timer counter register |
AnnaBridge | 171:3a7713b1edbc | 1137 | */ |
AnnaBridge | 171:3a7713b1edbc | 1138 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) |
AnnaBridge | 171:3a7713b1edbc | 1139 | |
AnnaBridge | 171:3a7713b1edbc | 1140 | /** |
AnnaBridge | 171:3a7713b1edbc | 1141 | * @brief Set the TIM Autoreload Register value on runtime without calling |
AnnaBridge | 171:3a7713b1edbc | 1142 | * another time any Init function. |
AnnaBridge | 171:3a7713b1edbc | 1143 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1144 | * @param __AUTORELOAD__ specifies the Counter register new value. |
AnnaBridge | 171:3a7713b1edbc | 1145 | * @retval 16-bit or 32-bit value of the timer auto-reload |
AnnaBridge | 171:3a7713b1edbc | 1146 | */ |
AnnaBridge | 171:3a7713b1edbc | 1147 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ |
AnnaBridge | 171:3a7713b1edbc | 1148 | do{ \ |
AnnaBridge | 171:3a7713b1edbc | 1149 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
AnnaBridge | 171:3a7713b1edbc | 1150 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
AnnaBridge | 171:3a7713b1edbc | 1151 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1152 | /** |
AnnaBridge | 171:3a7713b1edbc | 1153 | * @brief Get the TIM Autoreload Register value on runtime |
AnnaBridge | 171:3a7713b1edbc | 1154 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1155 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1156 | */ |
AnnaBridge | 171:3a7713b1edbc | 1157 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) |
AnnaBridge | 171:3a7713b1edbc | 1158 | |
AnnaBridge | 171:3a7713b1edbc | 1159 | /** |
AnnaBridge | 171:3a7713b1edbc | 1160 | * @brief Set the TIM Clock Division value on runtime without calling |
AnnaBridge | 171:3a7713b1edbc | 1161 | * another time any Init function. |
AnnaBridge | 171:3a7713b1edbc | 1162 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1163 | * @param __CKD__ specifies the clock division value. |
AnnaBridge | 171:3a7713b1edbc | 1164 | * This parameter can be one of the following value: |
AnnaBridge | 171:3a7713b1edbc | 1165 | * @arg TIM_CLOCKDIVISION_DIV1 |
AnnaBridge | 171:3a7713b1edbc | 1166 | * @arg TIM_CLOCKDIVISION_DIV2 |
AnnaBridge | 171:3a7713b1edbc | 1167 | * @arg TIM_CLOCKDIVISION_DIV4 |
AnnaBridge | 171:3a7713b1edbc | 1168 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1169 | */ |
AnnaBridge | 171:3a7713b1edbc | 1170 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ |
AnnaBridge | 171:3a7713b1edbc | 1171 | do{ \ |
AnnaBridge | 171:3a7713b1edbc | 1172 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ |
AnnaBridge | 171:3a7713b1edbc | 1173 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
AnnaBridge | 171:3a7713b1edbc | 1174 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
AnnaBridge | 171:3a7713b1edbc | 1175 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1176 | /** |
AnnaBridge | 171:3a7713b1edbc | 1177 | * @brief Get the TIM Clock Division value on runtime |
AnnaBridge | 171:3a7713b1edbc | 1178 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1179 | * @retval The clock division can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1180 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
AnnaBridge | 171:3a7713b1edbc | 1181 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
AnnaBridge | 171:3a7713b1edbc | 1182 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
AnnaBridge | 171:3a7713b1edbc | 1183 | */ |
AnnaBridge | 171:3a7713b1edbc | 1184 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
AnnaBridge | 171:3a7713b1edbc | 1185 | |
AnnaBridge | 171:3a7713b1edbc | 1186 | /** |
AnnaBridge | 171:3a7713b1edbc | 1187 | * @brief Set the TIM Input Capture prescaler on runtime without calling |
AnnaBridge | 171:3a7713b1edbc | 1188 | * another time HAL_TIM_IC_ConfigChannel() function. |
AnnaBridge | 171:3a7713b1edbc | 1189 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1190 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 171:3a7713b1edbc | 1191 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1192 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 171:3a7713b1edbc | 1193 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 171:3a7713b1edbc | 1194 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 171:3a7713b1edbc | 1195 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 171:3a7713b1edbc | 1196 | * @param __ICPSC__ specifies the Input Capture4 prescaler new value. |
AnnaBridge | 171:3a7713b1edbc | 1197 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1198 | * @arg TIM_ICPSC_DIV1: no prescaler |
AnnaBridge | 171:3a7713b1edbc | 1199 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
AnnaBridge | 171:3a7713b1edbc | 1200 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
AnnaBridge | 171:3a7713b1edbc | 1201 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
AnnaBridge | 171:3a7713b1edbc | 1202 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1203 | */ |
AnnaBridge | 171:3a7713b1edbc | 1204 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
AnnaBridge | 171:3a7713b1edbc | 1205 | do{ \ |
AnnaBridge | 171:3a7713b1edbc | 1206 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ |
AnnaBridge | 171:3a7713b1edbc | 1207 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
AnnaBridge | 171:3a7713b1edbc | 1208 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1209 | |
AnnaBridge | 171:3a7713b1edbc | 1210 | /** |
AnnaBridge | 171:3a7713b1edbc | 1211 | * @brief Get the TIM Input Capture prescaler on runtime |
AnnaBridge | 171:3a7713b1edbc | 1212 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1213 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 171:3a7713b1edbc | 1214 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1215 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
AnnaBridge | 171:3a7713b1edbc | 1216 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
AnnaBridge | 171:3a7713b1edbc | 1217 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
AnnaBridge | 171:3a7713b1edbc | 1218 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
AnnaBridge | 171:3a7713b1edbc | 1219 | * @retval The input capture prescaler can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1220 | * @arg TIM_ICPSC_DIV1: no prescaler |
AnnaBridge | 171:3a7713b1edbc | 1221 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
AnnaBridge | 171:3a7713b1edbc | 1222 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
AnnaBridge | 171:3a7713b1edbc | 1223 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
AnnaBridge | 171:3a7713b1edbc | 1224 | */ |
AnnaBridge | 171:3a7713b1edbc | 1225 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 1226 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
AnnaBridge | 171:3a7713b1edbc | 1227 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ |
AnnaBridge | 171:3a7713b1edbc | 1228 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
AnnaBridge | 171:3a7713b1edbc | 1229 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) |
AnnaBridge | 171:3a7713b1edbc | 1230 | |
AnnaBridge | 171:3a7713b1edbc | 1231 | /** |
AnnaBridge | 171:3a7713b1edbc | 1232 | * @brief Set the TIM Capture x input polarity on runtime. |
AnnaBridge | 171:3a7713b1edbc | 1233 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1234 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 171:3a7713b1edbc | 1235 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1236 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 171:3a7713b1edbc | 1237 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 171:3a7713b1edbc | 1238 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 171:3a7713b1edbc | 1239 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 171:3a7713b1edbc | 1240 | * @param __POLARITY__ Polarity for TIx source |
AnnaBridge | 171:3a7713b1edbc | 1241 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge |
AnnaBridge | 171:3a7713b1edbc | 1242 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge |
AnnaBridge | 171:3a7713b1edbc | 1243 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge |
AnnaBridge | 171:3a7713b1edbc | 1244 | * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. |
AnnaBridge | 171:3a7713b1edbc | 1245 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1246 | */ |
AnnaBridge | 171:3a7713b1edbc | 1247 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
AnnaBridge | 171:3a7713b1edbc | 1248 | do{ \ |
AnnaBridge | 171:3a7713b1edbc | 1249 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ |
AnnaBridge | 171:3a7713b1edbc | 1250 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ |
AnnaBridge | 171:3a7713b1edbc | 1251 | }while(0) |
AnnaBridge | 171:3a7713b1edbc | 1252 | |
AnnaBridge | 171:3a7713b1edbc | 1253 | /** |
AnnaBridge | 171:3a7713b1edbc | 1254 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1255 | */ |
AnnaBridge | 171:3a7713b1edbc | 1256 | /* End of exported macros ----------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1257 | |
AnnaBridge | 171:3a7713b1edbc | 1258 | /* Include TIM HAL Extension module */ |
AnnaBridge | 171:3a7713b1edbc | 1259 | #include "stm32f7xx_hal_tim_ex.h" |
AnnaBridge | 171:3a7713b1edbc | 1260 | |
AnnaBridge | 171:3a7713b1edbc | 1261 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1262 | /** @addtogroup TIM_Exported_Functions |
AnnaBridge | 171:3a7713b1edbc | 1263 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1264 | */ |
AnnaBridge | 171:3a7713b1edbc | 1265 | |
AnnaBridge | 171:3a7713b1edbc | 1266 | /** @addtogroup TIM_Exported_Functions_Group1 |
AnnaBridge | 171:3a7713b1edbc | 1267 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1268 | */ |
AnnaBridge | 171:3a7713b1edbc | 1269 | |
AnnaBridge | 171:3a7713b1edbc | 1270 | /* Time Base functions ********************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1271 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1272 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1273 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1274 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1275 | /* Blocking mode: Polling */ |
AnnaBridge | 171:3a7713b1edbc | 1276 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1277 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1278 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 1279 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1280 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1281 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 171:3a7713b1edbc | 1282 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
AnnaBridge | 171:3a7713b1edbc | 1283 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1284 | /** |
AnnaBridge | 171:3a7713b1edbc | 1285 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1286 | */ |
AnnaBridge | 171:3a7713b1edbc | 1287 | |
AnnaBridge | 171:3a7713b1edbc | 1288 | /** @addtogroup TIM_Exported_Functions_Group2 |
AnnaBridge | 171:3a7713b1edbc | 1289 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1290 | */ |
AnnaBridge | 171:3a7713b1edbc | 1291 | /* Timer Output Compare functions **********************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1292 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1293 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1294 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1295 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1296 | /* Blocking mode: Polling */ |
AnnaBridge | 171:3a7713b1edbc | 1297 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1298 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1299 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 1300 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1301 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1302 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 171:3a7713b1edbc | 1303 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 171:3a7713b1edbc | 1304 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1305 | |
AnnaBridge | 171:3a7713b1edbc | 1306 | /** |
AnnaBridge | 171:3a7713b1edbc | 1307 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1308 | */ |
AnnaBridge | 171:3a7713b1edbc | 1309 | |
AnnaBridge | 171:3a7713b1edbc | 1310 | /** @addtogroup TIM_Exported_Functions_Group3 |
AnnaBridge | 171:3a7713b1edbc | 1311 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1312 | */ |
AnnaBridge | 171:3a7713b1edbc | 1313 | /* Timer PWM functions *********************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1314 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1315 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1316 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1317 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1318 | |
AnnaBridge | 171:3a7713b1edbc | 1319 | /* Blocking mode: Polling */ |
AnnaBridge | 171:3a7713b1edbc | 1320 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1321 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1322 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 1323 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1324 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1325 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 171:3a7713b1edbc | 1326 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 171:3a7713b1edbc | 1327 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1328 | |
AnnaBridge | 171:3a7713b1edbc | 1329 | /** |
AnnaBridge | 171:3a7713b1edbc | 1330 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1331 | */ |
AnnaBridge | 171:3a7713b1edbc | 1332 | |
AnnaBridge | 171:3a7713b1edbc | 1333 | /** @addtogroup TIM_Exported_Functions_Group4 |
AnnaBridge | 171:3a7713b1edbc | 1334 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1335 | */ |
AnnaBridge | 171:3a7713b1edbc | 1336 | /* Timer Input Capture functions ***********************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1337 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1338 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1339 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1340 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1341 | /* Blocking mode: Polling */ |
AnnaBridge | 171:3a7713b1edbc | 1342 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1343 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1344 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 1345 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1346 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1347 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 171:3a7713b1edbc | 1348 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 171:3a7713b1edbc | 1349 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1350 | |
AnnaBridge | 171:3a7713b1edbc | 1351 | /** |
AnnaBridge | 171:3a7713b1edbc | 1352 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1353 | */ |
AnnaBridge | 171:3a7713b1edbc | 1354 | |
AnnaBridge | 171:3a7713b1edbc | 1355 | /** @addtogroup TIM_Exported_Functions_Group5 |
AnnaBridge | 171:3a7713b1edbc | 1356 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1357 | */ |
AnnaBridge | 171:3a7713b1edbc | 1358 | /* Timer One Pulse functions ***************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1359 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
AnnaBridge | 171:3a7713b1edbc | 1360 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1361 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1362 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1363 | /* Blocking mode: Polling */ |
AnnaBridge | 171:3a7713b1edbc | 1364 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 171:3a7713b1edbc | 1365 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 171:3a7713b1edbc | 1366 | |
AnnaBridge | 171:3a7713b1edbc | 1367 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 1368 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 171:3a7713b1edbc | 1369 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 171:3a7713b1edbc | 1370 | |
AnnaBridge | 171:3a7713b1edbc | 1371 | /** |
AnnaBridge | 171:3a7713b1edbc | 1372 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1373 | */ |
AnnaBridge | 171:3a7713b1edbc | 1374 | |
AnnaBridge | 171:3a7713b1edbc | 1375 | /** @addtogroup TIM_Exported_Functions_Group6 |
AnnaBridge | 171:3a7713b1edbc | 1376 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1377 | */ |
AnnaBridge | 171:3a7713b1edbc | 1378 | /* Timer Encoder functions *****************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1379 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); |
AnnaBridge | 171:3a7713b1edbc | 1380 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1381 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1382 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1383 | /* Blocking mode: Polling */ |
AnnaBridge | 171:3a7713b1edbc | 1384 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1385 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1386 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 1387 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1388 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1389 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 171:3a7713b1edbc | 1390 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); |
AnnaBridge | 171:3a7713b1edbc | 1391 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1392 | |
AnnaBridge | 171:3a7713b1edbc | 1393 | /** |
AnnaBridge | 171:3a7713b1edbc | 1394 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1395 | */ |
AnnaBridge | 171:3a7713b1edbc | 1396 | |
AnnaBridge | 171:3a7713b1edbc | 1397 | /** @addtogroup TIM_Exported_Functions_Group7 |
AnnaBridge | 171:3a7713b1edbc | 1398 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1399 | */ |
AnnaBridge | 171:3a7713b1edbc | 1400 | /* Interrupt Handler functions **********************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1401 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1402 | |
AnnaBridge | 171:3a7713b1edbc | 1403 | /** |
AnnaBridge | 171:3a7713b1edbc | 1404 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1405 | */ |
AnnaBridge | 171:3a7713b1edbc | 1406 | |
AnnaBridge | 171:3a7713b1edbc | 1407 | /** @addtogroup TIM_Exported_Functions_Group8 |
AnnaBridge | 171:3a7713b1edbc | 1408 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1409 | */ |
AnnaBridge | 171:3a7713b1edbc | 1410 | /* Control functions *********************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1411 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1412 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1413 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1414 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); |
AnnaBridge | 171:3a7713b1edbc | 1415 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1416 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); |
AnnaBridge | 171:3a7713b1edbc | 1417 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
AnnaBridge | 171:3a7713b1edbc | 1418 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
AnnaBridge | 171:3a7713b1edbc | 1419 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
AnnaBridge | 171:3a7713b1edbc | 1420 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 171:3a7713b1edbc | 1421 | uint32_t *BurstBuffer, uint32_t BurstLength); |
AnnaBridge | 171:3a7713b1edbc | 1422 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
AnnaBridge | 171:3a7713b1edbc | 1423 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 171:3a7713b1edbc | 1424 | uint32_t *BurstBuffer, uint32_t BurstLength); |
AnnaBridge | 171:3a7713b1edbc | 1425 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
AnnaBridge | 171:3a7713b1edbc | 1426 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
AnnaBridge | 171:3a7713b1edbc | 1427 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1428 | |
AnnaBridge | 171:3a7713b1edbc | 1429 | /** |
AnnaBridge | 171:3a7713b1edbc | 1430 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1431 | */ |
AnnaBridge | 171:3a7713b1edbc | 1432 | |
AnnaBridge | 171:3a7713b1edbc | 1433 | /** @addtogroup TIM_Exported_Functions_Group9 |
AnnaBridge | 171:3a7713b1edbc | 1434 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1435 | */ |
AnnaBridge | 171:3a7713b1edbc | 1436 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
AnnaBridge | 171:3a7713b1edbc | 1437 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1438 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1439 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1440 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1441 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1442 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1443 | |
AnnaBridge | 171:3a7713b1edbc | 1444 | /* Callbacks Register/UnRegister functions ***********************************/ |
AnnaBridge | 171:3a7713b1edbc | 1445 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
AnnaBridge | 171:3a7713b1edbc | 1446 | HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); |
AnnaBridge | 171:3a7713b1edbc | 1447 | HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); |
AnnaBridge | 171:3a7713b1edbc | 1448 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
AnnaBridge | 171:3a7713b1edbc | 1449 | |
AnnaBridge | 171:3a7713b1edbc | 1450 | /** |
AnnaBridge | 171:3a7713b1edbc | 1451 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1452 | */ |
AnnaBridge | 171:3a7713b1edbc | 1453 | |
AnnaBridge | 171:3a7713b1edbc | 1454 | /** @addtogroup TIM_Exported_Functions_Group10 |
AnnaBridge | 171:3a7713b1edbc | 1455 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1456 | */ |
AnnaBridge | 171:3a7713b1edbc | 1457 | /* Peripheral State functions **************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1458 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1459 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1460 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1461 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1462 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1463 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1464 | |
AnnaBridge | 171:3a7713b1edbc | 1465 | /** |
AnnaBridge | 171:3a7713b1edbc | 1466 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1467 | */ |
AnnaBridge | 171:3a7713b1edbc | 1468 | |
AnnaBridge | 171:3a7713b1edbc | 1469 | /** |
AnnaBridge | 171:3a7713b1edbc | 1470 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1471 | */ |
AnnaBridge | 171:3a7713b1edbc | 1472 | |
AnnaBridge | 171:3a7713b1edbc | 1473 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1474 | /** @defgroup TIM_Private_Constants TIM Private Constants |
AnnaBridge | 171:3a7713b1edbc | 1475 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1476 | */ |
AnnaBridge | 171:3a7713b1edbc | 1477 | /* The counter of a timer instance is disabled only if all the CCx and CCxN |
AnnaBridge | 171:3a7713b1edbc | 1478 | channels have been disabled */ |
AnnaBridge | 171:3a7713b1edbc | 1479 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
AnnaBridge | 171:3a7713b1edbc | 1480 | #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) |
AnnaBridge | 171:3a7713b1edbc | 1481 | /** |
AnnaBridge | 171:3a7713b1edbc | 1482 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1483 | */ |
AnnaBridge | 171:3a7713b1edbc | 1484 | /* End of private constants --------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1485 | |
AnnaBridge | 171:3a7713b1edbc | 1486 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1487 | /** @defgroup TIM_Private_Macros TIM Private Macros |
AnnaBridge | 171:3a7713b1edbc | 1488 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1489 | */ |
AnnaBridge | 171:3a7713b1edbc | 1490 | |
AnnaBridge | 171:3a7713b1edbc | 1491 | /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters |
AnnaBridge | 171:3a7713b1edbc | 1492 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1493 | */ |
AnnaBridge | 171:3a7713b1edbc | 1494 | #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ |
AnnaBridge | 171:3a7713b1edbc | 1495 | ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ |
AnnaBridge | 171:3a7713b1edbc | 1496 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1497 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1498 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) |
AnnaBridge | 171:3a7713b1edbc | 1499 | |
AnnaBridge | 171:3a7713b1edbc | 1500 | #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1501 | ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1502 | ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) |
AnnaBridge | 171:3a7713b1edbc | 1503 | |
AnnaBridge | 171:3a7713b1edbc | 1504 | #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1505 | ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) |
AnnaBridge | 171:3a7713b1edbc | 1506 | |
AnnaBridge | 171:3a7713b1edbc | 1507 | #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1508 | ((__STATE__) == TIM_OCFAST_ENABLE)) |
AnnaBridge | 171:3a7713b1edbc | 1509 | |
AnnaBridge | 171:3a7713b1edbc | 1510 | #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1511 | ((STATE) == TIM_OUTPUTSTATE_ENABLE)) |
AnnaBridge | 171:3a7713b1edbc | 1512 | |
AnnaBridge | 171:3a7713b1edbc | 1513 | #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1514 | ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) |
AnnaBridge | 171:3a7713b1edbc | 1515 | |
AnnaBridge | 171:3a7713b1edbc | 1516 | #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ |
AnnaBridge | 171:3a7713b1edbc | 1517 | ((__POLARITY__) == TIM_OCPOLARITY_LOW)) |
AnnaBridge | 171:3a7713b1edbc | 1518 | |
AnnaBridge | 171:3a7713b1edbc | 1519 | #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ |
AnnaBridge | 171:3a7713b1edbc | 1520 | ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) |
AnnaBridge | 171:3a7713b1edbc | 1521 | |
AnnaBridge | 171:3a7713b1edbc | 1522 | #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ |
AnnaBridge | 171:3a7713b1edbc | 1523 | ((__STATE__) == TIM_OCIDLESTATE_RESET)) |
AnnaBridge | 171:3a7713b1edbc | 1524 | |
AnnaBridge | 171:3a7713b1edbc | 1525 | #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ |
AnnaBridge | 171:3a7713b1edbc | 1526 | ((__STATE__) == TIM_OCNIDLESTATE_RESET)) |
AnnaBridge | 171:3a7713b1edbc | 1527 | |
AnnaBridge | 171:3a7713b1edbc | 1528 | #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ |
AnnaBridge | 171:3a7713b1edbc | 1529 | ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ |
AnnaBridge | 171:3a7713b1edbc | 1530 | ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) |
AnnaBridge | 171:3a7713b1edbc | 1531 | |
AnnaBridge | 171:3a7713b1edbc | 1532 | #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ |
AnnaBridge | 171:3a7713b1edbc | 1533 | ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ |
AnnaBridge | 171:3a7713b1edbc | 1534 | ((__SELECTION__) == TIM_ICSELECTION_TRC)) |
AnnaBridge | 171:3a7713b1edbc | 1535 | |
AnnaBridge | 171:3a7713b1edbc | 1536 | #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1537 | ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1538 | ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ |
AnnaBridge | 171:3a7713b1edbc | 1539 | ((__PRESCALER__) == TIM_ICPSC_DIV8)) |
AnnaBridge | 171:3a7713b1edbc | 1540 | |
AnnaBridge | 171:3a7713b1edbc | 1541 | #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1542 | ((__MODE__) == TIM_OPMODE_REPETITIVE)) |
AnnaBridge | 171:3a7713b1edbc | 1543 | |
AnnaBridge | 171:3a7713b1edbc | 1544 | #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1545 | ((__MODE__) == TIM_ENCODERMODE_TI2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1546 | ((__MODE__) == TIM_ENCODERMODE_TI12)) |
AnnaBridge | 171:3a7713b1edbc | 1547 | |
AnnaBridge | 171:3a7713b1edbc | 1548 | #define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00U) == 0x00000000U) && ((__IT__) != 0x00000000U)) |
AnnaBridge | 171:3a7713b1edbc | 1549 | |
AnnaBridge | 171:3a7713b1edbc | 1550 | |
AnnaBridge | 171:3a7713b1edbc | 1551 | #define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1552 | ((__IT__) == TIM_IT_CC1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1553 | ((__IT__) == TIM_IT_CC2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1554 | ((__IT__) == TIM_IT_CC3) || \ |
AnnaBridge | 171:3a7713b1edbc | 1555 | ((__IT__) == TIM_IT_CC4) || \ |
AnnaBridge | 171:3a7713b1edbc | 1556 | ((__IT__) == TIM_IT_COM) || \ |
AnnaBridge | 171:3a7713b1edbc | 1557 | ((__IT__) == TIM_IT_TRIGGER) || \ |
AnnaBridge | 171:3a7713b1edbc | 1558 | ((__IT__) == TIM_IT_BREAK)) |
AnnaBridge | 171:3a7713b1edbc | 1559 | |
AnnaBridge | 171:3a7713b1edbc | 1560 | #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) |
AnnaBridge | 171:3a7713b1edbc | 1561 | |
AnnaBridge | 171:3a7713b1edbc | 1562 | #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) |
AnnaBridge | 171:3a7713b1edbc | 1563 | |
AnnaBridge | 171:3a7713b1edbc | 1564 | #define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1565 | ((__FLAG__) == TIM_FLAG_CC1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1566 | ((__FLAG__) == TIM_FLAG_CC2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1567 | ((__FLAG__) == TIM_FLAG_CC3) || \ |
AnnaBridge | 171:3a7713b1edbc | 1568 | ((__FLAG__) == TIM_FLAG_CC4) || \ |
AnnaBridge | 171:3a7713b1edbc | 1569 | ((__FLAG__) == TIM_FLAG_COM) || \ |
AnnaBridge | 171:3a7713b1edbc | 1570 | ((__FLAG__) == TIM_FLAG_TRIGGER) || \ |
AnnaBridge | 171:3a7713b1edbc | 1571 | ((__FLAG__) == TIM_FLAG_BREAK) || \ |
AnnaBridge | 171:3a7713b1edbc | 1572 | ((__FLAG__) == TIM_FLAG_BREAK2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1573 | ((__FLAG__) == TIM_FLAG_CC1OF) || \ |
AnnaBridge | 171:3a7713b1edbc | 1574 | ((__FLAG__) == TIM_FLAG_CC2OF) || \ |
AnnaBridge | 171:3a7713b1edbc | 1575 | ((__FLAG__) == TIM_FLAG_CC3OF) || \ |
AnnaBridge | 171:3a7713b1edbc | 1576 | ((__FLAG__) == TIM_FLAG_CC4OF)) |
AnnaBridge | 171:3a7713b1edbc | 1577 | |
AnnaBridge | 171:3a7713b1edbc | 1578 | #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ |
AnnaBridge | 171:3a7713b1edbc | 1579 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1580 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ |
AnnaBridge | 171:3a7713b1edbc | 1581 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1582 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1583 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ |
AnnaBridge | 171:3a7713b1edbc | 1584 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ |
AnnaBridge | 171:3a7713b1edbc | 1585 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1586 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1587 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) |
AnnaBridge | 171:3a7713b1edbc | 1588 | |
AnnaBridge | 171:3a7713b1edbc | 1589 | #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ |
AnnaBridge | 171:3a7713b1edbc | 1590 | ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
AnnaBridge | 171:3a7713b1edbc | 1591 | ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ |
AnnaBridge | 171:3a7713b1edbc | 1592 | ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ |
AnnaBridge | 171:3a7713b1edbc | 1593 | ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
AnnaBridge | 171:3a7713b1edbc | 1594 | |
AnnaBridge | 171:3a7713b1edbc | 1595 | #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1596 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1597 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ |
AnnaBridge | 171:3a7713b1edbc | 1598 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) |
AnnaBridge | 171:3a7713b1edbc | 1599 | |
AnnaBridge | 171:3a7713b1edbc | 1600 | #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) |
AnnaBridge | 171:3a7713b1edbc | 1601 | |
AnnaBridge | 171:3a7713b1edbc | 1602 | #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
AnnaBridge | 171:3a7713b1edbc | 1603 | ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
AnnaBridge | 171:3a7713b1edbc | 1604 | |
AnnaBridge | 171:3a7713b1edbc | 1605 | #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1606 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1607 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
AnnaBridge | 171:3a7713b1edbc | 1608 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) |
AnnaBridge | 171:3a7713b1edbc | 1609 | |
AnnaBridge | 171:3a7713b1edbc | 1610 | #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) |
AnnaBridge | 171:3a7713b1edbc | 1611 | |
AnnaBridge | 171:3a7713b1edbc | 1612 | #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1613 | ((__STATE__) == TIM_OSSR_DISABLE)) |
AnnaBridge | 171:3a7713b1edbc | 1614 | |
AnnaBridge | 171:3a7713b1edbc | 1615 | #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1616 | ((__STATE__) == TIM_OSSI_DISABLE)) |
AnnaBridge | 171:3a7713b1edbc | 1617 | |
AnnaBridge | 171:3a7713b1edbc | 1618 | #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ |
AnnaBridge | 171:3a7713b1edbc | 1619 | ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1620 | ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1621 | ((__LEVEL__) == TIM_LOCKLEVEL_3)) |
AnnaBridge | 171:3a7713b1edbc | 1622 | |
AnnaBridge | 171:3a7713b1edbc | 1623 | #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1624 | ((__STATE__) == TIM_BREAK_DISABLE)) |
AnnaBridge | 171:3a7713b1edbc | 1625 | |
AnnaBridge | 171:3a7713b1edbc | 1626 | #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ |
AnnaBridge | 171:3a7713b1edbc | 1627 | ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) |
AnnaBridge | 171:3a7713b1edbc | 1628 | |
AnnaBridge | 171:3a7713b1edbc | 1629 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1630 | ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) |
AnnaBridge | 171:3a7713b1edbc | 1631 | |
AnnaBridge | 171:3a7713b1edbc | 1632 | #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ |
AnnaBridge | 171:3a7713b1edbc | 1633 | ((__SOURCE__) == TIM_TRGO_ENABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1634 | ((__SOURCE__) == TIM_TRGO_UPDATE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1635 | ((__SOURCE__) == TIM_TRGO_OC1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1636 | ((__SOURCE__) == TIM_TRGO_OC1REF) || \ |
AnnaBridge | 171:3a7713b1edbc | 1637 | ((__SOURCE__) == TIM_TRGO_OC2REF) || \ |
AnnaBridge | 171:3a7713b1edbc | 1638 | ((__SOURCE__) == TIM_TRGO_OC3REF) || \ |
AnnaBridge | 171:3a7713b1edbc | 1639 | ((__SOURCE__) == TIM_TRGO_OC4REF)) |
AnnaBridge | 171:3a7713b1edbc | 1640 | |
AnnaBridge | 171:3a7713b1edbc | 1641 | #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1642 | ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) |
AnnaBridge | 171:3a7713b1edbc | 1643 | |
AnnaBridge | 171:3a7713b1edbc | 1644 | #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
AnnaBridge | 171:3a7713b1edbc | 1645 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1646 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1647 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
AnnaBridge | 171:3a7713b1edbc | 1648 | ((__SELECTION__) == TIM_TS_TI1F_ED) || \ |
AnnaBridge | 171:3a7713b1edbc | 1649 | ((__SELECTION__) == TIM_TS_TI1FP1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1650 | ((__SELECTION__) == TIM_TS_TI2FP2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1651 | ((__SELECTION__) == TIM_TS_ETRF)) |
AnnaBridge | 171:3a7713b1edbc | 1652 | |
AnnaBridge | 171:3a7713b1edbc | 1653 | #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
AnnaBridge | 171:3a7713b1edbc | 1654 | ((SELECTION) == TIM_TS_ITR1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1655 | ((SELECTION) == TIM_TS_ITR2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1656 | ((SELECTION) == TIM_TS_ITR3)) |
AnnaBridge | 171:3a7713b1edbc | 1657 | |
AnnaBridge | 171:3a7713b1edbc | 1658 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
AnnaBridge | 171:3a7713b1edbc | 1659 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1660 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1661 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
AnnaBridge | 171:3a7713b1edbc | 1662 | ((__SELECTION__) == TIM_TS_NONE)) |
AnnaBridge | 171:3a7713b1edbc | 1663 | |
AnnaBridge | 171:3a7713b1edbc | 1664 | #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
AnnaBridge | 171:3a7713b1edbc | 1665 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
AnnaBridge | 171:3a7713b1edbc | 1666 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ |
AnnaBridge | 171:3a7713b1edbc | 1667 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
AnnaBridge | 171:3a7713b1edbc | 1668 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
AnnaBridge | 171:3a7713b1edbc | 1669 | |
AnnaBridge | 171:3a7713b1edbc | 1670 | #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1671 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1672 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ |
AnnaBridge | 171:3a7713b1edbc | 1673 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) |
AnnaBridge | 171:3a7713b1edbc | 1674 | |
AnnaBridge | 171:3a7713b1edbc | 1675 | #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) |
AnnaBridge | 171:3a7713b1edbc | 1676 | |
AnnaBridge | 171:3a7713b1edbc | 1677 | #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1678 | ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) |
AnnaBridge | 171:3a7713b1edbc | 1679 | |
AnnaBridge | 171:3a7713b1edbc | 1680 | #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1681 | ((__BASE__) == TIM_DMABASE_CR2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1682 | ((__BASE__) == TIM_DMABASE_SMCR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1683 | ((__BASE__) == TIM_DMABASE_DIER) || \ |
AnnaBridge | 171:3a7713b1edbc | 1684 | ((__BASE__) == TIM_DMABASE_SR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1685 | ((__BASE__) == TIM_DMABASE_EGR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1686 | ((__BASE__) == TIM_DMABASE_CCMR1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1687 | ((__BASE__) == TIM_DMABASE_CCMR2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1688 | ((__BASE__) == TIM_DMABASE_CCER) || \ |
AnnaBridge | 171:3a7713b1edbc | 1689 | ((__BASE__) == TIM_DMABASE_CNT) || \ |
AnnaBridge | 171:3a7713b1edbc | 1690 | ((__BASE__) == TIM_DMABASE_PSC) || \ |
AnnaBridge | 171:3a7713b1edbc | 1691 | ((__BASE__) == TIM_DMABASE_ARR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1692 | ((__BASE__) == TIM_DMABASE_RCR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1693 | ((__BASE__) == TIM_DMABASE_CCR1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1694 | ((__BASE__) == TIM_DMABASE_CCR2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1695 | ((__BASE__) == TIM_DMABASE_CCR3) || \ |
AnnaBridge | 171:3a7713b1edbc | 1696 | ((__BASE__) == TIM_DMABASE_CCR4) || \ |
AnnaBridge | 171:3a7713b1edbc | 1697 | ((__BASE__) == TIM_DMABASE_BDTR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1698 | ((__BASE__) == TIM_DMABASE_DCR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1699 | ((__BASE__) == TIM_DMABASE_OR)) |
AnnaBridge | 171:3a7713b1edbc | 1700 | |
AnnaBridge | 171:3a7713b1edbc | 1701 | #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
AnnaBridge | 171:3a7713b1edbc | 1702 | ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1703 | ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1704 | ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1705 | ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1706 | ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1707 | ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1708 | ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1709 | ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1710 | ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1711 | ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1712 | ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1713 | ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1714 | ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1715 | ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1716 | ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1717 | ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1718 | ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) |
AnnaBridge | 171:3a7713b1edbc | 1719 | |
AnnaBridge | 171:3a7713b1edbc | 1720 | #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
AnnaBridge | 171:3a7713b1edbc | 1721 | /** |
AnnaBridge | 171:3a7713b1edbc | 1722 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1723 | */ |
AnnaBridge | 171:3a7713b1edbc | 1724 | |
AnnaBridge | 171:3a7713b1edbc | 1725 | /** @defgroup TIM_ICPRESCALER TIM Private macros to SET/RESET TIM Input capture value |
AnnaBridge | 171:3a7713b1edbc | 1726 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1727 | */ |
AnnaBridge | 171:3a7713b1edbc | 1728 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
AnnaBridge | 171:3a7713b1edbc | 1729 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1730 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1731 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1732 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) |
AnnaBridge | 171:3a7713b1edbc | 1733 | |
AnnaBridge | 171:3a7713b1edbc | 1734 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 1735 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ |
AnnaBridge | 171:3a7713b1edbc | 1736 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ |
AnnaBridge | 171:3a7713b1edbc | 1737 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ |
AnnaBridge | 171:3a7713b1edbc | 1738 | ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) |
AnnaBridge | 171:3a7713b1edbc | 1739 | /** |
AnnaBridge | 171:3a7713b1edbc | 1740 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1741 | */ |
AnnaBridge | 171:3a7713b1edbc | 1742 | |
AnnaBridge | 171:3a7713b1edbc | 1743 | /** @defgroup TIM_CAPTUREPOLARITY TIM Private macros to SET/RESET TIM capture polarity value |
AnnaBridge | 171:3a7713b1edbc | 1744 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1745 | */ |
AnnaBridge | 171:3a7713b1edbc | 1746 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
AnnaBridge | 171:3a7713b1edbc | 1747 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1748 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1749 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1750 | ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) |
AnnaBridge | 171:3a7713b1edbc | 1751 | |
AnnaBridge | 171:3a7713b1edbc | 1752 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 1753 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1754 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1755 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1756 | ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) |
AnnaBridge | 171:3a7713b1edbc | 1757 | /** |
AnnaBridge | 171:3a7713b1edbc | 1758 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1759 | */ |
AnnaBridge | 171:3a7713b1edbc | 1760 | |
AnnaBridge | 171:3a7713b1edbc | 1761 | /** |
AnnaBridge | 171:3a7713b1edbc | 1762 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1763 | */ |
AnnaBridge | 171:3a7713b1edbc | 1764 | /* End of private macros -----------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1765 | |
AnnaBridge | 171:3a7713b1edbc | 1766 | /* Private functions ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1767 | /** @defgroup TIM_Private_Functions TIM Private Functions |
AnnaBridge | 171:3a7713b1edbc | 1768 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1769 | */ |
AnnaBridge | 171:3a7713b1edbc | 1770 | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); |
AnnaBridge | 171:3a7713b1edbc | 1771 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); |
AnnaBridge | 171:3a7713b1edbc | 1772 | void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
AnnaBridge | 171:3a7713b1edbc | 1773 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
AnnaBridge | 171:3a7713b1edbc | 1774 | void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
AnnaBridge | 171:3a7713b1edbc | 1775 | void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
AnnaBridge | 171:3a7713b1edbc | 1776 | void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); |
AnnaBridge | 171:3a7713b1edbc | 1777 | |
AnnaBridge | 171:3a7713b1edbc | 1778 | void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
AnnaBridge | 171:3a7713b1edbc | 1779 | void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma); |
AnnaBridge | 171:3a7713b1edbc | 1780 | void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
AnnaBridge | 171:3a7713b1edbc | 1781 | void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); |
AnnaBridge | 171:3a7713b1edbc | 1782 | |
AnnaBridge | 171:3a7713b1edbc | 1783 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
AnnaBridge | 171:3a7713b1edbc | 1784 | void TIM_ResetCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1785 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
AnnaBridge | 171:3a7713b1edbc | 1786 | |
AnnaBridge | 171:3a7713b1edbc | 1787 | /** |
AnnaBridge | 171:3a7713b1edbc | 1788 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1789 | */ |
AnnaBridge | 171:3a7713b1edbc | 1790 | /* End of private functions --------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1791 | |
AnnaBridge | 171:3a7713b1edbc | 1792 | /** |
AnnaBridge | 171:3a7713b1edbc | 1793 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1794 | */ |
AnnaBridge | 171:3a7713b1edbc | 1795 | |
AnnaBridge | 171:3a7713b1edbc | 1796 | /** |
AnnaBridge | 171:3a7713b1edbc | 1797 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1798 | */ |
AnnaBridge | 171:3a7713b1edbc | 1799 | |
AnnaBridge | 171:3a7713b1edbc | 1800 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 1801 | } |
AnnaBridge | 171:3a7713b1edbc | 1802 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1803 | |
AnnaBridge | 171:3a7713b1edbc | 1804 | #endif /* __STM32F7xx_HAL_TIM_H */ |
AnnaBridge | 171:3a7713b1edbc | 1805 | |
AnnaBridge | 171:3a7713b1edbc | 1806 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |